projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cnic: Convert ctx_flags to bit fields
[deliverable/linux.git] / drivers / net / cnic.c
CommitLineData
a4636960
MC		 1/* cnic.c: Broadcom CNIC core network driver.
2 *
1d9cfc4e 3 * Copyright (c) 2006-2010 Broadcom Corporation
a4636960
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
ddf79b20
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
a4636960
MC		 15#include <linux/module.h>
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/list.h>
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/netdevice.h>
24#include <linux/uio_driver.h>
25#include <linux/in.h>
26#include <linux/dma-mapping.h>
27#include <linux/delay.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31#define BCM_VLAN 1
32#endif
33#include <net/ip.h>
34#include <net/tcp.h>
35#include <net/route.h>
36#include <net/ipv6.h>
37#include <net/ip6_route.h>
c05e85a0 38#include <net/ip6_checksum.h>
a4636960
MC		 39#include <scsi/iscsi_if.h>
40
41#include "cnic_if.h"
42#include "bnx2.h"
5d1e859c
DK		 43#include "bnx2x/bnx2x_reg.h"
44#include "bnx2x/bnx2x_fw_defs.h"
45#include "bnx2x/bnx2x_hsi.h"
e2513065
MC		 46#include "../scsi/bnx2i/57xx_iscsi_constants.h"
47#include "../scsi/bnx2i/57xx_iscsi_hsi.h"
a4636960
MC		 48#include "cnic.h"
49#include "cnic_defs.h"
50
51#define DRV_MODULE_NAME "cnic"
a4636960
MC		 52
53static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59MODULE_LICENSE("GPL");
60MODULE_VERSION(CNIC_MODULE_VERSION);
61
62static LIST_HEAD(cnic_dev_list);
63static DEFINE_RWLOCK(cnic_dev_lock);
64static DEFINE_MUTEX(cnic_lock);
65
66static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
67
68static int cnic_service_bnx2(void *, void *);
71034ba8 69static int cnic_service_bnx2x(void *, void *);
a4636960
MC		 70static int cnic_ctl(void *, struct cnic_ctl_info *);
71
72static struct cnic_ops cnic_bnx2_ops = {
73 .cnic_owner = THIS_MODULE,
74 .cnic_handler = cnic_service_bnx2,
75 .cnic_ctl = cnic_ctl,
76};
77
71034ba8
MC		 78static struct cnic_ops cnic_bnx2x_ops = {
79 .cnic_owner = THIS_MODULE,
80 .cnic_handler = cnic_service_bnx2x,
81 .cnic_ctl = cnic_ctl,
82};
83
86b53606
MC		 84static void cnic_shutdown_rings(struct cnic_dev *);
85static void cnic_init_rings(struct cnic_dev *);
a4636960
MC		 86static int cnic_cm_set_pg(struct cnic_sock *);
87
88static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
89{
90 struct cnic_dev *dev = uinfo->priv;
91 struct cnic_local *cp = dev->cnic_priv;
92
93 if (!capable(CAP_NET_ADMIN))
94 return -EPERM;
95
96 if (cp->uio_dev != -1)
97 return -EBUSY;
98
86b53606
MC		 99 rtnl_lock();
100 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
101 rtnl_unlock();
102 return -ENODEV;
103 }
104
a4636960
MC		 105 cp->uio_dev = iminor(inode);
106
86b53606
MC		 107 cnic_init_rings(dev);
108 rtnl_unlock();
a4636960
MC		 109
110 return 0;
111}
112
113static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
114{
115 struct cnic_dev *dev = uinfo->priv;
116 struct cnic_local *cp = dev->cnic_priv;
117
86b53606 118 cnic_shutdown_rings(dev);
6ef57a0e 119
a4636960
MC		 120 cp->uio_dev = -1;
121 return 0;
122}
123
124static inline void cnic_hold(struct cnic_dev *dev)
125{
126 atomic_inc(&dev->ref_count);
127}
128
129static inline void cnic_put(struct cnic_dev *dev)
130{
131 atomic_dec(&dev->ref_count);
132}
133
134static inline void csk_hold(struct cnic_sock *csk)
135{
136 atomic_inc(&csk->ref_count);
137}
138
139static inline void csk_put(struct cnic_sock *csk)
140{
141 atomic_dec(&csk->ref_count);
142}
143
144static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
145{
146 struct cnic_dev *cdev;
147
148 read_lock(&cnic_dev_lock);
149 list_for_each_entry(cdev, &cnic_dev_list, list) {
150 if (netdev == cdev->netdev) {
151 cnic_hold(cdev);
152 read_unlock(&cnic_dev_lock);
153 return cdev;
154 }
155 }
156 read_unlock(&cnic_dev_lock);
157 return NULL;
158}
159
7fc1ece4
MC		 160static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
161{
162 atomic_inc(&ulp_ops->ref_count);
163}
164
165static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
166{
167 atomic_dec(&ulp_ops->ref_count);
168}
169
a4636960
MC		 170static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
171{
172 struct cnic_local *cp = dev->cnic_priv;
173 struct cnic_eth_dev *ethdev = cp->ethdev;
174 struct drv_ctl_info info;
175 struct drv_ctl_io *io = &info.data.io;
176
177 info.cmd = DRV_CTL_CTX_WR_CMD;
178 io->cid_addr = cid_addr;
179 io->offset = off;
180 io->data = val;
181 ethdev->drv_ctl(dev->netdev, &info);
182}
183
71034ba8
MC		 184static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
185{
186 struct cnic_local *cp = dev->cnic_priv;
187 struct cnic_eth_dev *ethdev = cp->ethdev;
188 struct drv_ctl_info info;
189 struct drv_ctl_io *io = &info.data.io;
190
191 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
192 io->offset = off;
193 io->dma_addr = addr;
194 ethdev->drv_ctl(dev->netdev, &info);
195}
196
197static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
198{
199 struct cnic_local *cp = dev->cnic_priv;
200 struct cnic_eth_dev *ethdev = cp->ethdev;
201 struct drv_ctl_info info;
202 struct drv_ctl_l2_ring *ring = &info.data.ring;
203
204 if (start)
205 info.cmd = DRV_CTL_START_L2_CMD;
206 else
207 info.cmd = DRV_CTL_STOP_L2_CMD;
208
209 ring->cid = cid;
210 ring->client_id = cl_id;
211 ethdev->drv_ctl(dev->netdev, &info);
212}
213
a4636960
MC		 214static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
215{
216 struct cnic_local *cp = dev->cnic_priv;
217 struct cnic_eth_dev *ethdev = cp->ethdev;
218 struct drv_ctl_info info;
219 struct drv_ctl_io *io = &info.data.io;
220
221 info.cmd = DRV_CTL_IO_WR_CMD;
222 io->offset = off;
223 io->data = val;
224 ethdev->drv_ctl(dev->netdev, &info);
225}
226
227static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
228{
229 struct cnic_local *cp = dev->cnic_priv;
230 struct cnic_eth_dev *ethdev = cp->ethdev;
231 struct drv_ctl_info info;
232 struct drv_ctl_io *io = &info.data.io;
233
234 info.cmd = DRV_CTL_IO_RD_CMD;
235 io->offset = off;
236 ethdev->drv_ctl(dev->netdev, &info);
237 return io->data;
238}
239
240static int cnic_in_use(struct cnic_sock *csk)
241{
242 return test_bit(SK_F_INUSE, &csk->flags);
243}
244
c2bff63f 245static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
a4636960
MC		 246{
247 struct cnic_local *cp = dev->cnic_priv;
248 struct cnic_eth_dev *ethdev = cp->ethdev;
249 struct drv_ctl_info info;
250
c2bff63f
DK		 251 info.cmd = cmd;
252 info.data.credit.credit_count = count;
a4636960
MC		 253 ethdev->drv_ctl(dev->netdev, &info);
254}
255
71034ba8
MC		 256static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
257{
258 u32 i;
259
520efdf4 260 for (i = 0; i < cp->max_cid_space; i++) {
71034ba8
MC		 261 if (cp->ctx_tbl[i].cid == cid) {
262 *l5_cid = i;
263 return 0;
264 }
265 }
266 return -EINVAL;
267}
268
a4636960
MC		 269static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
270 struct cnic_sock *csk)
271{
272 struct iscsi_path path_req;
273 char *buf = NULL;
274 u16 len = 0;
275 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
276 struct cnic_ulp_ops *ulp_ops;
277
278 if (cp->uio_dev == -1)
279 return -ENODEV;
280
281 if (csk) {
282 len = sizeof(path_req);
283 buf = (char *) &path_req;
284 memset(&path_req, 0, len);
285
286 msg_type = ISCSI_KEVENT_PATH_REQ;
287 path_req.handle = (u64) csk->l5_cid;
288 if (test_bit(SK_F_IPV6, &csk->flags)) {
289 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
290 sizeof(struct in6_addr));
291 path_req.ip_addr_len = 16;
292 } else {
293 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
294 sizeof(struct in_addr));
295 path_req.ip_addr_len = 4;
296 }
297 path_req.vlan_id = csk->vlan_id;
298 path_req.pmtu = csk->mtu;
299 }
300
301 rcu_read_lock();
6d7760a8 302 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
a4636960
MC		 303 if (ulp_ops)
304 ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
305 rcu_read_unlock();
306 return 0;
307}
308
309static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
310 char *buf, u16 len)
311{
312 int rc = -EINVAL;
313
314 switch (msg_type) {
315 case ISCSI_UEVENT_PATH_UPDATE: {
316 struct cnic_local *cp;
317 u32 l5_cid;
318 struct cnic_sock *csk;
319 struct iscsi_path *path_resp;
320
321 if (len < sizeof(*path_resp))
322 break;
323
324 path_resp = (struct iscsi_path *) buf;
325 cp = dev->cnic_priv;
326 l5_cid = (u32) path_resp->handle;
327 if (l5_cid >= MAX_CM_SK_TBL_SZ)
328 break;
329
d02a5e6c
MC		 330 rcu_read_lock();
331 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
332 rc = -ENODEV;
333 rcu_read_unlock();
334 break;
335 }
a4636960
MC		 336 csk = &cp->csk_tbl[l5_cid];
337 csk_hold(csk);
338 if (cnic_in_use(csk)) {
339 memcpy(csk->ha, path_resp->mac_addr, 6);
340 if (test_bit(SK_F_IPV6, &csk->flags))
341 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
342 sizeof(struct in6_addr));
343 else
344 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
345 sizeof(struct in_addr));
346 if (is_valid_ether_addr(csk->ha))
347 cnic_cm_set_pg(csk);
348 }
349 csk_put(csk);
d02a5e6c 350 rcu_read_unlock();
a4636960
MC		 351 rc = 0;
352 }
353 }
354
355 return rc;
356}
357
358static int cnic_offld_prep(struct cnic_sock *csk)
359{
360 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
361 return 0;
362
363 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
364 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
365 return 0;
366 }
367
368 return 1;
369}
370
371static int cnic_close_prep(struct cnic_sock *csk)
372{
373 clear_bit(SK_F_CONNECT_START, &csk->flags);
374 smp_mb__after_clear_bit();
375
376 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
377 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
378 msleep(1);
379
380 return 1;
381 }
382 return 0;
383}
384
385static int cnic_abort_prep(struct cnic_sock *csk)
386{
387 clear_bit(SK_F_CONNECT_START, &csk->flags);
388 smp_mb__after_clear_bit();
389
390 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
391 msleep(1);
392
393 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
394 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
395 return 1;
396 }
397
398 return 0;
399}
400
6d7760a8
MC		 401static void cnic_uio_stop(void)
402{
403 struct cnic_dev *dev;
404
405 read_lock(&cnic_dev_lock);
406 list_for_each_entry(dev, &cnic_dev_list, list) {
407 struct cnic_local *cp = dev->cnic_priv;
408
409 if (cp->cnic_uinfo)
410 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
411 }
412 read_unlock(&cnic_dev_lock);
413}
414
a4636960
MC		 415int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
416{
417 struct cnic_dev *dev;
418
0d37f36f 419 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 420 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 421 return -EINVAL;
422 }
423 mutex_lock(&cnic_lock);
424 if (cnic_ulp_tbl[ulp_type]) {
ddf79b20
JP		 425 pr_err("%s: Type %d has already been registered\n",
426 __func__, ulp_type);
a4636960
MC		 427 mutex_unlock(&cnic_lock);
428 return -EBUSY;
429 }
430
431 read_lock(&cnic_dev_lock);
432 list_for_each_entry(dev, &cnic_dev_list, list) {
433 struct cnic_local *cp = dev->cnic_priv;
434
435 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
436 }
437 read_unlock(&cnic_dev_lock);
438
7fc1ece4 439 atomic_set(&ulp_ops->ref_count, 0);
a4636960
MC		 440 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
441 mutex_unlock(&cnic_lock);
442
443 /* Prevent race conditions with netdev_event */
444 rtnl_lock();
445 read_lock(&cnic_dev_lock);
446 list_for_each_entry(dev, &cnic_dev_list, list) {
447 struct cnic_local *cp = dev->cnic_priv;
448
449 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
450 ulp_ops->cnic_init(dev);
451 }
452 read_unlock(&cnic_dev_lock);
453 rtnl_unlock();
454
455 return 0;
456}
457
458int cnic_unregister_driver(int ulp_type)
459{
460 struct cnic_dev *dev;
7fc1ece4
MC		 461 struct cnic_ulp_ops *ulp_ops;
462 int i = 0;
a4636960 463
0d37f36f 464 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 465 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 466 return -EINVAL;
467 }
468 mutex_lock(&cnic_lock);
7fc1ece4
MC		 469 ulp_ops = cnic_ulp_tbl[ulp_type];
470 if (!ulp_ops) {
ddf79b20
JP		 471 pr_err("%s: Type %d has not been registered\n",
472 __func__, ulp_type);
a4636960
MC		 473 goto out_unlock;
474 }
475 read_lock(&cnic_dev_lock);
476 list_for_each_entry(dev, &cnic_dev_list, list) {
477 struct cnic_local *cp = dev->cnic_priv;
478
479 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
ddf79b20
JP		 480 pr_err("%s: Type %d still has devices registered\n",
481 __func__, ulp_type);
a4636960
MC		 482 read_unlock(&cnic_dev_lock);
483 goto out_unlock;
484 }
485 }
486 read_unlock(&cnic_dev_lock);
487
6d7760a8
MC		 488 if (ulp_type == CNIC_ULP_ISCSI)
489 cnic_uio_stop();
490
a4636960
MC		 491 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
492
493 mutex_unlock(&cnic_lock);
494 synchronize_rcu();
7fc1ece4
MC		 495 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
496 msleep(100);
497 i++;
498 }
499
500 if (atomic_read(&ulp_ops->ref_count) != 0)
ddf79b20 501 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
a4636960
MC		 502 return 0;
503
504out_unlock:
505 mutex_unlock(&cnic_lock);
506 return -EINVAL;
507}
508
509static int cnic_start_hw(struct cnic_dev *);
510static void cnic_stop_hw(struct cnic_dev *);
511
512static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
513 void *ulp_ctx)
514{
515 struct cnic_local *cp = dev->cnic_priv;
516 struct cnic_ulp_ops *ulp_ops;
517
0d37f36f 518 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 519 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 520 return -EINVAL;
521 }
522 mutex_lock(&cnic_lock);
523 if (cnic_ulp_tbl[ulp_type] == NULL) {
ddf79b20
JP		 524 pr_err("%s: Driver with type %d has not been registered\n",
525 __func__, ulp_type);
a4636960
MC		 526 mutex_unlock(&cnic_lock);
527 return -EAGAIN;
528 }
529 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
ddf79b20
JP		 530 pr_err("%s: Type %d has already been registered to this device\n",
531 __func__, ulp_type);
a4636960
MC		 532 mutex_unlock(&cnic_lock);
533 return -EBUSY;
534 }
535
536 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
537 cp->ulp_handle[ulp_type] = ulp_ctx;
538 ulp_ops = cnic_ulp_tbl[ulp_type];
539 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
540 cnic_hold(dev);
541
542 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
543 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
544 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
545
546 mutex_unlock(&cnic_lock);
547
548 return 0;
549
550}
551EXPORT_SYMBOL(cnic_register_driver);
552
553static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
554{
555 struct cnic_local *cp = dev->cnic_priv;
681dbd71 556 int i = 0;
a4636960 557
0d37f36f 558 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 559 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 560 return -EINVAL;
561 }
562 mutex_lock(&cnic_lock);
563 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
564 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
565 cnic_put(dev);
566 } else {
ddf79b20
JP		 567 pr_err("%s: device not registered to this ulp type %d\n",
568 __func__, ulp_type);
a4636960
MC		 569 mutex_unlock(&cnic_lock);
570 return -EINVAL;
571 }
572 mutex_unlock(&cnic_lock);
573
574 synchronize_rcu();
575
681dbd71
MC		 576 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
577 i < 20) {
578 msleep(100);
579 i++;
580 }
581 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
ddf79b20 582 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
681dbd71 583
a4636960
MC		 584 return 0;
585}
586EXPORT_SYMBOL(cnic_unregister_driver);
587
588static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
589{
590 id_tbl->start = start_id;
591 id_tbl->max = size;
592 id_tbl->next = 0;
593 spin_lock_init(&id_tbl->lock);
594 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
595 if (!id_tbl->table)
596 return -ENOMEM;
597
598 return 0;
599}
600
601static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
602{
603 kfree(id_tbl->table);
604 id_tbl->table = NULL;
605}
606
607static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
608{
609 int ret = -1;
610
611 id -= id_tbl->start;
612 if (id >= id_tbl->max)
613 return ret;
614
615 spin_lock(&id_tbl->lock);
616 if (!test_bit(id, id_tbl->table)) {
617 set_bit(id, id_tbl->table);
618 ret = 0;
619 }
620 spin_unlock(&id_tbl->lock);
621 return ret;
622}
623
624/* Returns -1 if not successful */
625static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
626{
627 u32 id;
628
629 spin_lock(&id_tbl->lock);
630 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
631 if (id >= id_tbl->max) {
632 id = -1;
633 if (id_tbl->next != 0) {
634 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
635 if (id >= id_tbl->next)
636 id = -1;
637 }
638 }
639
640 if (id < id_tbl->max) {
641 set_bit(id, id_tbl->table);
642 id_tbl->next = (id + 1) & (id_tbl->max - 1);
643 id += id_tbl->start;
644 }
645
646 spin_unlock(&id_tbl->lock);
647
648 return id;
649}
650
651static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
652{
653 if (id == -1)
654 return;
655
656 id -= id_tbl->start;
657 if (id >= id_tbl->max)
658 return;
659
660 clear_bit(id, id_tbl->table);
661}
662
663static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
664{
665 int i;
666
667 if (!dma->pg_arr)
668 return;
669
670 for (i = 0; i < dma->num_pages; i++) {
671 if (dma->pg_arr[i]) {
3248e168
MC		 672 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
673 dma->pg_arr[i], dma->pg_map_arr[i]);
a4636960
MC		 674 dma->pg_arr[i] = NULL;
675 }
676 }
677 if (dma->pgtbl) {
3248e168
MC		 678 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
679 dma->pgtbl, dma->pgtbl_map);
a4636960
MC		 680 dma->pgtbl = NULL;
681 }
682 kfree(dma->pg_arr);
683 dma->pg_arr = NULL;
684 dma->num_pages = 0;
685}
686
687static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
688{
689 int i;
690 u32 *page_table = dma->pgtbl;
691
692 for (i = 0; i < dma->num_pages; i++) {
693 /* Each entry needs to be in big endian format. */
694 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
695 page_table++;
696 *page_table = (u32) dma->pg_map_arr[i];
697 page_table++;
698 }
699}
700
71034ba8
MC		 701static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
702{
703 int i;
704 u32 *page_table = dma->pgtbl;
705
706 for (i = 0; i < dma->num_pages; i++) {
707 /* Each entry needs to be in little endian format. */
708 *page_table = dma->pg_map_arr[i] & 0xffffffff;
709 page_table++;
710 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
711 page_table++;
712 }
713}
714
a4636960
MC		 715static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
716 int pages, int use_pg_tbl)
717{
718 int i, size;
719 struct cnic_local *cp = dev->cnic_priv;
720
721 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
722 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
723 if (dma->pg_arr == NULL)
724 return -ENOMEM;
725
726 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
727 dma->num_pages = pages;
728
729 for (i = 0; i < pages; i++) {
3248e168
MC		 730 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
731 BCM_PAGE_SIZE,
732 &dma->pg_map_arr[i],
733 GFP_ATOMIC);
a4636960
MC		 734 if (dma->pg_arr[i] == NULL)
735 goto error;
736 }
737 if (!use_pg_tbl)
738 return 0;
739
740 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
741 ~(BCM_PAGE_SIZE - 1);
3248e168
MC		 742 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
743 &dma->pgtbl_map, GFP_ATOMIC);
a4636960
MC		 744 if (dma->pgtbl == NULL)
745 goto error;
746
747 cp->setup_pgtbl(dev, dma);
748
749 return 0;
750
751error:
752 cnic_free_dma(dev, dma);
753 return -ENOMEM;
754}
755
86b53606
MC		 756static void cnic_free_context(struct cnic_dev *dev)
757{
758 struct cnic_local *cp = dev->cnic_priv;
759 int i;
760
761 for (i = 0; i < cp->ctx_blks; i++) {
762 if (cp->ctx_arr[i].ctx) {
3248e168
MC		 763 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
764 cp->ctx_arr[i].ctx,
765 cp->ctx_arr[i].mapping);
86b53606
MC		 766 cp->ctx_arr[i].ctx = NULL;
767 }
768 }
769}
770
a4636960
MC		 771static void cnic_free_resc(struct cnic_dev *dev)
772{
773 struct cnic_local *cp = dev->cnic_priv;
774 int i = 0;
775
776 if (cp->cnic_uinfo) {
a4636960
MC		 777 while (cp->uio_dev != -1 && i < 15) {
778 msleep(100);
779 i++;
780 }
781 uio_unregister_device(cp->cnic_uinfo);
782 kfree(cp->cnic_uinfo);
783 cp->cnic_uinfo = NULL;
784 }
785
786 if (cp->l2_buf) {
3248e168
MC		 787 dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
788 cp->l2_buf, cp->l2_buf_map);
a4636960
MC		 789 cp->l2_buf = NULL;
790 }
791
792 if (cp->l2_ring) {
3248e168
MC		 793 dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
794 cp->l2_ring, cp->l2_ring_map);
a4636960
MC		 795 cp->l2_ring = NULL;
796 }
797
86b53606 798 cnic_free_context(dev);
a4636960
MC		 799 kfree(cp->ctx_arr);
800 cp->ctx_arr = NULL;
801 cp->ctx_blks = 0;
802
803 cnic_free_dma(dev, &cp->gbl_buf_info);
804 cnic_free_dma(dev, &cp->conn_buf_info);
805 cnic_free_dma(dev, &cp->kwq_info);
71034ba8 806 cnic_free_dma(dev, &cp->kwq_16_data_info);
e6c28894 807 cnic_free_dma(dev, &cp->kcq1.dma);
a4636960
MC		 808 kfree(cp->iscsi_tbl);
809 cp->iscsi_tbl = NULL;
810 kfree(cp->ctx_tbl);
811 cp->ctx_tbl = NULL;
812
813 cnic_free_id_tbl(&cp->cid_tbl);
814}
815
816static int cnic_alloc_context(struct cnic_dev *dev)
817{
818 struct cnic_local *cp = dev->cnic_priv;
819
820 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
821 int i, k, arr_size;
822
823 cp->ctx_blk_size = BCM_PAGE_SIZE;
824 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
825 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
826 sizeof(struct cnic_ctx);
827 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
828 if (cp->ctx_arr == NULL)
829 return -ENOMEM;
830
831 k = 0;
832 for (i = 0; i < 2; i++) {
833 u32 j, reg, off, lo, hi;
834
835 if (i == 0)
836 off = BNX2_PG_CTX_MAP;
837 else
838 off = BNX2_ISCSI_CTX_MAP;
839
840 reg = cnic_reg_rd_ind(dev, off);
841 lo = reg >> 16;
842 hi = reg & 0xffff;
843 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
844 cp->ctx_arr[k].cid = j;
845 }
846
847 cp->ctx_blks = k;
848 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
849 cp->ctx_blks = 0;
850 return -ENOMEM;
851 }
852
853 for (i = 0; i < cp->ctx_blks; i++) {
854 cp->ctx_arr[i].ctx =
3248e168
MC		 855 dma_alloc_coherent(&dev->pcidev->dev,
856 BCM_PAGE_SIZE,
857 &cp->ctx_arr[i].mapping,
858 GFP_KERNEL);
a4636960
MC		 859 if (cp->ctx_arr[i].ctx == NULL)
860 return -ENOMEM;
861 }
862 }
863 return 0;
864}
865
e6c28894
MC		 866static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
867{
868 int err, i, is_bnx2 = 0;
869 struct kcqe **kcq;
870
871 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
872 is_bnx2 = 1;
873
874 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
875 if (err)
876 return err;
877
878 kcq = (struct kcqe **) info->dma.pg_arr;
879 info->kcq = kcq;
880
881 if (is_bnx2)
882 return 0;
883
884 for (i = 0; i < KCQ_PAGE_CNT; i++) {
885 struct bnx2x_bd_chain_next *next =
886 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
887 int j = i + 1;
888
889 if (j >= KCQ_PAGE_CNT)
890 j = 0;
891 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
892 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
893 }
894 return 0;
895}
896
ec0248ea
MC		 897static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
898{
899 struct cnic_local *cp = dev->cnic_priv;
900
901 cp->l2_ring_size = pages * BCM_PAGE_SIZE;
3248e168
MC		 902 cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
903 &cp->l2_ring_map,
904 GFP_KERNEL | __GFP_COMP);
ec0248ea
MC		 905 if (!cp->l2_ring)
906 return -ENOMEM;
907
908 cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
909 cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
3248e168
MC		 910 cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
911 &cp->l2_buf_map,
912 GFP_KERNEL | __GFP_COMP);
ec0248ea
MC		 913 if (!cp->l2_buf)
914 return -ENOMEM;
915
916 return 0;
917}
918
5e9b2dbf 919static int cnic_alloc_uio(struct cnic_dev *dev) {
a4636960
MC		 920 struct cnic_local *cp = dev->cnic_priv;
921 struct uio_info *uinfo;
922 int ret;
923
a4636960
MC		 924 uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
925 if (!uinfo)
5e9b2dbf 926 return -ENOMEM;
a4636960
MC		 927
928 uinfo->mem[0].addr = dev->netdev->base_addr;
929 uinfo->mem[0].internal_addr = dev->regview;
930 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
931 uinfo->mem[0].memtype = UIO_MEM_PHYS;
932
5e9b2dbf 933 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
a4dde3ab
MC		 934 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
935 PAGE_MASK;
5e9b2dbf
MC		 936 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
937 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
938 else
939 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
940
941 uinfo->name = "bnx2_cnic";
71034ba8
MC		 942 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
943 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
944 PAGE_MASK;
523224a3 945 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
71034ba8
MC		 946
947 uinfo->name = "bnx2x_cnic";
5e9b2dbf
MC		 948 }
949
a4636960
MC		 950 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
951
952 uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
953 uinfo->mem[2].size = cp->l2_ring_size;
954 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
955
956 uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
957 uinfo->mem[3].size = cp->l2_buf_size;
958 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
959
a4636960
MC		 960 uinfo->version = CNIC_MODULE_VERSION;
961 uinfo->irq = UIO_IRQ_CUSTOM;
962
963 uinfo->open = cnic_uio_open;
964 uinfo->release = cnic_uio_close;
965
966 uinfo->priv = dev;
967
968 ret = uio_register_device(&dev->pcidev->dev, uinfo);
969 if (ret) {
970 kfree(uinfo);
5e9b2dbf 971 return ret;
a4636960
MC		 972 }
973
974 cp->cnic_uinfo = uinfo;
5e9b2dbf
MC		 975 return 0;
976}
977
978static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
979{
980 struct cnic_local *cp = dev->cnic_priv;
981 int ret;
982
983 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
984 if (ret)
985 goto error;
986 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
987
e6c28894 988 ret = cnic_alloc_kcq(dev, &cp->kcq1);
5e9b2dbf
MC		 989 if (ret)
990 goto error;
5e9b2dbf
MC		 991
992 ret = cnic_alloc_context(dev);
993 if (ret)
994 goto error;
995
996 ret = cnic_alloc_l2_rings(dev, 2);
997 if (ret)
998 goto error;
999
1000 ret = cnic_alloc_uio(dev);
1001 if (ret)
1002 goto error;
a4636960
MC		 1003
1004 return 0;
1005
1006error:
1007 cnic_free_resc(dev);
1008 return ret;
1009}
1010
71034ba8
MC		 1011static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1012{
1013 struct cnic_local *cp = dev->cnic_priv;
71034ba8 1014 int ctx_blk_size = cp->ethdev->ctx_blk_size;
520efdf4 1015 int total_mem, blks, i;
71034ba8 1016
520efdf4 1017 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
71034ba8
MC		 1018 blks = total_mem / ctx_blk_size;
1019 if (total_mem % ctx_blk_size)
1020 blks++;
1021
1022 if (blks > cp->ethdev->ctx_tbl_len)
1023 return -ENOMEM;
1024
baeb2ffa 1025 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
71034ba8
MC		 1026 if (cp->ctx_arr == NULL)
1027 return -ENOMEM;
1028
1029 cp->ctx_blks = blks;
1030 cp->ctx_blk_size = ctx_blk_size;
1031 if (BNX2X_CHIP_IS_E1H(cp->chip_id))
1032 cp->ctx_align = 0;
1033 else
1034 cp->ctx_align = ctx_blk_size;
1035
1036 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1037
1038 for (i = 0; i < blks; i++) {
1039 cp->ctx_arr[i].ctx =
3248e168
MC		 1040 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1041 &cp->ctx_arr[i].mapping,
1042 GFP_KERNEL);
71034ba8
MC		 1043 if (cp->ctx_arr[i].ctx == NULL)
1044 return -ENOMEM;
1045
1046 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1047 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1048 cnic_free_context(dev);
1049 cp->ctx_blk_size += cp->ctx_align;
1050 i = -1;
1051 continue;
1052 }
1053 }
1054 }
1055 return 0;
1056}
1057
1058static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1059{
1060 struct cnic_local *cp = dev->cnic_priv;
520efdf4
MC		 1061 struct cnic_eth_dev *ethdev = cp->ethdev;
1062 u32 start_cid = ethdev->starting_cid;
71034ba8
MC		 1063 int i, j, n, ret, pages;
1064 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1065
523224a3
DK		 1066 cp->iro_arr = ethdev->iro_arr;
1067
520efdf4
MC		 1068 cp->max_cid_space = MAX_ISCSI_TBL_SZ;
1069 cp->iscsi_start_cid = start_cid;
1070 if (start_cid < BNX2X_ISCSI_START_CID) {
1071 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1072
1073 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1074 cp->max_cid_space += delta;
1075 }
1076
71034ba8
MC		 1077 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1078 GFP_KERNEL);
1079 if (!cp->iscsi_tbl)
1080 goto error;
1081
1082 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
520efdf4 1083 cp->max_cid_space, GFP_KERNEL);
71034ba8
MC		 1084 if (!cp->ctx_tbl)
1085 goto error;
1086
1087 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1088 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1089 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1090 }
1091
520efdf4 1092 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
71034ba8
MC		 1093 PAGE_SIZE;
1094
1095 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1096 if (ret)
1097 return -ENOMEM;
1098
1099 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
520efdf4 1100 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
71034ba8
MC		 1101 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1102
1103 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1104 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1105 off;
1106
1107 if ((i % n) == (n - 1))
1108 j++;
1109 }
1110
e6c28894 1111 ret = cnic_alloc_kcq(dev, &cp->kcq1);
71034ba8
MC		 1112 if (ret)
1113 goto error;
71034ba8
MC		 1114
1115 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1116 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1117 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1118 if (ret)
1119 goto error;
1120
1121 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1122 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1123 if (ret)
1124 goto error;
1125
1126 ret = cnic_alloc_bnx2x_context(dev);
1127 if (ret)
1128 goto error;
1129
71034ba8
MC		 1130 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1131
1132 cp->l2_rx_ring_size = 15;
1133
1134 ret = cnic_alloc_l2_rings(dev, 4);
1135 if (ret)
1136 goto error;
1137
1138 ret = cnic_alloc_uio(dev);
1139 if (ret)
1140 goto error;
1141
1142 return 0;
1143
1144error:
1145 cnic_free_resc(dev);
1146 return -ENOMEM;
1147}
1148
a4636960
MC		 1149static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1150{
1151 return cp->max_kwq_idx -
1152 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1153}
1154
1155static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1156 u32 num_wqes)
1157{
1158 struct cnic_local *cp = dev->cnic_priv;
1159 struct kwqe *prod_qe;
1160 u16 prod, sw_prod, i;
1161
1162 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1163 return -EAGAIN; /* bnx2 is down */
1164
1165 spin_lock_bh(&cp->cnic_ulp_lock);
1166 if (num_wqes > cnic_kwq_avail(cp) &&
1f1332a3 1167 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
a4636960
MC		 1168 spin_unlock_bh(&cp->cnic_ulp_lock);
1169 return -EAGAIN;
1170 }
1171
1f1332a3 1172 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
a4636960
MC		 1173
1174 prod = cp->kwq_prod_idx;
1175 sw_prod = prod & MAX_KWQ_IDX;
1176 for (i = 0; i < num_wqes; i++) {
1177 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1178 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1179 prod++;
1180 sw_prod = prod & MAX_KWQ_IDX;
1181 }
1182 cp->kwq_prod_idx = prod;
1183
1184 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1185
1186 spin_unlock_bh(&cp->cnic_ulp_lock);
1187 return 0;
1188}
1189
71034ba8
MC		 1190static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1191 union l5cm_specific_data *l5_data)
1192{
1193 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1194 dma_addr_t map;
1195
1196 map = ctx->kwqe_data_mapping;
1197 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1198 l5_data->phy_address.hi = (u64) map >> 32;
1199 return ctx->kwqe_data;
1200}
1201
1202static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1203 u32 type, union l5cm_specific_data *l5_data)
1204{
1205 struct cnic_local *cp = dev->cnic_priv;
1206 struct l5cm_spe kwqe;
1207 struct kwqe_16 *kwq[1];
1208 int ret;
1209
1210 kwqe.hdr.conn_and_cmd_data =
1211 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
ceb7e1c7 1212 BNX2X_HW_CID(cp, cid)));
71034ba8 1213 kwqe.hdr.type = cpu_to_le16(type);
523224a3 1214 kwqe.hdr.reserved1 = 0;
71034ba8
MC		 1215 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1216 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1217
1218 kwq[0] = (struct kwqe_16 *) &kwqe;
1219
1220 spin_lock_bh(&cp->cnic_ulp_lock);
1221 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1222 spin_unlock_bh(&cp->cnic_ulp_lock);
1223
1224 if (ret == 1)
1225 return 0;
1226
1227 return -EBUSY;
1228}
1229
1230static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1231 struct kcqe *cqes[], u32 num_cqes)
1232{
1233 struct cnic_local *cp = dev->cnic_priv;
1234 struct cnic_ulp_ops *ulp_ops;
1235
1236 rcu_read_lock();
1237 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1238 if (likely(ulp_ops)) {
1239 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1240 cqes, num_cqes);
1241 }
1242 rcu_read_unlock();
1243}
1244
1245static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1246{
1247 struct cnic_local *cp = dev->cnic_priv;
1248 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1420398d
MC		 1249 int hq_bds, pages;
1250 u32 pfid = cp->pfid;
71034ba8
MC		 1251
1252 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1253 cp->num_ccells = req1->num_ccells_per_conn;
1254 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1255 cp->num_iscsi_tasks;
1256 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1257 BNX2X_ISCSI_R2TQE_SIZE;
1258 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1259 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1260 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1261 cp->num_cqs = req1->num_cqs;
1262
1263 if (!dev->max_iscsi_conn)
1264 return 0;
1265
1266 /* init Tstorm RAM */
1420398d 1267 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
71034ba8 1268 req1->rq_num_wqes);
1420398d 1269 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
71034ba8
MC		 1270 PAGE_SIZE);
1271 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1272 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
71034ba8 1273 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1420398d 1274 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
71034ba8
MC		 1275 req1->num_tasks_per_conn);
1276
1277 /* init Ustorm RAM */
1278 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1420398d 1279 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
71034ba8 1280 req1->rq_buffer_size);
1420398d 1281 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
71034ba8
MC		 1282 PAGE_SIZE);
1283 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1420398d 1284 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
71034ba8 1285 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1420398d 1286 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
71034ba8 1287 req1->num_tasks_per_conn);
1420398d 1288 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
71034ba8 1289 req1->rq_num_wqes);
1420398d 1290 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
71034ba8 1291 req1->cq_num_wqes);
1420398d 1292 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
71034ba8
MC		 1293 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1294
1295 /* init Xstorm RAM */
1420398d 1296 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
71034ba8
MC		 1297 PAGE_SIZE);
1298 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1299 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
71034ba8 1300 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1420398d 1301 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
71034ba8 1302 req1->num_tasks_per_conn);
1420398d 1303 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
71034ba8 1304 hq_bds);
1420398d 1305 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
71034ba8 1306 req1->num_tasks_per_conn);
1420398d 1307 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
71034ba8
MC		 1308 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1309
1310 /* init Cstorm RAM */
1420398d 1311 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
71034ba8
MC		 1312 PAGE_SIZE);
1313 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1420398d 1314 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
71034ba8 1315 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1420398d 1316 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
71034ba8 1317 req1->num_tasks_per_conn);
1420398d 1318 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
71034ba8 1319 req1->cq_num_wqes);
1420398d 1320 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
71034ba8
MC		 1321 hq_bds);
1322
1323 return 0;
1324}
1325
1326static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1327{
1328 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1329 struct cnic_local *cp = dev->cnic_priv;
1420398d 1330 u32 pfid = cp->pfid;
71034ba8
MC		 1331 struct iscsi_kcqe kcqe;
1332 struct kcqe *cqes[1];
1333
1334 memset(&kcqe, 0, sizeof(kcqe));
1335 if (!dev->max_iscsi_conn) {
1336 kcqe.completion_status =
1337 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1338 goto done;
1339 }
1340
1341 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1420398d 1342 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
71034ba8 1343 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1420398d 1344 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
71034ba8
MC		 1345 req2->error_bit_map[1]);
1346
1347 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1420398d 1348 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
71034ba8 1349 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1420398d 1350 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
71034ba8 1351 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1420398d 1352 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
71034ba8
MC		 1353 req2->error_bit_map[1]);
1354
1355 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1420398d 1356 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
71034ba8
MC		 1357
1358 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1359
1360done:
1361 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1362 cqes[0] = (struct kcqe *) &kcqe;
1363 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1364
1365 return 0;
1366}
1367
1368static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1369{
1370 struct cnic_local *cp = dev->cnic_priv;
1371 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1372
1373 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1374 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1375
1376 cnic_free_dma(dev, &iscsi->hq_info);
1377 cnic_free_dma(dev, &iscsi->r2tq_info);
1378 cnic_free_dma(dev, &iscsi->task_array_info);
1379 }
1380 cnic_free_id(&cp->cid_tbl, ctx->cid);
1381 ctx->cid = 0;
1382}
1383
1384static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1385{
1386 u32 cid;
1387 int ret, pages;
1388 struct cnic_local *cp = dev->cnic_priv;
1389 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1390 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1391
1392 cid = cnic_alloc_new_id(&cp->cid_tbl);
1393 if (cid == -1) {
1394 ret = -ENOMEM;
1395 goto error;
1396 }
1397
1398 ctx->cid = cid;
1399 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1400
1401 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1402 if (ret)
1403 goto error;
1404
1405 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1406 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1407 if (ret)
1408 goto error;
1409
1410 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1411 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1412 if (ret)
1413 goto error;
1414
1415 return 0;
1416
1417error:
1418 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1419 return ret;
1420}
1421
1422static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1423 struct regpair *ctx_addr)
1424{
1425 struct cnic_local *cp = dev->cnic_priv;
1426 struct cnic_eth_dev *ethdev = cp->ethdev;
1427 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1428 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1429 unsigned long align_off = 0;
1430 dma_addr_t ctx_map;
1431 void *ctx;
1432
1433 if (cp->ctx_align) {
1434 unsigned long mask = cp->ctx_align - 1;
1435
1436 if (cp->ctx_arr[blk].mapping & mask)
1437 align_off = cp->ctx_align -
1438 (cp->ctx_arr[blk].mapping & mask);
1439 }
1440 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1441 (off * BNX2X_CONTEXT_MEM_SIZE);
1442 ctx = cp->ctx_arr[blk].ctx + align_off +
1443 (off * BNX2X_CONTEXT_MEM_SIZE);
1444 if (init)
1445 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1446
1447 ctx_addr->lo = ctx_map & 0xffffffff;
1448 ctx_addr->hi = (u64) ctx_map >> 32;
1449 return ctx;
1450}
1451
1452static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1453 u32 num)
1454{
1455 struct cnic_local *cp = dev->cnic_priv;
1456 struct iscsi_kwqe_conn_offload1 *req1 =
1457 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1458 struct iscsi_kwqe_conn_offload2 *req2 =
1459 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1460 struct iscsi_kwqe_conn_offload3 *req3;
1461 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1462 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1463 u32 cid = ctx->cid;
ceb7e1c7 1464 u32 hw_cid = BNX2X_HW_CID(cp, cid);
71034ba8
MC		 1465 struct iscsi_context *ictx;
1466 struct regpair context_addr;
1467 int i, j, n = 2, n_max;
1468
1469 ctx->ctx_flags = 0;
1470 if (!req2->num_additional_wqes)
1471 return -EINVAL;
1472
1473 n_max = req2->num_additional_wqes + 2;
1474
1475 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1476 if (ictx == NULL)
1477 return -ENOMEM;
1478
1479 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1480
1481 ictx->xstorm_ag_context.hq_prod = 1;
1482
1483 ictx->xstorm_st_context.iscsi.first_burst_length =
1484 ISCSI_DEF_FIRST_BURST_LEN;
1485 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1486 ISCSI_DEF_MAX_RECV_SEG_LEN;
1487 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1488 req1->sq_page_table_addr_lo;
1489 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1490 req1->sq_page_table_addr_hi;
1491 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1492 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1493 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1494 iscsi->hq_info.pgtbl_map & 0xffffffff;
1495 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1496 (u64) iscsi->hq_info.pgtbl_map >> 32;
1497 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1498 iscsi->hq_info.pgtbl[0];
1499 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1500 iscsi->hq_info.pgtbl[1];
1501 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1502 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1503 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1504 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1505 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1506 iscsi->r2tq_info.pgtbl[0];
1507 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1508 iscsi->r2tq_info.pgtbl[1];
1509 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1510 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1511 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1512 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1513 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1514 BNX2X_ISCSI_PBL_NOT_CACHED;
1515 ictx->xstorm_st_context.iscsi.flags.flags |=
1516 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1517 ictx->xstorm_st_context.iscsi.flags.flags |=
1518 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1519
1520 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1521 /* TSTORM requires the base address of RQ DB & not PTE */
1522 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1523 req2->rq_page_table_addr_lo & PAGE_MASK;
1524 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1525 req2->rq_page_table_addr_hi;
1526 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1527 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1528 ictx->tstorm_st_context.tcp.flags2 |=
1529 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
523224a3
DK		 1530 ictx->tstorm_st_context.tcp.ooo_support_mode =
1531 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
71034ba8 1532
523224a3 1533 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
71034ba8
MC		 1534
1535 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
15971c3c 1536 req2->rq_page_table_addr_lo;
71034ba8 1537 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
15971c3c 1538 req2->rq_page_table_addr_hi;
71034ba8
MC		 1539 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1540 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1541 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1542 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1543 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1544 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1545 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1546 iscsi->r2tq_info.pgtbl[0];
1547 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1548 iscsi->r2tq_info.pgtbl[1];
1549 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1550 req1->cq_page_table_addr_lo;
1551 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1552 req1->cq_page_table_addr_hi;
1553 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1554 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1555 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1556 ictx->ustorm_st_context.task_pbe_cache_index =
1557 BNX2X_ISCSI_PBL_NOT_CACHED;
1558 ictx->ustorm_st_context.task_pdu_cache_index =
1559 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1560
1561 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1562 if (j == 3) {
1563 if (n >= n_max)
1564 break;
1565 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1566 j = 0;
1567 }
1568 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1569 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1570 req3->qp_first_pte[j].hi;
1571 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1572 req3->qp_first_pte[j].lo;
1573 }
1574
1575 ictx->ustorm_st_context.task_pbl_base.lo =
1576 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1577 ictx->ustorm_st_context.task_pbl_base.hi =
1578 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1579 ictx->ustorm_st_context.tce_phy_addr.lo =
1580 iscsi->task_array_info.pgtbl[0];
1581 ictx->ustorm_st_context.tce_phy_addr.hi =
1582 iscsi->task_array_info.pgtbl[1];
1583 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1584 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1585 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1586 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1587 ISCSI_DEF_MAX_BURST_LEN;
1588 ictx->ustorm_st_context.negotiated_rx |=
1589 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1590 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1591
1592 ictx->cstorm_st_context.hq_pbl_base.lo =
1593 iscsi->hq_info.pgtbl_map & 0xffffffff;
1594 ictx->cstorm_st_context.hq_pbl_base.hi =
1595 (u64) iscsi->hq_info.pgtbl_map >> 32;
1596 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1597 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1598 ictx->cstorm_st_context.task_pbl_base.lo =
1599 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1600 ictx->cstorm_st_context.task_pbl_base.hi =
1601 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1602 /* CSTORM and USTORM initialization is different, CSTORM requires
1603 * CQ DB base & not PTE addr */
1604 ictx->cstorm_st_context.cq_db_base.lo =
1605 req1->cq_page_table_addr_lo & PAGE_MASK;
1606 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1607 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1608 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1609 for (i = 0; i < cp->num_cqs; i++) {
1610 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1611 ISCSI_INITIAL_SN;
1612 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1613 ISCSI_INITIAL_SN;
1614 }
1615
1616 ictx->xstorm_ag_context.cdu_reserved =
1617 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1618 ISCSI_CONNECTION_TYPE);
1619 ictx->ustorm_ag_context.cdu_usage =
1620 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1621 ISCSI_CONNECTION_TYPE);
1622 return 0;
1623
1624}
1625
1626static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1627 u32 num, int *work)
1628{
1629 struct iscsi_kwqe_conn_offload1 *req1;
1630 struct iscsi_kwqe_conn_offload2 *req2;
1631 struct cnic_local *cp = dev->cnic_priv;
1632 struct iscsi_kcqe kcqe;
1633 struct kcqe *cqes[1];
1634 u32 l5_cid;
1635 int ret;
1636
1637 if (num < 2) {
1638 *work = num;
1639 return -EINVAL;
1640 }
1641
1642 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1643 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1644 if ((num - 2) < req2->num_additional_wqes) {
1645 *work = num;
1646 return -EINVAL;
1647 }
1648 *work = 2 + req2->num_additional_wqes;;
1649
1650 l5_cid = req1->iscsi_conn_id;
1651 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1652 return -EINVAL;
1653
1654 memset(&kcqe, 0, sizeof(kcqe));
1655 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1656 kcqe.iscsi_conn_id = l5_cid;
1657 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1658
1659 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1660 atomic_dec(&cp->iscsi_conn);
1661 ret = 0;
1662 goto done;
1663 }
1664 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1665 if (ret) {
1666 atomic_dec(&cp->iscsi_conn);
1667 ret = 0;
1668 goto done;
1669 }
1670 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1671 if (ret < 0) {
1672 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1673 atomic_dec(&cp->iscsi_conn);
1674 goto done;
1675 }
1676
1677 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
ceb7e1c7 1678 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
71034ba8
MC		 1679
1680done:
1681 cqes[0] = (struct kcqe *) &kcqe;
1682 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1683 return ret;
1684}
1685
1686
1687static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1688{
1689 struct cnic_local *cp = dev->cnic_priv;
1690 struct iscsi_kwqe_conn_update *req =
1691 (struct iscsi_kwqe_conn_update *) kwqe;
1692 void *data;
1693 union l5cm_specific_data l5_data;
1694 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1695 int ret;
1696
1697 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1698 return -EINVAL;
1699
1700 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1701 if (!data)
1702 return -ENOMEM;
1703
1704 memcpy(data, kwqe, sizeof(struct kwqe));
1705
1706 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1707 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1708 return ret;
1709}
1710
1711static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1712{
1713 struct cnic_local *cp = dev->cnic_priv;
1714 struct iscsi_kwqe_conn_destroy *req =
1715 (struct iscsi_kwqe_conn_destroy *) kwqe;
1716 union l5cm_specific_data l5_data;
1717 u32 l5_cid = req->reserved0;
1718 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1719 int ret = 0;
1720 struct iscsi_kcqe kcqe;
1721 struct kcqe *cqes[1];
523224a3 1722 u32 hw_cid, type;
71034ba8 1723
6e0dda0c 1724 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
71034ba8
MC		 1725 goto skip_cfc_delete;
1726
1727 while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
1728 msleep(250);
1729
1730 init_waitqueue_head(&ctx->waitq);
1731 ctx->wait_cond = 0;
1732 memset(&l5_data, 0, sizeof(l5_data));
523224a3
DK		 1733 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1734 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
1735 & SPE_HDR_CONN_TYPE;
1736 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1737 SPE_HDR_FUNCTION_ID);
1738
1739 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1740 hw_cid, type, &l5_data);
1741
71034ba8
MC		 1742 if (ret == 0)
1743 wait_event(ctx->waitq, ctx->wait_cond);
1744
1745skip_cfc_delete:
1746 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1747
1748 atomic_dec(&cp->iscsi_conn);
1749
1750 memset(&kcqe, 0, sizeof(kcqe));
1751 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1752 kcqe.iscsi_conn_id = l5_cid;
1753 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1754 kcqe.iscsi_conn_context_id = req->context_id;
1755
1756 cqes[0] = (struct kcqe *) &kcqe;
1757 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1758
1759 return ret;
1760}
1761
1762static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1763 struct l4_kwq_connect_req1 *kwqe1,
1764 struct l4_kwq_connect_req3 *kwqe3,
1765 struct l5cm_active_conn_buffer *conn_buf)
1766{
1767 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1768 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1769 &conn_buf->xstorm_conn_buffer;
1770 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1771 &conn_buf->tstorm_conn_buffer;
1772 struct regpair context_addr;
1773 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1774 struct in6_addr src_ip, dst_ip;
1775 int i;
1776 u32 *addrp;
1777
1778 addrp = (u32 *) &conn_addr->local_ip_addr;
1779 for (i = 0; i < 4; i++, addrp++)
1780 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1781
1782 addrp = (u32 *) &conn_addr->remote_ip_addr;
1783 for (i = 0; i < 4; i++, addrp++)
1784 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1785
1786 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1787
1788 xstorm_buf->context_addr.hi = context_addr.hi;
1789 xstorm_buf->context_addr.lo = context_addr.lo;
1790 xstorm_buf->mss = 0xffff;
1791 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1792 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1793 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1794 xstorm_buf->pseudo_header_checksum =
1795 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1796
1797 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1798 tstorm_buf->params |=
1799 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1800 if (kwqe3->ka_timeout) {
1801 tstorm_buf->ka_enable = 1;
1802 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1803 tstorm_buf->ka_interval = kwqe3->ka_interval;
1804 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1805 }
1806 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1807 tstorm_buf->snd_buf = kwqe3->snd_buf;
1808 tstorm_buf->max_rt_time = 0xffffffff;
1809}
1810
1811static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1812{
1813 struct cnic_local *cp = dev->cnic_priv;
1420398d 1814 u32 pfid = cp->pfid;
71034ba8
MC		 1815 u8 *mac = dev->mac_addr;
1816
1817 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1818 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
71034ba8 1819 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1820 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
71034ba8 1821 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1822 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
71034ba8 1823 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1824 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
71034ba8 1825 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1826 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
71034ba8 1827 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1828 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
71034ba8
MC		 1829
1830 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1831 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
71034ba8 1832 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1833 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
71034ba8
MC		 1834 mac[4]);
1835 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1836 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
71034ba8 1837 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1838 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
71034ba8
MC		 1839 mac[2]);
1840 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1841 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
71034ba8
MC		 1842 mac[1]);
1843 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1420398d 1844 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
71034ba8
MC		 1845 mac[0]);
1846}
1847
1848static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1849{
1850 struct cnic_local *cp = dev->cnic_priv;
1851 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1852 u16 tstorm_flags = 0;
1853
1854 if (tcp_ts) {
1855 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1856 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1857 }
1858
1859 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 1860 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
71034ba8
MC		 1861
1862 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1420398d 1863 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
71034ba8
MC		 1864}
1865
1866static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1867 u32 num, int *work)
1868{
1869 struct cnic_local *cp = dev->cnic_priv;
1870 struct l4_kwq_connect_req1 *kwqe1 =
1871 (struct l4_kwq_connect_req1 *) wqes[0];
1872 struct l4_kwq_connect_req3 *kwqe3;
1873 struct l5cm_active_conn_buffer *conn_buf;
1874 struct l5cm_conn_addr_params *conn_addr;
1875 union l5cm_specific_data l5_data;
1876 u32 l5_cid = kwqe1->pg_cid;
1877 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
1878 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1879 int ret;
1880
1881 if (num < 2) {
1882 *work = num;
1883 return -EINVAL;
1884 }
1885
1886 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
1887 *work = 3;
1888 else
1889 *work = 2;
1890
1891 if (num < *work) {
1892 *work = num;
1893 return -EINVAL;
1894 }
1895
1896 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
ddf79b20 1897 netdev_err(dev->netdev, "conn_buf size too big\n");
71034ba8
MC		 1898 return -ENOMEM;
1899 }
1900 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1901 if (!conn_buf)
1902 return -ENOMEM;
1903
1904 memset(conn_buf, 0, sizeof(*conn_buf));
1905
1906 conn_addr = &conn_buf->conn_addr_buf;
1907 conn_addr->remote_addr_0 = csk->ha[0];
1908 conn_addr->remote_addr_1 = csk->ha[1];
1909 conn_addr->remote_addr_2 = csk->ha[2];
1910 conn_addr->remote_addr_3 = csk->ha[3];
1911 conn_addr->remote_addr_4 = csk->ha[4];
1912 conn_addr->remote_addr_5 = csk->ha[5];
1913
1914 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
1915 struct l4_kwq_connect_req2 *kwqe2 =
1916 (struct l4_kwq_connect_req2 *) wqes[1];
1917
1918 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
1919 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
1920 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
1921
1922 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
1923 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
1924 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
1925 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
1926 }
1927 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
1928
1929 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
1930 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
1931 conn_addr->local_tcp_port = kwqe1->src_port;
1932 conn_addr->remote_tcp_port = kwqe1->dst_port;
1933
1934 conn_addr->pmtu = kwqe3->pmtu;
1935 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
1936
1937 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1420398d 1938 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
71034ba8
MC		 1939
1940 cnic_bnx2x_set_tcp_timestamp(dev,
1941 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
1942
1943 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
1944 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1945 if (!ret)
6e0dda0c 1946 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
71034ba8
MC		 1947
1948 return ret;
1949}
1950
1951static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
1952{
1953 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
1954 union l5cm_specific_data l5_data;
1955 int ret;
1956
1957 memset(&l5_data, 0, sizeof(l5_data));
1958 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
1959 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1960 return ret;
1961}
1962
1963static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
1964{
1965 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
1966 union l5cm_specific_data l5_data;
1967 int ret;
1968
1969 memset(&l5_data, 0, sizeof(l5_data));
1970 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
1971 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1972 return ret;
1973}
1974static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1975{
1976 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
1977 struct l4_kcq kcqe;
1978 struct kcqe *cqes[1];
1979
1980 memset(&kcqe, 0, sizeof(kcqe));
1981 kcqe.pg_host_opaque = req->host_opaque;
1982 kcqe.pg_cid = req->host_opaque;
1983 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
1984 cqes[0] = (struct kcqe *) &kcqe;
1985 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
1986 return 0;
1987}
1988
1989static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1990{
1991 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
1992 struct l4_kcq kcqe;
1993 struct kcqe *cqes[1];
1994
1995 memset(&kcqe, 0, sizeof(kcqe));
1996 kcqe.pg_host_opaque = req->pg_host_opaque;
1997 kcqe.pg_cid = req->pg_cid;
1998 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
1999 cqes[0] = (struct kcqe *) &kcqe;
2000 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2001 return 0;
2002}
2003
2004static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2005 u32 num_wqes)
2006{
2007 int i, work, ret;
2008 u32 opcode;
2009 struct kwqe *kwqe;
2010
2011 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2012 return -EAGAIN; /* bnx2 is down */
2013
2014 for (i = 0; i < num_wqes; ) {
2015 kwqe = wqes[i];
2016 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2017 work = 1;
2018
2019 switch (opcode) {
2020 case ISCSI_KWQE_OPCODE_INIT1:
2021 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2022 break;
2023 case ISCSI_KWQE_OPCODE_INIT2:
2024 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2025 break;
2026 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2027 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2028 num_wqes - i, &work);
2029 break;
2030 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2031 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2032 break;
2033 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2034 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2035 break;
2036 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2037 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2038 &work);
2039 break;
2040 case L4_KWQE_OPCODE_VALUE_CLOSE:
2041 ret = cnic_bnx2x_close(dev, kwqe);
2042 break;
2043 case L4_KWQE_OPCODE_VALUE_RESET:
2044 ret = cnic_bnx2x_reset(dev, kwqe);
2045 break;
2046 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2047 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2048 break;
2049 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2050 ret = cnic_bnx2x_update_pg(dev, kwqe);
2051 break;
2052 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2053 ret = 0;
2054 break;
2055 default:
2056 ret = 0;
ddf79b20
JP		 2057 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2058 opcode);
71034ba8
MC		 2059 break;
2060 }
2061 if (ret < 0)
ddf79b20
JP		 2062 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2063 opcode);
71034ba8
MC		 2064 i += work;
2065 }
2066 return 0;
2067}
2068
a4636960
MC		 2069static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2070{
2071 struct cnic_local *cp = dev->cnic_priv;
c2bff63f 2072 int i, j, comp = 0;
a4636960
MC		 2073
2074 i = 0;
2075 j = 1;
2076 while (num_cqes) {
2077 struct cnic_ulp_ops *ulp_ops;
2078 int ulp_type;
2079 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2080 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
2081
2082 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
c2bff63f 2083 comp++;
a4636960
MC		 2084
2085 while (j < num_cqes) {
2086 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2087
2088 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
2089 break;
2090
2091 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
c2bff63f 2092 comp++;
a4636960
MC		 2093 j++;
2094 }
2095
2096 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2097 ulp_type = CNIC_ULP_RDMA;
2098 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2099 ulp_type = CNIC_ULP_ISCSI;
2100 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2101 ulp_type = CNIC_ULP_L4;
2102 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2103 goto end;
2104 else {
ddf79b20
JP		 2105 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2106 kcqe_op_flag);
a4636960
MC		 2107 goto end;
2108 }
2109
2110 rcu_read_lock();
2111 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2112 if (likely(ulp_ops)) {
2113 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2114 cp->completed_kcq + i, j);
2115 }
2116 rcu_read_unlock();
2117end:
2118 num_cqes -= j;
2119 i += j;
2120 j = 1;
2121 }
c2bff63f
DK		 2122 if (unlikely(comp))
2123 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
a4636960
MC		 2124}
2125
71034ba8
MC		 2126static u16 cnic_bnx2_next_idx(u16 idx)
2127{
2128 return idx + 1;
2129}
2130
2131static u16 cnic_bnx2_hw_idx(u16 idx)
2132{
2133 return idx;
2134}
2135
2136static u16 cnic_bnx2x_next_idx(u16 idx)
a4636960 2137{
71034ba8
MC		 2138 idx++;
2139 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2140 idx++;
2141
2142 return idx;
a4636960
MC		 2143}
2144
71034ba8 2145static u16 cnic_bnx2x_hw_idx(u16 idx)
a4636960 2146{
71034ba8
MC		 2147 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2148 idx++;
a4636960
MC		 2149 return idx;
2150}
2151
644b9d4f 2152static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
a4636960
MC		 2153{
2154 struct cnic_local *cp = dev->cnic_priv;
644b9d4f 2155 u16 i, ri, hw_prod, last;
a4636960
MC		 2156 struct kcqe *kcqe;
2157 int kcqe_cnt = 0, last_cnt = 0;
2158
644b9d4f 2159 i = ri = last = info->sw_prod_idx;
a4636960 2160 ri &= MAX_KCQ_IDX;
644b9d4f
MC		 2161 hw_prod = *info->hw_prod_idx_ptr;
2162 hw_prod = cp->hw_idx(hw_prod);
a4636960
MC		 2163
2164 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
644b9d4f 2165 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
a4636960
MC		 2166 cp->completed_kcq[kcqe_cnt++] = kcqe;
2167 i = cp->next_idx(i);
2168 ri = i & MAX_KCQ_IDX;
2169 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2170 last_cnt = kcqe_cnt;
2171 last = i;
2172 }
2173 }
2174
644b9d4f 2175 info->sw_prod_idx = last;
a4636960
MC		 2176 return last_cnt;
2177}
2178
48f753d2
MC		 2179static int cnic_l2_completion(struct cnic_local *cp)
2180{
2181 u16 hw_cons, sw_cons;
2182 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2183 (cp->l2_ring + (2 * BCM_PAGE_SIZE));
2184 u32 cmd;
2185 int comp = 0;
2186
2187 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2188 return 0;
2189
2190 hw_cons = *cp->rx_cons_ptr;
2191 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2192 hw_cons++;
2193
2194 sw_cons = cp->rx_cons;
2195 while (sw_cons != hw_cons) {
2196 u8 cqe_fp_flags;
2197
2198 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2199 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2200 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2201 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2202 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2203 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2204 cmd == RAMROD_CMD_ID_ETH_HALT)
2205 comp++;
2206 }
2207 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2208 }
2209 return comp;
2210}
2211
86b53606 2212static void cnic_chk_pkt_rings(struct cnic_local *cp)
a4636960 2213{
541a7810 2214 u16 rx_cons, tx_cons;
48f753d2 2215 int comp = 0;
a4636960 2216
541a7810 2217 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
66fee9ed
MC		 2218 return;
2219
541a7810
MC		 2220 rx_cons = *cp->rx_cons_ptr;
2221 tx_cons = *cp->tx_cons_ptr;
a4636960 2222 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
48f753d2
MC		 2223 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2224 comp = cnic_l2_completion(cp);
2225
a4636960
MC		 2226 cp->tx_cons = tx_cons;
2227 cp->rx_cons = rx_cons;
71034ba8 2228
a4636960
MC		 2229 uio_event_notify(cp->cnic_uinfo);
2230 }
48f753d2
MC		 2231 if (comp)
2232 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
a4636960
MC		 2233}
2234
b177a5d5 2235static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
a4636960 2236{
a4636960 2237 struct cnic_local *cp = dev->cnic_priv;
b177a5d5 2238 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
a4636960
MC		 2239 int kcqe_cnt;
2240
a4636960
MC		 2241 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2242
644b9d4f 2243 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
a4636960
MC		 2244
2245 service_kcqes(dev, kcqe_cnt);
2246
2247 /* Tell compiler that status_blk fields can change. */
2248 barrier();
644b9d4f 2249 if (status_idx != *cp->kcq1.status_idx_ptr) {
b177a5d5 2250 status_idx = (u16) *cp->kcq1.status_idx_ptr;
a4636960 2251 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
a4636960
MC		 2252 } else
2253 break;
2254 }
2255
644b9d4f 2256 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
a4636960 2257
86b53606 2258 cnic_chk_pkt_rings(cp);
b177a5d5 2259
a4636960
MC		 2260 return status_idx;
2261}
2262
b177a5d5 2263static int cnic_service_bnx2(void *data, void *status_blk)
a4636960 2264{
b177a5d5 2265 struct cnic_dev *dev = data;
a4636960 2266 struct cnic_local *cp = dev->cnic_priv;
644b9d4f 2267 u32 status_idx = *cp->kcq1.status_idx_ptr;
a4636960 2268
b177a5d5
MC		 2269 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2270 return status_idx;
a4636960 2271
b177a5d5
MC		 2272 return cnic_service_bnx2_queues(dev);
2273}
a4636960 2274
b177a5d5
MC		 2275static void cnic_service_bnx2_msix(unsigned long data)
2276{
2277 struct cnic_dev *dev = (struct cnic_dev *) data;
2278 struct cnic_local *cp = dev->cnic_priv;
a4636960 2279
b177a5d5 2280 cp->last_status_idx = cnic_service_bnx2_queues(dev);
a4636960 2281
a4636960
MC		 2282 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2283 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2284}
2285
66fee9ed
MC		 2286static void cnic_doirq(struct cnic_dev *dev)
2287{
2288 struct cnic_local *cp = dev->cnic_priv;
e6c28894 2289 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
66fee9ed
MC		 2290
2291 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2292 prefetch(cp->status_blk.gen);
e6c28894 2293 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
66fee9ed
MC		 2294
2295 tasklet_schedule(&cp->cnic_irq_task);
2296 }
2297}
2298
a4636960
MC		 2299static irqreturn_t cnic_irq(int irq, void *dev_instance)
2300{
2301 struct cnic_dev *dev = dev_instance;
2302 struct cnic_local *cp = dev->cnic_priv;
a4636960
MC		 2303
2304 if (cp->ack_int)
2305 cp->ack_int(dev);
2306
66fee9ed 2307 cnic_doirq(dev);
a4636960
MC		 2308
2309 return IRQ_HANDLED;
2310}
2311
71034ba8
MC		 2312static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2313 u16 index, u8 op, u8 update)
2314{
2315 struct cnic_local *cp = dev->cnic_priv;
2316 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2317 COMMAND_REG_INT_ACK);
2318 struct igu_ack_register igu_ack;
2319
2320 igu_ack.status_block_index = index;
2321 igu_ack.sb_id_and_flags =
2322 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2323 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2324 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2325 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2326
2327 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2328}
2329
2330static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2331{
2332 struct cnic_local *cp = dev->cnic_priv;
2333
523224a3 2334 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
71034ba8
MC		 2335 IGU_INT_DISABLE, 0);
2336}
2337
b177a5d5 2338static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
71034ba8 2339{
b177a5d5 2340 u32 last_status = *info->status_idx_ptr;
71034ba8
MC		 2341 int kcqe_cnt;
2342
b177a5d5 2343 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
71034ba8
MC		 2344
2345 service_kcqes(dev, kcqe_cnt);
2346
2347 /* Tell compiler that sblk fields can change. */
2348 barrier();
b177a5d5 2349 if (last_status == *info->status_idx_ptr)
71034ba8
MC		 2350 break;
2351
b177a5d5 2352 last_status = *info->status_idx_ptr;
71034ba8 2353 }
b177a5d5
MC		 2354 return last_status;
2355}
2356
2357static void cnic_service_bnx2x_bh(unsigned long data)
2358{
2359 struct cnic_dev *dev = (struct cnic_dev *) data;
2360 struct cnic_local *cp = dev->cnic_priv;
2361 u32 status_idx;
2362
2363 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2364 return;
2365
2366 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
71034ba8 2367
644b9d4f 2368 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
523224a3 2369 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
71034ba8 2370 status_idx, IGU_INT_ENABLE, 1);
71034ba8
MC		 2371}
2372
2373static int cnic_service_bnx2x(void *data, void *status_blk)
2374{
2375 struct cnic_dev *dev = data;
2376 struct cnic_local *cp = dev->cnic_priv;
71034ba8 2377
66fee9ed
MC		 2378 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2379 cnic_doirq(dev);
71034ba8 2380
66fee9ed 2381 cnic_chk_pkt_rings(cp);
71034ba8
MC		 2382
2383 return 0;
2384}
2385
a4636960
MC		 2386static void cnic_ulp_stop(struct cnic_dev *dev)
2387{
2388 struct cnic_local *cp = dev->cnic_priv;
2389 int if_type;
2390
6d7760a8
MC		 2391 if (cp->cnic_uinfo)
2392 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2393
a4636960
MC		 2394 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2395 struct cnic_ulp_ops *ulp_ops;
2396
681dbd71
MC		 2397 mutex_lock(&cnic_lock);
2398 ulp_ops = cp->ulp_ops[if_type];
2399 if (!ulp_ops) {
2400 mutex_unlock(&cnic_lock);
a4636960 2401 continue;
681dbd71
MC		 2402 }
2403 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2404 mutex_unlock(&cnic_lock);
a4636960
MC		 2405
2406 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2407 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
681dbd71
MC		 2408
2409 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
a4636960 2410 }
a4636960
MC		 2411}
2412
2413static void cnic_ulp_start(struct cnic_dev *dev)
2414{
2415 struct cnic_local *cp = dev->cnic_priv;
2416 int if_type;
2417
a4636960
MC		 2418 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2419 struct cnic_ulp_ops *ulp_ops;
2420
681dbd71
MC		 2421 mutex_lock(&cnic_lock);
2422 ulp_ops = cp->ulp_ops[if_type];
2423 if (!ulp_ops || !ulp_ops->cnic_start) {
2424 mutex_unlock(&cnic_lock);
a4636960 2425 continue;
681dbd71
MC		 2426 }
2427 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2428 mutex_unlock(&cnic_lock);
a4636960
MC		 2429
2430 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2431 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
681dbd71
MC		 2432
2433 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
a4636960 2434 }
a4636960
MC		 2435}
2436
2437static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2438{
2439 struct cnic_dev *dev = data;
2440
2441 switch (info->cmd) {
2442 case CNIC_CTL_STOP_CMD:
2443 cnic_hold(dev);
a4636960
MC		 2444
2445 cnic_ulp_stop(dev);
2446 cnic_stop_hw(dev);
2447
a4636960
MC		 2448 cnic_put(dev);
2449 break;
2450 case CNIC_CTL_START_CMD:
2451 cnic_hold(dev);
a4636960
MC		 2452
2453 if (!cnic_start_hw(dev))
2454 cnic_ulp_start(dev);
2455
a4636960
MC		 2456 cnic_put(dev);
2457 break;
71034ba8
MC		 2458 case CNIC_CTL_COMPLETION_CMD: {
2459 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
2460 u32 l5_cid;
2461 struct cnic_local *cp = dev->cnic_priv;
2462
2463 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
2464 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2465
2466 ctx->wait_cond = 1;
2467 wake_up(&ctx->waitq);
2468 }
2469 break;
2470 }
a4636960
MC		 2471 default:
2472 return -EINVAL;
2473 }
2474 return 0;
2475}
2476
2477static void cnic_ulp_init(struct cnic_dev *dev)
2478{
2479 int i;
2480 struct cnic_local *cp = dev->cnic_priv;
2481
a4636960
MC		 2482 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2483 struct cnic_ulp_ops *ulp_ops;
2484
7fc1ece4
MC		 2485 mutex_lock(&cnic_lock);
2486 ulp_ops = cnic_ulp_tbl[i];
2487 if (!ulp_ops || !ulp_ops->cnic_init) {
2488 mutex_unlock(&cnic_lock);
a4636960 2489 continue;
7fc1ece4
MC		 2490 }
2491 ulp_get(ulp_ops);
2492 mutex_unlock(&cnic_lock);
a4636960
MC		 2493
2494 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2495 ulp_ops->cnic_init(dev);
2496
7fc1ece4 2497 ulp_put(ulp_ops);
a4636960 2498 }
a4636960
MC		 2499}
2500
2501static void cnic_ulp_exit(struct cnic_dev *dev)
2502{
2503 int i;
2504 struct cnic_local *cp = dev->cnic_priv;
2505
a4636960
MC		 2506 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2507 struct cnic_ulp_ops *ulp_ops;
2508
7fc1ece4
MC		 2509 mutex_lock(&cnic_lock);
2510 ulp_ops = cnic_ulp_tbl[i];
2511 if (!ulp_ops || !ulp_ops->cnic_exit) {
2512 mutex_unlock(&cnic_lock);
a4636960 2513 continue;
7fc1ece4
MC		 2514 }
2515 ulp_get(ulp_ops);
2516 mutex_unlock(&cnic_lock);
a4636960
MC		 2517
2518 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2519 ulp_ops->cnic_exit(dev);
2520
7fc1ece4 2521 ulp_put(ulp_ops);
a4636960 2522 }
a4636960
MC		 2523}
2524
2525static int cnic_cm_offload_pg(struct cnic_sock *csk)
2526{
2527 struct cnic_dev *dev = csk->dev;
2528 struct l4_kwq_offload_pg *l4kwqe;
2529 struct kwqe *wqes[1];
2530
2531 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
2532 memset(l4kwqe, 0, sizeof(*l4kwqe));
2533 wqes[0] = (struct kwqe *) l4kwqe;
2534
2535 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
2536 l4kwqe->flags =
2537 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
2538 l4kwqe->l2hdr_nbytes = ETH_HLEN;
2539
2540 l4kwqe->da0 = csk->ha[0];
2541 l4kwqe->da1 = csk->ha[1];
2542 l4kwqe->da2 = csk->ha[2];
2543 l4kwqe->da3 = csk->ha[3];
2544 l4kwqe->da4 = csk->ha[4];
2545 l4kwqe->da5 = csk->ha[5];
2546
2547 l4kwqe->sa0 = dev->mac_addr[0];
2548 l4kwqe->sa1 = dev->mac_addr[1];
2549 l4kwqe->sa2 = dev->mac_addr[2];
2550 l4kwqe->sa3 = dev->mac_addr[3];
2551 l4kwqe->sa4 = dev->mac_addr[4];
2552 l4kwqe->sa5 = dev->mac_addr[5];
2553
2554 l4kwqe->etype = ETH_P_IP;
a9736c08 2555 l4kwqe->ipid_start = DEF_IPID_START;
a4636960
MC		 2556 l4kwqe->host_opaque = csk->l5_cid;
2557
2558 if (csk->vlan_id) {
2559 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
2560 l4kwqe->vlan_tag = csk->vlan_id;
2561 l4kwqe->l2hdr_nbytes += 4;
2562 }
2563
2564 return dev->submit_kwqes(dev, wqes, 1);
2565}
2566
2567static int cnic_cm_update_pg(struct cnic_sock *csk)
2568{
2569 struct cnic_dev *dev = csk->dev;
2570 struct l4_kwq_update_pg *l4kwqe;
2571 struct kwqe *wqes[1];
2572
2573 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
2574 memset(l4kwqe, 0, sizeof(*l4kwqe));
2575 wqes[0] = (struct kwqe *) l4kwqe;
2576
2577 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
2578 l4kwqe->flags =
2579 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
2580 l4kwqe->pg_cid = csk->pg_cid;
2581
2582 l4kwqe->da0 = csk->ha[0];
2583 l4kwqe->da1 = csk->ha[1];
2584 l4kwqe->da2 = csk->ha[2];
2585 l4kwqe->da3 = csk->ha[3];
2586 l4kwqe->da4 = csk->ha[4];
2587 l4kwqe->da5 = csk->ha[5];
2588
2589 l4kwqe->pg_host_opaque = csk->l5_cid;
2590 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
2591
2592 return dev->submit_kwqes(dev, wqes, 1);
2593}
2594
2595static int cnic_cm_upload_pg(struct cnic_sock *csk)
2596{
2597 struct cnic_dev *dev = csk->dev;
2598 struct l4_kwq_upload *l4kwqe;
2599 struct kwqe *wqes[1];
2600
2601 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
2602 memset(l4kwqe, 0, sizeof(*l4kwqe));
2603 wqes[0] = (struct kwqe *) l4kwqe;
2604
2605 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
2606 l4kwqe->flags =
2607 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
2608 l4kwqe->cid = csk->pg_cid;
2609
2610 return dev->submit_kwqes(dev, wqes, 1);
2611}
2612
2613static int cnic_cm_conn_req(struct cnic_sock *csk)
2614{
2615 struct cnic_dev *dev = csk->dev;
2616 struct l4_kwq_connect_req1 *l4kwqe1;
2617 struct l4_kwq_connect_req2 *l4kwqe2;
2618 struct l4_kwq_connect_req3 *l4kwqe3;
2619 struct kwqe *wqes[3];
2620 u8 tcp_flags = 0;
2621 int num_wqes = 2;
2622
2623 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
2624 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
2625 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
2626 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
2627 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
2628 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
2629
2630 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
2631 l4kwqe3->flags =
2632 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
2633 l4kwqe3->ka_timeout = csk->ka_timeout;
2634 l4kwqe3->ka_interval = csk->ka_interval;
2635 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
2636 l4kwqe3->tos = csk->tos;
2637 l4kwqe3->ttl = csk->ttl;
2638 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
2639 l4kwqe3->pmtu = csk->mtu;
2640 l4kwqe3->rcv_buf = csk->rcv_buf;
2641 l4kwqe3->snd_buf = csk->snd_buf;
2642 l4kwqe3->seed = csk->seed;
2643
2644 wqes[0] = (struct kwqe *) l4kwqe1;
2645 if (test_bit(SK_F_IPV6, &csk->flags)) {
2646 wqes[1] = (struct kwqe *) l4kwqe2;
2647 wqes[2] = (struct kwqe *) l4kwqe3;
2648 num_wqes = 3;
2649
2650 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
2651 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
2652 l4kwqe2->flags =
2653 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
2654 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
2655 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
2656 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
2657 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
2658 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
2659 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
2660 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
2661 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
2662 sizeof(struct tcphdr);
2663 } else {
2664 wqes[1] = (struct kwqe *) l4kwqe3;
2665 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
2666 sizeof(struct tcphdr);
2667 }
2668
2669 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
2670 l4kwqe1->flags =
2671 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
2672 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
2673 l4kwqe1->cid = csk->cid;
2674 l4kwqe1->pg_cid = csk->pg_cid;
2675 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
2676 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
2677 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
2678 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
2679 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
2680 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
2681 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
2682 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
2683 if (csk->tcp_flags & SK_TCP_NAGLE)
2684 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
2685 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
2686 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
2687 if (csk->tcp_flags & SK_TCP_SACK)
2688 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
2689 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
2690 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
2691
2692 l4kwqe1->tcp_flags = tcp_flags;
2693
2694 return dev->submit_kwqes(dev, wqes, num_wqes);
2695}
2696
2697static int cnic_cm_close_req(struct cnic_sock *csk)
2698{
2699 struct cnic_dev *dev = csk->dev;
2700 struct l4_kwq_close_req *l4kwqe;
2701 struct kwqe *wqes[1];
2702
2703 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
2704 memset(l4kwqe, 0, sizeof(*l4kwqe));
2705 wqes[0] = (struct kwqe *) l4kwqe;
2706
2707 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
2708 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
2709 l4kwqe->cid = csk->cid;
2710
2711 return dev->submit_kwqes(dev, wqes, 1);
2712}
2713
2714static int cnic_cm_abort_req(struct cnic_sock *csk)
2715{
2716 struct cnic_dev *dev = csk->dev;
2717 struct l4_kwq_reset_req *l4kwqe;
2718 struct kwqe *wqes[1];
2719
2720 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
2721 memset(l4kwqe, 0, sizeof(*l4kwqe));
2722 wqes[0] = (struct kwqe *) l4kwqe;
2723
2724 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
2725 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
2726 l4kwqe->cid = csk->cid;
2727
2728 return dev->submit_kwqes(dev, wqes, 1);
2729}
2730
2731static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
2732 u32 l5_cid, struct cnic_sock **csk, void *context)
2733{
2734 struct cnic_local *cp = dev->cnic_priv;
2735 struct cnic_sock *csk1;
2736
2737 if (l5_cid >= MAX_CM_SK_TBL_SZ)
2738 return -EINVAL;
2739
2740 csk1 = &cp->csk_tbl[l5_cid];
2741 if (atomic_read(&csk1->ref_count))
2742 return -EAGAIN;
2743
2744 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
2745 return -EBUSY;
2746
2747 csk1->dev = dev;
2748 csk1->cid = cid;
2749 csk1->l5_cid = l5_cid;
2750 csk1->ulp_type = ulp_type;
2751 csk1->context = context;
2752
2753 csk1->ka_timeout = DEF_KA_TIMEOUT;
2754 csk1->ka_interval = DEF_KA_INTERVAL;
2755 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
2756 csk1->tos = DEF_TOS;
2757 csk1->ttl = DEF_TTL;
2758 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
2759 csk1->rcv_buf = DEF_RCV_BUF;
2760 csk1->snd_buf = DEF_SND_BUF;
2761 csk1->seed = DEF_SEED;
2762
2763 *csk = csk1;
2764 return 0;
2765}
2766
2767static void cnic_cm_cleanup(struct cnic_sock *csk)
2768{
2769 if (csk->src_port) {
2770 struct cnic_dev *dev = csk->dev;
2771 struct cnic_local *cp = dev->cnic_priv;
2772
2773 cnic_free_id(&cp->csk_port_tbl, csk->src_port);
2774 csk->src_port = 0;
2775 }
2776}
2777
2778static void cnic_close_conn(struct cnic_sock *csk)
2779{
2780 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
2781 cnic_cm_upload_pg(csk);
2782 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
2783 }
2784 cnic_cm_cleanup(csk);
2785}
2786
2787static int cnic_cm_destroy(struct cnic_sock *csk)
2788{
2789 if (!cnic_in_use(csk))
2790 return -EINVAL;
2791
2792 csk_hold(csk);
2793 clear_bit(SK_F_INUSE, &csk->flags);
2794 smp_mb__after_clear_bit();
2795 while (atomic_read(&csk->ref_count) != 1)
2796 msleep(1);
2797 cnic_cm_cleanup(csk);
2798
2799 csk->flags = 0;
2800 csk_put(csk);
2801 return 0;
2802}
2803
2804static inline u16 cnic_get_vlan(struct net_device *dev,
2805 struct net_device **vlan_dev)
2806{
2807 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2808 *vlan_dev = vlan_dev_real_dev(dev);
2809 return vlan_dev_vlan_id(dev);
2810 }
2811 *vlan_dev = dev;
2812 return 0;
2813}
2814
2815static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
2816 struct dst_entry **dst)
2817{
faea56c9 2818#if defined(CONFIG_INET)
a4636960
MC		 2819 struct flowi fl;
2820 int err;
2821 struct rtable *rt;
2822
2823 memset(&fl, 0, sizeof(fl));
2824 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
2825
2826 err = ip_route_output_key(&init_net, &rt, &fl);
2827 if (!err)
d8d1f30b 2828 *dst = &rt->dst;
a4636960 2829 return err;
faea56c9
RD		 2830#else
2831 return -ENETUNREACH;
2832#endif
a4636960
MC		 2833}
2834
2835static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
2836 struct dst_entry **dst)
2837{
faea56c9 2838#if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
a4636960
MC		 2839 struct flowi fl;
2840
2841 memset(&fl, 0, sizeof(fl));
2842 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
2843 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
2844 fl.oif = dst_addr->sin6_scope_id;
2845
2846 *dst = ip6_route_output(&init_net, NULL, &fl);
2847 if (*dst)
2848 return 0;
2849#endif
2850
2851 return -ENETUNREACH;
2852}
2853
2854static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
2855 int ulp_type)
2856{
2857 struct cnic_dev *dev = NULL;
2858 struct dst_entry *dst;
2859 struct net_device *netdev = NULL;
2860 int err = -ENETUNREACH;
2861
2862 if (dst_addr->sin_family == AF_INET)
2863 err = cnic_get_v4_route(dst_addr, &dst);
2864 else if (dst_addr->sin_family == AF_INET6) {
2865 struct sockaddr_in6 *dst_addr6 =
2866 (struct sockaddr_in6 *) dst_addr;
2867
2868 err = cnic_get_v6_route(dst_addr6, &dst);
2869 } else
2870 return NULL;
2871
2872 if (err)
2873 return NULL;
2874
2875 if (!dst->dev)
2876 goto done;
2877
2878 cnic_get_vlan(dst->dev, &netdev);
2879
2880 dev = cnic_from_netdev(netdev);
2881
2882done:
2883 dst_release(dst);
2884 if (dev)
2885 cnic_put(dev);
2886 return dev;
2887}
2888
2889static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2890{
2891 struct cnic_dev *dev = csk->dev;
2892 struct cnic_local *cp = dev->cnic_priv;
2893
2894 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
2895}
2896
2897static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2898{
2899 struct cnic_dev *dev = csk->dev;
2900 struct cnic_local *cp = dev->cnic_priv;
c76284af
MC		 2901 int is_v6, rc = 0;
2902 struct dst_entry *dst = NULL;
a4636960
MC		 2903 struct net_device *realdev;
2904 u32 local_port;
2905
2906 if (saddr->local.v6.sin6_family == AF_INET6 &&
2907 saddr->remote.v6.sin6_family == AF_INET6)
2908 is_v6 = 1;
2909 else if (saddr->local.v4.sin_family == AF_INET &&
2910 saddr->remote.v4.sin_family == AF_INET)
2911 is_v6 = 0;
2912 else
2913 return -EINVAL;
2914
2915 clear_bit(SK_F_IPV6, &csk->flags);
2916
2917 if (is_v6) {
a4636960 2918 set_bit(SK_F_IPV6, &csk->flags);
c76284af 2919 cnic_get_v6_route(&saddr->remote.v6, &dst);
a4636960
MC		 2920
2921 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
2922 sizeof(struct in6_addr));
2923 csk->dst_port = saddr->remote.v6.sin6_port;
2924 local_port = saddr->local.v6.sin6_port;
a4636960
MC		 2925
2926 } else {
c76284af 2927 cnic_get_v4_route(&saddr->remote.v4, &dst);
a4636960
MC		 2928
2929 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
2930 csk->dst_port = saddr->remote.v4.sin_port;
2931 local_port = saddr->local.v4.sin_port;
2932 }
2933
c76284af
MC		 2934 csk->vlan_id = 0;
2935 csk->mtu = dev->netdev->mtu;
2936 if (dst && dst->dev) {
2937 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
2938 if (realdev == dev->netdev) {
2939 csk->vlan_id = vlan;
2940 csk->mtu = dst_mtu(dst);
2941 }
2942 }
a4636960
MC		 2943
2944 if (local_port >= CNIC_LOCAL_PORT_MIN &&
2945 local_port < CNIC_LOCAL_PORT_MAX) {
2946 if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
2947 local_port = 0;
2948 } else
2949 local_port = 0;
2950
2951 if (!local_port) {
2952 local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
2953 if (local_port == -1) {
2954 rc = -ENOMEM;
2955 goto err_out;
2956 }
2957 }
2958 csk->src_port = local_port;
2959
a4636960
MC		 2960err_out:
2961 dst_release(dst);
2962 return rc;
2963}
2964
2965static void cnic_init_csk_state(struct cnic_sock *csk)
2966{
2967 csk->state = 0;
2968 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
2969 clear_bit(SK_F_CLOSING, &csk->flags);
2970}
2971
2972static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2973{
2974 int err = 0;
2975
2976 if (!cnic_in_use(csk))
2977 return -EINVAL;
2978
2979 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
2980 return -EINVAL;
2981
2982 cnic_init_csk_state(csk);
2983
2984 err = cnic_get_route(csk, saddr);
2985 if (err)
2986 goto err_out;
2987
2988 err = cnic_resolve_addr(csk, saddr);
2989 if (!err)
2990 return 0;
2991
2992err_out:
2993 clear_bit(SK_F_CONNECT_START, &csk->flags);
2994 return err;
2995}
2996
2997static int cnic_cm_abort(struct cnic_sock *csk)
2998{
2999 struct cnic_local *cp = csk->dev->cnic_priv;
7b34a464 3000 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
a4636960
MC		 3001
3002 if (!cnic_in_use(csk))
3003 return -EINVAL;
3004
3005 if (cnic_abort_prep(csk))
3006 return cnic_cm_abort_req(csk);
3007
3008 /* Getting here means that we haven't started connect, or
3009 * connect was not successful.
3010 */
3011
a4636960 3012 cp->close_conn(csk, opcode);
7b34a464
MC		 3013 if (csk->state != opcode)
3014 return -EALREADY;
a4636960
MC		 3015
3016 return 0;
3017}
3018
3019static int cnic_cm_close(struct cnic_sock *csk)
3020{
3021 if (!cnic_in_use(csk))
3022 return -EINVAL;
3023
3024 if (cnic_close_prep(csk)) {
3025 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3026 return cnic_cm_close_req(csk);
ed99daa5
MC		 3027 } else {
3028 return -EALREADY;
a4636960
MC		 3029 }
3030 return 0;
3031}
3032
3033static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3034 u8 opcode)
3035{
3036 struct cnic_ulp_ops *ulp_ops;
3037 int ulp_type = csk->ulp_type;
3038
3039 rcu_read_lock();
3040 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3041 if (ulp_ops) {
3042 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3043 ulp_ops->cm_connect_complete(csk);
3044 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3045 ulp_ops->cm_close_complete(csk);
3046 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3047 ulp_ops->cm_remote_abort(csk);
3048 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3049 ulp_ops->cm_abort_complete(csk);
3050 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3051 ulp_ops->cm_remote_close(csk);
3052 }
3053 rcu_read_unlock();
3054}
3055
3056static int cnic_cm_set_pg(struct cnic_sock *csk)
3057{
3058 if (cnic_offld_prep(csk)) {
3059 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3060 cnic_cm_update_pg(csk);
3061 else
3062 cnic_cm_offload_pg(csk);
3063 }
3064 return 0;
3065}
3066
3067static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3068{
3069 struct cnic_local *cp = dev->cnic_priv;
3070 u32 l5_cid = kcqe->pg_host_opaque;
3071 u8 opcode = kcqe->op_code;
3072 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3073
3074 csk_hold(csk);
3075 if (!cnic_in_use(csk))
3076 goto done;
3077
3078 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3079 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3080 goto done;
3081 }
a9736c08
EW		 3082 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3083 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3084 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3085 cnic_cm_upcall(cp, csk,
3086 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3087 goto done;
3088 }
3089
a4636960
MC		 3090 csk->pg_cid = kcqe->pg_cid;
3091 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3092 cnic_cm_conn_req(csk);
3093
3094done:
3095 csk_put(csk);
3096}
3097
3098static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3099{
3100 struct cnic_local *cp = dev->cnic_priv;
3101 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3102 u8 opcode = l4kcqe->op_code;
3103 u32 l5_cid;
3104 struct cnic_sock *csk;
3105
3106 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3107 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3108 cnic_cm_process_offld_pg(dev, l4kcqe);
3109 return;
3110 }
3111
3112 l5_cid = l4kcqe->conn_id;
3113 if (opcode & 0x80)
3114 l5_cid = l4kcqe->cid;
3115 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3116 return;
3117
3118 csk = &cp->csk_tbl[l5_cid];
3119 csk_hold(csk);
3120
3121 if (!cnic_in_use(csk)) {
3122 csk_put(csk);
3123 return;
3124 }
3125
3126 switch (opcode) {
a9736c08
EW		 3127 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3128 if (l4kcqe->status != 0) {
3129 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3130 cnic_cm_upcall(cp, csk,
3131 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3132 }
3133 break;
a4636960
MC		 3134 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3135 if (l4kcqe->status == 0)
3136 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3137
3138 smp_mb__before_clear_bit();
3139 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3140 cnic_cm_upcall(cp, csk, opcode);
3141 break;
3142
3143 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
a4636960
MC		 3144 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3145 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
71034ba8
MC		 3146 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3147 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
a4636960
MC		 3148 cp->close_conn(csk, opcode);
3149 break;
3150
3151 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3152 cnic_cm_upcall(cp, csk, opcode);
3153 break;
3154 }
3155 csk_put(csk);
3156}
3157
3158static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3159{
3160 struct cnic_dev *dev = data;
3161 int i;
3162
3163 for (i = 0; i < num; i++)
3164 cnic_cm_process_kcqe(dev, kcqe[i]);
3165}
3166
3167static struct cnic_ulp_ops cm_ulp_ops = {
3168 .indicate_kcqes = cnic_cm_indicate_kcqe,
3169};
3170
3171static void cnic_cm_free_mem(struct cnic_dev *dev)
3172{
3173 struct cnic_local *cp = dev->cnic_priv;
3174
3175 kfree(cp->csk_tbl);
3176 cp->csk_tbl = NULL;
3177 cnic_free_id_tbl(&cp->csk_port_tbl);
3178}
3179
3180static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3181{
3182 struct cnic_local *cp = dev->cnic_priv;
3183
3184 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3185 GFP_KERNEL);
3186 if (!cp->csk_tbl)
3187 return -ENOMEM;
3188
3189 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3190 CNIC_LOCAL_PORT_MIN)) {
3191 cnic_cm_free_mem(dev);
3192 return -ENOMEM;
3193 }
3194 return 0;
3195}
3196
3197static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3198{
943189f1
MC		 3199 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3200 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3201 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3202 csk->state = opcode;
a4636960 3203 }
943189f1
MC		 3204
3205 /* 1. If event opcode matches the expected event in csk->state
3206 * 2. If the expected event is CLOSE_COMP, we accept any event
7b34a464
MC		 3207 * 3. If the expected event is 0, meaning the connection was never
3208 * never established, we accept the opcode from cm_abort.
66883e90 3209 */
7b34a464
MC		 3210 if (opcode == csk->state || csk->state == 0 ||
3211 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3212 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3213 if (csk->state == 0)
3214 csk->state = opcode;
66883e90 3215 return 1;
7b34a464 3216 }
66883e90 3217 }
a4636960
MC		 3218 return 0;
3219}
3220
3221static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3222{
3223 struct cnic_dev *dev = csk->dev;
3224 struct cnic_local *cp = dev->cnic_priv;
3225
a1e621bf
MC		 3226 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3227 cnic_cm_upcall(cp, csk, opcode);
3228 return;
3229 }
3230
a4636960 3231 clear_bit(SK_F_CONNECT_START, &csk->flags);
66883e90 3232 cnic_close_conn(csk);
7b34a464 3233 csk->state = opcode;
66883e90 3234 cnic_cm_upcall(cp, csk, opcode);
a4636960
MC		 3235}
3236
3237static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3238{
3239}
3240
3241static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3242{
3243 u32 seed;
3244
3245 get_random_bytes(&seed, 4);
3246 cnic_ctx_wr(dev, 45, 0, seed);
3247 return 0;
3248}
3249
71034ba8
MC		 3250static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3251{
3252 struct cnic_dev *dev = csk->dev;
3253 struct cnic_local *cp = dev->cnic_priv;
3254 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3255 union l5cm_specific_data l5_data;
3256 u32 cmd = 0;
3257 int close_complete = 0;
3258
3259 switch (opcode) {
3260 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3261 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3262 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
7b34a464
MC		 3263 if (cnic_ready_to_close(csk, opcode)) {
3264 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3265 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3266 else
3267 close_complete = 1;
3268 }
71034ba8
MC		 3269 break;
3270 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3271 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3272 break;
3273 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3274 close_complete = 1;
3275 break;
3276 }
3277 if (cmd) {
3278 memset(&l5_data, 0, sizeof(l5_data));
3279
3280 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3281 &l5_data);
3282 } else if (close_complete) {
3283 ctx->timestamp = jiffies;
3284 cnic_close_conn(csk);
3285 cnic_cm_upcall(cp, csk, csk->state);
3286 }
3287}
3288
3289static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3290{
3291}
3292
3293static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3294{
3295 struct cnic_local *cp = dev->cnic_priv;
1420398d 3296 u32 pfid = cp->pfid;
523224a3 3297 u32 port = CNIC_PORT(cp);
71034ba8
MC		 3298
3299 cnic_init_bnx2x_mac(dev);
3300 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3301
3302 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1420398d 3303 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
71034ba8
MC		 3304
3305 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
523224a3 3306 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
71034ba8 3307 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
523224a3 3308 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
71034ba8
MC		 3309 DEF_MAX_DA_COUNT);
3310
3311 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 3312 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
71034ba8 3313 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 3314 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
71034ba8 3315 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1420398d 3316 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
71034ba8 3317 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
1420398d 3318 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
71034ba8 3319
1420398d 3320 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
71034ba8
MC		 3321 DEF_MAX_CWND);
3322 return 0;
3323}
3324
a4636960
MC		 3325static int cnic_cm_open(struct cnic_dev *dev)
3326{
3327 struct cnic_local *cp = dev->cnic_priv;
3328 int err;
3329
3330 err = cnic_cm_alloc_mem(dev);
3331 if (err)
3332 return err;
3333
3334 err = cp->start_cm(dev);
3335
3336 if (err)
3337 goto err_out;
3338
3339 dev->cm_create = cnic_cm_create;
3340 dev->cm_destroy = cnic_cm_destroy;
3341 dev->cm_connect = cnic_cm_connect;
3342 dev->cm_abort = cnic_cm_abort;
3343 dev->cm_close = cnic_cm_close;
3344 dev->cm_select_dev = cnic_cm_select_dev;
3345
3346 cp->ulp_handle[CNIC_ULP_L4] = dev;
3347 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3348 return 0;
3349
3350err_out:
3351 cnic_cm_free_mem(dev);
3352 return err;
3353}
3354
3355static int cnic_cm_shutdown(struct cnic_dev *dev)
3356{
3357 struct cnic_local *cp = dev->cnic_priv;
3358 int i;
3359
3360 cp->stop_cm(dev);
3361
3362 if (!cp->csk_tbl)
3363 return 0;
3364
3365 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
3366 struct cnic_sock *csk = &cp->csk_tbl[i];
3367
3368 clear_bit(SK_F_INUSE, &csk->flags);
3369 cnic_cm_cleanup(csk);
3370 }
3371 cnic_cm_free_mem(dev);
3372
3373 return 0;
3374}
3375
3376static void cnic_init_context(struct cnic_dev *dev, u32 cid)
3377{
a4636960
MC		 3378 u32 cid_addr;
3379 int i;
3380
a4636960
MC		 3381 cid_addr = GET_CID_ADDR(cid);
3382
3383 for (i = 0; i < CTX_SIZE; i += 4)
3384 cnic_ctx_wr(dev, cid_addr, i, 0);
3385}
3386
3387static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
3388{
3389 struct cnic_local *cp = dev->cnic_priv;
3390 int ret = 0, i;
3391 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
3392
3393 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3394 return 0;
3395
3396 for (i = 0; i < cp->ctx_blks; i++) {
3397 int j;
3398 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
3399 u32 val;
3400
3401 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
3402
3403 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
3404 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
3405 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
3406 (u64) cp->ctx_arr[i].mapping >> 32);
3407 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
3408 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3409 for (j = 0; j < 10; j++) {
3410
3411 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3412 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
3413 break;
3414 udelay(5);
3415 }
3416 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
3417 ret = -EBUSY;
3418 break;
3419 }
3420 }
3421 return ret;
3422}
3423
3424static void cnic_free_irq(struct cnic_dev *dev)
3425{
3426 struct cnic_local *cp = dev->cnic_priv;
3427 struct cnic_eth_dev *ethdev = cp->ethdev;
3428
3429 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3430 cp->disable_int_sync(dev);
6e0dc643 3431 tasklet_kill(&cp->cnic_irq_task);
a4636960
MC		 3432 free_irq(ethdev->irq_arr[0].vector, dev);
3433 }
3434}
3435
6e0dc643
MC		 3436static int cnic_request_irq(struct cnic_dev *dev)
3437{
3438 struct cnic_local *cp = dev->cnic_priv;
3439 struct cnic_eth_dev *ethdev = cp->ethdev;
3440 int err;
3441
3442 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
3443 if (err)
3444 tasklet_disable(&cp->cnic_irq_task);
3445
3446 return err;
3447}
3448
a4636960
MC		 3449static int cnic_init_bnx2_irq(struct cnic_dev *dev)
3450{
3451 struct cnic_local *cp = dev->cnic_priv;
3452 struct cnic_eth_dev *ethdev = cp->ethdev;
3453
3454 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3455 int err, i = 0;
3456 int sblk_num = cp->status_blk_num;
3457 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
3458 BNX2_HC_SB_CONFIG_1;
3459
3460 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
3461
3462 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
3463 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
3464 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
3465
a4dde3ab 3466 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
164165da 3467 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
a4636960 3468 (unsigned long) dev);
6e0dc643
MC		 3469 err = cnic_request_irq(dev);
3470 if (err)
a4636960 3471 return err;
6e0dc643 3472
a4dde3ab 3473 while (cp->status_blk.bnx2->status_completion_producer_index &&
a4636960
MC		 3474 i < 10) {
3475 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
3476 1 << (11 + sblk_num));
3477 udelay(10);
3478 i++;
3479 barrier();
3480 }
a4dde3ab 3481 if (cp->status_blk.bnx2->status_completion_producer_index) {
a4636960
MC		 3482 cnic_free_irq(dev);
3483 goto failed;
3484 }
3485
3486 } else {
a4dde3ab 3487 struct status_block *sblk = cp->status_blk.gen;
a4636960
MC		 3488 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
3489 int i = 0;
3490
3491 while (sblk->status_completion_producer_index && i < 10) {
3492 CNIC_WR(dev, BNX2_HC_COMMAND,
3493 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3494 udelay(10);
3495 i++;
3496 barrier();
3497 }
3498 if (sblk->status_completion_producer_index)
3499 goto failed;
3500
3501 }
3502 return 0;
3503
3504failed:
ddf79b20 3505 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
a4636960
MC		 3506 return -EBUSY;
3507}
3508
3509static void cnic_enable_bnx2_int(struct cnic_dev *dev)
3510{
3511 struct cnic_local *cp = dev->cnic_priv;
3512 struct cnic_eth_dev *ethdev = cp->ethdev;
3513
3514 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3515 return;
3516
3517 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3519}
3520
3521static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
3522{
3523 struct cnic_local *cp = dev->cnic_priv;
3524 struct cnic_eth_dev *ethdev = cp->ethdev;
3525
3526 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3527 return;
3528
3529 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3530 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3531 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
3532 synchronize_irq(ethdev->irq_arr[0].vector);
3533}
3534
3535static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
3536{
3537 struct cnic_local *cp = dev->cnic_priv;
3538 struct cnic_eth_dev *ethdev = cp->ethdev;
3539 u32 cid_addr, tx_cid, sb_id;
3540 u32 val, offset0, offset1, offset2, offset3;
3541 int i;
3542 struct tx_bd *txbd;
3543 dma_addr_t buf_map;
a4dde3ab 3544 struct status_block *s_blk = cp->status_blk.gen;
a4636960
MC		 3545
3546 sb_id = cp->status_blk_num;
3547 tx_cid = 20;
a4636960
MC		 3548 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
3549 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
a4dde3ab 3550 struct status_block_msix *sblk = cp->status_blk.bnx2;
a4636960
MC		 3551
3552 tx_cid = TX_TSS_CID + sb_id - 1;
a4636960
MC		 3553 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
3554 (TX_TSS_CID << 7));
3555 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
3556 }
3557 cp->tx_cons = *cp->tx_cons_ptr;
3558
3559 cid_addr = GET_CID_ADDR(tx_cid);
3560 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
3561 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
3562
3563 for (i = 0; i < PHY_CTX_SIZE; i += 4)
3564 cnic_ctx_wr(dev, cid_addr2, i, 0);
3565
3566 offset0 = BNX2_L2CTX_TYPE_XI;
3567 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3568 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3569 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3570 } else {
b58ffb41
MC		 3571 cnic_init_context(dev, tx_cid);
3572 cnic_init_context(dev, tx_cid + 1);
3573
a4636960
MC		 3574 offset0 = BNX2_L2CTX_TYPE;
3575 offset1 = BNX2_L2CTX_CMD_TYPE;
3576 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3577 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3578 }
3579 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3580 cnic_ctx_wr(dev, cid_addr, offset0, val);
3581
3582 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3583 cnic_ctx_wr(dev, cid_addr, offset1, val);
3584
3585 txbd = (struct tx_bd *) cp->l2_ring;
3586
3587 buf_map = cp->l2_buf_map;
3588 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
3589 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
3590 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3591 }
3592 val = (u64) cp->l2_ring_map >> 32;
3593 cnic_ctx_wr(dev, cid_addr, offset2, val);
3594 txbd->tx_bd_haddr_hi = val;
3595
3596 val = (u64) cp->l2_ring_map & 0xffffffff;
3597 cnic_ctx_wr(dev, cid_addr, offset3, val);
3598 txbd->tx_bd_haddr_lo = val;
3599}
3600
3601static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
3602{
3603 struct cnic_local *cp = dev->cnic_priv;
3604 struct cnic_eth_dev *ethdev = cp->ethdev;
3605 u32 cid_addr, sb_id, val, coal_reg, coal_val;
3606 int i;
3607 struct rx_bd *rxbd;
a4dde3ab 3608 struct status_block *s_blk = cp->status_blk.gen;
a4636960
MC		 3609
3610 sb_id = cp->status_blk_num;
3611 cnic_init_context(dev, 2);
3612 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
3613 coal_reg = BNX2_HC_COMMAND;
3614 coal_val = CNIC_RD(dev, coal_reg);
3615 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
a4dde3ab 3616 struct status_block_msix *sblk = cp->status_blk.bnx2;
a4636960
MC		 3617
3618 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
3619 coal_reg = BNX2_HC_COALESCE_NOW;
3620 coal_val = 1 << (11 + sb_id);
3621 }
3622 i = 0;
3623 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
3624 CNIC_WR(dev, coal_reg, coal_val);
3625 udelay(10);
3626 i++;
3627 barrier();
3628 }
3629 cp->rx_cons = *cp->rx_cons_ptr;
3630
3631 cid_addr = GET_CID_ADDR(2);
3632 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3633 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3634 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
3635
3636 if (sb_id == 0)
d0549382 3637 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
a4636960 3638 else
d0549382 3639 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
a4636960
MC		 3640 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
3641
3642 rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
3643 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3644 dma_addr_t buf_map;
3645 int n = (i % cp->l2_rx_ring_size) + 1;
3646
3647 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
3648 rxbd->rx_bd_len = cp->l2_single_buf_size;
3649 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3650 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
3651 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3652 }
3653 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
3654 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
3655 rxbd->rx_bd_haddr_hi = val;
3656
3657 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3658 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
3659 rxbd->rx_bd_haddr_lo = val;
3660
3661 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
3662 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
3663}
3664
3665static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3666{
3667 struct kwqe *wqes[1], l2kwqe;
3668
3669 memset(&l2kwqe, 0, sizeof(l2kwqe));
3670 wqes[0] = &l2kwqe;
3671 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
3672 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3673 KWQE_OPCODE_SHIFT) | 2;
3674 dev->submit_kwqes(dev, wqes, 1);
3675}
3676
3677static void cnic_set_bnx2_mac(struct cnic_dev *dev)
3678{
3679 struct cnic_local *cp = dev->cnic_priv;
3680 u32 val;
3681
3682 val = cp->func << 2;
3683
3684 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
3685
3686 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3687 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
3688 dev->mac_addr[0] = (u8) (val >> 8);
3689 dev->mac_addr[1] = (u8) val;
3690
3691 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
3692
3693 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3694 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
3695 dev->mac_addr[2] = (u8) (val >> 24);
3696 dev->mac_addr[3] = (u8) (val >> 16);
3697 dev->mac_addr[4] = (u8) (val >> 8);
3698 dev->mac_addr[5] = (u8) val;
3699
3700 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
3701
3702 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
3703 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3704 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
3705
3706 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
3707 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
3708 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
3709}
3710
3711static int cnic_start_bnx2_hw(struct cnic_dev *dev)
3712{
3713 struct cnic_local *cp = dev->cnic_priv;
3714 struct cnic_eth_dev *ethdev = cp->ethdev;
a4dde3ab 3715 struct status_block *sblk = cp->status_blk.gen;
e6c28894 3716 u32 val, kcq_cid_addr, kwq_cid_addr;
a4636960
MC		 3717 int err;
3718
3719 cnic_set_bnx2_mac(dev);
3720
3721 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
3722 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3723 if (BCM_PAGE_BITS > 12)
3724 val |= (12 - 8) << 4;
3725 else
3726 val |= (BCM_PAGE_BITS - 8) << 4;
3727
3728 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
3729
3730 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
3731 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
3732 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
3733
3734 err = cnic_setup_5709_context(dev, 1);
3735 if (err)
3736 return err;
3737
3738 cnic_init_context(dev, KWQ_CID);
3739 cnic_init_context(dev, KCQ_CID);
3740
e6c28894 3741 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
a4636960
MC		 3742 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
3743
3744 cp->max_kwq_idx = MAX_KWQ_IDX;
3745 cp->kwq_prod_idx = 0;
3746 cp->kwq_con_idx = 0;
1f1332a3 3747 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
a4636960
MC		 3748
3749 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
3750 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
3751 else
3752 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
3753
3754 /* Initialize the kernel work queue context. */
3755 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3756 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
e6c28894 3757 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
a4636960
MC		 3758
3759 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
e6c28894 3760 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
a4636960
MC		 3761
3762 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
e6c28894 3763 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
a4636960
MC		 3764
3765 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
e6c28894 3766 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
a4636960
MC		 3767
3768 val = (u32) cp->kwq_info.pgtbl_map;
e6c28894
MC		 3769 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3770
3771 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
3772 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
a4636960 3773
e6c28894
MC		 3774 cp->kcq1.sw_prod_idx = 0;
3775 cp->kcq1.hw_prod_idx_ptr =
3776 (u16 *) &sblk->status_completion_producer_index;
a4636960 3777
e6c28894 3778 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
a4636960
MC		 3779
3780 /* Initialize the kernel complete queue context. */
3781 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3782 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
e6c28894 3783 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
a4636960
MC		 3784
3785 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
e6c28894 3786 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
a4636960
MC		 3787
3788 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
e6c28894 3789 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
a4636960 3790
e6c28894
MC		 3791 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
3792 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
a4636960 3793
e6c28894
MC		 3794 val = (u32) cp->kcq1.dma.pgtbl_map;
3795 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
a4636960
MC		 3796
3797 cp->int_num = 0;
3798 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
e6c28894 3799 struct status_block_msix *msblk = cp->status_blk.bnx2;
a4636960 3800 u32 sb_id = cp->status_blk_num;
d0549382 3801 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
a4636960 3802
e6c28894
MC		 3803 cp->kcq1.hw_prod_idx_ptr =
3804 (u16 *) &msblk->status_completion_producer_index;
3805 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
b177a5d5 3806 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
a4636960 3807 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
e6c28894
MC		 3808 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3809 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
a4636960
MC		 3810 }
3811
3812 /* Enable Commnad Scheduler notification when we write to the
3813 * host producer index of the kernel contexts. */
3814 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
3815
3816 /* Enable Command Scheduler notification when we write to either
3817 * the Send Queue or Receive Queue producer indexes of the kernel
3818 * bypass contexts. */
3819 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
3820 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
3821
3822 /* Notify COM when the driver post an application buffer. */
3823 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
3824
3825 /* Set the CP and COM doorbells. These two processors polls the
3826 * doorbell for a non zero value before running. This must be done
3827 * after setting up the kernel queue contexts. */
3828 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
3829 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
3830
3831 cnic_init_bnx2_tx_ring(dev);
3832 cnic_init_bnx2_rx_ring(dev);
3833
3834 err = cnic_init_bnx2_irq(dev);
3835 if (err) {
ddf79b20 3836 netdev_err(dev->netdev, "cnic_init_irq failed\n");
a4636960
MC		 3837 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
3838 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
3839 return err;
3840 }
3841
3842 return 0;
3843}
3844
71034ba8
MC		 3845static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
3846{
3847 struct cnic_local *cp = dev->cnic_priv;
3848 struct cnic_eth_dev *ethdev = cp->ethdev;
3849 u32 start_offset = ethdev->ctx_tbl_offset;
3850 int i;
3851
3852 for (i = 0; i < cp->ctx_blks; i++) {
3853 struct cnic_ctx *ctx = &cp->ctx_arr[i];
3854 dma_addr_t map = ctx->mapping;
3855
3856 if (cp->ctx_align) {
3857 unsigned long mask = cp->ctx_align - 1;
3858
3859 map = (map + mask) & ~mask;
3860 }
3861
3862 cnic_ctx_tbl_wr(dev, start_offset + i, map);
3863 }
3864}
3865
3866static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
3867{
3868 struct cnic_local *cp = dev->cnic_priv;
3869 struct cnic_eth_dev *ethdev = cp->ethdev;
3870 int err = 0;
3871
164165da 3872 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
71034ba8 3873 (unsigned long) dev);
6e0dc643
MC		 3874 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
3875 err = cnic_request_irq(dev);
3876
71034ba8
MC		 3877 return err;
3878}
3879
523224a3
DK		 3880static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
3881 u16 sb_id, u8 sb_index,
3882 u8 disable)
3883{
3884
3885 u32 addr = BAR_CSTRORM_INTMEM +
3886 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
3887 offsetof(struct hc_status_block_data_e1x, index_data) +
3888 sizeof(struct hc_index_data)*sb_index +
3889 offsetof(struct hc_index_data, flags);
3890 u16 flags = CNIC_RD16(dev, addr);
3891 /* clear and set */
3892 flags &= ~HC_INDEX_DATA_HC_ENABLED;
3893 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
3894 HC_INDEX_DATA_HC_ENABLED);
3895 CNIC_WR16(dev, addr, flags);
3896}
3897
71034ba8
MC		 3898static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
3899{
3900 struct cnic_local *cp = dev->cnic_priv;
3901 u8 sb_id = cp->status_blk_num;
71034ba8
MC		 3902
3903 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
523224a3
DK		 3904 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
3905 offsetof(struct hc_status_block_data_e1x, index_data) +
3906 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
3907 offsetof(struct hc_index_data, timeout), 64 / 12);
3908 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
71034ba8
MC		 3909}
3910
3911static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
3912{
3913}
3914
523224a3
DK		 3915static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
3916 struct client_init_ramrod_data *data)
71034ba8
MC		 3917{
3918 struct cnic_local *cp = dev->cnic_priv;
3919 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
523224a3
DK		 3920 dma_addr_t buf_map, ring_map = cp->l2_ring_map;
3921 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
71034ba8
MC		 3922 int port = CNIC_PORT(cp);
3923 int i;
3924 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
3925 u32 val;
3926
3927 memset(txbd, 0, BCM_PAGE_SIZE);
3928
3929 buf_map = cp->l2_buf_map;
3930 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
3931 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
3932 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
3933
3934 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
3935 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
3936 reg_bd->addr_hi = start_bd->addr_hi;
3937 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
3938 start_bd->nbytes = cpu_to_le16(0x10);
3939 start_bd->nbd = cpu_to_le16(3);
3940 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3941 start_bd->general_data = (UNICAST_ADDRESS <<
3942 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
3943 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
3944
3945 }
71034ba8 3946
523224a3 3947 val = (u64) ring_map >> 32;
71034ba8
MC		 3948 txbd->next_bd.addr_hi = cpu_to_le32(val);
3949
523224a3 3950 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
71034ba8 3951
523224a3 3952 val = (u64) ring_map & 0xffffffff;
71034ba8
MC		 3953 txbd->next_bd.addr_lo = cpu_to_le32(val);
3954
523224a3 3955 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
71034ba8 3956
523224a3
DK		 3957 /* Other ramrod params */
3958 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
3959 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
71034ba8
MC		 3960
3961 /* reset xstorm per client statistics */
523224a3 3962 if (cli < MAX_STAT_COUNTER_ID) {
6b2a541d
DK		 3963 val = BAR_XSTRORM_INTMEM +
3964 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
3965 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
3966 CNIC_WR(dev, val + i * 4, 0);
3967 }
71034ba8
MC		 3968
3969 cp->tx_cons_ptr =
523224a3 3970 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
71034ba8
MC		 3971}
3972
523224a3
DK		 3973static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
3974 struct client_init_ramrod_data *data)
71034ba8
MC		 3975{
3976 struct cnic_local *cp = dev->cnic_priv;
3977 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
3978 BCM_PAGE_SIZE);
3979 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
3980 (cp->l2_ring + (2 * BCM_PAGE_SIZE));
523224a3 3981 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
71034ba8
MC		 3982 int i;
3983 int port = CNIC_PORT(cp);
71034ba8 3984 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
523224a3 3985 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
71034ba8 3986 u32 val;
523224a3
DK		 3987 dma_addr_t ring_map = cp->l2_ring_map;
3988
3989 /* General data */
3990 data->general.client_id = cli;
3991 data->general.statistics_en_flg = 1;
3992 data->general.statistics_counter_id = cli;
3993 data->general.activate_flg = 1;
3994 data->general.sp_client_id = cli;
71034ba8
MC		 3995
3996 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
3997 dma_addr_t buf_map;
3998 int n = (i % cp->l2_rx_ring_size) + 1;
3999
4000 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
4001 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4002 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4003 }
71034ba8 4004
523224a3 4005 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
71034ba8 4006 rxbd->addr_hi = cpu_to_le32(val);
523224a3 4007 data->rx.bd_page_base.hi = cpu_to_le32(val);
71034ba8 4008
523224a3 4009 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
71034ba8 4010 rxbd->addr_lo = cpu_to_le32(val);
523224a3 4011 data->rx.bd_page_base.lo = cpu_to_le32(val);
71034ba8
MC		 4012
4013 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
523224a3 4014 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
71034ba8 4015 rxcqe->addr_hi = cpu_to_le32(val);
523224a3 4016 data->rx.cqe_page_base.hi = cpu_to_le32(val);
71034ba8 4017
523224a3 4018 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
71034ba8 4019 rxcqe->addr_lo = cpu_to_le32(val);
523224a3 4020 data->rx.cqe_page_base.lo = cpu_to_le32(val);
71034ba8 4021
523224a3
DK		 4022 /* Other ramrod params */
4023 data->rx.client_qzone_id = cl_qzone_id;
4024 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4025 data->rx.status_block_id = BNX2X_DEF_SB_ID;
71034ba8 4026
523224a3
DK		 4027 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4028 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
71034ba8 4029
523224a3
DK		 4030 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4031 data->rx.outer_vlan_removal_enable_flg = 1;
6b2a541d 4032
523224a3
DK		 4033 /* reset tstorm and ustorm per client statistics */
4034 if (cli < MAX_STAT_COUNTER_ID) {
6b2a541d
DK		 4035 val = BAR_TSTRORM_INTMEM +
4036 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4037 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4038 CNIC_WR(dev, val + i * 4, 0);
71034ba8 4039
6b2a541d
DK		 4040 val = BAR_USTRORM_INTMEM +
4041 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4042 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4043 CNIC_WR(dev, val + i * 4, 0);
4044 }
71034ba8
MC		 4045
4046 cp->rx_cons_ptr =
523224a3 4047 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
71034ba8
MC		 4048}
4049
4050static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4051{
4052 struct cnic_local *cp = dev->cnic_priv;
4053 u32 base, addr, val;
4054 int port = CNIC_PORT(cp);
4055
4056 dev->max_iscsi_conn = 0;
4057 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
523224a3 4058 if (base == 0)
71034ba8
MC		 4059 return;
4060
dd2e4dbc 4061 addr = BNX2X_SHMEM_ADDR(base,
71034ba8
MC		 4062 dev_info.port_hw_config[port].iscsi_mac_upper);
4063
dd2e4dbc
MC		 4064 val = CNIC_RD(dev, addr);
4065
71034ba8
MC		 4066 dev->mac_addr[0] = (u8) (val >> 8);
4067 dev->mac_addr[1] = (u8) val;
4068
dd2e4dbc 4069 addr = BNX2X_SHMEM_ADDR(base,
71034ba8
MC		 4070 dev_info.port_hw_config[port].iscsi_mac_lower);
4071
dd2e4dbc
MC		 4072 val = CNIC_RD(dev, addr);
4073
71034ba8
MC		 4074 dev->mac_addr[2] = (u8) (val >> 24);
4075 dev->mac_addr[3] = (u8) (val >> 16);
4076 dev->mac_addr[4] = (u8) (val >> 8);
4077 dev->mac_addr[5] = (u8) val;
4078
4079 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4080 val = CNIC_RD(dev, addr);
4081
4082 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4083 u16 val16;
4084
4085 addr = BNX2X_SHMEM_ADDR(base,
4086 drv_lic_key[port].max_iscsi_init_conn);
4087 val16 = CNIC_RD16(dev, addr);
4088
4089 if (val16)
4090 val16 ^= 0x1e1e;
4091 dev->max_iscsi_conn = val16;
4092 }
4093 if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
4094 int func = CNIC_FUNC(cp);
523224a3
DK		 4095 u32 mf_cfg_addr;
4096
4097 mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
4098
4099 addr = mf_cfg_addr +
4100 offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
71034ba8 4101
71034ba8
MC		 4102 val = CNIC_RD(dev, addr);
4103 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4104 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
523224a3
DK		 4105 addr = mf_cfg_addr +
4106 offsetof(struct mf_cfg,
4107 func_mf_config[func].config);
71034ba8
MC		 4108 val = CNIC_RD(dev, addr);
4109 val &= FUNC_MF_CFG_PROTOCOL_MASK;
4110 if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
4111 dev->max_iscsi_conn = 0;
4112 }
4113 }
4114}
4115
4116static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4117{
4118 struct cnic_local *cp = dev->cnic_priv;
523224a3 4119 struct cnic_eth_dev *ethdev = cp->ethdev;
71034ba8 4120 int func = CNIC_FUNC(cp), ret, i;
1420398d 4121 u32 pfid;
523224a3 4122 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
71034ba8 4123
1420398d
MC		 4124 cp->pfid = func;
4125 pfid = cp->pfid;
4126
71034ba8 4127 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
520efdf4 4128 cp->iscsi_start_cid);
71034ba8
MC		 4129
4130 if (ret)
4131 return -ENOMEM;
4132
523224a3
DK		 4133 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4134
e6c28894 4135 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
1420398d 4136 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
e6c28894
MC		 4137 cp->kcq1.sw_prod_idx = 0;
4138
4139 cp->kcq1.hw_prod_idx_ptr =
523224a3 4140 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
e6c28894 4141 cp->kcq1.status_idx_ptr =
523224a3 4142 &sb->sb.running_index[SM_RX_ID];
71034ba8
MC		 4143
4144 cnic_get_bnx2x_iscsi_info(dev);
4145
4146 /* Only 1 EQ */
e6c28894 4147 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
71034ba8 4148 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4149 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
71034ba8 4150 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4151 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
e6c28894 4152 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
71034ba8 4153 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4154 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
e6c28894 4155 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
71034ba8 4156 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4157 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
e6c28894 4158 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
71034ba8 4159 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4160 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
e6c28894 4161 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
71034ba8 4162 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1420398d 4163 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
71034ba8 4164 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1420398d 4165 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
71034ba8 4166 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1420398d 4167 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
523224a3 4168 HC_INDEX_ISCSI_EQ_CONS);
71034ba8
MC		 4169
4170 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4171 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1420398d 4172 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
71034ba8
MC		 4173 cp->conn_buf_info.pgtbl[2 * i]);
4174 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1420398d 4175 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
71034ba8
MC		 4176 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4177 }
4178
4179 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1420398d 4180 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
71034ba8
MC		 4181 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4182 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1420398d 4183 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
71034ba8
MC		 4184 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4185
523224a3
DK		 4186 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4187 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4188
71034ba8
MC		 4189 cnic_setup_bnx2x_context(dev);
4190
71034ba8
MC		 4191 ret = cnic_init_bnx2x_irq(dev);
4192 if (ret)
4193 return ret;
4194
71034ba8
MC		 4195 return 0;
4196}
4197
86b53606
MC		 4198static void cnic_init_rings(struct cnic_dev *dev)
4199{
541a7810
MC		 4200 struct cnic_local *cp = dev->cnic_priv;
4201
4202 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4203 return;
4204
86b53606
MC		 4205 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4206 cnic_init_bnx2_tx_ring(dev);
4207 cnic_init_bnx2_rx_ring(dev);
541a7810 4208 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
71034ba8 4209 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
71034ba8 4210 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
523224a3
DK		 4211 u32 cl_qzone_id, type;
4212 struct client_init_ramrod_data *data;
71034ba8
MC		 4213 union l5cm_specific_data l5_data;
4214 struct ustorm_eth_rx_producers rx_prods = {0};
c7596b79 4215 u32 off, i;
71034ba8
MC		 4216
4217 rx_prods.bd_prod = 0;
4218 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4219 barrier();
4220
523224a3
DK		 4221 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4222
c7596b79 4223 off = BAR_USTRORM_INTMEM +
523224a3 4224 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
71034ba8
MC		 4225
4226 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
c7596b79 4227 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
71034ba8 4228
48f753d2
MC		 4229 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4230
523224a3
DK		 4231 data = cp->l2_buf;
4232
4233 memset(data, 0, sizeof(*data));
4234
4235 cnic_init_bnx2x_tx_ring(dev, data);
4236 cnic_init_bnx2x_rx_ring(dev, data);
4237
4238 l5_data.phy_address.lo = cp->l2_buf_map & 0xffffffff;
4239 l5_data.phy_address.hi = (u64) cp->l2_buf_map >> 32;
4240
4241 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4242 & SPE_HDR_CONN_TYPE;
4243 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4244 SPE_HDR_FUNCTION_ID);
71034ba8 4245
541a7810
MC		 4246 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4247
71034ba8 4248 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
523224a3
DK		 4249 BNX2X_ISCSI_L2_CID, type, &l5_data);
4250
48f753d2
MC		 4251 i = 0;
4252 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4253 ++i < 10)
4254 msleep(1);
4255
4256 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4257 netdev_err(dev->netdev,
4258 "iSCSI CLIENT_SETUP did not complete\n");
c2bff63f 4259 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
71034ba8 4260 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
86b53606
MC		 4261 }
4262}
4263
4264static void cnic_shutdown_rings(struct cnic_dev *dev)
4265{
541a7810
MC		 4266 struct cnic_local *cp = dev->cnic_priv;
4267
4268 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4269 return;
4270
86b53606
MC		 4271 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4272 cnic_shutdown_bnx2_rx_ring(dev);
71034ba8
MC		 4273 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4274 struct cnic_local *cp = dev->cnic_priv;
4275 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
8b065b67 4276 union l5cm_specific_data l5_data;
48f753d2 4277 int i;
523224a3 4278 u32 type;
71034ba8
MC		 4279
4280 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
8b065b67 4281
48f753d2
MC		 4282 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4283
8b065b67
MC		 4284 l5_data.phy_address.lo = cli;
4285 l5_data.phy_address.hi = 0;
4286 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4287 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
48f753d2
MC		 4288 i = 0;
4289 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4290 ++i < 10)
4291 msleep(1);
4292
4293 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4294 netdev_err(dev->netdev,
4295 "iSCSI CLIENT_HALT did not complete\n");
c2bff63f 4296 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
1bcdc32c
MC		 4297
4298 memset(&l5_data, 0, sizeof(l5_data));
523224a3
DK		 4299 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4300 & SPE_HDR_CONN_TYPE;
4301 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4302 SPE_HDR_FUNCTION_ID);
4303 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
4304 BNX2X_ISCSI_L2_CID, type, &l5_data);
1bcdc32c 4305 msleep(10);
86b53606 4306 }
541a7810 4307 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
86b53606
MC		 4308}
4309
a3059b12 4310static int cnic_register_netdev(struct cnic_dev *dev)
a4636960
MC		 4311{
4312 struct cnic_local *cp = dev->cnic_priv;
4313 struct cnic_eth_dev *ethdev = cp->ethdev;
4314 int err;
4315
a3059b12
MC		 4316 if (!ethdev)
4317 return -ENODEV;
4318
4319 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4320 return 0;
a4636960
MC		 4321
4322 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
a3059b12 4323 if (err)
ddf79b20 4324 netdev_err(dev->netdev, "register_cnic failed\n");
a3059b12
MC		 4325
4326 return err;
4327}
4328
4329static void cnic_unregister_netdev(struct cnic_dev *dev)
4330{
4331 struct cnic_local *cp = dev->cnic_priv;
4332 struct cnic_eth_dev *ethdev = cp->ethdev;
4333
4334 if (!ethdev)
4335 return;
4336
4337 ethdev->drv_unregister_cnic(dev->netdev);
4338}
4339
4340static int cnic_start_hw(struct cnic_dev *dev)
4341{
4342 struct cnic_local *cp = dev->cnic_priv;
4343 struct cnic_eth_dev *ethdev = cp->ethdev;
4344 int err;
4345
4346 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
4347 return -EALREADY;
a4636960
MC		 4348
4349 dev->regview = ethdev->io_base;
4350 cp->chip_id = ethdev->chip_id;
4351 pci_dev_get(dev->pcidev);
4352 cp->func = PCI_FUNC(dev->pcidev->devfn);
a4dde3ab 4353 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
a4636960
MC		 4354 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
4355
4356 err = cp->alloc_resc(dev);
4357 if (err) {
ddf79b20 4358 netdev_err(dev->netdev, "allocate resource failure\n");
a4636960
MC		 4359 goto err1;
4360 }
4361
4362 err = cp->start_hw(dev);
4363 if (err)
4364 goto err1;
4365
4366 err = cnic_cm_open(dev);
4367 if (err)
4368 goto err1;
4369
4370 set_bit(CNIC_F_CNIC_UP, &dev->flags);
4371
4372 cp->enable_int(dev);
4373
4374 return 0;
4375
4376err1:
a4636960
MC		 4377 cp->free_resc(dev);
4378 pci_dev_put(dev->pcidev);
a4636960
MC		 4379 return err;
4380}
4381
4382static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
4383{
a4636960
MC		 4384 cnic_disable_bnx2_int_sync(dev);
4385
4386 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4387 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4388
4389 cnic_init_context(dev, KWQ_CID);
4390 cnic_init_context(dev, KCQ_CID);
4391
4392 cnic_setup_5709_context(dev, 0);
4393 cnic_free_irq(dev);
4394
a4636960
MC		 4395 cnic_free_resc(dev);
4396}
4397
71034ba8
MC		 4398
4399static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
4400{
4401 struct cnic_local *cp = dev->cnic_priv;
71034ba8
MC		 4402
4403 cnic_free_irq(dev);
523224a3 4404 *cp->kcq1.hw_prod_idx_ptr = 0;
4e9c4fd3 4405 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
1420398d 4406 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
e6c28894 4407 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
71034ba8
MC		 4408 cnic_free_resc(dev);
4409}
4410
a4636960
MC		 4411static void cnic_stop_hw(struct cnic_dev *dev)
4412{
4413 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4414 struct cnic_local *cp = dev->cnic_priv;
48f753d2 4415 int i = 0;
a4636960 4416
48f753d2
MC		 4417 /* Need to wait for the ring shutdown event to complete
4418 * before clearing the CNIC_UP flag.
4419 */
4420 while (cp->uio_dev != -1 && i < 15) {
4421 msleep(100);
4422 i++;
4423 }
a4636960
MC		 4424 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
4425 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
4426 synchronize_rcu();
4427 cnic_cm_shutdown(dev);
4428 cp->stop_hw(dev);
4429 pci_dev_put(dev->pcidev);
4430 }
4431}
4432
4433static void cnic_free_dev(struct cnic_dev *dev)
4434{
4435 int i = 0;
4436
4437 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
4438 msleep(100);
4439 i++;
4440 }
4441 if (atomic_read(&dev->ref_count) != 0)
ddf79b20 4442 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
a4636960 4443
ddf79b20 4444 netdev_info(dev->netdev, "Removed CNIC device\n");
a4636960
MC		 4445 dev_put(dev->netdev);
4446 kfree(dev);
4447}
4448
4449static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
4450 struct pci_dev *pdev)
4451{
4452 struct cnic_dev *cdev;
4453 struct cnic_local *cp;
4454 int alloc_size;
4455
4456 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
4457
4458 cdev = kzalloc(alloc_size , GFP_KERNEL);
4459 if (cdev == NULL) {
ddf79b20 4460 netdev_err(dev, "allocate dev struct failure\n");
a4636960
MC		 4461 return NULL;
4462 }
4463
4464 cdev->netdev = dev;
4465 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
4466 cdev->register_device = cnic_register_device;
4467 cdev->unregister_device = cnic_unregister_device;
4468 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
4469
4470 cp = cdev->cnic_priv;
4471 cp->dev = cdev;
4472 cp->uio_dev = -1;
4473 cp->l2_single_buf_size = 0x400;
4474 cp->l2_rx_ring_size = 3;
4475
4476 spin_lock_init(&cp->cnic_ulp_lock);
4477
ddf79b20 4478 netdev_info(dev, "Added CNIC device\n");
a4636960
MC		 4479
4480 return cdev;
4481}
4482
4483static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
4484{
4485 struct pci_dev *pdev;
4486 struct cnic_dev *cdev;
4487 struct cnic_local *cp;
4488 struct cnic_eth_dev *ethdev = NULL;
e2ee3616 4489 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
a4636960 4490
e2ee3616 4491 probe = symbol_get(bnx2_cnic_probe);
a4636960
MC		 4492 if (probe) {
4493 ethdev = (*probe)(dev);
64c64608 4494 symbol_put(bnx2_cnic_probe);
a4636960
MC		 4495 }
4496 if (!ethdev)
4497 return NULL;
4498
4499 pdev = ethdev->pdev;
4500 if (!pdev)
4501 return NULL;
4502
4503 dev_hold(dev);
4504 pci_dev_get(pdev);
4505 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
4506 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
4507 u8 rev;
4508
4509 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
4510 if (rev < 0x10) {
4511 pci_dev_put(pdev);
4512 goto cnic_err;
4513 }
4514 }
4515 pci_dev_put(pdev);
4516
4517 cdev = cnic_alloc_dev(dev, pdev);
4518 if (cdev == NULL)
4519 goto cnic_err;
4520
4521 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
4522 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
4523
4524 cp = cdev->cnic_priv;
4525 cp->ethdev = ethdev;
4526 cdev->pcidev = pdev;
4527
4528 cp->cnic_ops = &cnic_bnx2_ops;
4529 cp->start_hw = cnic_start_bnx2_hw;
4530 cp->stop_hw = cnic_stop_bnx2_hw;
4531 cp->setup_pgtbl = cnic_setup_page_tbl;
4532 cp->alloc_resc = cnic_alloc_bnx2_resc;
4533 cp->free_resc = cnic_free_resc;
4534 cp->start_cm = cnic_cm_init_bnx2_hw;
4535 cp->stop_cm = cnic_cm_stop_bnx2_hw;
4536 cp->enable_int = cnic_enable_bnx2_int;
4537 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
4538 cp->close_conn = cnic_close_bnx2_conn;
4539 cp->next_idx = cnic_bnx2_next_idx;
4540 cp->hw_idx = cnic_bnx2_hw_idx;
4541 return cdev;
4542
4543cnic_err:
4544 dev_put(dev);
4545 return NULL;
4546}
4547
71034ba8
MC		 4548static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
4549{
4550 struct pci_dev *pdev;
4551 struct cnic_dev *cdev;
4552 struct cnic_local *cp;
4553 struct cnic_eth_dev *ethdev = NULL;
4554 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4555
4556 probe = symbol_get(bnx2x_cnic_probe);
4557 if (probe) {
4558 ethdev = (*probe)(dev);
4559 symbol_put(bnx2x_cnic_probe);
4560 }
4561 if (!ethdev)
4562 return NULL;
4563
4564 pdev = ethdev->pdev;
4565 if (!pdev)
4566 return NULL;
4567
4568 dev_hold(dev);
4569 cdev = cnic_alloc_dev(dev, pdev);
4570 if (cdev == NULL) {
4571 dev_put(dev);
4572 return NULL;
4573 }
4574
4575 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
4576 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
4577
4578 cp = cdev->cnic_priv;
4579 cp->ethdev = ethdev;
4580 cdev->pcidev = pdev;
4581
4582 cp->cnic_ops = &cnic_bnx2x_ops;
4583 cp->start_hw = cnic_start_bnx2x_hw;
4584 cp->stop_hw = cnic_stop_bnx2x_hw;
4585 cp->setup_pgtbl = cnic_setup_page_tbl_le;
4586 cp->alloc_resc = cnic_alloc_bnx2x_resc;
4587 cp->free_resc = cnic_free_resc;
4588 cp->start_cm = cnic_cm_init_bnx2x_hw;
4589 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4590 cp->enable_int = cnic_enable_bnx2x_int;
4591 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4592 cp->ack_int = cnic_ack_bnx2x_msix;
4593 cp->close_conn = cnic_close_bnx2x_conn;
4594 cp->next_idx = cnic_bnx2x_next_idx;
4595 cp->hw_idx = cnic_bnx2x_hw_idx;
4596 return cdev;
4597}
4598
a4636960
MC		 4599static struct cnic_dev *is_cnic_dev(struct net_device *dev)
4600{
4601 struct ethtool_drvinfo drvinfo;
4602 struct cnic_dev *cdev = NULL;
4603
4604 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
4605 memset(&drvinfo, 0, sizeof(drvinfo));
4606 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
4607
4608 if (!strcmp(drvinfo.driver, "bnx2"))
4609 cdev = init_bnx2_cnic(dev);
71034ba8
MC		 4610 if (!strcmp(drvinfo.driver, "bnx2x"))
4611 cdev = init_bnx2x_cnic(dev);
a4636960
MC		 4612 if (cdev) {
4613 write_lock(&cnic_dev_lock);
4614 list_add(&cdev->list, &cnic_dev_list);
4615 write_unlock(&cnic_dev_lock);
4616 }
4617 }
4618 return cdev;
4619}
4620
4621/**
4622 * netdev event handler
4623 */
4624static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
4625 void *ptr)
4626{
4627 struct net_device *netdev = ptr;
4628 struct cnic_dev *dev;
4629 int if_type;
4630 int new_dev = 0;
4631
4632 dev = cnic_from_netdev(netdev);
4633
4634 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
4635 /* Check for the hot-plug device */
4636 dev = is_cnic_dev(netdev);
4637 if (dev) {
4638 new_dev = 1;
4639 cnic_hold(dev);
4640 }
4641 }
4642 if (dev) {
4643 struct cnic_local *cp = dev->cnic_priv;
4644
4645 if (new_dev)
4646 cnic_ulp_init(dev);
4647 else if (event == NETDEV_UNREGISTER)
4648 cnic_ulp_exit(dev);
6053bbf7
MC		 4649
4650 if (event == NETDEV_UP) {
a3059b12
MC		 4651 if (cnic_register_netdev(dev) != 0) {
4652 cnic_put(dev);
4653 goto done;
4654 }
a4636960
MC		 4655 if (!cnic_start_hw(dev))
4656 cnic_ulp_start(dev);
a4636960
MC		 4657 }
4658
4659 rcu_read_lock();
4660 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
4661 struct cnic_ulp_ops *ulp_ops;
4662 void *ctx;
4663
4664 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
4665 if (!ulp_ops || !ulp_ops->indicate_netevent)
4666 continue;
4667
4668 ctx = cp->ulp_handle[if_type];
4669
4670 ulp_ops->indicate_netevent(ctx, event);
4671 }
4672 rcu_read_unlock();
4673
4674 if (event == NETDEV_GOING_DOWN) {
a4636960
MC		 4675 cnic_ulp_stop(dev);
4676 cnic_stop_hw(dev);
a3059b12 4677 cnic_unregister_netdev(dev);
a4636960
MC		 4678 } else if (event == NETDEV_UNREGISTER) {
4679 write_lock(&cnic_dev_lock);
4680 list_del_init(&dev->list);
4681 write_unlock(&cnic_dev_lock);
4682
4683 cnic_put(dev);
4684 cnic_free_dev(dev);
4685 goto done;
4686 }
4687 cnic_put(dev);
4688 }
4689done:
4690 return NOTIFY_DONE;
4691}
4692
4693static struct notifier_block cnic_netdev_notifier = {
4694 .notifier_call = cnic_netdev_event
4695};
4696
4697static void cnic_release(void)
4698{
4699 struct cnic_dev *dev;
4700
4701 while (!list_empty(&cnic_dev_list)) {
4702 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
4703 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4704 cnic_ulp_stop(dev);
4705 cnic_stop_hw(dev);
4706 }
4707
4708 cnic_ulp_exit(dev);
a3059b12 4709 cnic_unregister_netdev(dev);
a4636960
MC		 4710 list_del_init(&dev->list);
4711 cnic_free_dev(dev);
4712 }
4713}
4714
4715static int __init cnic_init(void)
4716{
4717 int rc = 0;
4718
ddf79b20 4719 pr_info("%s", version);
a4636960
MC		 4720
4721 rc = register_netdevice_notifier(&cnic_netdev_notifier);
4722 if (rc) {
4723 cnic_release();
4724 return rc;
4725 }
4726
4727 return 0;
4728}
4729
4730static void __exit cnic_exit(void)
4731{
4732 unregister_netdevice_notifier(&cnic_netdev_notifier);
4733 cnic_release();
a4636960
MC		 4734}
4735
4736module_init(cnic_init);
4737module_exit(cnic_exit);
Linux kernel - Deliverables
This page took 0.374661 seconds and 5 git commands to generate.