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d95b39c3 MC |
1 | /* |
2 | * Copyright (C) 2006, 2007 Eugene Konev | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/moduleparam.h> | |
22 | ||
23 | #include <linux/sched.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/delay.h> | |
d95b39c3 MC |
29 | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/phy.h> | |
b88219f8 | 36 | #include <linux/phy_fixed.h> |
d95b39c3 MC |
37 | #include <linux/platform_device.h> |
38 | #include <linux/dma-mapping.h> | |
39 | #include <asm/gpio.h> | |
f917d580 | 40 | #include <asm/atomic.h> |
d95b39c3 MC |
41 | |
42 | MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>"); | |
43 | MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)"); | |
44 | MODULE_LICENSE("GPL"); | |
72abb461 | 45 | MODULE_ALIAS("platform:cpmac"); |
d95b39c3 MC |
46 | |
47 | static int debug_level = 8; | |
48 | static int dumb_switch; | |
49 | ||
50 | /* Next 2 are only used in cpmac_probe, so it's pointless to change them */ | |
51 | module_param(debug_level, int, 0444); | |
52 | module_param(dumb_switch, int, 0444); | |
53 | ||
54 | MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); | |
55 | MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); | |
56 | ||
57 | #define CPMAC_VERSION "0.5.0" | |
d95b39c3 MC |
58 | /* frame size + 802.1q tag */ |
59 | #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4) | |
60 | #define CPMAC_QUEUES 8 | |
61 | ||
62 | /* Ethernet registers */ | |
63 | #define CPMAC_TX_CONTROL 0x0004 | |
64 | #define CPMAC_TX_TEARDOWN 0x0008 | |
65 | #define CPMAC_RX_CONTROL 0x0014 | |
66 | #define CPMAC_RX_TEARDOWN 0x0018 | |
67 | #define CPMAC_MBP 0x0100 | |
68 | # define MBP_RXPASSCRC 0x40000000 | |
69 | # define MBP_RXQOS 0x20000000 | |
70 | # define MBP_RXNOCHAIN 0x10000000 | |
71 | # define MBP_RXCMF 0x01000000 | |
72 | # define MBP_RXSHORT 0x00800000 | |
73 | # define MBP_RXCEF 0x00400000 | |
74 | # define MBP_RXPROMISC 0x00200000 | |
75 | # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16) | |
76 | # define MBP_RXBCAST 0x00002000 | |
77 | # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8) | |
78 | # define MBP_RXMCAST 0x00000020 | |
79 | # define MBP_MCASTCHAN(channel) ((channel) & 0x7) | |
80 | #define CPMAC_UNICAST_ENABLE 0x0104 | |
81 | #define CPMAC_UNICAST_CLEAR 0x0108 | |
82 | #define CPMAC_MAX_LENGTH 0x010c | |
83 | #define CPMAC_BUFFER_OFFSET 0x0110 | |
84 | #define CPMAC_MAC_CONTROL 0x0160 | |
85 | # define MAC_TXPTYPE 0x00000200 | |
86 | # define MAC_TXPACE 0x00000040 | |
87 | # define MAC_MII 0x00000020 | |
88 | # define MAC_TXFLOW 0x00000010 | |
89 | # define MAC_RXFLOW 0x00000008 | |
90 | # define MAC_MTEST 0x00000004 | |
91 | # define MAC_LOOPBACK 0x00000002 | |
92 | # define MAC_FDX 0x00000001 | |
93 | #define CPMAC_MAC_STATUS 0x0164 | |
94 | # define MAC_STATUS_QOS 0x00000004 | |
95 | # define MAC_STATUS_RXFLOW 0x00000002 | |
96 | # define MAC_STATUS_TXFLOW 0x00000001 | |
97 | #define CPMAC_TX_INT_ENABLE 0x0178 | |
98 | #define CPMAC_TX_INT_CLEAR 0x017c | |
99 | #define CPMAC_MAC_INT_VECTOR 0x0180 | |
100 | # define MAC_INT_STATUS 0x00080000 | |
101 | # define MAC_INT_HOST 0x00040000 | |
102 | # define MAC_INT_RX 0x00020000 | |
103 | # define MAC_INT_TX 0x00010000 | |
104 | #define CPMAC_MAC_EOI_VECTOR 0x0184 | |
105 | #define CPMAC_RX_INT_ENABLE 0x0198 | |
106 | #define CPMAC_RX_INT_CLEAR 0x019c | |
107 | #define CPMAC_MAC_INT_ENABLE 0x01a8 | |
108 | #define CPMAC_MAC_INT_CLEAR 0x01ac | |
109 | #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4) | |
110 | #define CPMAC_MAC_ADDR_MID 0x01d0 | |
111 | #define CPMAC_MAC_ADDR_HI 0x01d4 | |
112 | #define CPMAC_MAC_HASH_LO 0x01d8 | |
113 | #define CPMAC_MAC_HASH_HI 0x01dc | |
114 | #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4) | |
115 | #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4) | |
116 | #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4) | |
117 | #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4) | |
118 | #define CPMAC_REG_END 0x0680 | |
119 | /* | |
120 | * Rx/Tx statistics | |
121 | * TODO: use some of them to fill stats in cpmac_stats() | |
122 | */ | |
123 | #define CPMAC_STATS_RX_GOOD 0x0200 | |
124 | #define CPMAC_STATS_RX_BCAST 0x0204 | |
125 | #define CPMAC_STATS_RX_MCAST 0x0208 | |
126 | #define CPMAC_STATS_RX_PAUSE 0x020c | |
127 | #define CPMAC_STATS_RX_CRC 0x0210 | |
128 | #define CPMAC_STATS_RX_ALIGN 0x0214 | |
129 | #define CPMAC_STATS_RX_OVER 0x0218 | |
130 | #define CPMAC_STATS_RX_JABBER 0x021c | |
131 | #define CPMAC_STATS_RX_UNDER 0x0220 | |
132 | #define CPMAC_STATS_RX_FRAG 0x0224 | |
133 | #define CPMAC_STATS_RX_FILTER 0x0228 | |
134 | #define CPMAC_STATS_RX_QOSFILTER 0x022c | |
135 | #define CPMAC_STATS_RX_OCTETS 0x0230 | |
136 | ||
137 | #define CPMAC_STATS_TX_GOOD 0x0234 | |
138 | #define CPMAC_STATS_TX_BCAST 0x0238 | |
139 | #define CPMAC_STATS_TX_MCAST 0x023c | |
140 | #define CPMAC_STATS_TX_PAUSE 0x0240 | |
141 | #define CPMAC_STATS_TX_DEFER 0x0244 | |
142 | #define CPMAC_STATS_TX_COLLISION 0x0248 | |
143 | #define CPMAC_STATS_TX_SINGLECOLL 0x024c | |
144 | #define CPMAC_STATS_TX_MULTICOLL 0x0250 | |
145 | #define CPMAC_STATS_TX_EXCESSCOLL 0x0254 | |
146 | #define CPMAC_STATS_TX_LATECOLL 0x0258 | |
147 | #define CPMAC_STATS_TX_UNDERRUN 0x025c | |
148 | #define CPMAC_STATS_TX_CARRIERSENSE 0x0260 | |
149 | #define CPMAC_STATS_TX_OCTETS 0x0264 | |
150 | ||
151 | #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg))) | |
152 | #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ | |
153 | (reg))) | |
154 | ||
155 | /* MDIO bus */ | |
156 | #define CPMAC_MDIO_VERSION 0x0000 | |
157 | #define CPMAC_MDIO_CONTROL 0x0004 | |
158 | # define MDIOC_IDLE 0x80000000 | |
159 | # define MDIOC_ENABLE 0x40000000 | |
160 | # define MDIOC_PREAMBLE 0x00100000 | |
161 | # define MDIOC_FAULT 0x00080000 | |
162 | # define MDIOC_FAULTDETECT 0x00040000 | |
163 | # define MDIOC_INTTEST 0x00020000 | |
164 | # define MDIOC_CLKDIV(div) ((div) & 0xff) | |
165 | #define CPMAC_MDIO_ALIVE 0x0008 | |
166 | #define CPMAC_MDIO_LINK 0x000c | |
167 | #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8) | |
168 | # define MDIO_BUSY 0x80000000 | |
169 | # define MDIO_WRITE 0x40000000 | |
170 | # define MDIO_REG(reg) (((reg) & 0x1f) << 21) | |
171 | # define MDIO_PHY(phy) (((phy) & 0x1f) << 16) | |
172 | # define MDIO_DATA(data) ((data) & 0xffff) | |
173 | #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8) | |
174 | # define PHYSEL_LINKSEL 0x00000040 | |
175 | # define PHYSEL_LINKINT 0x00000020 | |
176 | ||
177 | struct cpmac_desc { | |
178 | u32 hw_next; | |
179 | u32 hw_data; | |
180 | u16 buflen; | |
181 | u16 bufflags; | |
182 | u16 datalen; | |
183 | u16 dataflags; | |
184 | #define CPMAC_SOP 0x8000 | |
185 | #define CPMAC_EOP 0x4000 | |
186 | #define CPMAC_OWN 0x2000 | |
187 | #define CPMAC_EOQ 0x1000 | |
188 | struct sk_buff *skb; | |
189 | struct cpmac_desc *next; | |
f917d580 | 190 | struct cpmac_desc *prev; |
d95b39c3 MC |
191 | dma_addr_t mapping; |
192 | dma_addr_t data_mapping; | |
193 | }; | |
194 | ||
195 | struct cpmac_priv { | |
196 | spinlock_t lock; | |
197 | spinlock_t rx_lock; | |
198 | struct cpmac_desc *rx_head; | |
199 | int ring_size; | |
200 | struct cpmac_desc *desc_ring; | |
201 | dma_addr_t dma_ring; | |
202 | void __iomem *regs; | |
203 | struct mii_bus *mii_bus; | |
204 | struct phy_device *phy; | |
205 | char phy_name[BUS_ID_SIZE]; | |
206 | int oldlink, oldspeed, oldduplex; | |
207 | u32 msg_enable; | |
208 | struct net_device *dev; | |
209 | struct work_struct reset_work; | |
210 | struct platform_device *pdev; | |
67d129d1 | 211 | struct napi_struct napi; |
f917d580 | 212 | atomic_t reset_pending; |
d95b39c3 MC |
213 | }; |
214 | ||
215 | static irqreturn_t cpmac_irq(int, void *); | |
216 | static void cpmac_hw_start(struct net_device *dev); | |
217 | static void cpmac_hw_stop(struct net_device *dev); | |
218 | static int cpmac_stop(struct net_device *dev); | |
219 | static int cpmac_open(struct net_device *dev); | |
220 | ||
221 | static void cpmac_dump_regs(struct net_device *dev) | |
222 | { | |
223 | int i; | |
224 | struct cpmac_priv *priv = netdev_priv(dev); | |
225 | for (i = 0; i < CPMAC_REG_END; i += 4) { | |
226 | if (i % 16 == 0) { | |
227 | if (i) | |
228 | printk("\n"); | |
229 | printk(KERN_DEBUG "%s: reg[%p]:", dev->name, | |
230 | priv->regs + i); | |
231 | } | |
232 | printk(" %08x", cpmac_read(priv->regs, i)); | |
233 | } | |
234 | printk("\n"); | |
235 | } | |
236 | ||
237 | static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc) | |
238 | { | |
239 | int i; | |
240 | printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc); | |
241 | for (i = 0; i < sizeof(*desc) / 4; i++) | |
242 | printk(" %08x", ((u32 *)desc)[i]); | |
243 | printk("\n"); | |
244 | } | |
245 | ||
f917d580 MC |
246 | static void cpmac_dump_all_desc(struct net_device *dev) |
247 | { | |
248 | struct cpmac_priv *priv = netdev_priv(dev); | |
249 | struct cpmac_desc *dump = priv->rx_head; | |
250 | do { | |
251 | cpmac_dump_desc(dev, dump); | |
252 | dump = dump->next; | |
253 | } while (dump != priv->rx_head); | |
254 | } | |
255 | ||
d95b39c3 MC |
256 | static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb) |
257 | { | |
258 | int i; | |
259 | printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len); | |
260 | for (i = 0; i < skb->len; i++) { | |
261 | if (i % 16 == 0) { | |
262 | if (i) | |
263 | printk("\n"); | |
264 | printk(KERN_DEBUG "%s: data[%p]:", dev->name, | |
265 | skb->data + i); | |
266 | } | |
267 | printk(" %02x", ((u8 *)skb->data)[i]); | |
268 | } | |
269 | printk("\n"); | |
270 | } | |
271 | ||
272 | static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg) | |
273 | { | |
274 | u32 val; | |
275 | ||
276 | while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) | |
277 | cpu_relax(); | |
278 | cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) | | |
279 | MDIO_PHY(phy_id)); | |
280 | while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY) | |
281 | cpu_relax(); | |
282 | return MDIO_DATA(val); | |
283 | } | |
284 | ||
285 | static int cpmac_mdio_write(struct mii_bus *bus, int phy_id, | |
286 | int reg, u16 val) | |
287 | { | |
288 | while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) | |
289 | cpu_relax(); | |
290 | cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE | | |
291 | MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val)); | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static int cpmac_mdio_reset(struct mii_bus *bus) | |
296 | { | |
297 | ar7_device_reset(AR7_RESET_BIT_MDIO); | |
298 | cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE | | |
299 | MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1)); | |
300 | return 0; | |
301 | } | |
302 | ||
303 | static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, }; | |
304 | ||
298cf9be | 305 | static struct mii_bus *cpmac_mii; |
d95b39c3 MC |
306 | |
307 | static int cpmac_config(struct net_device *dev, struct ifmap *map) | |
308 | { | |
309 | if (dev->flags & IFF_UP) | |
310 | return -EBUSY; | |
311 | ||
312 | /* Don't allow changing the I/O address */ | |
313 | if (map->base_addr != dev->base_addr) | |
314 | return -EOPNOTSUPP; | |
315 | ||
316 | /* ignore other fields */ | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static void cpmac_set_multicast_list(struct net_device *dev) | |
321 | { | |
322 | struct dev_mc_list *iter; | |
323 | int i; | |
324 | u8 tmp; | |
325 | u32 mbp, bit, hash[2] = { 0, }; | |
326 | struct cpmac_priv *priv = netdev_priv(dev); | |
327 | ||
328 | mbp = cpmac_read(priv->regs, CPMAC_MBP); | |
329 | if (dev->flags & IFF_PROMISC) { | |
330 | cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) | | |
331 | MBP_RXPROMISC); | |
332 | } else { | |
333 | cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC); | |
334 | if (dev->flags & IFF_ALLMULTI) { | |
335 | /* enable all multicast mode */ | |
336 | cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff); | |
337 | cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff); | |
338 | } else { | |
339 | /* | |
340 | * cpmac uses some strange mac address hashing | |
341 | * (not crc32) | |
342 | */ | |
343 | for (i = 0, iter = dev->mc_list; i < dev->mc_count; | |
344 | i++, iter = iter->next) { | |
345 | bit = 0; | |
346 | tmp = iter->dmi_addr[0]; | |
347 | bit ^= (tmp >> 2) ^ (tmp << 4); | |
348 | tmp = iter->dmi_addr[1]; | |
349 | bit ^= (tmp >> 4) ^ (tmp << 2); | |
350 | tmp = iter->dmi_addr[2]; | |
351 | bit ^= (tmp >> 6) ^ tmp; | |
352 | tmp = iter->dmi_addr[3]; | |
353 | bit ^= (tmp >> 2) ^ (tmp << 4); | |
354 | tmp = iter->dmi_addr[4]; | |
355 | bit ^= (tmp >> 4) ^ (tmp << 2); | |
356 | tmp = iter->dmi_addr[5]; | |
357 | bit ^= (tmp >> 6) ^ tmp; | |
358 | bit &= 0x3f; | |
359 | hash[bit / 32] |= 1 << (bit % 32); | |
360 | } | |
361 | ||
362 | cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]); | |
363 | cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]); | |
364 | } | |
365 | } | |
366 | } | |
367 | ||
67d129d1 | 368 | static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv, |
d95b39c3 MC |
369 | struct cpmac_desc *desc) |
370 | { | |
371 | struct sk_buff *skb, *result = NULL; | |
372 | ||
373 | if (unlikely(netif_msg_hw(priv))) | |
67d129d1 | 374 | cpmac_dump_desc(priv->dev, desc); |
d95b39c3 MC |
375 | cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping); |
376 | if (unlikely(!desc->datalen)) { | |
377 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
378 | printk(KERN_WARNING "%s: rx: spurious interrupt\n", | |
67d129d1 | 379 | priv->dev->name); |
d95b39c3 MC |
380 | return NULL; |
381 | } | |
382 | ||
67d129d1 | 383 | skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE); |
d95b39c3 MC |
384 | if (likely(skb)) { |
385 | skb_reserve(skb, 2); | |
386 | skb_put(desc->skb, desc->datalen); | |
67d129d1 | 387 | desc->skb->protocol = eth_type_trans(desc->skb, priv->dev); |
d95b39c3 | 388 | desc->skb->ip_summed = CHECKSUM_NONE; |
67d129d1 EK |
389 | priv->dev->stats.rx_packets++; |
390 | priv->dev->stats.rx_bytes += desc->datalen; | |
d95b39c3 | 391 | result = desc->skb; |
67d129d1 EK |
392 | dma_unmap_single(&priv->dev->dev, desc->data_mapping, |
393 | CPMAC_SKB_SIZE, DMA_FROM_DEVICE); | |
d95b39c3 | 394 | desc->skb = skb; |
67d129d1 | 395 | desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data, |
d95b39c3 MC |
396 | CPMAC_SKB_SIZE, |
397 | DMA_FROM_DEVICE); | |
398 | desc->hw_data = (u32)desc->data_mapping; | |
399 | if (unlikely(netif_msg_pktdata(priv))) { | |
67d129d1 EK |
400 | printk(KERN_DEBUG "%s: received packet:\n", |
401 | priv->dev->name); | |
402 | cpmac_dump_skb(priv->dev, result); | |
d95b39c3 MC |
403 | } |
404 | } else { | |
405 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
406 | printk(KERN_WARNING | |
67d129d1 EK |
407 | "%s: low on skbs, dropping packet\n", |
408 | priv->dev->name); | |
409 | priv->dev->stats.rx_dropped++; | |
d95b39c3 MC |
410 | } |
411 | ||
412 | desc->buflen = CPMAC_SKB_SIZE; | |
413 | desc->dataflags = CPMAC_OWN; | |
414 | ||
415 | return result; | |
416 | } | |
417 | ||
67d129d1 | 418 | static int cpmac_poll(struct napi_struct *napi, int budget) |
d95b39c3 MC |
419 | { |
420 | struct sk_buff *skb; | |
f917d580 | 421 | struct cpmac_desc *desc, *restart; |
67d129d1 | 422 | struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi); |
f917d580 | 423 | int received = 0, processed = 0; |
d95b39c3 MC |
424 | |
425 | spin_lock(&priv->rx_lock); | |
426 | if (unlikely(!priv->rx_head)) { | |
427 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
428 | printk(KERN_WARNING "%s: rx: polling, but no queue\n", | |
67d129d1 | 429 | priv->dev->name); |
f917d580 | 430 | spin_unlock(&priv->rx_lock); |
67d129d1 | 431 | netif_rx_complete(priv->dev, napi); |
d95b39c3 MC |
432 | return 0; |
433 | } | |
434 | ||
435 | desc = priv->rx_head; | |
f917d580 | 436 | restart = NULL; |
67d129d1 | 437 | while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) { |
f917d580 MC |
438 | processed++; |
439 | ||
440 | if ((desc->dataflags & CPMAC_EOQ) != 0) { | |
441 | /* The last update to eoq->hw_next didn't happen | |
442 | * soon enough, and the receiver stopped here. | |
443 | *Remember this descriptor so we can restart | |
444 | * the receiver after freeing some space. | |
445 | */ | |
446 | if (unlikely(restart)) { | |
447 | if (netif_msg_rx_err(priv)) | |
448 | printk(KERN_ERR "%s: poll found a" | |
449 | " duplicate EOQ: %p and %p\n", | |
450 | priv->dev->name, restart, desc); | |
451 | goto fatal_error; | |
452 | } | |
453 | ||
454 | restart = desc->next; | |
455 | } | |
456 | ||
67d129d1 | 457 | skb = cpmac_rx_one(priv, desc); |
d95b39c3 MC |
458 | if (likely(skb)) { |
459 | netif_receive_skb(skb); | |
460 | received++; | |
461 | } | |
462 | desc = desc->next; | |
463 | } | |
464 | ||
f917d580 MC |
465 | if (desc != priv->rx_head) { |
466 | /* We freed some buffers, but not the whole ring, | |
467 | * add what we did free to the rx list */ | |
468 | desc->prev->hw_next = (u32)0; | |
469 | priv->rx_head->prev->hw_next = priv->rx_head->mapping; | |
470 | } | |
471 | ||
472 | /* Optimization: If we did not actually process an EOQ (perhaps because | |
473 | * of quota limits), check to see if the tail of the queue has EOQ set. | |
474 | * We should immediately restart in that case so that the receiver can | |
475 | * restart and run in parallel with more packet processing. | |
476 | * This lets us handle slightly larger bursts before running | |
477 | * out of ring space (assuming dev->weight < ring_size) */ | |
478 | ||
479 | if (!restart && | |
480 | (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ)) | |
481 | == CPMAC_EOQ && | |
482 | (priv->rx_head->dataflags & CPMAC_OWN) != 0) { | |
483 | /* reset EOQ so the poll loop (above) doesn't try to | |
484 | * restart this when it eventually gets to this descriptor. | |
485 | */ | |
486 | priv->rx_head->prev->dataflags &= ~CPMAC_EOQ; | |
487 | restart = priv->rx_head; | |
488 | } | |
489 | ||
490 | if (restart) { | |
491 | priv->dev->stats.rx_errors++; | |
492 | priv->dev->stats.rx_fifo_errors++; | |
493 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
494 | printk(KERN_WARNING "%s: rx dma ring overrun\n", | |
495 | priv->dev->name); | |
496 | ||
497 | if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) { | |
498 | if (netif_msg_drv(priv)) | |
499 | printk(KERN_ERR "%s: cpmac_poll is trying to " | |
500 | "restart rx from a descriptor that's " | |
501 | "not free: %p\n", | |
502 | priv->dev->name, restart); | |
503 | goto fatal_error; | |
504 | } | |
505 | ||
506 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping); | |
507 | } | |
508 | ||
d95b39c3 MC |
509 | priv->rx_head = desc; |
510 | spin_unlock(&priv->rx_lock); | |
d95b39c3 | 511 | if (unlikely(netif_msg_rx_status(priv))) |
67d129d1 EK |
512 | printk(KERN_DEBUG "%s: poll processed %d packets\n", |
513 | priv->dev->name, received); | |
f917d580 MC |
514 | if (processed == 0) { |
515 | /* we ran out of packets to read, | |
516 | * revert to interrupt-driven mode */ | |
67d129d1 | 517 | netif_rx_complete(priv->dev, napi); |
d95b39c3 MC |
518 | cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); |
519 | return 0; | |
520 | } | |
521 | ||
522 | return 1; | |
f917d580 MC |
523 | |
524 | fatal_error: | |
525 | /* Something went horribly wrong. | |
526 | * Reset hardware to try to recover rather than wedging. */ | |
527 | ||
528 | if (netif_msg_drv(priv)) { | |
529 | printk(KERN_ERR "%s: cpmac_poll is confused. " | |
530 | "Resetting hardware\n", priv->dev->name); | |
531 | cpmac_dump_all_desc(priv->dev); | |
532 | printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n", | |
533 | priv->dev->name, | |
534 | cpmac_read(priv->regs, CPMAC_RX_PTR(0)), | |
535 | cpmac_read(priv->regs, CPMAC_RX_ACK(0))); | |
536 | } | |
537 | ||
538 | spin_unlock(&priv->rx_lock); | |
539 | netif_rx_complete(priv->dev, napi); | |
fd2ea0a7 | 540 | netif_tx_stop_all_queues(priv->dev); |
f917d580 MC |
541 | napi_disable(&priv->napi); |
542 | ||
543 | atomic_inc(&priv->reset_pending); | |
544 | cpmac_hw_stop(priv->dev); | |
545 | if (!schedule_work(&priv->reset_work)) | |
546 | atomic_dec(&priv->reset_pending); | |
547 | return 0; | |
548 | ||
d95b39c3 MC |
549 | } |
550 | ||
551 | static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
552 | { | |
553 | int queue, len; | |
554 | struct cpmac_desc *desc; | |
555 | struct cpmac_priv *priv = netdev_priv(dev); | |
556 | ||
f917d580 MC |
557 | if (unlikely(atomic_read(&priv->reset_pending))) |
558 | return NETDEV_TX_BUSY; | |
559 | ||
6cd043d9 MC |
560 | if (unlikely(skb_padto(skb, ETH_ZLEN))) |
561 | return NETDEV_TX_OK; | |
d95b39c3 MC |
562 | |
563 | len = max(skb->len, ETH_ZLEN); | |
ba596a01 | 564 | queue = skb_get_queue_mapping(skb); |
d95b39c3 | 565 | netif_stop_subqueue(dev, queue); |
d95b39c3 MC |
566 | |
567 | desc = &priv->desc_ring[queue]; | |
568 | if (unlikely(desc->dataflags & CPMAC_OWN)) { | |
569 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
6cd043d9 | 570 | printk(KERN_WARNING "%s: tx dma ring full\n", |
d95b39c3 | 571 | dev->name); |
6cd043d9 | 572 | return NETDEV_TX_BUSY; |
d95b39c3 MC |
573 | } |
574 | ||
575 | spin_lock(&priv->lock); | |
576 | dev->trans_start = jiffies; | |
577 | spin_unlock(&priv->lock); | |
578 | desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN; | |
579 | desc->skb = skb; | |
580 | desc->data_mapping = dma_map_single(&dev->dev, skb->data, len, | |
581 | DMA_TO_DEVICE); | |
582 | desc->hw_data = (u32)desc->data_mapping; | |
583 | desc->datalen = len; | |
584 | desc->buflen = len; | |
585 | if (unlikely(netif_msg_tx_queued(priv))) | |
586 | printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb, | |
587 | skb->len); | |
588 | if (unlikely(netif_msg_hw(priv))) | |
589 | cpmac_dump_desc(dev, desc); | |
590 | if (unlikely(netif_msg_pktdata(priv))) | |
591 | cpmac_dump_skb(dev, skb); | |
592 | cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping); | |
593 | ||
6cd043d9 | 594 | return NETDEV_TX_OK; |
d95b39c3 MC |
595 | } |
596 | ||
597 | static void cpmac_end_xmit(struct net_device *dev, int queue) | |
598 | { | |
599 | struct cpmac_desc *desc; | |
600 | struct cpmac_priv *priv = netdev_priv(dev); | |
601 | ||
602 | desc = &priv->desc_ring[queue]; | |
603 | cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping); | |
604 | if (likely(desc->skb)) { | |
605 | spin_lock(&priv->lock); | |
606 | dev->stats.tx_packets++; | |
607 | dev->stats.tx_bytes += desc->skb->len; | |
608 | spin_unlock(&priv->lock); | |
609 | dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len, | |
610 | DMA_TO_DEVICE); | |
611 | ||
612 | if (unlikely(netif_msg_tx_done(priv))) | |
613 | printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name, | |
614 | desc->skb, desc->skb->len); | |
615 | ||
616 | dev_kfree_skb_irq(desc->skb); | |
617 | desc->skb = NULL; | |
d95b39c3 MC |
618 | if (netif_subqueue_stopped(dev, queue)) |
619 | netif_wake_subqueue(dev, queue); | |
d95b39c3 MC |
620 | } else { |
621 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
622 | printk(KERN_WARNING | |
623 | "%s: end_xmit: spurious interrupt\n", dev->name); | |
d95b39c3 MC |
624 | if (netif_subqueue_stopped(dev, queue)) |
625 | netif_wake_subqueue(dev, queue); | |
d95b39c3 MC |
626 | } |
627 | } | |
628 | ||
629 | static void cpmac_hw_stop(struct net_device *dev) | |
630 | { | |
631 | int i; | |
632 | struct cpmac_priv *priv = netdev_priv(dev); | |
633 | struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data; | |
634 | ||
635 | ar7_device_reset(pdata->reset_bit); | |
636 | cpmac_write(priv->regs, CPMAC_RX_CONTROL, | |
637 | cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1); | |
638 | cpmac_write(priv->regs, CPMAC_TX_CONTROL, | |
639 | cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1); | |
640 | for (i = 0; i < 8; i++) { | |
641 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
642 | cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); | |
643 | } | |
644 | cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); | |
645 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); | |
646 | cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); | |
647 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
648 | cpmac_write(priv->regs, CPMAC_MAC_CONTROL, | |
649 | cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII); | |
650 | } | |
651 | ||
652 | static void cpmac_hw_start(struct net_device *dev) | |
653 | { | |
654 | int i; | |
655 | struct cpmac_priv *priv = netdev_priv(dev); | |
656 | struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data; | |
657 | ||
658 | ar7_device_reset(pdata->reset_bit); | |
659 | for (i = 0; i < 8; i++) { | |
660 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
661 | cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); | |
662 | } | |
663 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping); | |
664 | ||
665 | cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST | | |
666 | MBP_RXMCAST); | |
667 | cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0); | |
668 | for (i = 0; i < 8; i++) | |
669 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]); | |
670 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]); | |
671 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] | | |
672 | (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) | | |
673 | (dev->dev_addr[3] << 24)); | |
674 | cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE); | |
675 | cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); | |
676 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); | |
677 | cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); | |
678 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
679 | cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1); | |
680 | cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); | |
681 | cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff); | |
682 | cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); | |
683 | ||
684 | cpmac_write(priv->regs, CPMAC_RX_CONTROL, | |
685 | cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1); | |
686 | cpmac_write(priv->regs, CPMAC_TX_CONTROL, | |
687 | cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1); | |
688 | cpmac_write(priv->regs, CPMAC_MAC_CONTROL, | |
689 | cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII | | |
690 | MAC_FDX); | |
691 | } | |
692 | ||
693 | static void cpmac_clear_rx(struct net_device *dev) | |
694 | { | |
695 | struct cpmac_priv *priv = netdev_priv(dev); | |
696 | struct cpmac_desc *desc; | |
697 | int i; | |
698 | if (unlikely(!priv->rx_head)) | |
699 | return; | |
700 | desc = priv->rx_head; | |
701 | for (i = 0; i < priv->ring_size; i++) { | |
702 | if ((desc->dataflags & CPMAC_OWN) == 0) { | |
703 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
704 | printk(KERN_WARNING "%s: packet dropped\n", | |
705 | dev->name); | |
706 | if (unlikely(netif_msg_hw(priv))) | |
707 | cpmac_dump_desc(dev, desc); | |
708 | desc->dataflags = CPMAC_OWN; | |
709 | dev->stats.rx_dropped++; | |
710 | } | |
f917d580 | 711 | desc->hw_next = desc->next->mapping; |
d95b39c3 MC |
712 | desc = desc->next; |
713 | } | |
f917d580 | 714 | priv->rx_head->prev->hw_next = 0; |
d95b39c3 MC |
715 | } |
716 | ||
717 | static void cpmac_clear_tx(struct net_device *dev) | |
718 | { | |
719 | struct cpmac_priv *priv = netdev_priv(dev); | |
720 | int i; | |
721 | if (unlikely(!priv->desc_ring)) | |
722 | return; | |
6cd043d9 MC |
723 | for (i = 0; i < CPMAC_QUEUES; i++) { |
724 | priv->desc_ring[i].dataflags = 0; | |
d95b39c3 MC |
725 | if (priv->desc_ring[i].skb) { |
726 | dev_kfree_skb_any(priv->desc_ring[i].skb); | |
f917d580 | 727 | priv->desc_ring[i].skb = NULL; |
d95b39c3 | 728 | } |
6cd043d9 | 729 | } |
d95b39c3 MC |
730 | } |
731 | ||
732 | static void cpmac_hw_error(struct work_struct *work) | |
733 | { | |
f917d580 | 734 | int i; |
d95b39c3 MC |
735 | struct cpmac_priv *priv = |
736 | container_of(work, struct cpmac_priv, reset_work); | |
737 | ||
738 | spin_lock(&priv->rx_lock); | |
739 | cpmac_clear_rx(priv->dev); | |
740 | spin_unlock(&priv->rx_lock); | |
741 | cpmac_clear_tx(priv->dev); | |
742 | cpmac_hw_start(priv->dev); | |
f917d580 MC |
743 | barrier(); |
744 | atomic_dec(&priv->reset_pending); | |
745 | ||
fd2ea0a7 | 746 | netif_tx_wake_all_queues(priv->dev); |
f917d580 MC |
747 | cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); |
748 | } | |
749 | ||
750 | static void cpmac_check_status(struct net_device *dev) | |
751 | { | |
752 | struct cpmac_priv *priv = netdev_priv(dev); | |
753 | ||
754 | u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS); | |
755 | int rx_channel = (macstatus >> 8) & 7; | |
756 | int rx_code = (macstatus >> 12) & 15; | |
757 | int tx_channel = (macstatus >> 16) & 7; | |
758 | int tx_code = (macstatus >> 20) & 15; | |
759 | ||
760 | if (rx_code || tx_code) { | |
761 | if (netif_msg_drv(priv) && net_ratelimit()) { | |
762 | /* Can't find any documentation on what these | |
763 | *error codes actually are. So just log them and hope.. | |
764 | */ | |
765 | if (rx_code) | |
766 | printk(KERN_WARNING "%s: host error %d on rx " | |
767 | "channel %d (macstatus %08x), resetting\n", | |
768 | dev->name, rx_code, rx_channel, macstatus); | |
769 | if (tx_code) | |
770 | printk(KERN_WARNING "%s: host error %d on tx " | |
771 | "channel %d (macstatus %08x), resetting\n", | |
772 | dev->name, tx_code, tx_channel, macstatus); | |
773 | } | |
774 | ||
fd2ea0a7 | 775 | netif_tx_stop_all_queues(dev); |
f917d580 MC |
776 | cpmac_hw_stop(dev); |
777 | if (schedule_work(&priv->reset_work)) | |
778 | atomic_inc(&priv->reset_pending); | |
779 | if (unlikely(netif_msg_hw(priv))) | |
780 | cpmac_dump_regs(dev); | |
781 | } | |
782 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
d95b39c3 MC |
783 | } |
784 | ||
785 | static irqreturn_t cpmac_irq(int irq, void *dev_id) | |
786 | { | |
787 | struct net_device *dev = dev_id; | |
788 | struct cpmac_priv *priv; | |
789 | int queue; | |
790 | u32 status; | |
791 | ||
d95b39c3 MC |
792 | priv = netdev_priv(dev); |
793 | ||
794 | status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR); | |
795 | ||
796 | if (unlikely(netif_msg_intr(priv))) | |
797 | printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name, | |
798 | status); | |
799 | ||
800 | if (status & MAC_INT_TX) | |
801 | cpmac_end_xmit(dev, (status & 7)); | |
802 | ||
803 | if (status & MAC_INT_RX) { | |
804 | queue = (status >> 8) & 7; | |
67d129d1 EK |
805 | if (netif_rx_schedule_prep(dev, &priv->napi)) { |
806 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue); | |
807 | __netif_rx_schedule(dev, &priv->napi); | |
808 | } | |
d95b39c3 MC |
809 | } |
810 | ||
811 | cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0); | |
812 | ||
f917d580 MC |
813 | if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) |
814 | cpmac_check_status(dev); | |
d95b39c3 MC |
815 | |
816 | return IRQ_HANDLED; | |
817 | } | |
818 | ||
819 | static void cpmac_tx_timeout(struct net_device *dev) | |
820 | { | |
d95b39c3 | 821 | int i; |
f917d580 | 822 | struct cpmac_priv *priv = netdev_priv(dev); |
d95b39c3 MC |
823 | |
824 | spin_lock(&priv->lock); | |
825 | dev->stats.tx_errors++; | |
826 | spin_unlock(&priv->lock); | |
827 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
828 | printk(KERN_WARNING "%s: transmit timeout\n", dev->name); | |
f917d580 MC |
829 | |
830 | atomic_inc(&priv->reset_pending); | |
831 | barrier(); | |
832 | cpmac_clear_tx(dev); | |
833 | barrier(); | |
834 | atomic_dec(&priv->reset_pending); | |
835 | ||
fd2ea0a7 | 836 | netif_tx_wake_all_queues(priv->dev); |
d95b39c3 MC |
837 | } |
838 | ||
839 | static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
840 | { | |
841 | struct cpmac_priv *priv = netdev_priv(dev); | |
842 | if (!(netif_running(dev))) | |
843 | return -EINVAL; | |
844 | if (!priv->phy) | |
845 | return -EINVAL; | |
846 | if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) || | |
847 | (cmd == SIOCSMIIREG)) | |
848 | return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd); | |
849 | ||
850 | return -EOPNOTSUPP; | |
851 | } | |
852 | ||
853 | static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
854 | { | |
855 | struct cpmac_priv *priv = netdev_priv(dev); | |
856 | ||
857 | if (priv->phy) | |
858 | return phy_ethtool_gset(priv->phy, cmd); | |
859 | ||
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
864 | { | |
865 | struct cpmac_priv *priv = netdev_priv(dev); | |
866 | ||
867 | if (!capable(CAP_NET_ADMIN)) | |
868 | return -EPERM; | |
869 | ||
870 | if (priv->phy) | |
871 | return phy_ethtool_sset(priv->phy, cmd); | |
872 | ||
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
877 | { | |
878 | struct cpmac_priv *priv = netdev_priv(dev); | |
879 | ||
880 | ring->rx_max_pending = 1024; | |
881 | ring->rx_mini_max_pending = 1; | |
882 | ring->rx_jumbo_max_pending = 1; | |
883 | ring->tx_max_pending = 1; | |
884 | ||
885 | ring->rx_pending = priv->ring_size; | |
886 | ring->rx_mini_pending = 1; | |
887 | ring->rx_jumbo_pending = 1; | |
888 | ring->tx_pending = 1; | |
889 | } | |
890 | ||
891 | static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
892 | { | |
893 | struct cpmac_priv *priv = netdev_priv(dev); | |
894 | ||
6cd043d9 | 895 | if (netif_running(dev)) |
d95b39c3 MC |
896 | return -EBUSY; |
897 | priv->ring_size = ring->rx_pending; | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static void cpmac_get_drvinfo(struct net_device *dev, | |
902 | struct ethtool_drvinfo *info) | |
903 | { | |
904 | strcpy(info->driver, "cpmac"); | |
905 | strcpy(info->version, CPMAC_VERSION); | |
906 | info->fw_version[0] = '\0'; | |
907 | sprintf(info->bus_info, "%s", "cpmac"); | |
908 | info->regdump_len = 0; | |
909 | } | |
910 | ||
911 | static const struct ethtool_ops cpmac_ethtool_ops = { | |
912 | .get_settings = cpmac_get_settings, | |
913 | .set_settings = cpmac_set_settings, | |
914 | .get_drvinfo = cpmac_get_drvinfo, | |
915 | .get_link = ethtool_op_get_link, | |
916 | .get_ringparam = cpmac_get_ringparam, | |
917 | .set_ringparam = cpmac_set_ringparam, | |
918 | }; | |
919 | ||
920 | static void cpmac_adjust_link(struct net_device *dev) | |
921 | { | |
922 | struct cpmac_priv *priv = netdev_priv(dev); | |
923 | int new_state = 0; | |
924 | ||
925 | spin_lock(&priv->lock); | |
926 | if (priv->phy->link) { | |
fd2ea0a7 | 927 | netif_tx_start_all_queues(dev); |
d95b39c3 MC |
928 | if (priv->phy->duplex != priv->oldduplex) { |
929 | new_state = 1; | |
930 | priv->oldduplex = priv->phy->duplex; | |
931 | } | |
932 | ||
933 | if (priv->phy->speed != priv->oldspeed) { | |
934 | new_state = 1; | |
935 | priv->oldspeed = priv->phy->speed; | |
936 | } | |
937 | ||
938 | if (!priv->oldlink) { | |
939 | new_state = 1; | |
940 | priv->oldlink = 1; | |
d95b39c3 MC |
941 | } |
942 | } else if (priv->oldlink) { | |
d95b39c3 MC |
943 | new_state = 1; |
944 | priv->oldlink = 0; | |
945 | priv->oldspeed = 0; | |
946 | priv->oldduplex = -1; | |
947 | } | |
948 | ||
949 | if (new_state && netif_msg_link(priv) && net_ratelimit()) | |
950 | phy_print_status(priv->phy); | |
951 | ||
952 | spin_unlock(&priv->lock); | |
953 | } | |
954 | ||
955 | static int cpmac_open(struct net_device *dev) | |
956 | { | |
957 | int i, size, res; | |
958 | struct cpmac_priv *priv = netdev_priv(dev); | |
959 | struct resource *mem; | |
960 | struct cpmac_desc *desc; | |
961 | struct sk_buff *skb; | |
962 | ||
d95b39c3 MC |
963 | mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); |
964 | if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) { | |
965 | if (netif_msg_drv(priv)) | |
966 | printk(KERN_ERR "%s: failed to request registers\n", | |
967 | dev->name); | |
968 | res = -ENXIO; | |
969 | goto fail_reserve; | |
970 | } | |
971 | ||
972 | priv->regs = ioremap(mem->start, mem->end - mem->start); | |
973 | if (!priv->regs) { | |
974 | if (netif_msg_drv(priv)) | |
975 | printk(KERN_ERR "%s: failed to remap registers\n", | |
976 | dev->name); | |
977 | res = -ENXIO; | |
978 | goto fail_remap; | |
979 | } | |
980 | ||
981 | size = priv->ring_size + CPMAC_QUEUES; | |
982 | priv->desc_ring = dma_alloc_coherent(&dev->dev, | |
983 | sizeof(struct cpmac_desc) * size, | |
984 | &priv->dma_ring, | |
985 | GFP_KERNEL); | |
986 | if (!priv->desc_ring) { | |
987 | res = -ENOMEM; | |
988 | goto fail_alloc; | |
989 | } | |
990 | ||
991 | for (i = 0; i < size; i++) | |
992 | priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i; | |
993 | ||
994 | priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; | |
995 | for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) { | |
996 | skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE); | |
997 | if (unlikely(!skb)) { | |
998 | res = -ENOMEM; | |
999 | goto fail_desc; | |
1000 | } | |
1001 | skb_reserve(skb, 2); | |
1002 | desc->skb = skb; | |
1003 | desc->data_mapping = dma_map_single(&dev->dev, skb->data, | |
1004 | CPMAC_SKB_SIZE, | |
1005 | DMA_FROM_DEVICE); | |
1006 | desc->hw_data = (u32)desc->data_mapping; | |
1007 | desc->buflen = CPMAC_SKB_SIZE; | |
1008 | desc->dataflags = CPMAC_OWN; | |
1009 | desc->next = &priv->rx_head[(i + 1) % priv->ring_size]; | |
f917d580 | 1010 | desc->next->prev = desc; |
d95b39c3 MC |
1011 | desc->hw_next = (u32)desc->next->mapping; |
1012 | } | |
1013 | ||
f917d580 MC |
1014 | priv->rx_head->prev->hw_next = (u32)0; |
1015 | ||
d95b39c3 MC |
1016 | if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, |
1017 | dev->name, dev))) { | |
1018 | if (netif_msg_drv(priv)) | |
1019 | printk(KERN_ERR "%s: failed to obtain irq\n", | |
1020 | dev->name); | |
1021 | goto fail_irq; | |
1022 | } | |
1023 | ||
f917d580 | 1024 | atomic_set(&priv->reset_pending, 0); |
d95b39c3 MC |
1025 | INIT_WORK(&priv->reset_work, cpmac_hw_error); |
1026 | cpmac_hw_start(dev); | |
1027 | ||
67d129d1 | 1028 | napi_enable(&priv->napi); |
d95b39c3 MC |
1029 | priv->phy->state = PHY_CHANGELINK; |
1030 | phy_start(priv->phy); | |
1031 | ||
1032 | return 0; | |
1033 | ||
1034 | fail_irq: | |
1035 | fail_desc: | |
1036 | for (i = 0; i < priv->ring_size; i++) { | |
1037 | if (priv->rx_head[i].skb) { | |
1038 | dma_unmap_single(&dev->dev, | |
1039 | priv->rx_head[i].data_mapping, | |
1040 | CPMAC_SKB_SIZE, | |
1041 | DMA_FROM_DEVICE); | |
1042 | kfree_skb(priv->rx_head[i].skb); | |
1043 | } | |
1044 | } | |
1045 | fail_alloc: | |
1046 | kfree(priv->desc_ring); | |
1047 | iounmap(priv->regs); | |
1048 | ||
1049 | fail_remap: | |
1050 | release_mem_region(mem->start, mem->end - mem->start); | |
1051 | ||
1052 | fail_reserve: | |
d95b39c3 MC |
1053 | return res; |
1054 | } | |
1055 | ||
1056 | static int cpmac_stop(struct net_device *dev) | |
1057 | { | |
1058 | int i; | |
1059 | struct cpmac_priv *priv = netdev_priv(dev); | |
1060 | struct resource *mem; | |
1061 | ||
fd2ea0a7 | 1062 | netif_tx_stop_all_queues(dev); |
d95b39c3 MC |
1063 | |
1064 | cancel_work_sync(&priv->reset_work); | |
67d129d1 | 1065 | napi_disable(&priv->napi); |
d95b39c3 | 1066 | phy_stop(priv->phy); |
d95b39c3 MC |
1067 | |
1068 | cpmac_hw_stop(dev); | |
1069 | ||
1070 | for (i = 0; i < 8; i++) | |
1071 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
1072 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0); | |
1073 | cpmac_write(priv->regs, CPMAC_MBP, 0); | |
1074 | ||
1075 | free_irq(dev->irq, dev); | |
1076 | iounmap(priv->regs); | |
1077 | mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); | |
1078 | release_mem_region(mem->start, mem->end - mem->start); | |
1079 | priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; | |
1080 | for (i = 0; i < priv->ring_size; i++) { | |
1081 | if (priv->rx_head[i].skb) { | |
1082 | dma_unmap_single(&dev->dev, | |
1083 | priv->rx_head[i].data_mapping, | |
1084 | CPMAC_SKB_SIZE, | |
1085 | DMA_FROM_DEVICE); | |
1086 | kfree_skb(priv->rx_head[i].skb); | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * | |
1091 | (CPMAC_QUEUES + priv->ring_size), | |
1092 | priv->desc_ring, priv->dma_ring); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int external_switch; | |
1097 | ||
1098 | static int __devinit cpmac_probe(struct platform_device *pdev) | |
1099 | { | |
b88219f8 | 1100 | int rc, phy_id, i; |
9d9326d3 | 1101 | char *mdio_bus_id = "0"; |
d95b39c3 MC |
1102 | struct resource *mem; |
1103 | struct cpmac_priv *priv; | |
1104 | struct net_device *dev; | |
1105 | struct plat_cpmac_data *pdata; | |
1106 | ||
1107 | pdata = pdev->dev.platform_data; | |
1108 | ||
1109 | for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { | |
1110 | if (!(pdata->phy_mask & (1 << phy_id))) | |
1111 | continue; | |
298cf9be | 1112 | if (!cpmac_mii->phy_map[phy_id]) |
d95b39c3 MC |
1113 | continue; |
1114 | break; | |
1115 | } | |
1116 | ||
1117 | if (phy_id == PHY_MAX_ADDR) { | |
8353ec7b | 1118 | if (external_switch || dumb_switch) { |
f917d580 MC |
1119 | mdio_bus_id = 0; /* fixed phys bus */ |
1120 | phy_id = pdev->id; | |
8353ec7b | 1121 | } else { |
f917d580 | 1122 | dev_err(&pdev->dev, "no PHY present\n"); |
d95b39c3 MC |
1123 | return -ENODEV; |
1124 | } | |
1125 | } | |
1126 | ||
1127 | dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); | |
1128 | ||
1129 | if (!dev) { | |
1130 | printk(KERN_ERR "cpmac: Unable to allocate net_device\n"); | |
1131 | return -ENOMEM; | |
1132 | } | |
1133 | ||
1134 | platform_set_drvdata(pdev, dev); | |
1135 | priv = netdev_priv(dev); | |
1136 | ||
1137 | priv->pdev = pdev; | |
1138 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
1139 | if (!mem) { | |
1140 | rc = -ENODEV; | |
1141 | goto fail; | |
1142 | } | |
1143 | ||
1144 | dev->irq = platform_get_irq_byname(pdev, "irq"); | |
1145 | ||
1146 | dev->open = cpmac_open; | |
1147 | dev->stop = cpmac_stop; | |
1148 | dev->set_config = cpmac_config; | |
1149 | dev->hard_start_xmit = cpmac_start_xmit; | |
1150 | dev->do_ioctl = cpmac_ioctl; | |
1151 | dev->set_multicast_list = cpmac_set_multicast_list; | |
1152 | dev->tx_timeout = cpmac_tx_timeout; | |
1153 | dev->ethtool_ops = &cpmac_ethtool_ops; | |
d95b39c3 | 1154 | |
67d129d1 EK |
1155 | netif_napi_add(dev, &priv->napi, cpmac_poll, 64); |
1156 | ||
d95b39c3 MC |
1157 | spin_lock_init(&priv->lock); |
1158 | spin_lock_init(&priv->rx_lock); | |
1159 | priv->dev = dev; | |
1160 | priv->ring_size = 64; | |
1161 | priv->msg_enable = netif_msg_init(debug_level, 0xff); | |
1162 | memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr)); | |
b88219f8 | 1163 | |
298cf9be | 1164 | priv->phy = phy_connect(dev, cpmac_mii->phy_map[phy_id]->dev.bus_id, |
f917d580 | 1165 | &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII); |
b88219f8 EK |
1166 | if (IS_ERR(priv->phy)) { |
1167 | if (netif_msg_drv(priv)) | |
1168 | printk(KERN_ERR "%s: Could not attach to PHY\n", | |
1169 | dev->name); | |
1170 | return PTR_ERR(priv->phy); | |
1171 | } | |
d95b39c3 MC |
1172 | |
1173 | if ((rc = register_netdev(dev))) { | |
1174 | printk(KERN_ERR "cpmac: error %i registering device %s\n", rc, | |
1175 | dev->name); | |
1176 | goto fail; | |
1177 | } | |
1178 | ||
1179 | if (netif_msg_probe(priv)) { | |
1180 | printk(KERN_INFO | |
df523b5c | 1181 | "cpmac: device %s (regs: %p, irq: %d, phy: %s, " |
e174961c JB |
1182 | "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq, |
1183 | priv->phy_name, dev->dev_addr); | |
d95b39c3 MC |
1184 | } |
1185 | return 0; | |
1186 | ||
1187 | fail: | |
1188 | free_netdev(dev); | |
1189 | return rc; | |
1190 | } | |
1191 | ||
1192 | static int __devexit cpmac_remove(struct platform_device *pdev) | |
1193 | { | |
1194 | struct net_device *dev = platform_get_drvdata(pdev); | |
1195 | unregister_netdev(dev); | |
1196 | free_netdev(dev); | |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static struct platform_driver cpmac_driver = { | |
1201 | .driver.name = "cpmac", | |
72abb461 | 1202 | .driver.owner = THIS_MODULE, |
d95b39c3 MC |
1203 | .probe = cpmac_probe, |
1204 | .remove = __devexit_p(cpmac_remove), | |
1205 | }; | |
1206 | ||
1207 | int __devinit cpmac_init(void) | |
1208 | { | |
1209 | u32 mask; | |
1210 | int i, res; | |
1211 | ||
298cf9be LB |
1212 | cpmac_mii = mdiobus_alloc(); |
1213 | if (cpmac_mii == NULL) | |
1214 | return -ENOMEM; | |
1215 | ||
1216 | cpmac_mii->name = "cpmac-mii"; | |
1217 | cpmac_mii->read = cpmac_mdio_read; | |
1218 | cpmac_mii->write = cpmac_mdio_write; | |
1219 | cpmac_mii->reset = cpmac_mdio_reset; | |
1220 | cpmac_mii->irq = mii_irqs; | |
1221 | ||
1222 | cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); | |
d95b39c3 | 1223 | |
298cf9be | 1224 | if (!cpmac_mii->priv) { |
d95b39c3 | 1225 | printk(KERN_ERR "Can't ioremap mdio registers\n"); |
298cf9be LB |
1226 | res = -ENXIO; |
1227 | goto fail_alloc; | |
d95b39c3 MC |
1228 | } |
1229 | ||
1230 | #warning FIXME: unhardcode gpio&reset bits | |
1231 | ar7_gpio_disable(26); | |
1232 | ar7_gpio_disable(27); | |
1233 | ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); | |
1234 | ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); | |
1235 | ar7_device_reset(AR7_RESET_BIT_EPHY); | |
1236 | ||
298cf9be | 1237 | cpmac_mii->reset(cpmac_mii); |
d95b39c3 MC |
1238 | |
1239 | for (i = 0; i < 300000; i++) | |
298cf9be | 1240 | if ((mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE))) |
d95b39c3 MC |
1241 | break; |
1242 | else | |
1243 | cpu_relax(); | |
1244 | ||
1245 | mask &= 0x7fffffff; | |
1246 | if (mask & (mask - 1)) { | |
1247 | external_switch = 1; | |
1248 | mask = 0; | |
1249 | } | |
1250 | ||
298cf9be LB |
1251 | cpmac_mii->phy_mask = ~(mask | 0x80000000); |
1252 | snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "0"); | |
d95b39c3 | 1253 | |
298cf9be | 1254 | res = mdiobus_register(cpmac_mii); |
d95b39c3 MC |
1255 | if (res) |
1256 | goto fail_mii; | |
1257 | ||
1258 | res = platform_driver_register(&cpmac_driver); | |
1259 | if (res) | |
1260 | goto fail_cpmac; | |
1261 | ||
1262 | return 0; | |
1263 | ||
1264 | fail_cpmac: | |
298cf9be | 1265 | mdiobus_unregister(cpmac_mii); |
d95b39c3 MC |
1266 | |
1267 | fail_mii: | |
298cf9be LB |
1268 | iounmap(cpmac_mii->priv); |
1269 | ||
1270 | fail_alloc: | |
1271 | mdiobus_free(cpmac_mii); | |
d95b39c3 MC |
1272 | |
1273 | return res; | |
1274 | } | |
1275 | ||
1276 | void __devexit cpmac_exit(void) | |
1277 | { | |
1278 | platform_driver_unregister(&cpmac_driver); | |
298cf9be LB |
1279 | mdiobus_unregister(cpmac_mii); |
1280 | mdiobus_free(cpmac_mii); | |
1281 | iounmap(cpmac_mii->priv); | |
d95b39c3 MC |
1282 | } |
1283 | ||
1284 | module_init(cpmac_init); | |
1285 | module_exit(cpmac_exit); |