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cpmac: use print_mac() instead of MAC_FMT
[deliverable/linux.git] / drivers / net / cpmac.c
CommitLineData
d95b39c3
MC		 1/*
2 * Copyright (C) 2006, 2007 Eugene Konev
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/moduleparam.h>
22
23#include <linux/sched.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/types.h>
28#include <linux/delay.h>
29#include <linux/version.h>
30
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/skbuff.h>
35#include <linux/mii.h>
36#include <linux/phy.h>
37#include <linux/platform_device.h>
38#include <linux/dma-mapping.h>
39#include <asm/gpio.h>
40
41MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
42MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
43MODULE_LICENSE("GPL");
44
45static int debug_level = 8;
46static int dumb_switch;
47
48/* Next 2 are only used in cpmac_probe, so it's pointless to change them */
49module_param(debug_level, int, 0444);
50module_param(dumb_switch, int, 0444);
51
52MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
53MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
54
55#define CPMAC_VERSION "0.5.0"
d95b39c3
MC		 56/* frame size + 802.1q tag */
57#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
58#define CPMAC_QUEUES 8
59
60/* Ethernet registers */
61#define CPMAC_TX_CONTROL 0x0004
62#define CPMAC_TX_TEARDOWN 0x0008
63#define CPMAC_RX_CONTROL 0x0014
64#define CPMAC_RX_TEARDOWN 0x0018
65#define CPMAC_MBP 0x0100
66# define MBP_RXPASSCRC 0x40000000
67# define MBP_RXQOS 0x20000000
68# define MBP_RXNOCHAIN 0x10000000
69# define MBP_RXCMF 0x01000000
70# define MBP_RXSHORT 0x00800000
71# define MBP_RXCEF 0x00400000
72# define MBP_RXPROMISC 0x00200000
73# define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
74# define MBP_RXBCAST 0x00002000
75# define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
76# define MBP_RXMCAST 0x00000020
77# define MBP_MCASTCHAN(channel) ((channel) & 0x7)
78#define CPMAC_UNICAST_ENABLE 0x0104
79#define CPMAC_UNICAST_CLEAR 0x0108
80#define CPMAC_MAX_LENGTH 0x010c
81#define CPMAC_BUFFER_OFFSET 0x0110
82#define CPMAC_MAC_CONTROL 0x0160
83# define MAC_TXPTYPE 0x00000200
84# define MAC_TXPACE 0x00000040
85# define MAC_MII 0x00000020
86# define MAC_TXFLOW 0x00000010
87# define MAC_RXFLOW 0x00000008
88# define MAC_MTEST 0x00000004
89# define MAC_LOOPBACK 0x00000002
90# define MAC_FDX 0x00000001
91#define CPMAC_MAC_STATUS 0x0164
92# define MAC_STATUS_QOS 0x00000004
93# define MAC_STATUS_RXFLOW 0x00000002
94# define MAC_STATUS_TXFLOW 0x00000001
95#define CPMAC_TX_INT_ENABLE 0x0178
96#define CPMAC_TX_INT_CLEAR 0x017c
97#define CPMAC_MAC_INT_VECTOR 0x0180
98# define MAC_INT_STATUS 0x00080000
99# define MAC_INT_HOST 0x00040000
100# define MAC_INT_RX 0x00020000
101# define MAC_INT_TX 0x00010000
102#define CPMAC_MAC_EOI_VECTOR 0x0184
103#define CPMAC_RX_INT_ENABLE 0x0198
104#define CPMAC_RX_INT_CLEAR 0x019c
105#define CPMAC_MAC_INT_ENABLE 0x01a8
106#define CPMAC_MAC_INT_CLEAR 0x01ac
107#define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
108#define CPMAC_MAC_ADDR_MID 0x01d0
109#define CPMAC_MAC_ADDR_HI 0x01d4
110#define CPMAC_MAC_HASH_LO 0x01d8
111#define CPMAC_MAC_HASH_HI 0x01dc
112#define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
113#define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
114#define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
115#define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
116#define CPMAC_REG_END 0x0680
117/*
118 * Rx/Tx statistics
119 * TODO: use some of them to fill stats in cpmac_stats()
120 */
121#define CPMAC_STATS_RX_GOOD 0x0200
122#define CPMAC_STATS_RX_BCAST 0x0204
123#define CPMAC_STATS_RX_MCAST 0x0208
124#define CPMAC_STATS_RX_PAUSE 0x020c
125#define CPMAC_STATS_RX_CRC 0x0210
126#define CPMAC_STATS_RX_ALIGN 0x0214
127#define CPMAC_STATS_RX_OVER 0x0218
128#define CPMAC_STATS_RX_JABBER 0x021c
129#define CPMAC_STATS_RX_UNDER 0x0220
130#define CPMAC_STATS_RX_FRAG 0x0224
131#define CPMAC_STATS_RX_FILTER 0x0228
132#define CPMAC_STATS_RX_QOSFILTER 0x022c
133#define CPMAC_STATS_RX_OCTETS 0x0230
134
135#define CPMAC_STATS_TX_GOOD 0x0234
136#define CPMAC_STATS_TX_BCAST 0x0238
137#define CPMAC_STATS_TX_MCAST 0x023c
138#define CPMAC_STATS_TX_PAUSE 0x0240
139#define CPMAC_STATS_TX_DEFER 0x0244
140#define CPMAC_STATS_TX_COLLISION 0x0248
141#define CPMAC_STATS_TX_SINGLECOLL 0x024c
142#define CPMAC_STATS_TX_MULTICOLL 0x0250
143#define CPMAC_STATS_TX_EXCESSCOLL 0x0254
144#define CPMAC_STATS_TX_LATECOLL 0x0258
145#define CPMAC_STATS_TX_UNDERRUN 0x025c
146#define CPMAC_STATS_TX_CARRIERSENSE 0x0260
147#define CPMAC_STATS_TX_OCTETS 0x0264
148
149#define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
150#define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
151 (reg)))
152
153/* MDIO bus */
154#define CPMAC_MDIO_VERSION 0x0000
155#define CPMAC_MDIO_CONTROL 0x0004
156# define MDIOC_IDLE 0x80000000
157# define MDIOC_ENABLE 0x40000000
158# define MDIOC_PREAMBLE 0x00100000
159# define MDIOC_FAULT 0x00080000
160# define MDIOC_FAULTDETECT 0x00040000
161# define MDIOC_INTTEST 0x00020000
162# define MDIOC_CLKDIV(div) ((div) & 0xff)
163#define CPMAC_MDIO_ALIVE 0x0008
164#define CPMAC_MDIO_LINK 0x000c
165#define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
166# define MDIO_BUSY 0x80000000
167# define MDIO_WRITE 0x40000000
168# define MDIO_REG(reg) (((reg) & 0x1f) << 21)
169# define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
170# define MDIO_DATA(data) ((data) & 0xffff)
171#define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
172# define PHYSEL_LINKSEL 0x00000040
173# define PHYSEL_LINKINT 0x00000020
174
175struct cpmac_desc {
176 u32 hw_next;
177 u32 hw_data;
178 u16 buflen;
179 u16 bufflags;
180 u16 datalen;
181 u16 dataflags;
182#define CPMAC_SOP 0x8000
183#define CPMAC_EOP 0x4000
184#define CPMAC_OWN 0x2000
185#define CPMAC_EOQ 0x1000
186 struct sk_buff *skb;
187 struct cpmac_desc *next;
188 dma_addr_t mapping;
189 dma_addr_t data_mapping;
190};
191
192struct cpmac_priv {
193 spinlock_t lock;
194 spinlock_t rx_lock;
195 struct cpmac_desc *rx_head;
196 int ring_size;
197 struct cpmac_desc *desc_ring;
198 dma_addr_t dma_ring;
199 void __iomem *regs;
200 struct mii_bus *mii_bus;
201 struct phy_device *phy;
202 char phy_name[BUS_ID_SIZE];
203 int oldlink, oldspeed, oldduplex;
204 u32 msg_enable;
205 struct net_device *dev;
206 struct work_struct reset_work;
207 struct platform_device *pdev;
208};
209
210static irqreturn_t cpmac_irq(int, void *);
211static void cpmac_hw_start(struct net_device *dev);
212static void cpmac_hw_stop(struct net_device *dev);
213static int cpmac_stop(struct net_device *dev);
214static int cpmac_open(struct net_device *dev);
215
216static void cpmac_dump_regs(struct net_device *dev)
217{
218 int i;
219 struct cpmac_priv *priv = netdev_priv(dev);
220 for (i = 0; i < CPMAC_REG_END; i += 4) {
221 if (i % 16 == 0) {
222 if (i)
223 printk("\n");
224 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
225 priv->regs + i);
226 }
227 printk(" %08x", cpmac_read(priv->regs, i));
228 }
229 printk("\n");
230}
231
232static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
233{
234 int i;
235 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
236 for (i = 0; i < sizeof(*desc) / 4; i++)
237 printk(" %08x", ((u32 *)desc)[i]);
238 printk("\n");
239}
240
241static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
242{
243 int i;
244 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
245 for (i = 0; i < skb->len; i++) {
246 if (i % 16 == 0) {
247 if (i)
248 printk("\n");
249 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
250 skb->data + i);
251 }
252 printk(" %02x", ((u8 *)skb->data)[i]);
253 }
254 printk("\n");
255}
256
257static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
258{
259 u32 val;
260
261 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
262 cpu_relax();
263 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
264 MDIO_PHY(phy_id));
265 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
266 cpu_relax();
267 return MDIO_DATA(val);
268}
269
270static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
271 int reg, u16 val)
272{
273 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
274 cpu_relax();
275 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
276 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
277 return 0;
278}
279
280static int cpmac_mdio_reset(struct mii_bus *bus)
281{
282 ar7_device_reset(AR7_RESET_BIT_MDIO);
283 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
284 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
285 return 0;
286}
287
288static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
289
290static struct mii_bus cpmac_mii = {
291 .name = "cpmac-mii",
292 .read = cpmac_mdio_read,
293 .write = cpmac_mdio_write,
294 .reset = cpmac_mdio_reset,
295 .irq = mii_irqs,
296};
297
298static int cpmac_config(struct net_device *dev, struct ifmap *map)
299{
300 if (dev->flags & IFF_UP)
301 return -EBUSY;
302
303 /* Don't allow changing the I/O address */
304 if (map->base_addr != dev->base_addr)
305 return -EOPNOTSUPP;
306
307 /* ignore other fields */
308 return 0;
309}
310
311static void cpmac_set_multicast_list(struct net_device *dev)
312{
313 struct dev_mc_list *iter;
314 int i;
315 u8 tmp;
316 u32 mbp, bit, hash[2] = { 0, };
317 struct cpmac_priv *priv = netdev_priv(dev);
318
319 mbp = cpmac_read(priv->regs, CPMAC_MBP);
320 if (dev->flags & IFF_PROMISC) {
321 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
322 MBP_RXPROMISC);
323 } else {
324 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
325 if (dev->flags & IFF_ALLMULTI) {
326 /* enable all multicast mode */
327 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
328 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
329 } else {
330 /*
331 * cpmac uses some strange mac address hashing
332 * (not crc32)
333 */
334 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
335 i++, iter = iter->next) {
336 bit = 0;
337 tmp = iter->dmi_addr[0];
338 bit ^= (tmp >> 2) ^ (tmp << 4);
339 tmp = iter->dmi_addr[1];
340 bit ^= (tmp >> 4) ^ (tmp << 2);
341 tmp = iter->dmi_addr[2];
342 bit ^= (tmp >> 6) ^ tmp;
343 tmp = iter->dmi_addr[3];
344 bit ^= (tmp >> 2) ^ (tmp << 4);
345 tmp = iter->dmi_addr[4];
346 bit ^= (tmp >> 4) ^ (tmp << 2);
347 tmp = iter->dmi_addr[5];
348 bit ^= (tmp >> 6) ^ tmp;
349 bit &= 0x3f;
350 hash[bit / 32] |= 1 << (bit % 32);
351 }
352
353 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
354 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
355 }
356 }
357}
358
359static struct sk_buff *cpmac_rx_one(struct net_device *dev,
360 struct cpmac_priv *priv,
361 struct cpmac_desc *desc)
362{
363 struct sk_buff *skb, *result = NULL;
364
365 if (unlikely(netif_msg_hw(priv)))
366 cpmac_dump_desc(dev, desc);
367 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
368 if (unlikely(!desc->datalen)) {
369 if (netif_msg_rx_err(priv) && net_ratelimit())
370 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
371 dev->name);
372 return NULL;
373 }
374
375 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
376 if (likely(skb)) {
377 skb_reserve(skb, 2);
378 skb_put(desc->skb, desc->datalen);
379 desc->skb->protocol = eth_type_trans(desc->skb, dev);
380 desc->skb->ip_summed = CHECKSUM_NONE;
381 dev->stats.rx_packets++;
382 dev->stats.rx_bytes += desc->datalen;
383 result = desc->skb;
384 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
385 DMA_FROM_DEVICE);
386 desc->skb = skb;
387 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
388 CPMAC_SKB_SIZE,
389 DMA_FROM_DEVICE);
390 desc->hw_data = (u32)desc->data_mapping;
391 if (unlikely(netif_msg_pktdata(priv))) {
392 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
393 cpmac_dump_skb(dev, result);
394 }
395 } else {
396 if (netif_msg_rx_err(priv) && net_ratelimit())
397 printk(KERN_WARNING
398 "%s: low on skbs, dropping packet\n", dev->name);
399 dev->stats.rx_dropped++;
400 }
401
402 desc->buflen = CPMAC_SKB_SIZE;
403 desc->dataflags = CPMAC_OWN;
404
405 return result;
406}
407
408static int cpmac_poll(struct net_device *dev, int *budget)
409{
410 struct sk_buff *skb;
411 struct cpmac_desc *desc;
412 int received = 0, quota = min(dev->quota, *budget);
413 struct cpmac_priv *priv = netdev_priv(dev);
414
415 spin_lock(&priv->rx_lock);
416 if (unlikely(!priv->rx_head)) {
417 if (netif_msg_rx_err(priv) && net_ratelimit())
418 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
419 dev->name);
420 netif_rx_complete(dev);
421 return 0;
422 }
423
424 desc = priv->rx_head;
425 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
426 skb = cpmac_rx_one(dev, priv, desc);
427 if (likely(skb)) {
428 netif_receive_skb(skb);
429 received++;
430 }
431 desc = desc->next;
432 }
433
434 priv->rx_head = desc;
435 spin_unlock(&priv->rx_lock);
436 *budget -= received;
437 dev->quota -= received;
438 if (unlikely(netif_msg_rx_status(priv)))
439 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
440 received);
441 if (desc->dataflags & CPMAC_OWN) {
442 netif_rx_complete(dev);
443 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
444 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
445 return 0;
446 }
447
448 return 1;
449}
450
451static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
452{
453 int queue, len;
454 struct cpmac_desc *desc;
455 struct cpmac_priv *priv = netdev_priv(dev);
456
6cd043d9
MC		 457 if (unlikely(skb_padto(skb, ETH_ZLEN)))
458 return NETDEV_TX_OK;
d95b39c3
MC		 459
460 len = max(skb->len, ETH_ZLEN);
6cd043d9 461 queue = skb->queue_mapping;
d95b39c3
MC		 462#ifdef CONFIG_NETDEVICES_MULTIQUEUE
463 netif_stop_subqueue(dev, queue);
464#else
465 netif_stop_queue(dev);
466#endif
467
468 desc = &priv->desc_ring[queue];
469 if (unlikely(desc->dataflags & CPMAC_OWN)) {
470 if (netif_msg_tx_err(priv) && net_ratelimit())
6cd043d9 471 printk(KERN_WARNING "%s: tx dma ring full\n",
d95b39c3 472 dev->name);
6cd043d9 473 return NETDEV_TX_BUSY;
d95b39c3
MC		 474 }
475
476 spin_lock(&priv->lock);
477 dev->trans_start = jiffies;
478 spin_unlock(&priv->lock);
479 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
480 desc->skb = skb;
481 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
482 DMA_TO_DEVICE);
483 desc->hw_data = (u32)desc->data_mapping;
484 desc->datalen = len;
485 desc->buflen = len;
486 if (unlikely(netif_msg_tx_queued(priv)))
487 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
488 skb->len);
489 if (unlikely(netif_msg_hw(priv)))
490 cpmac_dump_desc(dev, desc);
491 if (unlikely(netif_msg_pktdata(priv)))
492 cpmac_dump_skb(dev, skb);
493 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
494
6cd043d9 495 return NETDEV_TX_OK;
d95b39c3
MC		 496}
497
498static void cpmac_end_xmit(struct net_device *dev, int queue)
499{
500 struct cpmac_desc *desc;
501 struct cpmac_priv *priv = netdev_priv(dev);
502
503 desc = &priv->desc_ring[queue];
504 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
505 if (likely(desc->skb)) {
506 spin_lock(&priv->lock);
507 dev->stats.tx_packets++;
508 dev->stats.tx_bytes += desc->skb->len;
509 spin_unlock(&priv->lock);
510 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
511 DMA_TO_DEVICE);
512
513 if (unlikely(netif_msg_tx_done(priv)))
514 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
515 desc->skb, desc->skb->len);
516
517 dev_kfree_skb_irq(desc->skb);
518 desc->skb = NULL;
519#ifdef CONFIG_NETDEVICES_MULTIQUEUE
520 if (netif_subqueue_stopped(dev, queue))
521 netif_wake_subqueue(dev, queue);
522#else
523 if (netif_queue_stopped(dev))
524 netif_wake_queue(dev);
525#endif
526 } else {
527 if (netif_msg_tx_err(priv) && net_ratelimit())
528 printk(KERN_WARNING
529 "%s: end_xmit: spurious interrupt\n", dev->name);
530#ifdef CONFIG_NETDEVICES_MULTIQUEUE
531 if (netif_subqueue_stopped(dev, queue))
532 netif_wake_subqueue(dev, queue);
533#else
534 if (netif_queue_stopped(dev))
535 netif_wake_queue(dev);
536#endif
537 }
538}
539
540static void cpmac_hw_stop(struct net_device *dev)
541{
542 int i;
543 struct cpmac_priv *priv = netdev_priv(dev);
544 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
545
546 ar7_device_reset(pdata->reset_bit);
547 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
548 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
549 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
550 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
551 for (i = 0; i < 8; i++) {
552 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
553 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
554 }
555 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
556 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
557 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
558 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
559 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
560 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
561}
562
563static void cpmac_hw_start(struct net_device *dev)
564{
565 int i;
566 struct cpmac_priv *priv = netdev_priv(dev);
567 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
568
569 ar7_device_reset(pdata->reset_bit);
570 for (i = 0; i < 8; i++) {
571 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
572 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
573 }
574 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
575
576 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
577 MBP_RXMCAST);
578 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
579 for (i = 0; i < 8; i++)
580 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
581 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
582 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
583 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
584 (dev->dev_addr[3] << 24));
585 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
586 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
587 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
588 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
589 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
590 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
591 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
592 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
593 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
594
595 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
596 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
597 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
598 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
599 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
600 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
601 MAC_FDX);
602}
603
604static void cpmac_clear_rx(struct net_device *dev)
605{
606 struct cpmac_priv *priv = netdev_priv(dev);
607 struct cpmac_desc *desc;
608 int i;
609 if (unlikely(!priv->rx_head))
610 return;
611 desc = priv->rx_head;
612 for (i = 0; i < priv->ring_size; i++) {
613 if ((desc->dataflags & CPMAC_OWN) == 0) {
614 if (netif_msg_rx_err(priv) && net_ratelimit())
615 printk(KERN_WARNING "%s: packet dropped\n",
616 dev->name);
617 if (unlikely(netif_msg_hw(priv)))
618 cpmac_dump_desc(dev, desc);
619 desc->dataflags = CPMAC_OWN;
620 dev->stats.rx_dropped++;
621 }
622 desc = desc->next;
623 }
624}
625
626static void cpmac_clear_tx(struct net_device *dev)
627{
628 struct cpmac_priv *priv = netdev_priv(dev);
629 int i;
630 if (unlikely(!priv->desc_ring))
631 return;
6cd043d9
MC		 632 for (i = 0; i < CPMAC_QUEUES; i++) {
633 priv->desc_ring[i].dataflags = 0;
d95b39c3
MC		 634 if (priv->desc_ring[i].skb) {
635 dev_kfree_skb_any(priv->desc_ring[i].skb);
636 if (netif_subqueue_stopped(dev, i))
637 netif_wake_subqueue(dev, i);
638 }
6cd043d9 639 }
d95b39c3
MC		 640}
641
642static void cpmac_hw_error(struct work_struct *work)
643{
644 struct cpmac_priv *priv =
645 container_of(work, struct cpmac_priv, reset_work);
646
647 spin_lock(&priv->rx_lock);
648 cpmac_clear_rx(priv->dev);
649 spin_unlock(&priv->rx_lock);
650 cpmac_clear_tx(priv->dev);
651 cpmac_hw_start(priv->dev);
652 netif_start_queue(priv->dev);
653}
654
655static irqreturn_t cpmac_irq(int irq, void *dev_id)
656{
657 struct net_device *dev = dev_id;
658 struct cpmac_priv *priv;
659 int queue;
660 u32 status;
661
662 if (!dev)
663 return IRQ_NONE;
664
665 priv = netdev_priv(dev);
666
667 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
668
669 if (unlikely(netif_msg_intr(priv)))
670 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
671 status);
672
673 if (status & MAC_INT_TX)
674 cpmac_end_xmit(dev, (status & 7));
675
676 if (status & MAC_INT_RX) {
677 queue = (status >> 8) & 7;
678 netif_rx_schedule(dev);
679 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
680 }
681
682 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
683
684 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
685 if (netif_msg_drv(priv) && net_ratelimit())
686 printk(KERN_ERR "%s: hw error, resetting...\n",
687 dev->name);
688 netif_stop_queue(dev);
689 cpmac_hw_stop(dev);
690 schedule_work(&priv->reset_work);
691 if (unlikely(netif_msg_hw(priv)))
692 cpmac_dump_regs(dev);
693 }
694
695 return IRQ_HANDLED;
696}
697
698static void cpmac_tx_timeout(struct net_device *dev)
699{
700 struct cpmac_priv *priv = netdev_priv(dev);
701 int i;
702
703 spin_lock(&priv->lock);
704 dev->stats.tx_errors++;
705 spin_unlock(&priv->lock);
706 if (netif_msg_tx_err(priv) && net_ratelimit())
707 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
708 /*
709 * FIXME: waking up random queue is not the best thing to
710 * do... on the other hand why we got here at all?
711 */
712#ifdef CONFIG_NETDEVICES_MULTIQUEUE
713 for (i = 0; i < CPMAC_QUEUES; i++)
714 if (priv->desc_ring[i].skb) {
6cd043d9 715 priv->desc_ring[i].dataflags = 0;
d95b39c3
MC		 716 dev_kfree_skb_any(priv->desc_ring[i].skb);
717 netif_wake_subqueue(dev, i);
718 break;
719 }
720#else
6cd043d9 721 priv->desc_ring[0].dataflags = 0;
d95b39c3
MC		 722 if (priv->desc_ring[0].skb)
723 dev_kfree_skb_any(priv->desc_ring[0].skb);
724 netif_wake_queue(dev);
725#endif
726}
727
728static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
729{
730 struct cpmac_priv *priv = netdev_priv(dev);
731 if (!(netif_running(dev)))
732 return -EINVAL;
733 if (!priv->phy)
734 return -EINVAL;
735 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
736 (cmd == SIOCSMIIREG))
737 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
738
739 return -EOPNOTSUPP;
740}
741
742static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
743{
744 struct cpmac_priv *priv = netdev_priv(dev);
745
746 if (priv->phy)
747 return phy_ethtool_gset(priv->phy, cmd);
748
749 return -EINVAL;
750}
751
752static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
753{
754 struct cpmac_priv *priv = netdev_priv(dev);
755
756 if (!capable(CAP_NET_ADMIN))
757 return -EPERM;
758
759 if (priv->phy)
760 return phy_ethtool_sset(priv->phy, cmd);
761
762 return -EINVAL;
763}
764
765static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
766{
767 struct cpmac_priv *priv = netdev_priv(dev);
768
769 ring->rx_max_pending = 1024;
770 ring->rx_mini_max_pending = 1;
771 ring->rx_jumbo_max_pending = 1;
772 ring->tx_max_pending = 1;
773
774 ring->rx_pending = priv->ring_size;
775 ring->rx_mini_pending = 1;
776 ring->rx_jumbo_pending = 1;
777 ring->tx_pending = 1;
778}
779
780static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
781{
782 struct cpmac_priv *priv = netdev_priv(dev);
783
6cd043d9 784 if (netif_running(dev))
d95b39c3
MC		 785 return -EBUSY;
786 priv->ring_size = ring->rx_pending;
787 return 0;
788}
789
790static void cpmac_get_drvinfo(struct net_device *dev,
791 struct ethtool_drvinfo *info)
792{
793 strcpy(info->driver, "cpmac");
794 strcpy(info->version, CPMAC_VERSION);
795 info->fw_version[0] = '\0';
796 sprintf(info->bus_info, "%s", "cpmac");
797 info->regdump_len = 0;
798}
799
800static const struct ethtool_ops cpmac_ethtool_ops = {
801 .get_settings = cpmac_get_settings,
802 .set_settings = cpmac_set_settings,
803 .get_drvinfo = cpmac_get_drvinfo,
804 .get_link = ethtool_op_get_link,
805 .get_ringparam = cpmac_get_ringparam,
806 .set_ringparam = cpmac_set_ringparam,
807};
808
809static void cpmac_adjust_link(struct net_device *dev)
810{
811 struct cpmac_priv *priv = netdev_priv(dev);
812 int new_state = 0;
813
814 spin_lock(&priv->lock);
815 if (priv->phy->link) {
816 netif_start_queue(dev);
817 if (priv->phy->duplex != priv->oldduplex) {
818 new_state = 1;
819 priv->oldduplex = priv->phy->duplex;
820 }
821
822 if (priv->phy->speed != priv->oldspeed) {
823 new_state = 1;
824 priv->oldspeed = priv->phy->speed;
825 }
826
827 if (!priv->oldlink) {
828 new_state = 1;
829 priv->oldlink = 1;
830 netif_schedule(dev);
831 }
832 } else if (priv->oldlink) {
833 netif_stop_queue(dev);
834 new_state = 1;
835 priv->oldlink = 0;
836 priv->oldspeed = 0;
837 priv->oldduplex = -1;
838 }
839
840 if (new_state && netif_msg_link(priv) && net_ratelimit())
841 phy_print_status(priv->phy);
842
843 spin_unlock(&priv->lock);
844}
845
846static int cpmac_open(struct net_device *dev)
847{
848 int i, size, res;
849 struct cpmac_priv *priv = netdev_priv(dev);
850 struct resource *mem;
851 struct cpmac_desc *desc;
852 struct sk_buff *skb;
853
854 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
855 0, PHY_INTERFACE_MODE_MII);
856 if (IS_ERR(priv->phy)) {
857 if (netif_msg_drv(priv))
858 printk(KERN_ERR "%s: Could not attach to PHY\n",
859 dev->name);
860 return PTR_ERR(priv->phy);
861 }
862
863 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
864 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
865 if (netif_msg_drv(priv))
866 printk(KERN_ERR "%s: failed to request registers\n",
867 dev->name);
868 res = -ENXIO;
869 goto fail_reserve;
870 }
871
872 priv->regs = ioremap(mem->start, mem->end - mem->start);
873 if (!priv->regs) {
874 if (netif_msg_drv(priv))
875 printk(KERN_ERR "%s: failed to remap registers\n",
876 dev->name);
877 res = -ENXIO;
878 goto fail_remap;
879 }
880
881 size = priv->ring_size + CPMAC_QUEUES;
882 priv->desc_ring = dma_alloc_coherent(&dev->dev,
883 sizeof(struct cpmac_desc) * size,
884 &priv->dma_ring,
885 GFP_KERNEL);
886 if (!priv->desc_ring) {
887 res = -ENOMEM;
888 goto fail_alloc;
889 }
890
891 for (i = 0; i < size; i++)
892 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
893
894 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
895 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
896 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
897 if (unlikely(!skb)) {
898 res = -ENOMEM;
899 goto fail_desc;
900 }
901 skb_reserve(skb, 2);
902 desc->skb = skb;
903 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
904 CPMAC_SKB_SIZE,
905 DMA_FROM_DEVICE);
906 desc->hw_data = (u32)desc->data_mapping;
907 desc->buflen = CPMAC_SKB_SIZE;
908 desc->dataflags = CPMAC_OWN;
909 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
910 desc->hw_next = (u32)desc->next->mapping;
911 }
912
913 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
914 dev->name, dev))) {
915 if (netif_msg_drv(priv))
916 printk(KERN_ERR "%s: failed to obtain irq\n",
917 dev->name);
918 goto fail_irq;
919 }
920
921 INIT_WORK(&priv->reset_work, cpmac_hw_error);
922 cpmac_hw_start(dev);
923
924 priv->phy->state = PHY_CHANGELINK;
925 phy_start(priv->phy);
926
927 return 0;
928
929fail_irq:
930fail_desc:
931 for (i = 0; i < priv->ring_size; i++) {
932 if (priv->rx_head[i].skb) {
933 dma_unmap_single(&dev->dev,
934 priv->rx_head[i].data_mapping,
935 CPMAC_SKB_SIZE,
936 DMA_FROM_DEVICE);
937 kfree_skb(priv->rx_head[i].skb);
938 }
939 }
940fail_alloc:
941 kfree(priv->desc_ring);
942 iounmap(priv->regs);
943
944fail_remap:
945 release_mem_region(mem->start, mem->end - mem->start);
946
947fail_reserve:
948 phy_disconnect(priv->phy);
949
950 return res;
951}
952
953static int cpmac_stop(struct net_device *dev)
954{
955 int i;
956 struct cpmac_priv *priv = netdev_priv(dev);
957 struct resource *mem;
958
959 netif_stop_queue(dev);
960
961 cancel_work_sync(&priv->reset_work);
962 phy_stop(priv->phy);
963 phy_disconnect(priv->phy);
964 priv->phy = NULL;
965
966 cpmac_hw_stop(dev);
967
968 for (i = 0; i < 8; i++)
969 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
970 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
971 cpmac_write(priv->regs, CPMAC_MBP, 0);
972
973 free_irq(dev->irq, dev);
974 iounmap(priv->regs);
975 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
976 release_mem_region(mem->start, mem->end - mem->start);
977 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
978 for (i = 0; i < priv->ring_size; i++) {
979 if (priv->rx_head[i].skb) {
980 dma_unmap_single(&dev->dev,
981 priv->rx_head[i].data_mapping,
982 CPMAC_SKB_SIZE,
983 DMA_FROM_DEVICE);
984 kfree_skb(priv->rx_head[i].skb);
985 }
986 }
987
988 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
989 (CPMAC_QUEUES + priv->ring_size),
990 priv->desc_ring, priv->dma_ring);
991 return 0;
992}
993
994static int external_switch;
995
996static int __devinit cpmac_probe(struct platform_device *pdev)
997{
998 int rc, phy_id;
999 struct resource *mem;
1000 struct cpmac_priv *priv;
1001 struct net_device *dev;
1002 struct plat_cpmac_data *pdata;
df523b5c 1003 DECLARE_MAC_BUF(mac);
d95b39c3
MC		 1004
1005 pdata = pdev->dev.platform_data;
1006
1007 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1008 if (!(pdata->phy_mask & (1 << phy_id)))
1009 continue;
1010 if (!cpmac_mii.phy_map[phy_id])
1011 continue;
1012 break;
1013 }
1014
1015 if (phy_id == PHY_MAX_ADDR) {
1016 if (external_switch || dumb_switch)
1017 phy_id = 0;
1018 else {
1019 printk(KERN_ERR "cpmac: no PHY present\n");
1020 return -ENODEV;
1021 }
1022 }
1023
1024 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1025
1026 if (!dev) {
1027 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1028 return -ENOMEM;
1029 }
1030
1031 platform_set_drvdata(pdev, dev);
1032 priv = netdev_priv(dev);
1033
1034 priv->pdev = pdev;
1035 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1036 if (!mem) {
1037 rc = -ENODEV;
1038 goto fail;
1039 }
1040
1041 dev->irq = platform_get_irq_byname(pdev, "irq");
1042
1043 dev->open = cpmac_open;
1044 dev->stop = cpmac_stop;
1045 dev->set_config = cpmac_config;
1046 dev->hard_start_xmit = cpmac_start_xmit;
1047 dev->do_ioctl = cpmac_ioctl;
1048 dev->set_multicast_list = cpmac_set_multicast_list;
1049 dev->tx_timeout = cpmac_tx_timeout;
1050 dev->ethtool_ops = &cpmac_ethtool_ops;
1051 dev->poll = cpmac_poll;
1052 dev->weight = 64;
1053 dev->features |= NETIF_F_MULTI_QUEUE;
1054
1055 spin_lock_init(&priv->lock);
1056 spin_lock_init(&priv->rx_lock);
1057 priv->dev = dev;
1058 priv->ring_size = 64;
1059 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1060 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1061 if (phy_id == 31) {
1062 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1063 cpmac_mii.id, phy_id);
1064 } else
1065 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1066
1067 if ((rc = register_netdev(dev))) {
1068 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1069 dev->name);
1070 goto fail;
1071 }
1072
1073 if (netif_msg_probe(priv)) {
1074 printk(KERN_INFO
df523b5c
EK		 1075 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1076 "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1077 priv->phy_name, print_mac(mac, dev->dev_addr));
d95b39c3
MC		 1078 }
1079 return 0;
1080
1081fail:
1082 free_netdev(dev);
1083 return rc;
1084}
1085
1086static int __devexit cpmac_remove(struct platform_device *pdev)
1087{
1088 struct net_device *dev = platform_get_drvdata(pdev);
1089 unregister_netdev(dev);
1090 free_netdev(dev);
1091 return 0;
1092}
1093
1094static struct platform_driver cpmac_driver = {
1095 .driver.name = "cpmac",
1096 .probe = cpmac_probe,
1097 .remove = __devexit_p(cpmac_remove),
1098};
1099
1100int __devinit cpmac_init(void)
1101{
1102 u32 mask;
1103 int i, res;
1104
1105 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1106
1107 if (!cpmac_mii.priv) {
1108 printk(KERN_ERR "Can't ioremap mdio registers\n");
1109 return -ENXIO;
1110 }
1111
1112#warning FIXME: unhardcode gpio&reset bits
1113 ar7_gpio_disable(26);
1114 ar7_gpio_disable(27);
1115 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1116 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1117 ar7_device_reset(AR7_RESET_BIT_EPHY);
1118
1119 cpmac_mii.reset(&cpmac_mii);
1120
1121 for (i = 0; i < 300000; i++)
1122 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1123 break;
1124 else
1125 cpu_relax();
1126
1127 mask &= 0x7fffffff;
1128 if (mask & (mask - 1)) {
1129 external_switch = 1;
1130 mask = 0;
1131 }
1132
1133 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1134
1135 res = mdiobus_register(&cpmac_mii);
1136 if (res)
1137 goto fail_mii;
1138
1139 res = platform_driver_register(&cpmac_driver);
1140 if (res)
1141 goto fail_cpmac;
1142
1143 return 0;
1144
1145fail_cpmac:
1146 mdiobus_unregister(&cpmac_mii);
1147
1148fail_mii:
1149 iounmap(cpmac_mii.priv);
1150
1151 return res;
1152}
1153
1154void __devexit cpmac_exit(void)
1155{
1156 platform_driver_unregister(&cpmac_driver);
1157 mdiobus_unregister(&cpmac_mii);
1158 iounmap(cpmac_mii.priv);
1159}
1160
1161module_init(cpmac_init);
1162module_exit(cpmac_exit);
Linux kernel - Deliverables
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