[deliverable/linux.git] / drivers / net / cxgb3 / adapter.h

/*
 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/* This file should not be included directly.  Include common.h instead. */

#ifndef __T3_ADAPTER_H__
#define __T3_ADAPTER_H__

#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/cache.h>
#include <linux/mutex.h>
#include <linux/bitops.h>
#include "t3cdev.h"
#include <asm/io.h>

struct vlan_group;
struct adapter;
struct sge_qset;
struct port_info;

enum mac_idx_types {
	LAN_MAC_IDX	= 0,
	SAN_MAC_IDX,

	MAX_MAC_IDX
};

struct iscsi_config {
	__u8	mac_addr[ETH_ALEN];
	__u32	flags;
	int (*send)(struct port_info *pi, struct sk_buff **skb);
	int (*recv)(struct port_info *pi, struct sk_buff *skb);
};

struct port_info {
	struct adapter *adapter;
	struct vlan_group *vlan_grp;
	struct sge_qset *qs;
	u8 port_id;
	u8 nqsets;
	u8 first_qset;
	struct cphy phy;
	struct cmac mac;
	struct link_config link_config;
	struct net_device_stats netstats;
	int activity;
	__be32 iscsi_ipv4addr;
	struct iscsi_config iscsic;

	int link_fault; /* link fault was detected */
};

enum {				/* adapter flags */
	FULL_INIT_DONE = (1 << 0),
	USING_MSI = (1 << 1),
	USING_MSIX = (1 << 2),
	QUEUES_BOUND = (1 << 3),
	TP_PARITY_INIT = (1 << 4),
	NAPI_INIT = (1 << 5),
};

struct fl_pg_chunk {
	struct page *page;
	void *va;
	unsigned int offset;
	unsigned long *p_cnt;
	dma_addr_t mapping;
};

struct rx_desc;
struct rx_sw_desc;

struct sge_fl {                     /* SGE per free-buffer list state */
	unsigned int buf_size;      /* size of each Rx buffer */
	unsigned int credits;       /* # of available Rx buffers */
	unsigned int pend_cred;     /* new buffers since last FL DB ring */
	unsigned int size;          /* capacity of free list */
	unsigned int cidx;          /* consumer index */
	unsigned int pidx;          /* producer index */
	unsigned int gen;           /* free list generation */
	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
	unsigned int order;	    /* order of page allocations */
	unsigned int alloc_size;    /* size of allocated buffer */
	struct rx_desc *desc;       /* address of HW Rx descriptor ring */
	struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
	dma_addr_t   phys_addr;     /* physical address of HW ring start */
	unsigned int cntxt_id;      /* SGE context id for the free list */
	unsigned long empty;        /* # of times queue ran out of buffers */
	unsigned long alloc_failed; /* # of times buffer allocation failed */
};

/*
 * Bundle size for grouping offload RX packets for delivery to the stack.
 * Don't make this too big as we do prefetch on each packet in a bundle.
 */
# define RX_BUNDLE_SIZE 8

struct rsp_desc;

struct sge_rspq {		/* state for an SGE response queue */
	unsigned int credits;	/* # of pending response credits */
	unsigned int size;	/* capacity of response queue */
	unsigned int cidx;	/* consumer index */
	unsigned int gen;	/* current generation bit */
	unsigned int polling;	/* is the queue serviced through NAPI? */
	unsigned int holdoff_tmr;	/* interrupt holdoff timer in 100ns */
	unsigned int next_holdoff;	/* holdoff time for next interrupt */
	unsigned int rx_recycle_buf; /* whether recycling occurred
					within current sop-eop */
	struct rsp_desc *desc;	/* address of HW response ring */
	dma_addr_t phys_addr;	/* physical address of the ring */
	unsigned int cntxt_id;	/* SGE context id for the response q */
	spinlock_t lock;	/* guards response processing */
	struct sk_buff_head rx_queue; /* offload packet receive queue */
	struct sk_buff *pg_skb; /* used to build frag list in napi handler */

	unsigned long offload_pkts;
	unsigned long offload_bundles;
	unsigned long eth_pkts;	/* # of ethernet packets */
	unsigned long pure_rsps;	/* # of pure (non-data) responses */
	unsigned long imm_data;	/* responses with immediate data */
	unsigned long rx_drops;	/* # of packets dropped due to no mem */
	unsigned long async_notif; /* # of asynchronous notification events */
	unsigned long empty;	/* # of times queue ran out of credits */
	unsigned long nomem;	/* # of responses deferred due to no mem */
	unsigned long unhandled_irqs;	/* # of spurious intrs */
	unsigned long starved;
	unsigned long restarted;
};

struct tx_desc;
struct tx_sw_desc;

struct sge_txq {		/* state for an SGE Tx queue */
	unsigned long flags;	/* HW DMA fetch status */
	unsigned int in_use;	/* # of in-use Tx descriptors */
	unsigned int size;	/* # of descriptors */
	unsigned int processed;	/* total # of descs HW has processed */
	unsigned int cleaned;	/* total # of descs SW has reclaimed */
	unsigned int stop_thres;	/* SW TX queue suspend threshold */
	unsigned int cidx;	/* consumer index */
	unsigned int pidx;	/* producer index */
	unsigned int gen;	/* current value of generation bit */
	unsigned int unacked;	/* Tx descriptors used since last COMPL */
	struct tx_desc *desc;	/* address of HW Tx descriptor ring */
	struct tx_sw_desc *sdesc;	/* address of SW Tx descriptor ring */
	spinlock_t lock;	/* guards enqueueing of new packets */
	unsigned int token;	/* WR token */
	dma_addr_t phys_addr;	/* physical address of the ring */
	struct sk_buff_head sendq;	/* List of backpressured offload packets */
	struct tasklet_struct qresume_tsk;	/* restarts the queue */
	unsigned int cntxt_id;	/* SGE context id for the Tx q */
	unsigned long stops;	/* # of times q has been stopped */
	unsigned long restarts;	/* # of queue restarts */
};

enum {				/* per port SGE statistics */
	SGE_PSTAT_TSO,		/* # of TSO requests */
	SGE_PSTAT_RX_CSUM_GOOD,	/* # of successful RX csum offloads */
	SGE_PSTAT_TX_CSUM,	/* # of TX checksum offloads */
	SGE_PSTAT_VLANEX,	/* # of VLAN tag extractions */
	SGE_PSTAT_VLANINS,	/* # of VLAN tag insertions */

	SGE_PSTAT_MAX		/* must be last */
};

struct napi_gro_fraginfo;

struct sge_qset {		/* an SGE queue set */
	struct adapter *adap;
	struct napi_struct napi;
	struct sge_rspq rspq;
	struct sge_fl fl[SGE_RXQ_PER_SET];
	struct sge_txq txq[SGE_TXQ_PER_SET];
	int nomem;
	void *lro_va;
	struct net_device *netdev;
	struct netdev_queue *tx_q;	/* associated netdev TX queue */
	unsigned long txq_stopped;	/* which Tx queues are stopped */
	struct timer_list tx_reclaim_timer;	/* reclaims TX buffers */
	struct timer_list rx_reclaim_timer;	/* reclaims RX buffers */
	unsigned long port_stats[SGE_PSTAT_MAX];
} ____cacheline_aligned;

struct sge {
	struct sge_qset qs[SGE_QSETS];
	spinlock_t reg_lock;	/* guards non-atomic SGE registers (eg context) */
};

struct adapter {
	struct t3cdev tdev;
	struct list_head adapter_list;
	void __iomem *regs;
	struct pci_dev *pdev;
	unsigned long registered_device_map;
	unsigned long open_device_map;
	unsigned long flags;

	const char *name;
	int msg_enable;
	unsigned int mmio_len;

	struct adapter_params params;
	unsigned int slow_intr_mask;
	unsigned long irq_stats[IRQ_NUM_STATS];

	int msix_nvectors;
	struct {
		unsigned short vec;
		char desc[22];
	} msix_info[SGE_QSETS + 1];

	/* T3 modules */
	struct sge sge;
	struct mc7 pmrx;
	struct mc7 pmtx;
	struct mc7 cm;
	struct mc5 mc5;

	struct net_device *port[MAX_NPORTS];
	unsigned int check_task_cnt;
	struct delayed_work adap_check_task;
	struct work_struct ext_intr_handler_task;
	struct work_struct fatal_error_handler_task;
	struct work_struct link_fault_handler_task;

	struct work_struct db_full_task;
	struct work_struct db_empty_task;
	struct work_struct db_drop_task;

	struct dentry *debugfs_root;

	struct mutex mdio_lock;
	spinlock_t stats_lock;
	spinlock_t work_lock;

	struct sk_buff *nofail_skb;
};

static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
{
	u32 val = readl(adapter->regs + reg_addr);

	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
	return val;
}

static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
{
	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
	writel(val, adapter->regs + reg_addr);
}

static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
{
	return netdev_priv(adap->port[idx]);
}

static inline int phy2portid(struct cphy *phy)
{
	struct adapter *adap = phy->adapter;
	struct port_info *port0 = adap2pinfo(adap, 0);

	return &port0->phy == phy ? 0 : 1;
}

#define OFFLOAD_DEVMAP_BIT 15

#define tdev2adap(d) container_of(d, struct adapter, tdev)

static inline int offload_running(struct adapter *adapter)
{
	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
}

int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);

void t3_os_ext_intr_handler(struct adapter *adapter);
void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
			int speed, int duplex, int fc);
void t3_os_phymod_changed(struct adapter *adap, int port_id);
void t3_os_link_fault(struct adapter *adapter, int port_id, int state);
void t3_os_link_fault_handler(struct adapter *adapter, int port_id);

void t3_sge_start(struct adapter *adap);
void t3_sge_stop(struct adapter *adap);
void t3_start_sge_timers(struct adapter *adap);
void t3_stop_sge_timers(struct adapter *adap);
void t3_free_sge_resources(struct adapter *adap);
void t3_sge_err_intr_handler(struct adapter *adapter);
irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
		      int irq_vec_idx, const struct qset_params *p,
		      int ntxq, struct net_device *dev,
		      struct netdev_queue *netdevq);
extern struct workqueue_struct *cxgb3_wq;

int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);

#endif				/* __T3_ADAPTER_H__ */
Commit	Line	Data
4d22de3e	1	/*
a02d44a0	2	* Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e	3	*
1d68e93d DLR	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
4d22de3e	9	*
1d68e93d DLR	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
4d22de3e DLR	31	*/
	32
	33	/* This file should not be included directly. Include common.h instead. */
	34
	35	#ifndef __T3_ADAPTER_H__
	36	#define __T3_ADAPTER_H__
	37
	38	#include <linux/pci.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/interrupt.h>
	41	#include <linux/timer.h>
	42	#include <linux/cache.h>
a13fbee0	43	#include <linux/mutex.h>
1977f032	44	#include <linux/bitops.h>
4d22de3e	45	#include "t3cdev.h"
4d22de3e DLR	46	#include <asm/io.h>
4d22de3e DLR	47
4d22de3e	48	struct vlan_group;
5fbf816f	49	struct adapter;
bea3348e	50	struct sge_qset;
f14d42f3	51	struct port_info;
bea3348e	52
f14d42f3 KX	53	enum mac_idx_types {
	54	LAN_MAC_IDX = 0,
	55	SAN_MAC_IDX,
	56
	57	MAX_MAC_IDX
	58	};
	59
	60	struct iscsi_config {
	61	__u8 mac_addr[ETH_ALEN];
	62	__u32 flags;
	63	int (send)(struct port_info pi, struct sk_buff **skb);
	64	int (recv)(struct port_info pi, struct sk_buff *skb);
	65	};
	66
4d22de3e	67	struct port_info {
5fbf816f	68	struct adapter *adapter;
4d22de3e	69	struct vlan_group *vlan_grp;
bea3348e	70	struct sge_qset *qs;
4d22de3e	71	u8 port_id;
4d22de3e DLR	72	u8 nqsets;
	73	u8 first_qset;
	74	struct cphy phy;
	75	struct cmac mac;
	76	struct link_config link_config;
	77	struct net_device_stats netstats;
	78	int activity;
a109a5b9	79	__be32 iscsi_ipv4addr;
f14d42f3	80	struct iscsi_config iscsic;
bf792094 DLR	81
bf792094 DLR	82	int link_fault; /* link fault was detected */
4d22de3e DLR	83	};
	84
	85	enum { /* adapter flags */
	86	FULL_INIT_DONE = (1 << 0),
	87	USING_MSI = (1 << 1),
	88	USING_MSIX = (1 << 2),
14ab9892	89	QUEUES_BOUND = (1 << 3),
b881955b	90	TP_PARITY_INIT = (1 << 4),
48c4b6db	91	NAPI_INIT = (1 << 5),
4d22de3e DLR	92	};
4d22de3e DLR	93
cf992af5 DLR	94	struct fl_pg_chunk {
	95	struct page *page;
	96	void *va;
	97	unsigned int offset;
10b6d956 DLR	98	unsigned long *p_cnt;
10b6d956 DLR	99	dma_addr_t mapping;
cf992af5 DLR	100	};
cf992af5 DLR	101
4d22de3e DLR	102	struct rx_desc;
	103	struct rx_sw_desc;
	104
cf992af5 DLR	105	struct sge_fl { /* SGE per free-buffer list state */
	106	unsigned int buf_size; /* size of each Rx buffer */
	107	unsigned int credits; /* # of available Rx buffers */
26b3871d	108	unsigned int pend_cred; /* new buffers since last FL DB ring */
cf992af5 DLR	109	unsigned int size; /* capacity of free list */
	110	unsigned int cidx; /* consumer index */
	111	unsigned int pidx; /* producer index */
	112	unsigned int gen; /* free list generation */
	113	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	114	unsigned int use_pages; /* whether FL uses pages or sk_buffs */
7385ecf3	115	unsigned int order; /* order of page allocations */
5e68b772	116	unsigned int alloc_size; /* size of allocated buffer */
cf992af5 DLR	117	struct rx_desc desc; / address of HW Rx descriptor ring */
	118	struct rx_sw_desc sdesc; / address of SW Rx descriptor ring */
	119	dma_addr_t phys_addr; /* physical address of HW ring start */
	120	unsigned int cntxt_id; /* SGE context id for the free list */
	121	unsigned long empty; /* # of times queue ran out of buffers */
e0994eb1	122	unsigned long alloc_failed; /* # of times buffer allocation failed */
4d22de3e DLR	123	};
	124
	125	/*
	126	* Bundle size for grouping offload RX packets for delivery to the stack.
	127	* Don't make this too big as we do prefetch on each packet in a bundle.
	128	*/
	129	# define RX_BUNDLE_SIZE 8
	130
	131	struct rsp_desc;
	132
	133	struct sge_rspq { /* state for an SGE response queue */
	134	unsigned int credits; /* # of pending response credits */
	135	unsigned int size; /* capacity of response queue */
	136	unsigned int cidx; /* consumer index */
	137	unsigned int gen; /* current generation bit */
	138	unsigned int polling; /* is the queue serviced through NAPI? */
	139	unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
	140	unsigned int next_holdoff; /* holdoff time for next interrupt */
7385ecf3 DLR	141	unsigned int rx_recycle_buf; /* whether recycling occurred
7385ecf3 DLR	142	within current sop-eop */
4d22de3e DLR	143	struct rsp_desc desc; / address of HW response ring */
	144	dma_addr_t phys_addr; /* physical address of the ring */
	145	unsigned int cntxt_id; /* SGE context id for the response q */
	146	spinlock_t lock; /* guards response processing */
147e70e6	147	struct sk_buff_head rx_queue; /* offload packet receive queue */
7385ecf3	148	struct sk_buff pg_skb; / used to build frag list in napi handler */
4d22de3e DLR	149
	150	unsigned long offload_pkts;
	151	unsigned long offload_bundles;
	152	unsigned long eth_pkts; /* # of ethernet packets */
	153	unsigned long pure_rsps; /* # of pure (non-data) responses */
	154	unsigned long imm_data; /* responses with immediate data */
	155	unsigned long rx_drops; /* # of packets dropped due to no mem */
	156	unsigned long async_notif; /* # of asynchronous notification events */
	157	unsigned long empty; /* # of times queue ran out of credits */
	158	unsigned long nomem; /* # of responses deferred due to no mem */
	159	unsigned long unhandled_irqs; /* # of spurious intrs */
bae73f44 DLR	160	unsigned long starved;
bae73f44 DLR	161	unsigned long restarted;
4d22de3e DLR	162	};
	163
	164	struct tx_desc;
	165	struct tx_sw_desc;
	166
	167	struct sge_txq { /* state for an SGE Tx queue */
	168	unsigned long flags; /* HW DMA fetch status */
	169	unsigned int in_use; /* # of in-use Tx descriptors */
	170	unsigned int size; /* # of descriptors */
	171	unsigned int processed; /* total # of descs HW has processed */
	172	unsigned int cleaned; /* total # of descs SW has reclaimed */
	173	unsigned int stop_thres; /* SW TX queue suspend threshold */
	174	unsigned int cidx; /* consumer index */
	175	unsigned int pidx; /* producer index */
	176	unsigned int gen; /* current value of generation bit */
	177	unsigned int unacked; /* Tx descriptors used since last COMPL */
	178	struct tx_desc desc; / address of HW Tx descriptor ring */
	179	struct tx_sw_desc sdesc; / address of SW Tx descriptor ring */
	180	spinlock_t lock; /* guards enqueueing of new packets */
	181	unsigned int token; /* WR token */
	182	dma_addr_t phys_addr; /* physical address of the ring */
	183	struct sk_buff_head sendq; /* List of backpressured offload packets */
	184	struct tasklet_struct qresume_tsk; /* restarts the queue */
	185	unsigned int cntxt_id; /* SGE context id for the Tx q */
	186	unsigned long stops; /* # of times q has been stopped */
	187	unsigned long restarts; /* # of queue restarts */
	188	};
	189
	190	enum { /* per port SGE statistics */
	191	SGE_PSTAT_TSO, /* # of TSO requests */
	192	SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
	193	SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
	194	SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
	195	SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
	196
	197	SGE_PSTAT_MAX /* must be last */
	198	};
	199
7be2df45	200	struct napi_gro_fraginfo;
b47385bd	201
4d22de3e	202	struct sge_qset { /* an SGE queue set */
bea3348e SH	203	struct adapter *adap;
bea3348e SH	204	struct napi_struct napi;
4d22de3e DLR	205	struct sge_rspq rspq;
	206	struct sge_fl fl[SGE_RXQ_PER_SET];
	207	struct sge_txq txq[SGE_TXQ_PER_SET];
76620aaf	208	int nomem;
b47385bd	209	void *lro_va;
bea3348e	210	struct net_device *netdev;
82ad3329	211	struct netdev_queue tx_q; / associated netdev TX queue */
4d22de3e DLR	212	unsigned long txq_stopped; /* which Tx queues are stopped */
4d22de3e DLR	213	struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
42c8ea17	214	struct timer_list rx_reclaim_timer; /* reclaims RX buffers */
4d22de3e DLR	215	unsigned long port_stats[SGE_PSTAT_MAX];
	216	} ____cacheline_aligned;
	217
	218	struct sge {
	219	struct sge_qset qs[SGE_QSETS];
	220	spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */
	221	};
	222
	223	struct adapter {
	224	struct t3cdev tdev;
	225	struct list_head adapter_list;
	226	void __iomem *regs;
	227	struct pci_dev *pdev;
	228	unsigned long registered_device_map;
	229	unsigned long open_device_map;
	230	unsigned long flags;
	231
	232	const char *name;
	233	int msg_enable;
	234	unsigned int mmio_len;
	235
	236	struct adapter_params params;
	237	unsigned int slow_intr_mask;
	238	unsigned long irq_stats[IRQ_NUM_STATS];
	239
5cda9364	240	int msix_nvectors;
4d22de3e DLR	241	struct {
	242	unsigned short vec;
	243	char desc[22];
	244	} msix_info[SGE_QSETS + 1];
	245
	246	/* T3 modules */
	247	struct sge sge;
	248	struct mc7 pmrx;
	249	struct mc7 pmtx;
	250	struct mc7 cm;
	251	struct mc5 mc5;
	252
	253	struct net_device *port[MAX_NPORTS];
	254	unsigned int check_task_cnt;
	255	struct delayed_work adap_check_task;
	256	struct work_struct ext_intr_handler_task;
20d3fc11	257	struct work_struct fatal_error_handler_task;
bf792094	258	struct work_struct link_fault_handler_task;
4d22de3e	259
e998f245 SW	260	struct work_struct db_full_task;
	261	struct work_struct db_empty_task;
	262	struct work_struct db_drop_task;
	263
4d22de3e DLR	264	struct dentry *debugfs_root;
	265
	266	struct mutex mdio_lock;
	267	spinlock_t stats_lock;
	268	spinlock_t work_lock;
74b793e1 DLR	269
74b793e1 DLR	270	struct sk_buff *nofail_skb;
4d22de3e DLR	271	};
	272
	273	static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
	274	{
	275	u32 val = readl(adapter->regs + reg_addr);
	276
	277	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
	278	return val;
	279	}
	280
	281	static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
	282	{
	283	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
	284	writel(val, adapter->regs + reg_addr);
	285	}
	286
	287	static inline struct port_info adap2pinfo(struct adapter adap, int idx)
	288	{
	289	return netdev_priv(adap->port[idx]);
	290	}
	291
5e659515 DLR	292	static inline int phy2portid(struct cphy *phy)
	293	{
	294	struct adapter *adap = phy->adapter;
	295	struct port_info *port0 = adap2pinfo(adap, 0);
	296
	297	return &port0->phy == phy ? 0 : 1;
	298	}
	299
4d22de3e DLR	300	#define OFFLOAD_DEVMAP_BIT 15
	301
	302	#define tdev2adap(d) container_of(d, struct adapter, tdev)
	303
	304	static inline int offload_running(struct adapter *adapter)
	305	{
	306	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
	307	}
	308
	309	int t3_offload_tx(struct t3cdev tdev, struct sk_buff skb);
	310
	311	void t3_os_ext_intr_handler(struct adapter *adapter);
	312	void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
	313	int speed, int duplex, int fc);
04497982	314	void t3_os_phymod_changed(struct adapter *adap, int port_id);
bf792094 DLR	315	void t3_os_link_fault(struct adapter *adapter, int port_id, int state);
bf792094 DLR	316	void t3_os_link_fault_handler(struct adapter *adapter, int port_id);
4d22de3e DLR	317
	318	void t3_sge_start(struct adapter *adap);
	319	void t3_sge_stop(struct adapter *adap);
31563789	320	void t3_start_sge_timers(struct adapter *adap);
0ca41c04	321	void t3_stop_sge_timers(struct adapter *adap);
4d22de3e DLR	322	void t3_free_sge_resources(struct adapter *adap);
4d22de3e DLR	323	void t3_sge_err_intr_handler(struct adapter *adapter);
7c239975	324	irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
61357325	325	netdev_tx_t t3_eth_xmit(struct sk_buff skb, struct net_device dev);
14ab9892	326	int t3_mgmt_tx(struct adapter adap, struct sk_buff skb);
4d22de3e DLR	327	void t3_update_qset_coalesce(struct sge_qset qs, const struct qset_params p);
	328	int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
	329	int irq_vec_idx, const struct qset_params *p,
82ad3329 DLR	330	int ntxq, struct net_device *dev,
82ad3329 DLR	331	struct netdev_queue *netdevq);
e998f245	332	extern struct workqueue_struct *cxgb3_wq;
4d22de3e	333
2e8c07c3 DLR	334	int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);
2e8c07c3 DLR	335
4d22de3e	336	#endif /* __T3_ADAPTER_H__ */