[deliverable/linux.git] / drivers / net / cxgb3 / adapter.h

/*
 * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/* This file should not be included directly.  Include common.h instead. */

#ifndef __T3_ADAPTER_H__
#define __T3_ADAPTER_H__

#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/cache.h>
#include <linux/mutex.h>
#include "t3cdev.h"
#include <asm/semaphore.h>
#include <asm/bitops.h>
#include <asm/io.h>

typedef irqreturn_t(*intr_handler_t) (int, void *);

struct vlan_group;

struct port_info {
	struct vlan_group *vlan_grp;
	const struct port_type_info *port_type;
	u8 port_id;
	u8 rx_csum_offload;
	u8 nqsets;
	u8 first_qset;
	struct cphy phy;
	struct cmac mac;
	struct link_config link_config;
	struct net_device_stats netstats;
	int activity;
};

enum {				/* adapter flags */
	FULL_INIT_DONE = (1 << 0),
	USING_MSI = (1 << 1),
	USING_MSIX = (1 << 2),
	QUEUES_BOUND = (1 << 3),
};

struct fl_pg_chunk {
	struct page *page;
	void *va;
	unsigned int offset;
};

struct rx_desc;
struct rx_sw_desc;

struct sge_fl {                     /* SGE per free-buffer list state */
	unsigned int buf_size;      /* size of each Rx buffer */
	unsigned int credits;       /* # of available Rx buffers */
	unsigned int size;          /* capacity of free list */
	unsigned int cidx;          /* consumer index */
	unsigned int pidx;          /* producer index */
	unsigned int gen;           /* free list generation */
	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
	struct rx_desc *desc;       /* address of HW Rx descriptor ring */
	struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
	dma_addr_t   phys_addr;     /* physical address of HW ring start */
	unsigned int cntxt_id;      /* SGE context id for the free list */
	unsigned long empty;        /* # of times queue ran out of buffers */
	unsigned long alloc_failed; /* # of times buffer allocation failed */
};

/*
 * Bundle size for grouping offload RX packets for delivery to the stack.
 * Don't make this too big as we do prefetch on each packet in a bundle.
 */
# define RX_BUNDLE_SIZE 8

struct rsp_desc;

struct sge_rspq {		/* state for an SGE response queue */
	unsigned int credits;	/* # of pending response credits */
	unsigned int size;	/* capacity of response queue */
	unsigned int cidx;	/* consumer index */
	unsigned int gen;	/* current generation bit */
	unsigned int polling;	/* is the queue serviced through NAPI? */
	unsigned int holdoff_tmr;	/* interrupt holdoff timer in 100ns */
	unsigned int next_holdoff;	/* holdoff time for next interrupt */
	struct rsp_desc *desc;	/* address of HW response ring */
	dma_addr_t phys_addr;	/* physical address of the ring */
	unsigned int cntxt_id;	/* SGE context id for the response q */
	spinlock_t lock;	/* guards response processing */
	struct sk_buff *rx_head;	/* offload packet receive queue head */
	struct sk_buff *rx_tail;	/* offload packet receive queue tail */

	unsigned long offload_pkts;
	unsigned long offload_bundles;
	unsigned long eth_pkts;	/* # of ethernet packets */
	unsigned long pure_rsps;	/* # of pure (non-data) responses */
	unsigned long imm_data;	/* responses with immediate data */
	unsigned long rx_drops;	/* # of packets dropped due to no mem */
	unsigned long async_notif; /* # of asynchronous notification events */
	unsigned long empty;	/* # of times queue ran out of credits */
	unsigned long nomem;	/* # of responses deferred due to no mem */
	unsigned long unhandled_irqs;	/* # of spurious intrs */
	unsigned long starved;
	unsigned long restarted;
};

struct tx_desc;
struct tx_sw_desc;

struct sge_txq {		/* state for an SGE Tx queue */
	unsigned long flags;	/* HW DMA fetch status */
	unsigned int in_use;	/* # of in-use Tx descriptors */
	unsigned int size;	/* # of descriptors */
	unsigned int processed;	/* total # of descs HW has processed */
	unsigned int cleaned;	/* total # of descs SW has reclaimed */
	unsigned int stop_thres;	/* SW TX queue suspend threshold */
	unsigned int cidx;	/* consumer index */
	unsigned int pidx;	/* producer index */
	unsigned int gen;	/* current value of generation bit */
	unsigned int unacked;	/* Tx descriptors used since last COMPL */
	struct tx_desc *desc;	/* address of HW Tx descriptor ring */
	struct tx_sw_desc *sdesc;	/* address of SW Tx descriptor ring */
	spinlock_t lock;	/* guards enqueueing of new packets */
	unsigned int token;	/* WR token */
	dma_addr_t phys_addr;	/* physical address of the ring */
	struct sk_buff_head sendq;	/* List of backpressured offload packets */
	struct tasklet_struct qresume_tsk;	/* restarts the queue */
	unsigned int cntxt_id;	/* SGE context id for the Tx q */
	unsigned long stops;	/* # of times q has been stopped */
	unsigned long restarts;	/* # of queue restarts */
};

enum {				/* per port SGE statistics */
	SGE_PSTAT_TSO,		/* # of TSO requests */
	SGE_PSTAT_RX_CSUM_GOOD,	/* # of successful RX csum offloads */
	SGE_PSTAT_TX_CSUM,	/* # of TX checksum offloads */
	SGE_PSTAT_VLANEX,	/* # of VLAN tag extractions */
	SGE_PSTAT_VLANINS,	/* # of VLAN tag insertions */

	SGE_PSTAT_MAX		/* must be last */
};

struct sge_qset {		/* an SGE queue set */
	struct sge_rspq rspq;
	struct sge_fl fl[SGE_RXQ_PER_SET];
	struct sge_txq txq[SGE_TXQ_PER_SET];
	struct net_device *netdev;	/* associated net device */
	unsigned long txq_stopped;	/* which Tx queues are stopped */
	struct timer_list tx_reclaim_timer;	/* reclaims TX buffers */
	unsigned long port_stats[SGE_PSTAT_MAX];
} ____cacheline_aligned;

struct sge {
	struct sge_qset qs[SGE_QSETS];
	spinlock_t reg_lock;	/* guards non-atomic SGE registers (eg context) */
};

struct adapter {
	struct t3cdev tdev;
	struct list_head adapter_list;
	void __iomem *regs;
	struct pci_dev *pdev;
	unsigned long registered_device_map;
	unsigned long open_device_map;
	unsigned long flags;

	const char *name;
	int msg_enable;
	unsigned int mmio_len;

	struct adapter_params params;
	unsigned int slow_intr_mask;
	unsigned long irq_stats[IRQ_NUM_STATS];

	struct {
		unsigned short vec;
		char desc[22];
	} msix_info[SGE_QSETS + 1];

	/* T3 modules */
	struct sge sge;
	struct mc7 pmrx;
	struct mc7 pmtx;
	struct mc7 cm;
	struct mc5 mc5;

	struct net_device *port[MAX_NPORTS];
	unsigned int check_task_cnt;
	struct delayed_work adap_check_task;
	struct work_struct ext_intr_handler_task;

	/*
	 * Dummy netdevices are needed when using multiple receive queues with
	 * NAPI as each netdevice can service only one queue.
	 */
	struct net_device *dummy_netdev[SGE_QSETS - 1];

	struct dentry *debugfs_root;

	struct mutex mdio_lock;
	spinlock_t stats_lock;
	spinlock_t work_lock;
};

static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
{
	u32 val = readl(adapter->regs + reg_addr);

	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
	return val;
}

static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
{
	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
	writel(val, adapter->regs + reg_addr);
}

static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
{
	return netdev_priv(adap->port[idx]);
}

/*
 * We use the spare atalk_ptr to map a net device to its SGE queue set.
 * This is a macro so it can be used as l-value.
 */
#define dev2qset(netdev) ((netdev)->atalk_ptr)

#define OFFLOAD_DEVMAP_BIT 15

#define tdev2adap(d) container_of(d, struct adapter, tdev)

static inline int offload_running(struct adapter *adapter)
{
	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
}

int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);

void t3_os_ext_intr_handler(struct adapter *adapter);
void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
			int speed, int duplex, int fc);

void t3_sge_start(struct adapter *adap);
void t3_sge_stop(struct adapter *adap);
void t3_free_sge_resources(struct adapter *adap);
void t3_sge_err_intr_handler(struct adapter *adapter);
intr_handler_t t3_intr_handler(struct adapter *adap, int polling);
int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
		      int irq_vec_idx, const struct qset_params *p,
		      int ntxq, struct net_device *netdev);
int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
		unsigned char *data);
irqreturn_t t3_sge_intr_msix(int irq, void *cookie);

#endif				/* __T3_ADAPTER_H__ */
Commit	Line	Data
4d22de3e	1	/*
1d68e93d	2	* Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
4d22de3e	3	*
1d68e93d DLR	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
4d22de3e	9	*
1d68e93d DLR	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
4d22de3e DLR	31	*/
	32
	33	/* This file should not be included directly. Include common.h instead. */
	34
	35	#ifndef __T3_ADAPTER_H__
	36	#define __T3_ADAPTER_H__
	37
	38	#include <linux/pci.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/interrupt.h>
	41	#include <linux/timer.h>
	42	#include <linux/cache.h>
a13fbee0	43	#include <linux/mutex.h>
4d22de3e DLR	44	#include "t3cdev.h"
	45	#include <asm/semaphore.h>
	46	#include <asm/bitops.h>
	47	#include <asm/io.h>
	48
	49	typedef irqreturn_t(intr_handler_t) (int, void );
	50
	51	struct vlan_group;
	52
	53	struct port_info {
	54	struct vlan_group *vlan_grp;
	55	const struct port_type_info *port_type;
	56	u8 port_id;
	57	u8 rx_csum_offload;
	58	u8 nqsets;
	59	u8 first_qset;
	60	struct cphy phy;
	61	struct cmac mac;
	62	struct link_config link_config;
	63	struct net_device_stats netstats;
	64	int activity;
	65	};
	66
	67	enum { /* adapter flags */
	68	FULL_INIT_DONE = (1 << 0),
	69	USING_MSI = (1 << 1),
	70	USING_MSIX = (1 << 2),
14ab9892	71	QUEUES_BOUND = (1 << 3),
4d22de3e DLR	72	};
4d22de3e DLR	73
cf992af5 DLR	74	struct fl_pg_chunk {
	75	struct page *page;
	76	void *va;
	77	unsigned int offset;
	78	};
	79
4d22de3e DLR	80	struct rx_desc;
	81	struct rx_sw_desc;
	82
cf992af5 DLR	83	struct sge_fl { /* SGE per free-buffer list state */
	84	unsigned int buf_size; /* size of each Rx buffer */
	85	unsigned int credits; /* # of available Rx buffers */
	86	unsigned int size; /* capacity of free list */
	87	unsigned int cidx; /* consumer index */
	88	unsigned int pidx; /* producer index */
	89	unsigned int gen; /* free list generation */
	90	struct fl_pg_chunk pg_chunk;/* page chunk cache */
	91	unsigned int use_pages; /* whether FL uses pages or sk_buffs */
	92	struct rx_desc desc; / address of HW Rx descriptor ring */
	93	struct rx_sw_desc sdesc; / address of SW Rx descriptor ring */
	94	dma_addr_t phys_addr; /* physical address of HW ring start */
	95	unsigned int cntxt_id; /* SGE context id for the free list */
	96	unsigned long empty; /* # of times queue ran out of buffers */
e0994eb1	97	unsigned long alloc_failed; /* # of times buffer allocation failed */
4d22de3e DLR	98	};
	99
	100	/*
	101	* Bundle size for grouping offload RX packets for delivery to the stack.
	102	* Don't make this too big as we do prefetch on each packet in a bundle.
	103	*/
	104	# define RX_BUNDLE_SIZE 8
	105
	106	struct rsp_desc;
	107
	108	struct sge_rspq { /* state for an SGE response queue */
	109	unsigned int credits; /* # of pending response credits */
	110	unsigned int size; /* capacity of response queue */
	111	unsigned int cidx; /* consumer index */
	112	unsigned int gen; /* current generation bit */
	113	unsigned int polling; /* is the queue serviced through NAPI? */
	114	unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
	115	unsigned int next_holdoff; /* holdoff time for next interrupt */
	116	struct rsp_desc desc; / address of HW response ring */
	117	dma_addr_t phys_addr; /* physical address of the ring */
	118	unsigned int cntxt_id; /* SGE context id for the response q */
	119	spinlock_t lock; /* guards response processing */
	120	struct sk_buff rx_head; / offload packet receive queue head */
	121	struct sk_buff rx_tail; / offload packet receive queue tail */
	122
	123	unsigned long offload_pkts;
	124	unsigned long offload_bundles;
	125	unsigned long eth_pkts; /* # of ethernet packets */
	126	unsigned long pure_rsps; /* # of pure (non-data) responses */
	127	unsigned long imm_data; /* responses with immediate data */
	128	unsigned long rx_drops; /* # of packets dropped due to no mem */
	129	unsigned long async_notif; /* # of asynchronous notification events */
	130	unsigned long empty; /* # of times queue ran out of credits */
	131	unsigned long nomem; /* # of responses deferred due to no mem */
	132	unsigned long unhandled_irqs; /* # of spurious intrs */
bae73f44 DLR	133	unsigned long starved;
bae73f44 DLR	134	unsigned long restarted;
4d22de3e DLR	135	};
	136
	137	struct tx_desc;
	138	struct tx_sw_desc;
	139
	140	struct sge_txq { /* state for an SGE Tx queue */
	141	unsigned long flags; /* HW DMA fetch status */
	142	unsigned int in_use; /* # of in-use Tx descriptors */
	143	unsigned int size; /* # of descriptors */
	144	unsigned int processed; /* total # of descs HW has processed */
	145	unsigned int cleaned; /* total # of descs SW has reclaimed */
	146	unsigned int stop_thres; /* SW TX queue suspend threshold */
	147	unsigned int cidx; /* consumer index */
	148	unsigned int pidx; /* producer index */
	149	unsigned int gen; /* current value of generation bit */
	150	unsigned int unacked; /* Tx descriptors used since last COMPL */
	151	struct tx_desc desc; / address of HW Tx descriptor ring */
	152	struct tx_sw_desc sdesc; / address of SW Tx descriptor ring */
	153	spinlock_t lock; /* guards enqueueing of new packets */
	154	unsigned int token; /* WR token */
	155	dma_addr_t phys_addr; /* physical address of the ring */
	156	struct sk_buff_head sendq; /* List of backpressured offload packets */
	157	struct tasklet_struct qresume_tsk; /* restarts the queue */
	158	unsigned int cntxt_id; /* SGE context id for the Tx q */
	159	unsigned long stops; /* # of times q has been stopped */
	160	unsigned long restarts; /* # of queue restarts */
	161	};
	162
	163	enum { /* per port SGE statistics */
	164	SGE_PSTAT_TSO, /* # of TSO requests */
	165	SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
	166	SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
	167	SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
	168	SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
	169
	170	SGE_PSTAT_MAX /* must be last */
	171	};
	172
	173	struct sge_qset { /* an SGE queue set */
	174	struct sge_rspq rspq;
	175	struct sge_fl fl[SGE_RXQ_PER_SET];
	176	struct sge_txq txq[SGE_TXQ_PER_SET];
	177	struct net_device netdev; / associated net device */
	178	unsigned long txq_stopped; /* which Tx queues are stopped */
	179	struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
	180	unsigned long port_stats[SGE_PSTAT_MAX];
	181	} ____cacheline_aligned;
	182
	183	struct sge {
	184	struct sge_qset qs[SGE_QSETS];
	185	spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */
	186	};
	187
	188	struct adapter {
	189	struct t3cdev tdev;
	190	struct list_head adapter_list;
	191	void __iomem *regs;
	192	struct pci_dev *pdev;
	193	unsigned long registered_device_map;
	194	unsigned long open_device_map;
	195	unsigned long flags;
	196
	197	const char *name;
	198	int msg_enable;
199	unsigned int mmio_len;
200
201	struct adapter_params params;
202	unsigned int slow_intr_mask;
203	unsigned long irq_stats[IRQ_NUM_STATS];
204
205	struct {
206	unsigned short vec;
207	char desc[22];
208	} msix_info[SGE_QSETS + 1];
209
210	/* T3 modules */
211	struct sge sge;
212	struct mc7 pmrx;
213	struct mc7 pmtx;
214	struct mc7 cm;
215	struct mc5 mc5;
216
217	struct net_device *port[MAX_NPORTS];
218	unsigned int check_task_cnt;
219	struct delayed_work adap_check_task;
220	struct work_struct ext_intr_handler_task;
221
222	/*
223	* Dummy netdevices are needed when using multiple receive queues with
224	* NAPI as each netdevice can service only one queue.
225	*/
226	struct net_device *dummy_netdev[SGE_QSETS - 1];
227
228	struct dentry *debugfs_root;
229
230	struct mutex mdio_lock;
231	spinlock_t stats_lock;
232	spinlock_t work_lock;
233	};
234
235	static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
236	{
237	u32 val = readl(adapter->regs + reg_addr);
238
239	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
240	return val;
241	}
242
243	static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
244	{
245	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
246	writel(val, adapter->regs + reg_addr);
247	}
248
249	static inline struct port_info adap2pinfo(struct adapter adap, int idx)
250	{
251	return netdev_priv(adap->port[idx]);
252	}
253
254	/*
255	* We use the spare atalk_ptr to map a net device to its SGE queue set.
256	* This is a macro so it can be used as l-value.
257	*/
258	#define dev2qset(netdev) ((netdev)->atalk_ptr)
259
260	#define OFFLOAD_DEVMAP_BIT 15
261
262	#define tdev2adap(d) container_of(d, struct adapter, tdev)
263
264	static inline int offload_running(struct adapter *adapter)
265	{
266	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
267	}
268
269	int t3_offload_tx(struct t3cdev tdev, struct sk_buff skb);
270
271	void t3_os_ext_intr_handler(struct adapter *adapter);
272	void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
273	int speed, int duplex, int fc);
274
275	void t3_sge_start(struct adapter *adap);
276	void t3_sge_stop(struct adapter *adap);
277	void t3_free_sge_resources(struct adapter *adap);
278	void t3_sge_err_intr_handler(struct adapter *adapter);
279	intr_handler_t t3_intr_handler(struct adapter *adap, int polling);
280	int t3_eth_xmit(struct sk_buff skb, struct net_device dev);
14ab9892	281	int t3_mgmt_tx(struct adapter adap, struct sk_buff skb);
4d22de3e DLR	282	void t3_update_qset_coalesce(struct sge_qset qs, const struct qset_params p);
	283	int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
	284	int irq_vec_idx, const struct qset_params *p,
	285	int ntxq, struct net_device *netdev);
	286	int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
	287	unsigned char *data);
	288	irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
	289
	290	#endif /* __T3_ADAPTER_H__ */