Commit | Line | Data |
---|---|---|
4d22de3e | 1 | /* |
1d68e93d | 2 | * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved. |
4d22de3e | 3 | * |
1d68e93d DLR |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
4d22de3e | 9 | * |
1d68e93d DLR |
10 | * Redistribution and use in source and binary forms, with or |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
4d22de3e DLR |
31 | */ |
32 | ||
33 | /* This file should not be included directly. Include common.h instead. */ | |
34 | ||
35 | #ifndef __T3_ADAPTER_H__ | |
36 | #define __T3_ADAPTER_H__ | |
37 | ||
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/timer.h> | |
42 | #include <linux/cache.h> | |
a13fbee0 | 43 | #include <linux/mutex.h> |
4d22de3e DLR |
44 | #include "t3cdev.h" |
45 | #include <asm/semaphore.h> | |
46 | #include <asm/bitops.h> | |
47 | #include <asm/io.h> | |
48 | ||
49 | typedef irqreturn_t(*intr_handler_t) (int, void *); | |
50 | ||
51 | struct vlan_group; | |
5fbf816f | 52 | struct adapter; |
bea3348e SH |
53 | struct sge_qset; |
54 | ||
4d22de3e | 55 | struct port_info { |
5fbf816f | 56 | struct adapter *adapter; |
4d22de3e | 57 | struct vlan_group *vlan_grp; |
bea3348e | 58 | struct sge_qset *qs; |
4d22de3e DLR |
59 | const struct port_type_info *port_type; |
60 | u8 port_id; | |
61 | u8 rx_csum_offload; | |
62 | u8 nqsets; | |
63 | u8 first_qset; | |
64 | struct cphy phy; | |
65 | struct cmac mac; | |
66 | struct link_config link_config; | |
67 | struct net_device_stats netstats; | |
68 | int activity; | |
69 | }; | |
70 | ||
71 | enum { /* adapter flags */ | |
72 | FULL_INIT_DONE = (1 << 0), | |
73 | USING_MSI = (1 << 1), | |
74 | USING_MSIX = (1 << 2), | |
14ab9892 | 75 | QUEUES_BOUND = (1 << 3), |
4d22de3e DLR |
76 | }; |
77 | ||
cf992af5 DLR |
78 | struct fl_pg_chunk { |
79 | struct page *page; | |
80 | void *va; | |
81 | unsigned int offset; | |
82 | }; | |
83 | ||
4d22de3e DLR |
84 | struct rx_desc; |
85 | struct rx_sw_desc; | |
86 | ||
cf992af5 DLR |
87 | struct sge_fl { /* SGE per free-buffer list state */ |
88 | unsigned int buf_size; /* size of each Rx buffer */ | |
89 | unsigned int credits; /* # of available Rx buffers */ | |
90 | unsigned int size; /* capacity of free list */ | |
91 | unsigned int cidx; /* consumer index */ | |
92 | unsigned int pidx; /* producer index */ | |
93 | unsigned int gen; /* free list generation */ | |
94 | struct fl_pg_chunk pg_chunk;/* page chunk cache */ | |
95 | unsigned int use_pages; /* whether FL uses pages or sk_buffs */ | |
96 | struct rx_desc *desc; /* address of HW Rx descriptor ring */ | |
97 | struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ | |
98 | dma_addr_t phys_addr; /* physical address of HW ring start */ | |
99 | unsigned int cntxt_id; /* SGE context id for the free list */ | |
100 | unsigned long empty; /* # of times queue ran out of buffers */ | |
e0994eb1 | 101 | unsigned long alloc_failed; /* # of times buffer allocation failed */ |
4d22de3e DLR |
102 | }; |
103 | ||
104 | /* | |
105 | * Bundle size for grouping offload RX packets for delivery to the stack. | |
106 | * Don't make this too big as we do prefetch on each packet in a bundle. | |
107 | */ | |
108 | # define RX_BUNDLE_SIZE 8 | |
109 | ||
110 | struct rsp_desc; | |
111 | ||
112 | struct sge_rspq { /* state for an SGE response queue */ | |
113 | unsigned int credits; /* # of pending response credits */ | |
114 | unsigned int size; /* capacity of response queue */ | |
115 | unsigned int cidx; /* consumer index */ | |
116 | unsigned int gen; /* current generation bit */ | |
117 | unsigned int polling; /* is the queue serviced through NAPI? */ | |
118 | unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */ | |
119 | unsigned int next_holdoff; /* holdoff time for next interrupt */ | |
120 | struct rsp_desc *desc; /* address of HW response ring */ | |
121 | dma_addr_t phys_addr; /* physical address of the ring */ | |
122 | unsigned int cntxt_id; /* SGE context id for the response q */ | |
123 | spinlock_t lock; /* guards response processing */ | |
124 | struct sk_buff *rx_head; /* offload packet receive queue head */ | |
125 | struct sk_buff *rx_tail; /* offload packet receive queue tail */ | |
126 | ||
127 | unsigned long offload_pkts; | |
128 | unsigned long offload_bundles; | |
129 | unsigned long eth_pkts; /* # of ethernet packets */ | |
130 | unsigned long pure_rsps; /* # of pure (non-data) responses */ | |
131 | unsigned long imm_data; /* responses with immediate data */ | |
132 | unsigned long rx_drops; /* # of packets dropped due to no mem */ | |
133 | unsigned long async_notif; /* # of asynchronous notification events */ | |
134 | unsigned long empty; /* # of times queue ran out of credits */ | |
135 | unsigned long nomem; /* # of responses deferred due to no mem */ | |
136 | unsigned long unhandled_irqs; /* # of spurious intrs */ | |
bae73f44 DLR |
137 | unsigned long starved; |
138 | unsigned long restarted; | |
4d22de3e DLR |
139 | }; |
140 | ||
141 | struct tx_desc; | |
142 | struct tx_sw_desc; | |
143 | ||
144 | struct sge_txq { /* state for an SGE Tx queue */ | |
145 | unsigned long flags; /* HW DMA fetch status */ | |
146 | unsigned int in_use; /* # of in-use Tx descriptors */ | |
147 | unsigned int size; /* # of descriptors */ | |
148 | unsigned int processed; /* total # of descs HW has processed */ | |
149 | unsigned int cleaned; /* total # of descs SW has reclaimed */ | |
150 | unsigned int stop_thres; /* SW TX queue suspend threshold */ | |
151 | unsigned int cidx; /* consumer index */ | |
152 | unsigned int pidx; /* producer index */ | |
153 | unsigned int gen; /* current value of generation bit */ | |
154 | unsigned int unacked; /* Tx descriptors used since last COMPL */ | |
155 | struct tx_desc *desc; /* address of HW Tx descriptor ring */ | |
156 | struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ | |
157 | spinlock_t lock; /* guards enqueueing of new packets */ | |
158 | unsigned int token; /* WR token */ | |
159 | dma_addr_t phys_addr; /* physical address of the ring */ | |
160 | struct sk_buff_head sendq; /* List of backpressured offload packets */ | |
161 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
162 | unsigned int cntxt_id; /* SGE context id for the Tx q */ | |
163 | unsigned long stops; /* # of times q has been stopped */ | |
164 | unsigned long restarts; /* # of queue restarts */ | |
165 | }; | |
166 | ||
167 | enum { /* per port SGE statistics */ | |
168 | SGE_PSTAT_TSO, /* # of TSO requests */ | |
169 | SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ | |
170 | SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ | |
171 | SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ | |
172 | SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ | |
173 | ||
174 | SGE_PSTAT_MAX /* must be last */ | |
175 | }; | |
176 | ||
177 | struct sge_qset { /* an SGE queue set */ | |
bea3348e SH |
178 | struct adapter *adap; |
179 | struct napi_struct napi; | |
4d22de3e DLR |
180 | struct sge_rspq rspq; |
181 | struct sge_fl fl[SGE_RXQ_PER_SET]; | |
182 | struct sge_txq txq[SGE_TXQ_PER_SET]; | |
bea3348e | 183 | struct net_device *netdev; |
4d22de3e DLR |
184 | unsigned long txq_stopped; /* which Tx queues are stopped */ |
185 | struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ | |
186 | unsigned long port_stats[SGE_PSTAT_MAX]; | |
187 | } ____cacheline_aligned; | |
188 | ||
189 | struct sge { | |
190 | struct sge_qset qs[SGE_QSETS]; | |
191 | spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */ | |
192 | }; | |
193 | ||
194 | struct adapter { | |
195 | struct t3cdev tdev; | |
196 | struct list_head adapter_list; | |
197 | void __iomem *regs; | |
198 | struct pci_dev *pdev; | |
199 | unsigned long registered_device_map; | |
200 | unsigned long open_device_map; | |
201 | unsigned long flags; | |
202 | ||
203 | const char *name; | |
204 | int msg_enable; | |
205 | unsigned int mmio_len; | |
206 | ||
207 | struct adapter_params params; | |
208 | unsigned int slow_intr_mask; | |
209 | unsigned long irq_stats[IRQ_NUM_STATS]; | |
210 | ||
211 | struct { | |
212 | unsigned short vec; | |
213 | char desc[22]; | |
214 | } msix_info[SGE_QSETS + 1]; | |
215 | ||
216 | /* T3 modules */ | |
217 | struct sge sge; | |
218 | struct mc7 pmrx; | |
219 | struct mc7 pmtx; | |
220 | struct mc7 cm; | |
221 | struct mc5 mc5; | |
222 | ||
223 | struct net_device *port[MAX_NPORTS]; | |
224 | unsigned int check_task_cnt; | |
225 | struct delayed_work adap_check_task; | |
226 | struct work_struct ext_intr_handler_task; | |
227 | ||
4d22de3e DLR |
228 | struct dentry *debugfs_root; |
229 | ||
230 | struct mutex mdio_lock; | |
231 | spinlock_t stats_lock; | |
232 | spinlock_t work_lock; | |
233 | }; | |
234 | ||
235 | static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) | |
236 | { | |
237 | u32 val = readl(adapter->regs + reg_addr); | |
238 | ||
239 | CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); | |
240 | return val; | |
241 | } | |
242 | ||
243 | static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) | |
244 | { | |
245 | CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); | |
246 | writel(val, adapter->regs + reg_addr); | |
247 | } | |
248 | ||
249 | static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) | |
250 | { | |
251 | return netdev_priv(adap->port[idx]); | |
252 | } | |
253 | ||
4d22de3e DLR |
254 | #define OFFLOAD_DEVMAP_BIT 15 |
255 | ||
256 | #define tdev2adap(d) container_of(d, struct adapter, tdev) | |
257 | ||
258 | static inline int offload_running(struct adapter *adapter) | |
259 | { | |
260 | return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map); | |
261 | } | |
262 | ||
263 | int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb); | |
264 | ||
265 | void t3_os_ext_intr_handler(struct adapter *adapter); | |
266 | void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status, | |
267 | int speed, int duplex, int fc); | |
268 | ||
269 | void t3_sge_start(struct adapter *adap); | |
270 | void t3_sge_stop(struct adapter *adap); | |
271 | void t3_free_sge_resources(struct adapter *adap); | |
272 | void t3_sge_err_intr_handler(struct adapter *adapter); | |
273 | intr_handler_t t3_intr_handler(struct adapter *adap, int polling); | |
274 | int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev); | |
14ab9892 | 275 | int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb); |
4d22de3e DLR |
276 | void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); |
277 | int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, | |
278 | int irq_vec_idx, const struct qset_params *p, | |
bea3348e | 279 | int ntxq, struct net_device *dev); |
4d22de3e DLR |
280 | int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, |
281 | unsigned char *data); | |
282 | irqreturn_t t3_sge_intr_msix(int irq, void *cookie); | |
283 | ||
284 | #endif /* __T3_ADAPTER_H__ */ |