pnp: fix the fcpnp_driver declaration to only exist if CONFIG_PNP=y
[deliverable/linux.git] / drivers / net / cxgb3 / sge.c
CommitLineData
4d22de3e 1/*
1d68e93d 2 * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
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4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
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10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
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32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/dma-mapping.h>
39#include "common.h"
40#include "regs.h"
41#include "sge_defs.h"
42#include "t3_cpl.h"
43#include "firmware_exports.h"
44
45#define USE_GTS 0
46
47#define SGE_RX_SM_BUF_SIZE 1536
e0994eb1 48
4d22de3e 49#define SGE_RX_COPY_THRES 256
cf992af5 50#define SGE_RX_PULL_LEN 128
4d22de3e 51
e0994eb1 52/*
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53 * Page chunk size for FL0 buffers if FL0 is to be populated with page chunks.
54 * It must be a divisor of PAGE_SIZE. If set to 0 FL0 will use sk_buffs
55 * directly.
e0994eb1 56 */
cf992af5 57#define FL0_PG_CHUNK_SIZE 2048
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58#define FL0_PG_ORDER 0
59#define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192)
60#define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1)
cf992af5 61
e0994eb1 62#define SGE_RX_DROP_THRES 16
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63
64/*
65 * Period of the Tx buffer reclaim timer. This timer does not need to run
66 * frequently as Tx buffers are usually reclaimed by new Tx packets.
67 */
68#define TX_RECLAIM_PERIOD (HZ / 4)
69
70/* WR size in bytes */
71#define WR_LEN (WR_FLITS * 8)
72
73/*
74 * Types of Tx queues in each queue set. Order here matters, do not change.
75 */
76enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
77
78/* Values for sge_txq.flags */
79enum {
80 TXQ_RUNNING = 1 << 0, /* fetch engine is running */
81 TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */
82};
83
84struct tx_desc {
fb8e4444 85 __be64 flit[TX_DESC_FLITS];
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86};
87
88struct rx_desc {
89 __be32 addr_lo;
90 __be32 len_gen;
91 __be32 gen2;
92 __be32 addr_hi;
93};
94
95struct tx_sw_desc { /* SW state per Tx descriptor */
96 struct sk_buff *skb;
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97 u8 eop; /* set if last descriptor for packet */
98 u8 addr_idx; /* buffer index of first SGL entry in descriptor */
99 u8 fragidx; /* first page fragment associated with descriptor */
100 s8 sflit; /* start flit of first SGL entry in descriptor */
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101};
102
cf992af5 103struct rx_sw_desc { /* SW state per Rx descriptor */
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104 union {
105 struct sk_buff *skb;
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106 struct fl_pg_chunk pg_chunk;
107 };
108 DECLARE_PCI_UNMAP_ADDR(dma_addr);
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109};
110
111struct rsp_desc { /* response queue descriptor */
112 struct rss_header rss_hdr;
113 __be32 flags;
114 __be32 len_cq;
115 u8 imm_data[47];
116 u8 intr_gen;
117};
118
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119/*
120 * Holds unmapping information for Tx packets that need deferred unmapping.
121 * This structure lives at skb->head and must be allocated by callers.
122 */
123struct deferred_unmap_info {
124 struct pci_dev *pdev;
125 dma_addr_t addr[MAX_SKB_FRAGS + 1];
126};
127
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128/*
129 * Maps a number of flits to the number of Tx descriptors that can hold them.
130 * The formula is
131 *
132 * desc = 1 + (flits - 2) / (WR_FLITS - 1).
133 *
134 * HW allows up to 4 descriptors to be combined into a WR.
135 */
136static u8 flit_desc_map[] = {
137 0,
138#if SGE_NUM_GENBITS == 1
139 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
140 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
141 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
142 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
143#elif SGE_NUM_GENBITS == 2
144 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
145 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
146 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
147 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
148#else
149# error "SGE_NUM_GENBITS must be 1 or 2"
150#endif
151};
152
153static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx)
154{
155 return container_of(q, struct sge_qset, fl[qidx]);
156}
157
158static inline struct sge_qset *rspq_to_qset(const struct sge_rspq *q)
159{
160 return container_of(q, struct sge_qset, rspq);
161}
162
163static inline struct sge_qset *txq_to_qset(const struct sge_txq *q, int qidx)
164{
165 return container_of(q, struct sge_qset, txq[qidx]);
166}
167
168/**
169 * refill_rspq - replenish an SGE response queue
170 * @adapter: the adapter
171 * @q: the response queue to replenish
172 * @credits: how many new responses to make available
173 *
174 * Replenishes a response queue by making the supplied number of responses
175 * available to HW.
176 */
177static inline void refill_rspq(struct adapter *adapter,
178 const struct sge_rspq *q, unsigned int credits)
179{
afefce66 180 rmb();
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181 t3_write_reg(adapter, A_SG_RSPQ_CREDIT_RETURN,
182 V_RSPQ(q->cntxt_id) | V_CREDITS(credits));
183}
184
185/**
186 * need_skb_unmap - does the platform need unmapping of sk_buffs?
187 *
188 * Returns true if the platfrom needs sk_buff unmapping. The compiler
189 * optimizes away unecessary code if this returns true.
190 */
191static inline int need_skb_unmap(void)
192{
193 /*
194 * This structure is used to tell if the platfrom needs buffer
195 * unmapping by checking if DECLARE_PCI_UNMAP_ADDR defines anything.
196 */
197 struct dummy {
198 DECLARE_PCI_UNMAP_ADDR(addr);
199 };
200
201 return sizeof(struct dummy) != 0;
202}
203
204/**
205 * unmap_skb - unmap a packet main body and its page fragments
206 * @skb: the packet
207 * @q: the Tx queue containing Tx descriptors for the packet
208 * @cidx: index of Tx descriptor
209 * @pdev: the PCI device
210 *
211 * Unmap the main body of an sk_buff and its page fragments, if any.
212 * Because of the fairly complicated structure of our SGLs and the desire
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213 * to conserve space for metadata, the information necessary to unmap an
214 * sk_buff is spread across the sk_buff itself (buffer lengths), the HW Tx
215 * descriptors (the physical addresses of the various data buffers), and
216 * the SW descriptor state (assorted indices). The send functions
217 * initialize the indices for the first packet descriptor so we can unmap
218 * the buffers held in the first Tx descriptor here, and we have enough
219 * information at this point to set the state for the next Tx descriptor.
220 *
221 * Note that it is possible to clean up the first descriptor of a packet
222 * before the send routines have written the next descriptors, but this
223 * race does not cause any problem. We just end up writing the unmapping
224 * info for the descriptor first.
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225 */
226static inline void unmap_skb(struct sk_buff *skb, struct sge_txq *q,
227 unsigned int cidx, struct pci_dev *pdev)
228{
229 const struct sg_ent *sgp;
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230 struct tx_sw_desc *d = &q->sdesc[cidx];
231 int nfrags, frag_idx, curflit, j = d->addr_idx;
4d22de3e 232
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233 sgp = (struct sg_ent *)&q->desc[cidx].flit[d->sflit];
234 frag_idx = d->fragidx;
4d22de3e 235
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236 if (frag_idx == 0 && skb_headlen(skb)) {
237 pci_unmap_single(pdev, be64_to_cpu(sgp->addr[0]),
238 skb_headlen(skb), PCI_DMA_TODEVICE);
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239 j = 1;
240 }
241
23561c94 242 curflit = d->sflit + 1 + j;
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243 nfrags = skb_shinfo(skb)->nr_frags;
244
245 while (frag_idx < nfrags && curflit < WR_FLITS) {
246 pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]),
247 skb_shinfo(skb)->frags[frag_idx].size,
248 PCI_DMA_TODEVICE);
249 j ^= 1;
250 if (j == 0) {
251 sgp++;
252 curflit++;
253 }
254 curflit++;
255 frag_idx++;
256 }
257
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258 if (frag_idx < nfrags) { /* SGL continues into next Tx descriptor */
259 d = cidx + 1 == q->size ? q->sdesc : d + 1;
260 d->fragidx = frag_idx;
261 d->addr_idx = j;
262 d->sflit = curflit - WR_FLITS - j; /* sflit can be -1 */
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263 }
264}
265
266/**
267 * free_tx_desc - reclaims Tx descriptors and their buffers
268 * @adapter: the adapter
269 * @q: the Tx queue to reclaim descriptors from
270 * @n: the number of descriptors to reclaim
271 *
272 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
273 * Tx buffers. Called with the Tx queue lock held.
274 */
275static void free_tx_desc(struct adapter *adapter, struct sge_txq *q,
276 unsigned int n)
277{
278 struct tx_sw_desc *d;
279 struct pci_dev *pdev = adapter->pdev;
280 unsigned int cidx = q->cidx;
281
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282 const int need_unmap = need_skb_unmap() &&
283 q->cntxt_id >= FW_TUNNEL_SGEEC_START;
284
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285 d = &q->sdesc[cidx];
286 while (n--) {
287 if (d->skb) { /* an SGL is present */
99d7cf30 288 if (need_unmap)
4d22de3e 289 unmap_skb(d->skb, q, cidx, pdev);
23561c94 290 if (d->eop)
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291 kfree_skb(d->skb);
292 }
293 ++d;
294 if (++cidx == q->size) {
295 cidx = 0;
296 d = q->sdesc;
297 }
298 }
299 q->cidx = cidx;
300}
301
302/**
303 * reclaim_completed_tx - reclaims completed Tx descriptors
304 * @adapter: the adapter
305 * @q: the Tx queue to reclaim completed descriptors from
306 *
307 * Reclaims Tx descriptors that the SGE has indicated it has processed,
308 * and frees the associated buffers if possible. Called with the Tx
309 * queue's lock held.
310 */
311static inline void reclaim_completed_tx(struct adapter *adapter,
312 struct sge_txq *q)
313{
314 unsigned int reclaim = q->processed - q->cleaned;
315
316 if (reclaim) {
317 free_tx_desc(adapter, q, reclaim);
318 q->cleaned += reclaim;
319 q->in_use -= reclaim;
320 }
321}
322
323/**
324 * should_restart_tx - are there enough resources to restart a Tx queue?
325 * @q: the Tx queue
326 *
327 * Checks if there are enough descriptors to restart a suspended Tx queue.
328 */
329static inline int should_restart_tx(const struct sge_txq *q)
330{
331 unsigned int r = q->processed - q->cleaned;
332
333 return q->in_use - r < (q->size >> 1);
334}
335
336/**
337 * free_rx_bufs - free the Rx buffers on an SGE free list
338 * @pdev: the PCI device associated with the adapter
339 * @rxq: the SGE free list to clean up
340 *
341 * Release the buffers on an SGE free-buffer Rx queue. HW fetching from
342 * this queue should be stopped before calling this function.
343 */
344static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
345{
346 unsigned int cidx = q->cidx;
347
348 while (q->credits--) {
349 struct rx_sw_desc *d = &q->sdesc[cidx];
350
351 pci_unmap_single(pdev, pci_unmap_addr(d, dma_addr),
352 q->buf_size, PCI_DMA_FROMDEVICE);
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353 if (q->use_pages) {
354 put_page(d->pg_chunk.page);
355 d->pg_chunk.page = NULL;
e0994eb1 356 } else {
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357 kfree_skb(d->skb);
358 d->skb = NULL;
e0994eb1 359 }
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360 if (++cidx == q->size)
361 cidx = 0;
362 }
e0994eb1 363
cf992af5 364 if (q->pg_chunk.page) {
7385ecf3 365 __free_pages(q->pg_chunk.page, q->order);
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366 q->pg_chunk.page = NULL;
367 }
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368}
369
370/**
371 * add_one_rx_buf - add a packet buffer to a free-buffer list
cf992af5 372 * @va: buffer start VA
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373 * @len: the buffer length
374 * @d: the HW Rx descriptor to write
375 * @sd: the SW Rx descriptor to write
376 * @gen: the generation bit value
377 * @pdev: the PCI device associated with the adapter
378 *
379 * Add a buffer of the given length to the supplied HW and SW Rx
380 * descriptors.
381 */
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382static inline int add_one_rx_buf(void *va, unsigned int len,
383 struct rx_desc *d, struct rx_sw_desc *sd,
384 unsigned int gen, struct pci_dev *pdev)
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385{
386 dma_addr_t mapping;
387
e0994eb1 388 mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE);
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389 if (unlikely(pci_dma_mapping_error(mapping)))
390 return -ENOMEM;
391
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392 pci_unmap_addr_set(sd, dma_addr, mapping);
393
394 d->addr_lo = cpu_to_be32(mapping);
395 d->addr_hi = cpu_to_be32((u64) mapping >> 32);
396 wmb();
397 d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
398 d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
b1fb1f28 399 return 0;
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400}
401
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402static int alloc_pg_chunk(struct sge_fl *q, struct rx_sw_desc *sd, gfp_t gfp,
403 unsigned int order)
cf992af5
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404{
405 if (!q->pg_chunk.page) {
7385ecf3 406 q->pg_chunk.page = alloc_pages(gfp, order);
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407 if (unlikely(!q->pg_chunk.page))
408 return -ENOMEM;
409 q->pg_chunk.va = page_address(q->pg_chunk.page);
410 q->pg_chunk.offset = 0;
411 }
412 sd->pg_chunk = q->pg_chunk;
413
414 q->pg_chunk.offset += q->buf_size;
7385ecf3 415 if (q->pg_chunk.offset == (PAGE_SIZE << order))
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416 q->pg_chunk.page = NULL;
417 else {
418 q->pg_chunk.va += q->buf_size;
419 get_page(q->pg_chunk.page);
420 }
421 return 0;
422}
423
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424/**
425 * refill_fl - refill an SGE free-buffer list
426 * @adapter: the adapter
427 * @q: the free-list to refill
428 * @n: the number of new buffers to allocate
429 * @gfp: the gfp flags for allocating new buffers
430 *
431 * (Re)populate an SGE free-buffer list with up to @n new packet buffers,
432 * allocated with the supplied gfp flags. The caller must assure that
433 * @n does not exceed the queue's capacity.
434 */
b1fb1f28 435static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp)
4d22de3e 436{
cf992af5 437 void *buf_start;
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438 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
439 struct rx_desc *d = &q->desc[q->pidx];
b1fb1f28 440 unsigned int count = 0;
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441
442 while (n--) {
b1fb1f28
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443 int err;
444
cf992af5 445 if (q->use_pages) {
7385ecf3 446 if (unlikely(alloc_pg_chunk(q, sd, gfp, q->order))) {
cf992af5 447nomem: q->alloc_failed++;
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448 break;
449 }
cf992af5 450 buf_start = sd->pg_chunk.va;
e0994eb1 451 } else {
cf992af5 452 struct sk_buff *skb = alloc_skb(q->buf_size, gfp);
e0994eb1 453
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454 if (!skb)
455 goto nomem;
e0994eb1 456
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457 sd->skb = skb;
458 buf_start = skb->data;
e0994eb1
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459 }
460
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461 err = add_one_rx_buf(buf_start, q->buf_size, d, sd, q->gen,
462 adap->pdev);
463 if (unlikely(err)) {
464 if (!q->use_pages) {
465 kfree_skb(sd->skb);
466 sd->skb = NULL;
467 }
468 break;
469 }
470
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471 d++;
472 sd++;
473 if (++q->pidx == q->size) {
474 q->pidx = 0;
475 q->gen ^= 1;
476 sd = q->sdesc;
477 d = q->desc;
478 }
479 q->credits++;
b1fb1f28 480 count++;
4d22de3e 481 }
afefce66 482 wmb();
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483 if (likely(count))
484 t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
485
486 return count;
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487}
488
489static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
490{
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491 refill_fl(adap, fl, min(16U, fl->size - fl->credits),
492 GFP_ATOMIC | __GFP_COMP);
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493}
494
495/**
496 * recycle_rx_buf - recycle a receive buffer
497 * @adapter: the adapter
498 * @q: the SGE free list
499 * @idx: index of buffer to recycle
500 *
501 * Recycles the specified buffer on the given free list by adding it at
502 * the next available slot on the list.
503 */
504static void recycle_rx_buf(struct adapter *adap, struct sge_fl *q,
505 unsigned int idx)
506{
507 struct rx_desc *from = &q->desc[idx];
508 struct rx_desc *to = &q->desc[q->pidx];
509
cf992af5 510 q->sdesc[q->pidx] = q->sdesc[idx];
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511 to->addr_lo = from->addr_lo; /* already big endian */
512 to->addr_hi = from->addr_hi; /* likewise */
513 wmb();
514 to->len_gen = cpu_to_be32(V_FLD_GEN1(q->gen));
515 to->gen2 = cpu_to_be32(V_FLD_GEN2(q->gen));
516 q->credits++;
517
518 if (++q->pidx == q->size) {
519 q->pidx = 0;
520 q->gen ^= 1;
521 }
522 t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
523}
524
525/**
526 * alloc_ring - allocate resources for an SGE descriptor ring
527 * @pdev: the PCI device
528 * @nelem: the number of descriptors
529 * @elem_size: the size of each descriptor
530 * @sw_size: the size of the SW state associated with each ring element
531 * @phys: the physical address of the allocated ring
532 * @metadata: address of the array holding the SW state for the ring
533 *
534 * Allocates resources for an SGE descriptor ring, such as Tx queues,
535 * free buffer lists, or response queues. Each SGE ring requires
536 * space for its HW descriptors plus, optionally, space for the SW state
537 * associated with each HW entry (the metadata). The function returns
538 * three values: the virtual address for the HW ring (the return value
539 * of the function), the physical address of the HW ring, and the address
540 * of the SW ring.
541 */
542static void *alloc_ring(struct pci_dev *pdev, size_t nelem, size_t elem_size,
e0994eb1 543 size_t sw_size, dma_addr_t * phys, void *metadata)
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544{
545 size_t len = nelem * elem_size;
546 void *s = NULL;
547 void *p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL);
548
549 if (!p)
550 return NULL;
551 if (sw_size) {
552 s = kcalloc(nelem, sw_size, GFP_KERNEL);
553
554 if (!s) {
555 dma_free_coherent(&pdev->dev, len, p, *phys);
556 return NULL;
557 }
558 }
559 if (metadata)
560 *(void **)metadata = s;
561 memset(p, 0, len);
562 return p;
563}
564
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565/**
566 * t3_reset_qset - reset a sge qset
567 * @q: the queue set
568 *
569 * Reset the qset structure.
570 * the NAPI structure is preserved in the event of
571 * the qset's reincarnation, for example during EEH recovery.
572 */
573static void t3_reset_qset(struct sge_qset *q)
574{
575 if (q->adap &&
576 !(q->adap->flags & NAPI_INIT)) {
577 memset(q, 0, sizeof(*q));
578 return;
579 }
580
581 q->adap = NULL;
582 memset(&q->rspq, 0, sizeof(q->rspq));
583 memset(q->fl, 0, sizeof(struct sge_fl) * SGE_RXQ_PER_SET);
584 memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET);
585 q->txq_stopped = 0;
586 memset(&q->tx_reclaim_timer, 0, sizeof(q->tx_reclaim_timer));
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587 kfree(q->lro_frag_tbl);
588 q->lro_nfrags = q->lro_frag_len = 0;
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589}
590
591
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592/**
593 * free_qset - free the resources of an SGE queue set
594 * @adapter: the adapter owning the queue set
595 * @q: the queue set
596 *
597 * Release the HW and SW resources associated with an SGE queue set, such
598 * as HW contexts, packet buffers, and descriptor rings. Traffic to the
599 * queue set must be quiesced prior to calling this.
600 */
9265fabf 601static void t3_free_qset(struct adapter *adapter, struct sge_qset *q)
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602{
603 int i;
604 struct pci_dev *pdev = adapter->pdev;
605
606 if (q->tx_reclaim_timer.function)
607 del_timer_sync(&q->tx_reclaim_timer);
608
609 for (i = 0; i < SGE_RXQ_PER_SET; ++i)
610 if (q->fl[i].desc) {
b1186dee 611 spin_lock_irq(&adapter->sge.reg_lock);
4d22de3e 612 t3_sge_disable_fl(adapter, q->fl[i].cntxt_id);
b1186dee 613 spin_unlock_irq(&adapter->sge.reg_lock);
4d22de3e
DLR
614 free_rx_bufs(pdev, &q->fl[i]);
615 kfree(q->fl[i].sdesc);
616 dma_free_coherent(&pdev->dev,
617 q->fl[i].size *
618 sizeof(struct rx_desc), q->fl[i].desc,
619 q->fl[i].phys_addr);
620 }
621
622 for (i = 0; i < SGE_TXQ_PER_SET; ++i)
623 if (q->txq[i].desc) {
b1186dee 624 spin_lock_irq(&adapter->sge.reg_lock);
4d22de3e 625 t3_sge_enable_ecntxt(adapter, q->txq[i].cntxt_id, 0);
b1186dee 626 spin_unlock_irq(&adapter->sge.reg_lock);
4d22de3e
DLR
627 if (q->txq[i].sdesc) {
628 free_tx_desc(adapter, &q->txq[i],
629 q->txq[i].in_use);
630 kfree(q->txq[i].sdesc);
631 }
632 dma_free_coherent(&pdev->dev,
633 q->txq[i].size *
634 sizeof(struct tx_desc),
635 q->txq[i].desc, q->txq[i].phys_addr);
636 __skb_queue_purge(&q->txq[i].sendq);
637 }
638
639 if (q->rspq.desc) {
b1186dee 640 spin_lock_irq(&adapter->sge.reg_lock);
4d22de3e 641 t3_sge_disable_rspcntxt(adapter, q->rspq.cntxt_id);
b1186dee 642 spin_unlock_irq(&adapter->sge.reg_lock);
4d22de3e
DLR
643 dma_free_coherent(&pdev->dev,
644 q->rspq.size * sizeof(struct rsp_desc),
645 q->rspq.desc, q->rspq.phys_addr);
646 }
647
204e2f98 648 t3_reset_qset(q);
4d22de3e
DLR
649}
650
651/**
652 * init_qset_cntxt - initialize an SGE queue set context info
653 * @qs: the queue set
654 * @id: the queue set id
655 *
656 * Initializes the TIDs and context ids for the queues of a queue set.
657 */
658static void init_qset_cntxt(struct sge_qset *qs, unsigned int id)
659{
660 qs->rspq.cntxt_id = id;
661 qs->fl[0].cntxt_id = 2 * id;
662 qs->fl[1].cntxt_id = 2 * id + 1;
663 qs->txq[TXQ_ETH].cntxt_id = FW_TUNNEL_SGEEC_START + id;
664 qs->txq[TXQ_ETH].token = FW_TUNNEL_TID_START + id;
665 qs->txq[TXQ_OFLD].cntxt_id = FW_OFLD_SGEEC_START + id;
666 qs->txq[TXQ_CTRL].cntxt_id = FW_CTRL_SGEEC_START + id;
667 qs->txq[TXQ_CTRL].token = FW_CTRL_TID_START + id;
668}
669
670/**
671 * sgl_len - calculates the size of an SGL of the given capacity
672 * @n: the number of SGL entries
673 *
674 * Calculates the number of flits needed for a scatter/gather list that
675 * can hold the given number of entries.
676 */
677static inline unsigned int sgl_len(unsigned int n)
678{
679 /* alternatively: 3 * (n / 2) + 2 * (n & 1) */
680 return (3 * n) / 2 + (n & 1);
681}
682
683/**
684 * flits_to_desc - returns the num of Tx descriptors for the given flits
685 * @n: the number of flits
686 *
687 * Calculates the number of Tx descriptors needed for the supplied number
688 * of flits.
689 */
690static inline unsigned int flits_to_desc(unsigned int n)
691{
692 BUG_ON(n >= ARRAY_SIZE(flit_desc_map));
693 return flit_desc_map[n];
694}
695
cf992af5
DLR
696/**
697 * get_packet - return the next ingress packet buffer from a free list
698 * @adap: the adapter that received the packet
699 * @fl: the SGE free list holding the packet
700 * @len: the packet length including any SGE padding
701 * @drop_thres: # of remaining buffers before we start dropping packets
702 *
703 * Get the next packet from a free list and complete setup of the
704 * sk_buff. If the packet is small we make a copy and recycle the
705 * original buffer, otherwise we use the original buffer itself. If a
706 * positive drop threshold is supplied packets are dropped and their
707 * buffers recycled if (a) the number of remaining buffers is under the
708 * threshold and the packet is too big to copy, or (b) the packet should
709 * be copied but there is no memory for the copy.
710 */
711static struct sk_buff *get_packet(struct adapter *adap, struct sge_fl *fl,
712 unsigned int len, unsigned int drop_thres)
713{
714 struct sk_buff *skb = NULL;
715 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
716
717 prefetch(sd->skb->data);
718 fl->credits--;
719
720 if (len <= SGE_RX_COPY_THRES) {
721 skb = alloc_skb(len, GFP_ATOMIC);
722 if (likely(skb != NULL)) {
723 __skb_put(skb, len);
724 pci_dma_sync_single_for_cpu(adap->pdev,
725 pci_unmap_addr(sd, dma_addr), len,
726 PCI_DMA_FROMDEVICE);
727 memcpy(skb->data, sd->skb->data, len);
728 pci_dma_sync_single_for_device(adap->pdev,
729 pci_unmap_addr(sd, dma_addr), len,
730 PCI_DMA_FROMDEVICE);
731 } else if (!drop_thres)
732 goto use_orig_buf;
733recycle:
734 recycle_rx_buf(adap, fl, fl->cidx);
735 return skb;
736 }
737
738 if (unlikely(fl->credits < drop_thres))
739 goto recycle;
740
741use_orig_buf:
742 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
743 fl->buf_size, PCI_DMA_FROMDEVICE);
744 skb = sd->skb;
745 skb_put(skb, len);
746 __refill_fl(adap, fl);
747 return skb;
748}
749
750/**
751 * get_packet_pg - return the next ingress packet buffer from a free list
752 * @adap: the adapter that received the packet
753 * @fl: the SGE free list holding the packet
754 * @len: the packet length including any SGE padding
755 * @drop_thres: # of remaining buffers before we start dropping packets
756 *
757 * Get the next packet from a free list populated with page chunks.
758 * If the packet is small we make a copy and recycle the original buffer,
759 * otherwise we attach the original buffer as a page fragment to a fresh
760 * sk_buff. If a positive drop threshold is supplied packets are dropped
761 * and their buffers recycled if (a) the number of remaining buffers is
762 * under the threshold and the packet is too big to copy, or (b) there's
763 * no system memory.
764 *
765 * Note: this function is similar to @get_packet but deals with Rx buffers
766 * that are page chunks rather than sk_buffs.
767 */
768static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
7385ecf3
DLR
769 struct sge_rspq *q, unsigned int len,
770 unsigned int drop_thres)
cf992af5 771{
7385ecf3 772 struct sk_buff *newskb, *skb;
cf992af5
DLR
773 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
774
7385ecf3
DLR
775 newskb = skb = q->pg_skb;
776
777 if (!skb && (len <= SGE_RX_COPY_THRES)) {
778 newskb = alloc_skb(len, GFP_ATOMIC);
779 if (likely(newskb != NULL)) {
780 __skb_put(newskb, len);
cf992af5
DLR
781 pci_dma_sync_single_for_cpu(adap->pdev,
782 pci_unmap_addr(sd, dma_addr), len,
783 PCI_DMA_FROMDEVICE);
7385ecf3 784 memcpy(newskb->data, sd->pg_chunk.va, len);
cf992af5
DLR
785 pci_dma_sync_single_for_device(adap->pdev,
786 pci_unmap_addr(sd, dma_addr), len,
787 PCI_DMA_FROMDEVICE);
788 } else if (!drop_thres)
789 return NULL;
790recycle:
791 fl->credits--;
792 recycle_rx_buf(adap, fl, fl->cidx);
7385ecf3
DLR
793 q->rx_recycle_buf++;
794 return newskb;
cf992af5
DLR
795 }
796
7385ecf3 797 if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres)))
cf992af5
DLR
798 goto recycle;
799
7385ecf3 800 if (!skb)
b47385bd 801 newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC);
7385ecf3 802 if (unlikely(!newskb)) {
cf992af5
DLR
803 if (!drop_thres)
804 return NULL;
805 goto recycle;
806 }
807
808 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
809 fl->buf_size, PCI_DMA_FROMDEVICE);
7385ecf3
DLR
810 if (!skb) {
811 __skb_put(newskb, SGE_RX_PULL_LEN);
812 memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN);
813 skb_fill_page_desc(newskb, 0, sd->pg_chunk.page,
814 sd->pg_chunk.offset + SGE_RX_PULL_LEN,
815 len - SGE_RX_PULL_LEN);
816 newskb->len = len;
817 newskb->data_len = len - SGE_RX_PULL_LEN;
818 } else {
819 skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags,
820 sd->pg_chunk.page,
821 sd->pg_chunk.offset, len);
822 newskb->len += len;
823 newskb->data_len += len;
824 }
825 newskb->truesize += newskb->data_len;
cf992af5
DLR
826
827 fl->credits--;
828 /*
829 * We do not refill FLs here, we let the caller do it to overlap a
830 * prefetch.
831 */
7385ecf3 832 return newskb;
cf992af5
DLR
833}
834
4d22de3e
DLR
835/**
836 * get_imm_packet - return the next ingress packet buffer from a response
837 * @resp: the response descriptor containing the packet data
838 *
839 * Return a packet containing the immediate data of the given response.
840 */
841static inline struct sk_buff *get_imm_packet(const struct rsp_desc *resp)
842{
843 struct sk_buff *skb = alloc_skb(IMMED_PKT_SIZE, GFP_ATOMIC);
844
845 if (skb) {
846 __skb_put(skb, IMMED_PKT_SIZE);
27d7ff46 847 skb_copy_to_linear_data(skb, resp->imm_data, IMMED_PKT_SIZE);
4d22de3e
DLR
848 }
849 return skb;
850}
851
852/**
853 * calc_tx_descs - calculate the number of Tx descriptors for a packet
854 * @skb: the packet
855 *
856 * Returns the number of Tx descriptors needed for the given Ethernet
857 * packet. Ethernet packets require addition of WR and CPL headers.
858 */
859static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
860{
861 unsigned int flits;
862
863 if (skb->len <= WR_LEN - sizeof(struct cpl_tx_pkt))
864 return 1;
865
866 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 2;
867 if (skb_shinfo(skb)->gso_size)
868 flits++;
869 return flits_to_desc(flits);
870}
871
872/**
873 * make_sgl - populate a scatter/gather list for a packet
874 * @skb: the packet
875 * @sgp: the SGL to populate
876 * @start: start address of skb main body data to include in the SGL
877 * @len: length of skb main body data to include in the SGL
878 * @pdev: the PCI device
879 *
880 * Generates a scatter/gather list for the buffers that make up a packet
881 * and returns the SGL size in 8-byte words. The caller must size the SGL
882 * appropriately.
883 */
884static inline unsigned int make_sgl(const struct sk_buff *skb,
885 struct sg_ent *sgp, unsigned char *start,
886 unsigned int len, struct pci_dev *pdev)
887{
888 dma_addr_t mapping;
889 unsigned int i, j = 0, nfrags;
890
891 if (len) {
892 mapping = pci_map_single(pdev, start, len, PCI_DMA_TODEVICE);
893 sgp->len[0] = cpu_to_be32(len);
894 sgp->addr[0] = cpu_to_be64(mapping);
895 j = 1;
896 }
897
898 nfrags = skb_shinfo(skb)->nr_frags;
899 for (i = 0; i < nfrags; i++) {
900 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
901
902 mapping = pci_map_page(pdev, frag->page, frag->page_offset,
903 frag->size, PCI_DMA_TODEVICE);
904 sgp->len[j] = cpu_to_be32(frag->size);
905 sgp->addr[j] = cpu_to_be64(mapping);
906 j ^= 1;
907 if (j == 0)
908 ++sgp;
909 }
910 if (j)
911 sgp->len[j] = 0;
912 return ((nfrags + (len != 0)) * 3) / 2 + j;
913}
914
915/**
916 * check_ring_tx_db - check and potentially ring a Tx queue's doorbell
917 * @adap: the adapter
918 * @q: the Tx queue
919 *
920 * Ring the doorbel if a Tx queue is asleep. There is a natural race,
921 * where the HW is going to sleep just after we checked, however,
922 * then the interrupt handler will detect the outstanding TX packet
923 * and ring the doorbell for us.
924 *
925 * When GTS is disabled we unconditionally ring the doorbell.
926 */
927static inline void check_ring_tx_db(struct adapter *adap, struct sge_txq *q)
928{
929#if USE_GTS
930 clear_bit(TXQ_LAST_PKT_DB, &q->flags);
931 if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) {
932 set_bit(TXQ_LAST_PKT_DB, &q->flags);
933 t3_write_reg(adap, A_SG_KDOORBELL,
934 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
935 }
936#else
937 wmb(); /* write descriptors before telling HW */
938 t3_write_reg(adap, A_SG_KDOORBELL,
939 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
940#endif
941}
942
943static inline void wr_gen2(struct tx_desc *d, unsigned int gen)
944{
945#if SGE_NUM_GENBITS == 2
946 d->flit[TX_DESC_FLITS - 1] = cpu_to_be64(gen);
947#endif
948}
949
950/**
951 * write_wr_hdr_sgl - write a WR header and, optionally, SGL
952 * @ndesc: number of Tx descriptors spanned by the SGL
953 * @skb: the packet corresponding to the WR
954 * @d: first Tx descriptor to be written
955 * @pidx: index of above descriptors
956 * @q: the SGE Tx queue
957 * @sgl: the SGL
958 * @flits: number of flits to the start of the SGL in the first descriptor
959 * @sgl_flits: the SGL size in flits
960 * @gen: the Tx descriptor generation
961 * @wr_hi: top 32 bits of WR header based on WR type (big endian)
962 * @wr_lo: low 32 bits of WR header based on WR type (big endian)
963 *
964 * Write a work request header and an associated SGL. If the SGL is
965 * small enough to fit into one Tx descriptor it has already been written
966 * and we just need to write the WR header. Otherwise we distribute the
967 * SGL across the number of descriptors it spans.
968 */
969static void write_wr_hdr_sgl(unsigned int ndesc, struct sk_buff *skb,
970 struct tx_desc *d, unsigned int pidx,
971 const struct sge_txq *q,
972 const struct sg_ent *sgl,
973 unsigned int flits, unsigned int sgl_flits,
fb8e4444
AV
974 unsigned int gen, __be32 wr_hi,
975 __be32 wr_lo)
4d22de3e
DLR
976{
977 struct work_request_hdr *wrp = (struct work_request_hdr *)d;
978 struct tx_sw_desc *sd = &q->sdesc[pidx];
979
980 sd->skb = skb;
981 if (need_skb_unmap()) {
23561c94
DLR
982 sd->fragidx = 0;
983 sd->addr_idx = 0;
984 sd->sflit = flits;
4d22de3e
DLR
985 }
986
987 if (likely(ndesc == 1)) {
23561c94 988 sd->eop = 1;
4d22de3e
DLR
989 wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) |
990 V_WR_SGLSFLT(flits)) | wr_hi;
991 wmb();
992 wrp->wr_lo = htonl(V_WR_LEN(flits + sgl_flits) |
993 V_WR_GEN(gen)) | wr_lo;
994 wr_gen2(d, gen);
995 } else {
996 unsigned int ogen = gen;
997 const u64 *fp = (const u64 *)sgl;
998 struct work_request_hdr *wp = wrp;
999
1000 wrp->wr_hi = htonl(F_WR_SOP | V_WR_DATATYPE(1) |
1001 V_WR_SGLSFLT(flits)) | wr_hi;
1002
1003 while (sgl_flits) {
1004 unsigned int avail = WR_FLITS - flits;
1005
1006 if (avail > sgl_flits)
1007 avail = sgl_flits;
1008 memcpy(&d->flit[flits], fp, avail * sizeof(*fp));
1009 sgl_flits -= avail;
1010 ndesc--;
1011 if (!sgl_flits)
1012 break;
1013
1014 fp += avail;
1015 d++;
23561c94 1016 sd->eop = 0;
4d22de3e
DLR
1017 sd++;
1018 if (++pidx == q->size) {
1019 pidx = 0;
1020 gen ^= 1;
1021 d = q->desc;
1022 sd = q->sdesc;
1023 }
1024
1025 sd->skb = skb;
1026 wrp = (struct work_request_hdr *)d;
1027 wrp->wr_hi = htonl(V_WR_DATATYPE(1) |
1028 V_WR_SGLSFLT(1)) | wr_hi;
1029 wrp->wr_lo = htonl(V_WR_LEN(min(WR_FLITS,
1030 sgl_flits + 1)) |
1031 V_WR_GEN(gen)) | wr_lo;
1032 wr_gen2(d, gen);
1033 flits = 1;
1034 }
23561c94 1035 sd->eop = 1;
4d22de3e
DLR
1036 wrp->wr_hi |= htonl(F_WR_EOP);
1037 wmb();
1038 wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo;
1039 wr_gen2((struct tx_desc *)wp, ogen);
1040 WARN_ON(ndesc != 0);
1041 }
1042}
1043
1044/**
1045 * write_tx_pkt_wr - write a TX_PKT work request
1046 * @adap: the adapter
1047 * @skb: the packet to send
1048 * @pi: the egress interface
1049 * @pidx: index of the first Tx descriptor to write
1050 * @gen: the generation value to use
1051 * @q: the Tx queue
1052 * @ndesc: number of descriptors the packet will occupy
1053 * @compl: the value of the COMPL bit to use
1054 *
1055 * Generate a TX_PKT work request to send the supplied packet.
1056 */
1057static void write_tx_pkt_wr(struct adapter *adap, struct sk_buff *skb,
1058 const struct port_info *pi,
1059 unsigned int pidx, unsigned int gen,
1060 struct sge_txq *q, unsigned int ndesc,
1061 unsigned int compl)
1062{
1063 unsigned int flits, sgl_flits, cntrl, tso_info;
1064 struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
1065 struct tx_desc *d = &q->desc[pidx];
1066 struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)d;
1067
1068 cpl->len = htonl(skb->len | 0x80000000);
1069 cntrl = V_TXPKT_INTF(pi->port_id);
1070
1071 if (vlan_tx_tag_present(skb) && pi->vlan_grp)
1072 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb));
1073
1074 tso_info = V_LSO_MSS(skb_shinfo(skb)->gso_size);
1075 if (tso_info) {
1076 int eth_type;
1077 struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)cpl;
1078
1079 d->flit[2] = 0;
1080 cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO);
1081 hdr->cntrl = htonl(cntrl);
bbe735e4 1082 eth_type = skb_network_offset(skb) == ETH_HLEN ?
4d22de3e
DLR
1083 CPL_ETH_II : CPL_ETH_II_VLAN;
1084 tso_info |= V_LSO_ETH_TYPE(eth_type) |
eddc9ec5 1085 V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) |
aa8223c7 1086 V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff);
4d22de3e
DLR
1087 hdr->lso_info = htonl(tso_info);
1088 flits = 3;
1089 } else {
1090 cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT);
1091 cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */
1092 cntrl |= V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL);
1093 cpl->cntrl = htonl(cntrl);
1094
1095 if (skb->len <= WR_LEN - sizeof(*cpl)) {
1096 q->sdesc[pidx].skb = NULL;
1097 if (!skb->data_len)
d626f62b
ACM
1098 skb_copy_from_linear_data(skb, &d->flit[2],
1099 skb->len);
4d22de3e
DLR
1100 else
1101 skb_copy_bits(skb, 0, &d->flit[2], skb->len);
1102
1103 flits = (skb->len + 7) / 8 + 2;
1104 cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(skb->len & 7) |
1105 V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT)
1106 | F_WR_SOP | F_WR_EOP | compl);
1107 wmb();
1108 cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(gen) |
1109 V_WR_TID(q->token));
1110 wr_gen2(d, gen);
1111 kfree_skb(skb);
1112 return;
1113 }
1114
1115 flits = 2;
1116 }
1117
1118 sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
1119 sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), adap->pdev);
4d22de3e
DLR
1120
1121 write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, gen,
1122 htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | compl),
1123 htonl(V_WR_TID(q->token)));
1124}
1125
a8cc21f6
KK
1126static inline void t3_stop_queue(struct net_device *dev, struct sge_qset *qs,
1127 struct sge_txq *q)
1128{
1129 netif_stop_queue(dev);
1130 set_bit(TXQ_ETH, &qs->txq_stopped);
1131 q->stops++;
1132}
1133
4d22de3e
DLR
1134/**
1135 * eth_xmit - add a packet to the Ethernet Tx queue
1136 * @skb: the packet
1137 * @dev: the egress net device
1138 *
1139 * Add a packet to an SGE Tx queue. Runs with softirqs disabled.
1140 */
1141int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1142{
1143 unsigned int ndesc, pidx, credits, gen, compl;
1144 const struct port_info *pi = netdev_priv(dev);
5fbf816f 1145 struct adapter *adap = pi->adapter;
bea3348e 1146 struct sge_qset *qs = pi->qs;
4d22de3e
DLR
1147 struct sge_txq *q = &qs->txq[TXQ_ETH];
1148
1149 /*
1150 * The chip min packet length is 9 octets but play safe and reject
1151 * anything shorter than an Ethernet header.
1152 */
1153 if (unlikely(skb->len < ETH_HLEN)) {
1154 dev_kfree_skb(skb);
1155 return NETDEV_TX_OK;
1156 }
1157
1158 spin_lock(&q->lock);
1159 reclaim_completed_tx(adap, q);
1160
1161 credits = q->size - q->in_use;
1162 ndesc = calc_tx_descs(skb);
1163
1164 if (unlikely(credits < ndesc)) {
a8cc21f6
KK
1165 t3_stop_queue(dev, qs, q);
1166 dev_err(&adap->pdev->dev,
1167 "%s: Tx ring %u full while queue awake!\n",
1168 dev->name, q->cntxt_id & 7);
4d22de3e
DLR
1169 spin_unlock(&q->lock);
1170 return NETDEV_TX_BUSY;
1171 }
1172
1173 q->in_use += ndesc;
cd7e9034
DLR
1174 if (unlikely(credits - ndesc < q->stop_thres)) {
1175 t3_stop_queue(dev, qs, q);
1176
1177 if (should_restart_tx(q) &&
1178 test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
1179 q->restarts++;
1180 netif_wake_queue(dev);
1181 }
1182 }
4d22de3e
DLR
1183
1184 gen = q->gen;
1185 q->unacked += ndesc;
1186 compl = (q->unacked & 8) << (S_WR_COMPL - 3);
1187 q->unacked &= 7;
1188 pidx = q->pidx;
1189 q->pidx += ndesc;
1190 if (q->pidx >= q->size) {
1191 q->pidx -= q->size;
1192 q->gen ^= 1;
1193 }
1194
1195 /* update port statistics */
1196 if (skb->ip_summed == CHECKSUM_COMPLETE)
1197 qs->port_stats[SGE_PSTAT_TX_CSUM]++;
1198 if (skb_shinfo(skb)->gso_size)
1199 qs->port_stats[SGE_PSTAT_TSO]++;
1200 if (vlan_tx_tag_present(skb) && pi->vlan_grp)
1201 qs->port_stats[SGE_PSTAT_VLANINS]++;
1202
1203 dev->trans_start = jiffies;
1204 spin_unlock(&q->lock);
1205
1206 /*
1207 * We do not use Tx completion interrupts to free DMAd Tx packets.
1208 * This is good for performamce but means that we rely on new Tx
1209 * packets arriving to run the destructors of completed packets,
1210 * which open up space in their sockets' send queues. Sometimes
1211 * we do not get such new packets causing Tx to stall. A single
1212 * UDP transmitter is a good example of this situation. We have
1213 * a clean up timer that periodically reclaims completed packets
1214 * but it doesn't run often enough (nor do we want it to) to prevent
1215 * lengthy stalls. A solution to this problem is to run the
1216 * destructor early, after the packet is queued but before it's DMAd.
1217 * A cons is that we lie to socket memory accounting, but the amount
1218 * of extra memory is reasonable (limited by the number of Tx
1219 * descriptors), the packets do actually get freed quickly by new
1220 * packets almost always, and for protocols like TCP that wait for
1221 * acks to really free up the data the extra memory is even less.
1222 * On the positive side we run the destructors on the sending CPU
1223 * rather than on a potentially different completing CPU, usually a
1224 * good thing. We also run them without holding our Tx queue lock,
1225 * unlike what reclaim_completed_tx() would otherwise do.
1226 *
1227 * Run the destructor before telling the DMA engine about the packet
1228 * to make sure it doesn't complete and get freed prematurely.
1229 */
1230 if (likely(!skb_shared(skb)))
1231 skb_orphan(skb);
1232
1233 write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl);
1234 check_ring_tx_db(adap, q);
1235 return NETDEV_TX_OK;
1236}
1237
1238/**
1239 * write_imm - write a packet into a Tx descriptor as immediate data
1240 * @d: the Tx descriptor to write
1241 * @skb: the packet
1242 * @len: the length of packet data to write as immediate data
1243 * @gen: the generation bit value to write
1244 *
1245 * Writes a packet as immediate data into a Tx descriptor. The packet
1246 * contains a work request at its beginning. We must write the packet
27186dc3
DLR
1247 * carefully so the SGE doesn't read it accidentally before it's written
1248 * in its entirety.
4d22de3e
DLR
1249 */
1250static inline void write_imm(struct tx_desc *d, struct sk_buff *skb,
1251 unsigned int len, unsigned int gen)
1252{
1253 struct work_request_hdr *from = (struct work_request_hdr *)skb->data;
1254 struct work_request_hdr *to = (struct work_request_hdr *)d;
1255
27186dc3
DLR
1256 if (likely(!skb->data_len))
1257 memcpy(&to[1], &from[1], len - sizeof(*from));
1258 else
1259 skb_copy_bits(skb, sizeof(*from), &to[1], len - sizeof(*from));
1260
4d22de3e
DLR
1261 to->wr_hi = from->wr_hi | htonl(F_WR_SOP | F_WR_EOP |
1262 V_WR_BCNTLFLT(len & 7));
1263 wmb();
1264 to->wr_lo = from->wr_lo | htonl(V_WR_GEN(gen) |
1265 V_WR_LEN((len + 7) / 8));
1266 wr_gen2(d, gen);
1267 kfree_skb(skb);
1268}
1269
1270/**
1271 * check_desc_avail - check descriptor availability on a send queue
1272 * @adap: the adapter
1273 * @q: the send queue
1274 * @skb: the packet needing the descriptors
1275 * @ndesc: the number of Tx descriptors needed
1276 * @qid: the Tx queue number in its queue set (TXQ_OFLD or TXQ_CTRL)
1277 *
1278 * Checks if the requested number of Tx descriptors is available on an
1279 * SGE send queue. If the queue is already suspended or not enough
1280 * descriptors are available the packet is queued for later transmission.
1281 * Must be called with the Tx queue locked.
1282 *
1283 * Returns 0 if enough descriptors are available, 1 if there aren't
1284 * enough descriptors and the packet has been queued, and 2 if the caller
1285 * needs to retry because there weren't enough descriptors at the
1286 * beginning of the call but some freed up in the mean time.
1287 */
1288static inline int check_desc_avail(struct adapter *adap, struct sge_txq *q,
1289 struct sk_buff *skb, unsigned int ndesc,
1290 unsigned int qid)
1291{
1292 if (unlikely(!skb_queue_empty(&q->sendq))) {
1293 addq_exit:__skb_queue_tail(&q->sendq, skb);
1294 return 1;
1295 }
1296 if (unlikely(q->size - q->in_use < ndesc)) {
1297 struct sge_qset *qs = txq_to_qset(q, qid);
1298
1299 set_bit(qid, &qs->txq_stopped);
1300 smp_mb__after_clear_bit();
1301
1302 if (should_restart_tx(q) &&
1303 test_and_clear_bit(qid, &qs->txq_stopped))
1304 return 2;
1305
1306 q->stops++;
1307 goto addq_exit;
1308 }
1309 return 0;
1310}
1311
1312/**
1313 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1314 * @q: the SGE control Tx queue
1315 *
1316 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1317 * that send only immediate data (presently just the control queues) and
1318 * thus do not have any sk_buffs to release.
1319 */
1320static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1321{
1322 unsigned int reclaim = q->processed - q->cleaned;
1323
1324 q->in_use -= reclaim;
1325 q->cleaned += reclaim;
1326}
1327
1328static inline int immediate(const struct sk_buff *skb)
1329{
27186dc3 1330 return skb->len <= WR_LEN;
4d22de3e
DLR
1331}
1332
1333/**
1334 * ctrl_xmit - send a packet through an SGE control Tx queue
1335 * @adap: the adapter
1336 * @q: the control queue
1337 * @skb: the packet
1338 *
1339 * Send a packet through an SGE control Tx queue. Packets sent through
1340 * a control queue must fit entirely as immediate data in a single Tx
1341 * descriptor and have no page fragments.
1342 */
1343static int ctrl_xmit(struct adapter *adap, struct sge_txq *q,
1344 struct sk_buff *skb)
1345{
1346 int ret;
1347 struct work_request_hdr *wrp = (struct work_request_hdr *)skb->data;
1348
1349 if (unlikely(!immediate(skb))) {
1350 WARN_ON(1);
1351 dev_kfree_skb(skb);
1352 return NET_XMIT_SUCCESS;
1353 }
1354
1355 wrp->wr_hi |= htonl(F_WR_SOP | F_WR_EOP);
1356 wrp->wr_lo = htonl(V_WR_TID(q->token));
1357
1358 spin_lock(&q->lock);
1359 again:reclaim_completed_tx_imm(q);
1360
1361 ret = check_desc_avail(adap, q, skb, 1, TXQ_CTRL);
1362 if (unlikely(ret)) {
1363 if (ret == 1) {
1364 spin_unlock(&q->lock);
1365 return NET_XMIT_CN;
1366 }
1367 goto again;
1368 }
1369
1370 write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
1371
1372 q->in_use++;
1373 if (++q->pidx >= q->size) {
1374 q->pidx = 0;
1375 q->gen ^= 1;
1376 }
1377 spin_unlock(&q->lock);
1378 wmb();
1379 t3_write_reg(adap, A_SG_KDOORBELL,
1380 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1381 return NET_XMIT_SUCCESS;
1382}
1383
1384/**
1385 * restart_ctrlq - restart a suspended control queue
1386 * @qs: the queue set cotaining the control queue
1387 *
1388 * Resumes transmission on a suspended Tx control queue.
1389 */
1390static void restart_ctrlq(unsigned long data)
1391{
1392 struct sk_buff *skb;
1393 struct sge_qset *qs = (struct sge_qset *)data;
1394 struct sge_txq *q = &qs->txq[TXQ_CTRL];
4d22de3e
DLR
1395
1396 spin_lock(&q->lock);
1397 again:reclaim_completed_tx_imm(q);
1398
bea3348e
SH
1399 while (q->in_use < q->size &&
1400 (skb = __skb_dequeue(&q->sendq)) != NULL) {
4d22de3e
DLR
1401
1402 write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
1403
1404 if (++q->pidx >= q->size) {
1405 q->pidx = 0;
1406 q->gen ^= 1;
1407 }
1408 q->in_use++;
1409 }
1410
1411 if (!skb_queue_empty(&q->sendq)) {
1412 set_bit(TXQ_CTRL, &qs->txq_stopped);
1413 smp_mb__after_clear_bit();
1414
1415 if (should_restart_tx(q) &&
1416 test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped))
1417 goto again;
1418 q->stops++;
1419 }
1420
1421 spin_unlock(&q->lock);
afefce66 1422 wmb();
bea3348e 1423 t3_write_reg(qs->adap, A_SG_KDOORBELL,
4d22de3e
DLR
1424 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1425}
1426
14ab9892
DLR
1427/*
1428 * Send a management message through control queue 0
1429 */
1430int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1431{
204e2f98 1432 int ret;
bc4b6b52
DLR
1433 local_bh_disable();
1434 ret = ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], skb);
1435 local_bh_enable();
1436
1437 return ret;
14ab9892
DLR
1438}
1439
99d7cf30
DLR
1440/**
1441 * deferred_unmap_destructor - unmap a packet when it is freed
1442 * @skb: the packet
1443 *
1444 * This is the packet destructor used for Tx packets that need to remain
1445 * mapped until they are freed rather than until their Tx descriptors are
1446 * freed.
1447 */
1448static void deferred_unmap_destructor(struct sk_buff *skb)
1449{
1450 int i;
1451 const dma_addr_t *p;
1452 const struct skb_shared_info *si;
1453 const struct deferred_unmap_info *dui;
99d7cf30
DLR
1454
1455 dui = (struct deferred_unmap_info *)skb->head;
1456 p = dui->addr;
1457
23561c94
DLR
1458 if (skb->tail - skb->transport_header)
1459 pci_unmap_single(dui->pdev, *p++,
1460 skb->tail - skb->transport_header,
1461 PCI_DMA_TODEVICE);
99d7cf30
DLR
1462
1463 si = skb_shinfo(skb);
1464 for (i = 0; i < si->nr_frags; i++)
1465 pci_unmap_page(dui->pdev, *p++, si->frags[i].size,
1466 PCI_DMA_TODEVICE);
1467}
1468
1469static void setup_deferred_unmapping(struct sk_buff *skb, struct pci_dev *pdev,
1470 const struct sg_ent *sgl, int sgl_flits)
1471{
1472 dma_addr_t *p;
1473 struct deferred_unmap_info *dui;
1474
1475 dui = (struct deferred_unmap_info *)skb->head;
1476 dui->pdev = pdev;
1477 for (p = dui->addr; sgl_flits >= 3; sgl++, sgl_flits -= 3) {
1478 *p++ = be64_to_cpu(sgl->addr[0]);
1479 *p++ = be64_to_cpu(sgl->addr[1]);
1480 }
1481 if (sgl_flits)
1482 *p = be64_to_cpu(sgl->addr[0]);
1483}
1484
4d22de3e
DLR
1485/**
1486 * write_ofld_wr - write an offload work request
1487 * @adap: the adapter
1488 * @skb: the packet to send
1489 * @q: the Tx queue
1490 * @pidx: index of the first Tx descriptor to write
1491 * @gen: the generation value to use
1492 * @ndesc: number of descriptors the packet will occupy
1493 *
1494 * Write an offload work request to send the supplied packet. The packet
1495 * data already carry the work request with most fields populated.
1496 */
1497static void write_ofld_wr(struct adapter *adap, struct sk_buff *skb,
1498 struct sge_txq *q, unsigned int pidx,
1499 unsigned int gen, unsigned int ndesc)
1500{
1501 unsigned int sgl_flits, flits;
1502 struct work_request_hdr *from;
1503 struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
1504 struct tx_desc *d = &q->desc[pidx];
1505
1506 if (immediate(skb)) {
1507 q->sdesc[pidx].skb = NULL;
1508 write_imm(d, skb, skb->len, gen);
1509 return;
1510 }
1511
1512 /* Only TX_DATA builds SGLs */
1513
1514 from = (struct work_request_hdr *)skb->data;
ea2ae17d
ACM
1515 memcpy(&d->flit[1], &from[1],
1516 skb_transport_offset(skb) - sizeof(*from));
4d22de3e 1517
ea2ae17d 1518 flits = skb_transport_offset(skb) / 8;
4d22de3e 1519 sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
9c70220b 1520 sgl_flits = make_sgl(skb, sgp, skb_transport_header(skb),
27a884dc 1521 skb->tail - skb->transport_header,
4d22de3e 1522 adap->pdev);
99d7cf30
DLR
1523 if (need_skb_unmap()) {
1524 setup_deferred_unmapping(skb, adap->pdev, sgp, sgl_flits);
1525 skb->destructor = deferred_unmap_destructor;
99d7cf30 1526 }
4d22de3e
DLR
1527
1528 write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits,
1529 gen, from->wr_hi, from->wr_lo);
1530}
1531
1532/**
1533 * calc_tx_descs_ofld - calculate # of Tx descriptors for an offload packet
1534 * @skb: the packet
1535 *
1536 * Returns the number of Tx descriptors needed for the given offload
1537 * packet. These packets are already fully constructed.
1538 */
1539static inline unsigned int calc_tx_descs_ofld(const struct sk_buff *skb)
1540{
27186dc3 1541 unsigned int flits, cnt;
4d22de3e 1542
27186dc3 1543 if (skb->len <= WR_LEN)
4d22de3e
DLR
1544 return 1; /* packet fits as immediate data */
1545
ea2ae17d 1546 flits = skb_transport_offset(skb) / 8; /* headers */
27186dc3 1547 cnt = skb_shinfo(skb)->nr_frags;
27a884dc 1548 if (skb->tail != skb->transport_header)
4d22de3e
DLR
1549 cnt++;
1550 return flits_to_desc(flits + sgl_len(cnt));
1551}
1552
1553/**
1554 * ofld_xmit - send a packet through an offload queue
1555 * @adap: the adapter
1556 * @q: the Tx offload queue
1557 * @skb: the packet
1558 *
1559 * Send an offload packet through an SGE offload queue.
1560 */
1561static int ofld_xmit(struct adapter *adap, struct sge_txq *q,
1562 struct sk_buff *skb)
1563{
1564 int ret;
1565 unsigned int ndesc = calc_tx_descs_ofld(skb), pidx, gen;
1566
1567 spin_lock(&q->lock);
1568 again:reclaim_completed_tx(adap, q);
1569
1570 ret = check_desc_avail(adap, q, skb, ndesc, TXQ_OFLD);
1571 if (unlikely(ret)) {
1572 if (ret == 1) {
1573 skb->priority = ndesc; /* save for restart */
1574 spin_unlock(&q->lock);
1575 return NET_XMIT_CN;
1576 }
1577 goto again;
1578 }
1579
1580 gen = q->gen;
1581 q->in_use += ndesc;
1582 pidx = q->pidx;
1583 q->pidx += ndesc;
1584 if (q->pidx >= q->size) {
1585 q->pidx -= q->size;
1586 q->gen ^= 1;
1587 }
1588 spin_unlock(&q->lock);
1589
1590 write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
1591 check_ring_tx_db(adap, q);
1592 return NET_XMIT_SUCCESS;
1593}
1594
1595/**
1596 * restart_offloadq - restart a suspended offload queue
1597 * @qs: the queue set cotaining the offload queue
1598 *
1599 * Resumes transmission on a suspended Tx offload queue.
1600 */
1601static void restart_offloadq(unsigned long data)
1602{
1603 struct sk_buff *skb;
1604 struct sge_qset *qs = (struct sge_qset *)data;
1605 struct sge_txq *q = &qs->txq[TXQ_OFLD];
5fbf816f
DLR
1606 const struct port_info *pi = netdev_priv(qs->netdev);
1607 struct adapter *adap = pi->adapter;
4d22de3e
DLR
1608
1609 spin_lock(&q->lock);
1610 again:reclaim_completed_tx(adap, q);
1611
1612 while ((skb = skb_peek(&q->sendq)) != NULL) {
1613 unsigned int gen, pidx;
1614 unsigned int ndesc = skb->priority;
1615
1616 if (unlikely(q->size - q->in_use < ndesc)) {
1617 set_bit(TXQ_OFLD, &qs->txq_stopped);
1618 smp_mb__after_clear_bit();
1619
1620 if (should_restart_tx(q) &&
1621 test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped))
1622 goto again;
1623 q->stops++;
1624 break;
1625 }
1626
1627 gen = q->gen;
1628 q->in_use += ndesc;
1629 pidx = q->pidx;
1630 q->pidx += ndesc;
1631 if (q->pidx >= q->size) {
1632 q->pidx -= q->size;
1633 q->gen ^= 1;
1634 }
1635 __skb_unlink(skb, &q->sendq);
1636 spin_unlock(&q->lock);
1637
1638 write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
1639 spin_lock(&q->lock);
1640 }
1641 spin_unlock(&q->lock);
1642
1643#if USE_GTS
1644 set_bit(TXQ_RUNNING, &q->flags);
1645 set_bit(TXQ_LAST_PKT_DB, &q->flags);
1646#endif
afefce66 1647 wmb();
4d22de3e
DLR
1648 t3_write_reg(adap, A_SG_KDOORBELL,
1649 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1650}
1651
1652/**
1653 * queue_set - return the queue set a packet should use
1654 * @skb: the packet
1655 *
1656 * Maps a packet to the SGE queue set it should use. The desired queue
1657 * set is carried in bits 1-3 in the packet's priority.
1658 */
1659static inline int queue_set(const struct sk_buff *skb)
1660{
1661 return skb->priority >> 1;
1662}
1663
1664/**
1665 * is_ctrl_pkt - return whether an offload packet is a control packet
1666 * @skb: the packet
1667 *
1668 * Determines whether an offload packet should use an OFLD or a CTRL
1669 * Tx queue. This is indicated by bit 0 in the packet's priority.
1670 */
1671static inline int is_ctrl_pkt(const struct sk_buff *skb)
1672{
1673 return skb->priority & 1;
1674}
1675
1676/**
1677 * t3_offload_tx - send an offload packet
1678 * @tdev: the offload device to send to
1679 * @skb: the packet
1680 *
1681 * Sends an offload packet. We use the packet priority to select the
1682 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1683 * should be sent as regular or control, bits 1-3 select the queue set.
1684 */
1685int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
1686{
1687 struct adapter *adap = tdev2adap(tdev);
1688 struct sge_qset *qs = &adap->sge.qs[queue_set(skb)];
1689
1690 if (unlikely(is_ctrl_pkt(skb)))
1691 return ctrl_xmit(adap, &qs->txq[TXQ_CTRL], skb);
1692
1693 return ofld_xmit(adap, &qs->txq[TXQ_OFLD], skb);
1694}
1695
1696/**
1697 * offload_enqueue - add an offload packet to an SGE offload receive queue
1698 * @q: the SGE response queue
1699 * @skb: the packet
1700 *
1701 * Add a new offload packet to an SGE response queue's offload packet
1702 * queue. If the packet is the first on the queue it schedules the RX
1703 * softirq to process the queue.
1704 */
1705static inline void offload_enqueue(struct sge_rspq *q, struct sk_buff *skb)
1706{
1707 skb->next = skb->prev = NULL;
1708 if (q->rx_tail)
1709 q->rx_tail->next = skb;
1710 else {
1711 struct sge_qset *qs = rspq_to_qset(q);
1712
bea3348e 1713 napi_schedule(&qs->napi);
4d22de3e
DLR
1714 q->rx_head = skb;
1715 }
1716 q->rx_tail = skb;
1717}
1718
1719/**
1720 * deliver_partial_bundle - deliver a (partial) bundle of Rx offload pkts
1721 * @tdev: the offload device that will be receiving the packets
1722 * @q: the SGE response queue that assembled the bundle
1723 * @skbs: the partial bundle
1724 * @n: the number of packets in the bundle
1725 *
1726 * Delivers a (partial) bundle of Rx offload packets to an offload device.
1727 */
1728static inline void deliver_partial_bundle(struct t3cdev *tdev,
1729 struct sge_rspq *q,
1730 struct sk_buff *skbs[], int n)
1731{
1732 if (n) {
1733 q->offload_bundles++;
1734 tdev->recv(tdev, skbs, n);
1735 }
1736}
1737
1738/**
1739 * ofld_poll - NAPI handler for offload packets in interrupt mode
1740 * @dev: the network device doing the polling
1741 * @budget: polling budget
1742 *
1743 * The NAPI handler for offload packets when a response queue is serviced
1744 * by the hard interrupt handler, i.e., when it's operating in non-polling
1745 * mode. Creates small packet batches and sends them through the offload
1746 * receive handler. Batches need to be of modest size as we do prefetches
1747 * on the packets in each.
1748 */
bea3348e 1749static int ofld_poll(struct napi_struct *napi, int budget)
4d22de3e 1750{
bea3348e 1751 struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
4d22de3e 1752 struct sge_rspq *q = &qs->rspq;
bea3348e
SH
1753 struct adapter *adapter = qs->adap;
1754 int work_done = 0;
4d22de3e 1755
bea3348e 1756 while (work_done < budget) {
4d22de3e
DLR
1757 struct sk_buff *head, *tail, *skbs[RX_BUNDLE_SIZE];
1758 int ngathered;
1759
1760 spin_lock_irq(&q->lock);
1761 head = q->rx_head;
1762 if (!head) {
bea3348e 1763 napi_complete(napi);
4d22de3e 1764 spin_unlock_irq(&q->lock);
bea3348e 1765 return work_done;
4d22de3e
DLR
1766 }
1767
1768 tail = q->rx_tail;
1769 q->rx_head = q->rx_tail = NULL;
1770 spin_unlock_irq(&q->lock);
1771
bea3348e 1772 for (ngathered = 0; work_done < budget && head; work_done++) {
4d22de3e
DLR
1773 prefetch(head->data);
1774 skbs[ngathered] = head;
1775 head = head->next;
1776 skbs[ngathered]->next = NULL;
1777 if (++ngathered == RX_BUNDLE_SIZE) {
1778 q->offload_bundles++;
1779 adapter->tdev.recv(&adapter->tdev, skbs,
1780 ngathered);
1781 ngathered = 0;
1782 }
1783 }
1784 if (head) { /* splice remaining packets back onto Rx queue */
1785 spin_lock_irq(&q->lock);
1786 tail->next = q->rx_head;
1787 if (!q->rx_head)
1788 q->rx_tail = tail;
1789 q->rx_head = head;
1790 spin_unlock_irq(&q->lock);
1791 }
1792 deliver_partial_bundle(&adapter->tdev, q, skbs, ngathered);
1793 }
bea3348e
SH
1794
1795 return work_done;
4d22de3e
DLR
1796}
1797
1798/**
1799 * rx_offload - process a received offload packet
1800 * @tdev: the offload device receiving the packet
1801 * @rq: the response queue that received the packet
1802 * @skb: the packet
1803 * @rx_gather: a gather list of packets if we are building a bundle
1804 * @gather_idx: index of the next available slot in the bundle
1805 *
1806 * Process an ingress offload pakcet and add it to the offload ingress
1807 * queue. Returns the index of the next available slot in the bundle.
1808 */
1809static inline int rx_offload(struct t3cdev *tdev, struct sge_rspq *rq,
1810 struct sk_buff *skb, struct sk_buff *rx_gather[],
1811 unsigned int gather_idx)
1812{
459a98ed 1813 skb_reset_mac_header(skb);
c1d2bbe1 1814 skb_reset_network_header(skb);
badff6d0 1815 skb_reset_transport_header(skb);
4d22de3e
DLR
1816
1817 if (rq->polling) {
1818 rx_gather[gather_idx++] = skb;
1819 if (gather_idx == RX_BUNDLE_SIZE) {
1820 tdev->recv(tdev, rx_gather, RX_BUNDLE_SIZE);
1821 gather_idx = 0;
1822 rq->offload_bundles++;
1823 }
1824 } else
1825 offload_enqueue(rq, skb);
1826
1827 return gather_idx;
1828}
1829
4d22de3e
DLR
1830/**
1831 * restart_tx - check whether to restart suspended Tx queues
1832 * @qs: the queue set to resume
1833 *
1834 * Restarts suspended Tx queues of an SGE queue set if they have enough
1835 * free resources to resume operation.
1836 */
1837static void restart_tx(struct sge_qset *qs)
1838{
1839 if (test_bit(TXQ_ETH, &qs->txq_stopped) &&
1840 should_restart_tx(&qs->txq[TXQ_ETH]) &&
1841 test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
1842 qs->txq[TXQ_ETH].restarts++;
1843 if (netif_running(qs->netdev))
1844 netif_wake_queue(qs->netdev);
1845 }
1846
1847 if (test_bit(TXQ_OFLD, &qs->txq_stopped) &&
1848 should_restart_tx(&qs->txq[TXQ_OFLD]) &&
1849 test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) {
1850 qs->txq[TXQ_OFLD].restarts++;
1851 tasklet_schedule(&qs->txq[TXQ_OFLD].qresume_tsk);
1852 }
1853 if (test_bit(TXQ_CTRL, &qs->txq_stopped) &&
1854 should_restart_tx(&qs->txq[TXQ_CTRL]) &&
1855 test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) {
1856 qs->txq[TXQ_CTRL].restarts++;
1857 tasklet_schedule(&qs->txq[TXQ_CTRL].qresume_tsk);
1858 }
1859}
1860
1861/**
1862 * rx_eth - process an ingress ethernet packet
1863 * @adap: the adapter
1864 * @rq: the response queue that received the packet
1865 * @skb: the packet
1866 * @pad: amount of padding at the start of the buffer
1867 *
1868 * Process an ingress ethernet pakcet and deliver it to the stack.
1869 * The padding is 2 if the packet was delivered in an Rx buffer and 0
1870 * if it was immediate data in a response.
1871 */
1872static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
b47385bd 1873 struct sk_buff *skb, int pad, int lro)
4d22de3e
DLR
1874{
1875 struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad);
b47385bd 1876 struct sge_qset *qs = rspq_to_qset(rq);
4d22de3e
DLR
1877 struct port_info *pi;
1878
4d22de3e 1879 skb_pull(skb, sizeof(*p) + pad);
4c13eb66 1880 skb->protocol = eth_type_trans(skb, adap->port[p->iff]);
e360b562 1881 skb->dev->last_rx = jiffies;
4d22de3e 1882 pi = netdev_priv(skb->dev);
05e5c116 1883 if (pi->rx_csum_offload && p->csum_valid && p->csum == htons(0xffff) &&
4d22de3e
DLR
1884 !p->fragment) {
1885 rspq_to_qset(rq)->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
1886 skb->ip_summed = CHECKSUM_UNNECESSARY;
1887 } else
1888 skb->ip_summed = CHECKSUM_NONE;
1889
1890 if (unlikely(p->vlan_valid)) {
1891 struct vlan_group *grp = pi->vlan_grp;
1892
b47385bd 1893 qs->port_stats[SGE_PSTAT_VLANEX]++;
4d22de3e 1894 if (likely(grp))
b47385bd
DLR
1895 if (lro)
1896 lro_vlan_hwaccel_receive_skb(&qs->lro_mgr, skb,
1897 grp,
1898 ntohs(p->vlan),
1899 p);
1900 else
1901 __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan),
1902 rq->polling);
4d22de3e
DLR
1903 else
1904 dev_kfree_skb_any(skb);
b47385bd
DLR
1905 } else if (rq->polling) {
1906 if (lro)
1907 lro_receive_skb(&qs->lro_mgr, skb, p);
1908 else
1909 netif_receive_skb(skb);
1910 } else
4d22de3e
DLR
1911 netif_rx(skb);
1912}
1913
b47385bd
DLR
1914static inline int is_eth_tcp(u32 rss)
1915{
1916 return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE;
1917}
1918
1919/**
1920 * lro_frame_ok - check if an ingress packet is eligible for LRO
1921 * @p: the CPL header of the packet
1922 *
1923 * Returns true if a received packet is eligible for LRO.
1924 * The following conditions must be true:
1925 * - packet is TCP/IP Ethernet II (checked elsewhere)
1926 * - not an IP fragment
1927 * - no IP options
1928 * - TCP/IP checksums are correct
1929 * - the packet is for this host
1930 */
1931static inline int lro_frame_ok(const struct cpl_rx_pkt *p)
1932{
1933 const struct ethhdr *eh = (struct ethhdr *)(p + 1);
1934 const struct iphdr *ih = (struct iphdr *)(eh + 1);
1935
1936 return (*((u8 *)p + 1) & 0x90) == 0x10 && p->csum == htons(0xffff) &&
1937 eh->h_proto == htons(ETH_P_IP) && ih->ihl == (sizeof(*ih) >> 2);
1938}
1939
1940#define TCP_FLAG_MASK (TCP_FLAG_CWR | TCP_FLAG_ECE | TCP_FLAG_URG |\
1941 TCP_FLAG_ACK | TCP_FLAG_PSH | TCP_FLAG_RST |\
1942 TCP_FLAG_SYN | TCP_FLAG_FIN)
1943#define TSTAMP_WORD ((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\
1944 (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)
1945
1946/**
1947 * lro_segment_ok - check if a TCP segment is eligible for LRO
1948 * @tcph: the TCP header of the packet
1949 *
1950 * Returns true if a TCP packet is eligible for LRO. This requires that
1951 * the packet have only the ACK flag set and no TCP options besides
1952 * time stamps.
1953 */
1954static inline int lro_segment_ok(const struct tcphdr *tcph)
1955{
1956 int optlen;
1957
1958 if (unlikely((tcp_flag_word(tcph) & TCP_FLAG_MASK) != TCP_FLAG_ACK))
1959 return 0;
1960
1961 optlen = (tcph->doff << 2) - sizeof(*tcph);
1962 if (optlen) {
1963 const u32 *opt = (const u32 *)(tcph + 1);
1964
1965 if (optlen != TCPOLEN_TSTAMP_ALIGNED ||
1966 *opt != htonl(TSTAMP_WORD) || !opt[2])
1967 return 0;
1968 }
1969 return 1;
1970}
1971
1972static int t3_get_lro_header(void **eh, void **iph, void **tcph,
1973 u64 *hdr_flags, void *priv)
1974{
1975 const struct cpl_rx_pkt *cpl = priv;
1976
1977 if (!lro_frame_ok(cpl))
1978 return -1;
1979
1980 *eh = (struct ethhdr *)(cpl + 1);
1981 *iph = (struct iphdr *)((struct ethhdr *)*eh + 1);
1982 *tcph = (struct tcphdr *)((struct iphdr *)*iph + 1);
1983
1984 if (!lro_segment_ok(*tcph))
1985 return -1;
1986
1987 *hdr_flags = LRO_IPV4 | LRO_TCP;
1988 return 0;
1989}
1990
1991static int t3_get_skb_header(struct sk_buff *skb,
1992 void **iph, void **tcph, u64 *hdr_flags,
1993 void *priv)
1994{
1995 void *eh;
1996
1997 return t3_get_lro_header(&eh, iph, tcph, hdr_flags, priv);
1998}
1999
2000static int t3_get_frag_header(struct skb_frag_struct *frag, void **eh,
2001 void **iph, void **tcph, u64 *hdr_flags,
2002 void *priv)
2003{
2004 return t3_get_lro_header(eh, iph, tcph, hdr_flags, priv);
2005}
2006
2007/**
2008 * lro_add_page - add a page chunk to an LRO session
2009 * @adap: the adapter
2010 * @qs: the associated queue set
2011 * @fl: the free list containing the page chunk to add
2012 * @len: packet length
2013 * @complete: Indicates the last fragment of a frame
2014 *
2015 * Add a received packet contained in a page chunk to an existing LRO
2016 * session.
2017 */
2018static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
2019 struct sge_fl *fl, int len, int complete)
2020{
2021 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
2022 struct cpl_rx_pkt *cpl;
2023 struct skb_frag_struct *rx_frag = qs->lro_frag_tbl;
2024 int nr_frags = qs->lro_nfrags, frag_len = qs->lro_frag_len;
2025 int offset = 0;
2026
2027 if (!nr_frags) {
2028 offset = 2 + sizeof(struct cpl_rx_pkt);
2029 qs->lro_va = cpl = sd->pg_chunk.va + 2;
2030 }
2031
2032 fl->credits--;
2033
2034 len -= offset;
2035 pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
2036 fl->buf_size, PCI_DMA_FROMDEVICE);
2037
2038 rx_frag += nr_frags;
2039 rx_frag->page = sd->pg_chunk.page;
2040 rx_frag->page_offset = sd->pg_chunk.offset + offset;
2041 rx_frag->size = len;
2042 frag_len += len;
2043 qs->lro_nfrags++;
2044 qs->lro_frag_len = frag_len;
2045
2046 if (!complete)
2047 return;
2048
2049 qs->lro_nfrags = qs->lro_frag_len = 0;
2050 cpl = qs->lro_va;
2051
2052 if (unlikely(cpl->vlan_valid)) {
2053 struct net_device *dev = qs->netdev;
2054 struct port_info *pi = netdev_priv(dev);
2055 struct vlan_group *grp = pi->vlan_grp;
2056
2057 if (likely(grp != NULL)) {
2058 lro_vlan_hwaccel_receive_frags(&qs->lro_mgr,
2059 qs->lro_frag_tbl,
2060 frag_len, frag_len,
2061 grp, ntohs(cpl->vlan),
2062 cpl, 0);
2063 return;
2064 }
2065 }
2066 lro_receive_frags(&qs->lro_mgr, qs->lro_frag_tbl,
2067 frag_len, frag_len, cpl, 0);
2068}
2069
2070/**
2071 * init_lro_mgr - initialize a LRO manager object
2072 * @lro_mgr: the LRO manager object
2073 */
2074static void init_lro_mgr(struct sge_qset *qs, struct net_lro_mgr *lro_mgr)
2075{
2076 lro_mgr->dev = qs->netdev;
2077 lro_mgr->features = LRO_F_NAPI;
2078 lro_mgr->ip_summed = CHECKSUM_UNNECESSARY;
2079 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2080 lro_mgr->max_desc = T3_MAX_LRO_SES;
2081 lro_mgr->lro_arr = qs->lro_desc;
2082 lro_mgr->get_frag_header = t3_get_frag_header;
2083 lro_mgr->get_skb_header = t3_get_skb_header;
2084 lro_mgr->max_aggr = T3_MAX_LRO_MAX_PKTS;
2085 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2086 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2087}
2088
4d22de3e
DLR
2089/**
2090 * handle_rsp_cntrl_info - handles control information in a response
2091 * @qs: the queue set corresponding to the response
2092 * @flags: the response control flags
4d22de3e
DLR
2093 *
2094 * Handles the control information of an SGE response, such as GTS
2095 * indications and completion credits for the queue set's Tx queues.
6195c71d 2096 * HW coalesces credits, we don't do any extra SW coalescing.
4d22de3e 2097 */
6195c71d 2098static inline void handle_rsp_cntrl_info(struct sge_qset *qs, u32 flags)
4d22de3e
DLR
2099{
2100 unsigned int credits;
2101
2102#if USE_GTS
2103 if (flags & F_RSPD_TXQ0_GTS)
2104 clear_bit(TXQ_RUNNING, &qs->txq[TXQ_ETH].flags);
2105#endif
2106
4d22de3e
DLR
2107 credits = G_RSPD_TXQ0_CR(flags);
2108 if (credits)
2109 qs->txq[TXQ_ETH].processed += credits;
2110
6195c71d
DLR
2111 credits = G_RSPD_TXQ2_CR(flags);
2112 if (credits)
2113 qs->txq[TXQ_CTRL].processed += credits;
2114
4d22de3e
DLR
2115# if USE_GTS
2116 if (flags & F_RSPD_TXQ1_GTS)
2117 clear_bit(TXQ_RUNNING, &qs->txq[TXQ_OFLD].flags);
2118# endif
6195c71d
DLR
2119 credits = G_RSPD_TXQ1_CR(flags);
2120 if (credits)
2121 qs->txq[TXQ_OFLD].processed += credits;
4d22de3e
DLR
2122}
2123
2124/**
2125 * check_ring_db - check if we need to ring any doorbells
2126 * @adapter: the adapter
2127 * @qs: the queue set whose Tx queues are to be examined
2128 * @sleeping: indicates which Tx queue sent GTS
2129 *
2130 * Checks if some of a queue set's Tx queues need to ring their doorbells
2131 * to resume transmission after idling while they still have unprocessed
2132 * descriptors.
2133 */
2134static void check_ring_db(struct adapter *adap, struct sge_qset *qs,
2135 unsigned int sleeping)
2136{
2137 if (sleeping & F_RSPD_TXQ0_GTS) {
2138 struct sge_txq *txq = &qs->txq[TXQ_ETH];
2139
2140 if (txq->cleaned + txq->in_use != txq->processed &&
2141 !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
2142 set_bit(TXQ_RUNNING, &txq->flags);
2143 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
2144 V_EGRCNTX(txq->cntxt_id));
2145 }
2146 }
2147
2148 if (sleeping & F_RSPD_TXQ1_GTS) {
2149 struct sge_txq *txq = &qs->txq[TXQ_OFLD];
2150
2151 if (txq->cleaned + txq->in_use != txq->processed &&
2152 !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
2153 set_bit(TXQ_RUNNING, &txq->flags);
2154 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
2155 V_EGRCNTX(txq->cntxt_id));
2156 }
2157 }
2158}
2159
2160/**
2161 * is_new_response - check if a response is newly written
2162 * @r: the response descriptor
2163 * @q: the response queue
2164 *
2165 * Returns true if a response descriptor contains a yet unprocessed
2166 * response.
2167 */
2168static inline int is_new_response(const struct rsp_desc *r,
2169 const struct sge_rspq *q)
2170{
2171 return (r->intr_gen & F_RSPD_GEN2) == q->gen;
2172}
2173
7385ecf3
DLR
2174static inline void clear_rspq_bufstate(struct sge_rspq * const q)
2175{
2176 q->pg_skb = NULL;
2177 q->rx_recycle_buf = 0;
2178}
2179
4d22de3e
DLR
2180#define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS)
2181#define RSPD_CTRL_MASK (RSPD_GTS_MASK | \
2182 V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \
2183 V_RSPD_TXQ1_CR(M_RSPD_TXQ1_CR) | \
2184 V_RSPD_TXQ2_CR(M_RSPD_TXQ2_CR))
2185
2186/* How long to delay the next interrupt in case of memory shortage, in 0.1us. */
2187#define NOMEM_INTR_DELAY 2500
2188
2189/**
2190 * process_responses - process responses from an SGE response queue
2191 * @adap: the adapter
2192 * @qs: the queue set to which the response queue belongs
2193 * @budget: how many responses can be processed in this round
2194 *
2195 * Process responses from an SGE response queue up to the supplied budget.
2196 * Responses include received packets as well as credits and other events
2197 * for the queues that belong to the response queue's queue set.
2198 * A negative budget is effectively unlimited.
2199 *
2200 * Additionally choose the interrupt holdoff time for the next interrupt
2201 * on this queue. If the system is under memory shortage use a fairly
2202 * long delay to help recovery.
2203 */
2204static int process_responses(struct adapter *adap, struct sge_qset *qs,
2205 int budget)
2206{
2207 struct sge_rspq *q = &qs->rspq;
2208 struct rsp_desc *r = &q->desc[q->cidx];
2209 int budget_left = budget;
6195c71d 2210 unsigned int sleeping = 0;
4d22de3e
DLR
2211 struct sk_buff *offload_skbs[RX_BUNDLE_SIZE];
2212 int ngathered = 0;
2213
2214 q->next_holdoff = q->holdoff_tmr;
2215
2216 while (likely(budget_left && is_new_response(r, q))) {
b47385bd 2217 int packet_complete, eth, ethpad = 2, lro = qs->lro_enabled;
4d22de3e
DLR
2218 struct sk_buff *skb = NULL;
2219 u32 len, flags = ntohl(r->flags);
7385ecf3
DLR
2220 __be32 rss_hi = *(const __be32 *)r,
2221 rss_lo = r->rss_hdr.rss_hash_val;
4d22de3e
DLR
2222
2223 eth = r->rss_hdr.opcode == CPL_RX_PKT;
2224
2225 if (unlikely(flags & F_RSPD_ASYNC_NOTIF)) {
2226 skb = alloc_skb(AN_PKT_SIZE, GFP_ATOMIC);
2227 if (!skb)
2228 goto no_mem;
2229
2230 memcpy(__skb_put(skb, AN_PKT_SIZE), r, AN_PKT_SIZE);
2231 skb->data[0] = CPL_ASYNC_NOTIF;
2232 rss_hi = htonl(CPL_ASYNC_NOTIF << 24);
2233 q->async_notif++;
2234 } else if (flags & F_RSPD_IMM_DATA_VALID) {
2235 skb = get_imm_packet(r);
2236 if (unlikely(!skb)) {
cf992af5 2237no_mem:
4d22de3e
DLR
2238 q->next_holdoff = NOMEM_INTR_DELAY;
2239 q->nomem++;
2240 /* consume one credit since we tried */
2241 budget_left--;
2242 break;
2243 }
2244 q->imm_data++;
e0994eb1 2245 ethpad = 0;
4d22de3e 2246 } else if ((len = ntohl(r->len_cq)) != 0) {
cf992af5 2247 struct sge_fl *fl;
e0994eb1 2248
b47385bd
DLR
2249 if (eth)
2250 lro = qs->lro_enabled && is_eth_tcp(rss_hi);
2251
cf992af5
DLR
2252 fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0];
2253 if (fl->use_pages) {
2254 void *addr = fl->sdesc[fl->cidx].pg_chunk.va;
e0994eb1 2255
cf992af5
DLR
2256 prefetch(addr);
2257#if L1_CACHE_BYTES < 128
2258 prefetch(addr + L1_CACHE_BYTES);
2259#endif
e0994eb1 2260 __refill_fl(adap, fl);
b47385bd
DLR
2261 if (lro > 0) {
2262 lro_add_page(adap, qs, fl,
2263 G_RSPD_LEN(len),
2264 flags & F_RSPD_EOP);
2265 goto next_fl;
2266 }
e0994eb1 2267
7385ecf3
DLR
2268 skb = get_packet_pg(adap, fl, q,
2269 G_RSPD_LEN(len),
2270 eth ?
2271 SGE_RX_DROP_THRES : 0);
2272 q->pg_skb = skb;
cf992af5 2273 } else
e0994eb1
DLR
2274 skb = get_packet(adap, fl, G_RSPD_LEN(len),
2275 eth ? SGE_RX_DROP_THRES : 0);
cf992af5
DLR
2276 if (unlikely(!skb)) {
2277 if (!eth)
2278 goto no_mem;
2279 q->rx_drops++;
2280 } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT))
2281 __skb_pull(skb, 2);
b47385bd 2282next_fl:
4d22de3e
DLR
2283 if (++fl->cidx == fl->size)
2284 fl->cidx = 0;
2285 } else
2286 q->pure_rsps++;
2287
2288 if (flags & RSPD_CTRL_MASK) {
2289 sleeping |= flags & RSPD_GTS_MASK;
6195c71d 2290 handle_rsp_cntrl_info(qs, flags);
4d22de3e
DLR
2291 }
2292
2293 r++;
2294 if (unlikely(++q->cidx == q->size)) {
2295 q->cidx = 0;
2296 q->gen ^= 1;
2297 r = q->desc;
2298 }
2299 prefetch(r);
2300
2301 if (++q->credits >= (q->size / 4)) {
2302 refill_rspq(adap, q, q->credits);
2303 q->credits = 0;
2304 }
2305
7385ecf3
DLR
2306 packet_complete = flags &
2307 (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID |
2308 F_RSPD_ASYNC_NOTIF);
2309
2310 if (skb != NULL && packet_complete) {
4d22de3e 2311 if (eth)
b47385bd 2312 rx_eth(adap, q, skb, ethpad, lro);
4d22de3e 2313 else {
afefce66 2314 q->offload_pkts++;
cf992af5
DLR
2315 /* Preserve the RSS info in csum & priority */
2316 skb->csum = rss_hi;
2317 skb->priority = rss_lo;
2318 ngathered = rx_offload(&adap->tdev, q, skb,
2319 offload_skbs,
e0994eb1 2320 ngathered);
4d22de3e 2321 }
7385ecf3
DLR
2322
2323 if (flags & F_RSPD_EOP)
b47385bd 2324 clear_rspq_bufstate(q);
4d22de3e 2325 }
4d22de3e
DLR
2326 --budget_left;
2327 }
2328
4d22de3e 2329 deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered);
b47385bd
DLR
2330 lro_flush_all(&qs->lro_mgr);
2331 qs->port_stats[SGE_PSTAT_LRO_AGGR] = qs->lro_mgr.stats.aggregated;
2332 qs->port_stats[SGE_PSTAT_LRO_FLUSHED] = qs->lro_mgr.stats.flushed;
2333 qs->port_stats[SGE_PSTAT_LRO_NO_DESC] = qs->lro_mgr.stats.no_desc;
2334
4d22de3e
DLR
2335 if (sleeping)
2336 check_ring_db(adap, qs, sleeping);
2337
2338 smp_mb(); /* commit Tx queue .processed updates */
2339 if (unlikely(qs->txq_stopped != 0))
2340 restart_tx(qs);
2341
2342 budget -= budget_left;
2343 return budget;
2344}
2345
2346static inline int is_pure_response(const struct rsp_desc *r)
2347{
2348 u32 n = ntohl(r->flags) & (F_RSPD_ASYNC_NOTIF | F_RSPD_IMM_DATA_VALID);
2349
2350 return (n | r->len_cq) == 0;
2351}
2352
2353/**
2354 * napi_rx_handler - the NAPI handler for Rx processing
bea3348e 2355 * @napi: the napi instance
4d22de3e
DLR
2356 * @budget: how many packets we can process in this round
2357 *
2358 * Handler for new data events when using NAPI.
2359 */
bea3348e 2360static int napi_rx_handler(struct napi_struct *napi, int budget)
4d22de3e 2361{
bea3348e
SH
2362 struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
2363 struct adapter *adap = qs->adap;
2364 int work_done = process_responses(adap, qs, budget);
4d22de3e 2365
bea3348e
SH
2366 if (likely(work_done < budget)) {
2367 napi_complete(napi);
4d22de3e 2368
bea3348e
SH
2369 /*
2370 * Because we don't atomically flush the following
2371 * write it is possible that in very rare cases it can
2372 * reach the device in a way that races with a new
2373 * response being written plus an error interrupt
2374 * causing the NAPI interrupt handler below to return
2375 * unhandled status to the OS. To protect against
2376 * this would require flushing the write and doing
2377 * both the write and the flush with interrupts off.
2378 * Way too expensive and unjustifiable given the
2379 * rarity of the race.
2380 *
2381 * The race cannot happen at all with MSI-X.
2382 */
2383 t3_write_reg(adap, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) |
2384 V_NEWTIMER(qs->rspq.next_holdoff) |
2385 V_NEWINDEX(qs->rspq.cidx));
2386 }
2387 return work_done;
4d22de3e
DLR
2388}
2389
2390/*
2391 * Returns true if the device is already scheduled for polling.
2392 */
bea3348e 2393static inline int napi_is_scheduled(struct napi_struct *napi)
4d22de3e 2394{
bea3348e 2395 return test_bit(NAPI_STATE_SCHED, &napi->state);
4d22de3e
DLR
2396}
2397
2398/**
2399 * process_pure_responses - process pure responses from a response queue
2400 * @adap: the adapter
2401 * @qs: the queue set owning the response queue
2402 * @r: the first pure response to process
2403 *
2404 * A simpler version of process_responses() that handles only pure (i.e.,
2405 * non data-carrying) responses. Such respones are too light-weight to
2406 * justify calling a softirq under NAPI, so we handle them specially in
2407 * the interrupt handler. The function is called with a pointer to a
2408 * response, which the caller must ensure is a valid pure response.
2409 *
2410 * Returns 1 if it encounters a valid data-carrying response, 0 otherwise.
2411 */
2412static int process_pure_responses(struct adapter *adap, struct sge_qset *qs,
2413 struct rsp_desc *r)
2414{
2415 struct sge_rspq *q = &qs->rspq;
6195c71d 2416 unsigned int sleeping = 0;
4d22de3e
DLR
2417
2418 do {
2419 u32 flags = ntohl(r->flags);
2420
2421 r++;
2422 if (unlikely(++q->cidx == q->size)) {
2423 q->cidx = 0;
2424 q->gen ^= 1;
2425 r = q->desc;
2426 }
2427 prefetch(r);
2428
2429 if (flags & RSPD_CTRL_MASK) {
2430 sleeping |= flags & RSPD_GTS_MASK;
6195c71d 2431 handle_rsp_cntrl_info(qs, flags);
4d22de3e
DLR
2432 }
2433
2434 q->pure_rsps++;
2435 if (++q->credits >= (q->size / 4)) {
2436 refill_rspq(adap, q, q->credits);
2437 q->credits = 0;
2438 }
2439 } while (is_new_response(r, q) && is_pure_response(r));
2440
4d22de3e
DLR
2441 if (sleeping)
2442 check_ring_db(adap, qs, sleeping);
2443
2444 smp_mb(); /* commit Tx queue .processed updates */
2445 if (unlikely(qs->txq_stopped != 0))
2446 restart_tx(qs);
2447
2448 return is_new_response(r, q);
2449}
2450
2451/**
2452 * handle_responses - decide what to do with new responses in NAPI mode
2453 * @adap: the adapter
2454 * @q: the response queue
2455 *
2456 * This is used by the NAPI interrupt handlers to decide what to do with
2457 * new SGE responses. If there are no new responses it returns -1. If
2458 * there are new responses and they are pure (i.e., non-data carrying)
2459 * it handles them straight in hard interrupt context as they are very
2460 * cheap and don't deliver any packets. Finally, if there are any data
2461 * signaling responses it schedules the NAPI handler. Returns 1 if it
2462 * schedules NAPI, 0 if all new responses were pure.
2463 *
2464 * The caller must ascertain NAPI is not already running.
2465 */
2466static inline int handle_responses(struct adapter *adap, struct sge_rspq *q)
2467{
2468 struct sge_qset *qs = rspq_to_qset(q);
2469 struct rsp_desc *r = &q->desc[q->cidx];
2470
2471 if (!is_new_response(r, q))
2472 return -1;
2473 if (is_pure_response(r) && process_pure_responses(adap, qs, r) == 0) {
2474 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2475 V_NEWTIMER(q->holdoff_tmr) | V_NEWINDEX(q->cidx));
2476 return 0;
2477 }
bea3348e 2478 napi_schedule(&qs->napi);
4d22de3e
DLR
2479 return 1;
2480}
2481
2482/*
2483 * The MSI-X interrupt handler for an SGE response queue for the non-NAPI case
2484 * (i.e., response queue serviced in hard interrupt).
2485 */
2486irqreturn_t t3_sge_intr_msix(int irq, void *cookie)
2487{
2488 struct sge_qset *qs = cookie;
bea3348e 2489 struct adapter *adap = qs->adap;
4d22de3e
DLR
2490 struct sge_rspq *q = &qs->rspq;
2491
2492 spin_lock(&q->lock);
2493 if (process_responses(adap, qs, -1) == 0)
2494 q->unhandled_irqs++;
2495 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2496 V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
2497 spin_unlock(&q->lock);
2498 return IRQ_HANDLED;
2499}
2500
2501/*
2502 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
2503 * (i.e., response queue serviced by NAPI polling).
2504 */
9265fabf 2505static irqreturn_t t3_sge_intr_msix_napi(int irq, void *cookie)
4d22de3e
DLR
2506{
2507 struct sge_qset *qs = cookie;
4d22de3e
DLR
2508 struct sge_rspq *q = &qs->rspq;
2509
2510 spin_lock(&q->lock);
4d22de3e 2511
bea3348e 2512 if (handle_responses(qs->adap, q) < 0)
4d22de3e
DLR
2513 q->unhandled_irqs++;
2514 spin_unlock(&q->lock);
2515 return IRQ_HANDLED;
2516}
2517
2518/*
2519 * The non-NAPI MSI interrupt handler. This needs to handle data events from
2520 * SGE response queues as well as error and other async events as they all use
2521 * the same MSI vector. We use one SGE response queue per port in this mode
2522 * and protect all response queues with queue 0's lock.
2523 */
2524static irqreturn_t t3_intr_msi(int irq, void *cookie)
2525{
2526 int new_packets = 0;
2527 struct adapter *adap = cookie;
2528 struct sge_rspq *q = &adap->sge.qs[0].rspq;
2529
2530 spin_lock(&q->lock);
2531
2532 if (process_responses(adap, &adap->sge.qs[0], -1)) {
2533 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2534 V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
2535 new_packets = 1;
2536 }
2537
2538 if (adap->params.nports == 2 &&
2539 process_responses(adap, &adap->sge.qs[1], -1)) {
2540 struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
2541
2542 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q1->cntxt_id) |
2543 V_NEWTIMER(q1->next_holdoff) |
2544 V_NEWINDEX(q1->cidx));
2545 new_packets = 1;
2546 }
2547
2548 if (!new_packets && t3_slow_intr_handler(adap) == 0)
2549 q->unhandled_irqs++;
2550
2551 spin_unlock(&q->lock);
2552 return IRQ_HANDLED;
2553}
2554
bea3348e 2555static int rspq_check_napi(struct sge_qset *qs)
4d22de3e 2556{
bea3348e
SH
2557 struct sge_rspq *q = &qs->rspq;
2558
2559 if (!napi_is_scheduled(&qs->napi) &&
2560 is_new_response(&q->desc[q->cidx], q)) {
2561 napi_schedule(&qs->napi);
4d22de3e
DLR
2562 return 1;
2563 }
2564 return 0;
2565}
2566
2567/*
2568 * The MSI interrupt handler for the NAPI case (i.e., response queues serviced
2569 * by NAPI polling). Handles data events from SGE response queues as well as
2570 * error and other async events as they all use the same MSI vector. We use
2571 * one SGE response queue per port in this mode and protect all response
2572 * queues with queue 0's lock.
2573 */
9265fabf 2574static irqreturn_t t3_intr_msi_napi(int irq, void *cookie)
4d22de3e
DLR
2575{
2576 int new_packets;
2577 struct adapter *adap = cookie;
2578 struct sge_rspq *q = &adap->sge.qs[0].rspq;
2579
2580 spin_lock(&q->lock);
2581
bea3348e 2582 new_packets = rspq_check_napi(&adap->sge.qs[0]);
4d22de3e 2583 if (adap->params.nports == 2)
bea3348e 2584 new_packets += rspq_check_napi(&adap->sge.qs[1]);
4d22de3e
DLR
2585 if (!new_packets && t3_slow_intr_handler(adap) == 0)
2586 q->unhandled_irqs++;
2587
2588 spin_unlock(&q->lock);
2589 return IRQ_HANDLED;
2590}
2591
2592/*
2593 * A helper function that processes responses and issues GTS.
2594 */
2595static inline int process_responses_gts(struct adapter *adap,
2596 struct sge_rspq *rq)
2597{
2598 int work;
2599
2600 work = process_responses(adap, rspq_to_qset(rq), -1);
2601 t3_write_reg(adap, A_SG_GTS, V_RSPQ(rq->cntxt_id) |
2602 V_NEWTIMER(rq->next_holdoff) | V_NEWINDEX(rq->cidx));
2603 return work;
2604}
2605
2606/*
2607 * The legacy INTx interrupt handler. This needs to handle data events from
2608 * SGE response queues as well as error and other async events as they all use
2609 * the same interrupt pin. We use one SGE response queue per port in this mode
2610 * and protect all response queues with queue 0's lock.
2611 */
2612static irqreturn_t t3_intr(int irq, void *cookie)
2613{
2614 int work_done, w0, w1;
2615 struct adapter *adap = cookie;
2616 struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
2617 struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
2618
2619 spin_lock(&q0->lock);
2620
2621 w0 = is_new_response(&q0->desc[q0->cidx], q0);
2622 w1 = adap->params.nports == 2 &&
2623 is_new_response(&q1->desc[q1->cidx], q1);
2624
2625 if (likely(w0 | w1)) {
2626 t3_write_reg(adap, A_PL_CLI, 0);
2627 t3_read_reg(adap, A_PL_CLI); /* flush */
2628
2629 if (likely(w0))
2630 process_responses_gts(adap, q0);
2631
2632 if (w1)
2633 process_responses_gts(adap, q1);
2634
2635 work_done = w0 | w1;
2636 } else
2637 work_done = t3_slow_intr_handler(adap);
2638
2639 spin_unlock(&q0->lock);
2640 return IRQ_RETVAL(work_done != 0);
2641}
2642
2643/*
2644 * Interrupt handler for legacy INTx interrupts for T3B-based cards.
2645 * Handles data events from SGE response queues as well as error and other
2646 * async events as they all use the same interrupt pin. We use one SGE
2647 * response queue per port in this mode and protect all response queues with
2648 * queue 0's lock.
2649 */
2650static irqreturn_t t3b_intr(int irq, void *cookie)
2651{
2652 u32 map;
2653 struct adapter *adap = cookie;
2654 struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
2655
2656 t3_write_reg(adap, A_PL_CLI, 0);
2657 map = t3_read_reg(adap, A_SG_DATA_INTR);
2658
2659 if (unlikely(!map)) /* shared interrupt, most likely */
2660 return IRQ_NONE;
2661
2662 spin_lock(&q0->lock);
2663
2664 if (unlikely(map & F_ERRINTR))
2665 t3_slow_intr_handler(adap);
2666
2667 if (likely(map & 1))
2668 process_responses_gts(adap, q0);
2669
2670 if (map & 2)
2671 process_responses_gts(adap, &adap->sge.qs[1].rspq);
2672
2673 spin_unlock(&q0->lock);
2674 return IRQ_HANDLED;
2675}
2676
2677/*
2678 * NAPI interrupt handler for legacy INTx interrupts for T3B-based cards.
2679 * Handles data events from SGE response queues as well as error and other
2680 * async events as they all use the same interrupt pin. We use one SGE
2681 * response queue per port in this mode and protect all response queues with
2682 * queue 0's lock.
2683 */
2684static irqreturn_t t3b_intr_napi(int irq, void *cookie)
2685{
2686 u32 map;
4d22de3e 2687 struct adapter *adap = cookie;
bea3348e
SH
2688 struct sge_qset *qs0 = &adap->sge.qs[0];
2689 struct sge_rspq *q0 = &qs0->rspq;
4d22de3e
DLR
2690
2691 t3_write_reg(adap, A_PL_CLI, 0);
2692 map = t3_read_reg(adap, A_SG_DATA_INTR);
2693
2694 if (unlikely(!map)) /* shared interrupt, most likely */
2695 return IRQ_NONE;
2696
2697 spin_lock(&q0->lock);
2698
2699 if (unlikely(map & F_ERRINTR))
2700 t3_slow_intr_handler(adap);
2701
bea3348e
SH
2702 if (likely(map & 1))
2703 napi_schedule(&qs0->napi);
4d22de3e 2704
bea3348e
SH
2705 if (map & 2)
2706 napi_schedule(&adap->sge.qs[1].napi);
4d22de3e
DLR
2707
2708 spin_unlock(&q0->lock);
2709 return IRQ_HANDLED;
2710}
2711
2712/**
2713 * t3_intr_handler - select the top-level interrupt handler
2714 * @adap: the adapter
2715 * @polling: whether using NAPI to service response queues
2716 *
2717 * Selects the top-level interrupt handler based on the type of interrupts
2718 * (MSI-X, MSI, or legacy) and whether NAPI will be used to service the
2719 * response queues.
2720 */
7c239975 2721irq_handler_t t3_intr_handler(struct adapter *adap, int polling)
4d22de3e
DLR
2722{
2723 if (adap->flags & USING_MSIX)
2724 return polling ? t3_sge_intr_msix_napi : t3_sge_intr_msix;
2725 if (adap->flags & USING_MSI)
2726 return polling ? t3_intr_msi_napi : t3_intr_msi;
2727 if (adap->params.rev > 0)
2728 return polling ? t3b_intr_napi : t3b_intr;
2729 return t3_intr;
2730}
2731
b881955b
DLR
2732#define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
2733 F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
2734 V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
2735 F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
2736 F_HIRCQPARITYERROR)
2737#define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR)
2738#define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \
2739 F_RSPQDISABLED)
2740
4d22de3e
DLR
2741/**
2742 * t3_sge_err_intr_handler - SGE async event interrupt handler
2743 * @adapter: the adapter
2744 *
2745 * Interrupt handler for SGE asynchronous (non-data) events.
2746 */
2747void t3_sge_err_intr_handler(struct adapter *adapter)
2748{
2749 unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2750
b881955b
DLR
2751 if (status & SGE_PARERR)
2752 CH_ALERT(adapter, "SGE parity error (0x%x)\n",
2753 status & SGE_PARERR);
2754 if (status & SGE_FRAMINGERR)
2755 CH_ALERT(adapter, "SGE framing error (0x%x)\n",
2756 status & SGE_FRAMINGERR);
2757
4d22de3e
DLR
2758 if (status & F_RSPQCREDITOVERFOW)
2759 CH_ALERT(adapter, "SGE response queue credit overflow\n");
2760
2761 if (status & F_RSPQDISABLED) {
2762 v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
2763
2764 CH_ALERT(adapter,
2765 "packet delivered to disabled response queue "
2766 "(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff);
2767 }
2768
6e3f03b7
DLR
2769 if (status & (F_HIPIODRBDROPERR | F_LOPIODRBDROPERR))
2770 CH_ALERT(adapter, "SGE dropped %s priority doorbell\n",
2771 status & F_HIPIODRBDROPERR ? "high" : "lo");
2772
4d22de3e 2773 t3_write_reg(adapter, A_SG_INT_CAUSE, status);
b881955b 2774 if (status & SGE_FATALERR)
4d22de3e
DLR
2775 t3_fatal_err(adapter);
2776}
2777
2778/**
2779 * sge_timer_cb - perform periodic maintenance of an SGE qset
2780 * @data: the SGE queue set to maintain
2781 *
2782 * Runs periodically from a timer to perform maintenance of an SGE queue
2783 * set. It performs two tasks:
2784 *
2785 * a) Cleans up any completed Tx descriptors that may still be pending.
2786 * Normal descriptor cleanup happens when new packets are added to a Tx
2787 * queue so this timer is relatively infrequent and does any cleanup only
2788 * if the Tx queue has not seen any new packets in a while. We make a
2789 * best effort attempt to reclaim descriptors, in that we don't wait
2790 * around if we cannot get a queue's lock (which most likely is because
2791 * someone else is queueing new packets and so will also handle the clean
2792 * up). Since control queues use immediate data exclusively we don't
2793 * bother cleaning them up here.
2794 *
2795 * b) Replenishes Rx queues that have run out due to memory shortage.
2796 * Normally new Rx buffers are added when existing ones are consumed but
2797 * when out of memory a queue can become empty. We try to add only a few
2798 * buffers here, the queue will be replenished fully as these new buffers
2799 * are used up if memory shortage has subsided.
2800 */
2801static void sge_timer_cb(unsigned long data)
2802{
2803 spinlock_t *lock;
2804 struct sge_qset *qs = (struct sge_qset *)data;
bea3348e 2805 struct adapter *adap = qs->adap;
4d22de3e
DLR
2806
2807 if (spin_trylock(&qs->txq[TXQ_ETH].lock)) {
2808 reclaim_completed_tx(adap, &qs->txq[TXQ_ETH]);
2809 spin_unlock(&qs->txq[TXQ_ETH].lock);
2810 }
2811 if (spin_trylock(&qs->txq[TXQ_OFLD].lock)) {
2812 reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD]);
2813 spin_unlock(&qs->txq[TXQ_OFLD].lock);
2814 }
2815 lock = (adap->flags & USING_MSIX) ? &qs->rspq.lock :
bea3348e 2816 &adap->sge.qs[0].rspq.lock;
4d22de3e 2817 if (spin_trylock_irq(lock)) {
bea3348e 2818 if (!napi_is_scheduled(&qs->napi)) {
bae73f44
DLR
2819 u32 status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);
2820
4d22de3e
DLR
2821 if (qs->fl[0].credits < qs->fl[0].size)
2822 __refill_fl(adap, &qs->fl[0]);
2823 if (qs->fl[1].credits < qs->fl[1].size)
2824 __refill_fl(adap, &qs->fl[1]);
bae73f44
DLR
2825
2826 if (status & (1 << qs->rspq.cntxt_id)) {
2827 qs->rspq.starved++;
2828 if (qs->rspq.credits) {
2829 refill_rspq(adap, &qs->rspq, 1);
2830 qs->rspq.credits--;
2831 qs->rspq.restarted++;
e0994eb1 2832 t3_write_reg(adap, A_SG_RSPQ_FL_STATUS,
bae73f44
DLR
2833 1 << qs->rspq.cntxt_id);
2834 }
2835 }
4d22de3e
DLR
2836 }
2837 spin_unlock_irq(lock);
2838 }
2839 mod_timer(&qs->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
2840}
2841
2842/**
2843 * t3_update_qset_coalesce - update coalescing settings for a queue set
2844 * @qs: the SGE queue set
2845 * @p: new queue set parameters
2846 *
2847 * Update the coalescing settings for an SGE queue set. Nothing is done
2848 * if the queue set is not initialized yet.
2849 */
2850void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p)
2851{
4d22de3e
DLR
2852 qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U);/* can't be 0 */
2853 qs->rspq.polling = p->polling;
bea3348e 2854 qs->napi.poll = p->polling ? napi_rx_handler : ofld_poll;
4d22de3e
DLR
2855}
2856
2857/**
2858 * t3_sge_alloc_qset - initialize an SGE queue set
2859 * @adapter: the adapter
2860 * @id: the queue set id
2861 * @nports: how many Ethernet ports will be using this queue set
2862 * @irq_vec_idx: the IRQ vector index for response queue interrupts
2863 * @p: configuration parameters for this queue set
2864 * @ntxq: number of Tx queues for the queue set
2865 * @netdev: net device associated with this queue set
2866 *
2867 * Allocate resources and initialize an SGE queue set. A queue set
2868 * comprises a response queue, two Rx free-buffer queues, and up to 3
2869 * Tx queues. The Tx queues are assigned roles in the order Ethernet
2870 * queue, offload queue, and control queue.
2871 */
2872int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2873 int irq_vec_idx, const struct qset_params *p,
bea3348e 2874 int ntxq, struct net_device *dev)
4d22de3e 2875{
b1fb1f28 2876 int i, avail, ret = -ENOMEM;
4d22de3e 2877 struct sge_qset *q = &adapter->sge.qs[id];
b47385bd 2878 struct net_lro_mgr *lro_mgr = &q->lro_mgr;
4d22de3e
DLR
2879
2880 init_qset_cntxt(q, id);
2881 init_timer(&q->tx_reclaim_timer);
2882 q->tx_reclaim_timer.data = (unsigned long)q;
2883 q->tx_reclaim_timer.function = sge_timer_cb;
2884
2885 q->fl[0].desc = alloc_ring(adapter->pdev, p->fl_size,
2886 sizeof(struct rx_desc),
2887 sizeof(struct rx_sw_desc),
2888 &q->fl[0].phys_addr, &q->fl[0].sdesc);
2889 if (!q->fl[0].desc)
2890 goto err;
2891
2892 q->fl[1].desc = alloc_ring(adapter->pdev, p->jumbo_size,
2893 sizeof(struct rx_desc),
2894 sizeof(struct rx_sw_desc),
2895 &q->fl[1].phys_addr, &q->fl[1].sdesc);
2896 if (!q->fl[1].desc)
2897 goto err;
2898
2899 q->rspq.desc = alloc_ring(adapter->pdev, p->rspq_size,
2900 sizeof(struct rsp_desc), 0,
2901 &q->rspq.phys_addr, NULL);
2902 if (!q->rspq.desc)
2903 goto err;
2904
2905 for (i = 0; i < ntxq; ++i) {
2906 /*
2907 * The control queue always uses immediate data so does not
2908 * need to keep track of any sk_buffs.
2909 */
2910 size_t sz = i == TXQ_CTRL ? 0 : sizeof(struct tx_sw_desc);
2911
2912 q->txq[i].desc = alloc_ring(adapter->pdev, p->txq_size[i],
2913 sizeof(struct tx_desc), sz,
2914 &q->txq[i].phys_addr,
2915 &q->txq[i].sdesc);
2916 if (!q->txq[i].desc)
2917 goto err;
2918
2919 q->txq[i].gen = 1;
2920 q->txq[i].size = p->txq_size[i];
2921 spin_lock_init(&q->txq[i].lock);
2922 skb_queue_head_init(&q->txq[i].sendq);
2923 }
2924
2925 tasklet_init(&q->txq[TXQ_OFLD].qresume_tsk, restart_offloadq,
2926 (unsigned long)q);
2927 tasklet_init(&q->txq[TXQ_CTRL].qresume_tsk, restart_ctrlq,
2928 (unsigned long)q);
2929
2930 q->fl[0].gen = q->fl[1].gen = 1;
2931 q->fl[0].size = p->fl_size;
2932 q->fl[1].size = p->jumbo_size;
2933
2934 q->rspq.gen = 1;
2935 q->rspq.size = p->rspq_size;
2936 spin_lock_init(&q->rspq.lock);
2937
2938 q->txq[TXQ_ETH].stop_thres = nports *
2939 flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3);
2940
cf992af5
DLR
2941#if FL0_PG_CHUNK_SIZE > 0
2942 q->fl[0].buf_size = FL0_PG_CHUNK_SIZE;
e0994eb1 2943#else
cf992af5 2944 q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data);
e0994eb1 2945#endif
7385ecf3
DLR
2946#if FL1_PG_CHUNK_SIZE > 0
2947 q->fl[1].buf_size = FL1_PG_CHUNK_SIZE;
2948#else
cf992af5
DLR
2949 q->fl[1].buf_size = is_offload(adapter) ?
2950 (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2951 MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt);
7385ecf3
DLR
2952#endif
2953
2954 q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0;
2955 q->fl[1].use_pages = FL1_PG_CHUNK_SIZE > 0;
2956 q->fl[0].order = FL0_PG_ORDER;
2957 q->fl[1].order = FL1_PG_ORDER;
4d22de3e 2958
b47385bd
DLR
2959 q->lro_frag_tbl = kcalloc(MAX_FRAME_SIZE / FL1_PG_CHUNK_SIZE + 1,
2960 sizeof(struct skb_frag_struct),
2961 GFP_KERNEL);
2962 q->lro_nfrags = q->lro_frag_len = 0;
b1186dee 2963 spin_lock_irq(&adapter->sge.reg_lock);
4d22de3e
DLR
2964
2965 /* FL threshold comparison uses < */
2966 ret = t3_sge_init_rspcntxt(adapter, q->rspq.cntxt_id, irq_vec_idx,
2967 q->rspq.phys_addr, q->rspq.size,
2968 q->fl[0].buf_size, 1, 0);
2969 if (ret)
2970 goto err_unlock;
2971
2972 for (i = 0; i < SGE_RXQ_PER_SET; ++i) {
2973 ret = t3_sge_init_flcntxt(adapter, q->fl[i].cntxt_id, 0,
2974 q->fl[i].phys_addr, q->fl[i].size,
2975 q->fl[i].buf_size, p->cong_thres, 1,
2976 0);
2977 if (ret)
2978 goto err_unlock;
2979 }
2980
2981 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_ETH].cntxt_id, USE_GTS,
2982 SGE_CNTXT_ETH, id, q->txq[TXQ_ETH].phys_addr,
2983 q->txq[TXQ_ETH].size, q->txq[TXQ_ETH].token,
2984 1, 0);
2985 if (ret)
2986 goto err_unlock;
2987
2988 if (ntxq > 1) {
2989 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_OFLD].cntxt_id,
2990 USE_GTS, SGE_CNTXT_OFLD, id,
2991 q->txq[TXQ_OFLD].phys_addr,
2992 q->txq[TXQ_OFLD].size, 0, 1, 0);
2993 if (ret)
2994 goto err_unlock;
2995 }
2996
2997 if (ntxq > 2) {
2998 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_CTRL].cntxt_id, 0,
2999 SGE_CNTXT_CTRL, id,
3000 q->txq[TXQ_CTRL].phys_addr,
3001 q->txq[TXQ_CTRL].size,
3002 q->txq[TXQ_CTRL].token, 1, 0);
3003 if (ret)
3004 goto err_unlock;
3005 }
3006
b1186dee 3007 spin_unlock_irq(&adapter->sge.reg_lock);
4d22de3e 3008
bea3348e
SH
3009 q->adap = adapter;
3010 q->netdev = dev;
3011 t3_update_qset_coalesce(q, p);
b47385bd
DLR
3012
3013 init_lro_mgr(q, lro_mgr);
3014
7385ecf3
DLR
3015 avail = refill_fl(adapter, &q->fl[0], q->fl[0].size,
3016 GFP_KERNEL | __GFP_COMP);
b1fb1f28
DLR
3017 if (!avail) {
3018 CH_ALERT(adapter, "free list queue 0 initialization failed\n");
3019 goto err;
3020 }
3021 if (avail < q->fl[0].size)
3022 CH_WARN(adapter, "free list queue 0 enabled with %d credits\n",
3023 avail);
3024
7385ecf3
DLR
3025 avail = refill_fl(adapter, &q->fl[1], q->fl[1].size,
3026 GFP_KERNEL | __GFP_COMP);
b1fb1f28
DLR
3027 if (avail < q->fl[1].size)
3028 CH_WARN(adapter, "free list queue 1 enabled with %d credits\n",
3029 avail);
4d22de3e
DLR
3030 refill_rspq(adapter, &q->rspq, q->rspq.size - 1);
3031
3032 t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) |
3033 V_NEWTIMER(q->rspq.holdoff_tmr));
3034
3035 mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
3036 return 0;
3037
b1fb1f28 3038err_unlock:
b1186dee 3039 spin_unlock_irq(&adapter->sge.reg_lock);
b1fb1f28 3040err:
4d22de3e
DLR
3041 t3_free_qset(adapter, q);
3042 return ret;
3043}
3044
3045/**
3046 * t3_free_sge_resources - free SGE resources
3047 * @adap: the adapter
3048 *
3049 * Frees resources used by the SGE queue sets.
3050 */
3051void t3_free_sge_resources(struct adapter *adap)
3052{
3053 int i;
3054
3055 for (i = 0; i < SGE_QSETS; ++i)
3056 t3_free_qset(adap, &adap->sge.qs[i]);
3057}
3058
3059/**
3060 * t3_sge_start - enable SGE
3061 * @adap: the adapter
3062 *
3063 * Enables the SGE for DMAs. This is the last step in starting packet
3064 * transfers.
3065 */
3066void t3_sge_start(struct adapter *adap)
3067{
3068 t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE);
3069}
3070
3071/**
3072 * t3_sge_stop - disable SGE operation
3073 * @adap: the adapter
3074 *
3075 * Disables the DMA engine. This can be called in emeregencies (e.g.,
3076 * from error interrupts) or from normal process context. In the latter
3077 * case it also disables any pending queue restart tasklets. Note that
3078 * if it is called in interrupt context it cannot disable the restart
3079 * tasklets as it cannot wait, however the tasklets will have no effect
3080 * since the doorbells are disabled and the driver will call this again
3081 * later from process context, at which time the tasklets will be stopped
3082 * if they are still running.
3083 */
3084void t3_sge_stop(struct adapter *adap)
3085{
3086 t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, 0);
3087 if (!in_interrupt()) {
3088 int i;
3089
3090 for (i = 0; i < SGE_QSETS; ++i) {
3091 struct sge_qset *qs = &adap->sge.qs[i];
3092
3093 tasklet_kill(&qs->txq[TXQ_OFLD].qresume_tsk);
3094 tasklet_kill(&qs->txq[TXQ_CTRL].qresume_tsk);
3095 }
3096 }
3097}
3098
3099/**
3100 * t3_sge_init - initialize SGE
3101 * @adap: the adapter
3102 * @p: the SGE parameters
3103 *
3104 * Performs SGE initialization needed every time after a chip reset.
3105 * We do not initialize any of the queue sets here, instead the driver
3106 * top-level must request those individually. We also do not enable DMA
3107 * here, that should be done after the queues have been set up.
3108 */
3109void t3_sge_init(struct adapter *adap, struct sge_params *p)
3110{
3111 unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12);
3112
3113 ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
b881955b 3114 F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |
4d22de3e
DLR
3115 V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |
3116 V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;
3117#if SGE_NUM_GENBITS == 1
3118 ctrl |= F_EGRGENCTRL;
3119#endif
3120 if (adap->params.rev > 0) {
3121 if (!(adap->flags & (USING_MSIX | USING_MSI)))
3122 ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
4d22de3e
DLR
3123 }
3124 t3_write_reg(adap, A_SG_CONTROL, ctrl);
3125 t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
3126 V_LORCQDRBTHRSH(512));
3127 t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
3128 t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
6195c71d 3129 V_TIMEOUT(200 * core_ticks_per_usec(adap)));
b881955b
DLR
3130 t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,
3131 adap->params.rev < T3_REV_C ? 1000 : 500);
4d22de3e
DLR
3132 t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
3133 t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
3134 t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
3135 t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
3136 t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024);
3137}
3138
3139/**
3140 * t3_sge_prep - one-time SGE initialization
3141 * @adap: the associated adapter
3142 * @p: SGE parameters
3143 *
3144 * Performs one-time initialization of SGE SW state. Includes determining
3145 * defaults for the assorted SGE parameters, which admins can change until
3146 * they are used to initialize the SGE.
3147 */
7b9b0943 3148void t3_sge_prep(struct adapter *adap, struct sge_params *p)
4d22de3e
DLR
3149{
3150 int i;
3151
3152 p->max_pkt_size = (16 * 1024) - sizeof(struct cpl_rx_data) -
3153 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3154
3155 for (i = 0; i < SGE_QSETS; ++i) {
3156 struct qset_params *q = p->qset + i;
3157
3158 q->polling = adap->params.rev > 0;
3159 q->coalesce_usecs = 5;
3160 q->rspq_size = 1024;
e0994eb1 3161 q->fl_size = 1024;
7385ecf3 3162 q->jumbo_size = 512;
4d22de3e
DLR
3163 q->txq_size[TXQ_ETH] = 1024;
3164 q->txq_size[TXQ_OFLD] = 1024;
3165 q->txq_size[TXQ_CTRL] = 256;
3166 q->cong_thres = 0;
3167 }
3168
3169 spin_lock_init(&adap->sge.reg_lock);
3170}
3171
3172/**
3173 * t3_get_desc - dump an SGE descriptor for debugging purposes
3174 * @qs: the queue set
3175 * @qnum: identifies the specific queue (0..2: Tx, 3:response, 4..5: Rx)
3176 * @idx: the descriptor index in the queue
3177 * @data: where to dump the descriptor contents
3178 *
3179 * Dumps the contents of a HW descriptor of an SGE queue. Returns the
3180 * size of the descriptor.
3181 */
3182int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
3183 unsigned char *data)
3184{
3185 if (qnum >= 6)
3186 return -EINVAL;
3187
3188 if (qnum < 3) {
3189 if (!qs->txq[qnum].desc || idx >= qs->txq[qnum].size)
3190 return -EINVAL;
3191 memcpy(data, &qs->txq[qnum].desc[idx], sizeof(struct tx_desc));
3192 return sizeof(struct tx_desc);
3193 }
3194
3195 if (qnum == 3) {
3196 if (!qs->rspq.desc || idx >= qs->rspq.size)
3197 return -EINVAL;
3198 memcpy(data, &qs->rspq.desc[idx], sizeof(struct rsp_desc));
3199 return sizeof(struct rsp_desc);
3200 }
3201
3202 qnum -= 4;
3203 if (!qs->fl[qnum].desc || idx >= qs->fl[qnum].size)
3204 return -EINVAL;
3205 memcpy(data, &qs->fl[qnum].desc[idx], sizeof(struct rx_desc));
3206 return sizeof(struct rx_desc);
3207}
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