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1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef _T4FW_INTERFACE_H_ | |
36 | #define _T4FW_INTERFACE_H_ | |
37 | ||
38 | #define FW_T4VF_SGE_BASE_ADDR 0x0000 | |
39 | #define FW_T4VF_MPS_BASE_ADDR 0x0100 | |
40 | #define FW_T4VF_PL_BASE_ADDR 0x0200 | |
41 | #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 | |
42 | #define FW_T4VF_CIM_BASE_ADDR 0x0300 | |
43 | ||
44 | enum fw_wr_opcodes { | |
45 | FW_FILTER_WR = 0x02, | |
46 | FW_ULPTX_WR = 0x04, | |
47 | FW_TP_WR = 0x05, | |
48 | FW_ETH_TX_PKT_WR = 0x08, | |
49 | FW_FLOWC_WR = 0x0a, | |
50 | FW_OFLD_TX_DATA_WR = 0x0b, | |
51 | FW_CMD_WR = 0x10, | |
52 | FW_ETH_TX_PKT_VM_WR = 0x11, | |
53 | FW_RI_RES_WR = 0x0c, | |
54 | FW_RI_INIT_WR = 0x0d, | |
55 | FW_RI_RDMA_WRITE_WR = 0x14, | |
56 | FW_RI_SEND_WR = 0x15, | |
57 | FW_RI_RDMA_READ_WR = 0x16, | |
58 | FW_RI_RECV_WR = 0x17, | |
59 | FW_RI_BIND_MW_WR = 0x18, | |
60 | FW_RI_FR_NSMR_WR = 0x19, | |
61 | FW_RI_INV_LSTAG_WR = 0x1a, | |
62 | FW_LASTC2E_WR = 0x40 | |
63 | }; | |
64 | ||
65 | struct fw_wr_hdr { | |
66 | __be32 hi; | |
67 | __be32 lo; | |
68 | }; | |
69 | ||
70 | #define FW_WR_OP(x) ((x) << 24) | |
71 | #define FW_WR_ATOMIC(x) ((x) << 23) | |
72 | #define FW_WR_FLUSH(x) ((x) << 22) | |
73 | #define FW_WR_COMPL(x) ((x) << 21) | |
74 | #define FW_WR_IMMDLEN(x) ((x) << 0) | |
75 | ||
76 | #define FW_WR_EQUIQ (1U << 31) | |
77 | #define FW_WR_EQUEQ (1U << 30) | |
78 | #define FW_WR_FLOWID(x) ((x) << 8) | |
79 | #define FW_WR_LEN16(x) ((x) << 0) | |
80 | ||
81 | struct fw_ulptx_wr { | |
82 | __be32 op_to_compl; | |
83 | __be32 flowid_len16; | |
84 | u64 cookie; | |
85 | }; | |
86 | ||
87 | struct fw_tp_wr { | |
88 | __be32 op_to_immdlen; | |
89 | __be32 flowid_len16; | |
90 | u64 cookie; | |
91 | }; | |
92 | ||
93 | struct fw_eth_tx_pkt_wr { | |
94 | __be32 op_immdlen; | |
95 | __be32 equiq_to_len16; | |
96 | __be64 r3; | |
97 | }; | |
98 | ||
99 | enum fw_flowc_mnem { | |
100 | FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ | |
101 | FW_FLOWC_MNEM_CH, | |
102 | FW_FLOWC_MNEM_PORT, | |
103 | FW_FLOWC_MNEM_IQID, | |
104 | FW_FLOWC_MNEM_SNDNXT, | |
105 | FW_FLOWC_MNEM_RCVNXT, | |
106 | FW_FLOWC_MNEM_SNDBUF, | |
107 | FW_FLOWC_MNEM_MSS, | |
108 | }; | |
109 | ||
110 | struct fw_flowc_mnemval { | |
111 | u8 mnemonic; | |
112 | u8 r4[3]; | |
113 | __be32 val; | |
114 | }; | |
115 | ||
116 | struct fw_flowc_wr { | |
117 | __be32 op_to_nparams; | |
118 | #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0) | |
119 | __be32 flowid_len16; | |
120 | struct fw_flowc_mnemval mnemval[0]; | |
121 | }; | |
122 | ||
123 | struct fw_ofld_tx_data_wr { | |
124 | __be32 op_to_immdlen; | |
125 | __be32 flowid_len16; | |
126 | __be32 plen; | |
127 | __be32 tunnel_to_proxy; | |
128 | #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19) | |
129 | #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18) | |
130 | #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17) | |
131 | #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16) | |
132 | #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15) | |
133 | #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14) | |
134 | #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10) | |
135 | #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6) | |
136 | }; | |
137 | ||
138 | struct fw_cmd_wr { | |
139 | __be32 op_dma; | |
140 | #define FW_CMD_WR_DMA (1U << 17) | |
141 | __be32 len16_pkd; | |
142 | __be64 cookie_daddr; | |
143 | }; | |
144 | ||
145 | struct fw_eth_tx_pkt_vm_wr { | |
146 | __be32 op_immdlen; | |
147 | __be32 equiq_to_len16; | |
148 | __be32 r3[2]; | |
149 | u8 ethmacdst[6]; | |
150 | u8 ethmacsrc[6]; | |
151 | __be16 ethtype; | |
152 | __be16 vlantci; | |
153 | }; | |
154 | ||
155 | #define FW_CMD_MAX_TIMEOUT 3000 | |
156 | ||
157 | enum fw_cmd_opcodes { | |
158 | FW_LDST_CMD = 0x01, | |
159 | FW_RESET_CMD = 0x03, | |
160 | FW_HELLO_CMD = 0x04, | |
161 | FW_BYE_CMD = 0x05, | |
162 | FW_INITIALIZE_CMD = 0x06, | |
163 | FW_CAPS_CONFIG_CMD = 0x07, | |
164 | FW_PARAMS_CMD = 0x08, | |
165 | FW_PFVF_CMD = 0x09, | |
166 | FW_IQ_CMD = 0x10, | |
167 | FW_EQ_MNGT_CMD = 0x11, | |
168 | FW_EQ_ETH_CMD = 0x12, | |
169 | FW_EQ_CTRL_CMD = 0x13, | |
170 | FW_EQ_OFLD_CMD = 0x21, | |
171 | FW_VI_CMD = 0x14, | |
172 | FW_VI_MAC_CMD = 0x15, | |
173 | FW_VI_RXMODE_CMD = 0x16, | |
174 | FW_VI_ENABLE_CMD = 0x17, | |
175 | FW_ACL_MAC_CMD = 0x18, | |
176 | FW_ACL_VLAN_CMD = 0x19, | |
177 | FW_VI_STATS_CMD = 0x1a, | |
178 | FW_PORT_CMD = 0x1b, | |
179 | FW_PORT_STATS_CMD = 0x1c, | |
180 | FW_PORT_LB_STATS_CMD = 0x1d, | |
181 | FW_PORT_TRACE_CMD = 0x1e, | |
182 | FW_PORT_TRACE_MMAP_CMD = 0x1f, | |
183 | FW_RSS_IND_TBL_CMD = 0x20, | |
184 | FW_RSS_GLB_CONFIG_CMD = 0x22, | |
185 | FW_RSS_VI_CONFIG_CMD = 0x23, | |
186 | FW_LASTC2E_CMD = 0x40, | |
187 | FW_ERROR_CMD = 0x80, | |
188 | FW_DEBUG_CMD = 0x81, | |
189 | }; | |
190 | ||
191 | enum fw_cmd_cap { | |
192 | FW_CMD_CAP_PF = 0x01, | |
193 | FW_CMD_CAP_DMAQ = 0x02, | |
194 | FW_CMD_CAP_PORT = 0x04, | |
195 | FW_CMD_CAP_PORTPROMISC = 0x08, | |
196 | FW_CMD_CAP_PORTSTATS = 0x10, | |
197 | FW_CMD_CAP_VF = 0x80, | |
198 | }; | |
199 | ||
200 | /* | |
201 | * Generic command header flit0 | |
202 | */ | |
203 | struct fw_cmd_hdr { | |
204 | __be32 hi; | |
205 | __be32 lo; | |
206 | }; | |
207 | ||
208 | #define FW_CMD_OP(x) ((x) << 24) | |
209 | #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff) | |
210 | #define FW_CMD_REQUEST (1U << 23) | |
211 | #define FW_CMD_READ (1U << 22) | |
212 | #define FW_CMD_WRITE (1U << 21) | |
213 | #define FW_CMD_EXEC (1U << 20) | |
214 | #define FW_CMD_RAMASK(x) ((x) << 20) | |
215 | #define FW_CMD_RETVAL(x) ((x) << 8) | |
216 | #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff) | |
217 | #define FW_CMD_LEN16(x) ((x) << 0) | |
218 | ||
219 | enum fw_ldst_addrspc { | |
220 | FW_LDST_ADDRSPC_FIRMWARE = 0x0001, | |
221 | FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, | |
222 | FW_LDST_ADDRSPC_SGE_INGC = 0x0009, | |
223 | FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, | |
224 | FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, | |
225 | FW_LDST_ADDRSPC_TP_PIO = 0x0010, | |
226 | FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, | |
227 | FW_LDST_ADDRSPC_TP_MIB = 0x0012, | |
228 | FW_LDST_ADDRSPC_MDIO = 0x0018, | |
229 | FW_LDST_ADDRSPC_MPS = 0x0020, | |
230 | FW_LDST_ADDRSPC_FUNC = 0x0028 | |
231 | }; | |
232 | ||
233 | enum fw_ldst_mps_fid { | |
234 | FW_LDST_MPS_ATRB, | |
235 | FW_LDST_MPS_RPLC | |
236 | }; | |
237 | ||
238 | enum fw_ldst_func_access_ctl { | |
239 | FW_LDST_FUNC_ACC_CTL_VIID, | |
240 | FW_LDST_FUNC_ACC_CTL_FID | |
241 | }; | |
242 | ||
243 | enum fw_ldst_func_mod_index { | |
244 | FW_LDST_FUNC_MPS | |
245 | }; | |
246 | ||
247 | struct fw_ldst_cmd { | |
248 | __be32 op_to_addrspace; | |
249 | #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0) | |
250 | __be32 cycles_to_len16; | |
251 | union fw_ldst { | |
252 | struct fw_ldst_addrval { | |
253 | __be32 addr; | |
254 | __be32 val; | |
255 | } addrval; | |
256 | struct fw_ldst_idctxt { | |
257 | __be32 physid; | |
258 | __be32 msg_pkd; | |
259 | __be32 ctxt_data7; | |
260 | __be32 ctxt_data6; | |
261 | __be32 ctxt_data5; | |
262 | __be32 ctxt_data4; | |
263 | __be32 ctxt_data3; | |
264 | __be32 ctxt_data2; | |
265 | __be32 ctxt_data1; | |
266 | __be32 ctxt_data0; | |
267 | } idctxt; | |
268 | struct fw_ldst_mdio { | |
269 | __be16 paddr_mmd; | |
270 | __be16 raddr; | |
271 | __be16 vctl; | |
272 | __be16 rval; | |
273 | } mdio; | |
274 | struct fw_ldst_mps { | |
275 | __be16 fid_ctl; | |
276 | __be16 rplcpf_pkd; | |
277 | __be32 rplc127_96; | |
278 | __be32 rplc95_64; | |
279 | __be32 rplc63_32; | |
280 | __be32 rplc31_0; | |
281 | __be32 atrb; | |
282 | __be16 vlan[16]; | |
283 | } mps; | |
284 | struct fw_ldst_func { | |
285 | u8 access_ctl; | |
286 | u8 mod_index; | |
287 | __be16 ctl_id; | |
288 | __be32 offset; | |
289 | __be64 data0; | |
290 | __be64 data1; | |
291 | } func; | |
292 | } u; | |
293 | }; | |
294 | ||
295 | #define FW_LDST_CMD_MSG(x) ((x) << 31) | |
296 | #define FW_LDST_CMD_PADDR(x) ((x) << 8) | |
297 | #define FW_LDST_CMD_MMD(x) ((x) << 0) | |
298 | #define FW_LDST_CMD_FID(x) ((x) << 15) | |
299 | #define FW_LDST_CMD_CTL(x) ((x) << 0) | |
300 | #define FW_LDST_CMD_RPLCPF(x) ((x) << 0) | |
301 | ||
302 | struct fw_reset_cmd { | |
303 | __be32 op_to_write; | |
304 | __be32 retval_len16; | |
305 | __be32 val; | |
306 | __be32 r3; | |
307 | }; | |
308 | ||
309 | struct fw_hello_cmd { | |
310 | __be32 op_to_write; | |
311 | __be32 retval_len16; | |
312 | __be32 err_to_mbasyncnot; | |
313 | #define FW_HELLO_CMD_ERR (1U << 31) | |
314 | #define FW_HELLO_CMD_INIT (1U << 30) | |
315 | #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29) | |
316 | #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28) | |
317 | #define FW_HELLO_CMD_MBMASTER(x) ((x) << 24) | |
318 | #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20) | |
319 | __be32 fwrev; | |
320 | }; | |
321 | ||
322 | struct fw_bye_cmd { | |
323 | __be32 op_to_write; | |
324 | __be32 retval_len16; | |
325 | __be64 r3; | |
326 | }; | |
327 | ||
328 | struct fw_initialize_cmd { | |
329 | __be32 op_to_write; | |
330 | __be32 retval_len16; | |
331 | __be64 r3; | |
332 | }; | |
333 | ||
334 | enum fw_caps_config_hm { | |
335 | FW_CAPS_CONFIG_HM_PCIE = 0x00000001, | |
336 | FW_CAPS_CONFIG_HM_PL = 0x00000002, | |
337 | FW_CAPS_CONFIG_HM_SGE = 0x00000004, | |
338 | FW_CAPS_CONFIG_HM_CIM = 0x00000008, | |
339 | FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, | |
340 | FW_CAPS_CONFIG_HM_TP = 0x00000020, | |
341 | FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, | |
342 | FW_CAPS_CONFIG_HM_PMRX = 0x00000080, | |
343 | FW_CAPS_CONFIG_HM_PMTX = 0x00000100, | |
344 | FW_CAPS_CONFIG_HM_MC = 0x00000200, | |
345 | FW_CAPS_CONFIG_HM_LE = 0x00000400, | |
346 | FW_CAPS_CONFIG_HM_MPS = 0x00000800, | |
347 | FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, | |
348 | FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, | |
349 | FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, | |
350 | FW_CAPS_CONFIG_HM_MI = 0x00008000, | |
351 | FW_CAPS_CONFIG_HM_I2CM = 0x00010000, | |
352 | FW_CAPS_CONFIG_HM_NCSI = 0x00020000, | |
353 | FW_CAPS_CONFIG_HM_SMB = 0x00040000, | |
354 | FW_CAPS_CONFIG_HM_MA = 0x00080000, | |
355 | FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, | |
356 | FW_CAPS_CONFIG_HM_PMU = 0x00200000, | |
357 | FW_CAPS_CONFIG_HM_UART = 0x00400000, | |
358 | FW_CAPS_CONFIG_HM_SF = 0x00800000, | |
359 | }; | |
360 | ||
361 | enum fw_caps_config_nbm { | |
362 | FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, | |
363 | FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, | |
364 | }; | |
365 | ||
366 | enum fw_caps_config_link { | |
367 | FW_CAPS_CONFIG_LINK_PPP = 0x00000001, | |
368 | FW_CAPS_CONFIG_LINK_QFC = 0x00000002, | |
369 | FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, | |
370 | }; | |
371 | ||
372 | enum fw_caps_config_switch { | |
373 | FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, | |
374 | FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, | |
375 | }; | |
376 | ||
377 | enum fw_caps_config_nic { | |
378 | FW_CAPS_CONFIG_NIC = 0x00000001, | |
379 | FW_CAPS_CONFIG_NIC_VM = 0x00000002, | |
380 | }; | |
381 | ||
382 | enum fw_caps_config_ofld { | |
383 | FW_CAPS_CONFIG_OFLD = 0x00000001, | |
384 | }; | |
385 | ||
386 | enum fw_caps_config_rdma { | |
387 | FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, | |
388 | FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, | |
389 | }; | |
390 | ||
391 | enum fw_caps_config_iscsi { | |
392 | FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, | |
393 | FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, | |
394 | FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, | |
395 | FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, | |
396 | }; | |
397 | ||
398 | enum fw_caps_config_fcoe { | |
399 | FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, | |
400 | FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, | |
401 | }; | |
402 | ||
403 | struct fw_caps_config_cmd { | |
404 | __be32 op_to_write; | |
405 | __be32 retval_len16; | |
406 | __be32 r2; | |
407 | __be32 hwmbitmap; | |
408 | __be16 nbmcaps; | |
409 | __be16 linkcaps; | |
410 | __be16 switchcaps; | |
411 | __be16 r3; | |
412 | __be16 niccaps; | |
413 | __be16 ofldcaps; | |
414 | __be16 rdmacaps; | |
415 | __be16 r4; | |
416 | __be16 iscsicaps; | |
417 | __be16 fcoecaps; | |
418 | __be32 r5; | |
419 | __be64 r6; | |
420 | }; | |
421 | ||
422 | /* | |
423 | * params command mnemonics | |
424 | */ | |
425 | enum fw_params_mnem { | |
426 | FW_PARAMS_MNEM_DEV = 1, /* device params */ | |
427 | FW_PARAMS_MNEM_PFVF = 2, /* function params */ | |
428 | FW_PARAMS_MNEM_REG = 3, /* limited register access */ | |
429 | FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ | |
430 | FW_PARAMS_MNEM_LAST | |
431 | }; | |
432 | ||
433 | /* | |
434 | * device parameters | |
435 | */ | |
436 | enum fw_params_param_dev { | |
437 | FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ | |
438 | FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ | |
439 | FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs | |
440 | * allocated by the device's | |
441 | * Lookup Engine | |
442 | */ | |
443 | FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, | |
444 | FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, | |
445 | FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, | |
446 | FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, | |
447 | FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, | |
448 | FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, | |
449 | FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, | |
450 | FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A | |
451 | }; | |
452 | ||
453 | /* | |
454 | * physical and virtual function parameters | |
455 | */ | |
456 | enum fw_params_param_pfvf { | |
457 | FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, | |
458 | FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, | |
459 | FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, | |
460 | FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, | |
461 | FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, | |
462 | FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, | |
463 | FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, | |
464 | FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, | |
465 | FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, | |
466 | FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, | |
467 | FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, | |
468 | FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, | |
469 | FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, | |
470 | FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, | |
471 | FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, | |
472 | FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, | |
473 | FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, | |
474 | FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, | |
475 | FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, | |
476 | FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, | |
477 | FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, | |
478 | FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, | |
479 | }; | |
480 | ||
481 | /* | |
482 | * dma queue parameters | |
483 | */ | |
484 | enum fw_params_param_dmaq { | |
485 | FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, | |
486 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, | |
487 | FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, | |
488 | FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, | |
489 | FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, | |
490 | }; | |
491 | ||
492 | #define FW_PARAMS_MNEM(x) ((x) << 24) | |
493 | #define FW_PARAMS_PARAM_X(x) ((x) << 16) | |
494 | #define FW_PARAMS_PARAM_Y(x) ((x) << 8) | |
495 | #define FW_PARAMS_PARAM_Z(x) ((x) << 0) | |
496 | #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0) | |
497 | #define FW_PARAMS_PARAM_YZ(x) ((x) << 0) | |
498 | ||
499 | struct fw_params_cmd { | |
500 | __be32 op_to_vfn; | |
501 | __be32 retval_len16; | |
502 | struct fw_params_param { | |
503 | __be32 mnem; | |
504 | __be32 val; | |
505 | } param[7]; | |
506 | }; | |
507 | ||
508 | #define FW_PARAMS_CMD_PFN(x) ((x) << 8) | |
509 | #define FW_PARAMS_CMD_VFN(x) ((x) << 0) | |
510 | ||
511 | struct fw_pfvf_cmd { | |
512 | __be32 op_to_vfn; | |
513 | __be32 retval_len16; | |
514 | __be32 niqflint_niq; | |
515 | __be32 cmask_to_neq; | |
516 | __be32 tc_to_nexactf; | |
517 | __be32 r_caps_to_nethctrl; | |
518 | __be16 nricq; | |
519 | __be16 nriqp; | |
520 | __be32 r4; | |
521 | }; | |
522 | ||
523 | #define FW_PFVF_CMD_PFN(x) ((x) << 8) | |
524 | #define FW_PFVF_CMD_VFN(x) ((x) << 0) | |
525 | ||
526 | #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20) | |
527 | #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff) | |
528 | ||
529 | #define FW_PFVF_CMD_NIQ(x) ((x) << 0) | |
530 | #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff) | |
531 | ||
532 | #define FW_PFVF_CMD_CMASK(x) ((x) << 24) | |
533 | #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & 0xf) | |
534 | ||
535 | #define FW_PFVF_CMD_PMASK(x) ((x) << 20) | |
536 | #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & 0xf) | |
537 | ||
538 | #define FW_PFVF_CMD_NEQ(x) ((x) << 0) | |
539 | #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff) | |
540 | ||
541 | #define FW_PFVF_CMD_TC(x) ((x) << 24) | |
542 | #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff) | |
543 | ||
544 | #define FW_PFVF_CMD_NVI(x) ((x) << 16) | |
545 | #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff) | |
546 | ||
547 | #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0) | |
548 | #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff) | |
549 | ||
550 | #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24) | |
551 | #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff) | |
552 | ||
553 | #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16) | |
554 | #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff) | |
555 | ||
556 | #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0) | |
557 | #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff) | |
558 | ||
559 | enum fw_iq_type { | |
560 | FW_IQ_TYPE_FL_INT_CAP, | |
561 | FW_IQ_TYPE_NO_FL_INT_CAP | |
562 | }; | |
563 | ||
564 | struct fw_iq_cmd { | |
565 | __be32 op_to_vfn; | |
566 | __be32 alloc_to_len16; | |
567 | __be16 physiqid; | |
568 | __be16 iqid; | |
569 | __be16 fl0id; | |
570 | __be16 fl1id; | |
571 | __be32 type_to_iqandstindex; | |
572 | __be16 iqdroprss_to_iqesize; | |
573 | __be16 iqsize; | |
574 | __be64 iqaddr; | |
575 | __be32 iqns_to_fl0congen; | |
576 | __be16 fl0dcaen_to_fl0cidxfthresh; | |
577 | __be16 fl0size; | |
578 | __be64 fl0addr; | |
579 | __be32 fl1cngchmap_to_fl1congen; | |
580 | __be16 fl1dcaen_to_fl1cidxfthresh; | |
581 | __be16 fl1size; | |
582 | __be64 fl1addr; | |
583 | }; | |
584 | ||
585 | #define FW_IQ_CMD_PFN(x) ((x) << 8) | |
586 | #define FW_IQ_CMD_VFN(x) ((x) << 0) | |
587 | ||
588 | #define FW_IQ_CMD_ALLOC (1U << 31) | |
589 | #define FW_IQ_CMD_FREE (1U << 30) | |
590 | #define FW_IQ_CMD_MODIFY (1U << 29) | |
591 | #define FW_IQ_CMD_IQSTART(x) ((x) << 28) | |
592 | #define FW_IQ_CMD_IQSTOP(x) ((x) << 27) | |
593 | ||
594 | #define FW_IQ_CMD_TYPE(x) ((x) << 29) | |
595 | #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28) | |
596 | #define FW_IQ_CMD_VIID(x) ((x) << 16) | |
597 | #define FW_IQ_CMD_IQANDST(x) ((x) << 15) | |
598 | #define FW_IQ_CMD_IQANUS(x) ((x) << 14) | |
599 | #define FW_IQ_CMD_IQANUD(x) ((x) << 12) | |
600 | #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0) | |
601 | ||
602 | #define FW_IQ_CMD_IQDROPRSS (1U << 15) | |
603 | #define FW_IQ_CMD_IQGTSMODE (1U << 14) | |
604 | #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12) | |
605 | #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11) | |
606 | #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6) | |
607 | #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4) | |
608 | #define FW_IQ_CMD_IQO (1U << 3) | |
609 | #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2) | |
610 | #define FW_IQ_CMD_IQESIZE(x) ((x) << 0) | |
611 | ||
612 | #define FW_IQ_CMD_IQNS(x) ((x) << 31) | |
613 | #define FW_IQ_CMD_IQRO(x) ((x) << 30) | |
614 | #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28) | |
615 | #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27) | |
616 | #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26) | |
617 | #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20) | |
618 | #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15) | |
619 | #define FW_IQ_CMD_FL0DBP(x) ((x) << 14) | |
620 | #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13) | |
621 | #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12) | |
622 | #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11) | |
623 | #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10) | |
624 | #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9) | |
625 | #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8) | |
626 | #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7) | |
627 | #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6) | |
628 | #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4) | |
629 | #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3) | |
630 | #define FW_IQ_CMD_FL0PADEN (1U << 2) | |
631 | #define FW_IQ_CMD_FL0PACKEN (1U << 1) | |
632 | #define FW_IQ_CMD_FL0CONGEN (1U << 0) | |
633 | ||
634 | #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15) | |
635 | #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10) | |
636 | #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7) | |
637 | #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4) | |
638 | #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3) | |
639 | #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0) | |
640 | ||
641 | #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20) | |
642 | #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15) | |
643 | #define FW_IQ_CMD_FL1DBP(x) ((x) << 14) | |
644 | #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13) | |
645 | #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12) | |
646 | #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11) | |
647 | #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10) | |
648 | #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9) | |
649 | #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8) | |
650 | #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7) | |
651 | #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6) | |
652 | #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4) | |
653 | #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3) | |
654 | #define FW_IQ_CMD_FL1PADEN (1U << 2) | |
655 | #define FW_IQ_CMD_FL1PACKEN (1U << 1) | |
656 | #define FW_IQ_CMD_FL1CONGEN (1U << 0) | |
657 | ||
658 | #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15) | |
659 | #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10) | |
660 | #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7) | |
661 | #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4) | |
662 | #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3) | |
663 | #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0) | |
664 | ||
665 | struct fw_eq_eth_cmd { | |
666 | __be32 op_to_vfn; | |
667 | __be32 alloc_to_len16; | |
668 | __be32 eqid_pkd; | |
669 | __be32 physeqid_pkd; | |
670 | __be32 fetchszm_to_iqid; | |
671 | __be32 dcaen_to_eqsize; | |
672 | __be64 eqaddr; | |
673 | __be32 viid_pkd; | |
674 | __be32 r8_lo; | |
675 | __be64 r9; | |
676 | }; | |
677 | ||
678 | #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8) | |
679 | #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0) | |
680 | #define FW_EQ_ETH_CMD_ALLOC (1U << 31) | |
681 | #define FW_EQ_ETH_CMD_FREE (1U << 30) | |
682 | #define FW_EQ_ETH_CMD_MODIFY (1U << 29) | |
683 | #define FW_EQ_ETH_CMD_EQSTART (1U << 28) | |
684 | #define FW_EQ_ETH_CMD_EQSTOP (1U << 27) | |
685 | ||
686 | #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0) | |
687 | #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) | |
688 | #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0) | |
689 | ||
690 | #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26) | |
691 | #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25) | |
692 | #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24) | |
693 | #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23) | |
694 | #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22) | |
695 | #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20) | |
696 | #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19) | |
697 | #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18) | |
698 | #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16) | |
699 | #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0) | |
700 | ||
701 | #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31) | |
702 | #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26) | |
703 | #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23) | |
704 | #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20) | |
705 | #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19) | |
706 | #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16) | |
707 | #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0) | |
708 | ||
709 | #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16) | |
710 | ||
711 | struct fw_eq_ctrl_cmd { | |
712 | __be32 op_to_vfn; | |
713 | __be32 alloc_to_len16; | |
714 | __be32 cmpliqid_eqid; | |
715 | __be32 physeqid_pkd; | |
716 | __be32 fetchszm_to_iqid; | |
717 | __be32 dcaen_to_eqsize; | |
718 | __be64 eqaddr; | |
719 | }; | |
720 | ||
721 | #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8) | |
722 | #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0) | |
723 | ||
724 | #define FW_EQ_CTRL_CMD_ALLOC (1U << 31) | |
725 | #define FW_EQ_CTRL_CMD_FREE (1U << 30) | |
726 | #define FW_EQ_CTRL_CMD_MODIFY (1U << 29) | |
727 | #define FW_EQ_CTRL_CMD_EQSTART (1U << 28) | |
728 | #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27) | |
729 | ||
730 | #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20) | |
731 | #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0) | |
732 | #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) | |
733 | #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) | |
734 | ||
735 | #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26) | |
736 | #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25) | |
737 | #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24) | |
738 | #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23) | |
739 | #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22) | |
740 | #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20) | |
741 | #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19) | |
742 | #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18) | |
743 | #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16) | |
744 | #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0) | |
745 | ||
746 | #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31) | |
747 | #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26) | |
748 | #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23) | |
749 | #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20) | |
750 | #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19) | |
751 | #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16) | |
752 | #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0) | |
753 | ||
754 | struct fw_eq_ofld_cmd { | |
755 | __be32 op_to_vfn; | |
756 | __be32 alloc_to_len16; | |
757 | __be32 eqid_pkd; | |
758 | __be32 physeqid_pkd; | |
759 | __be32 fetchszm_to_iqid; | |
760 | __be32 dcaen_to_eqsize; | |
761 | __be64 eqaddr; | |
762 | }; | |
763 | ||
764 | #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8) | |
765 | #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0) | |
766 | ||
767 | #define FW_EQ_OFLD_CMD_ALLOC (1U << 31) | |
768 | #define FW_EQ_OFLD_CMD_FREE (1U << 30) | |
769 | #define FW_EQ_OFLD_CMD_MODIFY (1U << 29) | |
770 | #define FW_EQ_OFLD_CMD_EQSTART (1U << 28) | |
771 | #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27) | |
772 | ||
773 | #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0) | |
774 | #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) | |
775 | #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) | |
776 | ||
777 | #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26) | |
778 | #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25) | |
779 | #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24) | |
780 | #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23) | |
781 | #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22) | |
782 | #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20) | |
783 | #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19) | |
784 | #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18) | |
785 | #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16) | |
786 | #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0) | |
787 | ||
788 | #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31) | |
789 | #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26) | |
790 | #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23) | |
791 | #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20) | |
792 | #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19) | |
793 | #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16) | |
794 | #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0) | |
795 | ||
796 | /* | |
797 | * Macros for VIID parsing: | |
798 | * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number | |
799 | */ | |
800 | #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7) | |
801 | #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1) | |
802 | #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F) | |
803 | ||
804 | struct fw_vi_cmd { | |
805 | __be32 op_to_vfn; | |
806 | __be32 alloc_to_len16; | |
807 | __be16 viid_pkd; | |
808 | u8 mac[6]; | |
809 | u8 portid_pkd; | |
810 | u8 nmac; | |
811 | u8 nmac0[6]; | |
812 | __be16 rsssize_pkd; | |
813 | u8 nmac1[6]; | |
814 | __be16 r7; | |
815 | u8 nmac2[6]; | |
816 | __be16 r8; | |
817 | u8 nmac3[6]; | |
818 | __be64 r9; | |
819 | __be64 r10; | |
820 | }; | |
821 | ||
822 | #define FW_VI_CMD_PFN(x) ((x) << 8) | |
823 | #define FW_VI_CMD_VFN(x) ((x) << 0) | |
824 | #define FW_VI_CMD_ALLOC (1U << 31) | |
825 | #define FW_VI_CMD_FREE (1U << 30) | |
826 | #define FW_VI_CMD_VIID(x) ((x) << 0) | |
827 | #define FW_VI_CMD_PORTID(x) ((x) << 4) | |
828 | #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff) | |
829 | ||
830 | /* Special VI_MAC command index ids */ | |
831 | #define FW_VI_MAC_ADD_MAC 0x3FF | |
832 | #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE | |
833 | #define FW_VI_MAC_MAC_BASED_FREE 0x3FD | |
834 | ||
835 | enum fw_vi_mac_smac { | |
836 | FW_VI_MAC_MPS_TCAM_ENTRY, | |
837 | FW_VI_MAC_MPS_TCAM_ONLY, | |
838 | FW_VI_MAC_SMT_ONLY, | |
839 | FW_VI_MAC_SMT_AND_MPSTCAM | |
840 | }; | |
841 | ||
842 | enum fw_vi_mac_result { | |
843 | FW_VI_MAC_R_SUCCESS, | |
844 | FW_VI_MAC_R_F_NONEXISTENT_NOMEM, | |
845 | FW_VI_MAC_R_SMAC_FAIL, | |
846 | FW_VI_MAC_R_F_ACL_CHECK | |
847 | }; | |
848 | ||
849 | struct fw_vi_mac_cmd { | |
850 | __be32 op_to_viid; | |
851 | __be32 freemacs_to_len16; | |
852 | union fw_vi_mac { | |
853 | struct fw_vi_mac_exact { | |
854 | __be16 valid_to_idx; | |
855 | u8 macaddr[6]; | |
856 | } exact[7]; | |
857 | struct fw_vi_mac_hash { | |
858 | __be64 hashvec; | |
859 | } hash; | |
860 | } u; | |
861 | }; | |
862 | ||
863 | #define FW_VI_MAC_CMD_VIID(x) ((x) << 0) | |
864 | #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31) | |
865 | #define FW_VI_MAC_CMD_HASHVECEN (1U << 23) | |
866 | #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22) | |
867 | #define FW_VI_MAC_CMD_VALID (1U << 15) | |
868 | #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12) | |
869 | #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10) | |
870 | #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3) | |
871 | #define FW_VI_MAC_CMD_IDX(x) ((x) << 0) | |
872 | #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff) | |
873 | ||
874 | #define FW_RXMODE_MTU_NO_CHG 65535 | |
875 | ||
876 | struct fw_vi_rxmode_cmd { | |
877 | __be32 op_to_viid; | |
878 | __be32 retval_len16; | |
f8f5aafa | 879 | __be32 mtu_to_vlanexen; |
bbc02c7e DM |
880 | __be32 r4_lo; |
881 | }; | |
882 | ||
883 | #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0) | |
884 | #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16) | |
885 | #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3 | |
886 | #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14) | |
887 | #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3 | |
888 | #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12) | |
889 | #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3 | |
890 | #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10) | |
f8f5aafa DM |
891 | #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3 |
892 | #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8) | |
bbc02c7e DM |
893 | |
894 | struct fw_vi_enable_cmd { | |
895 | __be32 op_to_viid; | |
896 | __be32 ien_to_len16; | |
897 | __be16 blinkdur; | |
898 | __be16 r3; | |
899 | __be32 r4; | |
900 | }; | |
901 | ||
902 | #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0) | |
903 | #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31) | |
904 | #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30) | |
905 | #define FW_VI_ENABLE_CMD_LED (1U << 29) | |
906 | ||
907 | /* VI VF stats offset definitions */ | |
908 | #define VI_VF_NUM_STATS 16 | |
909 | enum fw_vi_stats_vf_index { | |
910 | FW_VI_VF_STAT_TX_BCAST_BYTES_IX, | |
911 | FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, | |
912 | FW_VI_VF_STAT_TX_MCAST_BYTES_IX, | |
913 | FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, | |
914 | FW_VI_VF_STAT_TX_UCAST_BYTES_IX, | |
915 | FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, | |
916 | FW_VI_VF_STAT_TX_DROP_FRAMES_IX, | |
917 | FW_VI_VF_STAT_TX_OFLD_BYTES_IX, | |
918 | FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, | |
919 | FW_VI_VF_STAT_RX_BCAST_BYTES_IX, | |
920 | FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, | |
921 | FW_VI_VF_STAT_RX_MCAST_BYTES_IX, | |
922 | FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, | |
923 | FW_VI_VF_STAT_RX_UCAST_BYTES_IX, | |
924 | FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, | |
925 | FW_VI_VF_STAT_RX_ERR_FRAMES_IX | |
926 | }; | |
927 | ||
928 | /* VI PF stats offset definitions */ | |
929 | #define VI_PF_NUM_STATS 17 | |
930 | enum fw_vi_stats_pf_index { | |
931 | FW_VI_PF_STAT_TX_BCAST_BYTES_IX, | |
932 | FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, | |
933 | FW_VI_PF_STAT_TX_MCAST_BYTES_IX, | |
934 | FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, | |
935 | FW_VI_PF_STAT_TX_UCAST_BYTES_IX, | |
936 | FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, | |
937 | FW_VI_PF_STAT_TX_OFLD_BYTES_IX, | |
938 | FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, | |
939 | FW_VI_PF_STAT_RX_BYTES_IX, | |
940 | FW_VI_PF_STAT_RX_FRAMES_IX, | |
941 | FW_VI_PF_STAT_RX_BCAST_BYTES_IX, | |
942 | FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, | |
943 | FW_VI_PF_STAT_RX_MCAST_BYTES_IX, | |
944 | FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, | |
945 | FW_VI_PF_STAT_RX_UCAST_BYTES_IX, | |
946 | FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, | |
947 | FW_VI_PF_STAT_RX_ERR_FRAMES_IX | |
948 | }; | |
949 | ||
950 | struct fw_vi_stats_cmd { | |
951 | __be32 op_to_viid; | |
952 | __be32 retval_len16; | |
953 | union fw_vi_stats { | |
954 | struct fw_vi_stats_ctl { | |
955 | __be16 nstats_ix; | |
956 | __be16 r6; | |
957 | __be32 r7; | |
958 | __be64 stat0; | |
959 | __be64 stat1; | |
960 | __be64 stat2; | |
961 | __be64 stat3; | |
962 | __be64 stat4; | |
963 | __be64 stat5; | |
964 | } ctl; | |
965 | struct fw_vi_stats_pf { | |
966 | __be64 tx_bcast_bytes; | |
967 | __be64 tx_bcast_frames; | |
968 | __be64 tx_mcast_bytes; | |
969 | __be64 tx_mcast_frames; | |
970 | __be64 tx_ucast_bytes; | |
971 | __be64 tx_ucast_frames; | |
972 | __be64 tx_offload_bytes; | |
973 | __be64 tx_offload_frames; | |
974 | __be64 rx_pf_bytes; | |
975 | __be64 rx_pf_frames; | |
976 | __be64 rx_bcast_bytes; | |
977 | __be64 rx_bcast_frames; | |
978 | __be64 rx_mcast_bytes; | |
979 | __be64 rx_mcast_frames; | |
980 | __be64 rx_ucast_bytes; | |
981 | __be64 rx_ucast_frames; | |
982 | __be64 rx_err_frames; | |
983 | } pf; | |
984 | struct fw_vi_stats_vf { | |
985 | __be64 tx_bcast_bytes; | |
986 | __be64 tx_bcast_frames; | |
987 | __be64 tx_mcast_bytes; | |
988 | __be64 tx_mcast_frames; | |
989 | __be64 tx_ucast_bytes; | |
990 | __be64 tx_ucast_frames; | |
991 | __be64 tx_drop_frames; | |
992 | __be64 tx_offload_bytes; | |
993 | __be64 tx_offload_frames; | |
994 | __be64 rx_bcast_bytes; | |
995 | __be64 rx_bcast_frames; | |
996 | __be64 rx_mcast_bytes; | |
997 | __be64 rx_mcast_frames; | |
998 | __be64 rx_ucast_bytes; | |
999 | __be64 rx_ucast_frames; | |
1000 | __be64 rx_err_frames; | |
1001 | } vf; | |
1002 | } u; | |
1003 | }; | |
1004 | ||
1005 | #define FW_VI_STATS_CMD_VIID(x) ((x) << 0) | |
1006 | #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12) | |
1007 | #define FW_VI_STATS_CMD_IX(x) ((x) << 0) | |
1008 | ||
1009 | struct fw_acl_mac_cmd { | |
1010 | __be32 op_to_vfn; | |
1011 | __be32 en_to_len16; | |
1012 | u8 nmac; | |
1013 | u8 r3[7]; | |
1014 | __be16 r4; | |
1015 | u8 macaddr0[6]; | |
1016 | __be16 r5; | |
1017 | u8 macaddr1[6]; | |
1018 | __be16 r6; | |
1019 | u8 macaddr2[6]; | |
1020 | __be16 r7; | |
1021 | u8 macaddr3[6]; | |
1022 | }; | |
1023 | ||
1024 | #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8) | |
1025 | #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0) | |
1026 | #define FW_ACL_MAC_CMD_EN(x) ((x) << 31) | |
1027 | ||
1028 | struct fw_acl_vlan_cmd { | |
1029 | __be32 op_to_vfn; | |
1030 | __be32 en_to_len16; | |
1031 | u8 nvlan; | |
1032 | u8 dropnovlan_fm; | |
1033 | u8 r3_lo[6]; | |
1034 | __be16 vlanid[16]; | |
1035 | }; | |
1036 | ||
1037 | #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8) | |
1038 | #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0) | |
1039 | #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31) | |
1040 | #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7) | |
1041 | #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6) | |
1042 | ||
1043 | enum fw_port_cap { | |
1044 | FW_PORT_CAP_SPEED_100M = 0x0001, | |
1045 | FW_PORT_CAP_SPEED_1G = 0x0002, | |
1046 | FW_PORT_CAP_SPEED_2_5G = 0x0004, | |
1047 | FW_PORT_CAP_SPEED_10G = 0x0008, | |
1048 | FW_PORT_CAP_SPEED_40G = 0x0010, | |
1049 | FW_PORT_CAP_SPEED_100G = 0x0020, | |
1050 | FW_PORT_CAP_FC_RX = 0x0040, | |
1051 | FW_PORT_CAP_FC_TX = 0x0080, | |
1052 | FW_PORT_CAP_ANEG = 0x0100, | |
1053 | FW_PORT_CAP_MDI_0 = 0x0200, | |
1054 | FW_PORT_CAP_MDI_1 = 0x0400, | |
1055 | FW_PORT_CAP_BEAN = 0x0800, | |
1056 | FW_PORT_CAP_PMA_LPBK = 0x1000, | |
1057 | FW_PORT_CAP_PCS_LPBK = 0x2000, | |
1058 | FW_PORT_CAP_PHYXS_LPBK = 0x4000, | |
1059 | FW_PORT_CAP_FAR_END_LPBK = 0x8000, | |
1060 | }; | |
1061 | ||
1062 | enum fw_port_mdi { | |
1063 | FW_PORT_MDI_UNCHANGED, | |
1064 | FW_PORT_MDI_AUTO, | |
1065 | FW_PORT_MDI_F_STRAIGHT, | |
1066 | FW_PORT_MDI_F_CROSSOVER | |
1067 | }; | |
1068 | ||
1069 | #define FW_PORT_MDI(x) ((x) << 9) | |
1070 | ||
1071 | enum fw_port_action { | |
1072 | FW_PORT_ACTION_L1_CFG = 0x0001, | |
1073 | FW_PORT_ACTION_L2_CFG = 0x0002, | |
1074 | FW_PORT_ACTION_GET_PORT_INFO = 0x0003, | |
1075 | FW_PORT_ACTION_L2_PPP_CFG = 0x0004, | |
1076 | FW_PORT_ACTION_L2_DCB_CFG = 0x0005, | |
1077 | FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, | |
1078 | FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, | |
1079 | FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, | |
1080 | FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, | |
1081 | FW_PORT_ACTION_L1_LPBK = 0x0021, | |
1082 | FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, | |
1083 | FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, | |
1084 | FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, | |
1085 | FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, | |
1086 | FW_PORT_ACTION_PHY_RESET = 0x0040, | |
1087 | FW_PORT_ACTION_PMA_RESET = 0x0041, | |
1088 | FW_PORT_ACTION_PCS_RESET = 0x0042, | |
1089 | FW_PORT_ACTION_PHYXS_RESET = 0x0043, | |
1090 | FW_PORT_ACTION_DTEXS_REEST = 0x0044, | |
1091 | FW_PORT_ACTION_AN_RESET = 0x0045 | |
1092 | }; | |
1093 | ||
1094 | enum fw_port_l2cfg_ctlbf { | |
1095 | FW_PORT_L2_CTLBF_OVLAN0 = 0x01, | |
1096 | FW_PORT_L2_CTLBF_OVLAN1 = 0x02, | |
1097 | FW_PORT_L2_CTLBF_OVLAN2 = 0x04, | |
1098 | FW_PORT_L2_CTLBF_OVLAN3 = 0x08, | |
1099 | FW_PORT_L2_CTLBF_IVLAN = 0x10, | |
1100 | FW_PORT_L2_CTLBF_TXIPG = 0x20 | |
1101 | }; | |
1102 | ||
1103 | enum fw_port_dcb_cfg { | |
1104 | FW_PORT_DCB_CFG_PG = 0x01, | |
1105 | FW_PORT_DCB_CFG_PFC = 0x02, | |
1106 | FW_PORT_DCB_CFG_APPL = 0x04 | |
1107 | }; | |
1108 | ||
1109 | enum fw_port_dcb_cfg_rc { | |
1110 | FW_PORT_DCB_CFG_SUCCESS = 0x0, | |
1111 | FW_PORT_DCB_CFG_ERROR = 0x1 | |
1112 | }; | |
1113 | ||
1114 | struct fw_port_cmd { | |
1115 | __be32 op_to_portid; | |
1116 | __be32 action_to_len16; | |
1117 | union fw_port { | |
1118 | struct fw_port_l1cfg { | |
1119 | __be32 rcap; | |
1120 | __be32 r; | |
1121 | } l1cfg; | |
1122 | struct fw_port_l2cfg { | |
1123 | __be16 ctlbf_to_ivlan0; | |
1124 | __be16 ivlantype; | |
1125 | __be32 txipg_pkd; | |
1126 | __be16 ovlan0mask; | |
1127 | __be16 ovlan0type; | |
1128 | __be16 ovlan1mask; | |
1129 | __be16 ovlan1type; | |
1130 | __be16 ovlan2mask; | |
1131 | __be16 ovlan2type; | |
1132 | __be16 ovlan3mask; | |
1133 | __be16 ovlan3type; | |
1134 | } l2cfg; | |
1135 | struct fw_port_info { | |
1136 | __be32 lstatus_to_modtype; | |
1137 | __be16 pcap; | |
1138 | __be16 acap; | |
1139 | } info; | |
1140 | struct fw_port_ppp { | |
1141 | __be32 pppen_to_ncsich; | |
1142 | __be32 r11; | |
1143 | } ppp; | |
1144 | struct fw_port_dcb { | |
1145 | __be16 cfg; | |
1146 | u8 up_map; | |
1147 | u8 sf_cfgrc; | |
1148 | __be16 prot_ix; | |
1149 | u8 pe7_to_pe0; | |
1150 | u8 numTCPFCs; | |
1151 | __be32 pgid0_to_pgid7; | |
1152 | __be32 numTCs_oui; | |
1153 | u8 pgpc[8]; | |
1154 | } dcb; | |
1155 | } u; | |
1156 | }; | |
1157 | ||
1158 | #define FW_PORT_CMD_READ (1U << 22) | |
1159 | ||
1160 | #define FW_PORT_CMD_PORTID(x) ((x) << 0) | |
1161 | #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf) | |
1162 | ||
1163 | #define FW_PORT_CMD_ACTION(x) ((x) << 16) | |
1164 | ||
1165 | #define FW_PORT_CMD_CTLBF(x) ((x) << 10) | |
1166 | #define FW_PORT_CMD_OVLAN3(x) ((x) << 7) | |
1167 | #define FW_PORT_CMD_OVLAN2(x) ((x) << 6) | |
1168 | #define FW_PORT_CMD_OVLAN1(x) ((x) << 5) | |
1169 | #define FW_PORT_CMD_OVLAN0(x) ((x) << 4) | |
1170 | #define FW_PORT_CMD_IVLAN0(x) ((x) << 3) | |
1171 | ||
1172 | #define FW_PORT_CMD_TXIPG(x) ((x) << 19) | |
1173 | ||
1174 | #define FW_PORT_CMD_LSTATUS (1U << 31) | |
1175 | #define FW_PORT_CMD_LSPEED(x) ((x) << 24) | |
1176 | #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f) | |
1177 | #define FW_PORT_CMD_TXPAUSE (1U << 23) | |
1178 | #define FW_PORT_CMD_RXPAUSE (1U << 22) | |
1179 | #define FW_PORT_CMD_MDIOCAP (1U << 21) | |
1180 | #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f) | |
1181 | #define FW_PORT_CMD_LPTXPAUSE (1U << 15) | |
1182 | #define FW_PORT_CMD_LPRXPAUSE (1U << 14) | |
1183 | #define FW_PORT_CMD_PTYPE_MASK 0x1f | |
1184 | #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK) | |
1185 | #define FW_PORT_CMD_MODTYPE_MASK 0x1f | |
1186 | #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK) | |
1187 | ||
1188 | #define FW_PORT_CMD_PPPEN(x) ((x) << 31) | |
1189 | #define FW_PORT_CMD_TPSRC(x) ((x) << 28) | |
1190 | #define FW_PORT_CMD_NCSISRC(x) ((x) << 24) | |
1191 | ||
1192 | #define FW_PORT_CMD_CH0(x) ((x) << 20) | |
1193 | #define FW_PORT_CMD_CH1(x) ((x) << 16) | |
1194 | #define FW_PORT_CMD_CH2(x) ((x) << 12) | |
1195 | #define FW_PORT_CMD_CH3(x) ((x) << 8) | |
1196 | #define FW_PORT_CMD_NCSICH(x) ((x) << 4) | |
1197 | ||
1198 | enum fw_port_type { | |
1199 | FW_PORT_TYPE_FIBER, | |
1200 | FW_PORT_TYPE_KX4, | |
1201 | FW_PORT_TYPE_BT_SGMII, | |
1202 | FW_PORT_TYPE_KX, | |
1203 | FW_PORT_TYPE_BT_XAUI, | |
1204 | FW_PORT_TYPE_KR, | |
1205 | FW_PORT_TYPE_CX4, | |
1206 | FW_PORT_TYPE_TWINAX, | |
1207 | ||
1208 | FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK | |
1209 | }; | |
1210 | ||
1211 | enum fw_port_module_type { | |
1212 | FW_PORT_MOD_TYPE_NA, | |
1213 | FW_PORT_MOD_TYPE_LR, | |
1214 | FW_PORT_MOD_TYPE_SR, | |
1215 | FW_PORT_MOD_TYPE_ER, | |
1216 | ||
1217 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK | |
1218 | }; | |
1219 | ||
1220 | /* port stats */ | |
1221 | #define FW_NUM_PORT_STATS 50 | |
1222 | #define FW_NUM_PORT_TX_STATS 23 | |
1223 | #define FW_NUM_PORT_RX_STATS 27 | |
1224 | ||
1225 | enum fw_port_stats_tx_index { | |
1226 | FW_STAT_TX_PORT_BYTES_IX, | |
1227 | FW_STAT_TX_PORT_FRAMES_IX, | |
1228 | FW_STAT_TX_PORT_BCAST_IX, | |
1229 | FW_STAT_TX_PORT_MCAST_IX, | |
1230 | FW_STAT_TX_PORT_UCAST_IX, | |
1231 | FW_STAT_TX_PORT_ERROR_IX, | |
1232 | FW_STAT_TX_PORT_64B_IX, | |
1233 | FW_STAT_TX_PORT_65B_127B_IX, | |
1234 | FW_STAT_TX_PORT_128B_255B_IX, | |
1235 | FW_STAT_TX_PORT_256B_511B_IX, | |
1236 | FW_STAT_TX_PORT_512B_1023B_IX, | |
1237 | FW_STAT_TX_PORT_1024B_1518B_IX, | |
1238 | FW_STAT_TX_PORT_1519B_MAX_IX, | |
1239 | FW_STAT_TX_PORT_DROP_IX, | |
1240 | FW_STAT_TX_PORT_PAUSE_IX, | |
1241 | FW_STAT_TX_PORT_PPP0_IX, | |
1242 | FW_STAT_TX_PORT_PPP1_IX, | |
1243 | FW_STAT_TX_PORT_PPP2_IX, | |
1244 | FW_STAT_TX_PORT_PPP3_IX, | |
1245 | FW_STAT_TX_PORT_PPP4_IX, | |
1246 | FW_STAT_TX_PORT_PPP5_IX, | |
1247 | FW_STAT_TX_PORT_PPP6_IX, | |
1248 | FW_STAT_TX_PORT_PPP7_IX | |
1249 | }; | |
1250 | ||
1251 | enum fw_port_stat_rx_index { | |
1252 | FW_STAT_RX_PORT_BYTES_IX, | |
1253 | FW_STAT_RX_PORT_FRAMES_IX, | |
1254 | FW_STAT_RX_PORT_BCAST_IX, | |
1255 | FW_STAT_RX_PORT_MCAST_IX, | |
1256 | FW_STAT_RX_PORT_UCAST_IX, | |
1257 | FW_STAT_RX_PORT_MTU_ERROR_IX, | |
1258 | FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, | |
1259 | FW_STAT_RX_PORT_CRC_ERROR_IX, | |
1260 | FW_STAT_RX_PORT_LEN_ERROR_IX, | |
1261 | FW_STAT_RX_PORT_SYM_ERROR_IX, | |
1262 | FW_STAT_RX_PORT_64B_IX, | |
1263 | FW_STAT_RX_PORT_65B_127B_IX, | |
1264 | FW_STAT_RX_PORT_128B_255B_IX, | |
1265 | FW_STAT_RX_PORT_256B_511B_IX, | |
1266 | FW_STAT_RX_PORT_512B_1023B_IX, | |
1267 | FW_STAT_RX_PORT_1024B_1518B_IX, | |
1268 | FW_STAT_RX_PORT_1519B_MAX_IX, | |
1269 | FW_STAT_RX_PORT_PAUSE_IX, | |
1270 | FW_STAT_RX_PORT_PPP0_IX, | |
1271 | FW_STAT_RX_PORT_PPP1_IX, | |
1272 | FW_STAT_RX_PORT_PPP2_IX, | |
1273 | FW_STAT_RX_PORT_PPP3_IX, | |
1274 | FW_STAT_RX_PORT_PPP4_IX, | |
1275 | FW_STAT_RX_PORT_PPP5_IX, | |
1276 | FW_STAT_RX_PORT_PPP6_IX, | |
1277 | FW_STAT_RX_PORT_PPP7_IX, | |
1278 | FW_STAT_RX_PORT_LESS_64B_IX | |
1279 | }; | |
1280 | ||
1281 | struct fw_port_stats_cmd { | |
1282 | __be32 op_to_portid; | |
1283 | __be32 retval_len16; | |
1284 | union fw_port_stats { | |
1285 | struct fw_port_stats_ctl { | |
1286 | u8 nstats_bg_bm; | |
1287 | u8 tx_ix; | |
1288 | __be16 r6; | |
1289 | __be32 r7; | |
1290 | __be64 stat0; | |
1291 | __be64 stat1; | |
1292 | __be64 stat2; | |
1293 | __be64 stat3; | |
1294 | __be64 stat4; | |
1295 | __be64 stat5; | |
1296 | } ctl; | |
1297 | struct fw_port_stats_all { | |
1298 | __be64 tx_bytes; | |
1299 | __be64 tx_frames; | |
1300 | __be64 tx_bcast; | |
1301 | __be64 tx_mcast; | |
1302 | __be64 tx_ucast; | |
1303 | __be64 tx_error; | |
1304 | __be64 tx_64b; | |
1305 | __be64 tx_65b_127b; | |
1306 | __be64 tx_128b_255b; | |
1307 | __be64 tx_256b_511b; | |
1308 | __be64 tx_512b_1023b; | |
1309 | __be64 tx_1024b_1518b; | |
1310 | __be64 tx_1519b_max; | |
1311 | __be64 tx_drop; | |
1312 | __be64 tx_pause; | |
1313 | __be64 tx_ppp0; | |
1314 | __be64 tx_ppp1; | |
1315 | __be64 tx_ppp2; | |
1316 | __be64 tx_ppp3; | |
1317 | __be64 tx_ppp4; | |
1318 | __be64 tx_ppp5; | |
1319 | __be64 tx_ppp6; | |
1320 | __be64 tx_ppp7; | |
1321 | __be64 rx_bytes; | |
1322 | __be64 rx_frames; | |
1323 | __be64 rx_bcast; | |
1324 | __be64 rx_mcast; | |
1325 | __be64 rx_ucast; | |
1326 | __be64 rx_mtu_error; | |
1327 | __be64 rx_mtu_crc_error; | |
1328 | __be64 rx_crc_error; | |
1329 | __be64 rx_len_error; | |
1330 | __be64 rx_sym_error; | |
1331 | __be64 rx_64b; | |
1332 | __be64 rx_65b_127b; | |
1333 | __be64 rx_128b_255b; | |
1334 | __be64 rx_256b_511b; | |
1335 | __be64 rx_512b_1023b; | |
1336 | __be64 rx_1024b_1518b; | |
1337 | __be64 rx_1519b_max; | |
1338 | __be64 rx_pause; | |
1339 | __be64 rx_ppp0; | |
1340 | __be64 rx_ppp1; | |
1341 | __be64 rx_ppp2; | |
1342 | __be64 rx_ppp3; | |
1343 | __be64 rx_ppp4; | |
1344 | __be64 rx_ppp5; | |
1345 | __be64 rx_ppp6; | |
1346 | __be64 rx_ppp7; | |
1347 | __be64 rx_less_64b; | |
1348 | __be64 rx_bg_drop; | |
1349 | __be64 rx_bg_trunc; | |
1350 | } all; | |
1351 | } u; | |
1352 | }; | |
1353 | ||
1354 | #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4) | |
1355 | #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0) | |
1356 | #define FW_PORT_STATS_CMD_TX(x) ((x) << 7) | |
1357 | #define FW_PORT_STATS_CMD_IX(x) ((x) << 0) | |
1358 | ||
1359 | /* port loopback stats */ | |
1360 | #define FW_NUM_LB_STATS 16 | |
1361 | enum fw_port_lb_stats_index { | |
1362 | FW_STAT_LB_PORT_BYTES_IX, | |
1363 | FW_STAT_LB_PORT_FRAMES_IX, | |
1364 | FW_STAT_LB_PORT_BCAST_IX, | |
1365 | FW_STAT_LB_PORT_MCAST_IX, | |
1366 | FW_STAT_LB_PORT_UCAST_IX, | |
1367 | FW_STAT_LB_PORT_ERROR_IX, | |
1368 | FW_STAT_LB_PORT_64B_IX, | |
1369 | FW_STAT_LB_PORT_65B_127B_IX, | |
1370 | FW_STAT_LB_PORT_128B_255B_IX, | |
1371 | FW_STAT_LB_PORT_256B_511B_IX, | |
1372 | FW_STAT_LB_PORT_512B_1023B_IX, | |
1373 | FW_STAT_LB_PORT_1024B_1518B_IX, | |
1374 | FW_STAT_LB_PORT_1519B_MAX_IX, | |
1375 | FW_STAT_LB_PORT_DROP_FRAMES_IX | |
1376 | }; | |
1377 | ||
1378 | struct fw_port_lb_stats_cmd { | |
1379 | __be32 op_to_lbport; | |
1380 | __be32 retval_len16; | |
1381 | union fw_port_lb_stats { | |
1382 | struct fw_port_lb_stats_ctl { | |
1383 | u8 nstats_bg_bm; | |
1384 | u8 ix_pkd; | |
1385 | __be16 r6; | |
1386 | __be32 r7; | |
1387 | __be64 stat0; | |
1388 | __be64 stat1; | |
1389 | __be64 stat2; | |
1390 | __be64 stat3; | |
1391 | __be64 stat4; | |
1392 | __be64 stat5; | |
1393 | } ctl; | |
1394 | struct fw_port_lb_stats_all { | |
1395 | __be64 tx_bytes; | |
1396 | __be64 tx_frames; | |
1397 | __be64 tx_bcast; | |
1398 | __be64 tx_mcast; | |
1399 | __be64 tx_ucast; | |
1400 | __be64 tx_error; | |
1401 | __be64 tx_64b; | |
1402 | __be64 tx_65b_127b; | |
1403 | __be64 tx_128b_255b; | |
1404 | __be64 tx_256b_511b; | |
1405 | __be64 tx_512b_1023b; | |
1406 | __be64 tx_1024b_1518b; | |
1407 | __be64 tx_1519b_max; | |
1408 | __be64 rx_lb_drop; | |
1409 | __be64 rx_lb_trunc; | |
1410 | } all; | |
1411 | } u; | |
1412 | }; | |
1413 | ||
1414 | #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0) | |
1415 | #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4) | |
1416 | #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0) | |
1417 | #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0) | |
1418 | ||
1419 | struct fw_rss_ind_tbl_cmd { | |
1420 | __be32 op_to_viid; | |
1421 | #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0) | |
1422 | __be32 retval_len16; | |
1423 | __be16 niqid; | |
1424 | __be16 startidx; | |
1425 | __be32 r3; | |
1426 | __be32 iq0_to_iq2; | |
1427 | #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20) | |
1428 | #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10) | |
1429 | #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0) | |
1430 | __be32 iq3_to_iq5; | |
1431 | __be32 iq6_to_iq8; | |
1432 | __be32 iq9_to_iq11; | |
1433 | __be32 iq12_to_iq14; | |
1434 | __be32 iq15_to_iq17; | |
1435 | __be32 iq18_to_iq20; | |
1436 | __be32 iq21_to_iq23; | |
1437 | __be32 iq24_to_iq26; | |
1438 | __be32 iq27_to_iq29; | |
1439 | __be32 iq30_iq31; | |
1440 | __be32 r15_lo; | |
1441 | }; | |
1442 | ||
1443 | struct fw_rss_glb_config_cmd { | |
1444 | __be32 op_to_write; | |
1445 | __be32 retval_len16; | |
1446 | union fw_rss_glb_config { | |
1447 | struct fw_rss_glb_config_manual { | |
1448 | __be32 mode_pkd; | |
1449 | __be32 r3; | |
1450 | __be64 r4; | |
1451 | __be64 r5; | |
1452 | } manual; | |
1453 | struct fw_rss_glb_config_basicvirtual { | |
1454 | __be32 mode_pkd; | |
1455 | __be32 synmapen_to_hashtoeplitz; | |
1456 | #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8) | |
1457 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7) | |
1458 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6) | |
1459 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5) | |
1460 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4) | |
1461 | #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3) | |
1462 | #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2) | |
1463 | #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1) | |
1464 | #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0) | |
1465 | __be64 r8; | |
1466 | __be64 r9; | |
1467 | } basicvirtual; | |
1468 | } u; | |
1469 | }; | |
1470 | ||
1471 | #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28) | |
1472 | ||
1473 | #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 | |
1474 | #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 | |
1475 | ||
1476 | struct fw_rss_vi_config_cmd { | |
1477 | __be32 op_to_viid; | |
1478 | #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) | |
1479 | __be32 retval_len16; | |
1480 | union fw_rss_vi_config { | |
1481 | struct fw_rss_vi_config_manual { | |
1482 | __be64 r3; | |
1483 | __be64 r4; | |
1484 | __be64 r5; | |
1485 | } manual; | |
1486 | struct fw_rss_vi_config_basicvirtual { | |
1487 | __be32 r6; | |
1488 | __be32 defaultq_to_ip4udpen; | |
1489 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16) | |
1490 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4) | |
1491 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3) | |
1492 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2) | |
1493 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1) | |
1494 | #define FW_RSS_VI_CONFIG_CMD_IP4UDPEN (1U << 0) | |
1495 | __be64 r9; | |
1496 | __be64 r10; | |
1497 | } basicvirtual; | |
1498 | } u; | |
1499 | }; | |
1500 | ||
1501 | enum fw_error_type { | |
1502 | FW_ERROR_TYPE_EXCEPTION = 0x0, | |
1503 | FW_ERROR_TYPE_HWMODULE = 0x1, | |
1504 | FW_ERROR_TYPE_WR = 0x2, | |
1505 | FW_ERROR_TYPE_ACL = 0x3, | |
1506 | }; | |
1507 | ||
1508 | struct fw_error_cmd { | |
1509 | __be32 op_to_type; | |
1510 | __be32 len16_pkd; | |
1511 | union fw_error { | |
1512 | struct fw_error_exception { | |
1513 | __be32 info[6]; | |
1514 | } exception; | |
1515 | struct fw_error_hwmodule { | |
1516 | __be32 regaddr; | |
1517 | __be32 regval; | |
1518 | } hwmodule; | |
1519 | struct fw_error_wr { | |
1520 | __be16 cidx; | |
1521 | __be16 pfn_vfn; | |
1522 | __be32 eqid; | |
1523 | u8 wrhdr[16]; | |
1524 | } wr; | |
1525 | struct fw_error_acl { | |
1526 | __be16 cidx; | |
1527 | __be16 pfn_vfn; | |
1528 | __be32 eqid; | |
1529 | __be16 mv_pkd; | |
1530 | u8 val[6]; | |
1531 | __be64 r4; | |
1532 | } acl; | |
1533 | } u; | |
1534 | }; | |
1535 | ||
1536 | struct fw_debug_cmd { | |
1537 | __be32 op_type; | |
1538 | #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff) | |
1539 | __be32 len16_pkd; | |
1540 | union fw_debug { | |
1541 | struct fw_debug_assert { | |
1542 | __be32 fcid; | |
1543 | __be32 line; | |
1544 | __be32 x; | |
1545 | __be32 y; | |
1546 | u8 filename_0_7[8]; | |
1547 | u8 filename_8_15[8]; | |
1548 | __be64 r3; | |
1549 | } assert; | |
1550 | struct fw_debug_prt { | |
1551 | __be16 dprtstridx; | |
1552 | __be16 r3[3]; | |
1553 | __be32 dprtstrparam0; | |
1554 | __be32 dprtstrparam1; | |
1555 | __be32 dprtstrparam2; | |
1556 | __be32 dprtstrparam3; | |
1557 | } prt; | |
1558 | } u; | |
1559 | }; | |
1560 | ||
1561 | struct fw_hdr { | |
1562 | u8 ver; | |
1563 | u8 reserved1; | |
1564 | __be16 len512; /* bin length in units of 512-bytes */ | |
1565 | __be32 fw_ver; /* firmware version */ | |
1566 | __be32 tp_microcode_ver; | |
1567 | u8 intfver_nic; | |
1568 | u8 intfver_vnic; | |
1569 | u8 intfver_ofld; | |
1570 | u8 intfver_ri; | |
1571 | u8 intfver_iscsipdu; | |
1572 | u8 intfver_iscsi; | |
1573 | u8 intfver_fcoe; | |
1574 | u8 reserved2; | |
1575 | __be32 reserved3[27]; | |
1576 | }; | |
1577 | ||
1578 | #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff) | |
1579 | #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff) | |
1580 | #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) | |
1581 | #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) | |
1582 | #endif /* _T4FW_INTERFACE_H_ */ |