Commit | Line | Data |
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a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
59eae1fa BD |
47 | #define CARDNAME "dm9000" |
48 | #define DRV_VERSION "1.31" | |
a1365275 | 49 | |
f40d24d9 AL |
50 | #ifdef CONFIG_BLACKFIN |
51 | #define readsb insb | |
52 | #define readsw insw | |
53 | #define readsl insl | |
54 | #define writesb outsb | |
55 | #define writesw outsw | |
56 | #define writesl outsl | |
f40d24d9 AL |
57 | #endif |
58 | ||
a1365275 SH |
59 | /* |
60 | * Transmit timeout, default 5 seconds. | |
61 | */ | |
62 | static int watchdog = 5000; | |
63 | module_param(watchdog, int, 0400); | |
64 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
65 | ||
9a2f037c BD |
66 | /* DM9000 register address locking. |
67 | * | |
68 | * The DM9000 uses an address register to control where data written | |
69 | * to the data register goes. This means that the address register | |
70 | * must be preserved over interrupts or similar calls. | |
71 | * | |
72 | * During interrupt and other critical calls, a spinlock is used to | |
73 | * protect the system, but the calls themselves save the address | |
74 | * in the address register in case they are interrupting another | |
75 | * access to the device. | |
76 | * | |
77 | * For general accesses a lock is provided so that calls which are | |
78 | * allowed to sleep are serialised so that the address register does | |
79 | * not need to be saved. This lock also serves to serialise access | |
80 | * to the EEPROM and PHY access registers which are shared between | |
81 | * these two devices. | |
82 | */ | |
83 | ||
6d406b3c BD |
84 | /* The driver supports the original DM9000E, and now the two newer |
85 | * devices, DM9000A and DM9000B. | |
86 | */ | |
87 | ||
88 | enum dm9000_type { | |
89 | TYPE_DM9000E, /* original DM9000 */ | |
90 | TYPE_DM9000A, | |
91 | TYPE_DM9000B | |
92 | }; | |
93 | ||
a1365275 SH |
94 | /* Structure/enum declaration ------------------------------- */ |
95 | typedef struct board_info { | |
96 | ||
59eae1fa BD |
97 | void __iomem *io_addr; /* Register I/O base address */ |
98 | void __iomem *io_data; /* Data I/O address */ | |
99 | u16 irq; /* IRQ */ | |
a1365275 | 100 | |
59eae1fa BD |
101 | u16 tx_pkt_cnt; |
102 | u16 queue_pkt_len; | |
103 | u16 queue_start_addr; | |
104 | u16 dbug_cnt; | |
105 | u8 io_mode; /* 0:word, 2:byte */ | |
106 | u8 phy_addr; | |
107 | u8 imr_all; | |
108 | ||
109 | unsigned int flags; | |
110 | unsigned int in_suspend :1; | |
111 | int debug_level; | |
a1365275 | 112 | |
6d406b3c | 113 | enum dm9000_type type; |
5b2b4ff0 | 114 | |
a1365275 SH |
115 | void (*inblk)(void __iomem *port, void *data, int length); |
116 | void (*outblk)(void __iomem *port, void *data, int length); | |
117 | void (*dumpblk)(void __iomem *port, int length); | |
118 | ||
a76836f9 BD |
119 | struct device *dev; /* parent device */ |
120 | ||
a1365275 SH |
121 | struct resource *addr_res; /* resources found */ |
122 | struct resource *data_res; | |
123 | struct resource *addr_req; /* resources requested */ | |
124 | struct resource *data_req; | |
125 | struct resource *irq_res; | |
126 | ||
9a2f037c BD |
127 | struct mutex addr_lock; /* phy and eeprom access lock */ |
128 | ||
8f5bf5f2 BD |
129 | struct delayed_work phy_poll; |
130 | struct net_device *ndev; | |
131 | ||
59eae1fa | 132 | spinlock_t lock; |
a1365275 SH |
133 | |
134 | struct mii_if_info mii; | |
59eae1fa | 135 | u32 msg_enable; |
a1365275 SH |
136 | } board_info_t; |
137 | ||
5b2b4ff0 BD |
138 | /* debug code */ |
139 | ||
140 | #define dm9000_dbg(db, lev, msg...) do { \ | |
141 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
142 | (lev) < db->debug_level) { \ | |
143 | dev_dbg(db->dev, msg); \ | |
144 | } \ | |
145 | } while (0) | |
146 | ||
7da99859 BD |
147 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
148 | { | |
149 | return dev->priv; | |
150 | } | |
151 | ||
a1365275 SH |
152 | /* DM9000 network board routine ---------------------------- */ |
153 | ||
154 | static void | |
155 | dm9000_reset(board_info_t * db) | |
156 | { | |
a76836f9 BD |
157 | dev_dbg(db->dev, "resetting device\n"); |
158 | ||
a1365275 SH |
159 | /* RESET device */ |
160 | writeb(DM9000_NCR, db->io_addr); | |
161 | udelay(200); | |
162 | writeb(NCR_RST, db->io_data); | |
163 | udelay(200); | |
164 | } | |
165 | ||
166 | /* | |
167 | * Read a byte from I/O port | |
168 | */ | |
169 | static u8 | |
170 | ior(board_info_t * db, int reg) | |
171 | { | |
172 | writeb(reg, db->io_addr); | |
173 | return readb(db->io_data); | |
174 | } | |
175 | ||
176 | /* | |
177 | * Write a byte to I/O port | |
178 | */ | |
179 | ||
180 | static void | |
181 | iow(board_info_t * db, int reg, int value) | |
182 | { | |
183 | writeb(reg, db->io_addr); | |
184 | writeb(value, db->io_data); | |
185 | } | |
186 | ||
187 | /* routines for sending block to chip */ | |
188 | ||
189 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
190 | { | |
191 | writesb(reg, data, count); | |
192 | } | |
193 | ||
194 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
195 | { | |
196 | writesw(reg, data, (count+1) >> 1); | |
197 | } | |
198 | ||
199 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
200 | { | |
201 | writesl(reg, data, (count+3) >> 2); | |
202 | } | |
203 | ||
204 | /* input block from chip to memory */ | |
205 | ||
206 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
207 | { | |
5f6b5517 | 208 | readsb(reg, data, count); |
a1365275 SH |
209 | } |
210 | ||
211 | ||
212 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
213 | { | |
214 | readsw(reg, data, (count+1) >> 1); | |
215 | } | |
216 | ||
217 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
218 | { | |
219 | readsl(reg, data, (count+3) >> 2); | |
220 | } | |
221 | ||
222 | /* dump block from chip to null */ | |
223 | ||
224 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
225 | { | |
226 | int i; | |
227 | int tmp; | |
228 | ||
229 | for (i = 0; i < count; i++) | |
230 | tmp = readb(reg); | |
231 | } | |
232 | ||
233 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
234 | { | |
235 | int i; | |
236 | int tmp; | |
237 | ||
238 | count = (count + 1) >> 1; | |
239 | ||
240 | for (i = 0; i < count; i++) | |
241 | tmp = readw(reg); | |
242 | } | |
243 | ||
244 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
245 | { | |
246 | int i; | |
247 | int tmp; | |
248 | ||
249 | count = (count + 3) >> 2; | |
250 | ||
251 | for (i = 0; i < count; i++) | |
252 | tmp = readl(reg); | |
253 | } | |
254 | ||
255 | /* dm9000_set_io | |
256 | * | |
257 | * select the specified set of io routines to use with the | |
258 | * device | |
259 | */ | |
260 | ||
261 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
262 | { | |
263 | /* use the size of the data resource to work out what IO | |
264 | * routines we want to use | |
265 | */ | |
266 | ||
267 | switch (byte_width) { | |
268 | case 1: | |
269 | db->dumpblk = dm9000_dumpblk_8bit; | |
270 | db->outblk = dm9000_outblk_8bit; | |
271 | db->inblk = dm9000_inblk_8bit; | |
272 | break; | |
273 | ||
a1365275 SH |
274 | |
275 | case 3: | |
a76836f9 BD |
276 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
277 | case 2: | |
a1365275 SH |
278 | db->dumpblk = dm9000_dumpblk_16bit; |
279 | db->outblk = dm9000_outblk_16bit; | |
280 | db->inblk = dm9000_inblk_16bit; | |
281 | break; | |
282 | ||
283 | case 4: | |
284 | default: | |
285 | db->dumpblk = dm9000_dumpblk_32bit; | |
286 | db->outblk = dm9000_outblk_32bit; | |
287 | db->inblk = dm9000_inblk_32bit; | |
288 | break; | |
289 | } | |
290 | } | |
291 | ||
8f5bf5f2 BD |
292 | static void dm9000_schedule_poll(board_info_t *db) |
293 | { | |
6d406b3c BD |
294 | if (db->type == TYPE_DM9000E) |
295 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
8f5bf5f2 | 296 | } |
a1365275 | 297 | |
f8d79e79 BD |
298 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
299 | { | |
300 | board_info_t *dm = to_dm9000_board(dev); | |
301 | ||
302 | if (!netif_running(dev)) | |
303 | return -EINVAL; | |
304 | ||
305 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
306 | } | |
307 | ||
308 | static unsigned int | |
309 | dm9000_read_locked(board_info_t *db, int reg) | |
a1365275 | 310 | { |
a1365275 | 311 | unsigned long flags; |
f8d79e79 | 312 | unsigned int ret; |
a1365275 | 313 | |
f8d79e79 BD |
314 | spin_lock_irqsave(&db->lock, flags); |
315 | ret = ior(db, reg); | |
316 | spin_unlock_irqrestore(&db->lock, flags); | |
a1365275 | 317 | |
f8d79e79 BD |
318 | return ret; |
319 | } | |
a1365275 | 320 | |
f8d79e79 BD |
321 | static int dm9000_wait_eeprom(board_info_t *db) |
322 | { | |
323 | unsigned int status; | |
324 | int timeout = 8; /* wait max 8msec */ | |
325 | ||
326 | /* The DM9000 data sheets say we should be able to | |
327 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
328 | * operation. From testing several chips, this bit | |
329 | * does not seem to work. | |
330 | * | |
331 | * We attempt to use the bit, but fall back to the | |
332 | * timeout (which is why we do not return an error | |
333 | * on expiry) to say that the EEPROM operation has | |
334 | * completed. | |
335 | */ | |
336 | ||
337 | while (1) { | |
338 | status = dm9000_read_locked(db, DM9000_EPCR); | |
339 | ||
340 | if ((status & EPCR_ERRE) == 0) | |
341 | break; | |
342 | ||
2fcf06ca BD |
343 | msleep(1); |
344 | ||
f8d79e79 BD |
345 | if (timeout-- < 0) { |
346 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
347 | break; | |
348 | } | |
349 | } | |
350 | ||
351 | return 0; | |
a1365275 SH |
352 | } |
353 | ||
2fd0e33f | 354 | /* |
f8d79e79 | 355 | * Read a word data from EEPROM |
2fd0e33f | 356 | */ |
f8d79e79 BD |
357 | static void |
358 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) | |
2fd0e33f | 359 | { |
f8d79e79 BD |
360 | unsigned long flags; |
361 | ||
362 | if (db->flags & DM9000_PLATF_NO_EEPROM) { | |
363 | to[0] = 0xff; | |
364 | to[1] = 0xff; | |
365 | return; | |
366 | } | |
367 | ||
368 | mutex_lock(&db->addr_lock); | |
369 | ||
370 | spin_lock_irqsave(&db->lock, flags); | |
371 | ||
372 | iow(db, DM9000_EPAR, offset); | |
373 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
374 | ||
375 | spin_unlock_irqrestore(&db->lock, flags); | |
376 | ||
377 | dm9000_wait_eeprom(db); | |
378 | ||
379 | /* delay for at-least 150uS */ | |
380 | msleep(1); | |
381 | ||
382 | spin_lock_irqsave(&db->lock, flags); | |
383 | ||
384 | iow(db, DM9000_EPCR, 0x0); | |
385 | ||
386 | to[0] = ior(db, DM9000_EPDRL); | |
387 | to[1] = ior(db, DM9000_EPDRH); | |
388 | ||
389 | spin_unlock_irqrestore(&db->lock, flags); | |
390 | ||
391 | mutex_unlock(&db->addr_lock); | |
2fd0e33f | 392 | } |
a1365275 | 393 | |
f8d79e79 BD |
394 | /* |
395 | * Write a word data to SROM | |
396 | */ | |
397 | static void | |
398 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) | |
f42d8aea | 399 | { |
f8d79e79 | 400 | unsigned long flags; |
f42d8aea | 401 | |
f8d79e79 BD |
402 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
403 | return; | |
f42d8aea | 404 | |
f8d79e79 BD |
405 | mutex_lock(&db->addr_lock); |
406 | ||
407 | spin_lock_irqsave(&db->lock, flags); | |
408 | iow(db, DM9000_EPAR, offset); | |
409 | iow(db, DM9000_EPDRH, data[1]); | |
410 | iow(db, DM9000_EPDRL, data[0]); | |
411 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
412 | spin_unlock_irqrestore(&db->lock, flags); | |
413 | ||
414 | dm9000_wait_eeprom(db); | |
415 | ||
416 | mdelay(1); /* wait at least 150uS to clear */ | |
417 | ||
418 | spin_lock_irqsave(&db->lock, flags); | |
419 | iow(db, DM9000_EPCR, 0); | |
420 | spin_unlock_irqrestore(&db->lock, flags); | |
421 | ||
422 | mutex_unlock(&db->addr_lock); | |
f42d8aea BD |
423 | } |
424 | ||
7da99859 BD |
425 | /* ethtool ops */ |
426 | ||
427 | static void dm9000_get_drvinfo(struct net_device *dev, | |
428 | struct ethtool_drvinfo *info) | |
429 | { | |
430 | board_info_t *dm = to_dm9000_board(dev); | |
431 | ||
432 | strcpy(info->driver, CARDNAME); | |
433 | strcpy(info->version, DRV_VERSION); | |
434 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
435 | } | |
436 | ||
e662ee02 BD |
437 | static u32 dm9000_get_msglevel(struct net_device *dev) |
438 | { | |
439 | board_info_t *dm = to_dm9000_board(dev); | |
440 | ||
441 | return dm->msg_enable; | |
442 | } | |
443 | ||
444 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
445 | { | |
446 | board_info_t *dm = to_dm9000_board(dev); | |
447 | ||
448 | dm->msg_enable = value; | |
449 | } | |
450 | ||
7da99859 BD |
451 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
452 | { | |
453 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 454 | |
7da99859 | 455 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
456 | return 0; |
457 | } | |
458 | ||
459 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
460 | { | |
461 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 462 | |
9a2f037c | 463 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
464 | } |
465 | ||
466 | static int dm9000_nway_reset(struct net_device *dev) | |
467 | { | |
468 | board_info_t *dm = to_dm9000_board(dev); | |
469 | return mii_nway_restart(&dm->mii); | |
470 | } | |
471 | ||
472 | static u32 dm9000_get_link(struct net_device *dev) | |
473 | { | |
474 | board_info_t *dm = to_dm9000_board(dev); | |
aa1eb452 BD |
475 | u32 ret; |
476 | ||
477 | if (dm->flags & DM9000_PLATF_EXT_PHY) | |
478 | ret = mii_link_ok(&dm->mii); | |
479 | else | |
480 | ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; | |
481 | ||
482 | return ret; | |
7da99859 BD |
483 | } |
484 | ||
29d52e54 BD |
485 | #define DM_EEPROM_MAGIC (0x444D394B) |
486 | ||
487 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
488 | { | |
489 | return 128; | |
490 | } | |
491 | ||
492 | static int dm9000_get_eeprom(struct net_device *dev, | |
493 | struct ethtool_eeprom *ee, u8 *data) | |
494 | { | |
495 | board_info_t *dm = to_dm9000_board(dev); | |
496 | int offset = ee->offset; | |
497 | int len = ee->len; | |
498 | int i; | |
499 | ||
500 | /* EEPROM access is aligned to two bytes */ | |
501 | ||
502 | if ((len & 1) != 0 || (offset & 1) != 0) | |
503 | return -EINVAL; | |
504 | ||
bb44fb70 BD |
505 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
506 | return -ENOENT; | |
507 | ||
29d52e54 BD |
508 | ee->magic = DM_EEPROM_MAGIC; |
509 | ||
510 | for (i = 0; i < len; i += 2) | |
511 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | static int dm9000_set_eeprom(struct net_device *dev, | |
517 | struct ethtool_eeprom *ee, u8 *data) | |
518 | { | |
519 | board_info_t *dm = to_dm9000_board(dev); | |
520 | int offset = ee->offset; | |
521 | int len = ee->len; | |
522 | int i; | |
523 | ||
524 | /* EEPROM access is aligned to two bytes */ | |
525 | ||
526 | if ((len & 1) != 0 || (offset & 1) != 0) | |
527 | return -EINVAL; | |
528 | ||
bb44fb70 BD |
529 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
530 | return -ENOENT; | |
531 | ||
29d52e54 BD |
532 | if (ee->magic != DM_EEPROM_MAGIC) |
533 | return -EINVAL; | |
534 | ||
535 | for (i = 0; i < len; i += 2) | |
536 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
7da99859 BD |
541 | static const struct ethtool_ops dm9000_ethtool_ops = { |
542 | .get_drvinfo = dm9000_get_drvinfo, | |
543 | .get_settings = dm9000_get_settings, | |
544 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
545 | .get_msglevel = dm9000_get_msglevel, |
546 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
547 | .nway_reset = dm9000_nway_reset, |
548 | .get_link = dm9000_get_link, | |
29d52e54 BD |
549 | .get_eeprom_len = dm9000_get_eeprom_len, |
550 | .get_eeprom = dm9000_get_eeprom, | |
551 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
552 | }; |
553 | ||
f8dd0ecb BD |
554 | static void dm9000_show_carrier(board_info_t *db, |
555 | unsigned carrier, unsigned nsr) | |
556 | { | |
557 | struct net_device *ndev = db->ndev; | |
558 | unsigned ncr = dm9000_read_locked(db, DM9000_NCR); | |
559 | ||
560 | if (carrier) | |
561 | dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", | |
562 | ndev->name, (nsr & NSR_SPEED) ? 10 : 100, | |
563 | (ncr & NCR_FDX) ? "full" : "half"); | |
564 | else | |
565 | dev_info(db->dev, "%s: link down\n", ndev->name); | |
566 | } | |
567 | ||
8f5bf5f2 BD |
568 | static void |
569 | dm9000_poll_work(struct work_struct *w) | |
570 | { | |
571 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
572 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
f8dd0ecb BD |
573 | struct net_device *ndev = db->ndev; |
574 | ||
575 | if (db->flags & DM9000_PLATF_SIMPLE_PHY && | |
576 | !(db->flags & DM9000_PLATF_EXT_PHY)) { | |
577 | unsigned nsr = dm9000_read_locked(db, DM9000_NSR); | |
578 | unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; | |
579 | unsigned new_carrier; | |
8f5bf5f2 | 580 | |
f8dd0ecb BD |
581 | new_carrier = (nsr & NSR_LINKST) ? 1 : 0; |
582 | ||
583 | if (old_carrier != new_carrier) { | |
584 | if (netif_msg_link(db)) | |
585 | dm9000_show_carrier(db, new_carrier, nsr); | |
586 | ||
587 | if (!new_carrier) | |
588 | netif_carrier_off(ndev); | |
589 | else | |
590 | netif_carrier_on(ndev); | |
591 | } | |
592 | } else | |
593 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
8f5bf5f2 | 594 | |
f8dd0ecb | 595 | if (netif_running(ndev)) |
8f5bf5f2 BD |
596 | dm9000_schedule_poll(db); |
597 | } | |
7da99859 | 598 | |
a1365275 SH |
599 | /* dm9000_release_board |
600 | * | |
601 | * release a board, and any mapped resources | |
602 | */ | |
603 | ||
604 | static void | |
605 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
606 | { | |
a1365275 SH |
607 | /* unmap our resources */ |
608 | ||
609 | iounmap(db->io_addr); | |
610 | iounmap(db->io_data); | |
611 | ||
612 | /* release the resources */ | |
613 | ||
9088fa4f BD |
614 | release_resource(db->data_req); |
615 | kfree(db->data_req); | |
a1365275 | 616 | |
9088fa4f BD |
617 | release_resource(db->addr_req); |
618 | kfree(db->addr_req); | |
a1365275 SH |
619 | } |
620 | ||
6d406b3c BD |
621 | static unsigned char dm9000_type_to_char(enum dm9000_type type) |
622 | { | |
623 | switch (type) { | |
624 | case TYPE_DM9000E: return 'e'; | |
625 | case TYPE_DM9000A: return 'a'; | |
626 | case TYPE_DM9000B: return 'b'; | |
627 | } | |
628 | ||
629 | return '?'; | |
630 | } | |
631 | ||
a1365275 | 632 | /* |
f8d79e79 | 633 | * Set DM9000 multicast address |
a1365275 | 634 | */ |
f8d79e79 BD |
635 | static void |
636 | dm9000_hash_table(struct net_device *dev) | |
a1365275 | 637 | { |
f8d79e79 BD |
638 | board_info_t *db = (board_info_t *) dev->priv; |
639 | struct dev_mc_list *mcptr = dev->mc_list; | |
640 | int mc_cnt = dev->mc_count; | |
641 | int i, oft; | |
642 | u32 hash_val; | |
643 | u16 hash_table[4]; | |
644 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; | |
645 | unsigned long flags; | |
a1365275 | 646 | |
f8d79e79 | 647 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 648 | |
f8d79e79 | 649 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 650 | |
f8d79e79 BD |
651 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
652 | iow(db, oft, dev->dev_addr[i]); | |
a1365275 | 653 | |
f8d79e79 BD |
654 | /* Clear Hash Table */ |
655 | for (i = 0; i < 4; i++) | |
656 | hash_table[i] = 0x0; | |
a76836f9 | 657 | |
f8d79e79 BD |
658 | /* broadcast address */ |
659 | hash_table[3] = 0x8000; | |
9ef9ac51 | 660 | |
f8d79e79 BD |
661 | if (dev->flags & IFF_PROMISC) |
662 | rcr |= RCR_PRMSC; | |
8f5bf5f2 | 663 | |
f8d79e79 BD |
664 | if (dev->flags & IFF_ALLMULTI) |
665 | rcr |= RCR_ALL; | |
08c3f57c | 666 | |
f8d79e79 BD |
667 | /* the multicast address in Hash Table : 64 bits */ |
668 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
669 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; | |
670 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
08c3f57c LP |
671 | } |
672 | ||
f8d79e79 BD |
673 | /* Write the hash table to MAC MD table */ |
674 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { | |
675 | iow(db, oft++, hash_table[i]); | |
676 | iow(db, oft++, hash_table[i] >> 8); | |
08c3f57c LP |
677 | } |
678 | ||
f8d79e79 BD |
679 | iow(db, DM9000_RCR, rcr); |
680 | spin_unlock_irqrestore(&db->lock, flags); | |
681 | } | |
08c3f57c | 682 | |
f8d79e79 BD |
683 | /* |
684 | * Initilize dm9000 board | |
685 | */ | |
686 | static void | |
687 | dm9000_init_dm9000(struct net_device *dev) | |
688 | { | |
689 | board_info_t *db = dev->priv; | |
690 | unsigned int imr; | |
08c3f57c | 691 | |
f8d79e79 | 692 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
08c3f57c | 693 | |
f8d79e79 BD |
694 | /* I/O mode */ |
695 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
08c3f57c | 696 | |
f8d79e79 BD |
697 | /* GPIO0 on pre-activate PHY */ |
698 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
699 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
700 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
08c3f57c | 701 | |
f8d79e79 BD |
702 | if (db->flags & DM9000_PLATF_EXT_PHY) |
703 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
33ba5091 | 704 | |
a1365275 SH |
705 | /* Program operating register */ |
706 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
707 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
708 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
709 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
710 | /* clear TX status */ | |
711 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
712 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
713 | ||
714 | /* Set address filter table */ | |
715 | dm9000_hash_table(dev); | |
716 | ||
6d406b3c BD |
717 | imr = IMR_PAR | IMR_PTM | IMR_PRM; |
718 | if (db->type != TYPE_DM9000E) | |
719 | imr |= IMR_LNKCHNG; | |
720 | ||
721 | db->imr_all = imr; | |
722 | ||
a1365275 | 723 | /* Enable TX/RX interrupt mask */ |
6d406b3c | 724 | iow(db, DM9000_IMR, imr); |
a1365275 SH |
725 | |
726 | /* Init Driver variable */ | |
727 | db->tx_pkt_cnt = 0; | |
728 | db->queue_pkt_len = 0; | |
729 | dev->trans_start = 0; | |
a1365275 SH |
730 | } |
731 | ||
f8d79e79 BD |
732 | /* Our watchdog timed out. Called by the networking layer */ |
733 | static void dm9000_timeout(struct net_device *dev) | |
734 | { | |
735 | board_info_t *db = (board_info_t *) dev->priv; | |
736 | u8 reg_save; | |
737 | unsigned long flags; | |
738 | ||
739 | /* Save previous register address */ | |
740 | reg_save = readb(db->io_addr); | |
741 | spin_lock_irqsave(&db->lock, flags); | |
742 | ||
743 | netif_stop_queue(dev); | |
744 | dm9000_reset(db); | |
745 | dm9000_init_dm9000(dev); | |
746 | /* We can accept TX packets again */ | |
747 | dev->trans_start = jiffies; | |
748 | netif_wake_queue(dev); | |
749 | ||
750 | /* Restore previous register address */ | |
751 | writeb(reg_save, db->io_addr); | |
752 | spin_unlock_irqrestore(&db->lock, flags); | |
753 | } | |
754 | ||
a1365275 SH |
755 | /* |
756 | * Hardware start transmission. | |
757 | * Send a packet to media from the upper layer. | |
758 | */ | |
759 | static int | |
760 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
761 | { | |
c46ac946 | 762 | unsigned long flags; |
59eae1fa | 763 | board_info_t *db = dev->priv; |
a1365275 | 764 | |
5b2b4ff0 | 765 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
766 | |
767 | if (db->tx_pkt_cnt > 1) | |
768 | return 1; | |
769 | ||
c46ac946 | 770 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
771 | |
772 | /* Move data to DM9000 TX RAM */ | |
773 | writeb(DM9000_MWCMD, db->io_addr); | |
774 | ||
775 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 776 | dev->stats.tx_bytes += skb->len; |
a1365275 | 777 | |
c46ac946 | 778 | db->tx_pkt_cnt++; |
a1365275 | 779 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 780 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 781 | /* Set TX length to DM9000 */ |
073d3f46 BD |
782 | iow(db, DM9000_TXPLL, skb->len); |
783 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
784 | |
785 | /* Issue TX polling command */ | |
786 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
787 | ||
788 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
789 | } else { |
790 | /* Second packet */ | |
a1365275 | 791 | db->queue_pkt_len = skb->len; |
c46ac946 | 792 | netif_stop_queue(dev); |
a1365275 SH |
793 | } |
794 | ||
c46ac946 FW |
795 | spin_unlock_irqrestore(&db->lock, flags); |
796 | ||
a1365275 SH |
797 | /* free this SKB */ |
798 | dev_kfree_skb(skb); | |
799 | ||
a1365275 SH |
800 | return 0; |
801 | } | |
802 | ||
a1365275 | 803 | /* |
f8d79e79 BD |
804 | * DM9000 interrupt handler |
805 | * receive the packet to upper layer, free the transmitted packet | |
a1365275 | 806 | */ |
f8d79e79 BD |
807 | |
808 | static void dm9000_tx_done(struct net_device *dev, board_info_t *db) | |
a1365275 | 809 | { |
f8d79e79 | 810 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ |
a1365275 | 811 | |
f8d79e79 BD |
812 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { |
813 | /* One packet sent complete */ | |
814 | db->tx_pkt_cnt--; | |
815 | dev->stats.tx_packets++; | |
a1365275 | 816 | |
f8d79e79 BD |
817 | if (netif_msg_tx_done(db)) |
818 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
c991d168 | 819 | |
a1365275 SH |
820 | /* Queue packet check & send */ |
821 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
822 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
823 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
824 | iow(db, DM9000_TCR, TCR_TXREQ); |
825 | dev->trans_start = jiffies; | |
826 | } | |
827 | netif_wake_queue(dev); | |
828 | } | |
829 | } | |
830 | ||
a1365275 | 831 | struct dm9000_rxhdr { |
93116573 BD |
832 | u8 RxPktReady; |
833 | u8 RxStatus; | |
8b9fc8ae | 834 | __le16 RxLen; |
a1365275 SH |
835 | } __attribute__((__packed__)); |
836 | ||
837 | /* | |
838 | * Received a packet and pass to upper layer | |
839 | */ | |
840 | static void | |
841 | dm9000_rx(struct net_device *dev) | |
842 | { | |
843 | board_info_t *db = (board_info_t *) dev->priv; | |
844 | struct dm9000_rxhdr rxhdr; | |
845 | struct sk_buff *skb; | |
846 | u8 rxbyte, *rdptr; | |
6478fac6 | 847 | bool GoodPacket; |
a1365275 SH |
848 | int RxLen; |
849 | ||
850 | /* Check packet ready or not */ | |
851 | do { | |
852 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
853 | ||
854 | /* Get most updated data */ | |
855 | rxbyte = readb(db->io_data); | |
856 | ||
857 | /* Status check: this byte must be 0 or 1 */ | |
858 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 859 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
860 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
861 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
862 | return; | |
863 | } | |
864 | ||
865 | if (rxbyte != DM9000_PKT_RDY) | |
866 | return; | |
867 | ||
868 | /* A packet ready now & Get status/length */ | |
6478fac6 | 869 | GoodPacket = true; |
a1365275 SH |
870 | writeb(DM9000_MRCMD, db->io_addr); |
871 | ||
872 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
873 | ||
93116573 | 874 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 875 | |
c991d168 BD |
876 | if (netif_msg_rx_status(db)) |
877 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
878 | rxhdr.RxStatus, RxLen); | |
879 | ||
a1365275 SH |
880 | /* Packet Status check */ |
881 | if (RxLen < 0x40) { | |
6478fac6 | 882 | GoodPacket = false; |
c991d168 BD |
883 | if (netif_msg_rx_err(db)) |
884 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
885 | } |
886 | ||
887 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 888 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
889 | } |
890 | ||
93116573 | 891 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 892 | GoodPacket = false; |
93116573 | 893 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
894 | if (netif_msg_rx_err(db)) |
895 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 896 | dev->stats.rx_fifo_errors++; |
a1365275 | 897 | } |
93116573 | 898 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
899 | if (netif_msg_rx_err(db)) |
900 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 901 | dev->stats.rx_crc_errors++; |
a1365275 | 902 | } |
93116573 | 903 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
904 | if (netif_msg_rx_err(db)) |
905 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 906 | dev->stats.rx_length_errors++; |
a1365275 SH |
907 | } |
908 | } | |
909 | ||
910 | /* Move data from DM9000 */ | |
911 | if (GoodPacket | |
912 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
913 | skb_reserve(skb, 2); |
914 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
915 | ||
916 | /* Read received packet from RX SRAM */ | |
917 | ||
918 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 919 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
920 | |
921 | /* Pass to upper layer */ | |
922 | skb->protocol = eth_type_trans(skb, dev); | |
923 | netif_rx(skb); | |
09f75cd7 | 924 | dev->stats.rx_packets++; |
a1365275 SH |
925 | |
926 | } else { | |
927 | /* need to dump the packet's data */ | |
928 | ||
929 | (db->dumpblk)(db->io_data, RxLen); | |
930 | } | |
931 | } while (rxbyte == DM9000_PKT_RDY); | |
932 | } | |
933 | ||
f8d79e79 | 934 | static irqreturn_t dm9000_interrupt(int irq, void *dev_id) |
39c341a8 | 935 | { |
f8d79e79 BD |
936 | struct net_device *dev = dev_id; |
937 | board_info_t *db = dev->priv; | |
938 | int int_status; | |
939 | u8 reg_save; | |
39c341a8 | 940 | |
f8d79e79 | 941 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
39c341a8 | 942 | |
f8d79e79 | 943 | /* A real interrupt coming */ |
39c341a8 | 944 | |
f8d79e79 | 945 | spin_lock(&db->lock); |
39c341a8 | 946 | |
f8d79e79 BD |
947 | /* Save previous register address */ |
948 | reg_save = readb(db->io_addr); | |
39c341a8 | 949 | |
f8d79e79 BD |
950 | /* Disable all interrupts */ |
951 | iow(db, DM9000_IMR, IMR_PAR); | |
39c341a8 | 952 | |
f8d79e79 BD |
953 | /* Got DM9000 interrupt status */ |
954 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
955 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
39c341a8 | 956 | |
f8d79e79 BD |
957 | if (netif_msg_intr(db)) |
958 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
959 | ||
960 | /* Received the coming packet */ | |
961 | if (int_status & ISR_PRS) | |
962 | dm9000_rx(dev); | |
963 | ||
964 | /* Trnasmit Interrupt check */ | |
965 | if (int_status & ISR_PTS) | |
966 | dm9000_tx_done(dev, db); | |
967 | ||
968 | if (db->type != TYPE_DM9000E) { | |
969 | if (int_status & ISR_LNKCHNG) { | |
970 | /* fire a link-change request */ | |
971 | schedule_delayed_work(&db->phy_poll, 1); | |
39c341a8 BD |
972 | } |
973 | } | |
974 | ||
f8d79e79 BD |
975 | /* Re-enable interrupt mask */ |
976 | iow(db, DM9000_IMR, db->imr_all); | |
977 | ||
978 | /* Restore previous register address */ | |
979 | writeb(reg_save, db->io_addr); | |
980 | ||
981 | spin_unlock(&db->lock); | |
982 | ||
983 | return IRQ_HANDLED; | |
39c341a8 BD |
984 | } |
985 | ||
f8d79e79 | 986 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a1365275 | 987 | /* |
f8d79e79 | 988 | *Used by netconsole |
a1365275 | 989 | */ |
f8d79e79 | 990 | static void dm9000_poll_controller(struct net_device *dev) |
a1365275 | 991 | { |
f8d79e79 BD |
992 | disable_irq(dev->irq); |
993 | dm9000_interrupt(dev->irq, dev); | |
994 | enable_irq(dev->irq); | |
995 | } | |
996 | #endif | |
9a2f037c | 997 | |
f8d79e79 BD |
998 | /* |
999 | * Open the interface. | |
1000 | * The interface is opened whenever "ifconfig" actives it. | |
1001 | */ | |
1002 | static int | |
1003 | dm9000_open(struct net_device *dev) | |
1004 | { | |
1005 | board_info_t *db = dev->priv; | |
1006 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; | |
621ddcb0 | 1007 | |
f8d79e79 BD |
1008 | if (netif_msg_ifup(db)) |
1009 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
621ddcb0 | 1010 | |
f8d79e79 BD |
1011 | /* If there is no IRQ type specified, default to something that |
1012 | * may work, and tell the user that this is a problem */ | |
621ddcb0 | 1013 | |
6ff4ff06 | 1014 | if (irqflags == IRQF_TRIGGER_NONE) |
f8d79e79 | 1015 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); |
6ff4ff06 | 1016 | |
f8d79e79 | 1017 | irqflags |= IRQF_SHARED; |
39c341a8 | 1018 | |
f8d79e79 BD |
1019 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) |
1020 | return -EAGAIN; | |
621ddcb0 | 1021 | |
f8d79e79 BD |
1022 | /* Initialize DM9000 board */ |
1023 | dm9000_reset(db); | |
1024 | dm9000_init_dm9000(dev); | |
621ddcb0 | 1025 | |
f8d79e79 BD |
1026 | /* Init driver variable */ |
1027 | db->dbug_cnt = 0; | |
86c62fab | 1028 | |
f8d79e79 BD |
1029 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
1030 | netif_start_queue(dev); | |
1031 | ||
1032 | dm9000_schedule_poll(db); | |
9a2f037c | 1033 | |
f8d79e79 BD |
1034 | return 0; |
1035 | } | |
621ddcb0 | 1036 | |
f8d79e79 BD |
1037 | /* |
1038 | * Sleep, either by using msleep() or if we are suspending, then | |
1039 | * use mdelay() to sleep. | |
1040 | */ | |
1041 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1042 | { | |
1043 | if (db->in_suspend) | |
1044 | mdelay(ms); | |
1045 | else | |
1046 | msleep(ms); | |
a1365275 SH |
1047 | } |
1048 | ||
a1365275 | 1049 | /* |
f8d79e79 | 1050 | * Read a word from phyxcer |
a1365275 | 1051 | */ |
f8d79e79 BD |
1052 | static int |
1053 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
a1365275 | 1054 | { |
f8d79e79 | 1055 | board_info_t *db = (board_info_t *) dev->priv; |
621ddcb0 | 1056 | unsigned long flags; |
f8d79e79 BD |
1057 | unsigned int reg_save; |
1058 | int ret; | |
bb44fb70 | 1059 | |
9a2f037c BD |
1060 | mutex_lock(&db->addr_lock); |
1061 | ||
f8d79e79 | 1062 | spin_lock_irqsave(&db->lock,flags); |
621ddcb0 | 1063 | |
f8d79e79 BD |
1064 | /* Save previous register address */ |
1065 | reg_save = readb(db->io_addr); | |
39c341a8 | 1066 | |
f8d79e79 BD |
1067 | /* Fill the phyxcer register into REG_0C */ |
1068 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
621ddcb0 | 1069 | |
f8d79e79 | 1070 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ |
9a2f037c | 1071 | |
f8d79e79 BD |
1072 | writeb(reg_save, db->io_addr); |
1073 | spin_unlock_irqrestore(&db->lock,flags); | |
89c8b0e6 | 1074 | |
321f69a4 | 1075 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1076 | |
1077 | spin_lock_irqsave(&db->lock,flags); | |
1078 | reg_save = readb(db->io_addr); | |
1079 | ||
a1365275 SH |
1080 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1081 | ||
1082 | /* The read data keeps on REG_0D & REG_0E */ | |
1083 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1084 | ||
9ef9ac51 BD |
1085 | /* restore the previous address */ |
1086 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1087 | spin_unlock_irqrestore(&db->lock,flags); |
1088 | ||
9a2f037c | 1089 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1090 | |
1091 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1092 | return ret; |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * Write a word to phyxcer | |
1097 | */ | |
1098 | static void | |
59eae1fa BD |
1099 | dm9000_phy_write(struct net_device *dev, |
1100 | int phyaddr_unused, int reg, int value) | |
a1365275 SH |
1101 | { |
1102 | board_info_t *db = (board_info_t *) dev->priv; | |
1103 | unsigned long flags; | |
9ef9ac51 | 1104 | unsigned long reg_save; |
a1365275 | 1105 | |
37d5dca6 | 1106 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1107 | mutex_lock(&db->addr_lock); |
1108 | ||
a1365275 SH |
1109 | spin_lock_irqsave(&db->lock,flags); |
1110 | ||
9ef9ac51 BD |
1111 | /* Save previous register address */ |
1112 | reg_save = readb(db->io_addr); | |
1113 | ||
a1365275 SH |
1114 | /* Fill the phyxcer register into REG_0C */ |
1115 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1116 | ||
1117 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1118 | iow(db, DM9000_EPDRL, value); |
1119 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1120 | |
1121 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1122 | |
1123 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1124 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1125 | |
321f69a4 | 1126 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1127 | |
1128 | spin_lock_irqsave(&db->lock,flags); | |
1129 | reg_save = readb(db->io_addr); | |
1130 | ||
a1365275 SH |
1131 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1132 | ||
9ef9ac51 BD |
1133 | /* restore the previous address */ |
1134 | writeb(reg_save, db->io_addr); | |
1135 | ||
9a2f037c BD |
1136 | spin_unlock_irqrestore(&db->lock, flags); |
1137 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1138 | } |
1139 | ||
f8d79e79 BD |
1140 | static void |
1141 | dm9000_shutdown(struct net_device *dev) | |
1142 | { | |
1143 | board_info_t *db = dev->priv; | |
1144 | ||
1145 | /* RESET device */ | |
1146 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
1147 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
1148 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
1149 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
1150 | } | |
1151 | ||
1152 | /* | |
1153 | * Stop the interface. | |
1154 | * The interface is stopped when it is brought. | |
1155 | */ | |
1156 | static int | |
1157 | dm9000_stop(struct net_device *ndev) | |
1158 | { | |
1159 | board_info_t *db = ndev->priv; | |
1160 | ||
1161 | if (netif_msg_ifdown(db)) | |
1162 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
1163 | ||
1164 | cancel_delayed_work_sync(&db->phy_poll); | |
1165 | ||
1166 | netif_stop_queue(ndev); | |
1167 | netif_carrier_off(ndev); | |
1168 | ||
1169 | /* free interrupt */ | |
1170 | free_irq(ndev->irq, ndev); | |
1171 | ||
1172 | dm9000_shutdown(ndev); | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
1178 | ||
1179 | /* | |
1180 | * Search DM9000 board, allocate space and register it | |
1181 | */ | |
1182 | static int __devinit | |
1183 | dm9000_probe(struct platform_device *pdev) | |
1184 | { | |
1185 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; | |
1186 | struct board_info *db; /* Point a board information structure */ | |
1187 | struct net_device *ndev; | |
1188 | const unsigned char *mac_src; | |
1189 | int ret = 0; | |
1190 | int iosize; | |
1191 | int i; | |
1192 | u32 id_val; | |
1193 | ||
1194 | /* Init network device */ | |
1195 | ndev = alloc_etherdev(sizeof(struct board_info)); | |
1196 | if (!ndev) { | |
1197 | dev_err(&pdev->dev, "could not allocate device.\n"); | |
1198 | return -ENOMEM; | |
1199 | } | |
1200 | ||
1201 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1202 | ||
1203 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); | |
1204 | ||
1205 | /* setup board info structure */ | |
1206 | db = ndev->priv; | |
1207 | memset(db, 0, sizeof(*db)); | |
1208 | ||
1209 | db->dev = &pdev->dev; | |
1210 | db->ndev = ndev; | |
1211 | ||
1212 | spin_lock_init(&db->lock); | |
1213 | mutex_init(&db->addr_lock); | |
1214 | ||
1215 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); | |
1216 | ||
1217 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1218 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1219 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1220 | ||
1221 | if (db->addr_res == NULL || db->data_res == NULL || | |
1222 | db->irq_res == NULL) { | |
1223 | dev_err(db->dev, "insufficient resources\n"); | |
1224 | ret = -ENOENT; | |
1225 | goto out; | |
1226 | } | |
1227 | ||
1228 | iosize = res_size(db->addr_res); | |
1229 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
1230 | pdev->name); | |
1231 | ||
1232 | if (db->addr_req == NULL) { | |
1233 | dev_err(db->dev, "cannot claim address reg area\n"); | |
1234 | ret = -EIO; | |
1235 | goto out; | |
1236 | } | |
1237 | ||
1238 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
1239 | ||
1240 | if (db->io_addr == NULL) { | |
1241 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
1242 | ret = -EINVAL; | |
1243 | goto out; | |
1244 | } | |
1245 | ||
1246 | iosize = res_size(db->data_res); | |
1247 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
1248 | pdev->name); | |
1249 | ||
1250 | if (db->data_req == NULL) { | |
1251 | dev_err(db->dev, "cannot claim data reg area\n"); | |
1252 | ret = -EIO; | |
1253 | goto out; | |
1254 | } | |
1255 | ||
1256 | db->io_data = ioremap(db->data_res->start, iosize); | |
1257 | ||
1258 | if (db->io_data == NULL) { | |
1259 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
1260 | ret = -EINVAL; | |
1261 | goto out; | |
1262 | } | |
1263 | ||
1264 | /* fill in parameters for net-dev structure */ | |
1265 | ndev->base_addr = (unsigned long)db->io_addr; | |
1266 | ndev->irq = db->irq_res->start; | |
1267 | ||
1268 | /* ensure at least we have a default set of IO routines */ | |
1269 | dm9000_set_io(db, iosize); | |
1270 | ||
1271 | /* check to see if anything is being over-ridden */ | |
1272 | if (pdata != NULL) { | |
1273 | /* check to see if the driver wants to over-ride the | |
1274 | * default IO width */ | |
1275 | ||
1276 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
1277 | dm9000_set_io(db, 1); | |
1278 | ||
1279 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
1280 | dm9000_set_io(db, 2); | |
1281 | ||
1282 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
1283 | dm9000_set_io(db, 4); | |
1284 | ||
1285 | /* check to see if there are any IO routine | |
1286 | * over-rides */ | |
1287 | ||
1288 | if (pdata->inblk != NULL) | |
1289 | db->inblk = pdata->inblk; | |
1290 | ||
1291 | if (pdata->outblk != NULL) | |
1292 | db->outblk = pdata->outblk; | |
1293 | ||
1294 | if (pdata->dumpblk != NULL) | |
1295 | db->dumpblk = pdata->dumpblk; | |
1296 | ||
1297 | db->flags = pdata->flags; | |
1298 | } | |
1299 | ||
f8dd0ecb BD |
1300 | #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL |
1301 | db->flags |= DM9000_PLATF_SIMPLE_PHY; | |
1302 | #endif | |
1303 | ||
f8d79e79 BD |
1304 | dm9000_reset(db); |
1305 | ||
1306 | /* try multiple times, DM9000 sometimes gets the read wrong */ | |
1307 | for (i = 0; i < 8; i++) { | |
1308 | id_val = ior(db, DM9000_VIDL); | |
1309 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
1310 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
1311 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
1312 | ||
1313 | if (id_val == DM9000_ID) | |
1314 | break; | |
1315 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); | |
1316 | } | |
1317 | ||
1318 | if (id_val != DM9000_ID) { | |
1319 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); | |
1320 | ret = -ENODEV; | |
1321 | goto out; | |
1322 | } | |
1323 | ||
1324 | /* Identify what type of DM9000 we are working on */ | |
1325 | ||
1326 | id_val = ior(db, DM9000_CHIPR); | |
1327 | dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); | |
1328 | ||
1329 | switch (id_val) { | |
1330 | case CHIPR_DM9000A: | |
1331 | db->type = TYPE_DM9000A; | |
1332 | break; | |
1333 | case CHIPR_DM9000B: | |
1334 | db->type = TYPE_DM9000B; | |
1335 | break; | |
1336 | default: | |
1337 | dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); | |
1338 | db->type = TYPE_DM9000E; | |
1339 | } | |
1340 | ||
1341 | /* from this point we assume that we have found a DM9000 */ | |
1342 | ||
1343 | /* driver system function */ | |
1344 | ether_setup(ndev); | |
1345 | ||
1346 | ndev->open = &dm9000_open; | |
1347 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
1348 | ndev->tx_timeout = &dm9000_timeout; | |
1349 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
1350 | ndev->stop = &dm9000_stop; | |
1351 | ndev->set_multicast_list = &dm9000_hash_table; | |
1352 | ndev->ethtool_ops = &dm9000_ethtool_ops; | |
1353 | ndev->do_ioctl = &dm9000_ioctl; | |
1354 | ||
1355 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1356 | ndev->poll_controller = &dm9000_poll_controller; | |
1357 | #endif | |
1358 | ||
1359 | db->msg_enable = NETIF_MSG_LINK; | |
1360 | db->mii.phy_id_mask = 0x1f; | |
1361 | db->mii.reg_num_mask = 0x1f; | |
1362 | db->mii.force_media = 0; | |
1363 | db->mii.full_duplex = 0; | |
1364 | db->mii.dev = ndev; | |
1365 | db->mii.mdio_read = dm9000_phy_read; | |
1366 | db->mii.mdio_write = dm9000_phy_write; | |
1367 | ||
1368 | mac_src = "eeprom"; | |
1369 | ||
1370 | /* try reading the node address from the attached EEPROM */ | |
1371 | for (i = 0; i < 6; i += 2) | |
1372 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
1373 | ||
1374 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1375 | /* try reading from mac */ | |
1376 | ||
1377 | mac_src = "chip"; | |
1378 | for (i = 0; i < 6; i++) | |
1379 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
1380 | } | |
1381 | ||
1382 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1383 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " | |
1384 | "set using ifconfig\n", ndev->name); | |
1385 | ||
1386 | platform_set_drvdata(pdev, ndev); | |
1387 | ret = register_netdev(ndev); | |
1388 | ||
1389 | if (ret == 0) { | |
1390 | DECLARE_MAC_BUF(mac); | |
1391 | printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", | |
1392 | ndev->name, dm9000_type_to_char(db->type), | |
1393 | db->io_addr, db->io_data, ndev->irq, | |
1394 | print_mac(mac, ndev->dev_addr), mac_src); | |
1395 | } | |
1396 | return 0; | |
1397 | ||
1398 | out: | |
1399 | dev_err(db->dev, "not found (%d).\n", ret); | |
1400 | ||
1401 | dm9000_release_board(pdev, db); | |
1402 | free_netdev(ndev); | |
1403 | ||
1404 | return ret; | |
1405 | } | |
1406 | ||
a1365275 | 1407 | static int |
3ae5eaec | 1408 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1409 | { |
3ae5eaec | 1410 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1411 | board_info_t *db; |
a1365275 | 1412 | |
9480e307 | 1413 | if (ndev) { |
321f69a4 BD |
1414 | db = (board_info_t *) ndev->priv; |
1415 | db->in_suspend = 1; | |
1416 | ||
a1365275 SH |
1417 | if (netif_running(ndev)) { |
1418 | netif_device_detach(ndev); | |
1419 | dm9000_shutdown(ndev); | |
1420 | } | |
1421 | } | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | static int | |
3ae5eaec | 1426 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1427 | { |
3ae5eaec | 1428 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1429 | board_info_t *db = (board_info_t *) ndev->priv; |
1430 | ||
9480e307 | 1431 | if (ndev) { |
a1365275 SH |
1432 | |
1433 | if (netif_running(ndev)) { | |
1434 | dm9000_reset(db); | |
1435 | dm9000_init_dm9000(ndev); | |
1436 | ||
1437 | netif_device_attach(ndev); | |
1438 | } | |
321f69a4 BD |
1439 | |
1440 | db->in_suspend = 0; | |
a1365275 SH |
1441 | } |
1442 | return 0; | |
1443 | } | |
1444 | ||
e21fd4f0 | 1445 | static int __devexit |
3ae5eaec | 1446 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1447 | { |
3ae5eaec | 1448 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1449 | |
3ae5eaec | 1450 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1451 | |
1452 | unregister_netdev(ndev); | |
1453 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1454 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1455 | |
a76836f9 | 1456 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1457 | return 0; |
1458 | } | |
1459 | ||
3ae5eaec | 1460 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1461 | .driver = { |
1462 | .name = "dm9000", | |
1463 | .owner = THIS_MODULE, | |
1464 | }, | |
a1365275 | 1465 | .probe = dm9000_probe, |
e21fd4f0 | 1466 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1467 | .suspend = dm9000_drv_suspend, |
1468 | .resume = dm9000_drv_resume, | |
1469 | }; | |
1470 | ||
1471 | static int __init | |
1472 | dm9000_init(void) | |
1473 | { | |
7da99859 | 1474 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1475 | |
59eae1fa | 1476 | return platform_driver_register(&dm9000_driver); |
a1365275 SH |
1477 | } |
1478 | ||
1479 | static void __exit | |
1480 | dm9000_cleanup(void) | |
1481 | { | |
3ae5eaec | 1482 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1483 | } |
1484 | ||
1485 | module_init(dm9000_init); | |
1486 | module_exit(dm9000_cleanup); | |
1487 | ||
1488 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1489 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1490 | MODULE_LICENSE("GPL"); | |
72abb461 | 1491 | MODULE_ALIAS("platform:dm9000"); |