projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[deliverable/linux.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
246d7f77
FF		 1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <net/dsa.h>
96e65d7f 25#include <linux/ethtool.h>
12f460f2 26#include <linux/if_bridge.h>
aafc66f1 27#include <linux/brcmphy.h>
246d7f77
FF		 28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
31
32/* String, offset, and register size in bytes if different from 4 bytes */
33static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
34 { "TxOctets", 0x000, 8 },
35 { "TxDropPkts", 0x020 },
36 { "TxQPKTQ0", 0x030 },
37 { "TxBroadcastPkts", 0x040 },
38 { "TxMulticastPkts", 0x050 },
39 { "TxUnicastPKts", 0x060 },
40 { "TxCollisions", 0x070 },
41 { "TxSingleCollision", 0x080 },
42 { "TxMultipleCollision", 0x090 },
43 { "TxDeferredCollision", 0x0a0 },
44 { "TxLateCollision", 0x0b0 },
45 { "TxExcessiveCollision", 0x0c0 },
46 { "TxFrameInDisc", 0x0d0 },
47 { "TxPausePkts", 0x0e0 },
48 { "TxQPKTQ1", 0x0f0 },
49 { "TxQPKTQ2", 0x100 },
50 { "TxQPKTQ3", 0x110 },
51 { "TxQPKTQ4", 0x120 },
52 { "TxQPKTQ5", 0x130 },
53 { "RxOctets", 0x140, 8 },
54 { "RxUndersizePkts", 0x160 },
55 { "RxPausePkts", 0x170 },
56 { "RxPkts64Octets", 0x180 },
57 { "RxPkts65to127Octets", 0x190 },
58 { "RxPkts128to255Octets", 0x1a0 },
59 { "RxPkts256to511Octets", 0x1b0 },
60 { "RxPkts512to1023Octets", 0x1c0 },
61 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
62 { "RxOversizePkts", 0x1e0 },
63 { "RxJabbers", 0x1f0 },
64 { "RxAlignmentErrors", 0x200 },
65 { "RxFCSErrors", 0x210 },
66 { "RxGoodOctets", 0x220, 8 },
67 { "RxDropPkts", 0x240 },
68 { "RxUnicastPkts", 0x250 },
69 { "RxMulticastPkts", 0x260 },
70 { "RxBroadcastPkts", 0x270 },
71 { "RxSAChanges", 0x280 },
72 { "RxFragments", 0x290 },
73 { "RxJumboPkt", 0x2a0 },
74 { "RxSymblErr", 0x2b0 },
75 { "InRangeErrCount", 0x2c0 },
76 { "OutRangeErrCount", 0x2d0 },
77 { "EEELpiEvent", 0x2e0 },
78 { "EEELpiDuration", 0x2f0 },
79 { "RxDiscard", 0x300, 8 },
80 { "TxQPKTQ6", 0x320 },
81 { "TxQPKTQ7", 0x330 },
82 { "TxPkts64Octets", 0x340 },
83 { "TxPkts65to127Octets", 0x350 },
84 { "TxPkts128to255Octets", 0x360 },
85 { "TxPkts256to511Ocets", 0x370 },
86 { "TxPkts512to1023Ocets", 0x380 },
87 { "TxPkts1024toMaxPktOcets", 0x390 },
88};
89
90#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
91
92static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
93 int port, uint8_t *data)
94{
95 unsigned int i;
96
97 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
98 memcpy(data + i * ETH_GSTRING_LEN,
99 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
100}
101
102static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
103 int port, uint64_t *data)
104{
105 struct bcm_sf2_priv *priv = ds_to_priv(ds);
106 const struct bcm_sf2_hw_stats *s;
107 unsigned int i;
108 u64 val = 0;
109 u32 offset;
110
111 mutex_lock(&priv->stats_mutex);
112
113 /* Now fetch the per-port counters */
114 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
115 s = &bcm_sf2_mib[i];
116
117 /* Do a latched 64-bit read if needed */
118 offset = s->reg + CORE_P_MIB_OFFSET(port);
119 if (s->sizeof_stat == 8)
120 val = core_readq(priv, offset);
121 else
122 val = core_readl(priv, offset);
123
124 data[i] = (u64)val;
125 }
126
127 mutex_unlock(&priv->stats_mutex);
128}
129
130static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
131{
132 return BCM_SF2_STATS_SIZE;
133}
134
b4d2394d 135static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
246d7f77
FF		 136{
137 return "Broadcom Starfighter 2";
138}
139
b6d045db 140static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
246d7f77
FF		 141{
142 struct bcm_sf2_priv *priv = ds_to_priv(ds);
143 unsigned int i;
b6d045db
FF		 144 u32 reg;
145
146 /* Enable the IMP Port to be in the same VLAN as the other ports
147 * on a per-port basis such that we only have Port i and IMP in
148 * the same VLAN.
149 */
150 for (i = 0; i < priv->hw_params.num_ports; i++) {
151 if (!((1 << i) & ds->phys_port_mask))
152 continue;
153
154 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
155 reg |= (1 << cpu_port);
156 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
157 }
158}
159
160static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
161{
162 struct bcm_sf2_priv *priv = ds_to_priv(ds);
246d7f77
FF		 163 u32 reg, val;
164
165 /* Enable the port memories */
166 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
167 reg &= ~P_TXQ_PSM_VDD(port);
168 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
169
170 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
171 reg = core_readl(priv, CORE_IMP_CTL);
172 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
173 reg &= ~(RX_DIS | TX_DIS);
174 core_writel(priv, reg, CORE_IMP_CTL);
175
176 /* Enable forwarding */
177 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
178
179 /* Enable IMP port in dumb mode */
180 reg = core_readl(priv, CORE_SWITCH_CTRL);
181 reg |= MII_DUMB_FWDG_EN;
182 core_writel(priv, reg, CORE_SWITCH_CTRL);
183
184 /* Resolve which bit controls the Broadcom tag */
185 switch (port) {
186 case 8:
187 val = BRCM_HDR_EN_P8;
188 break;
189 case 7:
190 val = BRCM_HDR_EN_P7;
191 break;
192 case 5:
193 val = BRCM_HDR_EN_P5;
194 break;
195 default:
196 val = 0;
197 break;
198 }
199
200 /* Enable Broadcom tags for IMP port */
201 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
202 reg |= val;
203 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
204
205 /* Enable reception Broadcom tag for CPU TX (switch RX) to
206 * allow us to tag outgoing frames
207 */
208 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
209 reg &= ~(1 << port);
210 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
211
212 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
213 * allow delivering frames to the per-port net_devices
214 */
215 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
216 reg &= ~(1 << port);
217 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
218
219 /* Force link status for IMP port */
220 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
221 reg |= (MII_SW_OR | LINK_STS);
222 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
246d7f77
FF		 223}
224
450b05c1
FF		 225static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
226{
227 struct bcm_sf2_priv *priv = ds_to_priv(ds);
228 u32 reg;
229
230 reg = core_readl(priv, CORE_EEE_EN_CTRL);
231 if (enable)
232 reg |= 1 << port;
233 else
234 reg &= ~(1 << port);
235 core_writel(priv, reg, CORE_EEE_EN_CTRL);
236}
237
b083668c
FF		 238static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
239{
240 struct bcm_sf2_priv *priv = ds_to_priv(ds);
241 u32 reg;
242
b083668c 243 reg = reg_readl(priv, REG_SPHY_CNTRL);
9af197a8
FF		 244 if (enable) {
245 reg |= PHY_RESET;
246 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
247 reg_writel(priv, reg, REG_SPHY_CNTRL);
248 udelay(21);
249 reg = reg_readl(priv, REG_SPHY_CNTRL);
250 reg &= ~PHY_RESET;
251 } else {
252 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
253 reg_writel(priv, reg, REG_SPHY_CNTRL);
254 mdelay(1);
255 reg |= CK25_DIS;
256 }
b083668c 257 reg_writel(priv, reg, REG_SPHY_CNTRL);
9af197a8
FF		 258
259 /* Use PHY-driven LED signaling */
260 if (!enable) {
261 reg = reg_readl(priv, REG_LED_CNTRL(0));
262 reg |= SPDLNK_SRC_SEL;
263 reg_writel(priv, reg, REG_LED_CNTRL(0));
264 }
b083668c
FF		 265}
266
b6d045db
FF		 267static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
268 struct phy_device *phy)
246d7f77
FF		 269{
270 struct bcm_sf2_priv *priv = ds_to_priv(ds);
b6d045db 271 s8 cpu_port = ds->dst[ds->index].cpu_port;
246d7f77
FF		 272 u32 reg;
273
274 /* Clear the memory power down */
275 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
276 reg &= ~P_TXQ_PSM_VDD(port);
277 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
278
279 /* Clear the Rx and Tx disable bits and set to no spanning tree */
280 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
281
9af197a8
FF		 282 /* Re-enable the GPHY and re-apply workarounds */
283 if (port == 0 && priv->hw_params.num_gphy == 1) {
284 bcm_sf2_gphy_enable_set(ds, true);
285 if (phy) {
286 /* if phy_stop() has been called before, phy
287 * will be in halted state, and phy_start()
288 * will call resume.
289 *
290 * the resume path does not configure back
291 * autoneg settings, and since we hard reset
292 * the phy manually here, we need to reset the
293 * state machine also.
294 */
295 phy->state = PHY_READY;
296 phy_init_hw(phy);
297 }
298 }
299
246d7f77
FF		 300 /* Enable port 7 interrupts to get notified */
301 if (port == 7)
302 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
303
12f460f2
FF		 304 /* Set this port, and only this one to be in the default VLAN,
305 * if member of a bridge, restore its membership prior to
306 * bringing down this port.
307 */
246d7f77
FF		 308 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
309 reg &= ~PORT_VLAN_CTRL_MASK;
310 reg |= (1 << port);
12f460f2 311 reg |= priv->port_sts[port].vlan_ctl_mask;
246d7f77 312 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
b6d045db
FF		 313
314 bcm_sf2_imp_vlan_setup(ds, cpu_port);
315
450b05c1
FF		 316 /* If EEE was enabled, restore it */
317 if (priv->port_sts[port].eee.eee_enabled)
318 bcm_sf2_eee_enable_set(ds, port, true);
319
b6d045db 320 return 0;
246d7f77
FF		 321}
322
b6d045db
FF		 323static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
324 struct phy_device *phy)
246d7f77
FF		 325{
326 struct bcm_sf2_priv *priv = ds_to_priv(ds);
327 u32 off, reg;
328
96e65d7f
FF		 329 if (priv->wol_ports_mask & (1 << port))
330 return;
331
b6d045db
FF		 332 if (port == 7) {
333 intrl2_1_mask_set(priv, P_IRQ_MASK(P7_IRQ_OFF));
334 intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
335 }
336
9af197a8
FF		 337 if (port == 0 && priv->hw_params.num_gphy == 1)
338 bcm_sf2_gphy_enable_set(ds, false);
339
246d7f77
FF		 340 if (dsa_is_cpu_port(ds, port))
341 off = CORE_IMP_CTL;
342 else
343 off = CORE_G_PCTL_PORT(port);
344
345 reg = core_readl(priv, off);
346 reg |= RX_DIS | TX_DIS;
347 core_writel(priv, reg, off);
348
349 /* Power down the port memory */
350 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
351 reg |= P_TXQ_PSM_VDD(port);
352 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
353}
354
450b05c1
FF		 355/* Returns 0 if EEE was not enabled, or 1 otherwise
356 */
357static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
358 struct phy_device *phy)
359{
360 struct bcm_sf2_priv *priv = ds_to_priv(ds);
361 struct ethtool_eee *p = &priv->port_sts[port].eee;
362 int ret;
363
364 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
365
366 ret = phy_init_eee(phy, 0);
367 if (ret)
368 return 0;
369
370 bcm_sf2_eee_enable_set(ds, port, true);
371
372 return 1;
373}
374
375static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
376 struct ethtool_eee *e)
377{
378 struct bcm_sf2_priv *priv = ds_to_priv(ds);
379 struct ethtool_eee *p = &priv->port_sts[port].eee;
380 u32 reg;
381
382 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
383 e->eee_enabled = p->eee_enabled;
384 e->eee_active = !!(reg & (1 << port));
385
386 return 0;
387}
388
389static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
390 struct phy_device *phydev,
391 struct ethtool_eee *e)
392{
393 struct bcm_sf2_priv *priv = ds_to_priv(ds);
394 struct ethtool_eee *p = &priv->port_sts[port].eee;
395
396 p->eee_enabled = e->eee_enabled;
397
398 if (!p->eee_enabled) {
399 bcm_sf2_eee_enable_set(ds, port, false);
400 } else {
401 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
402 if (!p->eee_enabled)
403 return -EOPNOTSUPP;
404 }
405
406 return 0;
407}
408
12f460f2
FF		 409/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
410 * flush for that port.
411 */
412static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
413{
414 struct bcm_sf2_priv *priv = ds_to_priv(ds);
415 unsigned int timeout = 1000;
416 u32 reg;
417
418 core_writel(priv, port, CORE_FAST_AGE_PORT);
419
420 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
421 reg |= EN_AGE_PORT | FAST_AGE_STR_DONE;
422 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
423
424 do {
425 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
426 if (!(reg & FAST_AGE_STR_DONE))
427 break;
428
429 cpu_relax();
430 } while (timeout--);
431
432 if (!timeout)
433 return -ETIMEDOUT;
434
435 return 0;
436}
437
438static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
439 u32 br_port_mask)
440{
441 struct bcm_sf2_priv *priv = ds_to_priv(ds);
442 unsigned int i;
443 u32 reg, p_ctl;
444
445 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
446
447 for (i = 0; i < priv->hw_params.num_ports; i++) {
448 if (!((1 << i) & br_port_mask))
449 continue;
450
451 /* Add this local port to the remote port VLAN control
452 * membership and update the remote port bitmask
453 */
454 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
455 reg |= 1 << port;
456 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
457 priv->port_sts[i].vlan_ctl_mask = reg;
458
459 p_ctl |= 1 << i;
460 }
461
462 /* Configure the local port VLAN control membership to include
463 * remote ports and update the local port bitmask
464 */
465 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
466 priv->port_sts[port].vlan_ctl_mask = p_ctl;
467
468 return 0;
469}
470
471static int bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
472 u32 br_port_mask)
473{
474 struct bcm_sf2_priv *priv = ds_to_priv(ds);
475 unsigned int i;
476 u32 reg, p_ctl;
477
478 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
479
480 for (i = 0; i < priv->hw_params.num_ports; i++) {
481 /* Don't touch the remaining ports */
482 if (!((1 << i) & br_port_mask))
483 continue;
484
485 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
486 reg &= ~(1 << port);
487 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
488 priv->port_sts[port].vlan_ctl_mask = reg;
489
490 /* Prevent self removal to preserve isolation */
491 if (port != i)
492 p_ctl &= ~(1 << i);
493 }
494
495 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
496 priv->port_sts[port].vlan_ctl_mask = p_ctl;
497
498 return 0;
499}
500
501static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
502 u8 state)
503{
504 struct bcm_sf2_priv *priv = ds_to_priv(ds);
505 u8 hw_state, cur_hw_state;
506 int ret = 0;
507 u32 reg;
508
509 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
510 cur_hw_state = reg >> G_MISTP_STATE_SHIFT;
511
512 switch (state) {
513 case BR_STATE_DISABLED:
514 hw_state = G_MISTP_DIS_STATE;
515 break;
516 case BR_STATE_LISTENING:
517 hw_state = G_MISTP_LISTEN_STATE;
518 break;
519 case BR_STATE_LEARNING:
520 hw_state = G_MISTP_LEARN_STATE;
521 break;
522 case BR_STATE_FORWARDING:
523 hw_state = G_MISTP_FWD_STATE;
524 break;
525 case BR_STATE_BLOCKING:
526 hw_state = G_MISTP_BLOCK_STATE;
527 break;
528 default:
529 pr_err("%s: invalid STP state: %d\n", __func__, state);
530 return -EINVAL;
531 }
532
533 /* Fast-age ARL entries if we are moving a port from Learning or
534 * Forwarding state to Disabled, Blocking or Listening state
535 */
536 if (cur_hw_state != hw_state) {
537 if (cur_hw_state & 4 && !(hw_state & 4)) {
538 ret = bcm_sf2_sw_fast_age_port(ds, port);
539 if (ret) {
540 pr_err("%s: fast-ageing failed\n", __func__);
541 return ret;
542 }
543 }
544 }
545
546 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
547 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
548 reg |= hw_state;
549 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
550
551 return 0;
552}
553
246d7f77
FF		 554static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
555{
556 struct bcm_sf2_priv *priv = dev_id;
557
558 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
559 ~priv->irq0_mask;
560 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
561
562 return IRQ_HANDLED;
563}
564
565static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
566{
567 struct bcm_sf2_priv *priv = dev_id;
568
569 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
570 ~priv->irq1_mask;
571 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
572
573 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
574 priv->port_sts[7].link = 1;
575 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
576 priv->port_sts[7].link = 0;
577
578 return IRQ_HANDLED;
579}
580
33f84614
FF		 581static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
582{
583 unsigned int timeout = 1000;
584 u32 reg;
585
586 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
587 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
588 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
589
590 do {
591 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
592 if (!(reg & SOFTWARE_RESET))
593 break;
594
595 usleep_range(1000, 2000);
596 } while (timeout-- > 0);
597
598 if (timeout == 0)
599 return -ETIMEDOUT;
600
601 return 0;
602}
603
691c9a8f
FF		 604static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
605{
606 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
607 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
608 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
609 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
610 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
611 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
612}
613
246d7f77
FF		 614static int bcm_sf2_sw_setup(struct dsa_switch *ds)
615{
616 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
617 struct bcm_sf2_priv *priv = ds_to_priv(ds);
618 struct device_node *dn;
619 void __iomem **base;
620 unsigned int port;
621 unsigned int i;
622 u32 reg, rev;
623 int ret;
624
625 spin_lock_init(&priv->indir_lock);
626 mutex_init(&priv->stats_mutex);
627
628 /* All the interesting properties are at the parent device_node
629 * level
630 */
631 dn = ds->pd->of_node->parent;
632
633 priv->irq0 = irq_of_parse_and_map(dn, 0);
634 priv->irq1 = irq_of_parse_and_map(dn, 1);
635
636 base = &priv->core;
637 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
638 *base = of_iomap(dn, i);
639 if (*base == NULL) {
640 pr_err("unable to find register: %s\n", reg_names[i]);
a566059d
FF		 641 ret = -ENOMEM;
642 goto out_unmap;
246d7f77
FF		 643 }
644 base++;
645 }
646
33f84614
FF		 647 ret = bcm_sf2_sw_rst(priv);
648 if (ret) {
649 pr_err("unable to software reset switch: %d\n", ret);
650 goto out_unmap;
651 }
652
246d7f77 653 /* Disable all interrupts and request them */
691c9a8f 654 bcm_sf2_intr_disable(priv);
246d7f77
FF		 655
656 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
657 "switch_0", priv);
658 if (ret < 0) {
659 pr_err("failed to request switch_0 IRQ\n");
660 goto out_unmap;
661 }
662
663 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
664 "switch_1", priv);
665 if (ret < 0) {
666 pr_err("failed to request switch_1 IRQ\n");
667 goto out_free_irq0;
668 }
669
670 /* Reset the MIB counters */
671 reg = core_readl(priv, CORE_GMNCFGCFG);
672 reg |= RST_MIB_CNT;
673 core_writel(priv, reg, CORE_GMNCFGCFG);
674 reg &= ~RST_MIB_CNT;
675 core_writel(priv, reg, CORE_GMNCFGCFG);
676
677 /* Get the maximum number of ports for this switch */
678 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
679 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
680 priv->hw_params.num_ports = DSA_MAX_PORTS;
681
682 /* Assume a single GPHY setup if we can't read that property */
683 if (of_property_read_u32(dn, "brcm,num-gphy",
684 &priv->hw_params.num_gphy))
685 priv->hw_params.num_gphy = 1;
686
687 /* Enable all valid ports and disable those unused */
688 for (port = 0; port < priv->hw_params.num_ports; port++) {
689 /* IMP port receives special treatment */
690 if ((1 << port) & ds->phys_port_mask)
b6d045db 691 bcm_sf2_port_setup(ds, port, NULL);
246d7f77
FF		 692 else if (dsa_is_cpu_port(ds, port))
693 bcm_sf2_imp_setup(ds, port);
694 else
b6d045db 695 bcm_sf2_port_disable(ds, port, NULL);
246d7f77
FF		 696 }
697
698 /* Include the pseudo-PHY address and the broadcast PHY address to
699 * divert reads towards our workaround
700 */
aafc66f1 701 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
246d7f77
FF		 702
703 rev = reg_readl(priv, REG_SWITCH_REVISION);
704 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
705 SWITCH_TOP_REV_MASK;
706 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
707
aa9aef77
FF		 708 rev = reg_readl(priv, REG_PHY_REVISION);
709 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
710
246d7f77
FF		 711 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
712 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
713 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
714 priv->core, priv->irq0, priv->irq1);
715
716 return 0;
717
718out_free_irq0:
719 free_irq(priv->irq0, priv);
720out_unmap:
721 base = &priv->core;
722 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
a566059d
FF		 723 if (*base)
724 iounmap(*base);
246d7f77
FF		 725 base++;
726 }
727 return ret;
728}
729
730static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
731{
732 return 0;
733}
734
aa9aef77
FF		 735static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
736{
737 struct bcm_sf2_priv *priv = ds_to_priv(ds);
738
739 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
740 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
741 * the REG_PHY_REVISION register layout is.
742 */
743
744 return priv->hw_params.gphy_rev;
745}
746
246d7f77
FF		 747static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
748 int regnum, u16 val)
749{
750 struct bcm_sf2_priv *priv = ds_to_priv(ds);
751 int ret = 0;
752 u32 reg;
753
754 reg = reg_readl(priv, REG_SWITCH_CNTRL);
755 reg |= MDIO_MASTER_SEL;
756 reg_writel(priv, reg, REG_SWITCH_CNTRL);
757
758 /* Page << 8 | offset */
759 reg = 0x70;
760 reg <<= 2;
761 core_writel(priv, addr, reg);
762
763 /* Page << 8 | offset */
764 reg = 0x80 << 8 | regnum << 1;
765 reg <<= 2;
766
767 if (op)
768 ret = core_readl(priv, reg);
769 else
770 core_writel(priv, val, reg);
771
772 reg = reg_readl(priv, REG_SWITCH_CNTRL);
773 reg &= ~MDIO_MASTER_SEL;
774 reg_writel(priv, reg, REG_SWITCH_CNTRL);
775
776 return ret & 0xffff;
777}
778
779static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
780{
781 /* Intercept reads from the MDIO broadcast address or Broadcom
782 * pseudo-PHY address
783 */
784 switch (addr) {
785 case 0:
aafc66f1 786 case BRCM_PSEUDO_PHY_ADDR:
246d7f77
FF		 787 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
788 default:
789 return 0xffff;
790 }
791}
792
793static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
794 u16 val)
795{
796 /* Intercept writes to the MDIO broadcast address or Broadcom
797 * pseudo-PHY address
798 */
799 switch (addr) {
800 case 0:
aafc66f1 801 case BRCM_PSEUDO_PHY_ADDR:
246d7f77
FF		 802 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
803 break;
804 }
805
806 return 0;
807}
808
809static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
810 struct phy_device *phydev)
811{
812 struct bcm_sf2_priv *priv = ds_to_priv(ds);
813 u32 id_mode_dis = 0, port_mode;
814 const char *str = NULL;
815 u32 reg;
816
817 switch (phydev->interface) {
818 case PHY_INTERFACE_MODE_RGMII:
819 str = "RGMII (no delay)";
820 id_mode_dis = 1;
821 case PHY_INTERFACE_MODE_RGMII_TXID:
822 if (!str)
823 str = "RGMII (TX delay)";
824 port_mode = EXT_GPHY;
825 break;
826 case PHY_INTERFACE_MODE_MII:
827 str = "MII";
828 port_mode = EXT_EPHY;
829 break;
830 case PHY_INTERFACE_MODE_REVMII:
831 str = "Reverse MII";
832 port_mode = EXT_REVMII;
833 break;
834 default:
7de1557c
FF		 835 /* All other PHYs: internal and MoCA */
836 goto force_link;
837 }
838
839 /* If the link is down, just disable the interface to conserve power */
840 if (!phydev->link) {
841 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
842 reg &= ~RGMII_MODE_EN;
843 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
246d7f77
FF		 844 goto force_link;
845 }
846
847 /* Clear id_mode_dis bit, and the existing port mode, but
848 * make sure we enable the RGMII block for data to pass
849 */
850 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
851 reg &= ~ID_MODE_DIS;
852 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
853 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
854
855 reg |= port_mode | RGMII_MODE_EN;
856 if (id_mode_dis)
857 reg |= ID_MODE_DIS;
858
859 if (phydev->pause) {
860 if (phydev->asym_pause)
861 reg |= TX_PAUSE_EN;
862 reg |= RX_PAUSE_EN;
863 }
864
865 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
866
867 pr_info("Port %d configured for %s\n", port, str);
868
869force_link:
870 /* Force link settings detected from the PHY */
871 reg = SW_OVERRIDE;
872 switch (phydev->speed) {
873 case SPEED_1000:
874 reg |= SPDSTS_1000 << SPEED_SHIFT;
875 break;
876 case SPEED_100:
877 reg |= SPDSTS_100 << SPEED_SHIFT;
878 break;
879 }
880
881 if (phydev->link)
882 reg |= LINK_STS;
883 if (phydev->duplex == DUPLEX_FULL)
884 reg |= DUPLX_MODE;
885
886 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
887}
888
889static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
890 struct fixed_phy_status *status)
891{
892 struct bcm_sf2_priv *priv = ds_to_priv(ds);
7855f675 893 u32 duplex, pause, speed;
246d7f77
FF		 894 u32 reg;
895
246d7f77
FF		 896 duplex = core_readl(priv, CORE_DUPSTS);
897 pause = core_readl(priv, CORE_PAUSESTS);
898 speed = core_readl(priv, CORE_SPDSTS);
899
900 speed >>= (port * SPDSTS_SHIFT);
901 speed &= SPDSTS_MASK;
902
903 status->link = 0;
904
905 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
906 * which means that we need to force the link at the port override
907 * level to get the data to flow. We do use what the interrupt handler
908 * did determine before.
7855f675
FF		 909 *
910 * For the other ports, we just force the link status, since this is
911 * a fixed PHY device.
246d7f77
FF		 912 */
913 if (port == 7) {
914 status->link = priv->port_sts[port].link;
4ab7f913
FF		 915 /* For MoCA interfaces, also force a link down notification
916 * since some version of the user-space daemon (mocad) use
917 * cmd->autoneg to force the link, which messes up the PHY
918 * state machine and make it go in PHY_FORCING state instead.
919 */
920 if (!status->link)
921 netif_carrier_off(ds->ports[port]);
246d7f77
FF		 922 status->duplex = 1;
923 } else {
7855f675 924 status->link = 1;
246d7f77
FF		 925 status->duplex = !!(duplex & (1 << port));
926 }
927
7855f675
FF		 928 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
929 reg |= SW_OVERRIDE;
930 if (status->link)
931 reg |= LINK_STS;
932 else
933 reg &= ~LINK_STS;
934 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
935
246d7f77
FF		 936 switch (speed) {
937 case SPDSTS_10:
938 status->speed = SPEED_10;
939 break;
940 case SPDSTS_100:
941 status->speed = SPEED_100;
942 break;
943 case SPDSTS_1000:
944 status->speed = SPEED_1000;
945 break;
946 }
947
948 if ((pause & (1 << port)) &&
949 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
950 status->asym_pause = 1;
951 status->pause = 1;
952 }
953
954 if (pause & (1 << port))
955 status->pause = 1;
956}
957
8cfa9498
FF		 958static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
959{
960 struct bcm_sf2_priv *priv = ds_to_priv(ds);
961 unsigned int port;
962
691c9a8f 963 bcm_sf2_intr_disable(priv);
8cfa9498
FF		 964
965 /* Disable all ports physically present including the IMP
966 * port, the other ones have already been disabled during
967 * bcm_sf2_sw_setup
968 */
969 for (port = 0; port < DSA_MAX_PORTS; port++) {
970 if ((1 << port) & ds->phys_port_mask ||
971 dsa_is_cpu_port(ds, port))
b6d045db 972 bcm_sf2_port_disable(ds, port, NULL);
8cfa9498
FF		 973 }
974
975 return 0;
976}
977
8cfa9498
FF		 978static int bcm_sf2_sw_resume(struct dsa_switch *ds)
979{
980 struct bcm_sf2_priv *priv = ds_to_priv(ds);
981 unsigned int port;
8cfa9498
FF		 982 int ret;
983
984 ret = bcm_sf2_sw_rst(priv);
985 if (ret) {
986 pr_err("%s: failed to software reset switch\n", __func__);
987 return ret;
988 }
989
b083668c
FF		 990 if (priv->hw_params.num_gphy == 1)
991 bcm_sf2_gphy_enable_set(ds, true);
8cfa9498
FF		 992
993 for (port = 0; port < DSA_MAX_PORTS; port++) {
994 if ((1 << port) & ds->phys_port_mask)
b6d045db 995 bcm_sf2_port_setup(ds, port, NULL);
8cfa9498
FF		 996 else if (dsa_is_cpu_port(ds, port))
997 bcm_sf2_imp_setup(ds, port);
998 }
999
1000 return 0;
1001}
1002
96e65d7f
FF		 1003static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1004 struct ethtool_wolinfo *wol)
1005{
1006 struct net_device *p = ds->dst[ds->index].master_netdev;
1007 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1008 struct ethtool_wolinfo pwol;
1009
1010 /* Get the parent device WoL settings */
1011 p->ethtool_ops->get_wol(p, &pwol);
1012
1013 /* Advertise the parent device supported settings */
1014 wol->supported = pwol.supported;
1015 memset(&wol->sopass, 0, sizeof(wol->sopass));
1016
1017 if (pwol.wolopts & WAKE_MAGICSECURE)
1018 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1019
1020 if (priv->wol_ports_mask & (1 << port))
1021 wol->wolopts = pwol.wolopts;
1022 else
1023 wol->wolopts = 0;
1024}
1025
1026static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1027 struct ethtool_wolinfo *wol)
1028{
1029 struct net_device *p = ds->dst[ds->index].master_netdev;
1030 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1031 s8 cpu_port = ds->dst[ds->index].cpu_port;
1032 struct ethtool_wolinfo pwol;
1033
1034 p->ethtool_ops->get_wol(p, &pwol);
1035 if (wol->wolopts & ~pwol.supported)
1036 return -EINVAL;
1037
1038 if (wol->wolopts)
1039 priv->wol_ports_mask |= (1 << port);
1040 else
1041 priv->wol_ports_mask &= ~(1 << port);
1042
1043 /* If we have at least one port enabled, make sure the CPU port
1044 * is also enabled. If the CPU port is the last one enabled, we disable
1045 * it since this configuration does not make sense.
1046 */
1047 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1048 priv->wol_ports_mask |= (1 << cpu_port);
1049 else
1050 priv->wol_ports_mask &= ~(1 << cpu_port);
1051
1052 return p->ethtool_ops->set_wol(p, wol);
1053}
1054
246d7f77 1055static struct dsa_switch_driver bcm_sf2_switch_driver = {
ac7a04c3 1056 .tag_protocol = DSA_TAG_PROTO_BRCM,
246d7f77
FF		 1057 .priv_size = sizeof(struct bcm_sf2_priv),
1058 .probe = bcm_sf2_sw_probe,
1059 .setup = bcm_sf2_sw_setup,
1060 .set_addr = bcm_sf2_sw_set_addr,
aa9aef77 1061 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
246d7f77
FF		 1062 .phy_read = bcm_sf2_sw_phy_read,
1063 .phy_write = bcm_sf2_sw_phy_write,
1064 .get_strings = bcm_sf2_sw_get_strings,
1065 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1066 .get_sset_count = bcm_sf2_sw_get_sset_count,
1067 .adjust_link = bcm_sf2_sw_adjust_link,
1068 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
8cfa9498
FF		 1069 .suspend = bcm_sf2_sw_suspend,
1070 .resume = bcm_sf2_sw_resume,
96e65d7f
FF		 1071 .get_wol = bcm_sf2_sw_get_wol,
1072 .set_wol = bcm_sf2_sw_set_wol,
b6d045db
FF		 1073 .port_enable = bcm_sf2_port_setup,
1074 .port_disable = bcm_sf2_port_disable,
450b05c1
FF		 1075 .get_eee = bcm_sf2_sw_get_eee,
1076 .set_eee = bcm_sf2_sw_set_eee,
12f460f2
FF		 1077 .port_join_bridge = bcm_sf2_sw_br_join,
1078 .port_leave_bridge = bcm_sf2_sw_br_leave,
1079 .port_stp_update = bcm_sf2_sw_br_set_stp_state,
246d7f77
FF		 1080};
1081
1082static int __init bcm_sf2_init(void)
1083{
1084 register_switch_driver(&bcm_sf2_switch_driver);
1085
1086 return 0;
1087}
1088module_init(bcm_sf2_init);
1089
1090static void __exit bcm_sf2_exit(void)
1091{
1092 unregister_switch_driver(&bcm_sf2_switch_driver);
1093}
1094module_exit(bcm_sf2_exit);
1095
1096MODULE_AUTHOR("Broadcom Corporation");
1097MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1098MODULE_LICENSE("GPL");
1099MODULE_ALIAS("platform:brcm-sf2");
Linux kernel - Deliverables
This page took 0.118032 seconds and 5 git commands to generate.