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2e16a77e LB |
1 | /* |
2 | * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
2e16a77e LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
2e16a77e | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
2e16a77e LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
2e16a77e LB |
18 | |
19 | #define REG_PORT(p) (8 + (p)) | |
20 | #define REG_GLOBAL 0x0f | |
21 | ||
22 | static int reg_read(struct dsa_switch *ds, int addr, int reg) | |
23 | { | |
b4d2394d AD |
24 | return mdiobus_read(to_mii_bus(ds->master_dev), |
25 | ds->pd->sw_addr + addr, reg); | |
2e16a77e LB |
26 | } |
27 | ||
28 | #define REG_READ(addr, reg) \ | |
29 | ({ \ | |
30 | int __ret; \ | |
31 | \ | |
32 | __ret = reg_read(ds, addr, reg); \ | |
33 | if (__ret < 0) \ | |
34 | return __ret; \ | |
35 | __ret; \ | |
36 | }) | |
37 | ||
38 | ||
39 | static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
40 | { | |
b4d2394d AD |
41 | return mdiobus_write(to_mii_bus(ds->master_dev), |
42 | ds->pd->sw_addr + addr, reg, val); | |
2e16a77e LB |
43 | } |
44 | ||
45 | #define REG_WRITE(addr, reg, val) \ | |
46 | ({ \ | |
47 | int __ret; \ | |
48 | \ | |
49 | __ret = reg_write(ds, addr, reg, val); \ | |
50 | if (__ret < 0) \ | |
51 | return __ret; \ | |
52 | }) | |
53 | ||
b4d2394d | 54 | static char *mv88e6060_probe(struct device *host_dev, int sw_addr) |
2e16a77e | 55 | { |
b4d2394d | 56 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
2e16a77e LB |
57 | int ret; |
58 | ||
b4d2394d AD |
59 | if (bus == NULL) |
60 | return NULL; | |
61 | ||
fdb838cd | 62 | ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03); |
2e16a77e LB |
63 | if (ret >= 0) { |
64 | ret &= 0xfff0; | |
65 | if (ret == 0x0600) | |
66 | return "Marvell 88E6060"; | |
67 | } | |
68 | ||
69 | return NULL; | |
70 | } | |
71 | ||
72 | static int mv88e6060_switch_reset(struct dsa_switch *ds) | |
73 | { | |
74 | int i; | |
75 | int ret; | |
19b2f97e | 76 | unsigned long timeout; |
2e16a77e | 77 | |
3675c8d7 | 78 | /* Set all ports to the disabled state. */ |
2e16a77e LB |
79 | for (i = 0; i < 6; i++) { |
80 | ret = REG_READ(REG_PORT(i), 0x04); | |
81 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
82 | } | |
83 | ||
3675c8d7 | 84 | /* Wait for transmit queues to drain. */ |
19b2f97e | 85 | usleep_range(2000, 4000); |
2e16a77e | 86 | |
3675c8d7 | 87 | /* Reset the switch. */ |
e84665c9 | 88 | REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); |
2e16a77e | 89 | |
3675c8d7 | 90 | /* Wait up to one second for reset to complete. */ |
19b2f97e BG |
91 | timeout = jiffies + 1 * HZ; |
92 | while (time_before(jiffies, timeout)) { | |
2e16a77e LB |
93 | ret = REG_READ(REG_GLOBAL, 0x00); |
94 | if ((ret & 0x8000) == 0x0000) | |
95 | break; | |
96 | ||
19b2f97e | 97 | usleep_range(1000, 2000); |
2e16a77e | 98 | } |
19b2f97e | 99 | if (time_after(jiffies, timeout)) |
2e16a77e LB |
100 | return -ETIMEDOUT; |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static int mv88e6060_setup_global(struct dsa_switch *ds) | |
106 | { | |
3675c8d7 | 107 | /* Disable discarding of frames with excessive collisions, |
2e16a77e LB |
108 | * set the maximum frame size to 1536 bytes, and mask all |
109 | * interrupt sources. | |
110 | */ | |
111 | REG_WRITE(REG_GLOBAL, 0x04, 0x0800); | |
112 | ||
3675c8d7 | 113 | /* Enable automatic address learning, set the address |
2e16a77e LB |
114 | * database size to 1024 entries, and set the default aging |
115 | * time to 5 minutes. | |
116 | */ | |
117 | REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | static int mv88e6060_setup_port(struct dsa_switch *ds, int p) | |
123 | { | |
124 | int addr = REG_PORT(p); | |
125 | ||
3675c8d7 | 126 | /* Do not force flow control, disable Ingress and Egress |
2e16a77e LB |
127 | * Header tagging, disable VLAN tunneling, and set the port |
128 | * state to Forwarding. Additionally, if this is the CPU | |
129 | * port, enable Ingress and Egress Trailer tagging mode. | |
130 | */ | |
e84665c9 | 131 | REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); |
2e16a77e | 132 | |
3675c8d7 | 133 | /* Port based VLAN map: give each port its own address |
2e16a77e LB |
134 | * database, allow the CPU port to talk to each of the 'real' |
135 | * ports, and allow each of the 'real' ports to only talk to | |
136 | * the CPU port. | |
137 | */ | |
138 | REG_WRITE(addr, 0x06, | |
139 | ((p & 0xf) << 12) | | |
e84665c9 LB |
140 | (dsa_is_cpu_port(ds, p) ? |
141 | ds->phys_port_mask : | |
142 | (1 << ds->dst->cpu_port))); | |
2e16a77e | 143 | |
3675c8d7 | 144 | /* Port Association Vector: when learning source addresses |
2e16a77e LB |
145 | * of packets, add the address to the address database using |
146 | * a port bitmap that has only the bit for this port set and | |
147 | * the other bits clear. | |
148 | */ | |
149 | REG_WRITE(addr, 0x0b, 1 << p); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int mv88e6060_setup(struct dsa_switch *ds) | |
155 | { | |
156 | int i; | |
157 | int ret; | |
158 | ||
159 | ret = mv88e6060_switch_reset(ds); | |
160 | if (ret < 0) | |
161 | return ret; | |
162 | ||
163 | /* @@@ initialise atu */ | |
164 | ||
165 | ret = mv88e6060_setup_global(ds); | |
166 | if (ret < 0) | |
167 | return ret; | |
168 | ||
169 | for (i = 0; i < 6; i++) { | |
170 | ret = mv88e6060_setup_port(ds, i); | |
171 | if (ret < 0) | |
172 | return ret; | |
173 | } | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr) | |
179 | { | |
180 | REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); | |
181 | REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); | |
182 | REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
187 | static int mv88e6060_port_to_phy_addr(int port) | |
188 | { | |
189 | if (port >= 0 && port <= 5) | |
190 | return port; | |
191 | return -1; | |
192 | } | |
193 | ||
194 | static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) | |
195 | { | |
196 | int addr; | |
197 | ||
198 | addr = mv88e6060_port_to_phy_addr(port); | |
199 | if (addr == -1) | |
200 | return 0xffff; | |
201 | ||
202 | return reg_read(ds, addr, regnum); | |
203 | } | |
204 | ||
205 | static int | |
206 | mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
207 | { | |
208 | int addr; | |
209 | ||
210 | addr = mv88e6060_port_to_phy_addr(port); | |
211 | if (addr == -1) | |
212 | return 0xffff; | |
213 | ||
214 | return reg_write(ds, addr, regnum, val); | |
215 | } | |
216 | ||
217 | static void mv88e6060_poll_link(struct dsa_switch *ds) | |
218 | { | |
219 | int i; | |
220 | ||
221 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
222 | struct net_device *dev; | |
d3f644da | 223 | int uninitialized_var(port_status); |
2e16a77e LB |
224 | int link; |
225 | int speed; | |
226 | int duplex; | |
227 | int fc; | |
228 | ||
229 | dev = ds->ports[i]; | |
230 | if (dev == NULL) | |
231 | continue; | |
232 | ||
233 | link = 0; | |
234 | if (dev->flags & IFF_UP) { | |
235 | port_status = reg_read(ds, REG_PORT(i), 0x00); | |
236 | if (port_status < 0) | |
237 | continue; | |
238 | ||
239 | link = !!(port_status & 0x1000); | |
240 | } | |
241 | ||
242 | if (!link) { | |
243 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 244 | netdev_info(dev, "link down\n"); |
2e16a77e LB |
245 | netif_carrier_off(dev); |
246 | } | |
247 | continue; | |
248 | } | |
249 | ||
250 | speed = (port_status & 0x0100) ? 100 : 10; | |
251 | duplex = (port_status & 0x0200) ? 1 : 0; | |
252 | fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; | |
253 | ||
254 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
255 | netdev_info(dev, |
256 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
257 | speed, | |
258 | duplex ? "full" : "half", | |
259 | fc ? "en" : "dis"); | |
2e16a77e LB |
260 | netif_carrier_on(dev); |
261 | } | |
262 | } | |
263 | } | |
264 | ||
265 | static struct dsa_switch_driver mv88e6060_switch_driver = { | |
ac7a04c3 | 266 | .tag_protocol = DSA_TAG_PROTO_TRAILER, |
2e16a77e LB |
267 | .probe = mv88e6060_probe, |
268 | .setup = mv88e6060_setup, | |
269 | .set_addr = mv88e6060_set_addr, | |
270 | .phy_read = mv88e6060_phy_read, | |
271 | .phy_write = mv88e6060_phy_write, | |
272 | .poll_link = mv88e6060_poll_link, | |
273 | }; | |
274 | ||
5eaa65b2 | 275 | static int __init mv88e6060_init(void) |
2e16a77e LB |
276 | { |
277 | register_switch_driver(&mv88e6060_switch_driver); | |
278 | return 0; | |
279 | } | |
280 | module_init(mv88e6060_init); | |
281 | ||
5eaa65b2 | 282 | static void __exit mv88e6060_cleanup(void) |
2e16a77e LB |
283 | { |
284 | unregister_switch_driver(&mv88e6060_switch_driver); | |
285 | } | |
286 | module_exit(mv88e6060_cleanup); | |
3d825ede BH |
287 | |
288 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
289 | MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip"); | |
290 | MODULE_LICENSE("GPL"); | |
291 | MODULE_ALIAS("platform:mv88e6060"); |