Commit | Line | Data |
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3ad50cca GR |
1 | /* |
2 | * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support | |
3 | * | |
4 | * Copyright (c) 2014 Guenter Roeck | |
5 | * | |
6 | * Derived from mv88e6123_61_65.c | |
7 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/jiffies.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/phy.h> | |
22 | #include <net/dsa.h> | |
23 | #include "mv88e6xxx.h" | |
24 | ||
3ad50cca GR |
25 | static char *mv88e6352_probe(struct device *host_dev, int sw_addr) |
26 | { | |
27 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); | |
28 | int ret; | |
29 | ||
30 | if (bus == NULL) | |
31 | return NULL; | |
32 | ||
33 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); | |
34 | if (ret >= 0) { | |
2716777b GR |
35 | if ((ret & 0xfff0) == 0x1760) |
36 | return "Marvell 88E6176"; | |
3ad50cca GR |
37 | if (ret == 0x3521) |
38 | return "Marvell 88E6352 (A0)"; | |
39 | if (ret == 0x3522) | |
40 | return "Marvell 88E6352 (A1)"; | |
41 | if ((ret & 0xfff0) == 0x3520) | |
42 | return "Marvell 88E6352"; | |
43 | } | |
44 | ||
45 | return NULL; | |
46 | } | |
47 | ||
48 | static int mv88e6352_switch_reset(struct dsa_switch *ds) | |
49 | { | |
44e50ddb | 50 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3ad50cca GR |
51 | unsigned long timeout; |
52 | int ret; | |
53 | int i; | |
54 | ||
55 | /* Set all ports to the disabled state. */ | |
44e50ddb | 56 | for (i = 0; i < ps->num_ports; i++) { |
3ad50cca GR |
57 | ret = REG_READ(REG_PORT(i), 0x04); |
58 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
59 | } | |
60 | ||
61 | /* Wait for transmit queues to drain. */ | |
62 | usleep_range(2000, 4000); | |
63 | ||
64 | /* Reset the switch. Keep PPU active (bit 14, undocumented). | |
65 | * The PPU needs to be active to support indirect phy register | |
66 | * accesses through global registers 0x18 and 0x19. | |
67 | */ | |
68 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
69 | ||
70 | /* Wait up to one second for reset to complete. */ | |
71 | timeout = jiffies + 1 * HZ; | |
72 | while (time_before(jiffies, timeout)) { | |
73 | ret = REG_READ(REG_GLOBAL, 0x00); | |
74 | if ((ret & 0x8800) == 0x8800) | |
75 | break; | |
76 | usleep_range(1000, 2000); | |
77 | } | |
78 | if (time_after(jiffies, timeout)) | |
79 | return -ETIMEDOUT; | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
84 | static int mv88e6352_setup_global(struct dsa_switch *ds) | |
85 | { | |
44e50ddb | 86 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3ad50cca GR |
87 | int ret; |
88 | int i; | |
89 | ||
90 | /* Discard packets with excessive collisions, | |
91 | * mask all interrupt sources, enable PPU (bit 14, undocumented). | |
92 | */ | |
93 | REG_WRITE(REG_GLOBAL, 0x04, 0x6000); | |
94 | ||
95 | /* Set the default address aging time to 5 minutes, and | |
96 | * enable address learn messages to be sent to all message | |
97 | * ports. | |
98 | */ | |
99 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
100 | ||
101 | /* Configure the priority mapping registers. */ | |
102 | ret = mv88e6xxx_config_prio(ds); | |
103 | if (ret < 0) | |
104 | return ret; | |
105 | ||
106 | /* Configure the upstream port, and configure the upstream | |
107 | * port as the port to which ingress and egress monitor frames | |
108 | * are to be sent. | |
109 | */ | |
110 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); | |
111 | ||
112 | /* Disable remote management for now, and set the switch's | |
113 | * DSA device number. | |
114 | */ | |
115 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); | |
116 | ||
117 | /* Send all frames with destination addresses matching | |
118 | * 01:80:c2:00:00:2x to the CPU port. | |
119 | */ | |
120 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | |
121 | ||
122 | /* Send all frames with destination addresses matching | |
123 | * 01:80:c2:00:00:0x to the CPU port. | |
124 | */ | |
125 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
126 | ||
127 | /* Disable the loopback filter, disable flow control | |
128 | * messages, disable flood broadcast override, disable | |
129 | * removing of provider tags, disable ATU age violation | |
130 | * interrupts, disable tag flow control, force flow | |
131 | * control priority to the highest, and send all special | |
132 | * multicast frames to the CPU at the highest priority. | |
133 | */ | |
134 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
135 | ||
136 | /* Program the DSA routing table. */ | |
137 | for (i = 0; i < 32; i++) { | |
138 | int nexthop = 0x1f; | |
139 | ||
140 | if (i != ds->index && i < ds->dst->pd->nr_chips) | |
141 | nexthop = ds->pd->rtable[i] & 0x1f; | |
142 | ||
143 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
144 | } | |
145 | ||
146 | /* Clear all trunk masks. */ | |
147 | for (i = 0; i < 8; i++) | |
148 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f); | |
149 | ||
150 | /* Clear all trunk mappings. */ | |
151 | for (i = 0; i < 16; i++) | |
152 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
153 | ||
154 | /* Disable ingress rate limiting by resetting all ingress | |
155 | * rate limit registers to their initial state. | |
156 | */ | |
44e50ddb | 157 | for (i = 0; i < ps->num_ports; i++) |
3ad50cca GR |
158 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); |
159 | ||
160 | /* Initialise cross-chip port VLAN table to reset defaults. */ | |
161 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); | |
162 | ||
163 | /* Clear the priority override table. */ | |
164 | for (i = 0; i < 16; i++) | |
165 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | |
166 | ||
167 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static int mv88e6352_setup_port(struct dsa_switch *ds, int p) | |
173 | { | |
174 | int addr = REG_PORT(p); | |
175 | u16 val; | |
176 | ||
177 | /* MAC Forcing register: don't force link, speed, duplex | |
178 | * or flow control state to any particular values on physical | |
179 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | |
180 | * full duplex. | |
181 | */ | |
182 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) | |
183 | REG_WRITE(addr, 0x01, 0x003e); | |
184 | else | |
185 | REG_WRITE(addr, 0x01, 0x0003); | |
186 | ||
187 | /* Do not limit the period of time that this port can be | |
188 | * paused for by the remote end or the period of time that | |
189 | * this port can pause the remote end. | |
190 | */ | |
191 | REG_WRITE(addr, 0x02, 0x0000); | |
192 | ||
193 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
194 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
195 | * tunneling, determine priority by looking at 802.1p and IP | |
196 | * priority fields (IP prio has precedence), and set STP state | |
197 | * to Forwarding. | |
198 | * | |
199 | * If this is the CPU link, use DSA or EDSA tagging depending | |
200 | * on which tagging mode was configured. | |
201 | * | |
202 | * If this is a link to another switch, use DSA tagging mode. | |
203 | * | |
204 | * If this is the upstream port for this switch, enable | |
205 | * forwarding of unknown unicasts and multicasts. | |
206 | */ | |
207 | val = 0x0433; | |
208 | if (dsa_is_cpu_port(ds, p)) { | |
209 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
210 | val |= 0x3300; | |
211 | else | |
212 | val |= 0x0100; | |
213 | } | |
214 | if (ds->dsa_port_mask & (1 << p)) | |
215 | val |= 0x0100; | |
216 | if (p == dsa_upstream_port(ds)) | |
217 | val |= 0x000c; | |
218 | REG_WRITE(addr, 0x04, val); | |
219 | ||
3ad50cca GR |
220 | /* Port Control 2: don't force a good FCS, set the maximum |
221 | * frame size to 10240 bytes, don't let the switch add or | |
222 | * strip 802.1q tags, don't discard tagged or untagged frames | |
223 | * on this port, do a destination address lookup on all | |
224 | * received packets as usual, disable ARP mirroring and don't | |
225 | * send a copy of all transmitted/received frames on this port | |
226 | * to the CPU. | |
227 | */ | |
228 | REG_WRITE(addr, 0x08, 0x2080); | |
229 | ||
230 | /* Egress rate control: disable egress rate control. */ | |
231 | REG_WRITE(addr, 0x09, 0x0001); | |
232 | ||
233 | /* Egress rate control 2: disable egress rate control. */ | |
234 | REG_WRITE(addr, 0x0a, 0x0000); | |
235 | ||
236 | /* Port Association Vector: when learning source addresses | |
237 | * of packets, add the address to the address database using | |
238 | * a port bitmap that has only the bit for this port set and | |
239 | * the other bits clear. | |
240 | */ | |
241 | REG_WRITE(addr, 0x0b, 1 << p); | |
242 | ||
243 | /* Port ATU control: disable limiting the number of address | |
244 | * database entries that this port is allowed to use. | |
245 | */ | |
246 | REG_WRITE(addr, 0x0c, 0x0000); | |
247 | ||
248 | /* Priority Override: disable DA, SA and VTU priority override. */ | |
249 | REG_WRITE(addr, 0x0d, 0x0000); | |
250 | ||
251 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ | |
252 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); | |
253 | ||
254 | /* Tag Remap: use an identity 802.1p prio -> switch prio | |
255 | * mapping. | |
256 | */ | |
257 | REG_WRITE(addr, 0x18, 0x3210); | |
258 | ||
259 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio | |
260 | * mapping. | |
261 | */ | |
262 | REG_WRITE(addr, 0x19, 0x7654); | |
263 | ||
2089052f | 264 | return mv88e6xxx_setup_port_common(ds, p); |
3ad50cca GR |
265 | } |
266 | ||
276db3b1 GR |
267 | #ifdef CONFIG_NET_DSA_HWMON |
268 | ||
269 | static int mv88e6352_phy_page_read(struct dsa_switch *ds, | |
270 | int port, int page, int reg) | |
271 | { | |
272 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
273 | int ret; | |
274 | ||
275 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 276 | ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
276db3b1 GR |
277 | if (ret < 0) |
278 | goto error; | |
f3044683 | 279 | ret = mv88e6xxx_phy_read_indirect(ds, port, reg); |
276db3b1 | 280 | error: |
f3044683 | 281 | mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
276db3b1 GR |
282 | mutex_unlock(&ps->phy_mutex); |
283 | return ret; | |
284 | } | |
285 | ||
286 | static int mv88e6352_phy_page_write(struct dsa_switch *ds, | |
287 | int port, int page, int reg, int val) | |
288 | { | |
289 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
290 | int ret; | |
291 | ||
292 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 293 | ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
276db3b1 GR |
294 | if (ret < 0) |
295 | goto error; | |
296 | ||
f3044683 | 297 | ret = mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
276db3b1 | 298 | error: |
f3044683 | 299 | mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
276db3b1 GR |
300 | mutex_unlock(&ps->phy_mutex); |
301 | return ret; | |
302 | } | |
303 | ||
304 | static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp) | |
305 | { | |
306 | int ret; | |
307 | ||
308 | *temp = 0; | |
309 | ||
310 | ret = mv88e6352_phy_page_read(ds, 0, 6, 27); | |
311 | if (ret < 0) | |
312 | return ret; | |
313 | ||
314 | *temp = (ret & 0xff) - 25; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp) | |
320 | { | |
321 | int ret; | |
322 | ||
323 | *temp = 0; | |
324 | ||
325 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
326 | if (ret < 0) | |
327 | return ret; | |
328 | ||
329 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp) | |
335 | { | |
336 | int ret; | |
337 | ||
338 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
339 | if (ret < 0) | |
340 | return ret; | |
341 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
342 | return mv88e6352_phy_page_write(ds, 0, 6, 26, | |
343 | (ret & 0xe0ff) | (temp << 8)); | |
344 | } | |
345 | ||
346 | static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
347 | { | |
348 | int ret; | |
349 | ||
350 | *alarm = false; | |
351 | ||
352 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
353 | if (ret < 0) | |
354 | return ret; | |
355 | ||
356 | *alarm = !!(ret & 0x40); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | #endif /* CONFIG_NET_DSA_HWMON */ | |
361 | ||
3ad50cca GR |
362 | static int mv88e6352_setup(struct dsa_switch *ds) |
363 | { | |
364 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
365 | int ret; | |
366 | int i; | |
367 | ||
acdaffcc GR |
368 | ret = mv88e6xxx_setup_common(ds); |
369 | if (ret < 0) | |
370 | return ret; | |
371 | ||
44e50ddb AL |
372 | ps->num_ports = 7; |
373 | ||
33b43df4 | 374 | mutex_init(&ps->eeprom_mutex); |
3ad50cca | 375 | |
3ad50cca GR |
376 | ret = mv88e6352_switch_reset(ds); |
377 | if (ret < 0) | |
378 | return ret; | |
379 | ||
380 | /* @@@ initialise vtu and atu */ | |
381 | ||
382 | ret = mv88e6352_setup_global(ds); | |
383 | if (ret < 0) | |
384 | return ret; | |
385 | ||
44e50ddb | 386 | for (i = 0; i < ps->num_ports; i++) { |
3ad50cca GR |
387 | ret = mv88e6352_setup_port(ds, i); |
388 | if (ret < 0) | |
389 | return ret; | |
390 | } | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static int mv88e6352_port_to_phy_addr(int port) | |
396 | { | |
397 | if (port >= 0 && port <= 4) | |
398 | return port; | |
399 | return -EINVAL; | |
400 | } | |
401 | ||
402 | static int | |
403 | mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum) | |
404 | { | |
405 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
406 | int addr = mv88e6352_port_to_phy_addr(port); | |
407 | int ret; | |
408 | ||
409 | if (addr < 0) | |
410 | return addr; | |
411 | ||
412 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 413 | ret = mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3ad50cca GR |
414 | mutex_unlock(&ps->phy_mutex); |
415 | ||
416 | return ret; | |
417 | } | |
418 | ||
419 | static int | |
420 | mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
421 | { | |
422 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
423 | int addr = mv88e6352_port_to_phy_addr(port); | |
424 | int ret; | |
425 | ||
426 | if (addr < 0) | |
427 | return addr; | |
428 | ||
429 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 430 | ret = mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3ad50cca GR |
431 | mutex_unlock(&ps->phy_mutex); |
432 | ||
433 | return ret; | |
434 | } | |
435 | ||
436 | static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = { | |
437 | { "in_good_octets", 8, 0x00, }, | |
438 | { "in_bad_octets", 4, 0x02, }, | |
439 | { "in_unicast", 4, 0x04, }, | |
440 | { "in_broadcasts", 4, 0x06, }, | |
441 | { "in_multicasts", 4, 0x07, }, | |
442 | { "in_pause", 4, 0x16, }, | |
443 | { "in_undersize", 4, 0x18, }, | |
444 | { "in_fragments", 4, 0x19, }, | |
445 | { "in_oversize", 4, 0x1a, }, | |
446 | { "in_jabber", 4, 0x1b, }, | |
447 | { "in_rx_error", 4, 0x1c, }, | |
448 | { "in_fcs_error", 4, 0x1d, }, | |
449 | { "out_octets", 8, 0x0e, }, | |
450 | { "out_unicast", 4, 0x10, }, | |
451 | { "out_broadcasts", 4, 0x13, }, | |
452 | { "out_multicasts", 4, 0x12, }, | |
453 | { "out_pause", 4, 0x15, }, | |
454 | { "excessive", 4, 0x11, }, | |
455 | { "collisions", 4, 0x1e, }, | |
456 | { "deferred", 4, 0x05, }, | |
457 | { "single", 4, 0x14, }, | |
458 | { "multiple", 4, 0x17, }, | |
459 | { "out_fcs_error", 4, 0x03, }, | |
460 | { "late", 4, 0x1f, }, | |
461 | { "hist_64bytes", 4, 0x08, }, | |
462 | { "hist_65_127bytes", 4, 0x09, }, | |
463 | { "hist_128_255bytes", 4, 0x0a, }, | |
464 | { "hist_256_511bytes", 4, 0x0b, }, | |
465 | { "hist_512_1023bytes", 4, 0x0c, }, | |
466 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
17ee3e04 GR |
467 | { "sw_in_discards", 4, 0x110, }, |
468 | { "sw_in_filtered", 2, 0x112, }, | |
469 | { "sw_out_filtered", 2, 0x113, }, | |
3ad50cca GR |
470 | }; |
471 | ||
33b43df4 GR |
472 | static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr) |
473 | { | |
474 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
475 | int ret; | |
476 | ||
477 | mutex_lock(&ps->eeprom_mutex); | |
478 | ||
479 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
480 | 0xc000 | (addr & 0xff)); | |
481 | if (ret < 0) | |
482 | goto error; | |
483 | ||
f3044683 | 484 | ret = mv88e6xxx_eeprom_busy_wait(ds); |
33b43df4 GR |
485 | if (ret < 0) |
486 | goto error; | |
487 | ||
488 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15); | |
489 | error: | |
490 | mutex_unlock(&ps->eeprom_mutex); | |
491 | return ret; | |
492 | } | |
493 | ||
494 | static int mv88e6352_get_eeprom(struct dsa_switch *ds, | |
495 | struct ethtool_eeprom *eeprom, u8 *data) | |
496 | { | |
497 | int offset; | |
498 | int len; | |
499 | int ret; | |
500 | ||
501 | offset = eeprom->offset; | |
502 | len = eeprom->len; | |
503 | eeprom->len = 0; | |
504 | ||
505 | eeprom->magic = 0xc3ec4951; | |
506 | ||
f3044683 | 507 | ret = mv88e6xxx_eeprom_load_wait(ds); |
33b43df4 GR |
508 | if (ret < 0) |
509 | return ret; | |
510 | ||
511 | if (offset & 1) { | |
512 | int word; | |
513 | ||
514 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
515 | if (word < 0) | |
516 | return word; | |
517 | ||
518 | *data++ = (word >> 8) & 0xff; | |
519 | ||
520 | offset++; | |
521 | len--; | |
522 | eeprom->len++; | |
523 | } | |
524 | ||
525 | while (len >= 2) { | |
526 | int word; | |
527 | ||
528 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
529 | if (word < 0) | |
530 | return word; | |
531 | ||
532 | *data++ = word & 0xff; | |
533 | *data++ = (word >> 8) & 0xff; | |
534 | ||
535 | offset += 2; | |
536 | len -= 2; | |
537 | eeprom->len += 2; | |
538 | } | |
539 | ||
540 | if (len) { | |
541 | int word; | |
542 | ||
543 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
544 | if (word < 0) | |
545 | return word; | |
546 | ||
547 | *data++ = word & 0xff; | |
548 | ||
549 | offset++; | |
550 | len--; | |
551 | eeprom->len++; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds) | |
558 | { | |
559 | int ret; | |
560 | ||
561 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14); | |
562 | if (ret < 0) | |
563 | return ret; | |
564 | ||
565 | if (!(ret & 0x0400)) | |
566 | return -EROFS; | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr, | |
572 | u16 data) | |
573 | { | |
574 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
575 | int ret; | |
576 | ||
577 | mutex_lock(&ps->eeprom_mutex); | |
578 | ||
579 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data); | |
580 | if (ret < 0) | |
581 | goto error; | |
582 | ||
583 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
584 | 0xb000 | (addr & 0xff)); | |
585 | if (ret < 0) | |
586 | goto error; | |
587 | ||
f3044683 | 588 | ret = mv88e6xxx_eeprom_busy_wait(ds); |
33b43df4 GR |
589 | error: |
590 | mutex_unlock(&ps->eeprom_mutex); | |
591 | return ret; | |
592 | } | |
593 | ||
594 | static int mv88e6352_set_eeprom(struct dsa_switch *ds, | |
595 | struct ethtool_eeprom *eeprom, u8 *data) | |
596 | { | |
597 | int offset; | |
598 | int ret; | |
599 | int len; | |
600 | ||
601 | if (eeprom->magic != 0xc3ec4951) | |
602 | return -EINVAL; | |
603 | ||
604 | ret = mv88e6352_eeprom_is_readonly(ds); | |
605 | if (ret) | |
606 | return ret; | |
607 | ||
608 | offset = eeprom->offset; | |
609 | len = eeprom->len; | |
610 | eeprom->len = 0; | |
611 | ||
f3044683 | 612 | ret = mv88e6xxx_eeprom_load_wait(ds); |
33b43df4 GR |
613 | if (ret < 0) |
614 | return ret; | |
615 | ||
616 | if (offset & 1) { | |
617 | int word; | |
618 | ||
619 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
620 | if (word < 0) | |
621 | return word; | |
622 | ||
623 | word = (*data++ << 8) | (word & 0xff); | |
624 | ||
625 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
626 | if (ret < 0) | |
627 | return ret; | |
628 | ||
629 | offset++; | |
630 | len--; | |
631 | eeprom->len++; | |
632 | } | |
633 | ||
634 | while (len >= 2) { | |
635 | int word; | |
636 | ||
637 | word = *data++; | |
638 | word |= *data++ << 8; | |
639 | ||
640 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
641 | if (ret < 0) | |
642 | return ret; | |
643 | ||
644 | offset += 2; | |
645 | len -= 2; | |
646 | eeprom->len += 2; | |
647 | } | |
648 | ||
649 | if (len) { | |
650 | int word; | |
651 | ||
652 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
653 | if (word < 0) | |
654 | return word; | |
655 | ||
656 | word = (word & 0xff00) | *data++; | |
657 | ||
658 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
659 | if (ret < 0) | |
660 | return ret; | |
661 | ||
662 | offset++; | |
663 | len--; | |
664 | eeprom->len++; | |
665 | } | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
3ad50cca GR |
670 | static void |
671 | mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
672 | { | |
673 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
674 | mv88e6352_hw_stats, port, data); | |
675 | } | |
676 | ||
677 | static void | |
678 | mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) | |
679 | { | |
680 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
681 | mv88e6352_hw_stats, port, data); | |
682 | } | |
683 | ||
684 | static int mv88e6352_get_sset_count(struct dsa_switch *ds) | |
685 | { | |
686 | return ARRAY_SIZE(mv88e6352_hw_stats); | |
687 | } | |
688 | ||
689 | struct dsa_switch_driver mv88e6352_switch_driver = { | |
690 | .tag_protocol = DSA_TAG_PROTO_EDSA, | |
691 | .priv_size = sizeof(struct mv88e6xxx_priv_state), | |
692 | .probe = mv88e6352_probe, | |
693 | .setup = mv88e6352_setup, | |
694 | .set_addr = mv88e6xxx_set_addr_indirect, | |
695 | .phy_read = mv88e6352_phy_read, | |
696 | .phy_write = mv88e6352_phy_write, | |
697 | .poll_link = mv88e6xxx_poll_link, | |
698 | .get_strings = mv88e6352_get_strings, | |
699 | .get_ethtool_stats = mv88e6352_get_ethtool_stats, | |
700 | .get_sset_count = mv88e6352_get_sset_count, | |
04b0a80b GR |
701 | .set_eee = mv88e6xxx_set_eee, |
702 | .get_eee = mv88e6xxx_get_eee, | |
276db3b1 GR |
703 | #ifdef CONFIG_NET_DSA_HWMON |
704 | .get_temp = mv88e6352_get_temp, | |
705 | .get_temp_limit = mv88e6352_get_temp_limit, | |
706 | .set_temp_limit = mv88e6352_set_temp_limit, | |
707 | .get_temp_alarm = mv88e6352_get_temp_alarm, | |
708 | #endif | |
33b43df4 GR |
709 | .get_eeprom = mv88e6352_get_eeprom, |
710 | .set_eeprom = mv88e6352_set_eeprom, | |
95d08b5a GR |
711 | .get_regs_len = mv88e6xxx_get_regs_len, |
712 | .get_regs = mv88e6xxx_get_regs, | |
3f244abb GR |
713 | .port_join_bridge = mv88e6xxx_join_bridge, |
714 | .port_leave_bridge = mv88e6xxx_leave_bridge, | |
715 | .port_stp_update = mv88e6xxx_port_stp_update, | |
4f431e56 GR |
716 | .fdb_add = mv88e6xxx_port_fdb_add, |
717 | .fdb_del = mv88e6xxx_port_fdb_del, | |
718 | .fdb_getnext = mv88e6xxx_port_fdb_getnext, | |
3ad50cca GR |
719 | }; |
720 | ||
721 | MODULE_ALIAS("platform:mv88e6352"); |