projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 91da11f8 | 1 | /* |
| 0d3cd4b6 VD |
2 | * Marvell 88e6xxx common definitions |
| 3 | * | |
| 91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __MV88E6XXX_H | |
| 13 | #define __MV88E6XXX_H | |
| 14 | ||
| 194fea7b | 15 | #include <linux/if_vlan.h> |
| 52638f71 | 16 | #include <linux/gpio/consumer.h> |
| 194fea7b | 17 | |
| 80c4627b AL |
18 | #ifndef UINT64_MAX |
| 19 | #define UINT64_MAX (u64)(~((u64)0)) | |
| 20 | #endif | |
| 21 | ||
| cca8b133 AL |
22 | #define SMI_CMD 0x00 |
| 23 | #define SMI_CMD_BUSY BIT(15) | |
| 24 | #define SMI_CMD_CLAUSE_22 BIT(12) | |
| 25 | #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
| 26 | #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
| 27 | #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) | |
| 28 | #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) | |
| 29 | #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) | |
| 30 | #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) | |
| 31 | #define SMI_DATA 0x01 | |
| b2eb0662 | 32 | |
| 13a7ebb3 PU |
33 | /* Fiber/SERDES Registers are located at SMI address F, page 1 */ |
| 34 | #define REG_FIBER_SERDES 0x0f | |
| 35 | #define PAGE_FIBER_SERDES 0x01 | |
| 36 | ||
| 91da11f8 | 37 | #define REG_PORT(p) (0x10 + (p)) |
| cca8b133 AL |
38 | #define PORT_STATUS 0x00 |
| 39 | #define PORT_STATUS_PAUSE_EN BIT(15) | |
| 40 | #define PORT_STATUS_MY_PAUSE BIT(14) | |
| 41 | #define PORT_STATUS_HD_FLOW BIT(13) | |
| 42 | #define PORT_STATUS_PHY_DETECT BIT(12) | |
| 43 | #define PORT_STATUS_LINK BIT(11) | |
| 44 | #define PORT_STATUS_DUPLEX BIT(10) | |
| 45 | #define PORT_STATUS_SPEED_MASK 0x0300 | |
| 46 | #define PORT_STATUS_SPEED_10 0x0000 | |
| 47 | #define PORT_STATUS_SPEED_100 0x0100 | |
| 48 | #define PORT_STATUS_SPEED_1000 0x0200 | |
| 49 | #define PORT_STATUS_EEE BIT(6) /* 6352 */ | |
| 50 | #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ | |
| 51 | #define PORT_STATUS_MGMII BIT(6) /* 6185 */ | |
| 52 | #define PORT_STATUS_TX_PAUSED BIT(5) | |
| 53 | #define PORT_STATUS_FLOW_CTRL BIT(4) | |
| 13a7ebb3 PU |
54 | #define PORT_STATUS_CMODE_MASK 0x0f |
| 55 | #define PORT_STATUS_CMODE_100BASE_X 0x8 | |
| 56 | #define PORT_STATUS_CMODE_1000BASE_X 0x9 | |
| 57 | #define PORT_STATUS_CMODE_SGMII 0xa | |
| cca8b133 | 58 | #define PORT_PCS_CTRL 0x01 |
| e7e72ac0 AL |
59 | #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) |
| 60 | #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) | |
| 54d792f2 AL |
61 | #define PORT_PCS_CTRL_FC BIT(7) |
| 62 | #define PORT_PCS_CTRL_FORCE_FC BIT(6) | |
| 63 | #define PORT_PCS_CTRL_LINK_UP BIT(5) | |
| 64 | #define PORT_PCS_CTRL_FORCE_LINK BIT(4) | |
| 65 | #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) | |
| 66 | #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) | |
| 67 | #define PORT_PCS_CTRL_10 0x00 | |
| 68 | #define PORT_PCS_CTRL_100 0x01 | |
| 69 | #define PORT_PCS_CTRL_1000 0x02 | |
| 70 | #define PORT_PCS_CTRL_UNFORCED 0x03 | |
| 71 | #define PORT_PAUSE_CTRL 0x02 | |
| cca8b133 | 72 | #define PORT_SWITCH_ID 0x03 |
| f6271e67 VD |
73 | #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a |
| 74 | #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 | |
| 75 | #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 | |
| 76 | #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 | |
| 77 | #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 | |
| 78 | #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 | |
| 79 | #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 | |
| 80 | #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 | |
| 81 | #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 | |
| 82 | #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 | |
| 83 | #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 | |
| 84 | #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 | |
| 85 | #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 | |
| 86 | #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 | |
| 87 | #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 | |
| 88 | #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 | |
| 89 | #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 | |
| cca8b133 | 90 | #define PORT_CONTROL 0x04 |
| 54d792f2 AL |
91 | #define PORT_CONTROL_USE_CORE_TAG BIT(15) |
| 92 | #define PORT_CONTROL_DROP_ON_LOCK BIT(14) | |
| 93 | #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) | |
| 94 | #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) | |
| 95 | #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) | |
| 96 | #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) | |
| 97 | #define PORT_CONTROL_HEADER BIT(11) | |
| 98 | #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) | |
| 99 | #define PORT_CONTROL_DOUBLE_TAG BIT(9) | |
| 100 | #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) | |
| 101 | #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) | |
| 102 | #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) | |
| 103 | #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) | |
| 104 | #define PORT_CONTROL_DSA_TAG BIT(8) | |
| 105 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) | |
| 106 | #define PORT_CONTROL_TAG_IF_BOTH BIT(6) | |
| 107 | #define PORT_CONTROL_USE_IP BIT(5) | |
| 108 | #define PORT_CONTROL_USE_TAG BIT(4) | |
| 109 | #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) | |
| 110 | #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) | |
| cca8b133 AL |
111 | #define PORT_CONTROL_STATE_MASK 0x03 |
| 112 | #define PORT_CONTROL_STATE_DISABLED 0x00 | |
| 113 | #define PORT_CONTROL_STATE_BLOCKING 0x01 | |
| 114 | #define PORT_CONTROL_STATE_LEARNING 0x02 | |
| 115 | #define PORT_CONTROL_STATE_FORWARDING 0x03 | |
| 116 | #define PORT_CONTROL_1 0x05 | |
| 2db9ce1f | 117 | #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) |
| cca8b133 | 118 | #define PORT_BASE_VLAN 0x06 |
| 2db9ce1f | 119 | #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) |
| cca8b133 | 120 | #define PORT_DEFAULT_VLAN 0x07 |
| b8fee957 | 121 | #define PORT_DEFAULT_VLAN_MASK 0xfff |
| cca8b133 | 122 | #define PORT_CONTROL_2 0x08 |
| 54d792f2 AL |
123 | #define PORT_CONTROL_2_IGNORE_FCS BIT(15) |
| 124 | #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) | |
| 125 | #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) | |
| 126 | #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) | |
| 127 | #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) | |
| 128 | #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) | |
| 129 | #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) | |
| 8efdda4a VD |
130 | #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) |
| 131 | #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) | |
| 132 | #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) | |
| 133 | #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) | |
| 134 | #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) | |
| 54d792f2 AL |
135 | #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) |
| 136 | #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) | |
| 137 | #define PORT_CONTROL_2_MAP_DA BIT(7) | |
| 138 | #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) | |
| 139 | #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) | |
| 140 | #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) | |
| 141 | #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) | |
| cca8b133 AL |
142 | #define PORT_RATE_CONTROL 0x09 |
| 143 | #define PORT_RATE_CONTROL_2 0x0a | |
| 144 | #define PORT_ASSOC_VECTOR 0x0b | |
| 4c7ea3c0 AL |
145 | #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) |
| 146 | #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) | |
| 147 | #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) | |
| 148 | #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) | |
| 149 | #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) | |
| 54d792f2 AL |
150 | #define PORT_ATU_CONTROL 0x0c |
| 151 | #define PORT_PRI_OVERRIDE 0x0d | |
| 152 | #define PORT_ETH_TYPE 0x0f | |
| cca8b133 AL |
153 | #define PORT_IN_DISCARD_LO 0x10 |
| 154 | #define PORT_IN_DISCARD_HI 0x11 | |
| 155 | #define PORT_IN_FILTERED 0x12 | |
| 156 | #define PORT_OUT_FILTERED 0x13 | |
| 54d792f2 AL |
157 | #define PORT_TAG_REGMAP_0123 0x18 |
| 158 | #define PORT_TAG_REGMAP_4567 0x19 | |
| facd95b2 | 159 | |
| cca8b133 AL |
160 | #define REG_GLOBAL 0x1b |
| 161 | #define GLOBAL_STATUS 0x00 | |
| 162 | #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ | |
| 163 | /* Two bits for 6165, 6185 etc */ | |
| 164 | #define GLOBAL_STATUS_PPU_MASK (0x3 << 14) | |
| 165 | #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) | |
| 166 | #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) | |
| 167 | #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) | |
| 168 | #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) | |
| 169 | #define GLOBAL_MAC_01 0x01 | |
| 170 | #define GLOBAL_MAC_23 0x02 | |
| 171 | #define GLOBAL_MAC_45 0x03 | |
| a08df0f0 | 172 | #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */ |
| b8fee957 VD |
173 | #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */ |
| 174 | #define GLOBAL_VTU_FID_MASK 0xfff | |
| 175 | #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ | |
| 176 | #define GLOBAL_VTU_SID_MASK 0x3f | |
| cca8b133 AL |
177 | #define GLOBAL_CONTROL 0x04 |
| 178 | #define GLOBAL_CONTROL_SW_RESET BIT(15) | |
| 179 | #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) | |
| 180 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ | |
| 181 | #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ | |
| 182 | #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ | |
| 54d792f2 | 183 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
| cca8b133 AL |
184 | #define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
| 185 | #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) | |
| 186 | #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) | |
| 187 | #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) | |
| 188 | #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) | |
| 189 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) | |
| 190 | #define GLOBAL_CONTROL_TCAM_EN BIT(1) | |
| 191 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) | |
| 192 | #define GLOBAL_VTU_OP 0x05 | |
| 6b17e864 VD |
193 | #define GLOBAL_VTU_OP_BUSY BIT(15) |
| 194 | #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) | |
| 7dad08d7 | 195 | #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
| b8fee957 | 196 | #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
| 0d3b33e6 VD |
197 | #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
| 198 | #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) | |
| cca8b133 | 199 | #define GLOBAL_VTU_VID 0x06 |
| b8fee957 VD |
200 | #define GLOBAL_VTU_VID_MASK 0xfff |
| 201 | #define GLOBAL_VTU_VID_VALID BIT(12) | |
| cca8b133 AL |
202 | #define GLOBAL_VTU_DATA_0_3 0x07 |
| 203 | #define GLOBAL_VTU_DATA_4_7 0x08 | |
| 204 | #define GLOBAL_VTU_DATA_8_11 0x09 | |
| b8fee957 VD |
205 | #define GLOBAL_VTU_STU_DATA_MASK 0x03 |
| 206 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 | |
| 207 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 | |
| 208 | #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 | |
| 209 | #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 | |
| 0d3b33e6 VD |
210 | #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
| 211 | #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 | |
| 212 | #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 | |
| 213 | #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 | |
| cca8b133 | 214 | #define GLOBAL_ATU_CONTROL 0x0a |
| 54d792f2 | 215 | #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
| cca8b133 AL |
216 | #define GLOBAL_ATU_OP 0x0b |
| 217 | #define GLOBAL_ATU_OP_BUSY BIT(15) | |
| 218 | #define GLOBAL_ATU_OP_NOP (0 << 12) | |
| 7fb5e755 VD |
219 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
| 220 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) | |
| cca8b133 AL |
221 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
| 222 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 7fb5e755 VD |
223 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
| 224 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) | |
| cca8b133 AL |
225 | #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
| 226 | #define GLOBAL_ATU_DATA 0x0c | |
| 8a0a265d | 227 | #define GLOBAL_ATU_DATA_TRUNK BIT(15) |
| fd231c82 VD |
228 | #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
| 229 | #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 | |
| 8a0a265d AL |
230 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
| 231 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 | |
| cca8b133 AL |
232 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
| 233 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 | |
| 234 | #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d | |
| 235 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e | |
| 236 | #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f | |
| 237 | #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 | |
| 238 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 | |
| 239 | #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e | |
| 240 | #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f | |
| 241 | #define GLOBAL_ATU_MAC_01 0x0d | |
| 242 | #define GLOBAL_ATU_MAC_23 0x0e | |
| 243 | #define GLOBAL_ATU_MAC_45 0x0f | |
| 244 | #define GLOBAL_IP_PRI_0 0x10 | |
| 245 | #define GLOBAL_IP_PRI_1 0x11 | |
| 246 | #define GLOBAL_IP_PRI_2 0x12 | |
| 247 | #define GLOBAL_IP_PRI_3 0x13 | |
| 248 | #define GLOBAL_IP_PRI_4 0x14 | |
| 249 | #define GLOBAL_IP_PRI_5 0x15 | |
| 250 | #define GLOBAL_IP_PRI_6 0x16 | |
| 251 | #define GLOBAL_IP_PRI_7 0x17 | |
| 252 | #define GLOBAL_IEEE_PRI 0x18 | |
| 253 | #define GLOBAL_CORE_TAG_TYPE 0x19 | |
| 254 | #define GLOBAL_MONITOR_CONTROL 0x1a | |
| 15966a2a AL |
255 | #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
| 256 | #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 | |
| 257 | #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 | |
| 258 | #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 | |
| 259 | #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) | |
| cca8b133 | 260 | #define GLOBAL_CONTROL_2 0x1c |
| 15966a2a AL |
261 | #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
| 262 | #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 | |
| 263 | ||
| cca8b133 AL |
264 | #define GLOBAL_STATS_OP 0x1d |
| 265 | #define GLOBAL_STATS_OP_BUSY BIT(15) | |
| 266 | #define GLOBAL_STATS_OP_NOP (0 << 12) | |
| 267 | #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 268 | #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 269 | #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 270 | #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 271 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) | |
| 272 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) | |
| 273 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) | |
| f5e2ed02 | 274 | #define GLOBAL_STATS_OP_BANK_1 BIT(9) |
| cca8b133 AL |
275 | #define GLOBAL_STATS_COUNTER_32 0x1e |
| 276 | #define GLOBAL_STATS_COUNTER_01 0x1f | |
| defb05b9 | 277 | |
| cca8b133 AL |
278 | #define REG_GLOBAL2 0x1c |
| 279 | #define GLOBAL2_INT_SOURCE 0x00 | |
| 280 | #define GLOBAL2_INT_MASK 0x01 | |
| 281 | #define GLOBAL2_MGMT_EN_2X 0x02 | |
| 282 | #define GLOBAL2_MGMT_EN_0X 0x03 | |
| 283 | #define GLOBAL2_FLOW_CONTROL 0x04 | |
| 284 | #define GLOBAL2_SWITCH_MGMT 0x05 | |
| 54d792f2 AL |
285 | #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) |
| 286 | #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) | |
| 287 | #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) | |
| 288 | #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) | |
| 289 | #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) | |
| cca8b133 | 290 | #define GLOBAL2_DEVICE_MAPPING 0x06 |
| 54d792f2 AL |
291 | #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) |
| 292 | #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 | |
| d35bd876 | 293 | #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f |
| cca8b133 | 294 | #define GLOBAL2_TRUNK_MASK 0x07 |
| 54d792f2 AL |
295 | #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) |
| 296 | #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 | |
| 5154041f | 297 | #define GLOBAL2_TRUNK_MASK_HASK BIT(11) |
| cca8b133 | 298 | #define GLOBAL2_TRUNK_MAPPING 0x08 |
| 54d792f2 AL |
299 | #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) |
| 300 | #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 | |
| 8ec61c7f VD |
301 | #define GLOBAL2_IRL_CMD 0x09 |
| 302 | #define GLOBAL2_IRL_CMD_BUSY BIT(15) | |
| 303 | #define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
| 304 | #define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
| 305 | #define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
| 306 | #define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
| 307 | #define GLOBAL2_IRL_DATA 0x0a | |
| cca8b133 | 308 | #define GLOBAL2_PVT_ADDR 0x0b |
| 63ed880d VD |
309 | #define GLOBAL2_PVT_ADDR_BUSY BIT(15) |
| 310 | #define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
| 311 | #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
| 312 | #define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
| cca8b133 AL |
313 | #define GLOBAL2_PVT_DATA 0x0c |
| 314 | #define GLOBAL2_SWITCH_MAC 0x0d | |
| cca8b133 AL |
315 | #define GLOBAL2_ATU_STATS 0x0e |
| 316 | #define GLOBAL2_PRIO_OVERRIDE 0x0f | |
| 15966a2a AL |
317 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) |
| 318 | #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 | |
| 319 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) | |
| 320 | #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 | |
| 855b1932 VD |
321 | #define GLOBAL2_EEPROM_CMD 0x14 |
| 322 | #define GLOBAL2_EEPROM_CMD_BUSY BIT(15) | |
| 323 | #define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
| 324 | #define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
| 325 | #define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
| 326 | #define GLOBAL2_EEPROM_CMD_RUNNING BIT(11) | |
| 327 | #define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10) | |
| 328 | #define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff | |
| cca8b133 AL |
329 | #define GLOBAL2_EEPROM_DATA 0x15 |
| 330 | #define GLOBAL2_PTP_AVB_OP 0x16 | |
| 331 | #define GLOBAL2_PTP_AVB_DATA 0x17 | |
| 332 | #define GLOBAL2_SMI_OP 0x18 | |
| 333 | #define GLOBAL2_SMI_OP_BUSY BIT(15) | |
| 334 | #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) | |
| 335 | #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
| 336 | GLOBAL2_SMI_OP_CLAUSE_22) | |
| 337 | #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
| 338 | GLOBAL2_SMI_OP_CLAUSE_22) | |
| 339 | #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 340 | #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 341 | #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 342 | #define GLOBAL2_SMI_DATA 0x19 | |
| 343 | #define GLOBAL2_SCRATCH_MISC 0x1a | |
| 56d95e22 AL |
344 | #define GLOBAL2_SCRATCH_BUSY BIT(15) |
| 345 | #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 | |
| 346 | #define GLOBAL2_SCRATCH_VALUE_MASK 0xff | |
| cca8b133 AL |
347 | #define GLOBAL2_WDOG_CONTROL 0x1b |
| 348 | #define GLOBAL2_QOS_WEIGHT 0x1c | |
| 349 | #define GLOBAL2_MISC 0x1d | |
| defb05b9 | 350 | |
| 3285f9e8 VD |
351 | #define MV88E6XXX_N_FID 4096 |
| 352 | ||
| f81ec90f VD |
353 | /* List of supported models */ |
| 354 | enum mv88e6xxx_model { | |
| 355 | MV88E6085, | |
| 356 | MV88E6095, | |
| 357 | MV88E6123, | |
| 358 | MV88E6131, | |
| 359 | MV88E6161, | |
| 360 | MV88E6165, | |
| 361 | MV88E6171, | |
| 362 | MV88E6172, | |
| 363 | MV88E6175, | |
| 364 | MV88E6176, | |
| 365 | MV88E6185, | |
| 366 | MV88E6240, | |
| 367 | MV88E6320, | |
| 368 | MV88E6321, | |
| 369 | MV88E6350, | |
| 370 | MV88E6351, | |
| 371 | MV88E6352, | |
| 372 | }; | |
| 373 | ||
| 22356476 VD |
374 | enum mv88e6xxx_family { |
| 375 | MV88E6XXX_FAMILY_NONE, | |
| 376 | MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ | |
| 377 | MV88E6XXX_FAMILY_6095, /* 6092 6095 */ | |
| 378 | MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ | |
| 379 | MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ | |
| 380 | MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ | |
| 381 | MV88E6XXX_FAMILY_6320, /* 6320 6321 */ | |
| 382 | MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ | |
| 383 | MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ | |
| 384 | }; | |
| 385 | ||
| 8c9983a2 | 386 | enum mv88e6xxx_cap { |
| aadbdb8a VD |
387 | /* Energy Efficient Ethernet. |
| 388 | */ | |
| 389 | MV88E6XXX_CAP_EEE, | |
| 390 | ||
| a0ffff24 VD |
391 | /* Multi-chip Addressing Mode. |
| 392 | * Some chips respond to only 2 registers of its own SMI device address | |
| 393 | * when it is non-zero, and use indirect access to internal registers. | |
| 394 | */ | |
| 395 | MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */ | |
| 396 | MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */ | |
| 397 | ||
| 9729934c VD |
398 | /* Switch Global 2 Registers. |
| 399 | * The device contains a second set of global 16-bit registers. | |
| 400 | */ | |
| 401 | MV88E6XXX_CAP_GLOBAL2, | |
| 47395ed2 VD |
402 | MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */ |
| 403 | MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */ | |
| 8ec61c7f VD |
404 | MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */ |
| 405 | MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */ | |
| 63ed880d VD |
406 | MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */ |
| 407 | MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */ | |
| 3b4caa1b | 408 | MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */ |
| 9bda889f | 409 | MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ |
| 855b1932 VD |
410 | MV88E6XXX_CAP_G2_EEPROM_CMD, /* (0x14) EEPROM Command */ |
| 411 | MV88E6XXX_CAP_G2_EEPROM_DATA, /* (0x15) EEPROM Data */ | |
| 9729934c | 412 | |
| 8c9983a2 VD |
413 | /* PHY Polling Unit. |
| 414 | * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING. | |
| 415 | */ | |
| 416 | MV88E6XXX_CAP_PPU, | |
| 552238b5 | 417 | MV88E6XXX_CAP_PPU_ACTIVE, |
| 6d5834a1 VD |
418 | |
| 419 | /* SMI PHY Command and Data registers. | |
| 420 | * This requires an indirect access to PHY registers through | |
| 421 | * GLOBAL2_SMI_OP, otherwise direct access to PHY registers is done. | |
| 422 | */ | |
| 423 | MV88E6XXX_CAP_SMI_PHY, | |
| 6594f615 | 424 | |
| cb9b9020 VD |
425 | /* Per VLAN Spanning Tree Unit (STU). |
| 426 | * The Port State database, if present, is accessed through VTU | |
| 427 | * operations and dedicated SID registers. See GLOBAL_VTU_SID. | |
| 428 | */ | |
| 429 | MV88E6XXX_CAP_STU, | |
| 430 | ||
| 6594f615 VD |
431 | /* Internal temperature sensor. |
| 432 | * Available from any enabled port's PHY register 26, page 6. | |
| 433 | */ | |
| 434 | MV88E6XXX_CAP_TEMP, | |
| 435 | MV88E6XXX_CAP_TEMP_LIMIT, | |
| 936f234a | 436 | |
| 54d77b5b VD |
437 | /* VLAN Table Unit. |
| 438 | * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP. | |
| 439 | */ | |
| 440 | MV88E6XXX_CAP_VTU, | |
| 8c9983a2 VD |
441 | }; |
| 442 | ||
| 443 | /* Bitmask of capabilities */ | |
| aadbdb8a | 444 | #define MV88E6XXX_FLAG_EEE BIT(MV88E6XXX_CAP_EEE) |
| a0ffff24 VD |
445 | |
| 446 | #define MV88E6XXX_FLAG_SMI_CMD BIT(MV88E6XXX_CAP_SMI_CMD) | |
| 447 | #define MV88E6XXX_FLAG_SMI_DATA BIT(MV88E6XXX_CAP_SMI_DATA) | |
| 448 | ||
| 9729934c | 449 | #define MV88E6XXX_FLAG_GLOBAL2 BIT(MV88E6XXX_CAP_GLOBAL2) |
| 47395ed2 VD |
450 | #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X) |
| 451 | #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X) | |
| 8ec61c7f VD |
452 | #define MV88E6XXX_FLAG_G2_IRL_CMD BIT(MV88E6XXX_CAP_G2_IRL_CMD) |
| 453 | #define MV88E6XXX_FLAG_G2_IRL_DATA BIT(MV88E6XXX_CAP_G2_IRL_DATA) | |
| 63ed880d VD |
454 | #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT(MV88E6XXX_CAP_G2_PVT_ADDR) |
| 455 | #define MV88E6XXX_FLAG_G2_PVT_DATA BIT(MV88E6XXX_CAP_G2_PVT_DATA) | |
| 3b4caa1b | 456 | #define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT(MV88E6XXX_CAP_G2_SWITCH_MAC) |
| 9bda889f | 457 | #define MV88E6XXX_FLAG_G2_POT BIT(MV88E6XXX_CAP_G2_POT) |
| 855b1932 VD |
458 | #define MV88E6XXX_FLAG_G2_EEPROM_CMD BIT(MV88E6XXX_CAP_G2_EEPROM_CMD) |
| 459 | #define MV88E6XXX_FLAG_G2_EEPROM_DATA BIT(MV88E6XXX_CAP_G2_EEPROM_DATA) | |
| a0ffff24 | 460 | |
| 8c9983a2 | 461 | #define MV88E6XXX_FLAG_PPU BIT(MV88E6XXX_CAP_PPU) |
| 552238b5 | 462 | #define MV88E6XXX_FLAG_PPU_ACTIVE BIT(MV88E6XXX_CAP_PPU_ACTIVE) |
| 6d5834a1 | 463 | #define MV88E6XXX_FLAG_SMI_PHY BIT(MV88E6XXX_CAP_SMI_PHY) |
| cb9b9020 | 464 | #define MV88E6XXX_FLAG_STU BIT(MV88E6XXX_CAP_STU) |
| 6594f615 VD |
465 | #define MV88E6XXX_FLAG_TEMP BIT(MV88E6XXX_CAP_TEMP) |
| 466 | #define MV88E6XXX_FLAG_TEMP_LIMIT BIT(MV88E6XXX_CAP_TEMP_LIMIT) | |
| 54d77b5b | 467 | #define MV88E6XXX_FLAG_VTU BIT(MV88E6XXX_CAP_VTU) |
| b5058d7a | 468 | |
| 855b1932 VD |
469 | /* EEPROM Programming via Global2 with 16-bit data */ |
| 470 | #define MV88E6XXX_FLAGS_EEPROM16 \ | |
| 471 | (MV88E6XXX_FLAG_G2_EEPROM_CMD | \ | |
| 472 | MV88E6XXX_FLAG_G2_EEPROM_DATA) | |
| 473 | ||
| 8ec61c7f VD |
474 | /* Ingress Rate Limit unit */ |
| 475 | #define MV88E6XXX_FLAGS_IRL \ | |
| 476 | (MV88E6XXX_FLAG_G2_IRL_CMD | \ | |
| 477 | MV88E6XXX_FLAG_G2_IRL_DATA) | |
| 478 | ||
| a0ffff24 VD |
479 | /* Multi-chip Addressing Mode */ |
| 480 | #define MV88E6XXX_FLAGS_MULTI_CHIP \ | |
| 481 | (MV88E6XXX_FLAG_SMI_CMD | \ | |
| 482 | MV88E6XXX_FLAG_SMI_DATA) | |
| 483 | ||
| 63ed880d VD |
484 | /* Cross-chip Port VLAN Table */ |
| 485 | #define MV88E6XXX_FLAGS_PVT \ | |
| 486 | (MV88E6XXX_FLAG_G2_PVT_ADDR | \ | |
| 487 | MV88E6XXX_FLAG_G2_PVT_DATA) | |
| 488 | ||
| 8c9983a2 | 489 | #define MV88E6XXX_FLAGS_FAMILY_6095 \ |
| 9729934c | 490 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 | 491 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
| 2672f825 | 492 | MV88E6XXX_FLAG_PPU | \ |
| a0ffff24 VD |
493 | MV88E6XXX_FLAG_VTU | \ |
| 494 | MV88E6XXX_FLAGS_MULTI_CHIP) | |
| 8c9983a2 VD |
495 | |
| 496 | #define MV88E6XXX_FLAGS_FAMILY_6097 \ | |
| 9729934c | 497 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 VD |
498 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 499 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
| 9bda889f | 500 | MV88E6XXX_FLAG_G2_POT | \ |
| 2672f825 | 501 | MV88E6XXX_FLAG_PPU | \ |
| cb9b9020 | 502 | MV88E6XXX_FLAG_STU | \ |
| 63ed880d | 503 | MV88E6XXX_FLAG_VTU | \ |
| 8ec61c7f | 504 | MV88E6XXX_FLAGS_IRL | \ |
| a0ffff24 | 505 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 63ed880d | 506 | MV88E6XXX_FLAGS_PVT) |
| b5058d7a | 507 | |
| 6594f615 | 508 | #define MV88E6XXX_FLAGS_FAMILY_6165 \ |
| 9729934c | 509 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 VD |
510 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 511 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
| 3b4caa1b | 512 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ |
| 9bda889f | 513 | MV88E6XXX_FLAG_G2_POT | \ |
| 914b32f6 | 514 | MV88E6XXX_FLAG_STU | \ |
| cb9b9020 | 515 | MV88E6XXX_FLAG_TEMP | \ |
| 63ed880d | 516 | MV88E6XXX_FLAG_VTU | \ |
| 8ec61c7f | 517 | MV88E6XXX_FLAGS_IRL | \ |
| a0ffff24 | 518 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 63ed880d | 519 | MV88E6XXX_FLAGS_PVT) |
| b5058d7a | 520 | |
| 8c9983a2 | 521 | #define MV88E6XXX_FLAGS_FAMILY_6185 \ |
| 9729934c | 522 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 | 523 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
| a0ffff24 | 524 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 2672f825 | 525 | MV88E6XXX_FLAG_PPU | \ |
| 54d77b5b | 526 | MV88E6XXX_FLAG_VTU) |
| b5058d7a | 527 | |
| 6d5834a1 | 528 | #define MV88E6XXX_FLAGS_FAMILY_6320 \ |
| d51c542b | 529 | (MV88E6XXX_FLAG_EEE | \ |
| 9729934c | 530 | MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 VD |
531 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 532 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
| 3b4caa1b | 533 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ |
| 9bda889f | 534 | MV88E6XXX_FLAG_G2_POT | \ |
| 552238b5 | 535 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
| 6594f615 VD |
536 | MV88E6XXX_FLAG_SMI_PHY | \ |
| 537 | MV88E6XXX_FLAG_TEMP | \ | |
| 936f234a | 538 | MV88E6XXX_FLAG_TEMP_LIMIT | \ |
| 63ed880d | 539 | MV88E6XXX_FLAG_VTU | \ |
| 855b1932 | 540 | MV88E6XXX_FLAGS_EEPROM16 | \ |
| 8ec61c7f | 541 | MV88E6XXX_FLAGS_IRL | \ |
| a0ffff24 | 542 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 63ed880d | 543 | MV88E6XXX_FLAGS_PVT) |
| b5058d7a | 544 | |
| 6d5834a1 | 545 | #define MV88E6XXX_FLAGS_FAMILY_6351 \ |
| 9729934c | 546 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 VD |
547 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 548 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
| 3b4caa1b | 549 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ |
| 9bda889f | 550 | MV88E6XXX_FLAG_G2_POT | \ |
| 552238b5 | 551 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
| 936f234a | 552 | MV88E6XXX_FLAG_SMI_PHY | \ |
| cb9b9020 | 553 | MV88E6XXX_FLAG_STU | \ |
| 936f234a | 554 | MV88E6XXX_FLAG_TEMP | \ |
| 63ed880d | 555 | MV88E6XXX_FLAG_VTU | \ |
| 8ec61c7f | 556 | MV88E6XXX_FLAGS_IRL | \ |
| a0ffff24 | 557 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 63ed880d | 558 | MV88E6XXX_FLAGS_PVT) |
| b5058d7a | 559 | |
| 6d5834a1 | 560 | #define MV88E6XXX_FLAGS_FAMILY_6352 \ |
| d51c542b | 561 | (MV88E6XXX_FLAG_EEE | \ |
| 9729934c | 562 | MV88E6XXX_FLAG_GLOBAL2 | \ |
| 47395ed2 VD |
563 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 564 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
| 3b4caa1b | 565 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ |
| 9bda889f | 566 | MV88E6XXX_FLAG_G2_POT | \ |
| 552238b5 | 567 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
| 936f234a | 568 | MV88E6XXX_FLAG_SMI_PHY | \ |
| cb9b9020 | 569 | MV88E6XXX_FLAG_STU | \ |
| 6594f615 | 570 | MV88E6XXX_FLAG_TEMP | \ |
| 936f234a | 571 | MV88E6XXX_FLAG_TEMP_LIMIT | \ |
| 63ed880d | 572 | MV88E6XXX_FLAG_VTU | \ |
| 855b1932 | 573 | MV88E6XXX_FLAGS_EEPROM16 | \ |
| 8ec61c7f | 574 | MV88E6XXX_FLAGS_IRL | \ |
| a0ffff24 | 575 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
| 63ed880d | 576 | MV88E6XXX_FLAGS_PVT) |
| b5058d7a | 577 | |
| f6271e67 | 578 | struct mv88e6xxx_info { |
| 22356476 | 579 | enum mv88e6xxx_family family; |
| f6271e67 VD |
580 | u16 prod_num; |
| 581 | const char *name; | |
| cd5a2c82 | 582 | unsigned int num_databases; |
| 009a2b98 | 583 | unsigned int num_ports; |
| 9dddd478 | 584 | unsigned int port_base_addr; |
| acddbd21 | 585 | unsigned int age_time_coeff; |
| b5058d7a | 586 | unsigned long flags; |
| b9b37713 VD |
587 | }; |
| 588 | ||
| fd231c82 VD |
589 | struct mv88e6xxx_atu_entry { |
| 590 | u16 fid; | |
| 591 | u8 state; | |
| 592 | bool trunk; | |
| 593 | u16 portv_trunkid; | |
| 594 | u8 mac[ETH_ALEN]; | |
| 595 | }; | |
| 596 | ||
| b8fee957 VD |
597 | struct mv88e6xxx_vtu_stu_entry { |
| 598 | /* VTU only */ | |
| 599 | u16 vid; | |
| 600 | u16 fid; | |
| 601 | ||
| 602 | /* VTU and STU */ | |
| 603 | u8 sid; | |
| 604 | bool valid; | |
| 605 | u8 data[DSA_MAX_PORTS]; | |
| 606 | }; | |
| 607 | ||
| 914b32f6 VD |
608 | struct mv88e6xxx_ops; |
| 609 | ||
| d715fa64 | 610 | struct mv88e6xxx_priv_port { |
| a6692754 | 611 | struct net_device *bridge_dev; |
| d715fa64 VD |
612 | }; |
| 613 | ||
| fad09c73 | 614 | struct mv88e6xxx_chip { |
| f6271e67 VD |
615 | const struct mv88e6xxx_info *info; |
| 616 | ||
| 7543a6d5 AL |
617 | /* The dsa_switch this private structure is related to */ |
| 618 | struct dsa_switch *ds; | |
| 619 | ||
| 158bc065 AL |
620 | /* The device this structure is associated to */ |
| 621 | struct device *dev; | |
| 622 | ||
| 9f8b3ee1 VD |
623 | /* This mutex protects the access to the switch registers */ |
| 624 | struct mutex reg_lock; | |
| 91da11f8 | 625 | |
| a77d43f1 AL |
626 | /* The MII bus and the address on the bus that is used to |
| 627 | * communication with the switch | |
| 628 | */ | |
| 914b32f6 | 629 | const struct mv88e6xxx_ops *smi_ops; |
| a77d43f1 AL |
630 | struct mii_bus *bus; |
| 631 | int sw_addr; | |
| 632 | ||
| 3675c8d7 | 633 | /* Handles automatic disabling and re-enabling of the PHY |
| 2e5f0320 LB |
634 | * polling unit. |
| 635 | */ | |
| 636 | struct mutex ppu_mutex; | |
| 637 | int ppu_disabled; | |
| 638 | struct work_struct ppu_work; | |
| 639 | struct timer_list ppu_timer; | |
| 2e5f0320 | 640 | |
| 3675c8d7 | 641 | /* This mutex serialises access to the statistics unit. |
| 91da11f8 LB |
642 | * Hold this mutex over snapshot + dump sequences. |
| 643 | */ | |
| 644 | struct mutex stats_mutex; | |
| 3ad50cca | 645 | |
| d715fa64 VD |
646 | struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS]; |
| 647 | ||
| 52638f71 AL |
648 | /* A switch may have a GPIO line tied to its reset pin. Parse |
| 649 | * this from the device tree, and use it before performing | |
| 650 | * switch soft reset. | |
| 651 | */ | |
| 652 | struct gpio_desc *reset; | |
| f8cd8753 AL |
653 | |
| 654 | /* set to size of eeprom if supported by the switch */ | |
| 655 | int eeprom_len; | |
| b516d453 AL |
656 | |
| 657 | /* Device node for the MDIO bus */ | |
| 658 | struct device_node *mdio_np; | |
| 659 | ||
| 660 | /* And the MDIO bus itself */ | |
| 661 | struct mii_bus *mdio_bus; | |
| 91da11f8 LB |
662 | }; |
| 663 | ||
| 914b32f6 | 664 | struct mv88e6xxx_ops { |
| fad09c73 VD |
665 | int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
| 666 | int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); | |
| 914b32f6 VD |
667 | }; |
| 668 | ||
| f5e2ed02 AL |
669 | enum stat_type { |
| 670 | BANK0, | |
| 671 | BANK1, | |
| 672 | PORT, | |
| 673 | }; | |
| 674 | ||
| 91da11f8 LB |
675 | struct mv88e6xxx_hw_stat { |
| 676 | char string[ETH_GSTRING_LEN]; | |
| 677 | int sizeof_stat; | |
| 678 | int reg; | |
| f5e2ed02 | 679 | enum stat_type type; |
| 91da11f8 LB |
680 | }; |
| 681 | ||
| fad09c73 | 682 | static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip, |
| b5058d7a VD |
683 | unsigned long flags) |
| 684 | { | |
| fad09c73 | 685 | return (chip->info->flags & flags) == flags; |
| b5058d7a VD |
686 | } |
| 687 | ||
| 91da11f8 | 688 | #endif |