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net: dsa: tag_{e}dsa.c: Remove dependency on platform data
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
14c7b3c3
AL		 8 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
9 *
91da11f8
LB		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
19b2f97e 16#include <linux/delay.h>
defb05b9 17#include <linux/etherdevice.h>
dea87024 18#include <linux/ethtool.h>
facd95b2 19#include <linux/if_bridge.h>
19b2f97e 20#include <linux/jiffies.h>
91da11f8 21#include <linux/list.h>
14c7b3c3 22#include <linux/mdio.h>
2bbba277 23#include <linux/module.h>
91da11f8 24#include <linux/netdevice.h>
c8c1b39a 25#include <linux/gpio/consumer.h>
91da11f8 26#include <linux/phy.h>
c8f0b869 27#include <net/dsa.h>
1f36faf2 28#include <net/switchdev.h>
91da11f8
LB		 29#include "mv88e6xxx.h"
30
158bc065 31static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
3996a4ff 32{
3996a4ff 33 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
158bc065 34 dev_err(ps->dev, "SMI lock not held!\n");
3996a4ff
VD		 35 dump_stack();
36 }
37}
38
3675c8d7 39/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 40 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
41 * will be directly accessible on some {device address,register address}
42 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
43 * will only respond to SMI transactions to that specific address, and
44 * an indirect addressing mechanism needs to be used to access its
45 * registers.
46 */
47static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
48{
49 int ret;
50 int i;
51
52 for (i = 0; i < 16; i++) {
6e899e6c 53 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 54 if (ret < 0)
55 return ret;
56
cca8b133 57 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 58 return 0;
59 }
60
61 return -ETIMEDOUT;
62}
63
b9b37713
VD		 64static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
65 int reg)
91da11f8
LB		 66{
67 int ret;
68
69 if (sw_addr == 0)
6e899e6c 70 return mdiobus_read_nested(bus, addr, reg);
91da11f8 71
3675c8d7 72 /* Wait for the bus to become free. */
91da11f8
LB		 73 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
74 if (ret < 0)
75 return ret;
76
3675c8d7 77 /* Transmit the read command. */
6e899e6c
NA		 78 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
79 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 80 if (ret < 0)
81 return ret;
82
3675c8d7 83 /* Wait for the read command to complete. */
91da11f8
LB		 84 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
85 if (ret < 0)
86 return ret;
87
3675c8d7 88 /* Read the data. */
6e899e6c 89 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 90 if (ret < 0)
91 return ret;
92
93 return ret & 0xffff;
94}
95
158bc065
AL		 96static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
97 int addr, int reg)
91da11f8 98{
91da11f8
LB		 99 int ret;
100
158bc065 101 assert_smi_lock(ps);
3996a4ff 102
a77d43f1 103 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
bb92ea5e
VD		 104 if (ret < 0)
105 return ret;
106
158bc065 107 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 108 addr, reg, ret);
109
91da11f8
LB		 110 return ret;
111}
112
158bc065 113int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg)
8d6d09e7 114{
8d6d09e7
GR		 115 int ret;
116
117 mutex_lock(&ps->smi_mutex);
158bc065 118 ret = _mv88e6xxx_reg_read(ps, addr, reg);
8d6d09e7
GR		 119 mutex_unlock(&ps->smi_mutex);
120
121 return ret;
122}
123
b9b37713
VD		 124static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
125 int reg, u16 val)
91da11f8
LB		 126{
127 int ret;
128
129 if (sw_addr == 0)
6e899e6c 130 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 131
3675c8d7 132 /* Wait for the bus to become free. */
91da11f8
LB		 133 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
134 if (ret < 0)
135 return ret;
136
3675c8d7 137 /* Transmit the data to write. */
6e899e6c 138 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 139 if (ret < 0)
140 return ret;
141
3675c8d7 142 /* Transmit the write command. */
6e899e6c
NA		 143 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
144 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 145 if (ret < 0)
146 return ret;
147
3675c8d7 148 /* Wait for the write command to complete. */
91da11f8
LB		 149 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
150 if (ret < 0)
151 return ret;
152
153 return 0;
154}
155
158bc065
AL		 156static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
157 int reg, u16 val)
91da11f8 158{
158bc065 159 assert_smi_lock(ps);
91da11f8 160
158bc065 161 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 162 addr, reg, val);
163
a77d43f1 164 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
8d6d09e7
GR		 165}
166
158bc065
AL		 167int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
168 int reg, u16 val)
8d6d09e7 169{
8d6d09e7
GR		 170 int ret;
171
91da11f8 172 mutex_lock(&ps->smi_mutex);
158bc065 173 ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
91da11f8
LB		 174 mutex_unlock(&ps->smi_mutex);
175
176 return ret;
177}
178
1d13a06e 179static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
2e5f0320 180{
158bc065 181 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 182 int err;
2e5f0320 183
158bc065 184 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
48ace4ef
AL		 185 (addr[0] << 8) | addr[1]);
186 if (err)
187 return err;
188
158bc065 189 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
48ace4ef
AL		 190 (addr[2] << 8) | addr[3]);
191 if (err)
192 return err;
193
158bc065 194 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
48ace4ef 195 (addr[4] << 8) | addr[5]);
2e5f0320
LB		 196}
197
1d13a06e 198static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
91da11f8 199{
158bc065 200 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 201 int ret;
48ace4ef 202 int i;
91da11f8
LB		 203
204 for (i = 0; i < 6; i++) {
205 int j;
206
3675c8d7 207 /* Write the MAC address byte. */
158bc065 208 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
48ace4ef
AL		 209 GLOBAL2_SWITCH_MAC_BUSY |
210 (i << 8) | addr[i]);
211 if (ret)
212 return ret;
91da11f8 213
3675c8d7 214 /* Wait for the write to complete. */
91da11f8 215 for (j = 0; j < 16; j++) {
158bc065 216 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
48ace4ef
AL		 217 GLOBAL2_SWITCH_MAC);
218 if (ret < 0)
219 return ret;
220
cca8b133 221 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 222 break;
223 }
224 if (j == 16)
225 return -ETIMEDOUT;
226 }
227
228 return 0;
229}
230
1d13a06e
VD		 231int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
232{
233 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
234
235 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
236 return mv88e6xxx_set_addr_indirect(ds, addr);
237 else
238 return mv88e6xxx_set_addr_direct(ds, addr);
239}
240
158bc065
AL		 241static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr,
242 int regnum)
91da11f8
LB		 243{
244 if (addr >= 0)
158bc065 245 return _mv88e6xxx_reg_read(ps, addr, regnum);
91da11f8
LB		 246 return 0xffff;
247}
248
158bc065
AL		 249static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
250 int regnum, u16 val)
91da11f8
LB		 251{
252 if (addr >= 0)
158bc065 253 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
91da11f8
LB		 254 return 0;
255}
256
158bc065 257static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
2e5f0320
LB		 258{
259 int ret;
19b2f97e 260 unsigned long timeout;
2e5f0320 261
8c9983a2 262 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 263 if (ret < 0)
264 return ret;
265
8c9983a2
VD		 266 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
267 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 268 if (ret)
269 return ret;
2e5f0320 270
19b2f97e
BG		 271 timeout = jiffies + 1 * HZ;
272 while (time_before(jiffies, timeout)) {
8c9983a2 273 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 274 if (ret < 0)
275 return ret;
276
19b2f97e 277 usleep_range(1000, 2000);
cca8b133
AL		 278 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
279 GLOBAL_STATUS_PPU_POLLING)
85686581 280 return 0;
2e5f0320
LB		 281 }
282
283 return -ETIMEDOUT;
284}
285
158bc065 286static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
2e5f0320 287{
48ace4ef 288 int ret, err;
19b2f97e 289 unsigned long timeout;
2e5f0320 290
762eb67b 291 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 292 if (ret < 0)
293 return ret;
294
762eb67b
VD		 295 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
296 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 297 if (err)
298 return err;
2e5f0320 299
19b2f97e
BG		 300 timeout = jiffies + 1 * HZ;
301 while (time_before(jiffies, timeout)) {
762eb67b 302 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 303 if (ret < 0)
304 return ret;
305
19b2f97e 306 usleep_range(1000, 2000);
cca8b133
AL		 307 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
308 GLOBAL_STATUS_PPU_POLLING)
85686581 309 return 0;
2e5f0320
LB		 310 }
311
312 return -ETIMEDOUT;
313}
314
315static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
316{
317 struct mv88e6xxx_priv_state *ps;
318
319 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
762eb67b
VD		 320
321 mutex_lock(&ps->smi_mutex);
322
2e5f0320 323 if (mutex_trylock(&ps->ppu_mutex)) {
158bc065 324 if (mv88e6xxx_ppu_enable(ps) == 0)
85686581
BG		 325 ps->ppu_disabled = 0;
326 mutex_unlock(&ps->ppu_mutex);
2e5f0320 327 }
762eb67b
VD		 328
329 mutex_unlock(&ps->smi_mutex);
2e5f0320
LB		 330}
331
332static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
333{
334 struct mv88e6xxx_priv_state *ps = (void *)_ps;
335
336 schedule_work(&ps->ppu_work);
337}
338
158bc065 339static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
2e5f0320 340{
2e5f0320
LB		 341 int ret;
342
343 mutex_lock(&ps->ppu_mutex);
344
3675c8d7 345 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 346 * we can access the PHY registers. If it was already
347 * disabled, cancel the timer that is going to re-enable
348 * it.
349 */
350 if (!ps->ppu_disabled) {
158bc065 351 ret = mv88e6xxx_ppu_disable(ps);
85686581
BG		 352 if (ret < 0) {
353 mutex_unlock(&ps->ppu_mutex);
354 return ret;
355 }
356 ps->ppu_disabled = 1;
2e5f0320 357 } else {
85686581
BG		 358 del_timer(&ps->ppu_timer);
359 ret = 0;
2e5f0320
LB		 360 }
361
362 return ret;
363}
364
158bc065 365static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
2e5f0320 366{
3675c8d7 367 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 368 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
369 mutex_unlock(&ps->ppu_mutex);
370}
371
158bc065 372void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
2e5f0320 373{
2e5f0320
LB		 374 mutex_init(&ps->ppu_mutex);
375 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
376 init_timer(&ps->ppu_timer);
377 ps->ppu_timer.data = (unsigned long)ps;
378 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
379}
380
8c9983a2
VD		 381static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
382 int regnum)
2e5f0320
LB		 383{
384 int ret;
385
158bc065 386 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 387 if (ret >= 0) {
8c9983a2 388 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
158bc065 389 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 390 }
391
392 return ret;
393}
394
8c9983a2
VD		 395static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
396 int regnum, u16 val)
2e5f0320
LB		 397{
398 int ret;
399
158bc065 400 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 401 if (ret >= 0) {
8c9983a2 402 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
158bc065 403 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 404 }
405
406 return ret;
407}
2e5f0320 408
158bc065 409static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
54d792f2 410{
22356476 411 return ps->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 412}
413
158bc065 414static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
54d792f2 415{
22356476 416 return ps->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 417}
418
158bc065 419static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
54d792f2 420{
22356476 421 return ps->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 422}
423
158bc065 424static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
54d792f2 425{
22356476 426 return ps->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 427}
428
158bc065 429static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
54d792f2 430{
22356476 431 return ps->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 432}
433
158bc065 434static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
7c3d0d67 435{
22356476 436 return ps->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 437}
438
158bc065 439static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
54d792f2 440{
22356476 441 return ps->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 442}
443
158bc065 444static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
f3a8b6b6 445{
22356476 446 return ps->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 447}
448
158bc065 449static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
f74df0be 450{
cd5a2c82 451 return ps->info->num_databases;
f74df0be
VD		 452}
453
158bc065 454static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
b426e5f7
VD		 455{
456 /* Does the device have dedicated FID registers for ATU and VTU ops? */
158bc065
AL		 457 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
458 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
b426e5f7
VD		 459 return true;
460
461 return false;
462}
463
dea87024
AL		 464/* We expect the switch to perform auto negotiation if there is a real
465 * phy. However, in the case of a fixed link phy, we force the port
466 * settings from the fixed link settings.
467 */
f81ec90f
VD		 468static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
469 struct phy_device *phydev)
dea87024
AL		 470{
471 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 472 u32 reg;
473 int ret;
dea87024
AL		 474
475 if (!phy_is_pseudo_fixed_link(phydev))
476 return;
477
478 mutex_lock(&ps->smi_mutex);
479
158bc065 480 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 481 if (ret < 0)
482 goto out;
483
484 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
485 PORT_PCS_CTRL_FORCE_LINK |
486 PORT_PCS_CTRL_DUPLEX_FULL |
487 PORT_PCS_CTRL_FORCE_DUPLEX |
488 PORT_PCS_CTRL_UNFORCED);
489
490 reg |= PORT_PCS_CTRL_FORCE_LINK;
491 if (phydev->link)
492 reg |= PORT_PCS_CTRL_LINK_UP;
493
158bc065 494 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
dea87024
AL		 495 goto out;
496
497 switch (phydev->speed) {
498 case SPEED_1000:
499 reg |= PORT_PCS_CTRL_1000;
500 break;
501 case SPEED_100:
502 reg |= PORT_PCS_CTRL_100;
503 break;
504 case SPEED_10:
505 reg |= PORT_PCS_CTRL_10;
506 break;
507 default:
508 pr_info("Unknown speed");
509 goto out;
510 }
511
512 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
513 if (phydev->duplex == DUPLEX_FULL)
514 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
515
158bc065 516 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
009a2b98 517 (port >= ps->info->num_ports - 2)) {
e7e72ac0
AL		 518 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
519 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
520 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
521 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
522 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
523 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
524 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
525 }
158bc065 526 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 527
528out:
529 mutex_unlock(&ps->smi_mutex);
530}
531
158bc065 532static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
91da11f8
LB		 533{
534 int ret;
535 int i;
536
537 for (i = 0; i < 10; i++) {
158bc065 538 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 539 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 540 return 0;
541 }
542
543 return -ETIMEDOUT;
544}
545
158bc065
AL		 546static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
547 int port)
91da11f8
LB		 548{
549 int ret;
550
158bc065 551 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
f3a8b6b6
AL		 552 port = (port + 1) << 5;
553
3675c8d7 554 /* Snapshot the hardware statistics counters for this port. */
158bc065 555 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 556 GLOBAL_STATS_OP_CAPTURE_PORT |
557 GLOBAL_STATS_OP_HIST_RX_TX | port);
558 if (ret < 0)
559 return ret;
91da11f8 560
3675c8d7 561 /* Wait for the snapshotting to complete. */
158bc065 562 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 563 if (ret < 0)
564 return ret;
565
566 return 0;
567}
568
158bc065
AL		 569static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
570 int stat, u32 *val)
91da11f8
LB		 571{
572 u32 _val;
573 int ret;
574
575 *val = 0;
576
158bc065 577 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 578 GLOBAL_STATS_OP_READ_CAPTURED |
579 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 580 if (ret < 0)
581 return;
582
158bc065 583 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 584 if (ret < 0)
585 return;
586
158bc065 587 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 588 if (ret < 0)
589 return;
590
591 _val = ret << 16;
592
158bc065 593 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 594 if (ret < 0)
595 return;
596
597 *val = _val | ret;
598}
599
e413e7e1 600static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 601 { "in_good_octets", 8, 0x00, BANK0, },
602 { "in_bad_octets", 4, 0x02, BANK0, },
603 { "in_unicast", 4, 0x04, BANK0, },
604 { "in_broadcasts", 4, 0x06, BANK0, },
605 { "in_multicasts", 4, 0x07, BANK0, },
606 { "in_pause", 4, 0x16, BANK0, },
607 { "in_undersize", 4, 0x18, BANK0, },
608 { "in_fragments", 4, 0x19, BANK0, },
609 { "in_oversize", 4, 0x1a, BANK0, },
610 { "in_jabber", 4, 0x1b, BANK0, },
611 { "in_rx_error", 4, 0x1c, BANK0, },
612 { "in_fcs_error", 4, 0x1d, BANK0, },
613 { "out_octets", 8, 0x0e, BANK0, },
614 { "out_unicast", 4, 0x10, BANK0, },
615 { "out_broadcasts", 4, 0x13, BANK0, },
616 { "out_multicasts", 4, 0x12, BANK0, },
617 { "out_pause", 4, 0x15, BANK0, },
618 { "excessive", 4, 0x11, BANK0, },
619 { "collisions", 4, 0x1e, BANK0, },
620 { "deferred", 4, 0x05, BANK0, },
621 { "single", 4, 0x14, BANK0, },
622 { "multiple", 4, 0x17, BANK0, },
623 { "out_fcs_error", 4, 0x03, BANK0, },
624 { "late", 4, 0x1f, BANK0, },
625 { "hist_64bytes", 4, 0x08, BANK0, },
626 { "hist_65_127bytes", 4, 0x09, BANK0, },
627 { "hist_128_255bytes", 4, 0x0a, BANK0, },
628 { "hist_256_511bytes", 4, 0x0b, BANK0, },
629 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
630 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
631 { "sw_in_discards", 4, 0x10, PORT, },
632 { "sw_in_filtered", 2, 0x12, PORT, },
633 { "sw_out_filtered", 2, 0x13, PORT, },
634 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
635 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
636 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
637 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
638 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
639 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
640 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
641 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
642 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
643 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
644 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
645 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
646 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
647 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
648 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
649 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
650 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
651 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
652 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 660};
661
158bc065 662static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 663 struct mv88e6xxx_hw_stat *stat)
e413e7e1 664{
f5e2ed02
AL		 665 switch (stat->type) {
666 case BANK0:
e413e7e1 667 return true;
f5e2ed02 668 case BANK1:
158bc065 669 return mv88e6xxx_6320_family(ps);
f5e2ed02 670 case PORT:
158bc065
AL		 671 return mv88e6xxx_6095_family(ps) ||
672 mv88e6xxx_6185_family(ps) ||
673 mv88e6xxx_6097_family(ps) ||
674 mv88e6xxx_6165_family(ps) ||
675 mv88e6xxx_6351_family(ps) ||
676 mv88e6xxx_6352_family(ps);
91da11f8 677 }
f5e2ed02 678 return false;
91da11f8
LB		 679}
680
158bc065 681static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 682 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 683 int port)
684{
80c4627b
AL		 685 u32 low;
686 u32 high = 0;
687 int ret;
688 u64 value;
689
f5e2ed02
AL		 690 switch (s->type) {
691 case PORT:
158bc065 692 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
80c4627b
AL		 693 if (ret < 0)
694 return UINT64_MAX;
695
696 low = ret;
697 if (s->sizeof_stat == 4) {
158bc065 698 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
f5e2ed02 699 s->reg + 1);
80c4627b
AL		 700 if (ret < 0)
701 return UINT64_MAX;
702 high = ret;
703 }
f5e2ed02
AL		 704 break;
705 case BANK0:
706 case BANK1:
158bc065 707 _mv88e6xxx_stats_read(ps, s->reg, &low);
80c4627b 708 if (s->sizeof_stat == 8)
158bc065 709 _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
80c4627b
AL		 710 }
711 value = (((u64)high) << 16) | low;
712 return value;
713}
714
f81ec90f
VD		 715static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
716 uint8_t *data)
91da11f8 717{
158bc065 718 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 719 struct mv88e6xxx_hw_stat *stat;
720 int i, j;
91da11f8 721
f5e2ed02
AL		 722 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
723 stat = &mv88e6xxx_hw_stats[i];
158bc065 724 if (mv88e6xxx_has_stat(ps, stat)) {
f5e2ed02
AL		 725 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
726 ETH_GSTRING_LEN);
727 j++;
728 }
91da11f8 729 }
e413e7e1
AL		 730}
731
f81ec90f 732static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 733{
158bc065 734 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 735 struct mv88e6xxx_hw_stat *stat;
736 int i, j;
737
738 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
739 stat = &mv88e6xxx_hw_stats[i];
158bc065 740 if (mv88e6xxx_has_stat(ps, stat))
f5e2ed02
AL		 741 j++;
742 }
743 return j;
e413e7e1
AL		 744}
745
f81ec90f
VD		 746static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
747 uint64_t *data)
e413e7e1 748{
f5e2ed02
AL		 749 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
750 struct mv88e6xxx_hw_stat *stat;
751 int ret;
752 int i, j;
753
754 mutex_lock(&ps->smi_mutex);
755
158bc065 756 ret = _mv88e6xxx_stats_snapshot(ps, port);
f5e2ed02
AL		 757 if (ret < 0) {
758 mutex_unlock(&ps->smi_mutex);
759 return;
760 }
761 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
762 stat = &mv88e6xxx_hw_stats[i];
158bc065
AL		 763 if (mv88e6xxx_has_stat(ps, stat)) {
764 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
f5e2ed02
AL		 765 j++;
766 }
767 }
768
769 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 770}
771
f81ec90f 772static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 773{
774 return 32 * sizeof(u16);
775}
776
f81ec90f
VD		 777static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
778 struct ethtool_regs *regs, void *_p)
a1ab91f3 779{
158bc065 780 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
a1ab91f3
GR		 781 u16 *p = _p;
782 int i;
783
784 regs->version = 0;
785
786 memset(p, 0xff, 32 * sizeof(u16));
787
23062513
VD		 788 mutex_lock(&ps->smi_mutex);
789
a1ab91f3
GR		 790 for (i = 0; i < 32; i++) {
791 int ret;
792
23062513 793 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
a1ab91f3
GR		 794 if (ret >= 0)
795 p[i] = ret;
796 }
23062513
VD		 797
798 mutex_unlock(&ps->smi_mutex);
a1ab91f3
GR		 799}
800
158bc065 801static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
3898c148 802 u16 mask)
f3044683
AL		 803{
804 unsigned long timeout = jiffies + HZ / 10;
805
806 while (time_before(jiffies, timeout)) {
807 int ret;
808
158bc065 809 ret = _mv88e6xxx_reg_read(ps, reg, offset);
3898c148
AL		 810 if (ret < 0)
811 return ret;
f3044683
AL		 812 if (!(ret & mask))
813 return 0;
814
815 usleep_range(1000, 2000);
816 }
817 return -ETIMEDOUT;
818}
819
158bc065
AL		 820static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
821 int offset, u16 mask)
3898c148 822{
3898c148
AL		 823 int ret;
824
825 mutex_lock(&ps->smi_mutex);
158bc065 826 ret = _mv88e6xxx_wait(ps, reg, offset, mask);
3898c148
AL		 827 mutex_unlock(&ps->smi_mutex);
828
829 return ret;
830}
831
158bc065 832static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps)
f3044683 833{
158bc065 834 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 835 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 836}
837
d24645be 838static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
f3044683 839{
158bc065
AL		 840 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
841
842 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 843 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 844}
845
d24645be 846static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
f3044683 847{
158bc065
AL		 848 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
849
850 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 851 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 852}
853
d24645be
VD		 854static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
855{
856 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
857 int ret;
858
859 mutex_lock(&ps->eeprom_mutex);
860
861 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
862 GLOBAL2_EEPROM_OP_READ |
863 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
864 if (ret < 0)
865 goto error;
866
867 ret = mv88e6xxx_eeprom_busy_wait(ds);
868 if (ret < 0)
869 goto error;
870
871 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
872error:
873 mutex_unlock(&ps->eeprom_mutex);
874 return ret;
875}
876
f8cd8753
AL		 877static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
878{
879 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
880
881 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
882 return ps->eeprom_len;
883
884 return 0;
885}
886
f81ec90f
VD		 887static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
888 struct ethtool_eeprom *eeprom, u8 *data)
d24645be
VD		 889{
890 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
891 int offset;
892 int len;
893 int ret;
894
895 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
896 return -EOPNOTSUPP;
897
898 offset = eeprom->offset;
899 len = eeprom->len;
900 eeprom->len = 0;
901
902 eeprom->magic = 0xc3ec4951;
903
904 ret = mv88e6xxx_eeprom_load_wait(ds);
905 if (ret < 0)
906 return ret;
907
908 if (offset & 1) {
909 int word;
910
911 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
912 if (word < 0)
913 return word;
914
915 *data++ = (word >> 8) & 0xff;
916
917 offset++;
918 len--;
919 eeprom->len++;
920 }
921
922 while (len >= 2) {
923 int word;
924
925 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
926 if (word < 0)
927 return word;
928
929 *data++ = word & 0xff;
930 *data++ = (word >> 8) & 0xff;
931
932 offset += 2;
933 len -= 2;
934 eeprom->len += 2;
935 }
936
937 if (len) {
938 int word;
939
940 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
941 if (word < 0)
942 return word;
943
944 *data++ = word & 0xff;
945
946 offset++;
947 len--;
948 eeprom->len++;
949 }
950
951 return 0;
952}
953
954static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
955{
956 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
957 int ret;
958
959 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
960 if (ret < 0)
961 return ret;
962
963 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
964 return -EROFS;
965
966 return 0;
967}
968
969static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
970 u16 data)
971{
972 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
973 int ret;
974
975 mutex_lock(&ps->eeprom_mutex);
976
977 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
978 if (ret < 0)
979 goto error;
980
981 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
982 GLOBAL2_EEPROM_OP_WRITE |
983 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
984 if (ret < 0)
985 goto error;
986
987 ret = mv88e6xxx_eeprom_busy_wait(ds);
988error:
989 mutex_unlock(&ps->eeprom_mutex);
990 return ret;
991}
992
f81ec90f
VD		 993static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
994 struct ethtool_eeprom *eeprom, u8 *data)
d24645be
VD		 995{
996 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
997 int offset;
998 int ret;
999 int len;
1000
1001 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
1002 return -EOPNOTSUPP;
1003
1004 if (eeprom->magic != 0xc3ec4951)
1005 return -EINVAL;
1006
1007 ret = mv88e6xxx_eeprom_is_readonly(ds);
1008 if (ret)
1009 return ret;
1010
1011 offset = eeprom->offset;
1012 len = eeprom->len;
1013 eeprom->len = 0;
1014
1015 ret = mv88e6xxx_eeprom_load_wait(ds);
1016 if (ret < 0)
1017 return ret;
1018
1019 if (offset & 1) {
1020 int word;
1021
1022 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1023 if (word < 0)
1024 return word;
1025
1026 word = (*data++ << 8) | (word & 0xff);
1027
1028 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1029 if (ret < 0)
1030 return ret;
1031
1032 offset++;
1033 len--;
1034 eeprom->len++;
1035 }
1036
1037 while (len >= 2) {
1038 int word;
1039
1040 word = *data++;
1041 word |= *data++ << 8;
1042
1043 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1044 if (ret < 0)
1045 return ret;
1046
1047 offset += 2;
1048 len -= 2;
1049 eeprom->len += 2;
1050 }
1051
1052 if (len) {
1053 int word;
1054
1055 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1056 if (word < 0)
1057 return word;
1058
1059 word = (word & 0xff00) | *data++;
1060
1061 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1062 if (ret < 0)
1063 return ret;
1064
1065 offset++;
1066 len--;
1067 eeprom->len++;
1068 }
1069
1070 return 0;
1071}
1072
158bc065 1073static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
facd95b2 1074{
158bc065 1075 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 1076 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1077}
1078
158bc065
AL		 1079static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps,
1080 int addr, int regnum)
f3044683
AL		 1081{
1082 int ret;
1083
158bc065 1084 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1085 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1086 regnum);
1087 if (ret < 0)
1088 return ret;
f3044683 1089
158bc065 1090 ret = _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1091 if (ret < 0)
1092 return ret;
1093
158bc065
AL		 1094 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1095
1096 return ret;
f3044683
AL		 1097}
1098
158bc065
AL		 1099static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps,
1100 int addr, int regnum, u16 val)
f3044683 1101{
3898c148
AL		 1102 int ret;
1103
158bc065 1104 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 1105 if (ret < 0)
1106 return ret;
f3044683 1107
158bc065 1108 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1109 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1110 regnum);
1111
158bc065 1112 return _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1113}
1114
f81ec90f
VD		 1115static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1116 struct ethtool_eee *e)
11b3b45d 1117{
2f40c698 1118 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 1119 int reg;
1120
aadbdb8a
VD		 1121 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1122 return -EOPNOTSUPP;
1123
3898c148 1124 mutex_lock(&ps->smi_mutex);
2f40c698 1125
158bc065 1126 reg = _mv88e6xxx_phy_read_indirect(ps, port, 16);
11b3b45d 1127 if (reg < 0)
2f40c698 1128 goto out;
11b3b45d
GR		 1129
1130 e->eee_enabled = !!(reg & 0x0200);
1131 e->tx_lpi_enabled = !!(reg & 0x0100);
1132
158bc065 1133 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
11b3b45d 1134 if (reg < 0)
2f40c698 1135 goto out;
11b3b45d 1136
cca8b133 1137 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1138 reg = 0;
11b3b45d 1139
2f40c698 1140out:
3898c148 1141 mutex_unlock(&ps->smi_mutex);
2f40c698 1142 return reg;
11b3b45d
GR		 1143}
1144
f81ec90f
VD		 1145static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1146 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1147{
2f40c698
AL		 1148 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1149 int reg;
11b3b45d
GR		 1150 int ret;
1151
aadbdb8a
VD		 1152 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1153 return -EOPNOTSUPP;
1154
3898c148 1155 mutex_lock(&ps->smi_mutex);
11b3b45d 1156
158bc065 1157 ret = _mv88e6xxx_phy_read_indirect(ps, port, 16);
2f40c698
AL		 1158 if (ret < 0)
1159 goto out;
1160
1161 reg = ret & ~0x0300;
1162 if (e->eee_enabled)
1163 reg |= 0x0200;
1164 if (e->tx_lpi_enabled)
1165 reg |= 0x0100;
1166
158bc065 1167 ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg);
2f40c698 1168out:
3898c148 1169 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 1170
1171 return ret;
11b3b45d
GR		 1172}
1173
158bc065 1174static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
facd95b2
GR		 1175{
1176 int ret;
1177
158bc065
AL		 1178 if (mv88e6xxx_has_fid_reg(ps)) {
1179 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
b426e5f7
VD		 1180 if (ret < 0)
1181 return ret;
158bc065 1182 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f 1183 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
158bc065 1184 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 1185 if (ret < 0)
1186 return ret;
1187
158bc065 1188 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 1189 (ret & 0xfff) |
1190 ((fid << 8) & 0xf000));
1191 if (ret < 0)
1192 return ret;
1193
1194 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1195 cmd |= fid & 0xf;
b426e5f7
VD		 1196 }
1197
158bc065 1198 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1199 if (ret < 0)
1200 return ret;
1201
158bc065 1202 return _mv88e6xxx_atu_wait(ps);
facd95b2
GR		 1203}
1204
158bc065 1205static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
37705b73
VD		 1206 struct mv88e6xxx_atu_entry *entry)
1207{
1208 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1209
1210 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1211 unsigned int mask, shift;
1212
1213 if (entry->trunk) {
1214 data |= GLOBAL_ATU_DATA_TRUNK;
1215 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1216 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1217 } else {
1218 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1219 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1220 }
1221
1222 data |= (entry->portv_trunkid << shift) & mask;
1223 }
1224
158bc065 1225 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1226}
1227
158bc065 1228static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
7fb5e755
VD		 1229 struct mv88e6xxx_atu_entry *entry,
1230 bool static_too)
facd95b2 1231{
7fb5e755
VD		 1232 int op;
1233 int err;
facd95b2 1234
158bc065 1235 err = _mv88e6xxx_atu_wait(ps);
7fb5e755
VD		 1236 if (err)
1237 return err;
facd95b2 1238
158bc065 1239 err = _mv88e6xxx_atu_data_write(ps, entry);
7fb5e755
VD		 1240 if (err)
1241 return err;
1242
1243 if (entry->fid) {
7fb5e755
VD		 1244 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1245 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1246 } else {
1247 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1248 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1249 }
1250
158bc065 1251 return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
7fb5e755
VD		 1252}
1253
158bc065
AL		 1254static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1255 u16 fid, bool static_too)
7fb5e755
VD		 1256{
1257 struct mv88e6xxx_atu_entry entry = {
1258 .fid = fid,
1259 .state = 0, /* EntryState bits must be 0 */
1260 };
70cc99d1 1261
158bc065 1262 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
7fb5e755
VD		 1263}
1264
158bc065
AL		 1265static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1266 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1267{
1268 struct mv88e6xxx_atu_entry entry = {
1269 .trunk = false,
1270 .fid = fid,
1271 };
1272
1273 /* EntryState bits must be 0xF */
1274 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1275
1276 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1277 entry.portv_trunkid = (to_port & 0x0f) << 4;
1278 entry.portv_trunkid |= from_port & 0x0f;
1279
158bc065 1280 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
9f4d55d2
VD		 1281}
1282
158bc065
AL		 1283static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1284 int port, bool static_too)
9f4d55d2
VD		 1285{
1286 /* Destination port 0xF means remove the entries */
158bc065 1287 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1288}
1289
2d9deae4
VD		 1290static const char * const mv88e6xxx_port_state_names[] = {
1291 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1292 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1293 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1294 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1295};
1296
158bc065
AL		 1297static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1298 u8 state)
facd95b2 1299{
158bc065 1300 struct dsa_switch *ds = ps->ds;
c3ffe6d2 1301 int reg, ret = 0;
facd95b2
GR		 1302 u8 oldstate;
1303
158bc065 1304 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1305 if (reg < 0)
1306 return reg;
facd95b2 1307
cca8b133 1308 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1309
facd95b2
GR		 1310 if (oldstate != state) {
1311 /* Flush forwarding database if we're moving a port
1312 * from Learning or Forwarding state to Disabled or
1313 * Blocking or Listening state.
1314 */
2d9deae4
VD		 1315 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1316 oldstate == PORT_CONTROL_STATE_FORWARDING)
1317 && (state == PORT_CONTROL_STATE_DISABLED ||
1318 state == PORT_CONTROL_STATE_BLOCKING)) {
158bc065 1319 ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
facd95b2 1320 if (ret)
2d9deae4 1321 return ret;
facd95b2 1322 }
2d9deae4 1323
cca8b133 1324 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
158bc065 1325 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
cca8b133 1326 reg);
2d9deae4
VD		 1327 if (ret)
1328 return ret;
1329
1330 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1331 mv88e6xxx_port_state_names[state],
1332 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1333 }
1334
facd95b2
GR		 1335 return ret;
1336}
1337
158bc065
AL		 1338static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1339 int port)
facd95b2 1340{
b7666efe 1341 struct net_device *bridge = ps->ports[port].bridge_dev;
009a2b98 1342 const u16 mask = (1 << ps->info->num_ports) - 1;
158bc065 1343 struct dsa_switch *ds = ps->ds;
b7666efe 1344 u16 output_ports = 0;
ede8098d 1345 int reg;
b7666efe
VD		 1346 int i;
1347
1348 /* allow CPU port or DSA link(s) to send frames to every port */
1349 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1350 output_ports = mask;
1351 } else {
009a2b98 1352 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe
VD		 1353 /* allow sending frames to every group member */
1354 if (bridge && ps->ports[i].bridge_dev == bridge)
1355 output_ports |= BIT(i);
1356
1357 /* allow sending frames to CPU port and DSA link(s) */
1358 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1359 output_ports |= BIT(i);
1360 }
1361 }
1362
1363 /* prevent frames from going back out of the port they came in on */
1364 output_ports &= ~BIT(port);
facd95b2 1365
158bc065 1366 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1367 if (reg < 0)
1368 return reg;
facd95b2 1369
ede8098d
VD		 1370 reg &= ~mask;
1371 reg |= output_ports & mask;
facd95b2 1372
158bc065 1373 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1374}
1375
f81ec90f
VD		 1376static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1377 u8 state)
facd95b2
GR		 1378{
1379 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1380 int stp_state;
553eb544 1381 int err;
facd95b2 1382
936f234a
VD		 1383 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1384 return;
1385
facd95b2
GR		 1386 switch (state) {
1387 case BR_STATE_DISABLED:
cca8b133 1388 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1389 break;
1390 case BR_STATE_BLOCKING:
1391 case BR_STATE_LISTENING:
cca8b133 1392 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1393 break;
1394 case BR_STATE_LEARNING:
cca8b133 1395 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1396 break;
1397 case BR_STATE_FORWARDING:
1398 default:
cca8b133 1399 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1400 break;
1401 }
1402
553eb544
VD		 1403 mutex_lock(&ps->smi_mutex);
1404 err = _mv88e6xxx_port_state(ps, port, stp_state);
1405 mutex_unlock(&ps->smi_mutex);
1406
1407 if (err)
1408 netdev_err(ds->ports[port], "failed to update state to %s\n",
1409 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1410}
1411
158bc065
AL		 1412static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1413 u16 *new, u16 *old)
76e398a6 1414{
158bc065 1415 struct dsa_switch *ds = ps->ds;
5da96031 1416 u16 pvid;
76e398a6
VD		 1417 int ret;
1418
158bc065 1419 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1420 if (ret < 0)
1421 return ret;
1422
5da96031
VD		 1423 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1424
1425 if (new) {
1426 ret &= ~PORT_DEFAULT_VLAN_MASK;
1427 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1428
158bc065 1429 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
5da96031
VD		 1430 PORT_DEFAULT_VLAN, ret);
1431 if (ret < 0)
1432 return ret;
1433
1434 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1435 pvid);
1436 }
1437
1438 if (old)
1439 *old = pvid;
76e398a6
VD		 1440
1441 return 0;
1442}
1443
158bc065
AL		 1444static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1445 int port, u16 *pvid)
5da96031 1446{
158bc065 1447 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
5da96031
VD		 1448}
1449
158bc065
AL		 1450static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1451 int port, u16 pvid)
0d3b33e6 1452{
158bc065 1453 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
0d3b33e6
VD		 1454}
1455
158bc065 1456static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
6b17e864 1457{
158bc065 1458 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1459 GLOBAL_VTU_OP_BUSY);
1460}
1461
158bc065 1462static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
6b17e864
VD		 1463{
1464 int ret;
1465
158bc065 1466 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1467 if (ret < 0)
1468 return ret;
1469
158bc065 1470 return _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1471}
1472
158bc065 1473static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
6b17e864
VD		 1474{
1475 int ret;
1476
158bc065 1477 ret = _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1478 if (ret < 0)
1479 return ret;
1480
158bc065 1481 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1482}
1483
158bc065 1484static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1485 struct mv88e6xxx_vtu_stu_entry *entry,
1486 unsigned int nibble_offset)
1487{
b8fee957
VD		 1488 u16 regs[3];
1489 int i;
1490 int ret;
1491
1492 for (i = 0; i < 3; ++i) {
158bc065 1493 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1494 GLOBAL_VTU_DATA_0_3 + i);
1495 if (ret < 0)
1496 return ret;
1497
1498 regs[i] = ret;
1499 }
1500
009a2b98 1501 for (i = 0; i < ps->info->num_ports; ++i) {
b8fee957
VD		 1502 unsigned int shift = (i % 4) * 4 + nibble_offset;
1503 u16 reg = regs[i / 4];
1504
1505 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1506 }
1507
1508 return 0;
1509}
1510
15d7d7d4
VD		 1511static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps,
1512 struct mv88e6xxx_vtu_stu_entry *entry)
1513{
1514 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0);
1515}
1516
1517static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps,
1518 struct mv88e6xxx_vtu_stu_entry *entry)
1519{
1520 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2);
1521}
1522
158bc065 1523static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1524 struct mv88e6xxx_vtu_stu_entry *entry,
1525 unsigned int nibble_offset)
1526{
7dad08d7
VD		 1527 u16 regs[3] = { 0 };
1528 int i;
1529 int ret;
1530
009a2b98 1531 for (i = 0; i < ps->info->num_ports; ++i) {
7dad08d7
VD		 1532 unsigned int shift = (i % 4) * 4 + nibble_offset;
1533 u8 data = entry->data[i];
1534
1535 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1536 }
1537
1538 for (i = 0; i < 3; ++i) {
158bc065 1539 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
7dad08d7
VD		 1540 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1541 if (ret < 0)
1542 return ret;
1543 }
1544
1545 return 0;
1546}
1547
15d7d7d4
VD		 1548static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps,
1549 struct mv88e6xxx_vtu_stu_entry *entry)
1550{
1551 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
1552}
1553
1554static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps,
1555 struct mv88e6xxx_vtu_stu_entry *entry)
1556{
1557 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
1558}
1559
158bc065 1560static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
36d04ba1 1561{
158bc065 1562 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1563 vid & GLOBAL_VTU_VID_MASK);
1564}
1565
158bc065 1566static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1567 struct mv88e6xxx_vtu_stu_entry *entry)
1568{
1569 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1570 int ret;
1571
158bc065 1572 ret = _mv88e6xxx_vtu_wait(ps);
b8fee957
VD		 1573 if (ret < 0)
1574 return ret;
1575
158bc065 1576 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1577 if (ret < 0)
1578 return ret;
1579
158bc065 1580 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1581 if (ret < 0)
1582 return ret;
1583
1584 next.vid = ret & GLOBAL_VTU_VID_MASK;
1585 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1586
1587 if (next.valid) {
15d7d7d4 1588 ret = mv88e6xxx_vtu_data_read(ps, &next);
b8fee957
VD		 1589 if (ret < 0)
1590 return ret;
1591
158bc065
AL		 1592 if (mv88e6xxx_has_fid_reg(ps)) {
1593 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1594 GLOBAL_VTU_FID);
1595 if (ret < 0)
1596 return ret;
1597
1598 next.fid = ret & GLOBAL_VTU_FID_MASK;
158bc065 1599 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1600 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1601 * VTU DBNum[3:0] are located in VTU Operation 3:0
1602 */
158bc065 1603 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
11ea809f
VD		 1604 GLOBAL_VTU_OP);
1605 if (ret < 0)
1606 return ret;
1607
1608 next.fid = (ret & 0xf00) >> 4;
1609 next.fid |= ret & 0xf;
2e7bd5ef 1610 }
b8fee957 1611
cb9b9020 1612 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
158bc065 1613 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1614 GLOBAL_VTU_SID);
1615 if (ret < 0)
1616 return ret;
1617
1618 next.sid = ret & GLOBAL_VTU_SID_MASK;
1619 }
1620 }
1621
1622 *entry = next;
1623 return 0;
1624}
1625
f81ec90f
VD		 1626static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1627 struct switchdev_obj_port_vlan *vlan,
1628 int (*cb)(struct switchdev_obj *obj))
ceff5eff
VD		 1629{
1630 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1631 struct mv88e6xxx_vtu_stu_entry next;
1632 u16 pvid;
1633 int err;
1634
54d77b5b
VD		 1635 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
1636 return -EOPNOTSUPP;
1637
ceff5eff
VD		 1638 mutex_lock(&ps->smi_mutex);
1639
158bc065 1640 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
ceff5eff
VD		 1641 if (err)
1642 goto unlock;
1643
158bc065 1644 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1645 if (err)
1646 goto unlock;
1647
1648 do {
158bc065 1649 err = _mv88e6xxx_vtu_getnext(ps, &next);
ceff5eff
VD		 1650 if (err)
1651 break;
1652
1653 if (!next.valid)
1654 break;
1655
1656 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1657 continue;
1658
1659 /* reinit and dump this VLAN obj */
1660 vlan->vid_begin = vlan->vid_end = next.vid;
1661 vlan->flags = 0;
1662
1663 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1664 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1665
1666 if (next.vid == pvid)
1667 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1668
1669 err = cb(&vlan->obj);
1670 if (err)
1671 break;
1672 } while (next.vid < GLOBAL_VTU_VID_MASK);
1673
1674unlock:
1675 mutex_unlock(&ps->smi_mutex);
1676
1677 return err;
1678}
1679
158bc065 1680static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1681 struct mv88e6xxx_vtu_stu_entry *entry)
1682{
11ea809f 1683 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1684 u16 reg = 0;
1685 int ret;
1686
158bc065 1687 ret = _mv88e6xxx_vtu_wait(ps);
7dad08d7
VD		 1688 if (ret < 0)
1689 return ret;
1690
1691 if (!entry->valid)
1692 goto loadpurge;
1693
1694 /* Write port member tags */
15d7d7d4 1695 ret = mv88e6xxx_vtu_data_write(ps, entry);
7dad08d7
VD		 1696 if (ret < 0)
1697 return ret;
1698
cb9b9020 1699 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
7dad08d7 1700 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1701 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
7dad08d7
VD		 1702 if (ret < 0)
1703 return ret;
b426e5f7 1704 }
7dad08d7 1705
158bc065 1706 if (mv88e6xxx_has_fid_reg(ps)) {
7dad08d7 1707 reg = entry->fid & GLOBAL_VTU_FID_MASK;
158bc065 1708 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
7dad08d7
VD		 1709 if (ret < 0)
1710 return ret;
158bc065 1711 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1712 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1713 * VTU DBNum[3:0] are located in VTU Operation 3:0
1714 */
1715 op |= (entry->fid & 0xf0) << 8;
1716 op |= entry->fid & 0xf;
7dad08d7
VD		 1717 }
1718
1719 reg = GLOBAL_VTU_VID_VALID;
1720loadpurge:
1721 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
158bc065 1722 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1723 if (ret < 0)
1724 return ret;
1725
158bc065 1726 return _mv88e6xxx_vtu_cmd(ps, op);
7dad08d7
VD		 1727}
1728
158bc065 1729static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
0d3b33e6
VD		 1730 struct mv88e6xxx_vtu_stu_entry *entry)
1731{
1732 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1733 int ret;
1734
158bc065 1735 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1736 if (ret < 0)
1737 return ret;
1738
158bc065 1739 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1740 sid & GLOBAL_VTU_SID_MASK);
1741 if (ret < 0)
1742 return ret;
1743
158bc065 1744 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1745 if (ret < 0)
1746 return ret;
1747
158bc065 1748 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1749 if (ret < 0)
1750 return ret;
1751
1752 next.sid = ret & GLOBAL_VTU_SID_MASK;
1753
158bc065 1754 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1755 if (ret < 0)
1756 return ret;
1757
1758 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1759
1760 if (next.valid) {
15d7d7d4 1761 ret = mv88e6xxx_stu_data_read(ps, &next);
0d3b33e6
VD		 1762 if (ret < 0)
1763 return ret;
1764 }
1765
1766 *entry = next;
1767 return 0;
1768}
1769
158bc065 1770static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
0d3b33e6
VD		 1771 struct mv88e6xxx_vtu_stu_entry *entry)
1772{
1773 u16 reg = 0;
1774 int ret;
1775
158bc065 1776 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1777 if (ret < 0)
1778 return ret;
1779
1780 if (!entry->valid)
1781 goto loadpurge;
1782
1783 /* Write port states */
15d7d7d4 1784 ret = mv88e6xxx_stu_data_write(ps, entry);
0d3b33e6
VD		 1785 if (ret < 0)
1786 return ret;
1787
1788 reg = GLOBAL_VTU_VID_VALID;
1789loadpurge:
158bc065 1790 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1791 if (ret < 0)
1792 return ret;
1793
1794 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1795 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1796 if (ret < 0)
1797 return ret;
1798
158bc065 1799 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1800}
1801
158bc065
AL		 1802static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1803 u16 *new, u16 *old)
2db9ce1f 1804{
158bc065 1805 struct dsa_switch *ds = ps->ds;
f74df0be 1806 u16 upper_mask;
2db9ce1f
VD		 1807 u16 fid;
1808 int ret;
1809
158bc065 1810 if (mv88e6xxx_num_databases(ps) == 4096)
f74df0be 1811 upper_mask = 0xff;
158bc065 1812 else if (mv88e6xxx_num_databases(ps) == 256)
11ea809f 1813 upper_mask = 0xf;
f74df0be
VD		 1814 else
1815 return -EOPNOTSUPP;
1816
2db9ce1f 1817 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
158bc065 1818 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1819 if (ret < 0)
1820 return ret;
1821
1822 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1823
1824 if (new) {
1825 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1826 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1827
158bc065 1828 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1829 ret);
1830 if (ret < 0)
1831 return ret;
1832 }
1833
1834 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
158bc065 1835 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1836 if (ret < 0)
1837 return ret;
1838
f74df0be 1839 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1840
1841 if (new) {
f74df0be
VD		 1842 ret &= ~upper_mask;
1843 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1844
158bc065 1845 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1846 ret);
1847 if (ret < 0)
1848 return ret;
1849
1850 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1851 }
1852
1853 if (old)
1854 *old = fid;
1855
1856 return 0;
1857}
1858
158bc065
AL		 1859static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1860 int port, u16 *fid)
2db9ce1f 1861{
158bc065 1862 return _mv88e6xxx_port_fid(ps, port, NULL, fid);
2db9ce1f
VD		 1863}
1864
158bc065
AL		 1865static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1866 int port, u16 fid)
2db9ce1f 1867{
158bc065 1868 return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
2db9ce1f
VD		 1869}
1870
158bc065 1871static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
3285f9e8
VD		 1872{
1873 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1874 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1875 int i, err;
3285f9e8
VD		 1876
1877 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1878
2db9ce1f 1879 /* Set every FID bit used by the (un)bridged ports */
009a2b98 1880 for (i = 0; i < ps->info->num_ports; ++i) {
158bc065 1881 err = _mv88e6xxx_port_fid_get(ps, i, fid);
2db9ce1f
VD		 1882 if (err)
1883 return err;
1884
1885 set_bit(*fid, fid_bitmap);
1886 }
1887
3285f9e8 1888 /* Set every FID bit used by the VLAN entries */
158bc065 1889 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1890 if (err)
1891 return err;
1892
1893 do {
158bc065 1894 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
3285f9e8
VD		 1895 if (err)
1896 return err;
1897
1898 if (!vlan.valid)
1899 break;
1900
1901 set_bit(vlan.fid, fid_bitmap);
1902 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1903
1904 /* The reset value 0x000 is used to indicate that multiple address
1905 * databases are not needed. Return the next positive available.
1906 */
1907 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
158bc065 1908 if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
3285f9e8
VD		 1909 return -ENOSPC;
1910
1911 /* Clear the database */
158bc065 1912 return _mv88e6xxx_atu_flush(ps, *fid, true);
3285f9e8
VD		 1913}
1914
158bc065 1915static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09 1916 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1917{
158bc065 1918 struct dsa_switch *ds = ps->ds;
0d3b33e6
VD		 1919 struct mv88e6xxx_vtu_stu_entry vlan = {
1920 .valid = true,
1921 .vid = vid,
1922 };
3285f9e8
VD		 1923 int i, err;
1924
158bc065 1925 err = _mv88e6xxx_fid_new(ps, &vlan.fid);
3285f9e8
VD		 1926 if (err)
1927 return err;
0d3b33e6 1928
3d131f07 1929 /* exclude all ports except the CPU and DSA ports */
009a2b98 1930 for (i = 0; i < ps->info->num_ports; ++i)
3d131f07
VD		 1931 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1932 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1933 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1934
158bc065
AL		 1935 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1936 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
0d3b33e6 1937 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1938
1939 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1940 * implemented, only one STU entry is needed to cover all VTU
1941 * entries. Thus, validate the SID 0.
1942 */
1943 vlan.sid = 0;
158bc065 1944 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1945 if (err)
1946 return err;
1947
1948 if (vstp.sid != vlan.sid || !vstp.valid) {
1949 memset(&vstp, 0, sizeof(vstp));
1950 vstp.valid = true;
1951 vstp.sid = vlan.sid;
1952
158bc065 1953 err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
0d3b33e6
VD		 1954 if (err)
1955 return err;
1956 }
0d3b33e6
VD		 1957 }
1958
1959 *entry = vlan;
1960 return 0;
1961}
1962
158bc065 1963static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09
VD		 1964 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1965{
1966 int err;
1967
1968 if (!vid)
1969 return -EINVAL;
1970
158bc065 1971 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
2fb5ef09
VD		 1972 if (err)
1973 return err;
1974
158bc065 1975 err = _mv88e6xxx_vtu_getnext(ps, entry);
2fb5ef09
VD		 1976 if (err)
1977 return err;
1978
1979 if (entry->vid != vid || !entry->valid) {
1980 if (!creat)
1981 return -EOPNOTSUPP;
1982 /* -ENOENT would've been more appropriate, but switchdev expects
1983 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1984 */
1985
158bc065 1986 err = _mv88e6xxx_vtu_new(ps, vid, entry);
2fb5ef09
VD		 1987 }
1988
1989 return err;
1990}
1991
da9c359e
VD		 1992static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1993 u16 vid_begin, u16 vid_end)
1994{
1995 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1996 struct mv88e6xxx_vtu_stu_entry vlan;
1997 int i, err;
1998
1999 if (!vid_begin)
2000 return -EOPNOTSUPP;
2001
2002 mutex_lock(&ps->smi_mutex);
2003
158bc065 2004 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
da9c359e
VD		 2005 if (err)
2006 goto unlock;
2007
2008 do {
158bc065 2009 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
da9c359e
VD		 2010 if (err)
2011 goto unlock;
2012
2013 if (!vlan.valid)
2014 break;
2015
2016 if (vlan.vid > vid_end)
2017 break;
2018
009a2b98 2019 for (i = 0; i < ps->info->num_ports; ++i) {
da9c359e
VD		 2020 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2021 continue;
2022
2023 if (vlan.data[i] ==
2024 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2025 continue;
2026
2027 if (ps->ports[i].bridge_dev ==
2028 ps->ports[port].bridge_dev)
2029 break; /* same bridge, check next VLAN */
2030
2031 netdev_warn(ds->ports[port],
2032 "hardware VLAN %d already used by %s\n",
2033 vlan.vid,
2034 netdev_name(ps->ports[i].bridge_dev));
2035 err = -EOPNOTSUPP;
2036 goto unlock;
2037 }
2038 } while (vlan.vid < vid_end);
2039
2040unlock:
2041 mutex_unlock(&ps->smi_mutex);
2042
2043 return err;
2044}
2045
214cdb99
VD		 2046static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2047 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2048 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2049 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2050 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2051};
2052
f81ec90f
VD		 2053static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2054 bool vlan_filtering)
214cdb99
VD		 2055{
2056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2057 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2058 PORT_CONTROL_2_8021Q_DISABLED;
2059 int ret;
2060
54d77b5b
VD		 2061 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2062 return -EOPNOTSUPP;
2063
214cdb99
VD		 2064 mutex_lock(&ps->smi_mutex);
2065
158bc065 2066 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 2067 if (ret < 0)
2068 goto unlock;
2069
2070 old = ret & PORT_CONTROL_2_8021Q_MASK;
2071
5220ef1e
VD		 2072 if (new != old) {
2073 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2074 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2075
158bc065 2076 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 2077 ret);
2078 if (ret < 0)
2079 goto unlock;
2080
2081 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
2082 mv88e6xxx_port_8021q_mode_names[new],
2083 mv88e6xxx_port_8021q_mode_names[old]);
2084 }
214cdb99 2085
5220ef1e 2086 ret = 0;
214cdb99
VD		 2087unlock:
2088 mutex_unlock(&ps->smi_mutex);
2089
2090 return ret;
2091}
2092
f81ec90f
VD		 2093static int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2094 const struct switchdev_obj_port_vlan *vlan,
2095 struct switchdev_trans *trans)
76e398a6 2096{
54d77b5b 2097 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
da9c359e
VD		 2098 int err;
2099
54d77b5b
VD		 2100 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2101 return -EOPNOTSUPP;
2102
da9c359e
VD		 2103 /* If the requested port doesn't belong to the same bridge as the VLAN
2104 * members, do not support it (yet) and fallback to software VLAN.
2105 */
2106 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2107 vlan->vid_end);
2108 if (err)
2109 return err;
2110
76e398a6
VD		 2111 /* We don't need any dynamic resource from the kernel (yet),
2112 * so skip the prepare phase.
2113 */
2114 return 0;
2115}
2116
158bc065
AL		 2117static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2118 u16 vid, bool untagged)
0d3b33e6 2119{
0d3b33e6
VD		 2120 struct mv88e6xxx_vtu_stu_entry vlan;
2121 int err;
2122
158bc065 2123 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
0d3b33e6 2124 if (err)
76e398a6 2125 return err;
0d3b33e6 2126
0d3b33e6
VD		 2127 vlan.data[port] = untagged ?
2128 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2129 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2130
158bc065 2131 return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2132}
2133
f81ec90f
VD		 2134static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2135 const struct switchdev_obj_port_vlan *vlan,
2136 struct switchdev_trans *trans)
76e398a6
VD		 2137{
2138 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2139 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2140 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2141 u16 vid;
76e398a6 2142
54d77b5b
VD		 2143 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2144 return;
2145
76e398a6
VD		 2146 mutex_lock(&ps->smi_mutex);
2147
4d5770b3 2148 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
158bc065 2149 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
4d5770b3
VD		 2150 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
2151 vid, untagged ? 'u' : 't');
76e398a6 2152
158bc065 2153 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
4d5770b3
VD		 2154 netdev_err(ds->ports[port], "failed to set PVID %d\n",
2155 vlan->vid_end);
0d3b33e6 2156
4d5770b3 2157 mutex_unlock(&ps->smi_mutex);
0d3b33e6
VD		 2158}
2159
158bc065
AL		 2160static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2161 int port, u16 vid)
7dad08d7 2162{
158bc065 2163 struct dsa_switch *ds = ps->ds;
7dad08d7 2164 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 2165 int i, err;
2166
158bc065 2167 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
7dad08d7 2168 if (err)
76e398a6 2169 return err;
7dad08d7 2170
2fb5ef09
VD		 2171 /* Tell switchdev if this VLAN is handled in software */
2172 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2173 return -EOPNOTSUPP;
7dad08d7
VD		 2174
2175 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2176
2177 /* keep the VLAN unless all ports are excluded */
f02bdffc 2178 vlan.valid = false;
009a2b98 2179 for (i = 0; i < ps->info->num_ports; ++i) {
3d131f07 2180 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2181 continue;
2182
2183 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2184 vlan.valid = true;
7dad08d7
VD		 2185 break;
2186 }
2187 }
2188
158bc065 2189 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2190 if (err)
2191 return err;
2192
158bc065 2193 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
76e398a6
VD		 2194}
2195
f81ec90f
VD		 2196static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2197 const struct switchdev_obj_port_vlan *vlan)
76e398a6
VD		 2198{
2199 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2200 u16 pvid, vid;
2201 int err = 0;
2202
54d77b5b
VD		 2203 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2204 return -EOPNOTSUPP;
2205
76e398a6
VD		 2206 mutex_lock(&ps->smi_mutex);
2207
158bc065 2208 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
7dad08d7
VD		 2209 if (err)
2210 goto unlock;
2211
76e398a6 2212 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
158bc065 2213 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
76e398a6
VD		 2214 if (err)
2215 goto unlock;
2216
2217 if (vid == pvid) {
158bc065 2218 err = _mv88e6xxx_port_pvid_set(ps, port, 0);
76e398a6
VD		 2219 if (err)
2220 goto unlock;
2221 }
2222 }
2223
7dad08d7
VD		 2224unlock:
2225 mutex_unlock(&ps->smi_mutex);
2226
2227 return err;
2228}
2229
158bc065 2230static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
c5723ac5 2231 const unsigned char *addr)
defb05b9
GR		 2232{
2233 int i, ret;
2234
2235 for (i = 0; i < 3; i++) {
cca8b133 2236 ret = _mv88e6xxx_reg_write(
158bc065 2237 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2238 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2239 if (ret < 0)
2240 return ret;
2241 }
2242
2243 return 0;
2244}
2245
158bc065
AL		 2246static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2247 unsigned char *addr)
defb05b9
GR		 2248{
2249 int i, ret;
2250
2251 for (i = 0; i < 3; i++) {
158bc065 2252 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
cca8b133 2253 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2254 if (ret < 0)
2255 return ret;
2256 addr[i * 2] = ret >> 8;
2257 addr[i * 2 + 1] = ret & 0xff;
2258 }
2259
2260 return 0;
2261}
2262
158bc065 2263static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
fd231c82 2264 struct mv88e6xxx_atu_entry *entry)
defb05b9 2265{
6630e236
VD		 2266 int ret;
2267
158bc065 2268 ret = _mv88e6xxx_atu_wait(ps);
defb05b9
GR		 2269 if (ret < 0)
2270 return ret;
2271
158bc065 2272 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
defb05b9
GR		 2273 if (ret < 0)
2274 return ret;
2275
158bc065 2276 ret = _mv88e6xxx_atu_data_write(ps, entry);
fd231c82 2277 if (ret < 0)
87820510
VD		 2278 return ret;
2279
158bc065 2280 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2281}
87820510 2282
158bc065 2283static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
fd231c82
VD		 2284 const unsigned char *addr, u16 vid,
2285 u8 state)
2286{
2287 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2288 struct mv88e6xxx_vtu_stu_entry vlan;
2289 int err;
2290
2db9ce1f
VD		 2291 /* Null VLAN ID corresponds to the port private database */
2292 if (vid == 0)
158bc065 2293 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2db9ce1f 2294 else
158bc065 2295 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
3285f9e8
VD		 2296 if (err)
2297 return err;
fd231c82 2298
3285f9e8 2299 entry.fid = vlan.fid;
fd231c82
VD		 2300 entry.state = state;
2301 ether_addr_copy(entry.mac, addr);
2302 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2303 entry.trunk = false;
2304 entry.portv_trunkid = BIT(port);
2305 }
2306
158bc065 2307 return _mv88e6xxx_atu_load(ps, &entry);
87820510
VD		 2308}
2309
f81ec90f
VD		 2310static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2311 const struct switchdev_obj_port_fdb *fdb,
2312 struct switchdev_trans *trans)
146a3206 2313{
2672f825
VD		 2314 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2315
2316 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2317 return -EOPNOTSUPP;
2318
146a3206
VD		 2319 /* We don't need any dynamic resource from the kernel (yet),
2320 * so skip the prepare phase.
2321 */
2322 return 0;
2323}
2324
f81ec90f
VD		 2325static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2326 const struct switchdev_obj_port_fdb *fdb,
2327 struct switchdev_trans *trans)
87820510 2328{
1f36faf2 2329 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2330 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2331 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2332 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510 2333
2672f825
VD		 2334 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2335 return;
2336
87820510 2337 mutex_lock(&ps->smi_mutex);
158bc065 2338 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
8497aa61 2339 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2340 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2341}
2342
f81ec90f
VD		 2343static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2344 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2345{
2346 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2347 int ret;
2348
2672f825
VD		 2349 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2350 return -EOPNOTSUPP;
2351
87820510 2352 mutex_lock(&ps->smi_mutex);
158bc065 2353 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
cdf09697 2354 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2355 mutex_unlock(&ps->smi_mutex);
2356
2357 return ret;
2358}
2359
158bc065 2360static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
1d194046 2361 struct mv88e6xxx_atu_entry *entry)
6630e236 2362{
1d194046
VD		 2363 struct mv88e6xxx_atu_entry next = { 0 };
2364 int ret;
2365
2366 next.fid = fid;
defb05b9 2367
158bc065 2368 ret = _mv88e6xxx_atu_wait(ps);
cdf09697
DM		 2369 if (ret < 0)
2370 return ret;
6630e236 2371
158bc065 2372 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2373 if (ret < 0)
2374 return ret;
6630e236 2375
158bc065 2376 ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
1d194046
VD		 2377 if (ret < 0)
2378 return ret;
6630e236 2379
158bc065 2380 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2381 if (ret < 0)
2382 return ret;
6630e236 2383
1d194046
VD		 2384 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2385 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2386 unsigned int mask, shift;
2387
2388 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2389 next.trunk = true;
2390 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2391 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2392 } else {
2393 next.trunk = false;
2394 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2395 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2396 }
2397
2398 next.portv_trunkid = (ret & mask) >> shift;
2399 }
cdf09697 2400
1d194046 2401 *entry = next;
cdf09697
DM		 2402 return 0;
2403}
2404
158bc065
AL		 2405static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2406 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2407 struct switchdev_obj_port_fdb *fdb,
2408 int (*cb)(struct switchdev_obj *obj))
2409{
2410 struct mv88e6xxx_atu_entry addr = {
2411 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2412 };
2413 int err;
2414
158bc065 2415 err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
74b6ba0d
VD		 2416 if (err)
2417 return err;
2418
2419 do {
158bc065 2420 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
74b6ba0d
VD		 2421 if (err)
2422 break;
2423
2424 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2425 break;
2426
2427 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2428 bool is_static = addr.state ==
2429 (is_multicast_ether_addr(addr.mac) ?
2430 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2431 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2432
2433 fdb->vid = vid;
2434 ether_addr_copy(fdb->addr, addr.mac);
2435 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2436
2437 err = cb(&fdb->obj);
2438 if (err)
2439 break;
2440 }
2441 } while (!is_broadcast_ether_addr(addr.mac));
2442
2443 return err;
2444}
2445
f81ec90f
VD		 2446static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2447 struct switchdev_obj_port_fdb *fdb,
2448 int (*cb)(struct switchdev_obj *obj))
f33475bd
VD		 2449{
2450 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2451 struct mv88e6xxx_vtu_stu_entry vlan = {
2452 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2453 };
2db9ce1f 2454 u16 fid;
f33475bd
VD		 2455 int err;
2456
2672f825
VD		 2457 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2458 return -EOPNOTSUPP;
2459
f33475bd
VD		 2460 mutex_lock(&ps->smi_mutex);
2461
2db9ce1f 2462 /* Dump port's default Filtering Information Database (VLAN ID 0) */
158bc065 2463 err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2db9ce1f
VD		 2464 if (err)
2465 goto unlock;
2466
158bc065 2467 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2468 if (err)
2469 goto unlock;
2470
74b6ba0d 2471 /* Dump VLANs' Filtering Information Databases */
158bc065 2472 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
f33475bd
VD		 2473 if (err)
2474 goto unlock;
2475
2476 do {
158bc065 2477 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
f33475bd 2478 if (err)
74b6ba0d 2479 break;
f33475bd
VD		 2480
2481 if (!vlan.valid)
2482 break;
2483
158bc065 2484 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
74b6ba0d 2485 fdb, cb);
f33475bd 2486 if (err)
74b6ba0d 2487 break;
f33475bd
VD		 2488 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2489
2490unlock:
2491 mutex_unlock(&ps->smi_mutex);
2492
2493 return err;
2494}
2495
f81ec90f
VD		 2496static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2497 struct net_device *bridge)
e79a8bcb 2498{
a6692754 2499 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d9619d5 2500 int i, err = 0;
466dfa07 2501
936f234a
VD		 2502 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2503 return -EOPNOTSUPP;
2504
466dfa07
VD		 2505 mutex_lock(&ps->smi_mutex);
2506
b7666efe 2507 /* Assign the bridge and remap each port's VLANTable */
a6692754 2508 ps->ports[port].bridge_dev = bridge;
b7666efe 2509
009a2b98 2510 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe 2511 if (ps->ports[i].bridge_dev == bridge) {
158bc065 2512 err = _mv88e6xxx_port_based_vlan_map(ps, i);
b7666efe
VD		 2513 if (err)
2514 break;
2515 }
2516 }
2517
466dfa07 2518 mutex_unlock(&ps->smi_mutex);
a6692754 2519
466dfa07 2520 return err;
e79a8bcb
VD		 2521}
2522
f81ec90f 2523static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2524{
a6692754 2525 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2526 struct net_device *bridge = ps->ports[port].bridge_dev;
16bfa702 2527 int i;
466dfa07 2528
936f234a
VD		 2529 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2530 return;
2531
466dfa07
VD		 2532 mutex_lock(&ps->smi_mutex);
2533
b7666efe 2534 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2535 ps->ports[port].bridge_dev = NULL;
b7666efe 2536
009a2b98 2537 for (i = 0; i < ps->info->num_ports; ++i)
16bfa702 2538 if (i == port || ps->ports[i].bridge_dev == bridge)
158bc065 2539 if (_mv88e6xxx_port_based_vlan_map(ps, i))
16bfa702 2540 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2541
466dfa07 2542 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2543}
2544
158bc065
AL		 2545static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps,
2546 int port, int page, int reg, int val)
75baacf0
PU		 2547{
2548 int ret;
2549
158bc065 2550 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2551 if (ret < 0)
2552 goto restore_page_0;
2553
158bc065 2554 ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val);
75baacf0 2555restore_page_0:
158bc065 2556 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2557
2558 return ret;
2559}
2560
158bc065
AL		 2561static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps,
2562 int port, int page, int reg)
75baacf0
PU		 2563{
2564 int ret;
2565
158bc065 2566 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2567 if (ret < 0)
2568 goto restore_page_0;
2569
158bc065 2570 ret = _mv88e6xxx_phy_read_indirect(ps, port, reg);
75baacf0 2571restore_page_0:
158bc065 2572 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2573
2574 return ret;
2575}
2576
552238b5
VD		 2577static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2578{
2579 bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE);
2580 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
52638f71 2581 struct gpio_desc *gpiod = ps->reset;
552238b5
VD		 2582 unsigned long timeout;
2583 int ret;
2584 int i;
2585
2586 /* Set all ports to the disabled state. */
2587 for (i = 0; i < ps->info->num_ports; i++) {
2588 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
2589 if (ret < 0)
2590 return ret;
2591
2592 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
2593 ret & 0xfffc);
2594 if (ret)
2595 return ret;
2596 }
2597
2598 /* Wait for transmit queues to drain. */
2599 usleep_range(2000, 4000);
2600
2601 /* If there is a gpio connected to the reset pin, toggle it */
2602 if (gpiod) {
2603 gpiod_set_value_cansleep(gpiod, 1);
2604 usleep_range(10000, 20000);
2605 gpiod_set_value_cansleep(gpiod, 0);
2606 usleep_range(10000, 20000);
2607 }
2608
2609 /* Reset the switch. Keep the PPU active if requested. The PPU
2610 * needs to be active to support indirect phy register access
2611 * through global registers 0x18 and 0x19.
2612 */
2613 if (ppu_active)
2614 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
2615 else
2616 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
2617 if (ret)
2618 return ret;
2619
2620 /* Wait up to one second for reset to complete. */
2621 timeout = jiffies + 1 * HZ;
2622 while (time_before(jiffies, timeout)) {
2623 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
2624 if (ret < 0)
2625 return ret;
2626
2627 if ((ret & is_reset) == is_reset)
2628 break;
2629 usleep_range(1000, 2000);
2630 }
2631 if (time_after(jiffies, timeout))
2632 ret = -ETIMEDOUT;
2633 else
2634 ret = 0;
2635
2636 return ret;
2637}
2638
158bc065 2639static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
13a7ebb3
PU		 2640{
2641 int ret;
2642
158bc065 2643 ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
13a7ebb3
PU		 2644 MII_BMCR);
2645 if (ret < 0)
2646 return ret;
2647
2648 if (ret & BMCR_PDOWN) {
2649 ret &= ~BMCR_PDOWN;
158bc065 2650 ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES,
13a7ebb3
PU		 2651 PAGE_FIBER_SERDES, MII_BMCR,
2652 ret);
2653 }
2654
2655 return ret;
2656}
2657
a1a6a4d1 2658static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
d827e88a 2659{
a1a6a4d1 2660 struct dsa_switch *ds = ps->ds;
f02bdffc 2661 int ret;
54d792f2 2662 u16 reg;
d827e88a 2663
158bc065
AL		 2664 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2665 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2666 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2667 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2668 /* MAC Forcing register: don't force link, speed,
2669 * duplex or flow control state to any particular
2670 * values on physical ports, but force the CPU port
2671 * and all DSA ports to their maximum bandwidth and
2672 * full duplex.
2673 */
158bc065 2674 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2675 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2676 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2677 reg |= PORT_PCS_CTRL_FORCE_LINK |
2678 PORT_PCS_CTRL_LINK_UP |
2679 PORT_PCS_CTRL_DUPLEX_FULL |
2680 PORT_PCS_CTRL_FORCE_DUPLEX;
158bc065 2681 if (mv88e6xxx_6065_family(ps))
54d792f2
AL		 2682 reg |= PORT_PCS_CTRL_100;
2683 else
2684 reg |= PORT_PCS_CTRL_1000;
2685 } else {
2686 reg |= PORT_PCS_CTRL_UNFORCED;
2687 }
2688
158bc065 2689 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2690 PORT_PCS_CTRL, reg);
2691 if (ret)
a1a6a4d1 2692 return ret;
54d792f2
AL		 2693 }
2694
2695 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2696 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2697 * tunneling, determine priority by looking at 802.1p and IP
2698 * priority fields (IP prio has precedence), and set STP state
2699 * to Forwarding.
2700 *
2701 * If this is the CPU link, use DSA or EDSA tagging depending
2702 * on which tagging mode was configured.
2703 *
2704 * If this is a link to another switch, use DSA tagging mode.
2705 *
2706 * If this is the upstream port for this switch, enable
2707 * forwarding of unknown unicasts and multicasts.
2708 */
2709 reg = 0;
158bc065
AL		 2710 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2711 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2712 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2713 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2714 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2715 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2716 PORT_CONTROL_STATE_FORWARDING;
2717 if (dsa_is_cpu_port(ds, port)) {
158bc065 2718 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
54d792f2 2719 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2720 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2721 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2722 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2723 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2724 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2725 else
2726 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2727 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2728 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2729 }
2730
158bc065
AL		 2731 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2732 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2733 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2734 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2735 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2736 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2737 }
2738 }
6083ce71 2739 if (dsa_is_dsa_port(ds, port)) {
158bc065 2740 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
6083ce71 2741 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2742 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2743 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2744 mv88e6xxx_6320_family(ps)) {
54d792f2 2745 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2746 }
2747
54d792f2
AL		 2748 if (port == dsa_upstream_port(ds))
2749 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2750 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2751 }
2752 if (reg) {
158bc065 2753 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2754 PORT_CONTROL, reg);
2755 if (ret)
a1a6a4d1 2756 return ret;
54d792f2
AL		 2757 }
2758
13a7ebb3
PU		 2759 /* If this port is connected to a SerDes, make sure the SerDes is not
2760 * powered down.
2761 */
158bc065
AL		 2762 if (mv88e6xxx_6352_family(ps)) {
2763 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
13a7ebb3 2764 if (ret < 0)
a1a6a4d1 2765 return ret;
13a7ebb3
PU		 2766 ret &= PORT_STATUS_CMODE_MASK;
2767 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2768 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2769 (ret == PORT_STATUS_CMODE_SGMII)) {
158bc065 2770 ret = mv88e6xxx_power_on_serdes(ps);
13a7ebb3 2771 if (ret < 0)
a1a6a4d1 2772 return ret;
13a7ebb3
PU		 2773 }
2774 }
2775
8efdda4a 2776 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2777 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2778 * untagged frames on this port, do a destination address lookup on all
2779 * received packets as usual, disable ARP mirroring and don't send a
2780 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2781 */
2782 reg = 0;
158bc065
AL		 2783 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2784 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2785 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2786 mv88e6xxx_6185_family(ps))
54d792f2
AL		 2787 reg = PORT_CONTROL_2_MAP_DA;
2788
158bc065
AL		 2789 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2790 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2791 reg |= PORT_CONTROL_2_JUMBO_10240;
2792
158bc065 2793 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
54d792f2
AL		 2794 /* Set the upstream port this port should use */
2795 reg |= dsa_upstream_port(ds);
2796 /* enable forwarding of unknown multicast addresses to
2797 * the upstream port
2798 */
2799 if (port == dsa_upstream_port(ds))
2800 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2801 }
2802
46fbe5e5 2803 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2804
54d792f2 2805 if (reg) {
158bc065 2806 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2807 PORT_CONTROL_2, reg);
2808 if (ret)
a1a6a4d1 2809 return ret;
54d792f2
AL		 2810 }
2811
2812 /* Port Association Vector: when learning source addresses
2813 * of packets, add the address to the address database using
2814 * a port bitmap that has only the bit for this port set and
2815 * the other bits clear.
2816 */
4c7ea3c0 2817 reg = 1 << port;
996ecb82
VD		 2818 /* Disable learning for CPU port */
2819 if (dsa_is_cpu_port(ds, port))
65fa4027 2820 reg = 0;
4c7ea3c0 2821
158bc065 2822 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2 2823 if (ret)
a1a6a4d1 2824 return ret;
54d792f2
AL		 2825
2826 /* Egress rate control 2: disable egress rate control. */
158bc065 2827 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2828 0x0000);
2829 if (ret)
a1a6a4d1 2830 return ret;
54d792f2 2831
158bc065
AL		 2832 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2833 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2834 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2835 /* Do not limit the period of time that this port can
2836 * be paused for by the remote end or the period of
2837 * time that this port can pause the remote end.
2838 */
158bc065 2839 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2840 PORT_PAUSE_CTRL, 0x0000);
2841 if (ret)
a1a6a4d1 2842 return ret;
54d792f2
AL		 2843
2844 /* Port ATU control: disable limiting the number of
2845 * address database entries that this port is allowed
2846 * to use.
2847 */
158bc065 2848 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2849 PORT_ATU_CONTROL, 0x0000);
2850 /* Priority Override: disable DA, SA and VTU priority
2851 * override.
2852 */
158bc065 2853 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2854 PORT_PRI_OVERRIDE, 0x0000);
2855 if (ret)
a1a6a4d1 2856 return ret;
54d792f2
AL		 2857
2858 /* Port Ethertype: use the Ethertype DSA Ethertype
2859 * value.
2860 */
158bc065 2861 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2862 PORT_ETH_TYPE, ETH_P_EDSA);
2863 if (ret)
a1a6a4d1 2864 return ret;
54d792f2
AL		 2865 /* Tag Remap: use an identity 802.1p prio -> switch
2866 * prio mapping.
2867 */
158bc065 2868 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2869 PORT_TAG_REGMAP_0123, 0x3210);
2870 if (ret)
a1a6a4d1 2871 return ret;
54d792f2
AL		 2872
2873 /* Tag Remap 2: use an identity 802.1p prio -> switch
2874 * prio mapping.
2875 */
158bc065 2876 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2877 PORT_TAG_REGMAP_4567, 0x7654);
2878 if (ret)
a1a6a4d1 2879 return ret;
54d792f2
AL		 2880 }
2881
158bc065
AL		 2882 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2883 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2884 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2885 mv88e6xxx_6320_family(ps)) {
54d792f2 2886 /* Rate Control: disable ingress rate limiting. */
158bc065 2887 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2888 PORT_RATE_CONTROL, 0x0001);
2889 if (ret)
a1a6a4d1 2890 return ret;
54d792f2
AL		 2891 }
2892
366f0a0f
GR		 2893 /* Port Control 1: disable trunking, disable sending
2894 * learning messages to this port.
d827e88a 2895 */
158bc065 2896 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a 2897 if (ret)
a1a6a4d1 2898 return ret;
d827e88a 2899
207afda1 2900 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2901 * database, and allow bidirectional communication between the
2902 * CPU and DSA port(s), and the other ports.
d827e88a 2903 */
158bc065 2904 ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2db9ce1f 2905 if (ret)
a1a6a4d1 2906 return ret;
2db9ce1f 2907
158bc065 2908 ret = _mv88e6xxx_port_based_vlan_map(ps, port);
d827e88a 2909 if (ret)
a1a6a4d1 2910 return ret;
d827e88a
GR		 2911
2912 /* Default VLAN ID and priority: don't set a default VLAN
2913 * ID, and set the default packet priority to zero.
2914 */
158bc065 2915 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2916 0x0000);
a1a6a4d1
VD		 2917 if (ret)
2918 return ret;
dbde9e66 2919
dbde9e66
AL		 2920 return 0;
2921}
2922
08a01261 2923static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
acdaffcc 2924{
b0745e87
VD		 2925 struct dsa_switch *ds = ps->ds;
2926 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2927 u16 reg;
552238b5 2928 int err;
54d792f2
AL		 2929 int i;
2930
119477bd
VD		 2931 /* Enable the PHY Polling Unit if present, don't discard any packets,
2932 * and mask all interrupt sources.
2933 */
2934 reg = 0;
2935 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
2936 mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
2937 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2938
2939 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
2940 if (err)
2941 return err;
2942
b0745e87
VD		 2943 /* Configure the upstream port, and configure it as the port to which
2944 * ingress and egress and ARP monitor frames are to be sent.
2945 */
2946 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2947 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2948 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2949 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
2950 if (err)
2951 return err;
2952
50484ff4
VD		 2953 /* Disable remote management, and set the switch's DSA device number. */
2954 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
2955 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2956 (ds->index & 0x1f));
2957 if (err)
2958 return err;
2959
54d792f2
AL		 2960 /* Set the default address aging time to 5 minutes, and
2961 * enable address learn messages to be sent to all message
2962 * ports.
2963 */
158bc065 2964 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
48ace4ef
AL		 2965 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2966 if (err)
08a01261 2967 return err;
54d792f2
AL		 2968
2969 /* Configure the IP ToS mapping registers. */
158bc065 2970 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2971 if (err)
08a01261 2972 return err;
158bc065 2973 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2974 if (err)
08a01261 2975 return err;
158bc065 2976 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2977 if (err)
08a01261 2978 return err;
158bc065 2979 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2980 if (err)
08a01261 2981 return err;
158bc065 2982 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2983 if (err)
08a01261 2984 return err;
158bc065 2985 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2986 if (err)
08a01261 2987 return err;
158bc065 2988 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2989 if (err)
08a01261 2990 return err;
158bc065 2991 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2992 if (err)
08a01261 2993 return err;
54d792f2
AL		 2994
2995 /* Configure the IEEE 802.1p priority mapping register. */
158bc065 2996 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2997 if (err)
08a01261 2998 return err;
54d792f2
AL		 2999
3000 /* Send all frames with destination addresses matching
3001 * 01:80:c2:00:00:0x to the CPU port.
3002 */
158bc065 3003 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
48ace4ef 3004 if (err)
08a01261 3005 return err;
54d792f2
AL		 3006
3007 /* Ignore removed tag data on doubly tagged packets, disable
3008 * flow control messages, force flow control priority to the
3009 * highest, and send all special multicast frames to the CPU
3010 * port at the highest priority.
3011 */
158bc065 3012 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
48ace4ef
AL		 3013 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3014 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3015 if (err)
08a01261 3016 return err;
54d792f2
AL		 3017
3018 /* Program the DSA routing table. */
3019 for (i = 0; i < 32; i++) {
3020 int nexthop = 0x1f;
3021
ff04955c 3022 if (ps->ds->cd->rtable &&
08a01261 3023 i != ps->ds->index && i < ps->ds->dst->pd->nr_chips)
ff04955c 3024 nexthop = ps->ds->cd->rtable[i] & 0x1f;
54d792f2 3025
48ace4ef 3026 err = _mv88e6xxx_reg_write(
158bc065 3027 ps, REG_GLOBAL2,
48ace4ef
AL		 3028 GLOBAL2_DEVICE_MAPPING,
3029 GLOBAL2_DEVICE_MAPPING_UPDATE |
3030 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
3031 if (err)
08a01261 3032 return err;
54d792f2
AL		 3033 }
3034
3035 /* Clear all trunk masks. */
48ace4ef 3036 for (i = 0; i < 8; i++) {
158bc065 3037 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
48ace4ef
AL		 3038 0x8000 |
3039 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
009a2b98 3040 ((1 << ps->info->num_ports) - 1));
48ace4ef 3041 if (err)
08a01261 3042 return err;
48ace4ef 3043 }
54d792f2
AL		 3044
3045 /* Clear all trunk mappings. */
48ace4ef
AL		 3046 for (i = 0; i < 16; i++) {
3047 err = _mv88e6xxx_reg_write(
158bc065 3048 ps, REG_GLOBAL2,
48ace4ef
AL		 3049 GLOBAL2_TRUNK_MAPPING,
3050 GLOBAL2_TRUNK_MAPPING_UPDATE |
3051 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
3052 if (err)
08a01261 3053 return err;
48ace4ef 3054 }
54d792f2 3055
158bc065
AL		 3056 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3057 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3058 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 3059 /* Send all frames with destination addresses matching
3060 * 01:80:c2:00:00:2x to the CPU port.
3061 */
158bc065 3062 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3063 GLOBAL2_MGMT_EN_2X, 0xffff);
3064 if (err)
08a01261 3065 return err;
54d792f2
AL		 3066
3067 /* Initialise cross-chip port VLAN table to reset
3068 * defaults.
3069 */
158bc065 3070 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3071 GLOBAL2_PVT_ADDR, 0x9000);
3072 if (err)
08a01261 3073 return err;
54d792f2
AL		 3074
3075 /* Clear the priority override table. */
48ace4ef 3076 for (i = 0; i < 16; i++) {
158bc065 3077 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3078 GLOBAL2_PRIO_OVERRIDE,
3079 0x8000 | (i << 8));
3080 if (err)
08a01261 3081 return err;
48ace4ef 3082 }
54d792f2
AL		 3083 }
3084
158bc065
AL		 3085 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3086 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3087 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
3088 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 3089 /* Disable ingress rate limiting by resetting all
3090 * ingress rate limit registers to their initial
3091 * state.
3092 */
009a2b98 3093 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 3094 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3095 GLOBAL2_INGRESS_OP,
3096 0x9000 | (i << 8));
3097 if (err)
08a01261 3098 return err;
48ace4ef 3099 }
54d792f2
AL		 3100 }
3101
db687a56 3102 /* Clear the statistics counters for all ports */
158bc065 3103 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
48ace4ef
AL		 3104 GLOBAL_STATS_OP_FLUSH_ALL);
3105 if (err)
08a01261 3106 return err;
db687a56
AL		 3107
3108 /* Wait for the flush to complete. */
158bc065 3109 err = _mv88e6xxx_stats_wait(ps);
08a01261
VD		 3110 if (err)
3111 return err;
6b17e864 3112
c161d0a5 3113 /* Clear all ATU entries */
158bc065 3114 err = _mv88e6xxx_atu_flush(ps, 0, true);
08a01261
VD		 3115 if (err)
3116 return err;
c161d0a5 3117
6b17e864 3118 /* Clear all the VTU and STU entries */
158bc065 3119 err = _mv88e6xxx_vtu_stu_flush(ps);
08a01261
VD		 3120 if (err < 0)
3121 return err;
3122
3123 return err;
3124}
3125
f81ec90f 3126static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3127{
a1a6a4d1 3128 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
08a01261 3129 int err;
a1a6a4d1
VD		 3130 int i;
3131
3132 ps->ds = ds;
08a01261 3133
08a01261
VD		 3134 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
3135 mutex_init(&ps->eeprom_mutex);
3136
3137 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3138 mv88e6xxx_ppu_state_init(ps);
3139
3140 mutex_lock(&ps->smi_mutex);
3141
3142 err = mv88e6xxx_switch_reset(ps);
3143 if (err)
3144 goto unlock;
3145
3146 err = mv88e6xxx_setup_global(ps);
a1a6a4d1
VD		 3147 if (err)
3148 goto unlock;
3149
3150 for (i = 0; i < ps->info->num_ports; i++) {
3151 err = mv88e6xxx_setup_port(ps, i);
3152 if (err)
3153 goto unlock;
3154 }
08a01261 3155
6b17e864 3156unlock:
24751e29 3157 mutex_unlock(&ps->smi_mutex);
db687a56 3158
48ace4ef 3159 return err;
54d792f2
AL		 3160}
3161
49143585
AL		 3162int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
3163{
3164 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3165 int ret;
3166
3898c148 3167 mutex_lock(&ps->smi_mutex);
158bc065 3168 ret = _mv88e6xxx_phy_page_read(ps, port, page, reg);
3898c148 3169 mutex_unlock(&ps->smi_mutex);
75baacf0 3170
49143585
AL		 3171 return ret;
3172}
3173
3174int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
3175 int reg, int val)
3176{
3177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3178 int ret;
3179
3898c148 3180 mutex_lock(&ps->smi_mutex);
158bc065 3181 ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val);
3898c148 3182 mutex_unlock(&ps->smi_mutex);
75baacf0 3183
fd3a0ee4
AL		 3184 return ret;
3185}
3186
158bc065
AL		 3187static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps,
3188 int port)
fd3a0ee4 3189{
009a2b98 3190 if (port >= 0 && port < ps->info->num_ports)
fd3a0ee4
AL		 3191 return port;
3192 return -EINVAL;
3193}
3194
f81ec90f 3195static int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
fd3a0ee4
AL		 3196{
3197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3198 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3199 int ret;
3200
3201 if (addr < 0)
158bc065 3202 return 0xffff;
fd3a0ee4 3203
3898c148 3204 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3205
3206 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3207 ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
6d5834a1
VD		 3208 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3209 ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum);
8c9983a2
VD		 3210 else
3211 ret = _mv88e6xxx_phy_read(ps, addr, regnum);
3212
3898c148 3213 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3214 return ret;
3215}
3216
f81ec90f
VD		 3217static int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum,
3218 u16 val)
fd3a0ee4
AL		 3219{
3220 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3221 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3222 int ret;
3223
3224 if (addr < 0)
158bc065 3225 return 0xffff;
fd3a0ee4 3226
3898c148 3227 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3228
3229 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3230 ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
6d5834a1
VD		 3231 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3232 ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val);
8c9983a2
VD		 3233 else
3234 ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
3235
3898c148 3236 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3237 return ret;
3238}
3239
c22995c5
GR		 3240#ifdef CONFIG_NET_DSA_HWMON
3241
3242static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3243{
3244 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3245 int ret;
3246 int val;
3247
3248 *temp = 0;
3249
3250 mutex_lock(&ps->smi_mutex);
3251
158bc065 3252 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6);
c22995c5
GR		 3253 if (ret < 0)
3254 goto error;
3255
3256 /* Enable temperature sensor */
158bc065 3257 ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3258 if (ret < 0)
3259 goto error;
3260
158bc065 3261 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3262 if (ret < 0)
3263 goto error;
3264
3265 /* Wait for temperature to stabilize */
3266 usleep_range(10000, 12000);
3267
158bc065 3268 val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3269 if (val < 0) {
3270 ret = val;
3271 goto error;
3272 }
3273
3274 /* Disable temperature sensor */
158bc065 3275 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3276 if (ret < 0)
3277 goto error;
3278
3279 *temp = ((val & 0x1f) - 5) * 5;
3280
3281error:
158bc065 3282 _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0);
c22995c5
GR		 3283 mutex_unlock(&ps->smi_mutex);
3284 return ret;
3285}
3286
3287static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3288{
158bc065
AL		 3289 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3290 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3291 int ret;
3292
3293 *temp = 0;
3294
3295 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3296 if (ret < 0)
3297 return ret;
3298
3299 *temp = (ret & 0xff) - 25;
3300
3301 return 0;
3302}
3303
f81ec90f 3304static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3305{
158bc065
AL		 3306 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3307
6594f615
VD		 3308 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3309 return -EOPNOTSUPP;
3310
158bc065 3311 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
c22995c5
GR		 3312 return mv88e63xx_get_temp(ds, temp);
3313
3314 return mv88e61xx_get_temp(ds, temp);
3315}
3316
f81ec90f 3317static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3318{
158bc065
AL		 3319 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3320 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3321 int ret;
3322
6594f615 3323 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3324 return -EOPNOTSUPP;
3325
3326 *temp = 0;
3327
3328 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3329 if (ret < 0)
3330 return ret;
3331
3332 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3333
3334 return 0;
3335}
3336
f81ec90f 3337static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3338{
158bc065
AL		 3339 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3340 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3341 int ret;
3342
6594f615 3343 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3344 return -EOPNOTSUPP;
3345
3346 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3347 if (ret < 0)
3348 return ret;
3349 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3350 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3351 (ret & 0xe0ff) | (temp << 8));
3352}
3353
f81ec90f 3354static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3355{
158bc065
AL		 3356 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3357 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3358 int ret;
3359
6594f615 3360 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3361 return -EOPNOTSUPP;
3362
3363 *alarm = false;
3364
3365 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3366 if (ret < 0)
3367 return ret;
3368
3369 *alarm = !!(ret & 0x40);
3370
3371 return 0;
3372}
3373#endif /* CONFIG_NET_DSA_HWMON */
3374
f81ec90f
VD		 3375static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3376 [MV88E6085] = {
3377 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3378 .family = MV88E6XXX_FAMILY_6097,
3379 .name = "Marvell 88E6085",
3380 .num_databases = 4096,
3381 .num_ports = 10,
3382 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3383 },
3384
3385 [MV88E6095] = {
3386 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3387 .family = MV88E6XXX_FAMILY_6095,
3388 .name = "Marvell 88E6095/88E6095F",
3389 .num_databases = 256,
3390 .num_ports = 11,
3391 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3392 },
3393
3394 [MV88E6123] = {
3395 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3396 .family = MV88E6XXX_FAMILY_6165,
3397 .name = "Marvell 88E6123",
3398 .num_databases = 4096,
3399 .num_ports = 3,
3400 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3401 },
3402
3403 [MV88E6131] = {
3404 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3405 .family = MV88E6XXX_FAMILY_6185,
3406 .name = "Marvell 88E6131",
3407 .num_databases = 256,
3408 .num_ports = 8,
3409 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3410 },
3411
3412 [MV88E6161] = {
3413 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3414 .family = MV88E6XXX_FAMILY_6165,
3415 .name = "Marvell 88E6161",
3416 .num_databases = 4096,
3417 .num_ports = 6,
3418 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3419 },
3420
3421 [MV88E6165] = {
3422 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3423 .family = MV88E6XXX_FAMILY_6165,
3424 .name = "Marvell 88E6165",
3425 .num_databases = 4096,
3426 .num_ports = 6,
3427 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3428 },
3429
3430 [MV88E6171] = {
3431 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3432 .family = MV88E6XXX_FAMILY_6351,
3433 .name = "Marvell 88E6171",
3434 .num_databases = 4096,
3435 .num_ports = 7,
3436 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3437 },
3438
3439 [MV88E6172] = {
3440 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3441 .family = MV88E6XXX_FAMILY_6352,
3442 .name = "Marvell 88E6172",
3443 .num_databases = 4096,
3444 .num_ports = 7,
3445 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3446 },
3447
3448 [MV88E6175] = {
3449 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3450 .family = MV88E6XXX_FAMILY_6351,
3451 .name = "Marvell 88E6175",
3452 .num_databases = 4096,
3453 .num_ports = 7,
3454 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3455 },
3456
3457 [MV88E6176] = {
3458 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3459 .family = MV88E6XXX_FAMILY_6352,
3460 .name = "Marvell 88E6176",
3461 .num_databases = 4096,
3462 .num_ports = 7,
3463 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3464 },
3465
3466 [MV88E6185] = {
3467 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3468 .family = MV88E6XXX_FAMILY_6185,
3469 .name = "Marvell 88E6185",
3470 .num_databases = 256,
3471 .num_ports = 10,
3472 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3473 },
3474
3475 [MV88E6240] = {
3476 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3477 .family = MV88E6XXX_FAMILY_6352,
3478 .name = "Marvell 88E6240",
3479 .num_databases = 4096,
3480 .num_ports = 7,
3481 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3482 },
3483
3484 [MV88E6320] = {
3485 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3486 .family = MV88E6XXX_FAMILY_6320,
3487 .name = "Marvell 88E6320",
3488 .num_databases = 4096,
3489 .num_ports = 7,
3490 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3491 },
3492
3493 [MV88E6321] = {
3494 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3495 .family = MV88E6XXX_FAMILY_6320,
3496 .name = "Marvell 88E6321",
3497 .num_databases = 4096,
3498 .num_ports = 7,
3499 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3500 },
3501
3502 [MV88E6350] = {
3503 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3504 .family = MV88E6XXX_FAMILY_6351,
3505 .name = "Marvell 88E6350",
3506 .num_databases = 4096,
3507 .num_ports = 7,
3508 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3509 },
3510
3511 [MV88E6351] = {
3512 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3513 .family = MV88E6XXX_FAMILY_6351,
3514 .name = "Marvell 88E6351",
3515 .num_databases = 4096,
3516 .num_ports = 7,
3517 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3518 },
3519
3520 [MV88E6352] = {
3521 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3522 .family = MV88E6XXX_FAMILY_6352,
3523 .name = "Marvell 88E6352",
3524 .num_databases = 4096,
3525 .num_ports = 7,
3526 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3527 },
3528};
3529
f6271e67
VD		 3530static const struct mv88e6xxx_info *
3531mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
0209d144 3532 unsigned int num)
b9b37713 3533{
a439c061 3534 int i;
b9b37713 3535
b9b37713 3536 for (i = 0; i < num; ++i)
f6271e67
VD		 3537 if (table[i].prod_num == prod_num)
3538 return &table[i];
b9b37713 3539
b9b37713
VD		 3540 return NULL;
3541}
3542
fcdce7d0
AL		 3543static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3544 struct device *host_dev, int sw_addr,
3545 void **priv)
a77d43f1 3546{
f6271e67 3547 const struct mv88e6xxx_info *info;
a77d43f1 3548 struct mv88e6xxx_priv_state *ps;
a439c061 3549 struct mii_bus *bus;
0209d144 3550 const char *name;
a439c061 3551 int id, prod_num, rev;
a77d43f1 3552
a439c061 3553 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3554 if (!bus)
3555 return NULL;
3556
a439c061
VD		 3557 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3558 if (id < 0)
3559 return NULL;
3560
3561 prod_num = (id & 0xfff0) >> 4;
3562 rev = id & 0x000f;
3563
f81ec90f
VD		 3564 info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table,
3565 ARRAY_SIZE(mv88e6xxx_table));
f6271e67 3566 if (!info)
a439c061
VD		 3567 return NULL;
3568
f6271e67
VD		 3569 name = info->name;
3570
a439c061
VD		 3571 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3572 if (!ps)
3573 return NULL;
3574
3575 ps->bus = bus;
3576 ps->sw_addr = sw_addr;
f6271e67 3577 ps->info = info;
b681957a 3578 mutex_init(&ps->smi_mutex);
a439c061
VD		 3579
3580 *priv = ps;
3581
3582 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3583 prod_num, name, rev);
3584
a77d43f1
AL		 3585 return name;
3586}
3587
f81ec90f
VD		 3588struct dsa_switch_driver mv88e6xxx_switch_driver = {
3589 .tag_protocol = DSA_TAG_PROTO_EDSA,
fcdce7d0 3590 .probe = mv88e6xxx_drv_probe,
f81ec90f
VD		 3591 .setup = mv88e6xxx_setup,
3592 .set_addr = mv88e6xxx_set_addr,
3593 .phy_read = mv88e6xxx_phy_read,
3594 .phy_write = mv88e6xxx_phy_write,
3595 .adjust_link = mv88e6xxx_adjust_link,
3596 .get_strings = mv88e6xxx_get_strings,
3597 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3598 .get_sset_count = mv88e6xxx_get_sset_count,
3599 .set_eee = mv88e6xxx_set_eee,
3600 .get_eee = mv88e6xxx_get_eee,
3601#ifdef CONFIG_NET_DSA_HWMON
3602 .get_temp = mv88e6xxx_get_temp,
3603 .get_temp_limit = mv88e6xxx_get_temp_limit,
3604 .set_temp_limit = mv88e6xxx_set_temp_limit,
3605 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3606#endif
f8cd8753 3607 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3608 .get_eeprom = mv88e6xxx_get_eeprom,
3609 .set_eeprom = mv88e6xxx_set_eeprom,
3610 .get_regs_len = mv88e6xxx_get_regs_len,
3611 .get_regs = mv88e6xxx_get_regs,
3612 .port_bridge_join = mv88e6xxx_port_bridge_join,
3613 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3614 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3615 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3616 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3617 .port_vlan_add = mv88e6xxx_port_vlan_add,
3618 .port_vlan_del = mv88e6xxx_port_vlan_del,
3619 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3620 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3621 .port_fdb_add = mv88e6xxx_port_fdb_add,
3622 .port_fdb_del = mv88e6xxx_port_fdb_del,
3623 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3624};
3625
14c7b3c3 3626int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3627{
14c7b3c3 3628 struct device *dev = &mdiodev->dev;
f8cd8753 3629 struct device_node *np = dev->of_node;
14c7b3c3
AL		 3630 struct mv88e6xxx_priv_state *ps;
3631 int id, prod_num, rev;
3632 struct dsa_switch *ds;
f8cd8753 3633 u32 eeprom_len;
52638f71 3634 int err;
14c7b3c3
AL		 3635
3636 ds = devm_kzalloc(dev, sizeof(*ds) + sizeof(*ps), GFP_KERNEL);
3637 if (!ds)
3638 return -ENOMEM;
3639
3640 ps = (struct mv88e6xxx_priv_state *)(ds + 1);
3641 ds->priv = ps;
c33063d6 3642 ds->dev = dev;
14c7b3c3
AL		 3643 ps->dev = dev;
3644 ps->ds = ds;
3645 ps->bus = mdiodev->bus;
3646 ps->sw_addr = mdiodev->addr;
3647 mutex_init(&ps->smi_mutex);
3648
3649 get_device(&ps->bus->dev);
3650
3651 ds->drv = &mv88e6xxx_switch_driver;
3652
3653 id = mv88e6xxx_reg_read(ps, REG_PORT(0), PORT_SWITCH_ID);
3654 if (id < 0)
3655 return id;
3656
3657 prod_num = (id & 0xfff0) >> 4;
3658 rev = id & 0x000f;
3659
3660 ps->info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table,
3661 ARRAY_SIZE(mv88e6xxx_table));
3662 if (!ps->info)
3663 return -ENODEV;
3664
52638f71
AL		 3665 ps->reset = devm_gpiod_get(&mdiodev->dev, "reset", GPIOD_ASIS);
3666 if (IS_ERR(ps->reset)) {
3667 err = PTR_ERR(ps->reset);
3668 if (err == -ENOENT) {
3669 /* Optional, so not an error */
3670 ps->reset = NULL;
3671 } else {
3672 return err;
3673 }
3674 }
3675
f8cd8753
AL		 3676 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) &&
3677 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3678 ps->eeprom_len = eeprom_len;
3679
14c7b3c3
AL		 3680 dev_set_drvdata(dev, ds);
3681
3682 dev_info(dev, "switch 0x%x probed: %s, revision %u\n",
3683 prod_num, ps->info->name, rev);
f81ec90f 3684
98e67308
BH		 3685 return 0;
3686}
14c7b3c3
AL		 3687
3688static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3689{
3690 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3691 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3692
3693 put_device(&ps->bus->dev);
3694}
3695
3696static const struct of_device_id mv88e6xxx_of_match[] = {
3697 { .compatible = "marvell,mv88e6085" },
3698 { /* sentinel */ },
3699};
3700
3701MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3702
3703static struct mdio_driver mv88e6xxx_driver = {
3704 .probe = mv88e6xxx_probe,
3705 .remove = mv88e6xxx_remove,
3706 .mdiodrv.driver = {
3707 .name = "mv88e6085",
3708 .of_match_table = mv88e6xxx_of_match,
3709 },
3710};
3711
3712static int __init mv88e6xxx_init(void)
3713{
3714 register_switch_driver(&mv88e6xxx_switch_driver);
3715 return mdio_driver_register(&mv88e6xxx_driver);
3716}
98e67308
BH		 3717module_init(mv88e6xxx_init);
3718
3719static void __exit mv88e6xxx_cleanup(void)
3720{
14c7b3c3 3721 mdio_driver_unregister(&mv88e6xxx_driver);
f81ec90f 3722 unregister_switch_driver(&mv88e6xxx_switch_driver);
98e67308
BH		 3723}
3724module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3725
3726MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3727MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3728MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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