[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.h

/*
 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __MV88E6XXX_H
#define __MV88E6XXX_H

#ifndef UINT64_MAX
#define UINT64_MAX		(u64)(~((u64)0))
#endif

#define SMI_CMD			0x00
#define SMI_CMD_BUSY		BIT(15)
#define SMI_CMD_CLAUSE_22	BIT(12)
#define SMI_CMD_OP_22_WRITE	((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
#define SMI_CMD_OP_22_READ	((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
#define SMI_CMD_OP_45_WRITE_ADDR	((0 << 10) | SMI_CMD_BUSY)
#define SMI_CMD_OP_45_WRITE_DATA	((1 << 10) | SMI_CMD_BUSY)
#define SMI_CMD_OP_45_READ_DATA		((2 << 10) | SMI_CMD_BUSY)
#define SMI_CMD_OP_45_READ_DATA_INC	((3 << 10) | SMI_CMD_BUSY)
#define SMI_DATA		0x01

#define REG_PORT(p)		(0x10 + (p))
#define PORT_STATUS		0x00
#define PORT_STATUS_PAUSE_EN	BIT(15)
#define PORT_STATUS_MY_PAUSE	BIT(14)
#define PORT_STATUS_HD_FLOW	BIT(13)
#define PORT_STATUS_PHY_DETECT	BIT(12)
#define PORT_STATUS_LINK	BIT(11)
#define PORT_STATUS_DUPLEX	BIT(10)
#define PORT_STATUS_SPEED_MASK	0x0300
#define PORT_STATUS_SPEED_10	0x0000
#define PORT_STATUS_SPEED_100	0x0100
#define PORT_STATUS_SPEED_1000	0x0200
#define PORT_STATUS_EEE		BIT(6) /* 6352 */
#define PORT_STATUS_AM_DIS	BIT(6) /* 6165 */
#define PORT_STATUS_MGMII	BIT(6) /* 6185 */
#define PORT_STATUS_TX_PAUSED	BIT(5)
#define PORT_STATUS_FLOW_CTRL	BIT(4)
#define PORT_PCS_CTRL		0x01
#define PORT_PCS_CTRL_FC		BIT(7)
#define PORT_PCS_CTRL_FORCE_FC		BIT(6)
#define PORT_PCS_CTRL_LINK_UP		BIT(5)
#define PORT_PCS_CTRL_FORCE_LINK	BIT(4)
#define PORT_PCS_CTRL_DUPLEX_FULL	BIT(3)
#define PORT_PCS_CTRL_FORCE_DUPLEX	BIT(2)
#define PORT_PCS_CTRL_10		0x00
#define PORT_PCS_CTRL_100		0x01
#define PORT_PCS_CTRL_1000		0x02
#define PORT_PCS_CTRL_UNFORCED		0x03
#define PORT_PAUSE_CTRL		0x02
#define PORT_SWITCH_ID		0x03
#define PORT_SWITCH_ID_6031	0x0310
#define PORT_SWITCH_ID_6035	0x0350
#define PORT_SWITCH_ID_6046	0x0480
#define PORT_SWITCH_ID_6061	0x0610
#define PORT_SWITCH_ID_6065	0x0650
#define PORT_SWITCH_ID_6085	0x04a0
#define PORT_SWITCH_ID_6092	0x0970
#define PORT_SWITCH_ID_6095	0x0950
#define PORT_SWITCH_ID_6096	0x0980
#define PORT_SWITCH_ID_6097	0x0990
#define PORT_SWITCH_ID_6108	0x1070
#define PORT_SWITCH_ID_6121	0x1040
#define PORT_SWITCH_ID_6122	0x1050
#define PORT_SWITCH_ID_6123	0x1210
#define PORT_SWITCH_ID_6123_A1	0x1212
#define PORT_SWITCH_ID_6123_A2	0x1213
#define PORT_SWITCH_ID_6131	0x1060
#define PORT_SWITCH_ID_6131_B2	0x1066
#define PORT_SWITCH_ID_6152	0x1a40
#define PORT_SWITCH_ID_6155	0x1a50
#define PORT_SWITCH_ID_6161	0x1610
#define PORT_SWITCH_ID_6161_A1	0x1612
#define PORT_SWITCH_ID_6161_A2	0x1613
#define PORT_SWITCH_ID_6165	0x1650
#define PORT_SWITCH_ID_6165_A1	0x1652
#define PORT_SWITCH_ID_6165_A2	0x1653
#define PORT_SWITCH_ID_6171	0x1710
#define PORT_SWITCH_ID_6172	0x1720
#define PORT_SWITCH_ID_6175	0x1750
#define PORT_SWITCH_ID_6176	0x1760
#define PORT_SWITCH_ID_6182	0x1a60
#define PORT_SWITCH_ID_6185	0x1a70
#define PORT_SWITCH_ID_6240	0x2400
#define PORT_SWITCH_ID_6320	0x1250
#define PORT_SWITCH_ID_6350	0x3710
#define PORT_SWITCH_ID_6351	0x3750
#define PORT_SWITCH_ID_6352	0x3520
#define PORT_SWITCH_ID_6352_A0	0x3521
#define PORT_SWITCH_ID_6352_A1	0x3522
#define PORT_CONTROL		0x04
#define PORT_CONTROL_USE_CORE_TAG	BIT(15)
#define PORT_CONTROL_DROP_ON_LOCK	BIT(14)
#define PORT_CONTROL_EGRESS_UNMODIFIED	(0x0 << 12)
#define PORT_CONTROL_EGRESS_UNTAGGED	(0x1 << 12)
#define PORT_CONTROL_EGRESS_TAGGED	(0x2 << 12)
#define PORT_CONTROL_EGRESS_ADD_TAG	(0x3 << 12)
#define PORT_CONTROL_HEADER		BIT(11)
#define PORT_CONTROL_IGMP_MLD_SNOOP	BIT(10)
#define PORT_CONTROL_DOUBLE_TAG		BIT(9)
#define PORT_CONTROL_FRAME_MODE_NORMAL		(0x0 << 8)
#define PORT_CONTROL_FRAME_MODE_DSA		(0x1 << 8)
#define PORT_CONTROL_FRAME_MODE_PROVIDER	(0x2 << 8)
#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA	(0x3 << 8)
#define PORT_CONTROL_DSA_TAG		BIT(8)
#define PORT_CONTROL_VLAN_TUNNEL	BIT(7)
#define PORT_CONTROL_TAG_IF_BOTH	BIT(6)
#define PORT_CONTROL_USE_IP		BIT(5)
#define PORT_CONTROL_USE_TAG		BIT(4)
#define PORT_CONTROL_FORWARD_UNKNOWN_MC	BIT(3)
#define PORT_CONTROL_FORWARD_UNKNOWN	BIT(2)
#define PORT_CONTROL_STATE_MASK		0x03
#define PORT_CONTROL_STATE_DISABLED	0x00
#define PORT_CONTROL_STATE_BLOCKING	0x01
#define PORT_CONTROL_STATE_LEARNING	0x02
#define PORT_CONTROL_STATE_FORWARDING	0x03
#define PORT_CONTROL_1		0x05
#define PORT_BASE_VLAN		0x06
#define PORT_DEFAULT_VLAN	0x07
#define PORT_CONTROL_2		0x08
#define PORT_CONTROL_2_IGNORE_FCS	BIT(15)
#define PORT_CONTROL_2_VTU_PRI_OVERRIDE	BIT(14)
#define PORT_CONTROL_2_SA_PRIO_OVERRIDE	BIT(13)
#define PORT_CONTROL_2_DA_PRIO_OVERRIDE	BIT(12)
#define PORT_CONTROL_2_JUMBO_1522	(0x00 << 12)
#define PORT_CONTROL_2_JUMBO_2048	(0x01 << 12)
#define PORT_CONTROL_2_JUMBO_10240	(0x02 << 12)
#define PORT_CONTROL_2_DISCARD_TAGGED	BIT(9)
#define PORT_CONTROL_2_DISCARD_UNTAGGED	BIT(8)
#define PORT_CONTROL_2_MAP_DA		BIT(7)
#define PORT_CONTROL_2_DEFAULT_FORWARD	BIT(6)
#define PORT_CONTROL_2_FORWARD_UNKNOWN	BIT(6)
#define PORT_CONTROL_2_EGRESS_MONITOR	BIT(5)
#define PORT_CONTROL_2_INGRESS_MONITOR	BIT(4)
#define PORT_RATE_CONTROL	0x09
#define PORT_RATE_CONTROL_2	0x0a
#define PORT_ASSOC_VECTOR	0x0b
#define PORT_ATU_CONTROL	0x0c
#define PORT_PRI_OVERRIDE	0x0d
#define PORT_ETH_TYPE		0x0f
#define PORT_IN_DISCARD_LO	0x10
#define PORT_IN_DISCARD_HI	0x11
#define PORT_IN_FILTERED	0x12
#define PORT_OUT_FILTERED	0x13
#define PORT_TAG_REGMAP_0123	0x18
#define PORT_TAG_REGMAP_4567	0x19

#define REG_GLOBAL		0x1b
#define GLOBAL_STATUS		0x00
#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
/* Two bits for 6165, 6185 etc */
#define GLOBAL_STATUS_PPU_MASK		(0x3 << 14)
#define GLOBAL_STATUS_PPU_DISABLED_RST	(0x0 << 14)
#define GLOBAL_STATUS_PPU_INITIALIZING	(0x1 << 14)
#define GLOBAL_STATUS_PPU_DISABLED	(0x2 << 14)
#define GLOBAL_STATUS_PPU_POLLING	(0x3 << 14)
#define GLOBAL_MAC_01		0x01
#define GLOBAL_MAC_23		0x02
#define GLOBAL_MAC_45		0x03
#define GLOBAL_CONTROL		0x04
#define GLOBAL_CONTROL_SW_RESET		BIT(15)
#define GLOBAL_CONTROL_PPU_ENABLE	BIT(14)
#define GLOBAL_CONTROL_DISCARD_EXCESS	BIT(13) /* 6352 */
#define GLOBAL_CONTROL_SCHED_PRIO	BIT(11) /* 6152 */
#define GLOBAL_CONTROL_MAX_FRAME_1632	BIT(10) /* 6152 */
#define GLOBAL_CONTROL_RELOAD_EEPROM	BIT(9)	/* 6152 */
#define GLOBAL_CONTROL_DEVICE_EN	BIT(7)
#define GLOBAL_CONTROL_STATS_DONE_EN	BIT(6)
#define GLOBAL_CONTROL_VTU_PROBLEM_EN	BIT(5)
#define GLOBAL_CONTROL_VTU_DONE_EN	BIT(4)
#define GLOBAL_CONTROL_ATU_PROBLEM_EN	BIT(3)
#define GLOBAL_CONTROL_ATU_DONE_EN	BIT(2)
#define GLOBAL_CONTROL_TCAM_EN		BIT(1)
#define GLOBAL_CONTROL_EEPROM_DONE_EN	BIT(0)
#define GLOBAL_VTU_OP		0x05
#define GLOBAL_VTU_VID		0x06
#define GLOBAL_VTU_DATA_0_3	0x07
#define GLOBAL_VTU_DATA_4_7	0x08
#define GLOBAL_VTU_DATA_8_11	0x09
#define GLOBAL_ATU_CONTROL	0x0a
#define GLOBAL_ATU_CONTROL_LEARN2ALL	BIT(3)
#define GLOBAL_ATU_OP		0x0b
#define GLOBAL_ATU_OP_BUSY	BIT(15)
#define GLOBAL_ATU_OP_NOP		(0 << 12)
#define GLOBAL_ATU_OP_FLUSH_ALL		((1 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_FLUSH_NON_STATIC	((2 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_LOAD_DB		((3 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_GET_NEXT_DB	((4 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_FLUSH_DB		((5 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_OP_GET_CLR_VIOLATION	  ((7 << 12) | GLOBAL_ATU_OP_BUSY)
#define GLOBAL_ATU_DATA		0x0c
#define GLOBAL_ATU_DATA_TRUNK			BIT(15)
#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK	0x3ff0
#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT	4
#define GLOBAL_ATU_DATA_STATE_MASK		0x0f
#define GLOBAL_ATU_DATA_STATE_UNUSED		0x00
#define GLOBAL_ATU_DATA_STATE_UC_MGMT		0x0d
#define GLOBAL_ATU_DATA_STATE_UC_STATIC		0x0e
#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER	0x0f
#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE	0x05
#define GLOBAL_ATU_DATA_STATE_MC_STATIC		0x07
#define GLOBAL_ATU_DATA_STATE_MC_MGMT		0x0e
#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER	0x0f
#define GLOBAL_ATU_MAC_01	0x0d
#define GLOBAL_ATU_MAC_23	0x0e
#define GLOBAL_ATU_MAC_45	0x0f
#define GLOBAL_IP_PRI_0		0x10
#define GLOBAL_IP_PRI_1		0x11
#define GLOBAL_IP_PRI_2		0x12
#define GLOBAL_IP_PRI_3		0x13
#define GLOBAL_IP_PRI_4		0x14
#define GLOBAL_IP_PRI_5		0x15
#define GLOBAL_IP_PRI_6		0x16
#define GLOBAL_IP_PRI_7		0x17
#define GLOBAL_IEEE_PRI		0x18
#define GLOBAL_CORE_TAG_TYPE	0x19
#define GLOBAL_MONITOR_CONTROL	0x1a
#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT	12
#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT	8
#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT	4
#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT	0
#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED	(0xf0)
#define GLOBAL_CONTROL_2	0x1c
#define GLOBAL_CONTROL_2_NO_CASCADE		0xe000
#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE	0xf000

#define GLOBAL_STATS_OP		0x1d
#define GLOBAL_STATS_OP_BUSY	BIT(15)
#define GLOBAL_STATS_OP_NOP		(0 << 12)
#define GLOBAL_STATS_OP_FLUSH_ALL	((1 << 12) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_FLUSH_PORT	((2 << 12) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_READ_CAPTURED	((4 << 12) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_CAPTURE_PORT	((5 << 12) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_HIST_RX		((1 << 10) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_HIST_TX		((2 << 10) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_OP_HIST_RX_TX	((3 << 10) | GLOBAL_STATS_OP_BUSY)
#define GLOBAL_STATS_COUNTER_32	0x1e
#define GLOBAL_STATS_COUNTER_01	0x1f

#define REG_GLOBAL2		0x1c
#define GLOBAL2_INT_SOURCE	0x00
#define GLOBAL2_INT_MASK	0x01
#define GLOBAL2_MGMT_EN_2X	0x02
#define GLOBAL2_MGMT_EN_0X	0x03
#define GLOBAL2_FLOW_CONTROL	0x04
#define GLOBAL2_SWITCH_MGMT	0x05
#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA	BIT(15)
#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS	BIT(14)
#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG	BIT(13)
#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI	BIT(7)
#define GLOBAL2_SWITCH_MGMT_RSVD2CPU		BIT(3)
#define GLOBAL2_DEVICE_MAPPING	0x06
#define GLOBAL2_DEVICE_MAPPING_UPDATE		BIT(15)
#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT	8
#define GLOBAL2_DEVICE_MAPPING_PORT_MASK	0x0f
#define GLOBAL2_TRUNK_MASK	0x07
#define GLOBAL2_TRUNK_MASK_UPDATE		BIT(15)
#define GLOBAL2_TRUNK_MASK_NUM_SHIFT		12
#define GLOBAL2_TRUNK_MAPPING	0x08
#define GLOBAL2_TRUNK_MAPPING_UPDATE		BIT(15)
#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT		11
#define GLOBAL2_INGRESS_OP	0x09
#define GLOBAL2_INGRESS_DATA	0x0a
#define GLOBAL2_PVT_ADDR	0x0b
#define GLOBAL2_PVT_DATA	0x0c
#define GLOBAL2_SWITCH_MAC	0x0d
#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
#define GLOBAL2_ATU_STATS	0x0e
#define GLOBAL2_PRIO_OVERRIDE	0x0f
#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP	BIT(7)
#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT	4
#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP		BIT(3)
#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT		0
#define GLOBAL2_EEPROM_OP	0x14
#define GLOBAL2_EEPROM_OP_BUSY	BIT(15)
#define GLOBAL2_EEPROM_OP_LOAD	BIT(11)
#define GLOBAL2_EEPROM_DATA	0x15
#define GLOBAL2_PTP_AVB_OP	0x16
#define GLOBAL2_PTP_AVB_DATA	0x17
#define GLOBAL2_SMI_OP		0x18
#define GLOBAL2_SMI_OP_BUSY		BIT(15)
#define GLOBAL2_SMI_OP_CLAUSE_22	BIT(12)
#define GLOBAL2_SMI_OP_22_WRITE		((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
					 GLOBAL2_SMI_OP_CLAUSE_22)
#define GLOBAL2_SMI_OP_22_READ		((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
					 GLOBAL2_SMI_OP_CLAUSE_22)
#define GLOBAL2_SMI_OP_45_WRITE_ADDR	((0 << 10) | GLOBAL2_SMI_OP_BUSY)
#define GLOBAL2_SMI_OP_45_WRITE_DATA	((1 << 10) | GLOBAL2_SMI_OP_BUSY)
#define GLOBAL2_SMI_OP_45_READ_DATA	((2 << 10) | GLOBAL2_SMI_OP_BUSY)
#define GLOBAL2_SMI_DATA	0x19
#define GLOBAL2_SCRATCH_MISC	0x1a
#define GLOBAL2_SCRATCH_BUSY		BIT(15)
#define GLOBAL2_SCRATCH_REGISTER_SHIFT	8
#define GLOBAL2_SCRATCH_VALUE_MASK	0xff
#define GLOBAL2_WDOG_CONTROL	0x1b
#define GLOBAL2_QOS_WEIGHT	0x1c
#define GLOBAL2_MISC		0x1d

struct mv88e6xxx_priv_state {
	/* When using multi-chip addressing, this mutex protects
	 * access to the indirect access registers.  (In single-chip
	 * mode, this mutex is effectively useless.)
	 */
	struct mutex	smi_mutex;

#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
	/* Handles automatic disabling and re-enabling of the PHY
	 * polling unit.
	 */
	struct mutex		ppu_mutex;
	int			ppu_disabled;
	struct work_struct	ppu_work;
	struct timer_list	ppu_timer;
#endif

	/* This mutex serialises access to the statistics unit.
	 * Hold this mutex over snapshot + dump sequences.
	 */
	struct mutex	stats_mutex;

	/* This mutex serializes phy access for chips with
	 * indirect phy addressing. It is unused for chips
	 * with direct phy access.
	 */
	struct mutex	phy_mutex;

	/* This mutex serializes eeprom access for chips with
	 * eeprom support.
	 */
	struct mutex eeprom_mutex;

	int		id; /* switch product id */
	int		num_ports;	/* number of switch ports */

	/* hw bridging */

	u32 fid_mask;
	u8 fid[DSA_MAX_PORTS];
	u16 bridge_mask[DSA_MAX_PORTS];

	unsigned long port_state_update_mask;
	u8 port_state[DSA_MAX_PORTS];

	struct work_struct bridge_work;

	struct dentry *dbgfs;
};

struct mv88e6xxx_hw_stat {
	char string[ETH_GSTRING_LEN];
	int sizeof_stat;
	int reg;
};

int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
int mv88e6xxx_setup_ports(struct dsa_switch *ds);
int mv88e6xxx_setup_common(struct dsa_switch *ds);
int mv88e6xxx_setup_global(struct dsa_switch *ds);
int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
			  int reg, u16 val);
int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
				 u16 val);
void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
			    int regnum, u16 val);
void mv88e6xxx_poll_link(struct dsa_switch *ds);
void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
				 uint64_t *data);
int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			struct ethtool_regs *regs, void *_p);
int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
				 u16 val);
int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
		      struct phy_device *phydev, struct ethtool_eee *e);
int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
			   const unsigned char *addr, u16 vid);
int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
			   const unsigned char *addr, u16 vid);
int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
			       unsigned char *addr, bool *is_static);
int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
			     int reg, int val);
extern struct dsa_switch_driver mv88e6131_switch_driver;
extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
extern struct dsa_switch_driver mv88e6352_switch_driver;
extern struct dsa_switch_driver mv88e6171_switch_driver;

#define REG_READ(addr, reg)						\
	({								\
		int __ret;						\
									\
		__ret = mv88e6xxx_reg_read(ds, addr, reg);		\
		if (__ret < 0)						\
			return __ret;					\
		__ret;							\
	})

#define REG_WRITE(addr, reg, val)					\
	({								\
		int __ret;						\
									\
		__ret = mv88e6xxx_reg_write(ds, addr, reg, val);	\
		if (__ret < 0)						\
			return __ret;					\
	})


#endif
Commit	Line	Data
91da11f8 LB	1	/*
	2	* net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
	3	* Copyright (c) 2008 Marvell Semiconductor
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#ifndef __MV88E6XXX_H
	12	#define __MV88E6XXX_H
	13
80c4627b AL	14	#ifndef UINT64_MAX
	15	#define UINT64_MAX (u64)(~((u64)0))
	16	#endif
	17
cca8b133 AL	18	#define SMI_CMD 0x00
	19	#define SMI_CMD_BUSY BIT(15)
	20	#define SMI_CMD_CLAUSE_22 BIT(12)
	21	#define SMI_CMD_OP_22_WRITE ((1 << 10) \| SMI_CMD_BUSY \| SMI_CMD_CLAUSE_22)
	22	#define SMI_CMD_OP_22_READ ((2 << 10) \| SMI_CMD_BUSY \| SMI_CMD_CLAUSE_22)
	23	#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) \| SMI_CMD_BUSY)
	24	#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) \| SMI_CMD_BUSY)
	25	#define SMI_CMD_OP_45_READ_DATA ((2 << 10) \| SMI_CMD_BUSY)
	26	#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) \| SMI_CMD_BUSY)
	27	#define SMI_DATA 0x01
b2eb0662	28
91da11f8	29	#define REG_PORT(p) (0x10 + (p))
cca8b133 AL	30	#define PORT_STATUS 0x00
	31	#define PORT_STATUS_PAUSE_EN BIT(15)
	32	#define PORT_STATUS_MY_PAUSE BIT(14)
	33	#define PORT_STATUS_HD_FLOW BIT(13)
	34	#define PORT_STATUS_PHY_DETECT BIT(12)
	35	#define PORT_STATUS_LINK BIT(11)
	36	#define PORT_STATUS_DUPLEX BIT(10)
	37	#define PORT_STATUS_SPEED_MASK 0x0300
	38	#define PORT_STATUS_SPEED_10 0x0000
	39	#define PORT_STATUS_SPEED_100 0x0100
	40	#define PORT_STATUS_SPEED_1000 0x0200
	41	#define PORT_STATUS_EEE BIT(6) /* 6352 */
	42	#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
	43	#define PORT_STATUS_MGMII BIT(6) /* 6185 */
	44	#define PORT_STATUS_TX_PAUSED BIT(5)
	45	#define PORT_STATUS_FLOW_CTRL BIT(4)
	46	#define PORT_PCS_CTRL 0x01
54d792f2 AL	47	#define PORT_PCS_CTRL_FC BIT(7)
	48	#define PORT_PCS_CTRL_FORCE_FC BIT(6)
	49	#define PORT_PCS_CTRL_LINK_UP BIT(5)
	50	#define PORT_PCS_CTRL_FORCE_LINK BIT(4)
	51	#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
	52	#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
	53	#define PORT_PCS_CTRL_10 0x00
	54	#define PORT_PCS_CTRL_100 0x01
	55	#define PORT_PCS_CTRL_1000 0x02
	56	#define PORT_PCS_CTRL_UNFORCED 0x03
	57	#define PORT_PAUSE_CTRL 0x02
cca8b133	58	#define PORT_SWITCH_ID 0x03
54d792f2 AL	59	#define PORT_SWITCH_ID_6031 0x0310
	60	#define PORT_SWITCH_ID_6035 0x0350
	61	#define PORT_SWITCH_ID_6046 0x0480
	62	#define PORT_SWITCH_ID_6061 0x0610
	63	#define PORT_SWITCH_ID_6065 0x0650
cca8b133	64	#define PORT_SWITCH_ID_6085 0x04a0
54d792f2	65	#define PORT_SWITCH_ID_6092 0x0970
cca8b133	66	#define PORT_SWITCH_ID_6095 0x0950
54d792f2 AL	67	#define PORT_SWITCH_ID_6096 0x0980
	68	#define PORT_SWITCH_ID_6097 0x0990
	69	#define PORT_SWITCH_ID_6108 0x1070
	70	#define PORT_SWITCH_ID_6121 0x1040
	71	#define PORT_SWITCH_ID_6122 0x1050
cca8b133 AL	72	#define PORT_SWITCH_ID_6123 0x1210
	73	#define PORT_SWITCH_ID_6123_A1 0x1212
	74	#define PORT_SWITCH_ID_6123_A2 0x1213
	75	#define PORT_SWITCH_ID_6131 0x1060
	76	#define PORT_SWITCH_ID_6131_B2 0x1066
	77	#define PORT_SWITCH_ID_6152 0x1a40
	78	#define PORT_SWITCH_ID_6155 0x1a50
	79	#define PORT_SWITCH_ID_6161 0x1610
	80	#define PORT_SWITCH_ID_6161_A1 0x1612
	81	#define PORT_SWITCH_ID_6161_A2 0x1613
	82	#define PORT_SWITCH_ID_6165 0x1650
	83	#define PORT_SWITCH_ID_6165_A1 0x1652
	84	#define PORT_SWITCH_ID_6165_A2 0x1653
	85	#define PORT_SWITCH_ID_6171 0x1710
	86	#define PORT_SWITCH_ID_6172 0x1720
54d792f2	87	#define PORT_SWITCH_ID_6175 0x1750
cca8b133 AL	88	#define PORT_SWITCH_ID_6176 0x1760
	89	#define PORT_SWITCH_ID_6182 0x1a60
	90	#define PORT_SWITCH_ID_6185 0x1a70
54d792f2 AL	91	#define PORT_SWITCH_ID_6240 0x2400
	92	#define PORT_SWITCH_ID_6320 0x1250
	93	#define PORT_SWITCH_ID_6350 0x3710
	94	#define PORT_SWITCH_ID_6351 0x3750
cca8b133 AL	95	#define PORT_SWITCH_ID_6352 0x3520
	96	#define PORT_SWITCH_ID_6352_A0 0x3521
	97	#define PORT_SWITCH_ID_6352_A1 0x3522
	98	#define PORT_CONTROL 0x04
54d792f2 AL	99	#define PORT_CONTROL_USE_CORE_TAG BIT(15)
	100	#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
	101	#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
	102	#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
	103	#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
	104	#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
	105	#define PORT_CONTROL_HEADER BIT(11)
	106	#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
	107	#define PORT_CONTROL_DOUBLE_TAG BIT(9)
	108	#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
	109	#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
	110	#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
	111	#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
	112	#define PORT_CONTROL_DSA_TAG BIT(8)
	113	#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
	114	#define PORT_CONTROL_TAG_IF_BOTH BIT(6)
	115	#define PORT_CONTROL_USE_IP BIT(5)
	116	#define PORT_CONTROL_USE_TAG BIT(4)
	117	#define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
	118	#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
cca8b133 AL	119	#define PORT_CONTROL_STATE_MASK 0x03
	120	#define PORT_CONTROL_STATE_DISABLED 0x00
	121	#define PORT_CONTROL_STATE_BLOCKING 0x01
	122	#define PORT_CONTROL_STATE_LEARNING 0x02
	123	#define PORT_CONTROL_STATE_FORWARDING 0x03
	124	#define PORT_CONTROL_1 0x05
	125	#define PORT_BASE_VLAN 0x06
	126	#define PORT_DEFAULT_VLAN 0x07
	127	#define PORT_CONTROL_2 0x08
54d792f2 AL	128	#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
	129	#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
	130	#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
	131	#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
	132	#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
	133	#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
	134	#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
	135	#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
	136	#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
	137	#define PORT_CONTROL_2_MAP_DA BIT(7)
	138	#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
	139	#define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
	140	#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
	141	#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
cca8b133 AL	142	#define PORT_RATE_CONTROL 0x09
	143	#define PORT_RATE_CONTROL_2 0x0a
	144	#define PORT_ASSOC_VECTOR 0x0b
54d792f2 AL	145	#define PORT_ATU_CONTROL 0x0c
	146	#define PORT_PRI_OVERRIDE 0x0d
	147	#define PORT_ETH_TYPE 0x0f
cca8b133 AL	148	#define PORT_IN_DISCARD_LO 0x10
	149	#define PORT_IN_DISCARD_HI 0x11
	150	#define PORT_IN_FILTERED 0x12
	151	#define PORT_OUT_FILTERED 0x13
54d792f2 AL	152	#define PORT_TAG_REGMAP_0123 0x18
54d792f2 AL	153	#define PORT_TAG_REGMAP_4567 0x19
facd95b2	154
cca8b133 AL	155	#define REG_GLOBAL 0x1b
	156	#define GLOBAL_STATUS 0x00
	157	#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
	158	/* Two bits for 6165, 6185 etc */
	159	#define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
	160	#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
	161	#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
	162	#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
	163	#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
	164	#define GLOBAL_MAC_01 0x01
	165	#define GLOBAL_MAC_23 0x02
	166	#define GLOBAL_MAC_45 0x03
	167	#define GLOBAL_CONTROL 0x04
	168	#define GLOBAL_CONTROL_SW_RESET BIT(15)
	169	#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
	170	#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
	171	#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
	172	#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
54d792f2	173	#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
cca8b133 AL	174	#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
	175	#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
	176	#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
	177	#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
	178	#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
	179	#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
	180	#define GLOBAL_CONTROL_TCAM_EN BIT(1)
	181	#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
	182	#define GLOBAL_VTU_OP 0x05
	183	#define GLOBAL_VTU_VID 0x06
	184	#define GLOBAL_VTU_DATA_0_3 0x07
	185	#define GLOBAL_VTU_DATA_4_7 0x08
	186	#define GLOBAL_VTU_DATA_8_11 0x09
	187	#define GLOBAL_ATU_CONTROL 0x0a
54d792f2	188	#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
cca8b133 AL	189	#define GLOBAL_ATU_OP 0x0b
	190	#define GLOBAL_ATU_OP_BUSY BIT(15)
	191	#define GLOBAL_ATU_OP_NOP (0 << 12)
	192	#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) \| GLOBAL_ATU_OP_BUSY)
	193	#define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) \| GLOBAL_ATU_OP_BUSY)
	194	#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) \| GLOBAL_ATU_OP_BUSY)
	195	#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) \| GLOBAL_ATU_OP_BUSY)
	196	#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) \| GLOBAL_ATU_OP_BUSY)
	197	#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) \| GLOBAL_ATU_OP_BUSY)
	198	#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) \| GLOBAL_ATU_OP_BUSY)
	199	#define GLOBAL_ATU_DATA 0x0c
8a0a265d AL	200	#define GLOBAL_ATU_DATA_TRUNK BIT(15)
	201	#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
	202	#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
cca8b133 AL	203	#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
	204	#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
	205	#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
	206	#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
	207	#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
	208	#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
	209	#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
	210	#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
	211	#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
	212	#define GLOBAL_ATU_MAC_01 0x0d
	213	#define GLOBAL_ATU_MAC_23 0x0e
	214	#define GLOBAL_ATU_MAC_45 0x0f
	215	#define GLOBAL_IP_PRI_0 0x10
	216	#define GLOBAL_IP_PRI_1 0x11
	217	#define GLOBAL_IP_PRI_2 0x12
	218	#define GLOBAL_IP_PRI_3 0x13
	219	#define GLOBAL_IP_PRI_4 0x14
	220	#define GLOBAL_IP_PRI_5 0x15
	221	#define GLOBAL_IP_PRI_6 0x16
	222	#define GLOBAL_IP_PRI_7 0x17
	223	#define GLOBAL_IEEE_PRI 0x18
	224	#define GLOBAL_CORE_TAG_TYPE 0x19
	225	#define GLOBAL_MONITOR_CONTROL 0x1a
15966a2a AL	226	#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
	227	#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
	228	#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
	229	#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
	230	#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
cca8b133	231	#define GLOBAL_CONTROL_2 0x1c
15966a2a AL	232	#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
	233	#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
	234
cca8b133 AL	235	#define GLOBAL_STATS_OP 0x1d
	236	#define GLOBAL_STATS_OP_BUSY BIT(15)
	237	#define GLOBAL_STATS_OP_NOP (0 << 12)
	238	#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) \| GLOBAL_STATS_OP_BUSY)
	239	#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) \| GLOBAL_STATS_OP_BUSY)
	240	#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) \| GLOBAL_STATS_OP_BUSY)
	241	#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) \| GLOBAL_STATS_OP_BUSY)
	242	#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) \| GLOBAL_STATS_OP_BUSY)
	243	#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) \| GLOBAL_STATS_OP_BUSY)
	244	#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) \| GLOBAL_STATS_OP_BUSY)
	245	#define GLOBAL_STATS_COUNTER_32 0x1e
	246	#define GLOBAL_STATS_COUNTER_01 0x1f
defb05b9	247
cca8b133 AL	248	#define REG_GLOBAL2 0x1c
	249	#define GLOBAL2_INT_SOURCE 0x00
	250	#define GLOBAL2_INT_MASK 0x01
	251	#define GLOBAL2_MGMT_EN_2X 0x02
	252	#define GLOBAL2_MGMT_EN_0X 0x03
	253	#define GLOBAL2_FLOW_CONTROL 0x04
	254	#define GLOBAL2_SWITCH_MGMT 0x05
54d792f2 AL	255	#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
	256	#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
	257	#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
	258	#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
	259	#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
cca8b133	260	#define GLOBAL2_DEVICE_MAPPING 0x06
54d792f2 AL	261	#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
54d792f2 AL	262	#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
d35bd876	263	#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
cca8b133	264	#define GLOBAL2_TRUNK_MASK 0x07
54d792f2 AL	265	#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
54d792f2 AL	266	#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
cca8b133	267	#define GLOBAL2_TRUNK_MAPPING 0x08
54d792f2 AL	268	#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
54d792f2 AL	269	#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
cca8b133 AL	270	#define GLOBAL2_INGRESS_OP 0x09
	271	#define GLOBAL2_INGRESS_DATA 0x0a
	272	#define GLOBAL2_PVT_ADDR 0x0b
	273	#define GLOBAL2_PVT_DATA 0x0c
	274	#define GLOBAL2_SWITCH_MAC 0x0d
	275	#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
	276	#define GLOBAL2_ATU_STATS 0x0e
	277	#define GLOBAL2_PRIO_OVERRIDE 0x0f
15966a2a AL	278	#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
	279	#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
	280	#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
	281	#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
cca8b133 AL	282	#define GLOBAL2_EEPROM_OP 0x14
	283	#define GLOBAL2_EEPROM_OP_BUSY BIT(15)
	284	#define GLOBAL2_EEPROM_OP_LOAD BIT(11)
	285	#define GLOBAL2_EEPROM_DATA 0x15
	286	#define GLOBAL2_PTP_AVB_OP 0x16
	287	#define GLOBAL2_PTP_AVB_DATA 0x17
	288	#define GLOBAL2_SMI_OP 0x18
	289	#define GLOBAL2_SMI_OP_BUSY BIT(15)
	290	#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
	291	#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) \| GLOBAL2_SMI_OP_BUSY \| \
	292	GLOBAL2_SMI_OP_CLAUSE_22)
	293	#define GLOBAL2_SMI_OP_22_READ ((2 << 10) \| GLOBAL2_SMI_OP_BUSY \| \
	294	GLOBAL2_SMI_OP_CLAUSE_22)
	295	#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) \| GLOBAL2_SMI_OP_BUSY)
	296	#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) \| GLOBAL2_SMI_OP_BUSY)
	297	#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) \| GLOBAL2_SMI_OP_BUSY)
	298	#define GLOBAL2_SMI_DATA 0x19
	299	#define GLOBAL2_SCRATCH_MISC 0x1a
56d95e22 AL	300	#define GLOBAL2_SCRATCH_BUSY BIT(15)
	301	#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
	302	#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
cca8b133 AL	303	#define GLOBAL2_WDOG_CONTROL 0x1b
	304	#define GLOBAL2_QOS_WEIGHT 0x1c
	305	#define GLOBAL2_MISC 0x1d
defb05b9	306
91da11f8	307	struct mv88e6xxx_priv_state {
3675c8d7	308	/* When using multi-chip addressing, this mutex protects
91da11f8 LB	309	* access to the indirect access registers. (In single-chip
	310	* mode, this mutex is effectively useless.)
	311	*/
	312	struct mutex smi_mutex;
	313
2e5f0320	314	#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
3675c8d7	315	/* Handles automatic disabling and re-enabling of the PHY
2e5f0320 LB	316	* polling unit.
	317	*/
	318	struct mutex ppu_mutex;
	319	int ppu_disabled;
	320	struct work_struct ppu_work;
	321	struct timer_list ppu_timer;
	322	#endif
	323
3675c8d7	324	/* This mutex serialises access to the statistics unit.
91da11f8 LB	325	* Hold this mutex over snapshot + dump sequences.
	326	*/
	327	struct mutex stats_mutex;
ec80bfcb	328
3ad50cca GR	329	/* This mutex serializes phy access for chips with
	330	* indirect phy addressing. It is unused for chips
	331	* with direct phy access.
	332	*/
	333	struct mutex phy_mutex;
	334
33b43df4 GR	335	/* This mutex serializes eeprom access for chips with
	336	* eeprom support.
	337	*/
	338	struct mutex eeprom_mutex;
	339
ec80bfcb	340	int id; /* switch product id */
d198893e	341	int num_ports; /* number of switch ports */
facd95b2 GR	342
	343	/* hw bridging */
	344
	345	u32 fid_mask;
	346	u8 fid[DSA_MAX_PORTS];
	347	u16 bridge_mask[DSA_MAX_PORTS];
	348
	349	unsigned long port_state_update_mask;
	350	u8 port_state[DSA_MAX_PORTS];
	351
	352	struct work_struct bridge_work;
87c8cefb AL	353
87c8cefb AL	354	struct dentry *dbgfs;
91da11f8 LB	355	};
	356
	357	struct mv88e6xxx_hw_stat {
	358	char string[ETH_GSTRING_LEN];
	359	int sizeof_stat;
	360	int reg;
	361	};
	362
143a8307	363	int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
dbde9e66	364	int mv88e6xxx_setup_ports(struct dsa_switch *ds);
acdaffcc	365	int mv88e6xxx_setup_common(struct dsa_switch *ds);
54d792f2	366	int mv88e6xxx_setup_global(struct dsa_switch *ds);
91da11f8 LB	367	int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
	368	int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
	369	int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
85686581	370	int reg, u16 val);
91da11f8	371	int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
2e5f0320	372	int mv88e6xxx_set_addr_direct(struct dsa_switch ds, u8 addr);
91da11f8	373	int mv88e6xxx_set_addr_indirect(struct dsa_switch ds, u8 addr);
fd3a0ee4 AL	374	int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
	375	int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
	376	int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
	377	int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
	378	u16 val);
2e5f0320 LB	379	void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
	380	int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
	381	int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
	382	int regnum, u16 val);
91da11f8	383	void mv88e6xxx_poll_link(struct dsa_switch *ds);
e413e7e1 AL	384	void mv88e6xxx_get_strings(struct dsa_switch ds, int port, uint8_t data);
	385	void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
	386	uint64_t *data);
	387	int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
	388	int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
a1ab91f3 GR	389	int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
	390	void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
	391	struct ethtool_regs regs, void _p);
eaa23765	392	int mv88e6xxx_get_temp(struct dsa_switch ds, int temp);
f3044683 AL	393	int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
	394	int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
	395	int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
	396	int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
	397	u16 val);
11b3b45d GR	398	int mv88e6xxx_get_eee(struct dsa_switch ds, int port, struct ethtool_eee e);
	399	int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
	400	struct phy_device phydev, struct ethtool_eee e);
facd95b2 GR	401	int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
	402	int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
	403	int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
defb05b9 GR	404	int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
	405	const unsigned char *addr, u16 vid);
	406	int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
	407	const unsigned char *addr, u16 vid);
	408	int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
	409	unsigned char addr, bool is_static);
49143585 AL	410	int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
	411	int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
	412	int reg, int val);
98e67308 BH	413	extern struct dsa_switch_driver mv88e6131_switch_driver;
98e67308 BH	414	extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
3ad50cca	415	extern struct dsa_switch_driver mv88e6352_switch_driver;
42f27253	416	extern struct dsa_switch_driver mv88e6171_switch_driver;
98e67308	417
91da11f8 LB	418	#define REG_READ(addr, reg) \
	419	({ \
	420	int __ret; \
	421	\
	422	__ret = mv88e6xxx_reg_read(ds, addr, reg); \
	423	if (__ret < 0) \
	424	return __ret; \
	425	__ret; \
	426	})
	427
	428	#define REG_WRITE(addr, reg, val) \
	429	({ \
	430	int __ret; \
	431	\
	432	__ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
	433	if (__ret < 0) \
	434	return __ret; \
	435	})
	436
	437
	438
	439	#endif