projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 91da11f8 LB |
1 | /* |
| 2 | * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support | |
| 3 | * Copyright (c) 2008 Marvell Semiconductor | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __MV88E6XXX_H | |
| 12 | #define __MV88E6XXX_H | |
| 13 | ||
| 194fea7b VD |
14 | #include <linux/if_vlan.h> |
| 15 | ||
| 80c4627b AL |
16 | #ifndef UINT64_MAX |
| 17 | #define UINT64_MAX (u64)(~((u64)0)) | |
| 18 | #endif | |
| 19 | ||
| cca8b133 AL |
20 | #define SMI_CMD 0x00 |
| 21 | #define SMI_CMD_BUSY BIT(15) | |
| 22 | #define SMI_CMD_CLAUSE_22 BIT(12) | |
| 23 | #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
| 24 | #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
| 25 | #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) | |
| 26 | #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) | |
| 27 | #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) | |
| 28 | #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) | |
| 29 | #define SMI_DATA 0x01 | |
| b2eb0662 | 30 | |
| 13a7ebb3 PU |
31 | /* Fiber/SERDES Registers are located at SMI address F, page 1 */ |
| 32 | #define REG_FIBER_SERDES 0x0f | |
| 33 | #define PAGE_FIBER_SERDES 0x01 | |
| 34 | ||
| 91da11f8 | 35 | #define REG_PORT(p) (0x10 + (p)) |
| cca8b133 AL |
36 | #define PORT_STATUS 0x00 |
| 37 | #define PORT_STATUS_PAUSE_EN BIT(15) | |
| 38 | #define PORT_STATUS_MY_PAUSE BIT(14) | |
| 39 | #define PORT_STATUS_HD_FLOW BIT(13) | |
| 40 | #define PORT_STATUS_PHY_DETECT BIT(12) | |
| 41 | #define PORT_STATUS_LINK BIT(11) | |
| 42 | #define PORT_STATUS_DUPLEX BIT(10) | |
| 43 | #define PORT_STATUS_SPEED_MASK 0x0300 | |
| 44 | #define PORT_STATUS_SPEED_10 0x0000 | |
| 45 | #define PORT_STATUS_SPEED_100 0x0100 | |
| 46 | #define PORT_STATUS_SPEED_1000 0x0200 | |
| 47 | #define PORT_STATUS_EEE BIT(6) /* 6352 */ | |
| 48 | #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ | |
| 49 | #define PORT_STATUS_MGMII BIT(6) /* 6185 */ | |
| 50 | #define PORT_STATUS_TX_PAUSED BIT(5) | |
| 51 | #define PORT_STATUS_FLOW_CTRL BIT(4) | |
| 13a7ebb3 PU |
52 | #define PORT_STATUS_CMODE_MASK 0x0f |
| 53 | #define PORT_STATUS_CMODE_100BASE_X 0x8 | |
| 54 | #define PORT_STATUS_CMODE_1000BASE_X 0x9 | |
| 55 | #define PORT_STATUS_CMODE_SGMII 0xa | |
| cca8b133 | 56 | #define PORT_PCS_CTRL 0x01 |
| e7e72ac0 AL |
57 | #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) |
| 58 | #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) | |
| 54d792f2 AL |
59 | #define PORT_PCS_CTRL_FC BIT(7) |
| 60 | #define PORT_PCS_CTRL_FORCE_FC BIT(6) | |
| 61 | #define PORT_PCS_CTRL_LINK_UP BIT(5) | |
| 62 | #define PORT_PCS_CTRL_FORCE_LINK BIT(4) | |
| 63 | #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) | |
| 64 | #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) | |
| 65 | #define PORT_PCS_CTRL_10 0x00 | |
| 66 | #define PORT_PCS_CTRL_100 0x01 | |
| 67 | #define PORT_PCS_CTRL_1000 0x02 | |
| 68 | #define PORT_PCS_CTRL_UNFORCED 0x03 | |
| 69 | #define PORT_PAUSE_CTRL 0x02 | |
| cca8b133 | 70 | #define PORT_SWITCH_ID 0x03 |
| f6271e67 VD |
71 | #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a |
| 72 | #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 | |
| 73 | #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 | |
| 74 | #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 | |
| 75 | #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 | |
| 76 | #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 | |
| 77 | #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 | |
| 78 | #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 | |
| 79 | #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 | |
| 80 | #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 | |
| 81 | #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 | |
| 82 | #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 | |
| 83 | #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 | |
| 84 | #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 | |
| 85 | #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 | |
| 86 | #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 | |
| 87 | #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 | |
| cca8b133 | 88 | #define PORT_CONTROL 0x04 |
| 54d792f2 AL |
89 | #define PORT_CONTROL_USE_CORE_TAG BIT(15) |
| 90 | #define PORT_CONTROL_DROP_ON_LOCK BIT(14) | |
| 91 | #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) | |
| 92 | #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) | |
| 93 | #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) | |
| 94 | #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) | |
| 95 | #define PORT_CONTROL_HEADER BIT(11) | |
| 96 | #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) | |
| 97 | #define PORT_CONTROL_DOUBLE_TAG BIT(9) | |
| 98 | #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) | |
| 99 | #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) | |
| 100 | #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) | |
| 101 | #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) | |
| 102 | #define PORT_CONTROL_DSA_TAG BIT(8) | |
| 103 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) | |
| 104 | #define PORT_CONTROL_TAG_IF_BOTH BIT(6) | |
| 105 | #define PORT_CONTROL_USE_IP BIT(5) | |
| 106 | #define PORT_CONTROL_USE_TAG BIT(4) | |
| 107 | #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) | |
| 108 | #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) | |
| cca8b133 AL |
109 | #define PORT_CONTROL_STATE_MASK 0x03 |
| 110 | #define PORT_CONTROL_STATE_DISABLED 0x00 | |
| 111 | #define PORT_CONTROL_STATE_BLOCKING 0x01 | |
| 112 | #define PORT_CONTROL_STATE_LEARNING 0x02 | |
| 113 | #define PORT_CONTROL_STATE_FORWARDING 0x03 | |
| 114 | #define PORT_CONTROL_1 0x05 | |
| 2db9ce1f | 115 | #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) |
| cca8b133 | 116 | #define PORT_BASE_VLAN 0x06 |
| 2db9ce1f | 117 | #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) |
| cca8b133 | 118 | #define PORT_DEFAULT_VLAN 0x07 |
| b8fee957 | 119 | #define PORT_DEFAULT_VLAN_MASK 0xfff |
| cca8b133 | 120 | #define PORT_CONTROL_2 0x08 |
| 54d792f2 AL |
121 | #define PORT_CONTROL_2_IGNORE_FCS BIT(15) |
| 122 | #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) | |
| 123 | #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) | |
| 124 | #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) | |
| 125 | #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) | |
| 126 | #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) | |
| 127 | #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) | |
| 8efdda4a VD |
128 | #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) |
| 129 | #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) | |
| 130 | #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) | |
| 131 | #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) | |
| 132 | #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) | |
| 54d792f2 AL |
133 | #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) |
| 134 | #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) | |
| 135 | #define PORT_CONTROL_2_MAP_DA BIT(7) | |
| 136 | #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) | |
| 137 | #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) | |
| 138 | #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) | |
| 139 | #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) | |
| cca8b133 AL |
140 | #define PORT_RATE_CONTROL 0x09 |
| 141 | #define PORT_RATE_CONTROL_2 0x0a | |
| 142 | #define PORT_ASSOC_VECTOR 0x0b | |
| 4c7ea3c0 AL |
143 | #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) |
| 144 | #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) | |
| 145 | #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) | |
| 146 | #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) | |
| 147 | #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) | |
| 54d792f2 AL |
148 | #define PORT_ATU_CONTROL 0x0c |
| 149 | #define PORT_PRI_OVERRIDE 0x0d | |
| 150 | #define PORT_ETH_TYPE 0x0f | |
| cca8b133 AL |
151 | #define PORT_IN_DISCARD_LO 0x10 |
| 152 | #define PORT_IN_DISCARD_HI 0x11 | |
| 153 | #define PORT_IN_FILTERED 0x12 | |
| 154 | #define PORT_OUT_FILTERED 0x13 | |
| 54d792f2 AL |
155 | #define PORT_TAG_REGMAP_0123 0x18 |
| 156 | #define PORT_TAG_REGMAP_4567 0x19 | |
| facd95b2 | 157 | |
| cca8b133 AL |
158 | #define REG_GLOBAL 0x1b |
| 159 | #define GLOBAL_STATUS 0x00 | |
| 160 | #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ | |
| 161 | /* Two bits for 6165, 6185 etc */ | |
| 162 | #define GLOBAL_STATUS_PPU_MASK (0x3 << 14) | |
| 163 | #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) | |
| 164 | #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) | |
| 165 | #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) | |
| 166 | #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) | |
| 167 | #define GLOBAL_MAC_01 0x01 | |
| 168 | #define GLOBAL_MAC_23 0x02 | |
| 169 | #define GLOBAL_MAC_45 0x03 | |
| a08df0f0 | 170 | #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */ |
| b8fee957 VD |
171 | #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */ |
| 172 | #define GLOBAL_VTU_FID_MASK 0xfff | |
| 173 | #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ | |
| 174 | #define GLOBAL_VTU_SID_MASK 0x3f | |
| cca8b133 AL |
175 | #define GLOBAL_CONTROL 0x04 |
| 176 | #define GLOBAL_CONTROL_SW_RESET BIT(15) | |
| 177 | #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) | |
| 178 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ | |
| 179 | #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ | |
| 180 | #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ | |
| 54d792f2 | 181 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
| cca8b133 AL |
182 | #define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
| 183 | #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) | |
| 184 | #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) | |
| 185 | #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) | |
| 186 | #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) | |
| 187 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) | |
| 188 | #define GLOBAL_CONTROL_TCAM_EN BIT(1) | |
| 189 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) | |
| 190 | #define GLOBAL_VTU_OP 0x05 | |
| 6b17e864 VD |
191 | #define GLOBAL_VTU_OP_BUSY BIT(15) |
| 192 | #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) | |
| 7dad08d7 | 193 | #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
| b8fee957 | 194 | #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
| 0d3b33e6 VD |
195 | #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
| 196 | #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) | |
| cca8b133 | 197 | #define GLOBAL_VTU_VID 0x06 |
| b8fee957 VD |
198 | #define GLOBAL_VTU_VID_MASK 0xfff |
| 199 | #define GLOBAL_VTU_VID_VALID BIT(12) | |
| cca8b133 AL |
200 | #define GLOBAL_VTU_DATA_0_3 0x07 |
| 201 | #define GLOBAL_VTU_DATA_4_7 0x08 | |
| 202 | #define GLOBAL_VTU_DATA_8_11 0x09 | |
| b8fee957 VD |
203 | #define GLOBAL_VTU_STU_DATA_MASK 0x03 |
| 204 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 | |
| 205 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 | |
| 206 | #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 | |
| 207 | #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 | |
| 0d3b33e6 VD |
208 | #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
| 209 | #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 | |
| 210 | #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 | |
| 211 | #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 | |
| cca8b133 | 212 | #define GLOBAL_ATU_CONTROL 0x0a |
| 54d792f2 | 213 | #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
| cca8b133 AL |
214 | #define GLOBAL_ATU_OP 0x0b |
| 215 | #define GLOBAL_ATU_OP_BUSY BIT(15) | |
| 216 | #define GLOBAL_ATU_OP_NOP (0 << 12) | |
| 7fb5e755 VD |
217 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
| 218 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) | |
| cca8b133 AL |
219 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
| 220 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) | |
| 7fb5e755 VD |
221 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
| 222 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) | |
| cca8b133 AL |
223 | #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
| 224 | #define GLOBAL_ATU_DATA 0x0c | |
| 8a0a265d | 225 | #define GLOBAL_ATU_DATA_TRUNK BIT(15) |
| fd231c82 VD |
226 | #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
| 227 | #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 | |
| 8a0a265d AL |
228 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
| 229 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 | |
| cca8b133 AL |
230 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
| 231 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 | |
| 232 | #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d | |
| 233 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e | |
| 234 | #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f | |
| 235 | #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 | |
| 236 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 | |
| 237 | #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e | |
| 238 | #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f | |
| 239 | #define GLOBAL_ATU_MAC_01 0x0d | |
| 240 | #define GLOBAL_ATU_MAC_23 0x0e | |
| 241 | #define GLOBAL_ATU_MAC_45 0x0f | |
| 242 | #define GLOBAL_IP_PRI_0 0x10 | |
| 243 | #define GLOBAL_IP_PRI_1 0x11 | |
| 244 | #define GLOBAL_IP_PRI_2 0x12 | |
| 245 | #define GLOBAL_IP_PRI_3 0x13 | |
| 246 | #define GLOBAL_IP_PRI_4 0x14 | |
| 247 | #define GLOBAL_IP_PRI_5 0x15 | |
| 248 | #define GLOBAL_IP_PRI_6 0x16 | |
| 249 | #define GLOBAL_IP_PRI_7 0x17 | |
| 250 | #define GLOBAL_IEEE_PRI 0x18 | |
| 251 | #define GLOBAL_CORE_TAG_TYPE 0x19 | |
| 252 | #define GLOBAL_MONITOR_CONTROL 0x1a | |
| 15966a2a AL |
253 | #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
| 254 | #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 | |
| 255 | #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 | |
| 256 | #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 | |
| 257 | #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) | |
| cca8b133 | 258 | #define GLOBAL_CONTROL_2 0x1c |
| 15966a2a AL |
259 | #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
| 260 | #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 | |
| 261 | ||
| cca8b133 AL |
262 | #define GLOBAL_STATS_OP 0x1d |
| 263 | #define GLOBAL_STATS_OP_BUSY BIT(15) | |
| 264 | #define GLOBAL_STATS_OP_NOP (0 << 12) | |
| 265 | #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 266 | #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 267 | #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 268 | #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) | |
| 269 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) | |
| 270 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) | |
| 271 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) | |
| f5e2ed02 | 272 | #define GLOBAL_STATS_OP_BANK_1 BIT(9) |
| cca8b133 AL |
273 | #define GLOBAL_STATS_COUNTER_32 0x1e |
| 274 | #define GLOBAL_STATS_COUNTER_01 0x1f | |
| defb05b9 | 275 | |
| cca8b133 AL |
276 | #define REG_GLOBAL2 0x1c |
| 277 | #define GLOBAL2_INT_SOURCE 0x00 | |
| 278 | #define GLOBAL2_INT_MASK 0x01 | |
| 279 | #define GLOBAL2_MGMT_EN_2X 0x02 | |
| 280 | #define GLOBAL2_MGMT_EN_0X 0x03 | |
| 281 | #define GLOBAL2_FLOW_CONTROL 0x04 | |
| 282 | #define GLOBAL2_SWITCH_MGMT 0x05 | |
| 54d792f2 AL |
283 | #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) |
| 284 | #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) | |
| 285 | #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) | |
| 286 | #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) | |
| 287 | #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) | |
| cca8b133 | 288 | #define GLOBAL2_DEVICE_MAPPING 0x06 |
| 54d792f2 AL |
289 | #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) |
| 290 | #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 | |
| d35bd876 | 291 | #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f |
| cca8b133 | 292 | #define GLOBAL2_TRUNK_MASK 0x07 |
| 54d792f2 AL |
293 | #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) |
| 294 | #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 | |
| cca8b133 | 295 | #define GLOBAL2_TRUNK_MAPPING 0x08 |
| 54d792f2 AL |
296 | #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) |
| 297 | #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 | |
| cca8b133 AL |
298 | #define GLOBAL2_INGRESS_OP 0x09 |
| 299 | #define GLOBAL2_INGRESS_DATA 0x0a | |
| 300 | #define GLOBAL2_PVT_ADDR 0x0b | |
| 301 | #define GLOBAL2_PVT_DATA 0x0c | |
| 302 | #define GLOBAL2_SWITCH_MAC 0x0d | |
| 303 | #define GLOBAL2_SWITCH_MAC_BUSY BIT(15) | |
| 304 | #define GLOBAL2_ATU_STATS 0x0e | |
| 305 | #define GLOBAL2_PRIO_OVERRIDE 0x0f | |
| 15966a2a AL |
306 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) |
| 307 | #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 | |
| 308 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) | |
| 309 | #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 | |
| cca8b133 | 310 | #define GLOBAL2_EEPROM_OP 0x14 |
| 966bce38 AL |
311 | #define GLOBAL2_EEPROM_OP_BUSY BIT(15) |
| 312 | #define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY) | |
| 313 | #define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY) | |
| 314 | #define GLOBAL2_EEPROM_OP_LOAD BIT(11) | |
| 315 | #define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10) | |
| 316 | #define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff | |
| cca8b133 AL |
317 | #define GLOBAL2_EEPROM_DATA 0x15 |
| 318 | #define GLOBAL2_PTP_AVB_OP 0x16 | |
| 319 | #define GLOBAL2_PTP_AVB_DATA 0x17 | |
| 320 | #define GLOBAL2_SMI_OP 0x18 | |
| 321 | #define GLOBAL2_SMI_OP_BUSY BIT(15) | |
| 322 | #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) | |
| 323 | #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
| 324 | GLOBAL2_SMI_OP_CLAUSE_22) | |
| 325 | #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
| 326 | GLOBAL2_SMI_OP_CLAUSE_22) | |
| 327 | #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 328 | #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 329 | #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) | |
| 330 | #define GLOBAL2_SMI_DATA 0x19 | |
| 331 | #define GLOBAL2_SCRATCH_MISC 0x1a | |
| 56d95e22 AL |
332 | #define GLOBAL2_SCRATCH_BUSY BIT(15) |
| 333 | #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 | |
| 334 | #define GLOBAL2_SCRATCH_VALUE_MASK 0xff | |
| cca8b133 AL |
335 | #define GLOBAL2_WDOG_CONTROL 0x1b |
| 336 | #define GLOBAL2_QOS_WEIGHT 0x1c | |
| 337 | #define GLOBAL2_MISC 0x1d | |
| defb05b9 | 338 | |
| 3285f9e8 VD |
339 | #define MV88E6XXX_N_FID 4096 |
| 340 | ||
| 22356476 VD |
341 | enum mv88e6xxx_family { |
| 342 | MV88E6XXX_FAMILY_NONE, | |
| 343 | MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ | |
| 344 | MV88E6XXX_FAMILY_6095, /* 6092 6095 */ | |
| 345 | MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ | |
| 346 | MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ | |
| 347 | MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ | |
| 348 | MV88E6XXX_FAMILY_6320, /* 6320 6321 */ | |
| 349 | MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ | |
| 350 | MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ | |
| 351 | }; | |
| 352 | ||
| b5058d7a VD |
353 | #define MV88E6XXX_FLAGS_FAMILY_6095 0 |
| 354 | ||
| 355 | #define MV88E6XXX_FLAGS_FAMILY_6097 0 | |
| 356 | ||
| 357 | #define MV88E6XXX_FLAGS_FAMILY_6165 0 | |
| 358 | ||
| 359 | #define MV88E6XXX_FLAGS_FAMILY_6185 0 | |
| 360 | ||
| 361 | #define MV88E6XXX_FLAGS_FAMILY_6320 0 | |
| 362 | ||
| 363 | #define MV88E6XXX_FLAGS_FAMILY_6351 0 | |
| 364 | ||
| 365 | #define MV88E6XXX_FLAGS_FAMILY_6352 0 | |
| 366 | ||
| f6271e67 | 367 | struct mv88e6xxx_info { |
| 22356476 | 368 | enum mv88e6xxx_family family; |
| f6271e67 VD |
369 | u16 prod_num; |
| 370 | const char *name; | |
| cd5a2c82 | 371 | unsigned int num_databases; |
| 009a2b98 | 372 | unsigned int num_ports; |
| b5058d7a | 373 | unsigned long flags; |
| b9b37713 VD |
374 | }; |
| 375 | ||
| fd231c82 VD |
376 | struct mv88e6xxx_atu_entry { |
| 377 | u16 fid; | |
| 378 | u8 state; | |
| 379 | bool trunk; | |
| 380 | u16 portv_trunkid; | |
| 381 | u8 mac[ETH_ALEN]; | |
| 382 | }; | |
| 383 | ||
| b8fee957 VD |
384 | struct mv88e6xxx_vtu_stu_entry { |
| 385 | /* VTU only */ | |
| 386 | u16 vid; | |
| 387 | u16 fid; | |
| 388 | ||
| 389 | /* VTU and STU */ | |
| 390 | u8 sid; | |
| 391 | bool valid; | |
| 392 | u8 data[DSA_MAX_PORTS]; | |
| 393 | }; | |
| 394 | ||
| d715fa64 | 395 | struct mv88e6xxx_priv_port { |
| a6692754 | 396 | struct net_device *bridge_dev; |
| d715fa64 VD |
397 | u8 state; |
| 398 | }; | |
| 399 | ||
| 91da11f8 | 400 | struct mv88e6xxx_priv_state { |
| f6271e67 VD |
401 | const struct mv88e6xxx_info *info; |
| 402 | ||
| 7543a6d5 AL |
403 | /* The dsa_switch this private structure is related to */ |
| 404 | struct dsa_switch *ds; | |
| 405 | ||
| 158bc065 AL |
406 | /* The device this structure is associated to */ |
| 407 | struct device *dev; | |
| 408 | ||
| 3675c8d7 | 409 | /* When using multi-chip addressing, this mutex protects |
| 91da11f8 LB |
410 | * access to the indirect access registers. (In single-chip |
| 411 | * mode, this mutex is effectively useless.) | |
| 412 | */ | |
| 413 | struct mutex smi_mutex; | |
| 414 | ||
| a77d43f1 AL |
415 | /* The MII bus and the address on the bus that is used to |
| 416 | * communication with the switch | |
| 417 | */ | |
| 418 | struct mii_bus *bus; | |
| 419 | int sw_addr; | |
| 420 | ||
| 2e5f0320 | 421 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
| 3675c8d7 | 422 | /* Handles automatic disabling and re-enabling of the PHY |
| 2e5f0320 LB |
423 | * polling unit. |
| 424 | */ | |
| 425 | struct mutex ppu_mutex; | |
| 426 | int ppu_disabled; | |
| 427 | struct work_struct ppu_work; | |
| 428 | struct timer_list ppu_timer; | |
| 429 | #endif | |
| 430 | ||
| 3675c8d7 | 431 | /* This mutex serialises access to the statistics unit. |
| 91da11f8 LB |
432 | * Hold this mutex over snapshot + dump sequences. |
| 433 | */ | |
| 434 | struct mutex stats_mutex; | |
| ec80bfcb | 435 | |
| 3ad50cca GR |
436 | /* This mutex serializes phy access for chips with |
| 437 | * indirect phy addressing. It is unused for chips | |
| 438 | * with direct phy access. | |
| 439 | */ | |
| 440 | struct mutex phy_mutex; | |
| 441 | ||
| 33b43df4 GR |
442 | /* This mutex serializes eeprom access for chips with |
| 443 | * eeprom support. | |
| 444 | */ | |
| 445 | struct mutex eeprom_mutex; | |
| 446 | ||
| d715fa64 VD |
447 | struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS]; |
| 448 | ||
| 2d9deae4 | 449 | DECLARE_BITMAP(port_state_update_mask, DSA_MAX_PORTS); |
| facd95b2 GR |
450 | |
| 451 | struct work_struct bridge_work; | |
| 91da11f8 LB |
452 | }; |
| 453 | ||
| f5e2ed02 AL |
454 | enum stat_type { |
| 455 | BANK0, | |
| 456 | BANK1, | |
| 457 | PORT, | |
| 458 | }; | |
| 459 | ||
| 91da11f8 LB |
460 | struct mv88e6xxx_hw_stat { |
| 461 | char string[ETH_GSTRING_LEN]; | |
| 462 | int sizeof_stat; | |
| 463 | int reg; | |
| f5e2ed02 | 464 | enum stat_type type; |
| 91da11f8 LB |
465 | }; |
| 466 | ||
| b5058d7a VD |
467 | static inline bool mv88e6xxx_has(struct mv88e6xxx_priv_state *ps, |
| 468 | unsigned long flags) | |
| 469 | { | |
| 470 | return (ps->info->flags & flags) == flags; | |
| 471 | } | |
| 472 | ||
| 158bc065 | 473 | int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps, bool ppu_active); |
| 0209d144 VD |
474 | const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev, |
| 475 | int sw_addr, void **priv, | |
| f6271e67 | 476 | const struct mv88e6xxx_info *table, |
| 0209d144 | 477 | unsigned int num); |
| a77d43f1 | 478 | |
| dbde9e66 | 479 | int mv88e6xxx_setup_ports(struct dsa_switch *ds); |
| 158bc065 | 480 | int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps); |
| 54d792f2 | 481 | int mv88e6xxx_setup_global(struct dsa_switch *ds); |
| 158bc065 AL |
482 | int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg); |
| 483 | int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, | |
| 484 | int reg, u16 val); | |
| 2e5f0320 | 485 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr); |
| 91da11f8 | 486 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr); |
| fd3a0ee4 AL |
487 | int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum); |
| 488 | int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val); | |
| 489 | int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum); | |
| 490 | int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
| 491 | u16 val); | |
| 158bc065 | 492 | void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps); |
| 2e5f0320 LB |
493 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum); |
| 494 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
| 495 | int regnum, u16 val); | |
| e413e7e1 AL |
496 | void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data); |
| 497 | void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, | |
| 498 | uint64_t *data); | |
| 499 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds); | |
| 500 | int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds); | |
| dea87024 AL |
501 | void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
| 502 | struct phy_device *phydev); | |
| a1ab91f3 GR |
503 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port); |
| 504 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
| 505 | struct ethtool_regs *regs, void *_p); | |
| c22995c5 GR |
506 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp); |
| 507 | int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp); | |
| 508 | int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp); | |
| 509 | int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm); | |
| f3044683 AL |
510 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds); |
| 511 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds); | |
| 512 | int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum); | |
| 513 | int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum, | |
| 514 | u16 val); | |
| 11b3b45d GR |
515 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e); |
| 516 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
| 517 | struct phy_device *phydev, struct ethtool_eee *e); | |
| a6692754 VD |
518 | int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
| 519 | struct net_device *bridge); | |
| 16bfa702 | 520 | void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port); |
| 43c44a9f | 521 | void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); |
| 214cdb99 VD |
522 | int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
| 523 | bool vlan_filtering); | |
| 76e398a6 VD |
524 | int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
| 525 | const struct switchdev_obj_port_vlan *vlan, | |
| 526 | struct switchdev_trans *trans); | |
| 4d5770b3 VD |
527 | void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
| 528 | const struct switchdev_obj_port_vlan *vlan, | |
| 529 | struct switchdev_trans *trans); | |
| 76e398a6 VD |
530 | int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
| 531 | const struct switchdev_obj_port_vlan *vlan); | |
| ceff5eff VD |
532 | int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
| 533 | struct switchdev_obj_port_vlan *vlan, | |
| 534 | int (*cb)(struct switchdev_obj *obj)); | |
| 146a3206 VD |
535 | int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
| 536 | const struct switchdev_obj_port_fdb *fdb, | |
| 537 | struct switchdev_trans *trans); | |
| 8497aa61 VD |
538 | void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
| 539 | const struct switchdev_obj_port_fdb *fdb, | |
| 540 | struct switchdev_trans *trans); | |
| cdf09697 | 541 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
| 8057b3e7 | 542 | const struct switchdev_obj_port_fdb *fdb); |
| f33475bd VD |
543 | int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
| 544 | struct switchdev_obj_port_fdb *fdb, | |
| 545 | int (*cb)(struct switchdev_obj *obj)); | |
| 49143585 AL |
546 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg); |
| 547 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
| 548 | int reg, int val); | |
| c22995c5 | 549 | |
| 98e67308 | 550 | extern struct dsa_switch_driver mv88e6131_switch_driver; |
| ca3dfa51 | 551 | extern struct dsa_switch_driver mv88e6123_switch_driver; |
| 3ad50cca | 552 | extern struct dsa_switch_driver mv88e6352_switch_driver; |
| 42f27253 | 553 | extern struct dsa_switch_driver mv88e6171_switch_driver; |
| 98e67308 | 554 | |
| 91da11f8 | 555 | #endif |