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jme: Advance driver version number
[deliverable/linux.git] / drivers / net / e1000 / e1000_ethtool.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for e1000 */
30
31#include "e1000.h"
1da177e4
LT		 32#include <asm/uaccess.h>
33
1da177e4
LT		 34struct e1000_stats {
35 char stat_string[ETH_GSTRING_LEN];
36 int sizeof_stat;
37 int stat_offset;
38};
39
030ed68b 40#define E1000_STAT(m) FIELD_SIZEOF(struct e1000_adapter, m), \
1da177e4
LT		 41 offsetof(struct e1000_adapter, m)
42static const struct e1000_stats e1000_gstrings_stats[] = {
49559854
MW		 43 { "rx_packets", E1000_STAT(stats.gprc) },
44 { "tx_packets", E1000_STAT(stats.gptc) },
45 { "rx_bytes", E1000_STAT(stats.gorcl) },
46 { "tx_bytes", E1000_STAT(stats.gotcl) },
47 { "rx_broadcast", E1000_STAT(stats.bprc) },
48 { "tx_broadcast", E1000_STAT(stats.bptc) },
49 { "rx_multicast", E1000_STAT(stats.mprc) },
50 { "tx_multicast", E1000_STAT(stats.mptc) },
51 { "rx_errors", E1000_STAT(stats.rxerrc) },
52 { "tx_errors", E1000_STAT(stats.txerrc) },
1da177e4 53 { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
49559854
MW		 54 { "multicast", E1000_STAT(stats.mprc) },
55 { "collisions", E1000_STAT(stats.colc) },
56 { "rx_length_errors", E1000_STAT(stats.rlerrc) },
1da177e4 57 { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
49559854 58 { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
1da177e4 59 { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
2648345f 60 { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
49559854
MW		 61 { "rx_missed_errors", E1000_STAT(stats.mpc) },
62 { "tx_aborted_errors", E1000_STAT(stats.ecol) },
63 { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
1da177e4
LT		 64 { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
65 { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
49559854 66 { "tx_window_errors", E1000_STAT(stats.latecol) },
1da177e4
LT		 67 { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
68 { "tx_deferred_ok", E1000_STAT(stats.dc) },
69 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
70 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
6b7660cd 71 { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
fcfb1224 72 { "tx_restart_queue", E1000_STAT(restart_queue) },
1da177e4
LT		 73 { "rx_long_length_errors", E1000_STAT(stats.roc) },
74 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
75 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
76 { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
77 { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
78 { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
79 { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
80 { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
81 { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
82 { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
83 { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
e4c811c9
MC		 84 { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
85 { "rx_header_split", E1000_STAT(rx_hdr_split) },
6b7660cd 86 { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
15e376b4
JG		 87 { "tx_smbus", E1000_STAT(stats.mgptc) },
88 { "rx_smbus", E1000_STAT(stats.mgprc) },
89 { "dropped_smbus", E1000_STAT(stats.mgpdc) },
1da177e4 90};
7bfa4816 91
7bfa4816 92#define E1000_QUEUE_STATS_LEN 0
ff8ac609 93#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats)
7bfa4816 94#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN + E1000_QUEUE_STATS_LEN)
1da177e4
LT		 95static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
96 "Register test (offline)", "Eeprom test (offline)",
97 "Interrupt test (offline)", "Loopback test (offline)",
98 "Link test (on/offline)"
99};
4c3616cd 100#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
1da177e4 101
64798845
JP		 102static int e1000_get_settings(struct net_device *netdev,
103 struct ethtool_cmd *ecmd)
1da177e4 104{
60490fe0 105 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 106 struct e1000_hw *hw = &adapter->hw;
107
96838a40 108 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 109
110 ecmd->supported = (SUPPORTED_10baseT_Half |
111 SUPPORTED_10baseT_Full |
112 SUPPORTED_100baseT_Half |
113 SUPPORTED_100baseT_Full |
114 SUPPORTED_1000baseT_Full|
115 SUPPORTED_Autoneg |
116 SUPPORTED_TP);
cd94dd0b
AK		 117 if (hw->phy_type == e1000_phy_ife)
118 ecmd->supported &= ~SUPPORTED_1000baseT_Full;
1da177e4
LT		 119 ecmd->advertising = ADVERTISED_TP;
120
96838a40 121 if (hw->autoneg == 1) {
1da177e4 122 ecmd->advertising |= ADVERTISED_Autoneg;
1da177e4 123 /* the e1000 autoneg seems to match ethtool nicely */
1da177e4
LT		 124 ecmd->advertising |= hw->autoneg_advertised;
125 }
126
127 ecmd->port = PORT_TP;
128 ecmd->phy_address = hw->phy_addr;
129
96838a40 130 if (hw->mac_type == e1000_82543)
1da177e4
LT		 131 ecmd->transceiver = XCVR_EXTERNAL;
132 else
133 ecmd->transceiver = XCVR_INTERNAL;
134
135 } else {
136 ecmd->supported = (SUPPORTED_1000baseT_Full |
137 SUPPORTED_FIBRE |
138 SUPPORTED_Autoneg);
139
012609a8
MC		 140 ecmd->advertising = (ADVERTISED_1000baseT_Full |
141 ADVERTISED_FIBRE |
142 ADVERTISED_Autoneg);
1da177e4
LT		 143
144 ecmd->port = PORT_FIBRE;
145
96838a40 146 if (hw->mac_type >= e1000_82545)
1da177e4
LT		 147 ecmd->transceiver = XCVR_INTERNAL;
148 else
149 ecmd->transceiver = XCVR_EXTERNAL;
150 }
151
1dc32918 152 if (er32(STATUS) & E1000_STATUS_LU) {
1da177e4
LT		 153
154 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
155 &adapter->link_duplex);
156 ecmd->speed = adapter->link_speed;
157
158 /* unfortunatly FULL_DUPLEX != DUPLEX_FULL
159 * and HALF_DUPLEX != DUPLEX_HALF */
160
96838a40 161 if (adapter->link_duplex == FULL_DUPLEX)
1da177e4
LT		 162 ecmd->duplex = DUPLEX_FULL;
163 else
164 ecmd->duplex = DUPLEX_HALF;
165 } else {
166 ecmd->speed = -1;
167 ecmd->duplex = -1;
168 }
169
170 ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) ||
171 hw->autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
172 return 0;
173}
174
64798845
JP		 175static int e1000_set_settings(struct net_device *netdev,
176 struct ethtool_cmd *ecmd)
1da177e4 177{
60490fe0 178 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 179 struct e1000_hw *hw = &adapter->hw;
180
57128197
JK		 181 /* When SoL/IDER sessions are active, autoneg/speed/duplex
182 * cannot be changed */
183 if (e1000_check_phy_reset_block(hw)) {
184 DPRINTK(DRV, ERR, "Cannot change link characteristics "
185 "when SoL/IDER is active.\n");
186 return -EINVAL;
187 }
188
1a821ca5
JB		 189 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
190 msleep(1);
191
57128197 192 if (ecmd->autoneg == AUTONEG_ENABLE) {
1da177e4 193 hw->autoneg = 1;
96838a40 194 if (hw->media_type == e1000_media_type_fiber)
012609a8
MC		 195 hw->autoneg_advertised = ADVERTISED_1000baseT_Full |
196 ADVERTISED_FIBRE |
197 ADVERTISED_Autoneg;
96838a40 198 else
2f2ca263
JK		 199 hw->autoneg_advertised = ecmd->advertising |
200 ADVERTISED_TP |
201 ADVERTISED_Autoneg;
012609a8 202 ecmd->advertising = hw->autoneg_advertised;
1da177e4 203 } else
1a821ca5
JB		 204 if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
205 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4 206 return -EINVAL;
1a821ca5 207 }
1da177e4
LT		 208
209 /* reset the link */
210
1a821ca5
JB		 211 if (netif_running(adapter->netdev)) {
212 e1000_down(adapter);
213 e1000_up(adapter);
214 } else
1da177e4
LT		 215 e1000_reset(adapter);
216
1a821ca5 217 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 218 return 0;
219}
220
64798845
JP		 221static void e1000_get_pauseparam(struct net_device *netdev,
222 struct ethtool_pauseparam *pause)
1da177e4 223{
60490fe0 224 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 225 struct e1000_hw *hw = &adapter->hw;
226
96838a40 227 pause->autoneg =
1da177e4 228 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
96838a40 229
11241b10 230 if (hw->fc == E1000_FC_RX_PAUSE)
1da177e4 231 pause->rx_pause = 1;
11241b10 232 else if (hw->fc == E1000_FC_TX_PAUSE)
1da177e4 233 pause->tx_pause = 1;
11241b10 234 else if (hw->fc == E1000_FC_FULL) {
1da177e4
LT		 235 pause->rx_pause = 1;
236 pause->tx_pause = 1;
237 }
238}
239
64798845
JP		 240static int e1000_set_pauseparam(struct net_device *netdev,
241 struct ethtool_pauseparam *pause)
1da177e4 242{
60490fe0 243 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 244 struct e1000_hw *hw = &adapter->hw;
1a821ca5 245 int retval = 0;
96838a40 246
1da177e4
LT		 247 adapter->fc_autoneg = pause->autoneg;
248
1a821ca5
JB		 249 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
250 msleep(1);
251
96838a40 252 if (pause->rx_pause && pause->tx_pause)
11241b10 253 hw->fc = E1000_FC_FULL;
96838a40 254 else if (pause->rx_pause && !pause->tx_pause)
11241b10 255 hw->fc = E1000_FC_RX_PAUSE;
96838a40 256 else if (!pause->rx_pause && pause->tx_pause)
11241b10 257 hw->fc = E1000_FC_TX_PAUSE;
96838a40 258 else if (!pause->rx_pause && !pause->tx_pause)
11241b10 259 hw->fc = E1000_FC_NONE;
1da177e4
LT		 260
261 hw->original_fc = hw->fc;
262
96838a40 263 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
1a821ca5
JB		 264 if (netif_running(adapter->netdev)) {
265 e1000_down(adapter);
266 e1000_up(adapter);
267 } else
1da177e4 268 e1000_reset(adapter);
96838a40 269 } else
1a821ca5 270 retval = ((hw->media_type == e1000_media_type_fiber) ?
90fb5135 271 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
96838a40 272
1a821ca5
JB		 273 clear_bit(__E1000_RESETTING, &adapter->flags);
274 return retval;
1da177e4
LT		 275}
276
64798845 277static u32 e1000_get_rx_csum(struct net_device *netdev)
1da177e4 278{
60490fe0 279 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 280 return adapter->rx_csum;
281}
282
64798845 283static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
1da177e4 284{
60490fe0 285 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 286 adapter->rx_csum = data;
287
2db10a08
AK		 288 if (netif_running(netdev))
289 e1000_reinit_locked(adapter);
290 else
1da177e4
LT		 291 e1000_reset(adapter);
292 return 0;
293}
96838a40 294
64798845 295static u32 e1000_get_tx_csum(struct net_device *netdev)
1da177e4
LT		 296{
297 return (netdev->features & NETIF_F_HW_CSUM) != 0;
298}
299
64798845 300static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
1da177e4 301{
60490fe0 302 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 303 struct e1000_hw *hw = &adapter->hw;
1da177e4 304
1dc32918 305 if (hw->mac_type < e1000_82543) {
1da177e4
LT		 306 if (!data)
307 return -EINVAL;
308 return 0;
309 }
310
311 if (data)
312 netdev->features |= NETIF_F_HW_CSUM;
313 else
314 netdev->features &= ~NETIF_F_HW_CSUM;
315
316 return 0;
317}
318
64798845 319static int e1000_set_tso(struct net_device *netdev, u32 data)
1da177e4 320{
60490fe0 321 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918
JP		 322 struct e1000_hw *hw = &adapter->hw;
323
324 if ((hw->mac_type < e1000_82544) ||
325 (hw->mac_type == e1000_82547))
1da177e4
LT		 326 return data ? -EINVAL : 0;
327
328 if (data)
329 netdev->features |= NETIF_F_TSO;
330 else
331 netdev->features &= ~NETIF_F_TSO;
7e6c9861 332
581abbc2 333 if (data && (adapter->hw.mac_type > e1000_82547_rev_2))
87ca4e5b
AK		 334 netdev->features |= NETIF_F_TSO6;
335 else
336 netdev->features &= ~NETIF_F_TSO6;
87ca4e5b 337
7e6c9861 338 DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled");
c3033b01 339 adapter->tso_force = true;
1da177e4 340 return 0;
96838a40 341}
1da177e4 342
64798845 343static u32 e1000_get_msglevel(struct net_device *netdev)
1da177e4 344{
60490fe0 345 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 346 return adapter->msg_enable;
347}
348
64798845 349static void e1000_set_msglevel(struct net_device *netdev, u32 data)
1da177e4 350{
60490fe0 351 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 352 adapter->msg_enable = data;
353}
354
64798845 355static int e1000_get_regs_len(struct net_device *netdev)
1da177e4
LT		 356{
357#define E1000_REGS_LEN 32
406874a7 358 return E1000_REGS_LEN * sizeof(u32);
1da177e4
LT		 359}
360
64798845
JP		 361static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
362 void *p)
1da177e4 363{
60490fe0 364 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 365 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 366 u32 *regs_buff = p;
367 u16 phy_data;
1da177e4 368
406874a7 369 memset(p, 0, E1000_REGS_LEN * sizeof(u32));
1da177e4
LT		 370
371 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
372
1dc32918
JP		 373 regs_buff[0] = er32(CTRL);
374 regs_buff[1] = er32(STATUS);
1da177e4 375
1dc32918
JP		 376 regs_buff[2] = er32(RCTL);
377 regs_buff[3] = er32(RDLEN);
378 regs_buff[4] = er32(RDH);
379 regs_buff[5] = er32(RDT);
380 regs_buff[6] = er32(RDTR);
1da177e4 381
1dc32918
JP		 382 regs_buff[7] = er32(TCTL);
383 regs_buff[8] = er32(TDLEN);
384 regs_buff[9] = er32(TDH);
385 regs_buff[10] = er32(TDT);
386 regs_buff[11] = er32(TIDV);
1da177e4 387
1dc32918 388 regs_buff[12] = hw->phy_type; /* PHY type (IGP=1, M88=0) */
96838a40 389 if (hw->phy_type == e1000_phy_igp) {
1da177e4
LT		 390 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
391 IGP01E1000_PHY_AGC_A);
392 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
393 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 394 regs_buff[13] = (u32)phy_data; /* cable length */
1da177e4
LT		 395 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
396 IGP01E1000_PHY_AGC_B);
397 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B &
398 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 399 regs_buff[14] = (u32)phy_data; /* cable length */
1da177e4
LT		 400 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
401 IGP01E1000_PHY_AGC_C);
402 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C &
403 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 404 regs_buff[15] = (u32)phy_data; /* cable length */
1da177e4
LT		 405 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
406 IGP01E1000_PHY_AGC_D);
407 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D &
408 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 409 regs_buff[16] = (u32)phy_data; /* cable length */
1da177e4
LT		 410 regs_buff[17] = 0; /* extended 10bt distance (not needed) */
411 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
412 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS &
413 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 414 regs_buff[18] = (u32)phy_data; /* cable polarity */
1da177e4
LT		 415 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
416 IGP01E1000_PHY_PCS_INIT_REG);
417 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
418 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
406874a7 419 regs_buff[19] = (u32)phy_data; /* cable polarity */
1da177e4
LT		 420 regs_buff[20] = 0; /* polarity correction enabled (always) */
421 regs_buff[22] = 0; /* phy receive errors (unavailable) */
422 regs_buff[23] = regs_buff[18]; /* mdix mode */
423 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
424 } else {
8fc897b0 425 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
406874a7 426 regs_buff[13] = (u32)phy_data; /* cable length */
1da177e4
LT		 427 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
428 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
429 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
8fc897b0 430 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
406874a7 431 regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
1da177e4
LT		 432 regs_buff[18] = regs_buff[13]; /* cable polarity */
433 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
434 regs_buff[20] = regs_buff[17]; /* polarity correction */
435 /* phy receive errors */
436 regs_buff[22] = adapter->phy_stats.receive_errors;
437 regs_buff[23] = regs_buff[13]; /* mdix mode */
438 }
439 regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
440 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
406874a7 441 regs_buff[24] = (u32)phy_data; /* phy local receiver status */
1da177e4 442 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
96838a40 443 if (hw->mac_type >= e1000_82540 &&
4ccc12ae
JB		 444 hw->mac_type < e1000_82571 &&
445 hw->media_type == e1000_media_type_copper) {
1dc32918 446 regs_buff[26] = er32(MANC);
1da177e4
LT		 447 }
448}
449
64798845 450static int e1000_get_eeprom_len(struct net_device *netdev)
1da177e4 451{
60490fe0 452 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918
JP		 453 struct e1000_hw *hw = &adapter->hw;
454
455 return hw->eeprom.word_size * 2;
1da177e4
LT		 456}
457
64798845
JP		 458static int e1000_get_eeprom(struct net_device *netdev,
459 struct ethtool_eeprom *eeprom, u8 *bytes)
1da177e4 460{
60490fe0 461 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 462 struct e1000_hw *hw = &adapter->hw;
406874a7 463 u16 *eeprom_buff;
1da177e4
LT		 464 int first_word, last_word;
465 int ret_val = 0;
406874a7 466 u16 i;
1da177e4 467
96838a40 468 if (eeprom->len == 0)
1da177e4
LT		 469 return -EINVAL;
470
471 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
472
473 first_word = eeprom->offset >> 1;
474 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
475
406874a7 476 eeprom_buff = kmalloc(sizeof(u16) *
1da177e4 477 (last_word - first_word + 1), GFP_KERNEL);
96838a40 478 if (!eeprom_buff)
1da177e4
LT		 479 return -ENOMEM;
480
96838a40 481 if (hw->eeprom.type == e1000_eeprom_spi)
1da177e4
LT		 482 ret_val = e1000_read_eeprom(hw, first_word,
483 last_word - first_word + 1,
484 eeprom_buff);
485 else {
c7be73bc
JP		 486 for (i = 0; i < last_word - first_word + 1; i++) {
487 ret_val = e1000_read_eeprom(hw, first_word + i, 1,
488 &eeprom_buff[i]);
489 if (ret_val)
1da177e4 490 break;
c7be73bc 491 }
1da177e4
LT		 492 }
493
494 /* Device's eeprom is always little-endian, word addressable */
495 for (i = 0; i < last_word - first_word + 1; i++)
496 le16_to_cpus(&eeprom_buff[i]);
497
406874a7 498 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
1da177e4
LT		 499 eeprom->len);
500 kfree(eeprom_buff);
501
502 return ret_val;
503}
504
64798845
JP		 505static int e1000_set_eeprom(struct net_device *netdev,
506 struct ethtool_eeprom *eeprom, u8 *bytes)
1da177e4 507{
60490fe0 508 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 509 struct e1000_hw *hw = &adapter->hw;
406874a7 510 u16 *eeprom_buff;
1da177e4
LT		 511 void *ptr;
512 int max_len, first_word, last_word, ret_val = 0;
406874a7 513 u16 i;
1da177e4 514
96838a40 515 if (eeprom->len == 0)
1da177e4
LT		 516 return -EOPNOTSUPP;
517
96838a40 518 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1da177e4
LT		 519 return -EFAULT;
520
521 max_len = hw->eeprom.word_size * 2;
522
523 first_word = eeprom->offset >> 1;
524 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
525 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
96838a40 526 if (!eeprom_buff)
1da177e4
LT		 527 return -ENOMEM;
528
529 ptr = (void *)eeprom_buff;
530
96838a40 531 if (eeprom->offset & 1) {
1da177e4
LT		 532 /* need read/modify/write of first changed EEPROM word */
533 /* only the second byte of the word is being modified */
534 ret_val = e1000_read_eeprom(hw, first_word, 1,
535 &eeprom_buff[0]);
536 ptr++;
537 }
96838a40 538 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
1da177e4
LT		 539 /* need read/modify/write of last changed EEPROM word */
540 /* only the first byte of the word is being modified */
541 ret_val = e1000_read_eeprom(hw, last_word, 1,
542 &eeprom_buff[last_word - first_word]);
543 }
544
545 /* Device's eeprom is always little-endian, word addressable */
546 for (i = 0; i < last_word - first_word + 1; i++)
547 le16_to_cpus(&eeprom_buff[i]);
548
549 memcpy(ptr, bytes, eeprom->len);
550
551 for (i = 0; i < last_word - first_word + 1; i++)
552 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
553
554 ret_val = e1000_write_eeprom(hw, first_word,
555 last_word - first_word + 1, eeprom_buff);
556
96838a40 557 /* Update the checksum over the first part of the EEPROM if needed
a7990ba6 558 * and flush shadow RAM for 82573 conrollers */
96838a40 559 if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) ||
a7990ba6 560 (hw->mac_type == e1000_82573)))
1da177e4
LT		 561 e1000_update_eeprom_checksum(hw);
562
563 kfree(eeprom_buff);
564 return ret_val;
565}
566
64798845
JP		 567static void e1000_get_drvinfo(struct net_device *netdev,
568 struct ethtool_drvinfo *drvinfo)
1da177e4 569{
60490fe0 570 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 571 struct e1000_hw *hw = &adapter->hw;
a2917e22 572 char firmware_version[32];
406874a7 573 u16 eeprom_data;
1da177e4
LT		 574
575 strncpy(drvinfo->driver, e1000_driver_name, 32);
576 strncpy(drvinfo->version, e1000_driver_version, 32);
a2917e22
JK		 577
578 /* EEPROM image version # is reported as firmware version # for
579 * 8257{1|2|3} controllers */
1dc32918
JP		 580 e1000_read_eeprom(hw, 5, 1, &eeprom_data);
581 switch (hw->mac_type) {
a2917e22
JK		 582 case e1000_82571:
583 case e1000_82572:
584 case e1000_82573:
6418ecc6 585 case e1000_80003es2lan:
cd94dd0b 586 case e1000_ich8lan:
a2917e22
JK		 587 sprintf(firmware_version, "%d.%d-%d",
588 (eeprom_data & 0xF000) >> 12,
589 (eeprom_data & 0x0FF0) >> 4,
590 eeprom_data & 0x000F);
591 break;
592 default:
593 sprintf(firmware_version, "N/A");
594 }
595
596 strncpy(drvinfo->fw_version, firmware_version, 32);
1da177e4 597 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
1da177e4
LT		 598 drvinfo->regdump_len = e1000_get_regs_len(netdev);
599 drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
600}
601
64798845
JP		 602static void e1000_get_ringparam(struct net_device *netdev,
603 struct ethtool_ringparam *ring)
1da177e4 604{
60490fe0 605 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918
JP		 606 struct e1000_hw *hw = &adapter->hw;
607 e1000_mac_type mac_type = hw->mac_type;
581d708e
MC		 608 struct e1000_tx_ring *txdr = adapter->tx_ring;
609 struct e1000_rx_ring *rxdr = adapter->rx_ring;
1da177e4
LT		 610
611 ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD :
612 E1000_MAX_82544_RXD;
613 ring->tx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_TXD :
614 E1000_MAX_82544_TXD;
615 ring->rx_mini_max_pending = 0;
616 ring->rx_jumbo_max_pending = 0;
617 ring->rx_pending = rxdr->count;
618 ring->tx_pending = txdr->count;
619 ring->rx_mini_pending = 0;
620 ring->rx_jumbo_pending = 0;
621}
622
64798845
JP		 623static int e1000_set_ringparam(struct net_device *netdev,
624 struct ethtool_ringparam *ring)
1da177e4 625{
60490fe0 626 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918
JP		 627 struct e1000_hw *hw = &adapter->hw;
628 e1000_mac_type mac_type = hw->mac_type;
793fab72
VA		 629 struct e1000_tx_ring *txdr, *tx_old;
630 struct e1000_rx_ring *rxdr, *rx_old;
1c7e5b12 631 int i, err;
581d708e 632
0989aa43
JK		 633 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
634 return -EINVAL;
635
2db10a08
AK		 636 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
637 msleep(1);
638
581d708e
MC		 639 if (netif_running(adapter->netdev))
640 e1000_down(adapter);
1da177e4
LT		 641
642 tx_old = adapter->tx_ring;
643 rx_old = adapter->rx_ring;
644
793fab72 645 err = -ENOMEM;
1c7e5b12 646 txdr = kcalloc(adapter->num_tx_queues, sizeof(struct e1000_tx_ring), GFP_KERNEL);
793fab72
VA		 647 if (!txdr)
648 goto err_alloc_tx;
581d708e 649
1c7e5b12 650 rxdr = kcalloc(adapter->num_rx_queues, sizeof(struct e1000_rx_ring), GFP_KERNEL);
793fab72
VA		 651 if (!rxdr)
652 goto err_alloc_rx;
581d708e 653
793fab72
VA		 654 adapter->tx_ring = txdr;
655 adapter->rx_ring = rxdr;
581d708e 656
406874a7
JP		 657 rxdr->count = max(ring->rx_pending,(u32)E1000_MIN_RXD);
658 rxdr->count = min(rxdr->count,(u32)(mac_type < e1000_82544 ?
1da177e4 659 E1000_MAX_RXD : E1000_MAX_82544_RXD));
9099cfb9 660 rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
1da177e4 661
406874a7
JP		 662 txdr->count = max(ring->tx_pending,(u32)E1000_MIN_TXD);
663 txdr->count = min(txdr->count,(u32)(mac_type < e1000_82544 ?
1da177e4 664 E1000_MAX_TXD : E1000_MAX_82544_TXD));
9099cfb9 665 txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
1da177e4 666
f56799ea 667 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 668 txdr[i].count = txdr->count;
f56799ea 669 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 670 rxdr[i].count = rxdr->count;
581d708e 671
96838a40 672 if (netif_running(adapter->netdev)) {
1da177e4 673 /* Try to get new resources before deleting old */
c7be73bc
JP		 674 err = e1000_setup_all_rx_resources(adapter);
675 if (err)
1da177e4 676 goto err_setup_rx;
c7be73bc
JP		 677 err = e1000_setup_all_tx_resources(adapter);
678 if (err)
1da177e4
LT		 679 goto err_setup_tx;
680
681 /* save the new, restore the old in order to free it,
682 * then restore the new back again */
683
1da177e4
LT		 684 adapter->rx_ring = rx_old;
685 adapter->tx_ring = tx_old;
581d708e
MC		 686 e1000_free_all_rx_resources(adapter);
687 e1000_free_all_tx_resources(adapter);
688 kfree(tx_old);
689 kfree(rx_old);
793fab72
VA		 690 adapter->rx_ring = rxdr;
691 adapter->tx_ring = txdr;
c7be73bc
JP		 692 err = e1000_up(adapter);
693 if (err)
2db10a08 694 goto err_setup;
1da177e4
LT		 695 }
696
2db10a08 697 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 698 return 0;
699err_setup_tx:
581d708e 700 e1000_free_all_rx_resources(adapter);
1da177e4
LT		 701err_setup_rx:
702 adapter->rx_ring = rx_old;
703 adapter->tx_ring = tx_old;
793fab72
VA		 704 kfree(rxdr);
705err_alloc_rx:
706 kfree(txdr);
707err_alloc_tx:
1da177e4 708 e1000_up(adapter);
2db10a08
AK		 709err_setup:
710 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 711 return err;
712}
713
64798845
JP		 714static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, int reg,
715 u32 mask, u32 write)
7e64300a 716{
1dc32918 717 struct e1000_hw *hw = &adapter->hw;
406874a7 718 static const u32 test[] =
7e64300a 719 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1dc32918 720 u8 __iomem *address = hw->hw_addr + reg;
406874a7 721 u32 read;
7e64300a
JP		 722 int i;
723
724 for (i = 0; i < ARRAY_SIZE(test); i++) {
725 writel(write & test[i], address);
726 read = readl(address);
727 if (read != (write & test[i] & mask)) {
728 DPRINTK(DRV, ERR, "pattern test reg %04X failed: "
729 "got 0x%08X expected 0x%08X\n",
cba0516d 730 reg, read, (write & test[i] & mask));
7e64300a
JP		 731 *data = reg;
732 return true;
733 }
734 }
735 return false;
1da177e4
LT		 736}
737
64798845
JP		 738static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, int reg,
739 u32 mask, u32 write)
7e64300a 740{
1dc32918
JP		 741 struct e1000_hw *hw = &adapter->hw;
742 u8 __iomem *address = hw->hw_addr + reg;
406874a7 743 u32 read;
7e64300a
JP		 744
745 writel(write & mask, address);
746 read = readl(address);
747 if ((read & mask) != (write & mask)) {
748 DPRINTK(DRV, ERR, "set/check reg %04X test failed: "
749 "got 0x%08X expected 0x%08X\n",
750 reg, (read & mask), (write & mask));
751 *data = reg;
752 return true;
753 }
754 return false;
1da177e4
LT		 755}
756
7e64300a
JP		 757#define REG_PATTERN_TEST(reg, mask, write) \
758 do { \
759 if (reg_pattern_test(adapter, data, \
1dc32918 760 (hw->mac_type >= e1000_82543) \
7e64300a
JP		 761 ? E1000_##reg : E1000_82542_##reg, \
762 mask, write)) \
763 return 1; \
764 } while (0)
765
766#define REG_SET_AND_CHECK(reg, mask, write) \
767 do { \
768 if (reg_set_and_check(adapter, data, \
1dc32918 769 (hw->mac_type >= e1000_82543) \
7e64300a
JP		 770 ? E1000_##reg : E1000_82542_##reg, \
771 mask, write)) \
772 return 1; \
773 } while (0)
774
64798845 775static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
1da177e4 776{
406874a7
JP		 777 u32 value, before, after;
778 u32 i, toggle;
1dc32918 779 struct e1000_hw *hw = &adapter->hw;
1da177e4
LT		 780
781 /* The status register is Read Only, so a write should fail.
782 * Some bits that get toggled are ignored.
783 */
1dc32918 784 switch (hw->mac_type) {
868d5309
MC		 785 /* there are several bits on newer hardware that are r/w */
786 case e1000_82571:
787 case e1000_82572:
6418ecc6 788 case e1000_80003es2lan:
868d5309
MC		 789 toggle = 0x7FFFF3FF;
790 break;
b01f6691 791 case e1000_82573:
cd94dd0b 792 case e1000_ich8lan:
b01f6691
MC		 793 toggle = 0x7FFFF033;
794 break;
795 default:
796 toggle = 0xFFFFF833;
797 break;
798 }
799
1dc32918
JP		 800 before = er32(STATUS);
801 value = (er32(STATUS) & toggle);
802 ew32(STATUS, toggle);
803 after = er32(STATUS) & toggle;
96838a40 804 if (value != after) {
b01f6691
MC		 805 DPRINTK(DRV, ERR, "failed STATUS register test got: "
806 "0x%08X expected: 0x%08X\n", after, value);
1da177e4
LT		 807 *data = 1;
808 return 1;
809 }
b01f6691 810 /* restore previous status */
1dc32918 811 ew32(STATUS, before);
90fb5135 812
1dc32918 813 if (hw->mac_type != e1000_ich8lan) {
cd94dd0b
AK		 814 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
815 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
816 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
817 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
818 }
90fb5135 819
1da177e4
LT		 820 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
821 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
822 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
823 REG_PATTERN_TEST(RDH, 0x0000FFFF, 0x0000FFFF);
824 REG_PATTERN_TEST(RDT, 0x0000FFFF, 0x0000FFFF);
825 REG_PATTERN_TEST(FCRTH, 0x0000FFF8, 0x0000FFF8);
826 REG_PATTERN_TEST(FCTTV, 0x0000FFFF, 0x0000FFFF);
827 REG_PATTERN_TEST(TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
828 REG_PATTERN_TEST(TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
829 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
830
831 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
90fb5135 832
1dc32918 833 before = (hw->mac_type == e1000_ich8lan ?
90fb5135 834 0x06C3B33E : 0x06DFB3FE);
cd94dd0b 835 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
1da177e4
LT		 836 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
837
1dc32918 838 if (hw->mac_type >= e1000_82543) {
1da177e4 839
cd94dd0b 840 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
1da177e4 841 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
1dc32918 842 if (hw->mac_type != e1000_ich8lan)
cd94dd0b 843 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
1da177e4
LT		 844 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
845 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
1dc32918 846 value = (hw->mac_type == e1000_ich8lan ?
90fb5135 847 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
cd94dd0b 848 for (i = 0; i < value; i++) {
1da177e4 849 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
90fb5135 850 0xFFFFFFFF);
1da177e4
LT		 851 }
852
853 } else {
854
855 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF);
856 REG_PATTERN_TEST(RDBAL, 0xFFFFF000, 0xFFFFFFFF);
857 REG_PATTERN_TEST(TXCW, 0x0000FFFF, 0x0000FFFF);
858 REG_PATTERN_TEST(TDBAL, 0xFFFFF000, 0xFFFFFFFF);
859
860 }
861
1dc32918 862 value = (hw->mac_type == e1000_ich8lan ?
cd94dd0b
AK		 863 E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
864 for (i = 0; i < value; i++)
1da177e4
LT		 865 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
866
867 *data = 0;
868 return 0;
869}
870
64798845 871static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
1da177e4 872{
1dc32918 873 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 874 u16 temp;
875 u16 checksum = 0;
876 u16 i;
1da177e4
LT		 877
878 *data = 0;
879 /* Read and add up the contents of the EEPROM */
96838a40 880 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
1dc32918 881 if ((e1000_read_eeprom(hw, i, 1, &temp)) < 0) {
1da177e4
LT		 882 *data = 1;
883 break;
884 }
885 checksum += temp;
886 }
887
888 /* If Checksum is not Correct return error else test passed */
e982f17c 889 if ((checksum != (u16)EEPROM_SUM) && !(*data))
1da177e4
LT		 890 *data = 2;
891
892 return *data;
893}
894
64798845 895static irqreturn_t e1000_test_intr(int irq, void *data)
1da177e4 896{
e982f17c 897 struct net_device *netdev = (struct net_device *)data;
60490fe0 898 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 899 struct e1000_hw *hw = &adapter->hw;
1da177e4 900
1dc32918 901 adapter->test_icr |= er32(ICR);
1da177e4
LT		 902
903 return IRQ_HANDLED;
904}
905
64798845 906static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
1da177e4
LT		 907{
908 struct net_device *netdev = adapter->netdev;
406874a7 909 u32 mask, i = 0;
c3033b01 910 bool shared_int = true;
406874a7 911 u32 irq = adapter->pdev->irq;
1dc32918 912 struct e1000_hw *hw = &adapter->hw;
1da177e4
LT		 913
914 *data = 0;
915
8fc897b0 916 /* NOTE: we don't test MSI interrupts here, yet */
1da177e4 917 /* Hook up test interrupt handler just for this test */
90fb5135
AK		 918 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
919 netdev))
c3033b01 920 shared_int = false;
8fc897b0 921 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
90fb5135 922 netdev->name, netdev)) {
1da177e4
LT		 923 *data = 1;
924 return -1;
925 }
8fc897b0 926 DPRINTK(HW, INFO, "testing %s interrupt\n",
b9b6e78b 927 (shared_int ? "shared" : "unshared"));
1da177e4
LT		 928
929 /* Disable all the interrupts */
1dc32918 930 ew32(IMC, 0xFFFFFFFF);
f8ec4733 931 msleep(10);
1da177e4
LT		 932
933 /* Test each interrupt */
96838a40 934 for (; i < 10; i++) {
1da177e4 935
1dc32918 936 if (hw->mac_type == e1000_ich8lan && i == 8)
cd94dd0b 937 continue;
90fb5135 938
1da177e4
LT		 939 /* Interrupt to test */
940 mask = 1 << i;
941
76c224bc
AK		 942 if (!shared_int) {
943 /* Disable the interrupt to be reported in
944 * the cause register and then force the same
945 * interrupt and see if one gets posted. If
946 * an interrupt was posted to the bus, the
947 * test failed.
948 */
949 adapter->test_icr = 0;
1dc32918
JP		 950 ew32(IMC, mask);
951 ew32(ICS, mask);
f8ec4733 952 msleep(10);
76c224bc
AK		 953
954 if (adapter->test_icr & mask) {
955 *data = 3;
956 break;
957 }
1da177e4
LT		 958 }
959
960 /* Enable the interrupt to be reported in
961 * the cause register and then force the same
962 * interrupt and see if one gets posted. If
963 * an interrupt was not posted to the bus, the
964 * test failed.
965 */
966 adapter->test_icr = 0;
1dc32918
JP		 967 ew32(IMS, mask);
968 ew32(ICS, mask);
f8ec4733 969 msleep(10);
1da177e4 970
96838a40 971 if (!(adapter->test_icr & mask)) {
1da177e4
LT		 972 *data = 4;
973 break;
974 }
975
76c224bc 976 if (!shared_int) {
1da177e4
LT		 977 /* Disable the other interrupts to be reported in
978 * the cause register and then force the other
979 * interrupts and see if any get posted. If
980 * an interrupt was posted to the bus, the
981 * test failed.
982 */
983 adapter->test_icr = 0;
1dc32918
JP		 984 ew32(IMC, ~mask & 0x00007FFF);
985 ew32(ICS, ~mask & 0x00007FFF);
f8ec4733 986 msleep(10);
1da177e4 987
96838a40 988 if (adapter->test_icr) {
1da177e4
LT		 989 *data = 5;
990 break;
991 }
992 }
993 }
994
995 /* Disable all the interrupts */
1dc32918 996 ew32(IMC, 0xFFFFFFFF);
f8ec4733 997 msleep(10);
1da177e4
LT		 998
999 /* Unhook test interrupt handler */
1000 free_irq(irq, netdev);
1001
1002 return *data;
1003}
1004
64798845 1005static void e1000_free_desc_rings(struct e1000_adapter *adapter)
1da177e4 1006{
581d708e
MC		 1007 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1008 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1da177e4
LT		 1009 struct pci_dev *pdev = adapter->pdev;
1010 int i;
1011
96838a40
JB		 1012 if (txdr->desc && txdr->buffer_info) {
1013 for (i = 0; i < txdr->count; i++) {
1014 if (txdr->buffer_info[i].dma)
1da177e4
LT		 1015 pci_unmap_single(pdev, txdr->buffer_info[i].dma,
1016 txdr->buffer_info[i].length,
1017 PCI_DMA_TODEVICE);
96838a40 1018 if (txdr->buffer_info[i].skb)
1da177e4
LT		 1019 dev_kfree_skb(txdr->buffer_info[i].skb);
1020 }
1021 }
1022
96838a40
JB		 1023 if (rxdr->desc && rxdr->buffer_info) {
1024 for (i = 0; i < rxdr->count; i++) {
1025 if (rxdr->buffer_info[i].dma)
1da177e4
LT		 1026 pci_unmap_single(pdev, rxdr->buffer_info[i].dma,
1027 rxdr->buffer_info[i].length,
1028 PCI_DMA_FROMDEVICE);
96838a40 1029 if (rxdr->buffer_info[i].skb)
1da177e4
LT		 1030 dev_kfree_skb(rxdr->buffer_info[i].skb);
1031 }
1032 }
1033
f5645110 1034 if (txdr->desc) {
1da177e4 1035 pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma);
6b27adb6
JL		 1036 txdr->desc = NULL;
1037 }
f5645110 1038 if (rxdr->desc) {
1da177e4 1039 pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
6b27adb6
JL		 1040 rxdr->desc = NULL;
1041 }
1da177e4 1042
b4558ea9 1043 kfree(txdr->buffer_info);
6b27adb6 1044 txdr->buffer_info = NULL;
b4558ea9 1045 kfree(rxdr->buffer_info);
6b27adb6 1046 rxdr->buffer_info = NULL;
f5645110 1047
1da177e4
LT		 1048 return;
1049}
1050
64798845 1051static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
1da177e4 1052{
1dc32918 1053 struct e1000_hw *hw = &adapter->hw;
581d708e
MC		 1054 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1055 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1da177e4 1056 struct pci_dev *pdev = adapter->pdev;
406874a7 1057 u32 rctl;
1c7e5b12 1058 int i, ret_val;
1da177e4
LT		 1059
1060 /* Setup Tx descriptor ring and Tx buffers */
1061
96838a40
JB		 1062 if (!txdr->count)
1063 txdr->count = E1000_DEFAULT_TXD;
1da177e4 1064
c7be73bc
JP		 1065 txdr->buffer_info = kcalloc(txdr->count, sizeof(struct e1000_buffer),
1066 GFP_KERNEL);
1067 if (!txdr->buffer_info) {
1da177e4
LT		 1068 ret_val = 1;
1069 goto err_nomem;
1070 }
1da177e4
LT		 1071
1072 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9099cfb9 1073 txdr->size = ALIGN(txdr->size, 4096);
c7be73bc
JP		 1074 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1075 if (!txdr->desc) {
1da177e4
LT		 1076 ret_val = 2;
1077 goto err_nomem;
1078 }
1079 memset(txdr->desc, 0, txdr->size);
1080 txdr->next_to_use = txdr->next_to_clean = 0;
1081
e982f17c
JP		 1082 ew32(TDBAL, ((u64)txdr->dma & 0x00000000FFFFFFFF));
1083 ew32(TDBAH, ((u64)txdr->dma >> 32));
1dc32918
JP		 1084 ew32(TDLEN, txdr->count * sizeof(struct e1000_tx_desc));
1085 ew32(TDH, 0);
1086 ew32(TDT, 0);
1087 ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN |
1088 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1089 E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1da177e4 1090
96838a40 1091 for (i = 0; i < txdr->count; i++) {
1da177e4
LT		 1092 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i);
1093 struct sk_buff *skb;
1094 unsigned int size = 1024;
1095
c7be73bc
JP		 1096 skb = alloc_skb(size, GFP_KERNEL);
1097 if (!skb) {
1da177e4
LT		 1098 ret_val = 3;
1099 goto err_nomem;
1100 }
1101 skb_put(skb, size);
1102 txdr->buffer_info[i].skb = skb;
1103 txdr->buffer_info[i].length = skb->len;
1104 txdr->buffer_info[i].dma =
1105 pci_map_single(pdev, skb->data, skb->len,
1106 PCI_DMA_TODEVICE);
1107 tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
1108 tx_desc->lower.data = cpu_to_le32(skb->len);
1109 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1110 E1000_TXD_CMD_IFCS |
1111 E1000_TXD_CMD_RPS);
1112 tx_desc->upper.data = 0;
1113 }
1114
1115 /* Setup Rx descriptor ring and Rx buffers */
1116
96838a40
JB		 1117 if (!rxdr->count)
1118 rxdr->count = E1000_DEFAULT_RXD;
1da177e4 1119
c7be73bc
JP		 1120 rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer),
1121 GFP_KERNEL);
1122 if (!rxdr->buffer_info) {
1da177e4
LT		 1123 ret_val = 4;
1124 goto err_nomem;
1125 }
1da177e4
LT		 1126
1127 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
c7be73bc
JP		 1128 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1129 if (!rxdr->desc) {
1da177e4
LT		 1130 ret_val = 5;
1131 goto err_nomem;
1132 }
1133 memset(rxdr->desc, 0, rxdr->size);
1134 rxdr->next_to_use = rxdr->next_to_clean = 0;
1135
1dc32918
JP		 1136 rctl = er32(RCTL);
1137 ew32(RCTL, rctl & ~E1000_RCTL_EN);
e982f17c
JP		 1138 ew32(RDBAL, ((u64)rxdr->dma & 0xFFFFFFFF));
1139 ew32(RDBAH, ((u64)rxdr->dma >> 32));
1dc32918
JP		 1140 ew32(RDLEN, rxdr->size);
1141 ew32(RDH, 0);
1142 ew32(RDT, 0);
1da177e4
LT		 1143 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1144 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1dc32918
JP		 1145 (hw->mc_filter_type << E1000_RCTL_MO_SHIFT);
1146 ew32(RCTL, rctl);
1da177e4 1147
96838a40 1148 for (i = 0; i < rxdr->count; i++) {
1da177e4
LT		 1149 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
1150 struct sk_buff *skb;
1151
c7be73bc
JP		 1152 skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1153 if (!skb) {
1da177e4
LT		 1154 ret_val = 6;
1155 goto err_nomem;
1156 }
1157 skb_reserve(skb, NET_IP_ALIGN);
1158 rxdr->buffer_info[i].skb = skb;
1159 rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
1160 rxdr->buffer_info[i].dma =
1161 pci_map_single(pdev, skb->data, E1000_RXBUFFER_2048,
1162 PCI_DMA_FROMDEVICE);
1163 rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
1164 memset(skb->data, 0x00, skb->len);
1165 }
1166
1167 return 0;
1168
1169err_nomem:
1170 e1000_free_desc_rings(adapter);
1171 return ret_val;
1172}
1173
64798845 1174static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
1da177e4 1175{
1dc32918
JP		 1176 struct e1000_hw *hw = &adapter->hw;
1177
1da177e4 1178 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1dc32918
JP		 1179 e1000_write_phy_reg(hw, 29, 0x001F);
1180 e1000_write_phy_reg(hw, 30, 0x8FFC);
1181 e1000_write_phy_reg(hw, 29, 0x001A);
1182 e1000_write_phy_reg(hw, 30, 0x8FF0);
1da177e4
LT		 1183}
1184
64798845 1185static void e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
1da177e4 1186{
1dc32918 1187 struct e1000_hw *hw = &adapter->hw;
406874a7 1188 u16 phy_reg;
1da177e4
LT		 1189
1190 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1191 * Extended PHY Specific Control Register to 25MHz clock. This
1192 * value defaults back to a 2.5MHz clock when the PHY is reset.
1193 */
1dc32918 1194 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1da177e4 1195 phy_reg |= M88E1000_EPSCR_TX_CLK_25;
1dc32918 1196 e1000_write_phy_reg(hw,
1da177e4
LT		 1197 M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
1198
1199 /* In addition, because of the s/w reset above, we need to enable
1200 * CRS on TX. This must be set for both full and half duplex
1201 * operation.
1202 */
1dc32918 1203 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1da177e4 1204 phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1dc32918 1205 e1000_write_phy_reg(hw,
1da177e4
LT		 1206 M88E1000_PHY_SPEC_CTRL, phy_reg);
1207}
1208
64798845 1209static int e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1da177e4 1210{
1dc32918 1211 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 1212 u32 ctrl_reg;
1213 u16 phy_reg;
1da177e4
LT		 1214
1215 /* Setup the Device Control Register for PHY loopback test. */
1216
1dc32918 1217 ctrl_reg = er32(CTRL);
1da177e4
LT		 1218 ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */
1219 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1220 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1221 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
1222 E1000_CTRL_FD); /* Force Duplex to FULL */
1223
1dc32918 1224 ew32(CTRL, ctrl_reg);
1da177e4
LT		 1225
1226 /* Read the PHY Specific Control Register (0x10) */
1dc32918 1227 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1da177e4
LT		 1228
1229 /* Clear Auto-Crossover bits in PHY Specific Control Register
1230 * (bits 6:5).
1231 */
1232 phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
1dc32918 1233 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
1da177e4
LT		 1234
1235 /* Perform software reset on the PHY */
1dc32918 1236 e1000_phy_reset(hw);
1da177e4
LT		 1237
1238 /* Have to setup TX_CLK and TX_CRS after software reset */
1239 e1000_phy_reset_clk_and_crs(adapter);
1240
1dc32918 1241 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100);
1da177e4
LT		 1242
1243 /* Wait for reset to complete. */
1244 udelay(500);
1245
1246 /* Have to setup TX_CLK and TX_CRS after software reset */
1247 e1000_phy_reset_clk_and_crs(adapter);
1248
1249 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1250 e1000_phy_disable_receiver(adapter);
1251
1252 /* Set the loopback bit in the PHY control register. */
1dc32918 1253 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1da177e4 1254 phy_reg |= MII_CR_LOOPBACK;
1dc32918 1255 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1da177e4
LT		 1256
1257 /* Setup TX_CLK and TX_CRS one more time. */
1258 e1000_phy_reset_clk_and_crs(adapter);
1259
1260 /* Check Phy Configuration */
1dc32918 1261 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
96838a40 1262 if (phy_reg != 0x4100)
1da177e4
LT		 1263 return 9;
1264
1dc32918 1265 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
96838a40 1266 if (phy_reg != 0x0070)
1da177e4
LT		 1267 return 10;
1268
1dc32918 1269 e1000_read_phy_reg(hw, 29, &phy_reg);
96838a40 1270 if (phy_reg != 0x001A)
1da177e4
LT		 1271 return 11;
1272
1273 return 0;
1274}
1275
64798845 1276static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1da177e4 1277{
1dc32918 1278 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 1279 u32 ctrl_reg = 0;
1280 u32 stat_reg = 0;
1da177e4 1281
1dc32918 1282 hw->autoneg = false;
1da177e4 1283
1dc32918 1284 if (hw->phy_type == e1000_phy_m88) {
1da177e4 1285 /* Auto-MDI/MDIX Off */
1dc32918 1286 e1000_write_phy_reg(hw,
1da177e4
LT		 1287 M88E1000_PHY_SPEC_CTRL, 0x0808);
1288 /* reset to update Auto-MDI/MDIX */
1dc32918 1289 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140);
1da177e4 1290 /* autoneg off */
1dc32918
JP		 1291 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
1292 } else if (hw->phy_type == e1000_phy_gg82563)
1293 e1000_write_phy_reg(hw,
87041639 1294 GG82563_PHY_KMRN_MODE_CTRL,
acfbc9fd 1295 0x1CC);
1da177e4 1296
1dc32918 1297 ctrl_reg = er32(CTRL);
cd94dd0b 1298
1dc32918 1299 if (hw->phy_type == e1000_phy_ife) {
cd94dd0b 1300 /* force 100, set loopback */
1dc32918 1301 e1000_write_phy_reg(hw, PHY_CTRL, 0x6100);
cd94dd0b
AK		 1302
1303 /* Now set up the MAC to the same speed/duplex as the PHY. */
1304 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1305 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1306 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1307 E1000_CTRL_SPD_100 |/* Force Speed to 100 */
1308 E1000_CTRL_FD); /* Force Duplex to FULL */
1309 } else {
1310 /* force 1000, set loopback */
1dc32918 1311 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
cd94dd0b
AK		 1312
1313 /* Now set up the MAC to the same speed/duplex as the PHY. */
1dc32918 1314 ctrl_reg = er32(CTRL);
cd94dd0b
AK		 1315 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1316 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1317 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1318 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1319 E1000_CTRL_FD); /* Force Duplex to FULL */
1320 }
1da177e4 1321
1dc32918
JP		 1322 if (hw->media_type == e1000_media_type_copper &&
1323 hw->phy_type == e1000_phy_m88)
1da177e4 1324 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
8fc897b0 1325 else {
1da177e4
LT		 1326 /* Set the ILOS bit on the fiber Nic is half
1327 * duplex link is detected. */
1dc32918 1328 stat_reg = er32(STATUS);
96838a40 1329 if ((stat_reg & E1000_STATUS_FD) == 0)
1da177e4
LT		 1330 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1331 }
1332
1dc32918 1333 ew32(CTRL, ctrl_reg);
1da177e4
LT		 1334
1335 /* Disable the receiver on the PHY so when a cable is plugged in, the
1336 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1337 */
1dc32918 1338 if (hw->phy_type == e1000_phy_m88)
1da177e4
LT		 1339 e1000_phy_disable_receiver(adapter);
1340
1341 udelay(500);
1342
1343 return 0;
1344}
1345
64798845 1346static int e1000_set_phy_loopback(struct e1000_adapter *adapter)
1da177e4 1347{
1dc32918 1348 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 1349 u16 phy_reg = 0;
1350 u16 count = 0;
1da177e4 1351
1dc32918 1352 switch (hw->mac_type) {
1da177e4 1353 case e1000_82543:
1dc32918 1354 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1355 /* Attempt to setup Loopback mode on Non-integrated PHY.
1356 * Some PHY registers get corrupted at random, so
1357 * attempt this 10 times.
1358 */
96838a40 1359 while (e1000_nonintegrated_phy_loopback(adapter) &&
1da177e4 1360 count++ < 10);
96838a40 1361 if (count < 11)
1da177e4
LT		 1362 return 0;
1363 }
1364 break;
1365
1366 case e1000_82544:
1367 case e1000_82540:
1368 case e1000_82545:
1369 case e1000_82545_rev_3:
1370 case e1000_82546:
1371 case e1000_82546_rev_3:
1372 case e1000_82541:
1373 case e1000_82541_rev_2:
1374 case e1000_82547:
1375 case e1000_82547_rev_2:
868d5309
MC		 1376 case e1000_82571:
1377 case e1000_82572:
4564327b 1378 case e1000_82573:
6418ecc6 1379 case e1000_80003es2lan:
cd94dd0b 1380 case e1000_ich8lan:
1da177e4
LT		 1381 return e1000_integrated_phy_loopback(adapter);
1382 break;
1383
1384 default:
1385 /* Default PHY loopback work is to read the MII
1386 * control register and assert bit 14 (loopback mode).
1387 */
1dc32918 1388 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1da177e4 1389 phy_reg |= MII_CR_LOOPBACK;
1dc32918 1390 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1da177e4
LT		 1391 return 0;
1392 break;
1393 }
1394
1395 return 8;
1396}
1397
64798845 1398static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
1da177e4 1399{
49273163 1400 struct e1000_hw *hw = &adapter->hw;
406874a7 1401 u32 rctl;
1da177e4 1402
49273163
JK		 1403 if (hw->media_type == e1000_media_type_fiber ||
1404 hw->media_type == e1000_media_type_internal_serdes) {
1405 switch (hw->mac_type) {
1406 case e1000_82545:
1407 case e1000_82546:
1408 case e1000_82545_rev_3:
1409 case e1000_82546_rev_3:
1da177e4 1410 return e1000_set_phy_loopback(adapter);
49273163
JK		 1411 break;
1412 case e1000_82571:
1413 case e1000_82572:
1414#define E1000_SERDES_LB_ON 0x410
1415 e1000_set_phy_loopback(adapter);
1dc32918 1416 ew32(SCTL, E1000_SERDES_LB_ON);
f8ec4733 1417 msleep(10);
49273163
JK		 1418 return 0;
1419 break;
1420 default:
1dc32918 1421 rctl = er32(RCTL);
1da177e4 1422 rctl |= E1000_RCTL_LBM_TCVR;
1dc32918 1423 ew32(RCTL, rctl);
1da177e4
LT		 1424 return 0;
1425 }
49273163 1426 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 1427 return e1000_set_phy_loopback(adapter);
1428
1429 return 7;
1430}
1431
64798845 1432static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
1da177e4 1433{
49273163 1434 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 1435 u32 rctl;
1436 u16 phy_reg;
1da177e4 1437
1dc32918 1438 rctl = er32(RCTL);
1da177e4 1439 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1dc32918 1440 ew32(RCTL, rctl);
1da177e4 1441
49273163
JK		 1442 switch (hw->mac_type) {
1443 case e1000_82571:
1444 case e1000_82572:
1445 if (hw->media_type == e1000_media_type_fiber ||
1446 hw->media_type == e1000_media_type_internal_serdes) {
1447#define E1000_SERDES_LB_OFF 0x400
1dc32918 1448 ew32(SCTL, E1000_SERDES_LB_OFF);
f8ec4733 1449 msleep(10);
49273163
JK		 1450 break;
1451 }
1452 /* Fall Through */
1453 case e1000_82545:
1454 case e1000_82546:
1455 case e1000_82545_rev_3:
1456 case e1000_82546_rev_3:
1457 default:
c3033b01 1458 hw->autoneg = true;
8fc897b0 1459 if (hw->phy_type == e1000_phy_gg82563)
87041639
JK		 1460 e1000_write_phy_reg(hw,
1461 GG82563_PHY_KMRN_MODE_CTRL,
1462 0x180);
49273163
JK		 1463 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1464 if (phy_reg & MII_CR_LOOPBACK) {
1da177e4 1465 phy_reg &= ~MII_CR_LOOPBACK;
49273163
JK		 1466 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1467 e1000_phy_reset(hw);
1da177e4 1468 }
49273163 1469 break;
1da177e4
LT		 1470 }
1471}
1472
64798845
JP		 1473static void e1000_create_lbtest_frame(struct sk_buff *skb,
1474 unsigned int frame_size)
1da177e4
LT		 1475{
1476 memset(skb->data, 0xFF, frame_size);
ce7393b9 1477 frame_size &= ~1;
1da177e4
LT		 1478 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1479 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1480 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1481}
1482
64798845
JP		 1483static int e1000_check_lbtest_frame(struct sk_buff *skb,
1484 unsigned int frame_size)
1da177e4 1485{
ce7393b9 1486 frame_size &= ~1;
96838a40
JB		 1487 if (*(skb->data + 3) == 0xFF) {
1488 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1da177e4
LT		 1489 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1490 return 0;
1491 }
1492 }
1493 return 13;
1494}
1495
64798845 1496static int e1000_run_loopback_test(struct e1000_adapter *adapter)
1da177e4 1497{
1dc32918 1498 struct e1000_hw *hw = &adapter->hw;
581d708e
MC		 1499 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1500 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1da177e4 1501 struct pci_dev *pdev = adapter->pdev;
e4eff729
MC		 1502 int i, j, k, l, lc, good_cnt, ret_val=0;
1503 unsigned long time;
1da177e4 1504
1dc32918 1505 ew32(RDT, rxdr->count - 1);
1da177e4 1506
96838a40 1507 /* Calculate the loop count based on the largest descriptor ring
e4eff729
MC		 1508 * The idea is to wrap the largest ring a number of times using 64
1509 * send/receive pairs during each loop
1510 */
1da177e4 1511
96838a40 1512 if (rxdr->count <= txdr->count)
e4eff729
MC		 1513 lc = ((txdr->count / 64) * 2) + 1;
1514 else
1515 lc = ((rxdr->count / 64) * 2) + 1;
1516
1517 k = l = 0;
96838a40
JB		 1518 for (j = 0; j <= lc; j++) { /* loop count loop */
1519 for (i = 0; i < 64; i++) { /* send the packets */
1520 e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
e4eff729 1521 1024);
96838a40 1522 pci_dma_sync_single_for_device(pdev,
e4eff729
MC		 1523 txdr->buffer_info[k].dma,
1524 txdr->buffer_info[k].length,
1525 PCI_DMA_TODEVICE);
96838a40 1526 if (unlikely(++k == txdr->count)) k = 0;
e4eff729 1527 }
1dc32918 1528 ew32(TDT, k);
f8ec4733 1529 msleep(200);
e4eff729
MC		 1530 time = jiffies; /* set the start time for the receive */
1531 good_cnt = 0;
1532 do { /* receive the sent packets */
96838a40 1533 pci_dma_sync_single_for_cpu(pdev,
e4eff729
MC		 1534 rxdr->buffer_info[l].dma,
1535 rxdr->buffer_info[l].length,
1536 PCI_DMA_FROMDEVICE);
96838a40 1537
e4eff729
MC		 1538 ret_val = e1000_check_lbtest_frame(
1539 rxdr->buffer_info[l].skb,
1540 1024);
96838a40 1541 if (!ret_val)
e4eff729 1542 good_cnt++;
96838a40
JB		 1543 if (unlikely(++l == rxdr->count)) l = 0;
1544 /* time + 20 msecs (200 msecs on 2.4) is more than
1545 * enough time to complete the receives, if it's
e4eff729
MC		 1546 * exceeded, break and error off
1547 */
1548 } while (good_cnt < 64 && jiffies < (time + 20));
96838a40 1549 if (good_cnt != 64) {
e4eff729 1550 ret_val = 13; /* ret_val is the same as mis-compare */
96838a40 1551 break;
e4eff729 1552 }
96838a40 1553 if (jiffies >= (time + 2)) {
e4eff729
MC		 1554 ret_val = 14; /* error code for time out error */
1555 break;
1556 }
1557 } /* end loop count loop */
1da177e4
LT		 1558 return ret_val;
1559}
1560
64798845 1561static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
1da177e4 1562{
1dc32918
JP		 1563 struct e1000_hw *hw = &adapter->hw;
1564
57128197
JK		 1565 /* PHY loopback cannot be performed if SoL/IDER
1566 * sessions are active */
1dc32918 1567 if (e1000_check_phy_reset_block(hw)) {
57128197
JK		 1568 DPRINTK(DRV, ERR, "Cannot do PHY loopback test "
1569 "when SoL/IDER is active.\n");
1570 *data = 0;
1571 goto out;
1572 }
1573
c7be73bc
JP		 1574 *data = e1000_setup_desc_rings(adapter);
1575 if (*data)
57128197 1576 goto out;
c7be73bc
JP		 1577 *data = e1000_setup_loopback_test(adapter);
1578 if (*data)
57128197 1579 goto err_loopback;
1da177e4
LT		 1580 *data = e1000_run_loopback_test(adapter);
1581 e1000_loopback_cleanup(adapter);
57128197 1582
1da177e4 1583err_loopback:
57128197
JK		 1584 e1000_free_desc_rings(adapter);
1585out:
1da177e4
LT		 1586 return *data;
1587}
1588
64798845 1589static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
1da177e4 1590{
1dc32918 1591 struct e1000_hw *hw = &adapter->hw;
1da177e4 1592 *data = 0;
1dc32918 1593 if (hw->media_type == e1000_media_type_internal_serdes) {
1da177e4 1594 int i = 0;
1dc32918 1595 hw->serdes_link_down = true;
1da177e4 1596
2648345f
MC		 1597 /* On some blade server designs, link establishment
1598 * could take as long as 2-3 minutes */
1da177e4 1599 do {
1dc32918
JP		 1600 e1000_check_for_link(hw);
1601 if (!hw->serdes_link_down)
1da177e4 1602 return *data;
f8ec4733 1603 msleep(20);
1da177e4
LT		 1604 } while (i++ < 3750);
1605
2648345f 1606 *data = 1;
1da177e4 1607 } else {
1dc32918
JP		 1608 e1000_check_for_link(hw);
1609 if (hw->autoneg) /* if auto_neg is set wait for it */
f8ec4733 1610 msleep(4000);
1da177e4 1611
1dc32918 1612 if (!(er32(STATUS) & E1000_STATUS_LU)) {
1da177e4
LT		 1613 *data = 1;
1614 }
1615 }
1616 return *data;
1617}
1618
64798845 1619static int e1000_get_sset_count(struct net_device *netdev, int sset)
1da177e4 1620{
b9f2c044
JG		 1621 switch (sset) {
1622 case ETH_SS_TEST:
1623 return E1000_TEST_LEN;
1624 case ETH_SS_STATS:
1625 return E1000_STATS_LEN;
1626 default:
1627 return -EOPNOTSUPP;
1628 }
1da177e4
LT		 1629}
1630
64798845
JP		 1631static void e1000_diag_test(struct net_device *netdev,
1632 struct ethtool_test *eth_test, u64 *data)
1da177e4 1633{
60490fe0 1634 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 1635 struct e1000_hw *hw = &adapter->hw;
c3033b01 1636 bool if_running = netif_running(netdev);
1da177e4 1637
1314bbf3 1638 set_bit(__E1000_TESTING, &adapter->flags);
96838a40 1639 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1da177e4
LT		 1640 /* Offline tests */
1641
1642 /* save speed, duplex, autoneg settings */
1dc32918
JP		 1643 u16 autoneg_advertised = hw->autoneg_advertised;
1644 u8 forced_speed_duplex = hw->forced_speed_duplex;
1645 u8 autoneg = hw->autoneg;
1da177e4 1646
d658266e
JB		 1647 DPRINTK(HW, INFO, "offline testing starting\n");
1648
1da177e4
LT		 1649 /* Link test performed before hardware reset so autoneg doesn't
1650 * interfere with test result */
96838a40 1651 if (e1000_link_test(adapter, &data[4]))
1da177e4
LT		 1652 eth_test->flags |= ETH_TEST_FL_FAILED;
1653
96838a40 1654 if (if_running)
2db10a08
AK		 1655 /* indicate we're in test mode */
1656 dev_close(netdev);
1da177e4
LT		 1657 else
1658 e1000_reset(adapter);
1659
96838a40 1660 if (e1000_reg_test(adapter, &data[0]))
1da177e4
LT		 1661 eth_test->flags |= ETH_TEST_FL_FAILED;
1662
1663 e1000_reset(adapter);
96838a40 1664 if (e1000_eeprom_test(adapter, &data[1]))
1da177e4
LT		 1665 eth_test->flags |= ETH_TEST_FL_FAILED;
1666
1667 e1000_reset(adapter);
96838a40 1668 if (e1000_intr_test(adapter, &data[2]))
1da177e4
LT		 1669 eth_test->flags |= ETH_TEST_FL_FAILED;
1670
1671 e1000_reset(adapter);
d658266e
JB		 1672 /* make sure the phy is powered up */
1673 e1000_power_up_phy(adapter);
96838a40 1674 if (e1000_loopback_test(adapter, &data[3]))
1da177e4
LT		 1675 eth_test->flags |= ETH_TEST_FL_FAILED;
1676
1677 /* restore speed, duplex, autoneg settings */
1dc32918
JP		 1678 hw->autoneg_advertised = autoneg_advertised;
1679 hw->forced_speed_duplex = forced_speed_duplex;
1680 hw->autoneg = autoneg;
1da177e4
LT		 1681
1682 e1000_reset(adapter);
1314bbf3 1683 clear_bit(__E1000_TESTING, &adapter->flags);
96838a40 1684 if (if_running)
2db10a08 1685 dev_open(netdev);
1da177e4 1686 } else {
d658266e 1687 DPRINTK(HW, INFO, "online testing starting\n");
1da177e4 1688 /* Online tests */
96838a40 1689 if (e1000_link_test(adapter, &data[4]))
1da177e4
LT		 1690 eth_test->flags |= ETH_TEST_FL_FAILED;
1691
90fb5135 1692 /* Online tests aren't run; pass by default */
1da177e4
LT		 1693 data[0] = 0;
1694 data[1] = 0;
1695 data[2] = 0;
1696 data[3] = 0;
2db10a08 1697
1314bbf3 1698 clear_bit(__E1000_TESTING, &adapter->flags);
1da177e4 1699 }
352c9f85 1700 msleep_interruptible(4 * 1000);
1da177e4
LT		 1701}
1702
64798845
JP		 1703static int e1000_wol_exclusion(struct e1000_adapter *adapter,
1704 struct ethtool_wolinfo *wol)
1da177e4 1705{
1da177e4 1706 struct e1000_hw *hw = &adapter->hw;
120cd576 1707 int retval = 1; /* fail by default */
1da177e4 1708
120cd576 1709 switch (hw->device_id) {
dc1f71f6 1710 case E1000_DEV_ID_82542:
1da177e4
LT		 1711 case E1000_DEV_ID_82543GC_FIBER:
1712 case E1000_DEV_ID_82543GC_COPPER:
1713 case E1000_DEV_ID_82544EI_FIBER:
1714 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1715 case E1000_DEV_ID_82545EM_FIBER:
1716 case E1000_DEV_ID_82545EM_COPPER:
84916829 1717 case E1000_DEV_ID_82546GB_QUAD_COPPER:
120cd576 1718 case E1000_DEV_ID_82546GB_PCIE:
ce57a02c 1719 case E1000_DEV_ID_82571EB_SERDES_QUAD:
120cd576 1720 /* these don't support WoL at all */
1da177e4 1721 wol->supported = 0;
120cd576 1722 break;
1da177e4
LT		 1723 case E1000_DEV_ID_82546EB_FIBER:
1724 case E1000_DEV_ID_82546GB_FIBER:
b7ee49db 1725 case E1000_DEV_ID_82571EB_FIBER:
120cd576
JB		 1726 case E1000_DEV_ID_82571EB_SERDES:
1727 case E1000_DEV_ID_82571EB_COPPER:
1728 /* Wake events not supported on port B */
1dc32918 1729 if (er32(STATUS) & E1000_STATUS_FUNC_1) {
1da177e4 1730 wol->supported = 0;
120cd576 1731 break;
1da177e4 1732 }
120cd576
JB		 1733 /* return success for non excluded adapter ports */
1734 retval = 0;
1735 break;
5881cde8 1736 case E1000_DEV_ID_82571EB_QUAD_COPPER:
ce57a02c 1737 case E1000_DEV_ID_82571EB_QUAD_FIBER:
fc2307d0 1738 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
f4ec7f98 1739 case E1000_DEV_ID_82571PT_QUAD_COPPER:
120cd576
JB		 1740 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1741 /* quad port adapters only support WoL on port A */
1742 if (!adapter->quad_port_a) {
1743 wol->supported = 0;
1744 break;
1745 }
1746 /* return success for non excluded adapter ports */
1747 retval = 0;
1748 break;
1da177e4 1749 default:
120cd576
JB		 1750 /* dual port cards only support WoL on port A from now on
1751 * unless it was enabled in the eeprom for port B
1752 * so exclude FUNC_1 ports from having WoL enabled */
1dc32918 1753 if (er32(STATUS) & E1000_STATUS_FUNC_1 &&
120cd576
JB		 1754 !adapter->eeprom_wol) {
1755 wol->supported = 0;
1756 break;
1757 }
84916829 1758
120cd576
JB		 1759 retval = 0;
1760 }
1761
1762 return retval;
1763}
1764
64798845
JP		 1765static void e1000_get_wol(struct net_device *netdev,
1766 struct ethtool_wolinfo *wol)
120cd576
JB		 1767{
1768 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 1769 struct e1000_hw *hw = &adapter->hw;
120cd576
JB		 1770
1771 wol->supported = WAKE_UCAST | WAKE_MCAST |
1772 WAKE_BCAST | WAKE_MAGIC;
1773 wol->wolopts = 0;
1774
1775 /* this function will set ->supported = 0 and return 1 if wol is not
1776 * supported by this hardware */
de126489
RW		 1777 if (e1000_wol_exclusion(adapter, wol) ||
1778 !device_can_wakeup(&adapter->pdev->dev))
1da177e4 1779 return;
120cd576
JB		 1780
1781 /* apply any specific unsupported masks here */
1dc32918 1782 switch (hw->device_id) {
120cd576
JB		 1783 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1784 /* KSP3 does not suppport UCAST wake-ups */
1785 wol->supported &= ~WAKE_UCAST;
1786
1787 if (adapter->wol & E1000_WUFC_EX)
1788 DPRINTK(DRV, ERR, "Interface does not support "
1789 "directed (unicast) frame wake-up packets\n");
1790 break;
1791 default:
1792 break;
1da177e4 1793 }
120cd576
JB		 1794
1795 if (adapter->wol & E1000_WUFC_EX)
1796 wol->wolopts |= WAKE_UCAST;
1797 if (adapter->wol & E1000_WUFC_MC)
1798 wol->wolopts |= WAKE_MCAST;
1799 if (adapter->wol & E1000_WUFC_BC)
1800 wol->wolopts |= WAKE_BCAST;
1801 if (adapter->wol & E1000_WUFC_MAG)
1802 wol->wolopts |= WAKE_MAGIC;
1803
1804 return;
1da177e4
LT		 1805}
1806
64798845 1807static int e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1da177e4 1808{
60490fe0 1809 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1810 struct e1000_hw *hw = &adapter->hw;
1811
120cd576
JB		 1812 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1813 return -EOPNOTSUPP;
1814
de126489
RW		 1815 if (e1000_wol_exclusion(adapter, wol) ||
1816 !device_can_wakeup(&adapter->pdev->dev))
1da177e4
LT		 1817 return wol->wolopts ? -EOPNOTSUPP : 0;
1818
120cd576 1819 switch (hw->device_id) {
84916829 1820 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
84916829
JK		 1821 if (wol->wolopts & WAKE_UCAST) {
1822 DPRINTK(DRV, ERR, "Interface does not support "
1823 "directed (unicast) frame wake-up packets\n");
1824 return -EOPNOTSUPP;
1825 }
120cd576 1826 break;
1da177e4 1827 default:
120cd576 1828 break;
1da177e4
LT		 1829 }
1830
120cd576
JB		 1831 /* these settings will always override what we currently have */
1832 adapter->wol = 0;
1833
1834 if (wol->wolopts & WAKE_UCAST)
1835 adapter->wol |= E1000_WUFC_EX;
1836 if (wol->wolopts & WAKE_MCAST)
1837 adapter->wol |= E1000_WUFC_MC;
1838 if (wol->wolopts & WAKE_BCAST)
1839 adapter->wol |= E1000_WUFC_BC;
1840 if (wol->wolopts & WAKE_MAGIC)
1841 adapter->wol |= E1000_WUFC_MAG;
1842
de126489
RW		 1843 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1844
1da177e4
LT		 1845 return 0;
1846}
1847
1848/* toggle LED 4 times per second = 2 "blinks" per second */
1849#define E1000_ID_INTERVAL (HZ/4)
1850
1851/* bit defines for adapter->led_status */
1852#define E1000_LED_ON 0
1853
64798845 1854static void e1000_led_blink_callback(unsigned long data)
1da177e4
LT		 1855{
1856 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1dc32918 1857 struct e1000_hw *hw = &adapter->hw;
1da177e4 1858
96838a40 1859 if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
1dc32918 1860 e1000_led_off(hw);
1da177e4 1861 else
1dc32918 1862 e1000_led_on(hw);
1da177e4
LT		 1863
1864 mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
1865}
1866
64798845 1867static int e1000_phys_id(struct net_device *netdev, u32 data)
1da177e4 1868{
60490fe0 1869 struct e1000_adapter *adapter = netdev_priv(netdev);
1dc32918 1870 struct e1000_hw *hw = &adapter->hw;
1da177e4 1871
abec42a4
SH		 1872 if (!data)
1873 data = INT_MAX;
1da177e4 1874
1dc32918 1875 if (hw->mac_type < e1000_82571) {
96838a40 1876 if (!adapter->blink_timer.function) {
d439d4b7
MC		 1877 init_timer(&adapter->blink_timer);
1878 adapter->blink_timer.function = e1000_led_blink_callback;
e982f17c 1879 adapter->blink_timer.data = (unsigned long)adapter;
d439d4b7 1880 }
1dc32918 1881 e1000_setup_led(hw);
d439d4b7
MC		 1882 mod_timer(&adapter->blink_timer, jiffies);
1883 msleep_interruptible(data * 1000);
1884 del_timer_sync(&adapter->blink_timer);
1dc32918 1885 } else if (hw->phy_type == e1000_phy_ife) {
cd94dd0b
AK		 1886 if (!adapter->blink_timer.function) {
1887 init_timer(&adapter->blink_timer);
1888 adapter->blink_timer.function = e1000_led_blink_callback;
e982f17c 1889 adapter->blink_timer.data = (unsigned long)adapter;
cd94dd0b
AK		 1890 }
1891 mod_timer(&adapter->blink_timer, jiffies);
d8c2bd3d 1892 msleep_interruptible(data * 1000);
cd94dd0b
AK		 1893 del_timer_sync(&adapter->blink_timer);
1894 e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
d8c2bd3d 1895 } else {
1dc32918 1896 e1000_blink_led_start(hw);
d439d4b7 1897 msleep_interruptible(data * 1000);
1da177e4
LT		 1898 }
1899
1dc32918 1900 e1000_led_off(hw);
1da177e4 1901 clear_bit(E1000_LED_ON, &adapter->led_status);
1dc32918 1902 e1000_cleanup_led(hw);
1da177e4
LT		 1903
1904 return 0;
1905}
1906
64798845 1907static int e1000_nway_reset(struct net_device *netdev)
1da177e4 1908{
60490fe0 1909 struct e1000_adapter *adapter = netdev_priv(netdev);
2db10a08
AK		 1910 if (netif_running(netdev))
1911 e1000_reinit_locked(adapter);
1da177e4
LT		 1912 return 0;
1913}
1914
64798845
JP		 1915static void e1000_get_ethtool_stats(struct net_device *netdev,
1916 struct ethtool_stats *stats, u64 *data)
1da177e4 1917{
60490fe0 1918 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1919 int i;
1920
1921 e1000_update_stats(adapter);
7bfa4816
JK		 1922 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1923 char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
1924 data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
406874a7 1925 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1da177e4 1926 }
7bfa4816 1927/* BUG_ON(i != E1000_STATS_LEN); */
1da177e4
LT		 1928}
1929
64798845
JP		 1930static void e1000_get_strings(struct net_device *netdev, u32 stringset,
1931 u8 *data)
1da177e4 1932{
406874a7 1933 u8 *p = data;
1da177e4
LT		 1934 int i;
1935
96838a40 1936 switch (stringset) {
1da177e4 1937 case ETH_SS_TEST:
96838a40 1938 memcpy(data, *e1000_gstrings_test,
c32bc6e9 1939 sizeof(e1000_gstrings_test));
1da177e4
LT		 1940 break;
1941 case ETH_SS_STATS:
7bfa4816
JK		 1942 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1943 memcpy(p, e1000_gstrings_stats[i].stat_string,
1944 ETH_GSTRING_LEN);
1945 p += ETH_GSTRING_LEN;
1946 }
7bfa4816 1947/* BUG_ON(p - data != E1000_STATS_LEN * ETH_GSTRING_LEN); */
1da177e4
LT		 1948 break;
1949 }
1950}
1951
7282d491 1952static const struct ethtool_ops e1000_ethtool_ops = {
1da177e4
LT		 1953 .get_settings = e1000_get_settings,
1954 .set_settings = e1000_set_settings,
1955 .get_drvinfo = e1000_get_drvinfo,
1956 .get_regs_len = e1000_get_regs_len,
1957 .get_regs = e1000_get_regs,
1958 .get_wol = e1000_get_wol,
1959 .set_wol = e1000_set_wol,
8fc897b0
AK		 1960 .get_msglevel = e1000_get_msglevel,
1961 .set_msglevel = e1000_set_msglevel,
1da177e4
LT		 1962 .nway_reset = e1000_nway_reset,
1963 .get_link = ethtool_op_get_link,
1964 .get_eeprom_len = e1000_get_eeprom_len,
1965 .get_eeprom = e1000_get_eeprom,
1966 .set_eeprom = e1000_set_eeprom,
1967 .get_ringparam = e1000_get_ringparam,
1968 .set_ringparam = e1000_set_ringparam,
8fc897b0
AK		 1969 .get_pauseparam = e1000_get_pauseparam,
1970 .set_pauseparam = e1000_set_pauseparam,
1971 .get_rx_csum = e1000_get_rx_csum,
1972 .set_rx_csum = e1000_set_rx_csum,
1973 .get_tx_csum = e1000_get_tx_csum,
1974 .set_tx_csum = e1000_set_tx_csum,
8fc897b0 1975 .set_sg = ethtool_op_set_sg,
8fc897b0 1976 .set_tso = e1000_set_tso,
1da177e4
LT		 1977 .self_test = e1000_diag_test,
1978 .get_strings = e1000_get_strings,
1979 .phys_id = e1000_phys_id,
1da177e4 1980 .get_ethtool_stats = e1000_get_ethtool_stats,
b9f2c044 1981 .get_sset_count = e1000_get_sset_count,
1da177e4
LT		 1982};
1983
1984void e1000_set_ethtool_ops(struct net_device *netdev)
1985{
1986 SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
1987}
Linux kernel - Deliverables
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