Commit | Line | Data |
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1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
0abb6eb1 AK |
3 | Intel PRO/1000 Linux driver |
4 | Copyright(c) 1999 - 2006 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
1da177e4 | 13 | more details. |
0abb6eb1 | 14 | |
1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
1da177e4 LT |
22 | Contact Information: |
23 | Linux NICS <linux.nics@intel.com> | |
3d41e30a | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* e1000_hw.c | |
30 | * Shared functions for accessing and configuring the MAC | |
31 | */ | |
32 | ||
8fc897b0 | 33 | |
1da177e4 LT |
34 | #include "e1000_hw.h" |
35 | ||
35574764 NN |
36 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); |
37 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); | |
38 | static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); | |
39 | static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); | |
40 | static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); | |
41 | static void e1000_release_software_semaphore(struct e1000_hw *hw); | |
42 | ||
43 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); | |
44 | static int32_t e1000_check_downshift(struct e1000_hw *hw); | |
45 | static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); | |
46 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); | |
47 | static void e1000_clear_vfta(struct e1000_hw *hw); | |
48 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); | |
49 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); | |
50 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); | |
51 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); | |
52 | static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); | |
53 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); | |
54 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); | |
55 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | |
56 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
57 | static int32_t e1000_get_software_flag(struct e1000_hw *hw); | |
58 | static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); | |
59 | static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); | |
60 | static int32_t e1000_id_led_init(struct e1000_hw *hw); | |
61 | static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); | |
62 | static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); | |
63 | static void e1000_init_rx_addrs(struct e1000_hw *hw); | |
09ae3e88 | 64 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw); |
35574764 NN |
65 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
66 | static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); | |
67 | static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); | |
68 | static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); | |
69 | static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); | |
70 | static int32_t e1000_mng_write_commit(struct e1000_hw *hw); | |
71 | static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | |
72 | static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | |
73 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | |
74 | static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | |
75 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | |
76 | static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | |
77 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | |
78 | static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); | |
79 | static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); | |
80 | static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); | |
81 | static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); | |
82 | static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); | |
83 | static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); | |
84 | static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | |
85 | static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | |
86 | static void e1000_release_software_flag(struct e1000_hw *hw); | |
87 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | |
88 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); | |
89 | static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); | |
90 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); | |
91 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); | |
92 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); | |
1da177e4 LT |
93 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
94 | static void e1000_phy_init_script(struct e1000_hw *hw); | |
95 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); | |
96 | static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); | |
97 | static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); | |
98 | static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
99 | static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); | |
100 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
101 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
102 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, | |
103 | uint16_t count); | |
104 | static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); | |
105 | static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); | |
106 | static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, | |
107 | uint16_t words, uint16_t *data); | |
108 | static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, | |
109 | uint16_t offset, uint16_t words, | |
110 | uint16_t *data); | |
111 | static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); | |
112 | static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
113 | static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
114 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, | |
115 | uint16_t count); | |
116 | static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, | |
117 | uint16_t phy_data); | |
118 | static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, | |
119 | uint16_t *phy_data); | |
120 | static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); | |
121 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); | |
122 | static void e1000_release_eeprom(struct e1000_hw *hw); | |
123 | static void e1000_standby_eeprom(struct e1000_hw *hw); | |
1da177e4 LT |
124 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
125 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); | |
126 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); | |
2d7edb92 MC |
127 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
128 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); | |
cd94dd0b AK |
129 | static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, |
130 | uint16_t duplex); | |
6418ecc6 | 131 | static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
1da177e4 LT |
132 | |
133 | /* IGP cable length table */ | |
134 | static const | |
135 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | |
136 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, | |
137 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, | |
138 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, | |
139 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, | |
140 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, | |
141 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, | |
142 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | |
143 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | |
144 | ||
2d7edb92 MC |
145 | static const |
146 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | |
868d5309 MC |
147 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
148 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
149 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
150 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
151 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
152 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
153 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
154 | 104, 109, 114, 118, 121, 124}; | |
2d7edb92 | 155 | |
1da177e4 LT |
156 | /****************************************************************************** |
157 | * Set the phy type member in the hw struct. | |
158 | * | |
159 | * hw - Struct containing variables accessed by shared code | |
160 | *****************************************************************************/ | |
35574764 | 161 | static int32_t |
1da177e4 LT |
162 | e1000_set_phy_type(struct e1000_hw *hw) |
163 | { | |
164 | DEBUGFUNC("e1000_set_phy_type"); | |
165 | ||
8fc897b0 | 166 | if (hw->mac_type == e1000_undefined) |
2d7edb92 MC |
167 | return -E1000_ERR_PHY_TYPE; |
168 | ||
8fc897b0 | 169 | switch (hw->phy_id) { |
1da177e4 LT |
170 | case M88E1000_E_PHY_ID: |
171 | case M88E1000_I_PHY_ID: | |
172 | case M88E1011_I_PHY_ID: | |
2d7edb92 | 173 | case M88E1111_I_PHY_ID: |
1da177e4 LT |
174 | hw->phy_type = e1000_phy_m88; |
175 | break; | |
176 | case IGP01E1000_I_PHY_ID: | |
8fc897b0 AK |
177 | if (hw->mac_type == e1000_82541 || |
178 | hw->mac_type == e1000_82541_rev_2 || | |
179 | hw->mac_type == e1000_82547 || | |
180 | hw->mac_type == e1000_82547_rev_2) { | |
1da177e4 LT |
181 | hw->phy_type = e1000_phy_igp; |
182 | break; | |
183 | } | |
cd94dd0b AK |
184 | case IGP03E1000_E_PHY_ID: |
185 | hw->phy_type = e1000_phy_igp_3; | |
186 | break; | |
187 | case IFE_E_PHY_ID: | |
188 | case IFE_PLUS_E_PHY_ID: | |
189 | case IFE_C_E_PHY_ID: | |
190 | hw->phy_type = e1000_phy_ife; | |
191 | break; | |
6418ecc6 JK |
192 | case GG82563_E_PHY_ID: |
193 | if (hw->mac_type == e1000_80003es2lan) { | |
194 | hw->phy_type = e1000_phy_gg82563; | |
195 | break; | |
196 | } | |
1da177e4 LT |
197 | /* Fall Through */ |
198 | default: | |
199 | /* Should never have loaded on this device */ | |
200 | hw->phy_type = e1000_phy_undefined; | |
201 | return -E1000_ERR_PHY_TYPE; | |
202 | } | |
203 | ||
204 | return E1000_SUCCESS; | |
205 | } | |
206 | ||
207 | /****************************************************************************** | |
208 | * IGP phy init script - initializes the GbE PHY | |
209 | * | |
210 | * hw - Struct containing variables accessed by shared code | |
211 | *****************************************************************************/ | |
212 | static void | |
213 | e1000_phy_init_script(struct e1000_hw *hw) | |
214 | { | |
215 | uint32_t ret_val; | |
216 | uint16_t phy_saved_data; | |
217 | ||
218 | DEBUGFUNC("e1000_phy_init_script"); | |
219 | ||
8fc897b0 | 220 | if (hw->phy_init_script) { |
f8ec4733 | 221 | msleep(20); |
1da177e4 LT |
222 | |
223 | /* Save off the current value of register 0x2F5B to be restored at | |
224 | * the end of this routine. */ | |
225 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
226 | ||
227 | /* Disabled the PHY transmitter */ | |
228 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
229 | ||
f8ec4733 | 230 | msleep(20); |
1da177e4 LT |
231 | |
232 | e1000_write_phy_reg(hw,0x0000,0x0140); | |
233 | ||
f8ec4733 | 234 | msleep(5); |
1da177e4 | 235 | |
8fc897b0 | 236 | switch (hw->mac_type) { |
1da177e4 LT |
237 | case e1000_82541: |
238 | case e1000_82547: | |
239 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
240 | ||
241 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
242 | ||
243 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
244 | ||
245 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
246 | ||
247 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
248 | ||
249 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
250 | ||
251 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
252 | ||
253 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
254 | ||
255 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
256 | break; | |
257 | ||
258 | case e1000_82541_rev_2: | |
259 | case e1000_82547_rev_2: | |
260 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
261 | break; | |
262 | default: | |
263 | break; | |
264 | } | |
265 | ||
266 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
267 | ||
f8ec4733 | 268 | msleep(20); |
1da177e4 LT |
269 | |
270 | /* Now enable the transmitter */ | |
271 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
272 | ||
8fc897b0 | 273 | if (hw->mac_type == e1000_82547) { |
1da177e4 LT |
274 | uint16_t fused, fine, coarse; |
275 | ||
276 | /* Move to analog registers page */ | |
277 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
278 | ||
8fc897b0 | 279 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
1da177e4 LT |
280 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
281 | ||
282 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
283 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
284 | ||
8fc897b0 | 285 | if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
1da177e4 LT |
286 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
287 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
8fc897b0 | 288 | } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
1da177e4 LT |
289 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
290 | ||
291 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
292 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
293 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
294 | ||
295 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
296 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, | |
297 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
298 | } | |
299 | } | |
300 | } | |
301 | } | |
302 | ||
303 | /****************************************************************************** | |
304 | * Set the mac type member in the hw struct. | |
305 | * | |
306 | * hw - Struct containing variables accessed by shared code | |
307 | *****************************************************************************/ | |
308 | int32_t | |
309 | e1000_set_mac_type(struct e1000_hw *hw) | |
310 | { | |
bd2371eb JG |
311 | DEBUGFUNC("e1000_set_mac_type"); |
312 | ||
313 | switch (hw->device_id) { | |
314 | case E1000_DEV_ID_82542: | |
315 | switch (hw->revision_id) { | |
316 | case E1000_82542_2_0_REV_ID: | |
317 | hw->mac_type = e1000_82542_rev2_0; | |
318 | break; | |
319 | case E1000_82542_2_1_REV_ID: | |
320 | hw->mac_type = e1000_82542_rev2_1; | |
321 | break; | |
322 | default: | |
323 | /* Invalid 82542 revision ID */ | |
324 | return -E1000_ERR_MAC_TYPE; | |
325 | } | |
326 | break; | |
327 | case E1000_DEV_ID_82543GC_FIBER: | |
328 | case E1000_DEV_ID_82543GC_COPPER: | |
329 | hw->mac_type = e1000_82543; | |
330 | break; | |
331 | case E1000_DEV_ID_82544EI_COPPER: | |
332 | case E1000_DEV_ID_82544EI_FIBER: | |
333 | case E1000_DEV_ID_82544GC_COPPER: | |
334 | case E1000_DEV_ID_82544GC_LOM: | |
335 | hw->mac_type = e1000_82544; | |
336 | break; | |
337 | case E1000_DEV_ID_82540EM: | |
338 | case E1000_DEV_ID_82540EM_LOM: | |
339 | case E1000_DEV_ID_82540EP: | |
340 | case E1000_DEV_ID_82540EP_LOM: | |
341 | case E1000_DEV_ID_82540EP_LP: | |
342 | hw->mac_type = e1000_82540; | |
343 | break; | |
344 | case E1000_DEV_ID_82545EM_COPPER: | |
345 | case E1000_DEV_ID_82545EM_FIBER: | |
346 | hw->mac_type = e1000_82545; | |
347 | break; | |
348 | case E1000_DEV_ID_82545GM_COPPER: | |
349 | case E1000_DEV_ID_82545GM_FIBER: | |
350 | case E1000_DEV_ID_82545GM_SERDES: | |
351 | hw->mac_type = e1000_82545_rev_3; | |
352 | break; | |
353 | case E1000_DEV_ID_82546EB_COPPER: | |
354 | case E1000_DEV_ID_82546EB_FIBER: | |
355 | case E1000_DEV_ID_82546EB_QUAD_COPPER: | |
356 | hw->mac_type = e1000_82546; | |
357 | break; | |
358 | case E1000_DEV_ID_82546GB_COPPER: | |
359 | case E1000_DEV_ID_82546GB_FIBER: | |
360 | case E1000_DEV_ID_82546GB_SERDES: | |
361 | case E1000_DEV_ID_82546GB_PCIE: | |
362 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | |
363 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | |
364 | hw->mac_type = e1000_82546_rev_3; | |
365 | break; | |
366 | case E1000_DEV_ID_82541EI: | |
367 | case E1000_DEV_ID_82541EI_MOBILE: | |
368 | case E1000_DEV_ID_82541ER_LOM: | |
369 | hw->mac_type = e1000_82541; | |
370 | break; | |
371 | case E1000_DEV_ID_82541ER: | |
372 | case E1000_DEV_ID_82541GI: | |
373 | case E1000_DEV_ID_82541GI_LF: | |
374 | case E1000_DEV_ID_82541GI_MOBILE: | |
375 | hw->mac_type = e1000_82541_rev_2; | |
376 | break; | |
377 | case E1000_DEV_ID_82547EI: | |
378 | case E1000_DEV_ID_82547EI_MOBILE: | |
379 | hw->mac_type = e1000_82547; | |
380 | break; | |
381 | case E1000_DEV_ID_82547GI: | |
382 | hw->mac_type = e1000_82547_rev_2; | |
383 | break; | |
384 | case E1000_DEV_ID_82571EB_COPPER: | |
385 | case E1000_DEV_ID_82571EB_FIBER: | |
386 | case E1000_DEV_ID_82571EB_SERDES: | |
387 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
388 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | |
389 | hw->mac_type = e1000_82571; | |
390 | break; | |
391 | case E1000_DEV_ID_82572EI_COPPER: | |
392 | case E1000_DEV_ID_82572EI_FIBER: | |
393 | case E1000_DEV_ID_82572EI_SERDES: | |
394 | case E1000_DEV_ID_82572EI: | |
395 | hw->mac_type = e1000_82572; | |
396 | break; | |
397 | case E1000_DEV_ID_82573E: | |
398 | case E1000_DEV_ID_82573E_IAMT: | |
399 | case E1000_DEV_ID_82573L: | |
400 | hw->mac_type = e1000_82573; | |
401 | break; | |
402 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: | |
403 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: | |
404 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: | |
405 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
406 | hw->mac_type = e1000_80003es2lan; | |
407 | break; | |
408 | case E1000_DEV_ID_ICH8_IGP_M_AMT: | |
409 | case E1000_DEV_ID_ICH8_IGP_AMT: | |
410 | case E1000_DEV_ID_ICH8_IGP_C: | |
411 | case E1000_DEV_ID_ICH8_IFE: | |
412 | case E1000_DEV_ID_ICH8_IFE_GT: | |
413 | case E1000_DEV_ID_ICH8_IFE_G: | |
414 | case E1000_DEV_ID_ICH8_IGP_M: | |
415 | hw->mac_type = e1000_ich8lan; | |
416 | break; | |
417 | default: | |
418 | /* Should never have loaded on this device */ | |
419 | return -E1000_ERR_MAC_TYPE; | |
420 | } | |
421 | ||
422 | switch (hw->mac_type) { | |
423 | case e1000_ich8lan: | |
424 | hw->swfwhw_semaphore_present = TRUE; | |
425 | hw->asf_firmware_present = TRUE; | |
426 | break; | |
427 | case e1000_80003es2lan: | |
428 | hw->swfw_sync_present = TRUE; | |
429 | /* fall through */ | |
430 | case e1000_82571: | |
431 | case e1000_82572: | |
432 | case e1000_82573: | |
433 | hw->eeprom_semaphore_present = TRUE; | |
434 | /* fall through */ | |
435 | case e1000_82541: | |
436 | case e1000_82547: | |
437 | case e1000_82541_rev_2: | |
438 | case e1000_82547_rev_2: | |
439 | hw->asf_firmware_present = TRUE; | |
440 | break; | |
441 | default: | |
442 | break; | |
443 | } | |
444 | ||
167fb284 JG |
445 | /* The 82543 chip does not count tx_carrier_errors properly in |
446 | * FD mode | |
447 | */ | |
448 | if (hw->mac_type == e1000_82543) | |
449 | hw->bad_tx_carr_stats_fd = TRUE; | |
450 | ||
0fccd0e9 JG |
451 | /* capable of receiving management packets to the host */ |
452 | if (hw->mac_type >= e1000_82571) | |
453 | hw->has_manc2h = TRUE; | |
454 | ||
bb8e3311 JG |
455 | /* In rare occasions, ESB2 systems would end up started without |
456 | * the RX unit being turned on. | |
457 | */ | |
458 | if (hw->mac_type == e1000_80003es2lan) | |
459 | hw->rx_needs_kicking = TRUE; | |
460 | ||
bd2371eb | 461 | return E1000_SUCCESS; |
1da177e4 LT |
462 | } |
463 | ||
464 | /***************************************************************************** | |
465 | * Set media type and TBI compatibility. | |
466 | * | |
467 | * hw - Struct containing variables accessed by shared code | |
468 | * **************************************************************************/ | |
469 | void | |
470 | e1000_set_media_type(struct e1000_hw *hw) | |
471 | { | |
472 | uint32_t status; | |
473 | ||
474 | DEBUGFUNC("e1000_set_media_type"); | |
475 | ||
8fc897b0 | 476 | if (hw->mac_type != e1000_82543) { |
1da177e4 LT |
477 | /* tbi_compatibility is only valid on 82543 */ |
478 | hw->tbi_compatibility_en = FALSE; | |
479 | } | |
480 | ||
481 | switch (hw->device_id) { | |
482 | case E1000_DEV_ID_82545GM_SERDES: | |
483 | case E1000_DEV_ID_82546GB_SERDES: | |
868d5309 MC |
484 | case E1000_DEV_ID_82571EB_SERDES: |
485 | case E1000_DEV_ID_82572EI_SERDES: | |
6418ecc6 | 486 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
1da177e4 LT |
487 | hw->media_type = e1000_media_type_internal_serdes; |
488 | break; | |
489 | default: | |
3893d547 MC |
490 | switch (hw->mac_type) { |
491 | case e1000_82542_rev2_0: | |
492 | case e1000_82542_rev2_1: | |
493 | hw->media_type = e1000_media_type_fiber; | |
494 | break; | |
cd94dd0b | 495 | case e1000_ich8lan: |
3893d547 MC |
496 | case e1000_82573: |
497 | /* The STATUS_TBIMODE bit is reserved or reused for the this | |
498 | * device. | |
499 | */ | |
500 | hw->media_type = e1000_media_type_copper; | |
501 | break; | |
502 | default: | |
1da177e4 | 503 | status = E1000_READ_REG(hw, STATUS); |
3893d547 | 504 | if (status & E1000_STATUS_TBIMODE) { |
1da177e4 LT |
505 | hw->media_type = e1000_media_type_fiber; |
506 | /* tbi_compatibility not valid on fiber */ | |
507 | hw->tbi_compatibility_en = FALSE; | |
508 | } else { | |
509 | hw->media_type = e1000_media_type_copper; | |
510 | } | |
3893d547 | 511 | break; |
1da177e4 LT |
512 | } |
513 | } | |
514 | } | |
515 | ||
516 | /****************************************************************************** | |
517 | * Reset the transmit and receive units; mask and clear all interrupts. | |
518 | * | |
519 | * hw - Struct containing variables accessed by shared code | |
520 | *****************************************************************************/ | |
521 | int32_t | |
522 | e1000_reset_hw(struct e1000_hw *hw) | |
523 | { | |
524 | uint32_t ctrl; | |
525 | uint32_t ctrl_ext; | |
526 | uint32_t icr; | |
527 | uint32_t manc; | |
528 | uint32_t led_ctrl; | |
2d7edb92 MC |
529 | uint32_t timeout; |
530 | uint32_t extcnf_ctrl; | |
531 | int32_t ret_val; | |
1da177e4 LT |
532 | |
533 | DEBUGFUNC("e1000_reset_hw"); | |
534 | ||
535 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ | |
8fc897b0 | 536 | if (hw->mac_type == e1000_82542_rev2_0) { |
1da177e4 LT |
537 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
538 | e1000_pci_clear_mwi(hw); | |
539 | } | |
540 | ||
8fc897b0 | 541 | if (hw->bus_type == e1000_bus_type_pci_express) { |
2d7edb92 MC |
542 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
543 | * on the last TLP read/write transaction when MAC is reset. | |
544 | */ | |
8fc897b0 | 545 | if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
2d7edb92 MC |
546 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
547 | } | |
548 | } | |
549 | ||
1da177e4 LT |
550 | /* Clear interrupt mask to stop board from generating interrupts */ |
551 | DEBUGOUT("Masking off all interrupts\n"); | |
552 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
553 | ||
554 | /* Disable the Transmit and Receive units. Then delay to allow | |
555 | * any pending transactions to complete before we hit the MAC with | |
556 | * the global reset. | |
557 | */ | |
558 | E1000_WRITE_REG(hw, RCTL, 0); | |
559 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); | |
560 | E1000_WRITE_FLUSH(hw); | |
561 | ||
562 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
563 | hw->tbi_compatibility_on = FALSE; | |
564 | ||
565 | /* Delay to allow any outstanding PCI transactions to complete before | |
566 | * resetting the device | |
567 | */ | |
f8ec4733 | 568 | msleep(10); |
1da177e4 LT |
569 | |
570 | ctrl = E1000_READ_REG(hw, CTRL); | |
571 | ||
572 | /* Must reset the PHY before resetting the MAC */ | |
8fc897b0 | 573 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
2d7edb92 | 574 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
f8ec4733 | 575 | msleep(5); |
1da177e4 LT |
576 | } |
577 | ||
2d7edb92 MC |
578 | /* Must acquire the MDIO ownership before MAC reset. |
579 | * Ownership defaults to firmware after a reset. */ | |
8fc897b0 | 580 | if (hw->mac_type == e1000_82573) { |
2d7edb92 MC |
581 | timeout = 10; |
582 | ||
583 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
584 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
585 | ||
586 | do { | |
587 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | |
588 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
589 | ||
8fc897b0 | 590 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
2d7edb92 MC |
591 | break; |
592 | else | |
593 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
594 | ||
f8ec4733 | 595 | msleep(2); |
2d7edb92 | 596 | timeout--; |
8fc897b0 | 597 | } while (timeout); |
2d7edb92 MC |
598 | } |
599 | ||
cd94dd0b AK |
600 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
601 | if (hw->mac_type == e1000_ich8lan) { | |
602 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
603 | E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); | |
604 | /* Set Packet Buffer Size to 16k. */ | |
605 | E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); | |
606 | } | |
607 | ||
1da177e4 LT |
608 | /* Issue a global reset to the MAC. This will reset the chip's |
609 | * transmit, receive, DMA, and link units. It will not effect | |
610 | * the current PCI configuration. The global reset bit is self- | |
611 | * clearing, and should clear within a microsecond. | |
612 | */ | |
613 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
614 | ||
8fc897b0 | 615 | switch (hw->mac_type) { |
1da177e4 LT |
616 | case e1000_82544: |
617 | case e1000_82540: | |
618 | case e1000_82545: | |
619 | case e1000_82546: | |
620 | case e1000_82541: | |
621 | case e1000_82541_rev_2: | |
622 | /* These controllers can't ack the 64-bit write when issuing the | |
623 | * reset, so use IO-mapping as a workaround to issue the reset */ | |
624 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
625 | break; | |
626 | case e1000_82545_rev_3: | |
627 | case e1000_82546_rev_3: | |
628 | /* Reset is performed on a shadow of the control register */ | |
629 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); | |
630 | break; | |
cd94dd0b AK |
631 | case e1000_ich8lan: |
632 | if (!hw->phy_reset_disable && | |
633 | e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { | |
634 | /* e1000_ich8lan PHY HW reset requires MAC CORE reset | |
635 | * at the same time to make sure the interface between | |
636 | * MAC and the external PHY is reset. | |
637 | */ | |
638 | ctrl |= E1000_CTRL_PHY_RST; | |
639 | } | |
640 | ||
641 | e1000_get_software_flag(hw); | |
642 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
f8ec4733 | 643 | msleep(5); |
cd94dd0b | 644 | break; |
1da177e4 LT |
645 | default: |
646 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
647 | break; | |
648 | } | |
649 | ||
650 | /* After MAC reset, force reload of EEPROM to restore power-on settings to | |
651 | * device. Later controllers reload the EEPROM automatically, so just wait | |
652 | * for reload to complete. | |
653 | */ | |
8fc897b0 | 654 | switch (hw->mac_type) { |
1da177e4 LT |
655 | case e1000_82542_rev2_0: |
656 | case e1000_82542_rev2_1: | |
657 | case e1000_82543: | |
658 | case e1000_82544: | |
659 | /* Wait for reset to complete */ | |
660 | udelay(10); | |
661 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
662 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
663 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
664 | E1000_WRITE_FLUSH(hw); | |
665 | /* Wait for EEPROM reload */ | |
f8ec4733 | 666 | msleep(2); |
1da177e4 LT |
667 | break; |
668 | case e1000_82541: | |
669 | case e1000_82541_rev_2: | |
670 | case e1000_82547: | |
671 | case e1000_82547_rev_2: | |
672 | /* Wait for EEPROM reload */ | |
f8ec4733 | 673 | msleep(20); |
1da177e4 | 674 | break; |
2d7edb92 | 675 | case e1000_82573: |
fd803241 JK |
676 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
677 | udelay(10); | |
678 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
679 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
680 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
681 | E1000_WRITE_FLUSH(hw); | |
682 | } | |
2d7edb92 | 683 | /* fall through */ |
2a88c173 JK |
684 | default: |
685 | /* Auto read done will delay 5ms or poll based on mac type */ | |
2d7edb92 | 686 | ret_val = e1000_get_auto_rd_done(hw); |
8fc897b0 | 687 | if (ret_val) |
2d7edb92 MC |
688 | return ret_val; |
689 | break; | |
1da177e4 LT |
690 | } |
691 | ||
692 | /* Disable HW ARPs on ASF enabled adapters */ | |
8fc897b0 | 693 | if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
1da177e4 LT |
694 | manc = E1000_READ_REG(hw, MANC); |
695 | manc &= ~(E1000_MANC_ARP_EN); | |
696 | E1000_WRITE_REG(hw, MANC, manc); | |
697 | } | |
698 | ||
8fc897b0 | 699 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1da177e4 LT |
700 | e1000_phy_init_script(hw); |
701 | ||
702 | /* Configure activity LED after PHY reset */ | |
703 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
704 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
705 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
706 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
707 | } | |
708 | ||
709 | /* Clear interrupt mask to stop board from generating interrupts */ | |
710 | DEBUGOUT("Masking off all interrupts\n"); | |
711 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
712 | ||
713 | /* Clear any pending interrupt events. */ | |
714 | icr = E1000_READ_REG(hw, ICR); | |
715 | ||
716 | /* If MWI was previously enabled, reenable it. */ | |
8fc897b0 | 717 | if (hw->mac_type == e1000_82542_rev2_0) { |
f8ec4733 | 718 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
1da177e4 LT |
719 | e1000_pci_set_mwi(hw); |
720 | } | |
721 | ||
cd94dd0b AK |
722 | if (hw->mac_type == e1000_ich8lan) { |
723 | uint32_t kab = E1000_READ_REG(hw, KABGTXD); | |
724 | kab |= E1000_KABGTXD_BGSQLBIAS; | |
725 | E1000_WRITE_REG(hw, KABGTXD, kab); | |
726 | } | |
727 | ||
1da177e4 LT |
728 | return E1000_SUCCESS; |
729 | } | |
730 | ||
09ae3e88 JK |
731 | /****************************************************************************** |
732 | * | |
733 | * Initialize a number of hardware-dependent bits | |
734 | * | |
735 | * hw: Struct containing variables accessed by shared code | |
736 | * | |
737 | * This function contains hardware limitation workarounds for PCI-E adapters | |
738 | * | |
739 | *****************************************************************************/ | |
740 | static void | |
741 | e1000_initialize_hardware_bits(struct e1000_hw *hw) | |
742 | { | |
743 | if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { | |
744 | /* Settings common to all PCI-express silicon */ | |
745 | uint32_t reg_ctrl, reg_ctrl_ext; | |
746 | uint32_t reg_tarc0, reg_tarc1; | |
747 | uint32_t reg_tctl; | |
748 | uint32_t reg_txdctl, reg_txdctl1; | |
749 | ||
750 | /* link autonegotiation/sync workarounds */ | |
751 | reg_tarc0 = E1000_READ_REG(hw, TARC0); | |
752 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); | |
753 | ||
754 | /* Enable not-done TX descriptor counting */ | |
755 | reg_txdctl = E1000_READ_REG(hw, TXDCTL); | |
756 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; | |
757 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); | |
758 | reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); | |
759 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; | |
760 | E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); | |
761 | ||
762 | switch (hw->mac_type) { | |
763 | case e1000_82571: | |
764 | case e1000_82572: | |
765 | /* Clear PHY TX compatible mode bits */ | |
766 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
767 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); | |
768 | ||
769 | /* link autonegotiation/sync workarounds */ | |
770 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); | |
771 | ||
772 | /* TX ring control fixes */ | |
773 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); | |
774 | ||
775 | /* Multiple read bit is reversed polarity */ | |
776 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
777 | if (reg_tctl & E1000_TCTL_MULR) | |
778 | reg_tarc1 &= ~(1 << 28); | |
779 | else | |
780 | reg_tarc1 |= (1 << 28); | |
781 | ||
782 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
783 | break; | |
784 | case e1000_82573: | |
785 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
786 | reg_ctrl_ext &= ~(1 << 23); | |
787 | reg_ctrl_ext |= (1 << 22); | |
788 | ||
789 | /* TX byte count fix */ | |
790 | reg_ctrl = E1000_READ_REG(hw, CTRL); | |
791 | reg_ctrl &= ~(1 << 29); | |
792 | ||
793 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
794 | E1000_WRITE_REG(hw, CTRL, reg_ctrl); | |
795 | break; | |
796 | case e1000_80003es2lan: | |
797 | /* improve small packet performace for fiber/serdes */ | |
798 | if ((hw->media_type == e1000_media_type_fiber) || | |
799 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
800 | reg_tarc0 &= ~(1 << 20); | |
801 | } | |
802 | ||
803 | /* Multiple read bit is reversed polarity */ | |
804 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
805 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
806 | if (reg_tctl & E1000_TCTL_MULR) | |
807 | reg_tarc1 &= ~(1 << 28); | |
808 | else | |
809 | reg_tarc1 |= (1 << 28); | |
810 | ||
811 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
812 | break; | |
813 | case e1000_ich8lan: | |
814 | /* Reduce concurrent DMA requests to 3 from 4 */ | |
815 | if ((hw->revision_id < 3) || | |
816 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
817 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) | |
818 | reg_tarc0 |= ((1 << 29)|(1 << 28)); | |
819 | ||
820 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
821 | reg_ctrl_ext |= (1 << 22); | |
822 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
823 | ||
824 | /* workaround TX hang with TSO=on */ | |
825 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); | |
826 | ||
827 | /* Multiple read bit is reversed polarity */ | |
828 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
829 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
830 | if (reg_tctl & E1000_TCTL_MULR) | |
831 | reg_tarc1 &= ~(1 << 28); | |
832 | else | |
833 | reg_tarc1 |= (1 << 28); | |
834 | ||
835 | /* workaround TX hang with TSO=on */ | |
836 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); | |
837 | ||
838 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
839 | break; | |
840 | default: | |
841 | break; | |
842 | } | |
843 | ||
844 | E1000_WRITE_REG(hw, TARC0, reg_tarc0); | |
845 | } | |
846 | } | |
847 | ||
1da177e4 LT |
848 | /****************************************************************************** |
849 | * Performs basic configuration of the adapter. | |
850 | * | |
851 | * hw - Struct containing variables accessed by shared code | |
852 | * | |
853 | * Assumes that the controller has previously been reset and is in a | |
854 | * post-reset uninitialized state. Initializes the receive address registers, | |
855 | * multicast table, and VLAN filter table. Calls routines to setup link | |
856 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
857 | * the transmit and receive units disabled and uninitialized. | |
858 | *****************************************************************************/ | |
859 | int32_t | |
860 | e1000_init_hw(struct e1000_hw *hw) | |
861 | { | |
862 | uint32_t ctrl; | |
863 | uint32_t i; | |
864 | int32_t ret_val; | |
865 | uint16_t pcix_cmd_word; | |
866 | uint16_t pcix_stat_hi_word; | |
867 | uint16_t cmd_mmrbc; | |
868 | uint16_t stat_mmrbc; | |
2d7edb92 | 869 | uint32_t mta_size; |
6418ecc6 | 870 | uint32_t reg_data; |
b7ee49db | 871 | uint32_t ctrl_ext; |
2d7edb92 | 872 | |
1da177e4 LT |
873 | DEBUGFUNC("e1000_init_hw"); |
874 | ||
7820d428 | 875 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
09ae3e88 JK |
876 | if ((hw->mac_type == e1000_ich8lan) && |
877 | ((hw->revision_id < 3) || | |
878 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
879 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { | |
880 | reg_data = E1000_READ_REG(hw, STATUS); | |
881 | reg_data &= ~0x80000000; | |
882 | E1000_WRITE_REG(hw, STATUS, reg_data); | |
7820d428 JK |
883 | } |
884 | ||
1da177e4 LT |
885 | /* Initialize Identification LED */ |
886 | ret_val = e1000_id_led_init(hw); | |
8fc897b0 | 887 | if (ret_val) { |
1da177e4 LT |
888 | DEBUGOUT("Error Initializing Identification LED\n"); |
889 | return ret_val; | |
890 | } | |
891 | ||
892 | /* Set the media type and TBI compatibility */ | |
893 | e1000_set_media_type(hw); | |
894 | ||
09ae3e88 JK |
895 | /* Must be called after e1000_set_media_type because media_type is used */ |
896 | e1000_initialize_hardware_bits(hw); | |
897 | ||
1da177e4 LT |
898 | /* Disabling VLAN filtering. */ |
899 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
cd94dd0b AK |
900 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
901 | if (hw->mac_type != e1000_ich8lan) { | |
902 | if (hw->mac_type < e1000_82545_rev_3) | |
903 | E1000_WRITE_REG(hw, VET, 0); | |
904 | e1000_clear_vfta(hw); | |
905 | } | |
1da177e4 LT |
906 | |
907 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
8fc897b0 | 908 | if (hw->mac_type == e1000_82542_rev2_0) { |
1da177e4 LT |
909 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
910 | e1000_pci_clear_mwi(hw); | |
911 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); | |
912 | E1000_WRITE_FLUSH(hw); | |
f8ec4733 | 913 | msleep(5); |
1da177e4 LT |
914 | } |
915 | ||
916 | /* Setup the receive address. This involves initializing all of the Receive | |
917 | * Address Registers (RARs 0 - 15). | |
918 | */ | |
919 | e1000_init_rx_addrs(hw); | |
920 | ||
921 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
8fc897b0 | 922 | if (hw->mac_type == e1000_82542_rev2_0) { |
1da177e4 LT |
923 | E1000_WRITE_REG(hw, RCTL, 0); |
924 | E1000_WRITE_FLUSH(hw); | |
f8ec4733 JG |
925 | msleep(1); |
926 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) | |
1da177e4 LT |
927 | e1000_pci_set_mwi(hw); |
928 | } | |
929 | ||
930 | /* Zero out the Multicast HASH table */ | |
931 | DEBUGOUT("Zeroing the MTA\n"); | |
2d7edb92 | 932 | mta_size = E1000_MC_TBL_SIZE; |
cd94dd0b AK |
933 | if (hw->mac_type == e1000_ich8lan) |
934 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; | |
8fc897b0 | 935 | for (i = 0; i < mta_size; i++) { |
1da177e4 | 936 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
4ca213a6 AK |
937 | /* use write flush to prevent Memory Write Block (MWB) from |
938 | * occuring when accessing our register space */ | |
939 | E1000_WRITE_FLUSH(hw); | |
940 | } | |
1da177e4 LT |
941 | |
942 | /* Set the PCI priority bit correctly in the CTRL register. This | |
943 | * determines if the adapter gives priority to receives, or if it | |
2d7edb92 MC |
944 | * gives equal priority to transmits and receives. Valid only on |
945 | * 82542 and 82543 silicon. | |
1da177e4 | 946 | */ |
8fc897b0 | 947 | if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
1da177e4 LT |
948 | ctrl = E1000_READ_REG(hw, CTRL); |
949 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); | |
950 | } | |
951 | ||
8fc897b0 | 952 | switch (hw->mac_type) { |
1da177e4 LT |
953 | case e1000_82545_rev_3: |
954 | case e1000_82546_rev_3: | |
955 | break; | |
956 | default: | |
957 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ | |
8fc897b0 | 958 | if (hw->bus_type == e1000_bus_type_pcix) { |
1da177e4 LT |
959 | e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); |
960 | e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, | |
961 | &pcix_stat_hi_word); | |
962 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> | |
963 | PCIX_COMMAND_MMRBC_SHIFT; | |
964 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> | |
965 | PCIX_STATUS_HI_MMRBC_SHIFT; | |
8fc897b0 | 966 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
1da177e4 | 967 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
8fc897b0 | 968 | if (cmd_mmrbc > stat_mmrbc) { |
1da177e4 LT |
969 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
970 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; | |
971 | e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, | |
972 | &pcix_cmd_word); | |
973 | } | |
974 | } | |
975 | break; | |
976 | } | |
977 | ||
cd94dd0b AK |
978 | /* More time needed for PHY to initialize */ |
979 | if (hw->mac_type == e1000_ich8lan) | |
f8ec4733 | 980 | msleep(15); |
cd94dd0b | 981 | |
1da177e4 LT |
982 | /* Call a subroutine to configure the link and setup flow control. */ |
983 | ret_val = e1000_setup_link(hw); | |
984 | ||
985 | /* Set the transmit descriptor write-back policy */ | |
8fc897b0 | 986 | if (hw->mac_type > e1000_82544) { |
1da177e4 LT |
987 | ctrl = E1000_READ_REG(hw, TXDCTL); |
988 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | |
989 | E1000_WRITE_REG(hw, TXDCTL, ctrl); | |
990 | } | |
991 | ||
2d7edb92 | 992 | if (hw->mac_type == e1000_82573) { |
76c224bc | 993 | e1000_enable_tx_pkt_filtering(hw); |
2d7edb92 MC |
994 | } |
995 | ||
868d5309 MC |
996 | switch (hw->mac_type) { |
997 | default: | |
998 | break; | |
6418ecc6 JK |
999 | case e1000_80003es2lan: |
1000 | /* Enable retransmit on late collisions */ | |
1001 | reg_data = E1000_READ_REG(hw, TCTL); | |
1002 | reg_data |= E1000_TCTL_RTLC; | |
1003 | E1000_WRITE_REG(hw, TCTL, reg_data); | |
1004 | ||
1005 | /* Configure Gigabit Carry Extend Padding */ | |
1006 | reg_data = E1000_READ_REG(hw, TCTL_EXT); | |
1007 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
1008 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | |
1009 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); | |
1010 | ||
1011 | /* Configure Transmit Inter-Packet Gap */ | |
1012 | reg_data = E1000_READ_REG(hw, TIPG); | |
1013 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
1014 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
1015 | E1000_WRITE_REG(hw, TIPG, reg_data); | |
1016 | ||
1017 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | |
1018 | reg_data &= ~0x00100000; | |
1019 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | |
1020 | /* Fall through */ | |
868d5309 | 1021 | case e1000_82571: |
a7990ba6 | 1022 | case e1000_82572: |
cd94dd0b | 1023 | case e1000_ich8lan: |
868d5309 | 1024 | ctrl = E1000_READ_REG(hw, TXDCTL1); |
6418ecc6 | 1025 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
868d5309 MC |
1026 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
1027 | break; | |
1028 | } | |
1029 | ||
1030 | ||
868d5309 MC |
1031 | if (hw->mac_type == e1000_82573) { |
1032 | uint32_t gcr = E1000_READ_REG(hw, GCR); | |
1033 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1034 | E1000_WRITE_REG(hw, GCR, gcr); | |
1035 | } | |
2d7edb92 | 1036 | |
1da177e4 LT |
1037 | /* Clear all of the statistics registers (clear on read). It is |
1038 | * important that we do this after we have tried to establish link | |
1039 | * because the symbol error count will increment wildly if there | |
1040 | * is no link. | |
1041 | */ | |
1042 | e1000_clear_hw_cntrs(hw); | |
1043 | ||
cd94dd0b AK |
1044 | /* ICH8 No-snoop bits are opposite polarity. |
1045 | * Set to snoop by default after reset. */ | |
1046 | if (hw->mac_type == e1000_ich8lan) | |
1047 | e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); | |
1048 | ||
b7ee49db JK |
1049 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
1050 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | |
1051 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1052 | /* Relaxed ordering must be disabled to avoid a parity | |
1053 | * error crash in a PCI slot. */ | |
1054 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
1055 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1056 | } | |
1057 | ||
1da177e4 LT |
1058 | return ret_val; |
1059 | } | |
1060 | ||
1061 | /****************************************************************************** | |
1062 | * Adjust SERDES output amplitude based on EEPROM setting. | |
1063 | * | |
1064 | * hw - Struct containing variables accessed by shared code. | |
1065 | *****************************************************************************/ | |
1066 | static int32_t | |
1067 | e1000_adjust_serdes_amplitude(struct e1000_hw *hw) | |
1068 | { | |
1069 | uint16_t eeprom_data; | |
1070 | int32_t ret_val; | |
1071 | ||
1072 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); | |
1073 | ||
8fc897b0 | 1074 | if (hw->media_type != e1000_media_type_internal_serdes) |
1da177e4 LT |
1075 | return E1000_SUCCESS; |
1076 | ||
8fc897b0 | 1077 | switch (hw->mac_type) { |
1da177e4 LT |
1078 | case e1000_82545_rev_3: |
1079 | case e1000_82546_rev_3: | |
1080 | break; | |
1081 | default: | |
1082 | return E1000_SUCCESS; | |
1083 | } | |
1084 | ||
1085 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); | |
1086 | if (ret_val) { | |
1087 | return ret_val; | |
1088 | } | |
1089 | ||
8fc897b0 | 1090 | if (eeprom_data != EEPROM_RESERVED_WORD) { |
1da177e4 | 1091 | /* Adjust SERDES output amplitude only. */ |
76c224bc | 1092 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
1da177e4 | 1093 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
8fc897b0 | 1094 | if (ret_val) |
1da177e4 LT |
1095 | return ret_val; |
1096 | } | |
1097 | ||
1098 | return E1000_SUCCESS; | |
1099 | } | |
1100 | ||
1101 | /****************************************************************************** | |
1102 | * Configures flow control and link settings. | |
1103 | * | |
1104 | * hw - Struct containing variables accessed by shared code | |
1105 | * | |
1106 | * Determines which flow control settings to use. Calls the apropriate media- | |
1107 | * specific link configuration function. Configures the flow control settings. | |
1108 | * Assuming the adapter has a valid link partner, a valid link should be | |
1109 | * established. Assumes the hardware has previously been reset and the | |
1110 | * transmitter and receiver are not enabled. | |
1111 | *****************************************************************************/ | |
1112 | int32_t | |
1113 | e1000_setup_link(struct e1000_hw *hw) | |
1114 | { | |
1115 | uint32_t ctrl_ext; | |
1116 | int32_t ret_val; | |
1117 | uint16_t eeprom_data; | |
1118 | ||
1119 | DEBUGFUNC("e1000_setup_link"); | |
1120 | ||
526f9957 JK |
1121 | /* In the case of the phy reset being blocked, we already have a link. |
1122 | * We do not have to set it up again. */ | |
1123 | if (e1000_check_phy_reset_block(hw)) | |
1124 | return E1000_SUCCESS; | |
1125 | ||
1da177e4 LT |
1126 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
1127 | * that determine the hardware's default PAUSE (flow control) mode, | |
1128 | * a bit that determines whether the HW defaults to enabling or | |
1129 | * disabling auto-negotiation, and the direction of the | |
1130 | * SW defined pins. If there is no SW over-ride of the flow | |
1131 | * control setting, then the variable hw->fc will | |
1132 | * be initialized based on a value in the EEPROM. | |
1133 | */ | |
11241b10 | 1134 | if (hw->fc == E1000_FC_DEFAULT) { |
fd803241 | 1135 | switch (hw->mac_type) { |
cd94dd0b | 1136 | case e1000_ich8lan: |
fd803241 | 1137 | case e1000_82573: |
11241b10 | 1138 | hw->fc = E1000_FC_FULL; |
fd803241 JK |
1139 | break; |
1140 | default: | |
1141 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | |
1142 | 1, &eeprom_data); | |
1143 | if (ret_val) { | |
1144 | DEBUGOUT("EEPROM Read Error\n"); | |
1145 | return -E1000_ERR_EEPROM; | |
1146 | } | |
1147 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) | |
11241b10 | 1148 | hw->fc = E1000_FC_NONE; |
fd803241 JK |
1149 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
1150 | EEPROM_WORD0F_ASM_DIR) | |
11241b10 | 1151 | hw->fc = E1000_FC_TX_PAUSE; |
fd803241 | 1152 | else |
11241b10 | 1153 | hw->fc = E1000_FC_FULL; |
fd803241 JK |
1154 | break; |
1155 | } | |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | /* We want to save off the original Flow Control configuration just | |
1159 | * in case we get disconnected and then reconnected into a different | |
1160 | * hub or switch with different Flow Control capabilities. | |
1161 | */ | |
8fc897b0 | 1162 | if (hw->mac_type == e1000_82542_rev2_0) |
11241b10 | 1163 | hw->fc &= (~E1000_FC_TX_PAUSE); |
1da177e4 | 1164 | |
8fc897b0 | 1165 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
11241b10 | 1166 | hw->fc &= (~E1000_FC_RX_PAUSE); |
1da177e4 LT |
1167 | |
1168 | hw->original_fc = hw->fc; | |
1169 | ||
1170 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | |
1171 | ||
1172 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial | |
1173 | * polarity value for the SW controlled pins, and setup the | |
1174 | * Extended Device Control reg with that info. | |
1175 | * This is needed because one of the SW controlled pins is used for | |
1176 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
1177 | * or e1000_phy_setup() is called. | |
1178 | */ | |
497fce5e | 1179 | if (hw->mac_type == e1000_82543) { |
8fc897b0 AK |
1180 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
1181 | 1, &eeprom_data); | |
1182 | if (ret_val) { | |
1183 | DEBUGOUT("EEPROM Read Error\n"); | |
1184 | return -E1000_ERR_EEPROM; | |
1185 | } | |
1da177e4 LT |
1186 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
1187 | SWDPIO__EXT_SHIFT); | |
1188 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1189 | } | |
1190 | ||
1191 | /* Call the necessary subroutine to configure the link. */ | |
1192 | ret_val = (hw->media_type == e1000_media_type_copper) ? | |
1193 | e1000_setup_copper_link(hw) : | |
1194 | e1000_setup_fiber_serdes_link(hw); | |
1195 | ||
1196 | /* Initialize the flow control address, type, and PAUSE timer | |
1197 | * registers to their default values. This is done even if flow | |
1198 | * control is disabled, because it does not hurt anything to | |
1199 | * initialize these registers. | |
1200 | */ | |
1201 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | |
1202 | ||
cd94dd0b AK |
1203 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
1204 | if (hw->mac_type != e1000_ich8lan) { | |
1205 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | |
1206 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
1207 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
1208 | } | |
2d7edb92 | 1209 | |
1da177e4 LT |
1210 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
1211 | ||
1212 | /* Set the flow control receive threshold registers. Normally, | |
1213 | * these registers will be set to a default threshold that may be | |
1214 | * adjusted later by the driver's runtime code. However, if the | |
1215 | * ability to transmit pause frames in not enabled, then these | |
1216 | * registers will be set to 0. | |
1217 | */ | |
11241b10 | 1218 | if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
1da177e4 LT |
1219 | E1000_WRITE_REG(hw, FCRTL, 0); |
1220 | E1000_WRITE_REG(hw, FCRTH, 0); | |
1221 | } else { | |
1222 | /* We need to set up the Receive Threshold high and low water marks | |
1223 | * as well as (optionally) enabling the transmission of XON frames. | |
1224 | */ | |
8fc897b0 | 1225 | if (hw->fc_send_xon) { |
1da177e4 LT |
1226 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
1227 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
1228 | } else { | |
1229 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); | |
1230 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
1231 | } | |
1232 | } | |
1233 | return ret_val; | |
1234 | } | |
1235 | ||
1236 | /****************************************************************************** | |
1237 | * Sets up link for a fiber based or serdes based adapter | |
1238 | * | |
1239 | * hw - Struct containing variables accessed by shared code | |
1240 | * | |
1241 | * Manipulates Physical Coding Sublayer functions in order to configure | |
1242 | * link. Assumes the hardware has been previously reset and the transmitter | |
1243 | * and receiver are not enabled. | |
1244 | *****************************************************************************/ | |
1245 | static int32_t | |
1246 | e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |
1247 | { | |
1248 | uint32_t ctrl; | |
1249 | uint32_t status; | |
1250 | uint32_t txcw = 0; | |
1251 | uint32_t i; | |
1252 | uint32_t signal = 0; | |
1253 | int32_t ret_val; | |
1254 | ||
1255 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); | |
1256 | ||
868d5309 MC |
1257 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
1258 | * until explicitly turned off or a power cycle is performed. A read to | |
1259 | * the register does not indicate its status. Therefore, we ensure | |
1260 | * loopback mode is disabled during initialization. | |
1261 | */ | |
1262 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) | |
1263 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); | |
1264 | ||
09ae3e88 | 1265 | /* On adapters with a MAC newer than 82544, SWDP 1 will be |
1da177e4 LT |
1266 | * set when the optics detect a signal. On older adapters, it will be |
1267 | * cleared when there is a signal. This applies to fiber media only. | |
09ae3e88 JK |
1268 | * If we're on serdes media, adjust the output amplitude to value |
1269 | * set in the EEPROM. | |
1da177e4 LT |
1270 | */ |
1271 | ctrl = E1000_READ_REG(hw, CTRL); | |
8fc897b0 | 1272 | if (hw->media_type == e1000_media_type_fiber) |
1da177e4 LT |
1273 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
1274 | ||
1275 | ret_val = e1000_adjust_serdes_amplitude(hw); | |
8fc897b0 | 1276 | if (ret_val) |
1da177e4 LT |
1277 | return ret_val; |
1278 | ||
1279 | /* Take the link out of reset */ | |
1280 | ctrl &= ~(E1000_CTRL_LRST); | |
1281 | ||
1282 | /* Adjust VCO speed to improve BER performance */ | |
1283 | ret_val = e1000_set_vco_speed(hw); | |
8fc897b0 | 1284 | if (ret_val) |
1da177e4 LT |
1285 | return ret_val; |
1286 | ||
1287 | e1000_config_collision_dist(hw); | |
1288 | ||
1289 | /* Check for a software override of the flow control settings, and setup | |
1290 | * the device accordingly. If auto-negotiation is enabled, then software | |
1291 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
1292 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
1293 | * auto-negotiation is disabled, then software will have to manually | |
1294 | * configure the two flow control enable bits in the CTRL register. | |
1295 | * | |
1296 | * The possible values of the "fc" parameter are: | |
1297 | * 0: Flow control is completely disabled | |
1298 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
1299 | * not send pause frames). | |
1300 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
1301 | * not support receiving pause frames). | |
1302 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1303 | */ | |
1304 | switch (hw->fc) { | |
11241b10 | 1305 | case E1000_FC_NONE: |
1da177e4 LT |
1306 | /* Flow control is completely disabled by a software over-ride. */ |
1307 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
1308 | break; | |
11241b10 | 1309 | case E1000_FC_RX_PAUSE: |
1da177e4 LT |
1310 | /* RX Flow control is enabled and TX Flow control is disabled by a |
1311 | * software over-ride. Since there really isn't a way to advertise | |
1312 | * that we are capable of RX Pause ONLY, we will advertise that we | |
1313 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
1314 | * disable the adapter's ability to send PAUSE frames. | |
1315 | */ | |
1316 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1317 | break; | |
11241b10 | 1318 | case E1000_FC_TX_PAUSE: |
1da177e4 LT |
1319 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
1320 | * software over-ride. | |
1321 | */ | |
1322 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
1323 | break; | |
11241b10 | 1324 | case E1000_FC_FULL: |
1da177e4 LT |
1325 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
1326 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1327 | break; | |
1328 | default: | |
1329 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1330 | return -E1000_ERR_CONFIG; | |
1331 | break; | |
1332 | } | |
1333 | ||
1334 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
1335 | * will be in reset, because we previously reset the chip). This will | |
1336 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
1337 | * link-up status bit will be set and the flow control enable bits (RFCE | |
1338 | * and TFCE) will be set according to their negotiated value. | |
1339 | */ | |
1340 | DEBUGOUT("Auto-negotiation enabled\n"); | |
1341 | ||
1342 | E1000_WRITE_REG(hw, TXCW, txcw); | |
1343 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1344 | E1000_WRITE_FLUSH(hw); | |
1345 | ||
1346 | hw->txcw = txcw; | |
f8ec4733 | 1347 | msleep(1); |
1da177e4 LT |
1348 | |
1349 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
1350 | * indication in the Device Status Register. Time-out if a link isn't | |
1351 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
1352 | * less than 500 milliseconds even if the other end is doing it in SW). | |
1353 | * For internal serdes, we just assume a signal is present, then poll. | |
1354 | */ | |
8fc897b0 | 1355 | if (hw->media_type == e1000_media_type_internal_serdes || |
1da177e4 LT |
1356 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
1357 | DEBUGOUT("Looking for Link\n"); | |
8fc897b0 | 1358 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
f8ec4733 | 1359 | msleep(10); |
1da177e4 | 1360 | status = E1000_READ_REG(hw, STATUS); |
8fc897b0 | 1361 | if (status & E1000_STATUS_LU) break; |
1da177e4 | 1362 | } |
8fc897b0 | 1363 | if (i == (LINK_UP_TIMEOUT / 10)) { |
1da177e4 LT |
1364 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
1365 | hw->autoneg_failed = 1; | |
1366 | /* AutoNeg failed to achieve a link, so we'll call | |
1367 | * e1000_check_for_link. This routine will force the link up if | |
1368 | * we detect a signal. This will allow us to communicate with | |
1369 | * non-autonegotiating link partners. | |
1370 | */ | |
1371 | ret_val = e1000_check_for_link(hw); | |
8fc897b0 | 1372 | if (ret_val) { |
1da177e4 LT |
1373 | DEBUGOUT("Error while checking for link\n"); |
1374 | return ret_val; | |
1375 | } | |
1376 | hw->autoneg_failed = 0; | |
1377 | } else { | |
1378 | hw->autoneg_failed = 0; | |
1379 | DEBUGOUT("Valid Link Found\n"); | |
1380 | } | |
1381 | } else { | |
1382 | DEBUGOUT("No Signal Detected\n"); | |
1383 | } | |
1384 | return E1000_SUCCESS; | |
1385 | } | |
1386 | ||
1387 | /****************************************************************************** | |
2d7edb92 | 1388 | * Make sure we have a valid PHY and change PHY mode before link setup. |
1da177e4 LT |
1389 | * |
1390 | * hw - Struct containing variables accessed by shared code | |
1391 | ******************************************************************************/ | |
1392 | static int32_t | |
2d7edb92 | 1393 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
1da177e4 LT |
1394 | { |
1395 | uint32_t ctrl; | |
1da177e4 | 1396 | int32_t ret_val; |
1da177e4 LT |
1397 | uint16_t phy_data; |
1398 | ||
2d7edb92 | 1399 | DEBUGFUNC("e1000_copper_link_preconfig"); |
1da177e4 LT |
1400 | |
1401 | ctrl = E1000_READ_REG(hw, CTRL); | |
1402 | /* With 82543, we need to force speed and duplex on the MAC equal to what | |
1403 | * the PHY speed and duplex configuration is. In addition, we need to | |
1404 | * perform a hardware reset on the PHY to take it out of reset. | |
1405 | */ | |
8fc897b0 | 1406 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
1407 | ctrl |= E1000_CTRL_SLU; |
1408 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1409 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1410 | } else { | |
1411 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | |
1412 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2d7edb92 | 1413 | ret_val = e1000_phy_hw_reset(hw); |
8fc897b0 | 1414 | if (ret_val) |
2d7edb92 | 1415 | return ret_val; |
1da177e4 LT |
1416 | } |
1417 | ||
1418 | /* Make sure we have a valid PHY */ | |
1419 | ret_val = e1000_detect_gig_phy(hw); | |
8fc897b0 | 1420 | if (ret_val) { |
1da177e4 LT |
1421 | DEBUGOUT("Error, did not detect valid phy.\n"); |
1422 | return ret_val; | |
1423 | } | |
1424 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); | |
1425 | ||
1426 | /* Set PHY to class A mode (if necessary) */ | |
1427 | ret_val = e1000_set_phy_mode(hw); | |
8fc897b0 | 1428 | if (ret_val) |
1da177e4 LT |
1429 | return ret_val; |
1430 | ||
8fc897b0 | 1431 | if ((hw->mac_type == e1000_82545_rev_3) || |
1da177e4 LT |
1432 | (hw->mac_type == e1000_82546_rev_3)) { |
1433 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1434 | phy_data |= 0x00000008; | |
1435 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1436 | } | |
1437 | ||
8fc897b0 AK |
1438 | if (hw->mac_type <= e1000_82543 || |
1439 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
1440 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | |
1da177e4 LT |
1441 | hw->phy_reset_disable = FALSE; |
1442 | ||
2d7edb92 MC |
1443 | return E1000_SUCCESS; |
1444 | } | |
1da177e4 | 1445 | |
1da177e4 | 1446 | |
2d7edb92 MC |
1447 | /******************************************************************** |
1448 | * Copper link setup for e1000_phy_igp series. | |
1449 | * | |
1450 | * hw - Struct containing variables accessed by shared code | |
1451 | *********************************************************************/ | |
1452 | static int32_t | |
1453 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | |
1454 | { | |
1455 | uint32_t led_ctrl; | |
1456 | int32_t ret_val; | |
1457 | uint16_t phy_data; | |
1da177e4 | 1458 | |
2d7edb92 | 1459 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
1da177e4 | 1460 | |
2d7edb92 MC |
1461 | if (hw->phy_reset_disable) |
1462 | return E1000_SUCCESS; | |
76c224bc | 1463 | |
2d7edb92 MC |
1464 | ret_val = e1000_phy_reset(hw); |
1465 | if (ret_val) { | |
1466 | DEBUGOUT("Error Resetting the PHY\n"); | |
1467 | return ret_val; | |
1468 | } | |
1da177e4 | 1469 | |
8fc897b0 | 1470 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
f8ec4733 | 1471 | msleep(15); |
cd94dd0b | 1472 | if (hw->mac_type != e1000_ich8lan) { |
2d7edb92 MC |
1473 | /* Configure activity LED after PHY reset */ |
1474 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
1475 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1476 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1477 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
cd94dd0b | 1478 | } |
1da177e4 | 1479 | |
c9c1b834 JK |
1480 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
1481 | if (hw->phy_type == e1000_phy_igp) { | |
1482 | /* disable lplu d3 during driver init */ | |
1483 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); | |
1484 | if (ret_val) { | |
1485 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
1486 | return ret_val; | |
1487 | } | |
2d7edb92 | 1488 | } |
1da177e4 | 1489 | |
2d7edb92 MC |
1490 | /* disable lplu d0 during driver init */ |
1491 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); | |
1492 | if (ret_val) { | |
1493 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
1494 | return ret_val; | |
1495 | } | |
1496 | /* Configure mdi-mdix settings */ | |
1497 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1498 | if (ret_val) | |
1499 | return ret_val; | |
1da177e4 | 1500 | |
2d7edb92 MC |
1501 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1502 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
1503 | /* Force MDI for earlier revs of the IGP PHY */ | |
1504 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
1505 | hw->mdix = 1; | |
1da177e4 | 1506 | |
2d7edb92 MC |
1507 | } else { |
1508 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1509 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1da177e4 | 1510 | |
2d7edb92 MC |
1511 | switch (hw->mdix) { |
1512 | case 1: | |
1513 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1514 | break; | |
1515 | case 2: | |
1516 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1517 | break; | |
1518 | case 0: | |
1519 | default: | |
1520 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
1521 | break; | |
1522 | } | |
1523 | } | |
1524 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
8fc897b0 | 1525 | if (ret_val) |
2d7edb92 | 1526 | return ret_val; |
1da177e4 | 1527 | |
2d7edb92 | 1528 | /* set auto-master slave resolution settings */ |
8fc897b0 | 1529 | if (hw->autoneg) { |
2d7edb92 | 1530 | e1000_ms_type phy_ms_setting = hw->master_slave; |
1da177e4 | 1531 | |
8fc897b0 | 1532 | if (hw->ffe_config_state == e1000_ffe_config_active) |
2d7edb92 | 1533 | hw->ffe_config_state = e1000_ffe_config_enabled; |
1da177e4 | 1534 | |
8fc897b0 | 1535 | if (hw->dsp_config_state == e1000_dsp_config_activated) |
2d7edb92 | 1536 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1da177e4 | 1537 | |
2d7edb92 MC |
1538 | /* when autonegotiation advertisment is only 1000Mbps then we |
1539 | * should disable SmartSpeed and enable Auto MasterSlave | |
1540 | * resolution as hardware default. */ | |
8fc897b0 | 1541 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
2d7edb92 | 1542 | /* Disable SmartSpeed */ |
8fc897b0 AK |
1543 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1544 | &phy_data); | |
1545 | if (ret_val) | |
1da177e4 | 1546 | return ret_val; |
2d7edb92 | 1547 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
8fc897b0 AK |
1548 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1549 | phy_data); | |
1550 | if (ret_val) | |
1da177e4 | 1551 | return ret_val; |
2d7edb92 MC |
1552 | /* Set auto Master/Slave resolution process */ |
1553 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
8fc897b0 | 1554 | if (ret_val) |
2d7edb92 MC |
1555 | return ret_val; |
1556 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1557 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
8fc897b0 | 1558 | if (ret_val) |
2d7edb92 MC |
1559 | return ret_val; |
1560 | } | |
1da177e4 | 1561 | |
2d7edb92 | 1562 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
8fc897b0 | 1563 | if (ret_val) |
2d7edb92 | 1564 | return ret_val; |
1da177e4 | 1565 | |
2d7edb92 MC |
1566 | /* load defaults for future use */ |
1567 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
1568 | ((phy_data & CR_1000T_MS_VALUE) ? | |
1569 | e1000_ms_force_master : | |
1570 | e1000_ms_force_slave) : | |
1571 | e1000_ms_auto; | |
1da177e4 | 1572 | |
2d7edb92 MC |
1573 | switch (phy_ms_setting) { |
1574 | case e1000_ms_force_master: | |
1575 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
1576 | break; | |
1577 | case e1000_ms_force_slave: | |
1578 | phy_data |= CR_1000T_MS_ENABLE; | |
1579 | phy_data &= ~(CR_1000T_MS_VALUE); | |
1580 | break; | |
1581 | case e1000_ms_auto: | |
1582 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1583 | default: | |
1584 | break; | |
1585 | } | |
1586 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
8fc897b0 | 1587 | if (ret_val) |
2d7edb92 | 1588 | return ret_val; |
2b02893e | 1589 | } |
1da177e4 | 1590 | |
2b02893e | 1591 | return E1000_SUCCESS; |
2d7edb92 | 1592 | } |
1da177e4 | 1593 | |
6418ecc6 JK |
1594 | /******************************************************************** |
1595 | * Copper link setup for e1000_phy_gg82563 series. | |
1596 | * | |
1597 | * hw - Struct containing variables accessed by shared code | |
1598 | *********************************************************************/ | |
1599 | static int32_t | |
1600 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) | |
1601 | { | |
1602 | int32_t ret_val; | |
1603 | uint16_t phy_data; | |
1604 | uint32_t reg_data; | |
1605 | ||
1606 | DEBUGFUNC("e1000_copper_link_ggp_setup"); | |
1607 | ||
8fc897b0 | 1608 | if (!hw->phy_reset_disable) { |
76c224bc | 1609 | |
6418ecc6 JK |
1610 | /* Enable CRS on TX for half-duplex operation. */ |
1611 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1612 | &phy_data); | |
8fc897b0 | 1613 | if (ret_val) |
6418ecc6 JK |
1614 | return ret_val; |
1615 | ||
1616 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
1617 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | |
1618 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | |
1619 | ||
1620 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1621 | phy_data); | |
8fc897b0 | 1622 | if (ret_val) |
6418ecc6 JK |
1623 | return ret_val; |
1624 | ||
1625 | /* Options: | |
1626 | * MDI/MDI-X = 0 (default) | |
1627 | * 0 - Auto for all speeds | |
1628 | * 1 - MDI mode | |
1629 | * 2 - MDI-X mode | |
1630 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1631 | */ | |
1632 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 1633 | if (ret_val) |
6418ecc6 JK |
1634 | return ret_val; |
1635 | ||
1636 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
1637 | ||
1638 | switch (hw->mdix) { | |
1639 | case 1: | |
1640 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
1641 | break; | |
1642 | case 2: | |
1643 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
1644 | break; | |
1645 | case 0: | |
1646 | default: | |
1647 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
1648 | break; | |
1649 | } | |
1650 | ||
1651 | /* Options: | |
1652 | * disable_polarity_correction = 0 (default) | |
1653 | * Automatic Correction for Reversed Cable Polarity | |
1654 | * 0 - Disabled | |
1655 | * 1 - Enabled | |
1656 | */ | |
1657 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
8fc897b0 | 1658 | if (hw->disable_polarity_correction == 1) |
6418ecc6 JK |
1659 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
1660 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
1661 | ||
8fc897b0 | 1662 | if (ret_val) |
6418ecc6 JK |
1663 | return ret_val; |
1664 | ||
1665 | /* SW Reset the PHY so all changes take effect */ | |
1666 | ret_val = e1000_phy_reset(hw); | |
1667 | if (ret_val) { | |
1668 | DEBUGOUT("Error Resetting the PHY\n"); | |
1669 | return ret_val; | |
1670 | } | |
1671 | } /* phy_reset_disable */ | |
1672 | ||
1673 | if (hw->mac_type == e1000_80003es2lan) { | |
1674 | /* Bypass RX and TX FIFO's */ | |
1675 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | |
1676 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | | |
1677 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | |
1678 | if (ret_val) | |
1679 | return ret_val; | |
1680 | ||
1681 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); | |
1682 | if (ret_val) | |
1683 | return ret_val; | |
1684 | ||
1685 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1686 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); | |
1687 | ||
1688 | if (ret_val) | |
1689 | return ret_val; | |
1690 | ||
1691 | reg_data = E1000_READ_REG(hw, CTRL_EXT); | |
1692 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1693 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); | |
1694 | ||
1695 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1696 | &phy_data); | |
1697 | if (ret_val) | |
1698 | return ret_val; | |
1699 | ||
1700 | /* Do not init these registers when the HW is in IAMT mode, since the | |
1701 | * firmware will have already initialized them. We only initialize | |
1702 | * them if the HW is not in IAMT mode. | |
1703 | */ | |
1704 | if (e1000_check_mng_mode(hw) == FALSE) { | |
1705 | /* Enable Electrical Idle on the PHY */ | |
1706 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1707 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1708 | phy_data); | |
1709 | if (ret_val) | |
1710 | return ret_val; | |
1711 | ||
1712 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1713 | &phy_data); | |
1714 | if (ret_val) | |
1715 | return ret_val; | |
1716 | ||
cd94dd0b | 1717 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
6418ecc6 JK |
1718 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
1719 | phy_data); | |
8fc897b0 | 1720 | |
6418ecc6 JK |
1721 | if (ret_val) |
1722 | return ret_val; | |
1723 | } | |
1724 | ||
1725 | /* Workaround: Disable padding in Kumeran interface in the MAC | |
1726 | * and in the PHY to avoid CRC errors. | |
1727 | */ | |
1728 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1729 | &phy_data); | |
1730 | if (ret_val) | |
1731 | return ret_val; | |
1732 | phy_data |= GG82563_ICR_DIS_PADDING; | |
1733 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1734 | phy_data); | |
1735 | if (ret_val) | |
1736 | return ret_val; | |
1737 | } | |
1738 | ||
1739 | return E1000_SUCCESS; | |
1740 | } | |
1da177e4 | 1741 | |
2d7edb92 MC |
1742 | /******************************************************************** |
1743 | * Copper link setup for e1000_phy_m88 series. | |
1744 | * | |
1745 | * hw - Struct containing variables accessed by shared code | |
1746 | *********************************************************************/ | |
1747 | static int32_t | |
1748 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | |
1749 | { | |
1750 | int32_t ret_val; | |
1751 | uint16_t phy_data; | |
1da177e4 | 1752 | |
2d7edb92 | 1753 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
1da177e4 | 1754 | |
8fc897b0 | 1755 | if (hw->phy_reset_disable) |
2d7edb92 | 1756 | return E1000_SUCCESS; |
76c224bc | 1757 | |
2d7edb92 MC |
1758 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
1759 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 1760 | if (ret_val) |
2d7edb92 | 1761 | return ret_val; |
1da177e4 | 1762 | |
2d7edb92 | 1763 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
1da177e4 | 1764 | |
2d7edb92 MC |
1765 | /* Options: |
1766 | * MDI/MDI-X = 0 (default) | |
1767 | * 0 - Auto for all speeds | |
1768 | * 1 - MDI mode | |
1769 | * 2 - MDI-X mode | |
1770 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1771 | */ | |
1772 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1da177e4 | 1773 | |
2d7edb92 MC |
1774 | switch (hw->mdix) { |
1775 | case 1: | |
1776 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
1777 | break; | |
1778 | case 2: | |
1779 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
1780 | break; | |
1781 | case 3: | |
1782 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
1783 | break; | |
1784 | case 0: | |
1785 | default: | |
1786 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
1787 | break; | |
1788 | } | |
1789 | ||
1790 | /* Options: | |
1791 | * disable_polarity_correction = 0 (default) | |
1792 | * Automatic Correction for Reversed Cable Polarity | |
1793 | * 0 - Disabled | |
1794 | * 1 - Enabled | |
1da177e4 | 1795 | */ |
2d7edb92 | 1796 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
8fc897b0 | 1797 | if (hw->disable_polarity_correction == 1) |
2d7edb92 | 1798 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
ee04022a AK |
1799 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
1800 | if (ret_val) | |
2d7edb92 MC |
1801 | return ret_val; |
1802 | ||
2d7edb92 | 1803 | if (hw->phy_revision < M88E1011_I_REV_4) { |
ee04022a AK |
1804 | /* Force TX_CLK in the Extended PHY Specific Control Register |
1805 | * to 25MHz clock. | |
1806 | */ | |
1807 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1808 | if (ret_val) | |
1809 | return ret_val; | |
1810 | ||
1811 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1812 | ||
1813 | if ((hw->phy_revision == E1000_REVISION_2) && | |
1814 | (hw->phy_id == M88E1111_I_PHY_ID)) { | |
1815 | /* Vidalia Phy, set the downshift counter to 5x */ | |
1816 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); | |
1817 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
1818 | ret_val = e1000_write_phy_reg(hw, | |
1819 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1820 | if (ret_val) | |
1821 | return ret_val; | |
1822 | } else { | |
1823 | /* Configure Master and Slave downshift values */ | |
1824 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
2d7edb92 | 1825 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
ee04022a | 1826 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
2d7edb92 | 1827 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
ee04022a AK |
1828 | ret_val = e1000_write_phy_reg(hw, |
1829 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1830 | if (ret_val) | |
1831 | return ret_val; | |
1832 | } | |
2d7edb92 | 1833 | } |
1da177e4 | 1834 | |
2d7edb92 MC |
1835 | /* SW Reset the PHY so all changes take effect */ |
1836 | ret_val = e1000_phy_reset(hw); | |
8fc897b0 | 1837 | if (ret_val) { |
2d7edb92 MC |
1838 | DEBUGOUT("Error Resetting the PHY\n"); |
1839 | return ret_val; | |
1da177e4 LT |
1840 | } |
1841 | ||
2d7edb92 | 1842 | return E1000_SUCCESS; |
1da177e4 LT |
1843 | } |
1844 | ||
2d7edb92 MC |
1845 | /******************************************************************** |
1846 | * Setup auto-negotiation and flow control advertisements, | |
1847 | * and then perform auto-negotiation. | |
1da177e4 LT |
1848 | * |
1849 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
1850 | *********************************************************************/ |
1851 | static int32_t | |
1852 | e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1da177e4 LT |
1853 | { |
1854 | int32_t ret_val; | |
2d7edb92 | 1855 | uint16_t phy_data; |
1da177e4 | 1856 | |
2d7edb92 | 1857 | DEBUGFUNC("e1000_copper_link_autoneg"); |
1da177e4 | 1858 | |
2d7edb92 MC |
1859 | /* Perform some bounds checking on the hw->autoneg_advertised |
1860 | * parameter. If this variable is zero, then set it to the default. | |
1861 | */ | |
1862 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1863 | ||
1864 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
1865 | * by the calling code so we set to advertise full capability. | |
1866 | */ | |
8fc897b0 | 1867 | if (hw->autoneg_advertised == 0) |
2d7edb92 MC |
1868 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
1869 | ||
cd94dd0b AK |
1870 | /* IFE phy only supports 10/100 */ |
1871 | if (hw->phy_type == e1000_phy_ife) | |
1872 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; | |
1873 | ||
2d7edb92 MC |
1874 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
1875 | ret_val = e1000_phy_setup_autoneg(hw); | |
8fc897b0 | 1876 | if (ret_val) { |
2d7edb92 MC |
1877 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
1878 | return ret_val; | |
1879 | } | |
1880 | DEBUGOUT("Restarting Auto-Neg\n"); | |
1881 | ||
1882 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
1883 | * the Auto Neg Restart bit in the PHY control register. | |
1884 | */ | |
1885 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
8fc897b0 | 1886 | if (ret_val) |
1da177e4 LT |
1887 | return ret_val; |
1888 | ||
2d7edb92 MC |
1889 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
1890 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
8fc897b0 | 1891 | if (ret_val) |
1da177e4 LT |
1892 | return ret_val; |
1893 | ||
2d7edb92 MC |
1894 | /* Does the user want to wait for Auto-Neg to complete here, or |
1895 | * check at a later time (for example, callback routine). | |
1896 | */ | |
8fc897b0 | 1897 | if (hw->wait_autoneg_complete) { |
2d7edb92 | 1898 | ret_val = e1000_wait_autoneg(hw); |
8fc897b0 | 1899 | if (ret_val) { |
2d7edb92 MC |
1900 | DEBUGOUT("Error while waiting for autoneg to complete\n"); |
1901 | return ret_val; | |
1902 | } | |
1903 | } | |
1904 | ||
1905 | hw->get_link_status = TRUE; | |
1906 | ||
1907 | return E1000_SUCCESS; | |
1908 | } | |
1909 | ||
2d7edb92 MC |
1910 | /****************************************************************************** |
1911 | * Config the MAC and the PHY after link is up. | |
1912 | * 1) Set up the MAC to the current PHY speed/duplex | |
1913 | * if we are on 82543. If we | |
1914 | * are on newer silicon, we only need to configure | |
1915 | * collision distance in the Transmit Control Register. | |
1916 | * 2) Set up flow control on the MAC to that established with | |
1917 | * the link partner. | |
76c224bc | 1918 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
2d7edb92 MC |
1919 | * |
1920 | * hw - Struct containing variables accessed by shared code | |
1921 | ******************************************************************************/ | |
1922 | static int32_t | |
1923 | e1000_copper_link_postconfig(struct e1000_hw *hw) | |
1924 | { | |
1925 | int32_t ret_val; | |
1926 | DEBUGFUNC("e1000_copper_link_postconfig"); | |
76c224bc | 1927 | |
8fc897b0 | 1928 | if (hw->mac_type >= e1000_82544) { |
2d7edb92 MC |
1929 | e1000_config_collision_dist(hw); |
1930 | } else { | |
1931 | ret_val = e1000_config_mac_to_phy(hw); | |
8fc897b0 | 1932 | if (ret_val) { |
2d7edb92 MC |
1933 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
1934 | return ret_val; | |
1935 | } | |
1936 | } | |
1937 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 1938 | if (ret_val) { |
2d7edb92 MC |
1939 | DEBUGOUT("Error Configuring Flow Control\n"); |
1940 | return ret_val; | |
1941 | } | |
1942 | ||
1943 | /* Config DSP to improve Giga link quality */ | |
8fc897b0 | 1944 | if (hw->phy_type == e1000_phy_igp) { |
2d7edb92 | 1945 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
8fc897b0 | 1946 | if (ret_val) { |
2d7edb92 MC |
1947 | DEBUGOUT("Error Configuring DSP after link up\n"); |
1948 | return ret_val; | |
1949 | } | |
1950 | } | |
76c224bc | 1951 | |
2d7edb92 MC |
1952 | return E1000_SUCCESS; |
1953 | } | |
1954 | ||
1955 | /****************************************************************************** | |
1956 | * Detects which PHY is present and setup the speed and duplex | |
1957 | * | |
1958 | * hw - Struct containing variables accessed by shared code | |
1959 | ******************************************************************************/ | |
1960 | static int32_t | |
1961 | e1000_setup_copper_link(struct e1000_hw *hw) | |
1962 | { | |
1963 | int32_t ret_val; | |
1964 | uint16_t i; | |
1965 | uint16_t phy_data; | |
6418ecc6 | 1966 | uint16_t reg_data; |
2d7edb92 MC |
1967 | |
1968 | DEBUGFUNC("e1000_setup_copper_link"); | |
1969 | ||
cd94dd0b AK |
1970 | switch (hw->mac_type) { |
1971 | case e1000_80003es2lan: | |
1972 | case e1000_ich8lan: | |
1973 | /* Set the mac to wait the maximum time between each | |
1974 | * iteration and increase the max iterations when | |
1975 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ | |
1976 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); | |
1977 | if (ret_val) | |
1978 | return ret_val; | |
1979 | ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
1980 | if (ret_val) | |
1981 | return ret_val; | |
1982 | reg_data |= 0x3F; | |
1983 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
1984 | if (ret_val) | |
1985 | return ret_val; | |
1986 | default: | |
1987 | break; | |
1988 | } | |
1989 | ||
2d7edb92 MC |
1990 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
1991 | ret_val = e1000_copper_link_preconfig(hw); | |
8fc897b0 | 1992 | if (ret_val) |
2d7edb92 MC |
1993 | return ret_val; |
1994 | ||
6418ecc6 JK |
1995 | switch (hw->mac_type) { |
1996 | case e1000_80003es2lan: | |
cd94dd0b AK |
1997 | /* Kumeran registers are written-only */ |
1998 | reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; | |
6418ecc6 JK |
1999 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
2000 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, | |
2001 | reg_data); | |
2002 | if (ret_val) | |
2003 | return ret_val; | |
2004 | break; | |
2005 | default: | |
2006 | break; | |
2007 | } | |
2008 | ||
2d7edb92 | 2009 | if (hw->phy_type == e1000_phy_igp || |
cd94dd0b | 2010 | hw->phy_type == e1000_phy_igp_3 || |
2d7edb92 MC |
2011 | hw->phy_type == e1000_phy_igp_2) { |
2012 | ret_val = e1000_copper_link_igp_setup(hw); | |
8fc897b0 | 2013 | if (ret_val) |
2d7edb92 MC |
2014 | return ret_val; |
2015 | } else if (hw->phy_type == e1000_phy_m88) { | |
2016 | ret_val = e1000_copper_link_mgp_setup(hw); | |
8fc897b0 | 2017 | if (ret_val) |
2d7edb92 | 2018 | return ret_val; |
6418ecc6 JK |
2019 | } else if (hw->phy_type == e1000_phy_gg82563) { |
2020 | ret_val = e1000_copper_link_ggp_setup(hw); | |
8fc897b0 | 2021 | if (ret_val) |
6418ecc6 | 2022 | return ret_val; |
2d7edb92 MC |
2023 | } |
2024 | ||
8fc897b0 | 2025 | if (hw->autoneg) { |
76c224bc AK |
2026 | /* Setup autoneg and flow control advertisement |
2027 | * and perform autonegotiation */ | |
2d7edb92 | 2028 | ret_val = e1000_copper_link_autoneg(hw); |
8fc897b0 | 2029 | if (ret_val) |
76c224bc | 2030 | return ret_val; |
2d7edb92 MC |
2031 | } else { |
2032 | /* PHY will be set to 10H, 10F, 100H,or 100F | |
2033 | * depending on value from forced_speed_duplex. */ | |
2034 | DEBUGOUT("Forcing speed and duplex\n"); | |
2035 | ret_val = e1000_phy_force_speed_duplex(hw); | |
8fc897b0 | 2036 | if (ret_val) { |
2d7edb92 MC |
2037 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
2038 | return ret_val; | |
2039 | } | |
2040 | } | |
2041 | ||
2042 | /* Check link status. Wait up to 100 microseconds for link to become | |
2043 | * valid. | |
2044 | */ | |
8fc897b0 | 2045 | for (i = 0; i < 10; i++) { |
2d7edb92 | 2046 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
8fc897b0 | 2047 | if (ret_val) |
2d7edb92 MC |
2048 | return ret_val; |
2049 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2050 | if (ret_val) |
2d7edb92 MC |
2051 | return ret_val; |
2052 | ||
8fc897b0 | 2053 | if (phy_data & MII_SR_LINK_STATUS) { |
2d7edb92 MC |
2054 | /* Config the MAC and PHY after link is up */ |
2055 | ret_val = e1000_copper_link_postconfig(hw); | |
8fc897b0 | 2056 | if (ret_val) |
2d7edb92 | 2057 | return ret_val; |
76c224bc | 2058 | |
2d7edb92 MC |
2059 | DEBUGOUT("Valid link established!!!\n"); |
2060 | return E1000_SUCCESS; | |
2061 | } | |
2062 | udelay(10); | |
2063 | } | |
2064 | ||
2065 | DEBUGOUT("Unable to establish link!!!\n"); | |
2066 | return E1000_SUCCESS; | |
2067 | } | |
2068 | ||
6418ecc6 JK |
2069 | /****************************************************************************** |
2070 | * Configure the MAC-to-PHY interface for 10/100Mbps | |
2071 | * | |
2072 | * hw - Struct containing variables accessed by shared code | |
2073 | ******************************************************************************/ | |
2074 | static int32_t | |
cd94dd0b | 2075 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) |
6418ecc6 JK |
2076 | { |
2077 | int32_t ret_val = E1000_SUCCESS; | |
2078 | uint32_t tipg; | |
2079 | uint16_t reg_data; | |
2080 | ||
2081 | DEBUGFUNC("e1000_configure_kmrn_for_10_100"); | |
2082 | ||
2083 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
2084 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
2085 | reg_data); | |
2086 | if (ret_val) | |
2087 | return ret_val; | |
2088 | ||
2089 | /* Configure Transmit Inter-Packet Gap */ | |
2090 | tipg = E1000_READ_REG(hw, TIPG); | |
2091 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
2092 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | |
2093 | E1000_WRITE_REG(hw, TIPG, tipg); | |
2094 | ||
cd94dd0b AK |
2095 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
2096 | ||
2097 | if (ret_val) | |
2098 | return ret_val; | |
2099 | ||
2100 | if (duplex == HALF_DUPLEX) | |
2101 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
2102 | else | |
2103 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2104 | ||
2105 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
2106 | ||
6418ecc6 JK |
2107 | return ret_val; |
2108 | } | |
2109 | ||
2110 | static int32_t | |
2111 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) | |
2112 | { | |
2113 | int32_t ret_val = E1000_SUCCESS; | |
2114 | uint16_t reg_data; | |
2115 | uint32_t tipg; | |
2116 | ||
2117 | DEBUGFUNC("e1000_configure_kmrn_for_1000"); | |
2118 | ||
2119 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | |
2120 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
2121 | reg_data); | |
2122 | if (ret_val) | |
2123 | return ret_val; | |
2124 | ||
2125 | /* Configure Transmit Inter-Packet Gap */ | |
2126 | tipg = E1000_READ_REG(hw, TIPG); | |
2127 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
2128 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
2129 | E1000_WRITE_REG(hw, TIPG, tipg); | |
2130 | ||
cd94dd0b AK |
2131 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
2132 | ||
2133 | if (ret_val) | |
2134 | return ret_val; | |
2135 | ||
2136 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2137 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
2138 | ||
6418ecc6 JK |
2139 | return ret_val; |
2140 | } | |
2141 | ||
2d7edb92 MC |
2142 | /****************************************************************************** |
2143 | * Configures PHY autoneg and flow control advertisement settings | |
2144 | * | |
2145 | * hw - Struct containing variables accessed by shared code | |
2146 | ******************************************************************************/ | |
2147 | int32_t | |
2148 | e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
2149 | { | |
2150 | int32_t ret_val; | |
2151 | uint16_t mii_autoneg_adv_reg; | |
2152 | uint16_t mii_1000t_ctrl_reg; | |
2153 | ||
2154 | DEBUGFUNC("e1000_phy_setup_autoneg"); | |
2155 | ||
2156 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
2157 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
8fc897b0 | 2158 | if (ret_val) |
2d7edb92 MC |
2159 | return ret_val; |
2160 | ||
cd94dd0b AK |
2161 | if (hw->phy_type != e1000_phy_ife) { |
2162 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
2163 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
2164 | if (ret_val) | |
2165 | return ret_val; | |
2166 | } else | |
2167 | mii_1000t_ctrl_reg=0; | |
2d7edb92 MC |
2168 | |
2169 | /* Need to parse both autoneg_advertised and fc and set up | |
2170 | * the appropriate PHY registers. First we will parse for | |
1da177e4 LT |
2171 | * autoneg_advertised software override. Since we can advertise |
2172 | * a plethora of combinations, we need to check each bit | |
2173 | * individually. | |
2174 | */ | |
2175 | ||
2176 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
2177 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
2178 | * the 1000Base-T Control Register (Address 9). | |
2179 | */ | |
2180 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
2181 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
2182 | ||
2183 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); | |
2184 | ||
2185 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
8fc897b0 | 2186 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
1da177e4 LT |
2187 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
2188 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
2189 | } | |
2190 | ||
2191 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
8fc897b0 | 2192 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
1da177e4 LT |
2193 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
2194 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
2195 | } | |
2196 | ||
2197 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
8fc897b0 | 2198 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
1da177e4 LT |
2199 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
2200 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
2201 | } | |
2202 | ||
2203 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
8fc897b0 | 2204 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
1da177e4 LT |
2205 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
2206 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
2207 | } | |
2208 | ||
2209 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
8fc897b0 | 2210 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
1da177e4 LT |
2211 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
2212 | } | |
2213 | ||
2214 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
8fc897b0 | 2215 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
1da177e4 LT |
2216 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
2217 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
cd94dd0b AK |
2218 | if (hw->phy_type == e1000_phy_ife) { |
2219 | DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); | |
2220 | } | |
1da177e4 LT |
2221 | } |
2222 | ||
2223 | /* Check for a software override of the flow control settings, and | |
2224 | * setup the PHY advertisement registers accordingly. If | |
2225 | * auto-negotiation is enabled, then software will have to set the | |
2226 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
2227 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
2228 | * | |
2229 | * The possible values of the "fc" parameter are: | |
2230 | * 0: Flow control is completely disabled | |
2231 | * 1: Rx flow control is enabled (we can receive pause frames | |
2232 | * but not send pause frames). | |
2233 | * 2: Tx flow control is enabled (we can send pause frames | |
2234 | * but we do not support receiving pause frames). | |
2235 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
2236 | * other: No software override. The flow control configuration | |
2237 | * in the EEPROM is used. | |
2238 | */ | |
2239 | switch (hw->fc) { | |
11241b10 | 2240 | case E1000_FC_NONE: /* 0 */ |
1da177e4 LT |
2241 | /* Flow control (RX & TX) is completely disabled by a |
2242 | * software over-ride. | |
2243 | */ | |
2244 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2245 | break; | |
11241b10 | 2246 | case E1000_FC_RX_PAUSE: /* 1 */ |
1da177e4 LT |
2247 | /* RX Flow control is enabled, and TX Flow control is |
2248 | * disabled, by a software over-ride. | |
2249 | */ | |
2250 | /* Since there really isn't a way to advertise that we are | |
2251 | * capable of RX Pause ONLY, we will advertise that we | |
2252 | * support both symmetric and asymmetric RX PAUSE. Later | |
2253 | * (in e1000_config_fc_after_link_up) we will disable the | |
2254 | *hw's ability to send PAUSE frames. | |
2255 | */ | |
2256 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2257 | break; | |
11241b10 | 2258 | case E1000_FC_TX_PAUSE: /* 2 */ |
1da177e4 LT |
2259 | /* TX Flow control is enabled, and RX Flow control is |
2260 | * disabled, by a software over-ride. | |
2261 | */ | |
2262 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
2263 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
2264 | break; | |
11241b10 | 2265 | case E1000_FC_FULL: /* 3 */ |
1da177e4 LT |
2266 | /* Flow control (both RX and TX) is enabled by a software |
2267 | * over-ride. | |
2268 | */ | |
2269 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2270 | break; | |
2271 | default: | |
2272 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2273 | return -E1000_ERR_CONFIG; | |
2274 | } | |
2275 | ||
2276 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
8fc897b0 | 2277 | if (ret_val) |
1da177e4 LT |
2278 | return ret_val; |
2279 | ||
2280 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
2281 | ||
cd94dd0b AK |
2282 | if (hw->phy_type != e1000_phy_ife) { |
2283 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | |
2284 | if (ret_val) | |
2285 | return ret_val; | |
2286 | } | |
1da177e4 LT |
2287 | |
2288 | return E1000_SUCCESS; | |
2289 | } | |
2290 | ||
2291 | /****************************************************************************** | |
2292 | * Force PHY speed and duplex settings to hw->forced_speed_duplex | |
2293 | * | |
2294 | * hw - Struct containing variables accessed by shared code | |
2295 | ******************************************************************************/ | |
2296 | static int32_t | |
2297 | e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2298 | { | |
2299 | uint32_t ctrl; | |
2300 | int32_t ret_val; | |
2301 | uint16_t mii_ctrl_reg; | |
2302 | uint16_t mii_status_reg; | |
2303 | uint16_t phy_data; | |
2304 | uint16_t i; | |
2305 | ||
2306 | DEBUGFUNC("e1000_phy_force_speed_duplex"); | |
2307 | ||
2308 | /* Turn off Flow control if we are forcing speed and duplex. */ | |
11241b10 | 2309 | hw->fc = E1000_FC_NONE; |
1da177e4 LT |
2310 | |
2311 | DEBUGOUT1("hw->fc = %d\n", hw->fc); | |
2312 | ||
2313 | /* Read the Device Control Register. */ | |
2314 | ctrl = E1000_READ_REG(hw, CTRL); | |
2315 | ||
2316 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ | |
2317 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2318 | ctrl &= ~(DEVICE_SPEED_MASK); | |
2319 | ||
2320 | /* Clear the Auto Speed Detect Enable bit. */ | |
2321 | ctrl &= ~E1000_CTRL_ASDE; | |
2322 | ||
2323 | /* Read the MII Control Register. */ | |
2324 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); | |
8fc897b0 | 2325 | if (ret_val) |
1da177e4 LT |
2326 | return ret_val; |
2327 | ||
2328 | /* We need to disable autoneg in order to force link and duplex. */ | |
2329 | ||
2330 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; | |
2331 | ||
2332 | /* Are we forcing Full or Half Duplex? */ | |
8fc897b0 AK |
2333 | if (hw->forced_speed_duplex == e1000_100_full || |
2334 | hw->forced_speed_duplex == e1000_10_full) { | |
1da177e4 LT |
2335 | /* We want to force full duplex so we SET the full duplex bits in the |
2336 | * Device and MII Control Registers. | |
2337 | */ | |
2338 | ctrl |= E1000_CTRL_FD; | |
2339 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; | |
2340 | DEBUGOUT("Full Duplex\n"); | |
2341 | } else { | |
2342 | /* We want to force half duplex so we CLEAR the full duplex bits in | |
2343 | * the Device and MII Control Registers. | |
2344 | */ | |
2345 | ctrl &= ~E1000_CTRL_FD; | |
2346 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; | |
2347 | DEBUGOUT("Half Duplex\n"); | |
2348 | } | |
2349 | ||
2350 | /* Are we forcing 100Mbps??? */ | |
8fc897b0 | 2351 | if (hw->forced_speed_duplex == e1000_100_full || |
1da177e4 LT |
2352 | hw->forced_speed_duplex == e1000_100_half) { |
2353 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ | |
2354 | ctrl |= E1000_CTRL_SPD_100; | |
2355 | mii_ctrl_reg |= MII_CR_SPEED_100; | |
2356 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
2357 | DEBUGOUT("Forcing 100mb "); | |
2358 | } else { | |
2359 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ | |
2360 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
2361 | mii_ctrl_reg |= MII_CR_SPEED_10; | |
2362 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
2363 | DEBUGOUT("Forcing 10mb "); | |
2364 | } | |
2365 | ||
2366 | e1000_config_collision_dist(hw); | |
2367 | ||
2368 | /* Write the configured values back to the Device Control Reg. */ | |
2369 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2370 | ||
6418ecc6 JK |
2371 | if ((hw->phy_type == e1000_phy_m88) || |
2372 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 | 2373 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
8fc897b0 | 2374 | if (ret_val) |
1da177e4 LT |
2375 | return ret_val; |
2376 | ||
2377 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
2378 | * forced whenever speed are duplex are forced. | |
2379 | */ | |
2380 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
2381 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2382 | if (ret_val) |
1da177e4 LT |
2383 | return ret_val; |
2384 | ||
2385 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | |
2386 | ||
2387 | /* Need to reset the PHY or these changes will be ignored */ | |
2388 | mii_ctrl_reg |= MII_CR_RESET; | |
90fb5135 | 2389 | |
cd94dd0b AK |
2390 | /* Disable MDI-X support for 10/100 */ |
2391 | } else if (hw->phy_type == e1000_phy_ife) { | |
2392 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | |
2393 | if (ret_val) | |
2394 | return ret_val; | |
2395 | ||
2396 | phy_data &= ~IFE_PMC_AUTO_MDIX; | |
2397 | phy_data &= ~IFE_PMC_FORCE_MDIX; | |
2398 | ||
2399 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); | |
2400 | if (ret_val) | |
2401 | return ret_val; | |
90fb5135 | 2402 | |
1da177e4 LT |
2403 | } else { |
2404 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
2405 | * forced whenever speed or duplex are forced. | |
2406 | */ | |
2407 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
8fc897b0 | 2408 | if (ret_val) |
1da177e4 LT |
2409 | return ret_val; |
2410 | ||
2411 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
2412 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2413 | ||
2414 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
8fc897b0 | 2415 | if (ret_val) |
1da177e4 LT |
2416 | return ret_val; |
2417 | } | |
2418 | ||
2419 | /* Write back the modified PHY MII control register. */ | |
2420 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); | |
8fc897b0 | 2421 | if (ret_val) |
1da177e4 LT |
2422 | return ret_val; |
2423 | ||
2424 | udelay(1); | |
2425 | ||
2426 | /* The wait_autoneg_complete flag may be a little misleading here. | |
2427 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | |
2428 | * But we do want to delay for a period while forcing only so we | |
2429 | * don't generate false No Link messages. So we will wait here | |
2430 | * only if the user has set wait_autoneg_complete to 1, which is | |
2431 | * the default. | |
2432 | */ | |
8fc897b0 | 2433 | if (hw->wait_autoneg_complete) { |
1da177e4 LT |
2434 | /* We will wait for autoneg to complete. */ |
2435 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); | |
2436 | mii_status_reg = 0; | |
2437 | ||
2438 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
8fc897b0 | 2439 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
2440 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2441 | * to be set. | |
2442 | */ | |
2443 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2444 | if (ret_val) |
1da177e4 LT |
2445 | return ret_val; |
2446 | ||
2447 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2448 | if (ret_val) |
1da177e4 LT |
2449 | return ret_val; |
2450 | ||
8fc897b0 | 2451 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
f8ec4733 | 2452 | msleep(100); |
1da177e4 | 2453 | } |
8fc897b0 | 2454 | if ((i == 0) && |
6418ecc6 JK |
2455 | ((hw->phy_type == e1000_phy_m88) || |
2456 | (hw->phy_type == e1000_phy_gg82563))) { | |
1da177e4 LT |
2457 | /* We didn't get link. Reset the DSP and wait again for link. */ |
2458 | ret_val = e1000_phy_reset_dsp(hw); | |
8fc897b0 | 2459 | if (ret_val) { |
1da177e4 LT |
2460 | DEBUGOUT("Error Resetting PHY DSP\n"); |
2461 | return ret_val; | |
2462 | } | |
2463 | } | |
2464 | /* This loop will early-out if the link condition has been met. */ | |
8fc897b0 AK |
2465 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
2466 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | |
f8ec4733 | 2467 | msleep(100); |
1da177e4 LT |
2468 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2469 | * to be set. | |
2470 | */ | |
2471 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2472 | if (ret_val) |
1da177e4 LT |
2473 | return ret_val; |
2474 | ||
2475 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2476 | if (ret_val) |
1da177e4 LT |
2477 | return ret_val; |
2478 | } | |
2479 | } | |
2480 | ||
2481 | if (hw->phy_type == e1000_phy_m88) { | |
2482 | /* Because we reset the PHY above, we need to re-force TX_CLK in the | |
2483 | * Extended PHY Specific Control Register to 25MHz clock. This value | |
2484 | * defaults back to a 2.5MHz clock when the PHY is reset. | |
2485 | */ | |
2486 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 2487 | if (ret_val) |
1da177e4 LT |
2488 | return ret_val; |
2489 | ||
2490 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
2491 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2492 | if (ret_val) |
1da177e4 LT |
2493 | return ret_val; |
2494 | ||
2495 | /* In addition, because of the s/w reset above, we need to enable CRS on | |
2496 | * TX. This must be set for both full and half duplex operation. | |
2497 | */ | |
2498 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 2499 | if (ret_val) |
1da177e4 LT |
2500 | return ret_val; |
2501 | ||
2502 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
2503 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2504 | if (ret_val) |
1da177e4 LT |
2505 | return ret_val; |
2506 | ||
8fc897b0 AK |
2507 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
2508 | (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || | |
2509 | hw->forced_speed_duplex == e1000_10_half)) { | |
1da177e4 | 2510 | ret_val = e1000_polarity_reversal_workaround(hw); |
8fc897b0 | 2511 | if (ret_val) |
1da177e4 LT |
2512 | return ret_val; |
2513 | } | |
6418ecc6 JK |
2514 | } else if (hw->phy_type == e1000_phy_gg82563) { |
2515 | /* The TX_CLK of the Extended PHY Specific Control Register defaults | |
2516 | * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if | |
2517 | * we're not in a forced 10/duplex configuration. */ | |
2518 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
2519 | if (ret_val) | |
2520 | return ret_val; | |
2521 | ||
2522 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
2523 | if ((hw->forced_speed_duplex == e1000_10_full) || | |
2524 | (hw->forced_speed_duplex == e1000_10_half)) | |
2525 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; | |
2526 | else | |
2527 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; | |
2528 | ||
2529 | /* Also due to the reset, we need to enable CRS on Tx. */ | |
2530 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
2531 | ||
2532 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
2533 | if (ret_val) | |
2534 | return ret_val; | |
1da177e4 LT |
2535 | } |
2536 | return E1000_SUCCESS; | |
2537 | } | |
2538 | ||
2539 | /****************************************************************************** | |
2540 | * Sets the collision distance in the Transmit Control register | |
2541 | * | |
2542 | * hw - Struct containing variables accessed by shared code | |
2543 | * | |
2544 | * Link should have been established previously. Reads the speed and duplex | |
2545 | * information from the Device Status register. | |
2546 | ******************************************************************************/ | |
2547 | void | |
2548 | e1000_config_collision_dist(struct e1000_hw *hw) | |
2549 | { | |
0fadb059 | 2550 | uint32_t tctl, coll_dist; |
1da177e4 LT |
2551 | |
2552 | DEBUGFUNC("e1000_config_collision_dist"); | |
2553 | ||
0fadb059 JK |
2554 | if (hw->mac_type < e1000_82543) |
2555 | coll_dist = E1000_COLLISION_DISTANCE_82542; | |
2556 | else | |
2557 | coll_dist = E1000_COLLISION_DISTANCE; | |
2558 | ||
1da177e4 LT |
2559 | tctl = E1000_READ_REG(hw, TCTL); |
2560 | ||
2561 | tctl &= ~E1000_TCTL_COLD; | |
0fadb059 | 2562 | tctl |= coll_dist << E1000_COLD_SHIFT; |
1da177e4 LT |
2563 | |
2564 | E1000_WRITE_REG(hw, TCTL, tctl); | |
2565 | E1000_WRITE_FLUSH(hw); | |
2566 | } | |
2567 | ||
2568 | /****************************************************************************** | |
2569 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
2570 | * | |
2571 | * hw - Struct containing variables accessed by shared code | |
2572 | * mii_reg - data to write to the MII control register | |
2573 | * | |
2574 | * The contents of the PHY register containing the needed information need to | |
2575 | * be passed in. | |
2576 | ******************************************************************************/ | |
2577 | static int32_t | |
2578 | e1000_config_mac_to_phy(struct e1000_hw *hw) | |
2579 | { | |
2580 | uint32_t ctrl; | |
2581 | int32_t ret_val; | |
2582 | uint16_t phy_data; | |
2583 | ||
2584 | DEBUGFUNC("e1000_config_mac_to_phy"); | |
2585 | ||
76c224bc | 2586 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
2d7edb92 MC |
2587 | * MAC speed/duplex configuration.*/ |
2588 | if (hw->mac_type >= e1000_82544) | |
2589 | return E1000_SUCCESS; | |
2590 | ||
1da177e4 LT |
2591 | /* Read the Device Control Register and set the bits to Force Speed |
2592 | * and Duplex. | |
2593 | */ | |
2594 | ctrl = E1000_READ_REG(hw, CTRL); | |
2595 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2596 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); | |
2597 | ||
2598 | /* Set up duplex in the Device Control and Transmit Control | |
2599 | * registers depending on negotiated values. | |
2600 | */ | |
2d7edb92 | 2601 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
8fc897b0 | 2602 | if (ret_val) |
2d7edb92 | 2603 | return ret_val; |
1da177e4 | 2604 | |
8fc897b0 | 2605 | if (phy_data & M88E1000_PSSR_DPLX) |
2d7edb92 | 2606 | ctrl |= E1000_CTRL_FD; |
76c224bc | 2607 | else |
2d7edb92 | 2608 | ctrl &= ~E1000_CTRL_FD; |
1da177e4 | 2609 | |
2d7edb92 | 2610 | e1000_config_collision_dist(hw); |
1da177e4 | 2611 | |
2d7edb92 MC |
2612 | /* Set up speed in the Device Control register depending on |
2613 | * negotiated values. | |
2614 | */ | |
8fc897b0 | 2615 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
2d7edb92 | 2616 | ctrl |= E1000_CTRL_SPD_1000; |
8fc897b0 | 2617 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
2d7edb92 | 2618 | ctrl |= E1000_CTRL_SPD_100; |
1da177e4 | 2619 | |
1da177e4 LT |
2620 | /* Write the configured values back to the Device Control Reg. */ |
2621 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2622 | return E1000_SUCCESS; | |
2623 | } | |
2624 | ||
2625 | /****************************************************************************** | |
2626 | * Forces the MAC's flow control settings. | |
2627 | * | |
2628 | * hw - Struct containing variables accessed by shared code | |
2629 | * | |
2630 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
2631 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
2632 | * software when a Copper PHY is used because autonegotiation is managed | |
2633 | * by the PHY rather than the MAC. Software must also configure these | |
2634 | * bits when link is forced on a fiber connection. | |
2635 | *****************************************************************************/ | |
2636 | int32_t | |
2637 | e1000_force_mac_fc(struct e1000_hw *hw) | |
2638 | { | |
2639 | uint32_t ctrl; | |
2640 | ||
2641 | DEBUGFUNC("e1000_force_mac_fc"); | |
2642 | ||
2643 | /* Get the current configuration of the Device Control Register */ | |
2644 | ctrl = E1000_READ_REG(hw, CTRL); | |
2645 | ||
2646 | /* Because we didn't get link via the internal auto-negotiation | |
2647 | * mechanism (we either forced link or we got link via PHY | |
2648 | * auto-neg), we have to manually enable/disable transmit an | |
2649 | * receive flow control. | |
2650 | * | |
2651 | * The "Case" statement below enables/disable flow control | |
2652 | * according to the "hw->fc" parameter. | |
2653 | * | |
2654 | * The possible values of the "fc" parameter are: | |
2655 | * 0: Flow control is completely disabled | |
2656 | * 1: Rx flow control is enabled (we can receive pause | |
2657 | * frames but not send pause frames). | |
2658 | * 2: Tx flow control is enabled (we can send pause frames | |
2659 | * frames but we do not receive pause frames). | |
2660 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
2661 | * other: No other values should be possible at this point. | |
2662 | */ | |
2663 | ||
2664 | switch (hw->fc) { | |
11241b10 | 2665 | case E1000_FC_NONE: |
1da177e4 LT |
2666 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
2667 | break; | |
11241b10 | 2668 | case E1000_FC_RX_PAUSE: |
1da177e4 LT |
2669 | ctrl &= (~E1000_CTRL_TFCE); |
2670 | ctrl |= E1000_CTRL_RFCE; | |
2671 | break; | |
11241b10 | 2672 | case E1000_FC_TX_PAUSE: |
1da177e4 LT |
2673 | ctrl &= (~E1000_CTRL_RFCE); |
2674 | ctrl |= E1000_CTRL_TFCE; | |
2675 | break; | |
11241b10 | 2676 | case E1000_FC_FULL: |
1da177e4 LT |
2677 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
2678 | break; | |
2679 | default: | |
2680 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2681 | return -E1000_ERR_CONFIG; | |
2682 | } | |
2683 | ||
2684 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
8fc897b0 | 2685 | if (hw->mac_type == e1000_82542_rev2_0) |
1da177e4 LT |
2686 | ctrl &= (~E1000_CTRL_TFCE); |
2687 | ||
2688 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2689 | return E1000_SUCCESS; | |
2690 | } | |
2691 | ||
2692 | /****************************************************************************** | |
2693 | * Configures flow control settings after link is established | |
2694 | * | |
2695 | * hw - Struct containing variables accessed by shared code | |
2696 | * | |
2697 | * Should be called immediately after a valid link has been established. | |
2698 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
2699 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
2700 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
2701 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
2702 | *****************************************************************************/ | |
3ad2cc67 | 2703 | static int32_t |
1da177e4 LT |
2704 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
2705 | { | |
2706 | int32_t ret_val; | |
2707 | uint16_t mii_status_reg; | |
2708 | uint16_t mii_nway_adv_reg; | |
2709 | uint16_t mii_nway_lp_ability_reg; | |
2710 | uint16_t speed; | |
2711 | uint16_t duplex; | |
2712 | ||
2713 | DEBUGFUNC("e1000_config_fc_after_link_up"); | |
2714 | ||
2715 | /* Check for the case where we have fiber media and auto-neg failed | |
2716 | * so we had to force link. In this case, we need to force the | |
2717 | * configuration of the MAC to match the "fc" parameter. | |
2718 | */ | |
8fc897b0 AK |
2719 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
2720 | ((hw->media_type == e1000_media_type_internal_serdes) && | |
2721 | (hw->autoneg_failed)) || | |
2722 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { | |
1da177e4 | 2723 | ret_val = e1000_force_mac_fc(hw); |
8fc897b0 | 2724 | if (ret_val) { |
1da177e4 LT |
2725 | DEBUGOUT("Error forcing flow control settings\n"); |
2726 | return ret_val; | |
2727 | } | |
2728 | } | |
2729 | ||
2730 | /* Check for the case where we have copper media and auto-neg is | |
2731 | * enabled. In this case, we need to check and see if Auto-Neg | |
2732 | * has completed, and if so, how the PHY and link partner has | |
2733 | * flow control configured. | |
2734 | */ | |
8fc897b0 | 2735 | if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
1da177e4 LT |
2736 | /* Read the MII Status Register and check to see if AutoNeg |
2737 | * has completed. We read this twice because this reg has | |
2738 | * some "sticky" (latched) bits. | |
2739 | */ | |
2740 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2741 | if (ret_val) |
1da177e4 LT |
2742 | return ret_val; |
2743 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2744 | if (ret_val) |
1da177e4 LT |
2745 | return ret_val; |
2746 | ||
8fc897b0 | 2747 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
1da177e4 LT |
2748 | /* The AutoNeg process has completed, so we now need to |
2749 | * read both the Auto Negotiation Advertisement Register | |
2750 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
2751 | * Register (Address 5) to determine how flow control was | |
2752 | * negotiated. | |
2753 | */ | |
2754 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, | |
2755 | &mii_nway_adv_reg); | |
8fc897b0 | 2756 | if (ret_val) |
1da177e4 LT |
2757 | return ret_val; |
2758 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, | |
2759 | &mii_nway_lp_ability_reg); | |
8fc897b0 | 2760 | if (ret_val) |
1da177e4 LT |
2761 | return ret_val; |
2762 | ||
2763 | /* Two bits in the Auto Negotiation Advertisement Register | |
2764 | * (Address 4) and two bits in the Auto Negotiation Base | |
2765 | * Page Ability Register (Address 5) determine flow control | |
2766 | * for both the PHY and the link partner. The following | |
2767 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
2768 | * 1999, describes these PAUSE resolution bits and how flow | |
2769 | * control is determined based upon these settings. | |
2770 | * NOTE: DC = Don't Care | |
2771 | * | |
2772 | * LOCAL DEVICE | LINK PARTNER | |
2773 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
2774 | *-------|---------|-------|---------|-------------------- | |
11241b10 JK |
2775 | * 0 | 0 | DC | DC | E1000_FC_NONE |
2776 | * 0 | 1 | 0 | DC | E1000_FC_NONE | |
2777 | * 0 | 1 | 1 | 0 | E1000_FC_NONE | |
2778 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE | |
2779 | * 1 | 0 | 0 | DC | E1000_FC_NONE | |
2780 | * 1 | DC | 1 | DC | E1000_FC_FULL | |
2781 | * 1 | 1 | 0 | 0 | E1000_FC_NONE | |
2782 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE | |
1da177e4 LT |
2783 | * |
2784 | */ | |
2785 | /* Are both PAUSE bits set to 1? If so, this implies | |
2786 | * Symmetric Flow Control is enabled at both ends. The | |
2787 | * ASM_DIR bits are irrelevant per the spec. | |
2788 | * | |
2789 | * For Symmetric Flow Control: | |
2790 | * | |
2791 | * LOCAL DEVICE | LINK PARTNER | |
2792 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2793 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2794 | * 1 | DC | 1 | DC | E1000_FC_FULL |
1da177e4 LT |
2795 | * |
2796 | */ | |
8fc897b0 AK |
2797 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2798 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
1da177e4 LT |
2799 | /* Now we need to check if the user selected RX ONLY |
2800 | * of pause frames. In this case, we had to advertise | |
2801 | * FULL flow control because we could not advertise RX | |
2802 | * ONLY. Hence, we must now check to see if we need to | |
2803 | * turn OFF the TRANSMISSION of PAUSE frames. | |
2804 | */ | |
11241b10 JK |
2805 | if (hw->original_fc == E1000_FC_FULL) { |
2806 | hw->fc = E1000_FC_FULL; | |
a42a507c | 2807 | DEBUGOUT("Flow Control = FULL.\n"); |
1da177e4 | 2808 | } else { |
11241b10 | 2809 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2810 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2811 | } |
2812 | } | |
2813 | /* For receiving PAUSE frames ONLY. | |
2814 | * | |
2815 | * LOCAL DEVICE | LINK PARTNER | |
2816 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2817 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2818 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
1da177e4 LT |
2819 | * |
2820 | */ | |
8fc897b0 AK |
2821 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2822 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2823 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2824 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
11241b10 | 2825 | hw->fc = E1000_FC_TX_PAUSE; |
a42a507c | 2826 | DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
1da177e4 LT |
2827 | } |
2828 | /* For transmitting PAUSE frames ONLY. | |
2829 | * | |
2830 | * LOCAL DEVICE | LINK PARTNER | |
2831 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2832 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2833 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
1da177e4 LT |
2834 | * |
2835 | */ | |
8fc897b0 AK |
2836 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2837 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2838 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2839 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
11241b10 | 2840 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2841 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2842 | } |
2843 | /* Per the IEEE spec, at this point flow control should be | |
2844 | * disabled. However, we want to consider that we could | |
2845 | * be connected to a legacy switch that doesn't advertise | |
2846 | * desired flow control, but can be forced on the link | |
2847 | * partner. So if we advertised no flow control, that is | |
2848 | * what we will resolve to. If we advertised some kind of | |
2849 | * receive capability (Rx Pause Only or Full Flow Control) | |
2850 | * and the link partner advertised none, we will configure | |
2851 | * ourselves to enable Rx Flow Control only. We can do | |
2852 | * this safely for two reasons: If the link partner really | |
2853 | * didn't want flow control enabled, and we enable Rx, no | |
2854 | * harm done since we won't be receiving any PAUSE frames | |
2855 | * anyway. If the intent on the link partner was to have | |
2856 | * flow control enabled, then by us enabling RX only, we | |
2857 | * can at least receive pause frames and process them. | |
2858 | * This is a good idea because in most cases, since we are | |
2859 | * predominantly a server NIC, more times than not we will | |
2860 | * be asked to delay transmission of packets than asking | |
2861 | * our link partner to pause transmission of frames. | |
2862 | */ | |
11241b10 JK |
2863 | else if ((hw->original_fc == E1000_FC_NONE || |
2864 | hw->original_fc == E1000_FC_TX_PAUSE) || | |
8fc897b0 | 2865 | hw->fc_strict_ieee) { |
11241b10 | 2866 | hw->fc = E1000_FC_NONE; |
a42a507c | 2867 | DEBUGOUT("Flow Control = NONE.\n"); |
1da177e4 | 2868 | } else { |
11241b10 | 2869 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2870 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2871 | } |
2872 | ||
2873 | /* Now we need to do one last check... If we auto- | |
2874 | * negotiated to HALF DUPLEX, flow control should not be | |
2875 | * enabled per IEEE 802.3 spec. | |
2876 | */ | |
2877 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
8fc897b0 | 2878 | if (ret_val) { |
1da177e4 LT |
2879 | DEBUGOUT("Error getting link speed and duplex\n"); |
2880 | return ret_val; | |
2881 | } | |
2882 | ||
8fc897b0 | 2883 | if (duplex == HALF_DUPLEX) |
11241b10 | 2884 | hw->fc = E1000_FC_NONE; |
1da177e4 LT |
2885 | |
2886 | /* Now we call a subroutine to actually force the MAC | |
2887 | * controller to use the correct flow control settings. | |
2888 | */ | |
2889 | ret_val = e1000_force_mac_fc(hw); | |
8fc897b0 | 2890 | if (ret_val) { |
1da177e4 LT |
2891 | DEBUGOUT("Error forcing flow control settings\n"); |
2892 | return ret_val; | |
2893 | } | |
2894 | } else { | |
a42a507c | 2895 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
1da177e4 LT |
2896 | } |
2897 | } | |
2898 | return E1000_SUCCESS; | |
2899 | } | |
2900 | ||
2901 | /****************************************************************************** | |
2902 | * Checks to see if the link status of the hardware has changed. | |
2903 | * | |
2904 | * hw - Struct containing variables accessed by shared code | |
2905 | * | |
2906 | * Called by any function that needs to check the link status of the adapter. | |
2907 | *****************************************************************************/ | |
2908 | int32_t | |
2909 | e1000_check_for_link(struct e1000_hw *hw) | |
2910 | { | |
2911 | uint32_t rxcw = 0; | |
2912 | uint32_t ctrl; | |
2913 | uint32_t status; | |
2914 | uint32_t rctl; | |
2915 | uint32_t icr; | |
2916 | uint32_t signal = 0; | |
2917 | int32_t ret_val; | |
2918 | uint16_t phy_data; | |
2919 | ||
2920 | DEBUGFUNC("e1000_check_for_link"); | |
2921 | ||
2922 | ctrl = E1000_READ_REG(hw, CTRL); | |
2923 | status = E1000_READ_REG(hw, STATUS); | |
2924 | ||
2925 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be | |
2926 | * set when the optics detect a signal. On older adapters, it will be | |
2927 | * cleared when there is a signal. This applies to fiber media only. | |
2928 | */ | |
8fc897b0 AK |
2929 | if ((hw->media_type == e1000_media_type_fiber) || |
2930 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
1da177e4 LT |
2931 | rxcw = E1000_READ_REG(hw, RXCW); |
2932 | ||
8fc897b0 | 2933 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 | 2934 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
8fc897b0 | 2935 | if (status & E1000_STATUS_LU) |
1da177e4 LT |
2936 | hw->get_link_status = FALSE; |
2937 | } | |
2938 | } | |
2939 | ||
2940 | /* If we have a copper PHY then we only want to go out to the PHY | |
2941 | * registers to see if Auto-Neg has completed and/or if our link | |
2942 | * status has changed. The get_link_status flag will be set if we | |
2943 | * receive a Link Status Change interrupt or we have Rx Sequence | |
2944 | * Errors. | |
2945 | */ | |
8fc897b0 | 2946 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
1da177e4 LT |
2947 | /* First we want to see if the MII Status Register reports |
2948 | * link. If so, then we want to get the current speed/duplex | |
2949 | * of the PHY. | |
2950 | * Read the register twice since the link bit is sticky. | |
2951 | */ | |
2952 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2953 | if (ret_val) |
1da177e4 LT |
2954 | return ret_val; |
2955 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2956 | if (ret_val) |
1da177e4 LT |
2957 | return ret_val; |
2958 | ||
8fc897b0 | 2959 | if (phy_data & MII_SR_LINK_STATUS) { |
1da177e4 LT |
2960 | hw->get_link_status = FALSE; |
2961 | /* Check if there was DownShift, must be checked immediately after | |
2962 | * link-up */ | |
2963 | e1000_check_downshift(hw); | |
2964 | ||
2965 | /* If we are on 82544 or 82543 silicon and speed/duplex | |
2966 | * are forced to 10H or 10F, then we will implement the polarity | |
2967 | * reversal workaround. We disable interrupts first, and upon | |
2968 | * returning, place the devices interrupt state to its previous | |
2969 | * value except for the link status change interrupt which will | |
2970 | * happen due to the execution of this workaround. | |
2971 | */ | |
2972 | ||
8fc897b0 AK |
2973 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
2974 | (!hw->autoneg) && | |
2975 | (hw->forced_speed_duplex == e1000_10_full || | |
2976 | hw->forced_speed_duplex == e1000_10_half)) { | |
1da177e4 LT |
2977 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
2978 | ret_val = e1000_polarity_reversal_workaround(hw); | |
2979 | icr = E1000_READ_REG(hw, ICR); | |
2980 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); | |
2981 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); | |
2982 | } | |
2983 | ||
2984 | } else { | |
2985 | /* No link detected */ | |
2986 | e1000_config_dsp_after_link_change(hw, FALSE); | |
2987 | return 0; | |
2988 | } | |
2989 | ||
2990 | /* If we are forcing speed/duplex, then we simply return since | |
2991 | * we have already determined whether we have link or not. | |
2992 | */ | |
8fc897b0 | 2993 | if (!hw->autoneg) return -E1000_ERR_CONFIG; |
1da177e4 LT |
2994 | |
2995 | /* optimize the dsp settings for the igp phy */ | |
2996 | e1000_config_dsp_after_link_change(hw, TRUE); | |
2997 | ||
2998 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
2999 | * have Si on board that is 82544 or newer, Auto | |
3000 | * Speed Detection takes care of MAC speed/duplex | |
3001 | * configuration. So we only need to configure Collision | |
3002 | * Distance in the MAC. Otherwise, we need to force | |
3003 | * speed/duplex on the MAC to the current PHY speed/duplex | |
3004 | * settings. | |
3005 | */ | |
8fc897b0 | 3006 | if (hw->mac_type >= e1000_82544) |
1da177e4 LT |
3007 | e1000_config_collision_dist(hw); |
3008 | else { | |
3009 | ret_val = e1000_config_mac_to_phy(hw); | |
8fc897b0 | 3010 | if (ret_val) { |
1da177e4 LT |
3011 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
3012 | return ret_val; | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | /* Configure Flow Control now that Auto-Neg has completed. First, we | |
3017 | * need to restore the desired flow control settings because we may | |
3018 | * have had to re-autoneg with a different link partner. | |
3019 | */ | |
3020 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 3021 | if (ret_val) { |
1da177e4 LT |
3022 | DEBUGOUT("Error configuring flow control\n"); |
3023 | return ret_val; | |
3024 | } | |
3025 | ||
3026 | /* At this point we know that we are on copper and we have | |
3027 | * auto-negotiated link. These are conditions for checking the link | |
3028 | * partner capability register. We use the link speed to determine if | |
3029 | * TBI compatibility needs to be turned on or off. If the link is not | |
3030 | * at gigabit speed, then TBI compatibility is not needed. If we are | |
3031 | * at gigabit speed, we turn on TBI compatibility. | |
3032 | */ | |
8fc897b0 | 3033 | if (hw->tbi_compatibility_en) { |
1da177e4 | 3034 | uint16_t speed, duplex; |
592600a0 AK |
3035 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
3036 | if (ret_val) { | |
3037 | DEBUGOUT("Error getting link speed and duplex\n"); | |
3038 | return ret_val; | |
3039 | } | |
3040 | if (speed != SPEED_1000) { | |
1da177e4 LT |
3041 | /* If link speed is not set to gigabit speed, we do not need |
3042 | * to enable TBI compatibility. | |
3043 | */ | |
8fc897b0 | 3044 | if (hw->tbi_compatibility_on) { |
1da177e4 LT |
3045 | /* If we previously were in the mode, turn it off. */ |
3046 | rctl = E1000_READ_REG(hw, RCTL); | |
3047 | rctl &= ~E1000_RCTL_SBP; | |
3048 | E1000_WRITE_REG(hw, RCTL, rctl); | |
3049 | hw->tbi_compatibility_on = FALSE; | |
3050 | } | |
3051 | } else { | |
3052 | /* If TBI compatibility is was previously off, turn it on. For | |
3053 | * compatibility with a TBI link partner, we will store bad | |
3054 | * packets. Some frames have an additional byte on the end and | |
3055 | * will look like CRC errors to to the hardware. | |
3056 | */ | |
8fc897b0 | 3057 | if (!hw->tbi_compatibility_on) { |
1da177e4 LT |
3058 | hw->tbi_compatibility_on = TRUE; |
3059 | rctl = E1000_READ_REG(hw, RCTL); | |
3060 | rctl |= E1000_RCTL_SBP; | |
3061 | E1000_WRITE_REG(hw, RCTL, rctl); | |
3062 | } | |
3063 | } | |
3064 | } | |
3065 | } | |
3066 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
3067 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
3068 | * link partner is not trying to auto-negotiate with us (we are receiving | |
3069 | * idles or data), we need to force link up. We also need to give | |
3070 | * auto-negotiation time to complete, in case the cable was just plugged | |
3071 | * in. The autoneg_failed flag does this. | |
3072 | */ | |
8fc897b0 | 3073 | else if ((((hw->media_type == e1000_media_type_fiber) && |
1da177e4 | 3074 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
8fc897b0 AK |
3075 | (hw->media_type == e1000_media_type_internal_serdes)) && |
3076 | (!(status & E1000_STATUS_LU)) && | |
3077 | (!(rxcw & E1000_RXCW_C))) { | |
3078 | if (hw->autoneg_failed == 0) { | |
1da177e4 LT |
3079 | hw->autoneg_failed = 1; |
3080 | return 0; | |
3081 | } | |
a42a507c | 3082 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
1da177e4 LT |
3083 | |
3084 | /* Disable auto-negotiation in the TXCW register */ | |
3085 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | |
3086 | ||
3087 | /* Force link-up and also force full-duplex. */ | |
3088 | ctrl = E1000_READ_REG(hw, CTRL); | |
3089 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
3090 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3091 | ||
3092 | /* Configure Flow Control after forcing link up. */ | |
3093 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 3094 | if (ret_val) { |
1da177e4 LT |
3095 | DEBUGOUT("Error configuring flow control\n"); |
3096 | return ret_val; | |
3097 | } | |
3098 | } | |
3099 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
3100 | * auto-negotiation in the TXCW register and disable forced link in the | |
3101 | * Device Control register in an attempt to auto-negotiate with our link | |
3102 | * partner. | |
3103 | */ | |
8fc897b0 AK |
3104 | else if (((hw->media_type == e1000_media_type_fiber) || |
3105 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
3106 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
a42a507c | 3107 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
1da177e4 LT |
3108 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
3109 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
3110 | ||
3111 | hw->serdes_link_down = FALSE; | |
3112 | } | |
3113 | /* If we force link for non-auto-negotiation switch, check link status | |
3114 | * based on MAC synchronization for internal serdes media type. | |
3115 | */ | |
8fc897b0 AK |
3116 | else if ((hw->media_type == e1000_media_type_internal_serdes) && |
3117 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
1da177e4 LT |
3118 | /* SYNCH bit and IV bit are sticky. */ |
3119 | udelay(10); | |
8fc897b0 AK |
3120 | if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
3121 | if (!(rxcw & E1000_RXCW_IV)) { | |
1da177e4 LT |
3122 | hw->serdes_link_down = FALSE; |
3123 | DEBUGOUT("SERDES: Link is up.\n"); | |
3124 | } | |
3125 | } else { | |
3126 | hw->serdes_link_down = TRUE; | |
3127 | DEBUGOUT("SERDES: Link is down.\n"); | |
3128 | } | |
3129 | } | |
8fc897b0 AK |
3130 | if ((hw->media_type == e1000_media_type_internal_serdes) && |
3131 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
1da177e4 LT |
3132 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
3133 | } | |
3134 | return E1000_SUCCESS; | |
3135 | } | |
3136 | ||
3137 | /****************************************************************************** | |
3138 | * Detects the current speed and duplex settings of the hardware. | |
3139 | * | |
3140 | * hw - Struct containing variables accessed by shared code | |
3141 | * speed - Speed of the connection | |
3142 | * duplex - Duplex setting of the connection | |
3143 | *****************************************************************************/ | |
3144 | int32_t | |
3145 | e1000_get_speed_and_duplex(struct e1000_hw *hw, | |
3146 | uint16_t *speed, | |
3147 | uint16_t *duplex) | |
3148 | { | |
3149 | uint32_t status; | |
3150 | int32_t ret_val; | |
3151 | uint16_t phy_data; | |
3152 | ||
3153 | DEBUGFUNC("e1000_get_speed_and_duplex"); | |
3154 | ||
8fc897b0 | 3155 | if (hw->mac_type >= e1000_82543) { |
1da177e4 | 3156 | status = E1000_READ_REG(hw, STATUS); |
8fc897b0 | 3157 | if (status & E1000_STATUS_SPEED_1000) { |
1da177e4 LT |
3158 | *speed = SPEED_1000; |
3159 | DEBUGOUT("1000 Mbs, "); | |
8fc897b0 | 3160 | } else if (status & E1000_STATUS_SPEED_100) { |
1da177e4 LT |
3161 | *speed = SPEED_100; |
3162 | DEBUGOUT("100 Mbs, "); | |
3163 | } else { | |
3164 | *speed = SPEED_10; | |
3165 | DEBUGOUT("10 Mbs, "); | |
3166 | } | |
3167 | ||
8fc897b0 | 3168 | if (status & E1000_STATUS_FD) { |
1da177e4 | 3169 | *duplex = FULL_DUPLEX; |
a42a507c | 3170 | DEBUGOUT("Full Duplex\n"); |
1da177e4 LT |
3171 | } else { |
3172 | *duplex = HALF_DUPLEX; | |
a42a507c | 3173 | DEBUGOUT(" Half Duplex\n"); |
1da177e4 LT |
3174 | } |
3175 | } else { | |
a42a507c | 3176 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
1da177e4 LT |
3177 | *speed = SPEED_1000; |
3178 | *duplex = FULL_DUPLEX; | |
3179 | } | |
3180 | ||
3181 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even | |
3182 | * if it is operating at half duplex. Here we set the duplex settings to | |
3183 | * match the duplex in the link partner's capabilities. | |
3184 | */ | |
8fc897b0 | 3185 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
1da177e4 | 3186 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
8fc897b0 | 3187 | if (ret_val) |
1da177e4 LT |
3188 | return ret_val; |
3189 | ||
8fc897b0 | 3190 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
1da177e4 LT |
3191 | *duplex = HALF_DUPLEX; |
3192 | else { | |
3193 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); | |
8fc897b0 | 3194 | if (ret_val) |
1da177e4 | 3195 | return ret_val; |
8fc897b0 | 3196 | if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
1da177e4 LT |
3197 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
3198 | *duplex = HALF_DUPLEX; | |
3199 | } | |
3200 | } | |
3201 | ||
76c224bc | 3202 | if ((hw->mac_type == e1000_80003es2lan) && |
6418ecc6 JK |
3203 | (hw->media_type == e1000_media_type_copper)) { |
3204 | if (*speed == SPEED_1000) | |
3205 | ret_val = e1000_configure_kmrn_for_1000(hw); | |
3206 | else | |
cd94dd0b AK |
3207 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
3208 | if (ret_val) | |
3209 | return ret_val; | |
3210 | } | |
3211 | ||
3212 | if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { | |
3213 | ret_val = e1000_kumeran_lock_loss_workaround(hw); | |
6418ecc6 JK |
3214 | if (ret_val) |
3215 | return ret_val; | |
3216 | } | |
3217 | ||
1da177e4 LT |
3218 | return E1000_SUCCESS; |
3219 | } | |
3220 | ||
3221 | /****************************************************************************** | |
3222 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
3223 | * | |
3224 | * hw - Struct containing variables accessed by shared code | |
3225 | ******************************************************************************/ | |
3ad2cc67 | 3226 | static int32_t |
1da177e4 LT |
3227 | e1000_wait_autoneg(struct e1000_hw *hw) |
3228 | { | |
3229 | int32_t ret_val; | |
3230 | uint16_t i; | |
3231 | uint16_t phy_data; | |
3232 | ||
3233 | DEBUGFUNC("e1000_wait_autoneg"); | |
3234 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
3235 | ||
3236 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
8fc897b0 | 3237 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
1da177e4 LT |
3238 | /* Read the MII Status Register and wait for Auto-Neg |
3239 | * Complete bit to be set. | |
3240 | */ | |
3241 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 3242 | if (ret_val) |
1da177e4 LT |
3243 | return ret_val; |
3244 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 3245 | if (ret_val) |
1da177e4 | 3246 | return ret_val; |
8fc897b0 | 3247 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
1da177e4 LT |
3248 | return E1000_SUCCESS; |
3249 | } | |
f8ec4733 | 3250 | msleep(100); |
1da177e4 LT |
3251 | } |
3252 | return E1000_SUCCESS; | |
3253 | } | |
3254 | ||
3255 | /****************************************************************************** | |
3256 | * Raises the Management Data Clock | |
3257 | * | |
3258 | * hw - Struct containing variables accessed by shared code | |
3259 | * ctrl - Device control register's current value | |
3260 | ******************************************************************************/ | |
3261 | static void | |
3262 | e1000_raise_mdi_clk(struct e1000_hw *hw, | |
3263 | uint32_t *ctrl) | |
3264 | { | |
3265 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
3266 | * bit), and then delay 10 microseconds. | |
3267 | */ | |
3268 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); | |
3269 | E1000_WRITE_FLUSH(hw); | |
3270 | udelay(10); | |
3271 | } | |
3272 | ||
3273 | /****************************************************************************** | |
3274 | * Lowers the Management Data Clock | |
3275 | * | |
3276 | * hw - Struct containing variables accessed by shared code | |
3277 | * ctrl - Device control register's current value | |
3278 | ******************************************************************************/ | |
3279 | static void | |
3280 | e1000_lower_mdi_clk(struct e1000_hw *hw, | |
3281 | uint32_t *ctrl) | |
3282 | { | |
3283 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
3284 | * bit), and then delay 10 microseconds. | |
3285 | */ | |
3286 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); | |
3287 | E1000_WRITE_FLUSH(hw); | |
3288 | udelay(10); | |
3289 | } | |
3290 | ||
3291 | /****************************************************************************** | |
3292 | * Shifts data bits out to the PHY | |
3293 | * | |
3294 | * hw - Struct containing variables accessed by shared code | |
3295 | * data - Data to send out to the PHY | |
3296 | * count - Number of bits to shift out | |
3297 | * | |
3298 | * Bits are shifted out in MSB to LSB order. | |
3299 | ******************************************************************************/ | |
3300 | static void | |
3301 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, | |
3302 | uint32_t data, | |
3303 | uint16_t count) | |
3304 | { | |
3305 | uint32_t ctrl; | |
3306 | uint32_t mask; | |
3307 | ||
3308 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
3309 | * in the "data" parameter will be shifted out to the PHY one bit at a | |
3310 | * time. In order to do this, "data" must be broken down into bits. | |
3311 | */ | |
3312 | mask = 0x01; | |
3313 | mask <<= (count - 1); | |
3314 | ||
3315 | ctrl = E1000_READ_REG(hw, CTRL); | |
3316 | ||
3317 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
3318 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
3319 | ||
8fc897b0 | 3320 | while (mask) { |
1da177e4 LT |
3321 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
3322 | * then raising and lowering the Management Data Clock. A "0" is | |
3323 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
3324 | * raising and lowering the clock. | |
3325 | */ | |
8fc897b0 AK |
3326 | if (data & mask) |
3327 | ctrl |= E1000_CTRL_MDIO; | |
3328 | else | |
3329 | ctrl &= ~E1000_CTRL_MDIO; | |
1da177e4 LT |
3330 | |
3331 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3332 | E1000_WRITE_FLUSH(hw); | |
3333 | ||
3334 | udelay(10); | |
3335 | ||
3336 | e1000_raise_mdi_clk(hw, &ctrl); | |
3337 | e1000_lower_mdi_clk(hw, &ctrl); | |
3338 | ||
3339 | mask = mask >> 1; | |
3340 | } | |
3341 | } | |
3342 | ||
3343 | /****************************************************************************** | |
3344 | * Shifts data bits in from the PHY | |
3345 | * | |
3346 | * hw - Struct containing variables accessed by shared code | |
3347 | * | |
3348 | * Bits are shifted in in MSB to LSB order. | |
3349 | ******************************************************************************/ | |
3350 | static uint16_t | |
3351 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) | |
3352 | { | |
3353 | uint32_t ctrl; | |
3354 | uint16_t data = 0; | |
3355 | uint8_t i; | |
3356 | ||
3357 | /* In order to read a register from the PHY, we need to shift in a total | |
3358 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
3359 | * to avoid contention on the MDIO pin when a read operation is performed. | |
3360 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
3361 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
3362 | * and then reading the value of the MDIO bit. | |
3363 | */ | |
3364 | ctrl = E1000_READ_REG(hw, CTRL); | |
3365 | ||
3366 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
3367 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
3368 | ctrl &= ~E1000_CTRL_MDIO; | |
3369 | ||
3370 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3371 | E1000_WRITE_FLUSH(hw); | |
3372 | ||
3373 | /* Raise and Lower the clock before reading in the data. This accounts for | |
3374 | * the turnaround bits. The first clock occurred when we clocked out the | |
3375 | * last bit of the Register Address. | |
3376 | */ | |
3377 | e1000_raise_mdi_clk(hw, &ctrl); | |
3378 | e1000_lower_mdi_clk(hw, &ctrl); | |
3379 | ||
8fc897b0 | 3380 | for (data = 0, i = 0; i < 16; i++) { |
1da177e4 LT |
3381 | data = data << 1; |
3382 | e1000_raise_mdi_clk(hw, &ctrl); | |
3383 | ctrl = E1000_READ_REG(hw, CTRL); | |
3384 | /* Check to see if we shifted in a "1". */ | |
8fc897b0 AK |
3385 | if (ctrl & E1000_CTRL_MDIO) |
3386 | data |= 1; | |
1da177e4 LT |
3387 | e1000_lower_mdi_clk(hw, &ctrl); |
3388 | } | |
3389 | ||
3390 | e1000_raise_mdi_clk(hw, &ctrl); | |
3391 | e1000_lower_mdi_clk(hw, &ctrl); | |
3392 | ||
3393 | return data; | |
3394 | } | |
3395 | ||
e4c780b1 | 3396 | static int32_t |
6418ecc6 JK |
3397 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
3398 | { | |
3399 | uint32_t swfw_sync = 0; | |
3400 | uint32_t swmask = mask; | |
3401 | uint32_t fwmask = mask << 16; | |
3402 | int32_t timeout = 200; | |
3403 | ||
3404 | DEBUGFUNC("e1000_swfw_sync_acquire"); | |
3405 | ||
cd94dd0b AK |
3406 | if (hw->swfwhw_semaphore_present) |
3407 | return e1000_get_software_flag(hw); | |
3408 | ||
6418ecc6 JK |
3409 | if (!hw->swfw_sync_present) |
3410 | return e1000_get_hw_eeprom_semaphore(hw); | |
3411 | ||
8fc897b0 | 3412 | while (timeout) { |
6418ecc6 JK |
3413 | if (e1000_get_hw_eeprom_semaphore(hw)) |
3414 | return -E1000_ERR_SWFW_SYNC; | |
3415 | ||
3416 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
3417 | if (!(swfw_sync & (fwmask | swmask))) { | |
3418 | break; | |
3419 | } | |
3420 | ||
3421 | /* firmware currently using resource (fwmask) */ | |
3422 | /* or other software thread currently using resource (swmask) */ | |
3423 | e1000_put_hw_eeprom_semaphore(hw); | |
f8ec4733 | 3424 | mdelay(5); |
6418ecc6 JK |
3425 | timeout--; |
3426 | } | |
3427 | ||
3428 | if (!timeout) { | |
3429 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
3430 | return -E1000_ERR_SWFW_SYNC; | |
3431 | } | |
3432 | ||
3433 | swfw_sync |= swmask; | |
3434 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
3435 | ||
3436 | e1000_put_hw_eeprom_semaphore(hw); | |
3437 | return E1000_SUCCESS; | |
3438 | } | |
3439 | ||
e4c780b1 | 3440 | static void |
6418ecc6 JK |
3441 | e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
3442 | { | |
3443 | uint32_t swfw_sync; | |
3444 | uint32_t swmask = mask; | |
3445 | ||
3446 | DEBUGFUNC("e1000_swfw_sync_release"); | |
3447 | ||
cd94dd0b AK |
3448 | if (hw->swfwhw_semaphore_present) { |
3449 | e1000_release_software_flag(hw); | |
3450 | return; | |
3451 | } | |
3452 | ||
6418ecc6 JK |
3453 | if (!hw->swfw_sync_present) { |
3454 | e1000_put_hw_eeprom_semaphore(hw); | |
3455 | return; | |
3456 | } | |
3457 | ||
3458 | /* if (e1000_get_hw_eeprom_semaphore(hw)) | |
3459 | * return -E1000_ERR_SWFW_SYNC; */ | |
3460 | while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); | |
3461 | /* empty */ | |
3462 | ||
3463 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
3464 | swfw_sync &= ~swmask; | |
3465 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
3466 | ||
3467 | e1000_put_hw_eeprom_semaphore(hw); | |
3468 | } | |
3469 | ||
1da177e4 LT |
3470 | /***************************************************************************** |
3471 | * Reads the value from a PHY register, if the value is on a specific non zero | |
3472 | * page, sets the page first. | |
3473 | * hw - Struct containing variables accessed by shared code | |
3474 | * reg_addr - address of the PHY register to read | |
3475 | ******************************************************************************/ | |
3476 | int32_t | |
3477 | e1000_read_phy_reg(struct e1000_hw *hw, | |
3478 | uint32_t reg_addr, | |
3479 | uint16_t *phy_data) | |
3480 | { | |
3481 | uint32_t ret_val; | |
6418ecc6 | 3482 | uint16_t swfw; |
1da177e4 LT |
3483 | |
3484 | DEBUGFUNC("e1000_read_phy_reg"); | |
3485 | ||
6418ecc6 JK |
3486 | if ((hw->mac_type == e1000_80003es2lan) && |
3487 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3488 | swfw = E1000_SWFW_PHY1_SM; | |
3489 | } else { | |
3490 | swfw = E1000_SWFW_PHY0_SM; | |
3491 | } | |
3492 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3493 | return -E1000_ERR_SWFW_SYNC; | |
3494 | ||
cd94dd0b AK |
3495 | if ((hw->phy_type == e1000_phy_igp || |
3496 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 3497 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3498 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3499 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
3500 | (uint16_t)reg_addr); | |
8fc897b0 | 3501 | if (ret_val) { |
6418ecc6 | 3502 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3503 | return ret_val; |
3504 | } | |
6418ecc6 JK |
3505 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3506 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3507 | (hw->mac_type == e1000_80003es2lan)) { | |
3508 | /* Select Configuration Page */ | |
3509 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3510 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
3511 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3512 | } else { | |
3513 | /* Use Alternative Page Select register to access | |
3514 | * registers 30 and 31 | |
3515 | */ | |
3516 | ret_val = e1000_write_phy_reg_ex(hw, | |
3517 | GG82563_PHY_PAGE_SELECT_ALT, | |
3518 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3519 | } | |
3520 | ||
3521 | if (ret_val) { | |
3522 | e1000_swfw_sync_release(hw, swfw); | |
3523 | return ret_val; | |
3524 | } | |
3525 | } | |
1da177e4 LT |
3526 | } |
3527 | ||
3528 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3529 | phy_data); | |
3530 | ||
6418ecc6 | 3531 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3532 | return ret_val; |
3533 | } | |
3534 | ||
35574764 NN |
3535 | static int32_t |
3536 | e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, | |
1da177e4 LT |
3537 | uint16_t *phy_data) |
3538 | { | |
3539 | uint32_t i; | |
3540 | uint32_t mdic = 0; | |
3541 | const uint32_t phy_addr = 1; | |
3542 | ||
3543 | DEBUGFUNC("e1000_read_phy_reg_ex"); | |
3544 | ||
8fc897b0 | 3545 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
1da177e4 LT |
3546 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3547 | return -E1000_ERR_PARAM; | |
3548 | } | |
3549 | ||
8fc897b0 | 3550 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
3551 | /* Set up Op-code, Phy Address, and register address in the MDI |
3552 | * Control register. The MAC will take care of interfacing with the | |
3553 | * PHY to retrieve the desired data. | |
3554 | */ | |
3555 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
3556 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3557 | (E1000_MDIC_OP_READ)); | |
3558 | ||
3559 | E1000_WRITE_REG(hw, MDIC, mdic); | |
3560 | ||
3561 | /* Poll the ready bit to see if the MDI read completed */ | |
8fc897b0 | 3562 | for (i = 0; i < 64; i++) { |
1da177e4 LT |
3563 | udelay(50); |
3564 | mdic = E1000_READ_REG(hw, MDIC); | |
8fc897b0 | 3565 | if (mdic & E1000_MDIC_READY) break; |
1da177e4 | 3566 | } |
8fc897b0 | 3567 | if (!(mdic & E1000_MDIC_READY)) { |
1da177e4 LT |
3568 | DEBUGOUT("MDI Read did not complete\n"); |
3569 | return -E1000_ERR_PHY; | |
3570 | } | |
8fc897b0 | 3571 | if (mdic & E1000_MDIC_ERROR) { |
1da177e4 LT |
3572 | DEBUGOUT("MDI Error\n"); |
3573 | return -E1000_ERR_PHY; | |
3574 | } | |
3575 | *phy_data = (uint16_t) mdic; | |
3576 | } else { | |
3577 | /* We must first send a preamble through the MDIO pin to signal the | |
3578 | * beginning of an MII instruction. This is done by sending 32 | |
3579 | * consecutive "1" bits. | |
3580 | */ | |
3581 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3582 | ||
3583 | /* Now combine the next few fields that are required for a read | |
3584 | * operation. We use this method instead of calling the | |
3585 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
3586 | * a MII read instruction consists of a shift out of 14 bits and is | |
3587 | * defined as follows: | |
3588 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
3589 | * followed by a shift in of 18 bits. This first two bits shifted in | |
3590 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
3591 | * READ operation is performed. These two bits are thrown away | |
3592 | * followed by a shift in of 16 bits which contains the desired data. | |
3593 | */ | |
3594 | mdic = ((reg_addr) | (phy_addr << 5) | | |
3595 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
3596 | ||
3597 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
3598 | ||
3599 | /* Now that we've shifted out the read command to the MII, we need to | |
3600 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
3601 | * register address. | |
3602 | */ | |
3603 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
3604 | } | |
3605 | return E1000_SUCCESS; | |
3606 | } | |
3607 | ||
3608 | /****************************************************************************** | |
3609 | * Writes a value to a PHY register | |
3610 | * | |
3611 | * hw - Struct containing variables accessed by shared code | |
3612 | * reg_addr - address of the PHY register to write | |
3613 | * data - data to write to the PHY | |
3614 | ******************************************************************************/ | |
3615 | int32_t | |
35574764 | 3616 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
1da177e4 LT |
3617 | uint16_t phy_data) |
3618 | { | |
3619 | uint32_t ret_val; | |
6418ecc6 | 3620 | uint16_t swfw; |
1da177e4 LT |
3621 | |
3622 | DEBUGFUNC("e1000_write_phy_reg"); | |
3623 | ||
6418ecc6 JK |
3624 | if ((hw->mac_type == e1000_80003es2lan) && |
3625 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3626 | swfw = E1000_SWFW_PHY1_SM; | |
3627 | } else { | |
3628 | swfw = E1000_SWFW_PHY0_SM; | |
3629 | } | |
3630 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3631 | return -E1000_ERR_SWFW_SYNC; | |
3632 | ||
cd94dd0b AK |
3633 | if ((hw->phy_type == e1000_phy_igp || |
3634 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 3635 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3636 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3637 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
3638 | (uint16_t)reg_addr); | |
8fc897b0 | 3639 | if (ret_val) { |
6418ecc6 | 3640 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3641 | return ret_val; |
3642 | } | |
6418ecc6 JK |
3643 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3644 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3645 | (hw->mac_type == e1000_80003es2lan)) { | |
3646 | /* Select Configuration Page */ | |
3647 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3648 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
3649 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3650 | } else { | |
3651 | /* Use Alternative Page Select register to access | |
3652 | * registers 30 and 31 | |
3653 | */ | |
3654 | ret_val = e1000_write_phy_reg_ex(hw, | |
3655 | GG82563_PHY_PAGE_SELECT_ALT, | |
3656 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3657 | } | |
3658 | ||
3659 | if (ret_val) { | |
3660 | e1000_swfw_sync_release(hw, swfw); | |
3661 | return ret_val; | |
3662 | } | |
3663 | } | |
1da177e4 LT |
3664 | } |
3665 | ||
3666 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3667 | phy_data); | |
3668 | ||
6418ecc6 | 3669 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3670 | return ret_val; |
3671 | } | |
3672 | ||
35574764 NN |
3673 | static int32_t |
3674 | e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, | |
3675 | uint16_t phy_data) | |
1da177e4 LT |
3676 | { |
3677 | uint32_t i; | |
3678 | uint32_t mdic = 0; | |
3679 | const uint32_t phy_addr = 1; | |
3680 | ||
3681 | DEBUGFUNC("e1000_write_phy_reg_ex"); | |
3682 | ||
8fc897b0 | 3683 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
1da177e4 LT |
3684 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3685 | return -E1000_ERR_PARAM; | |
3686 | } | |
3687 | ||
8fc897b0 | 3688 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
3689 | /* Set up Op-code, Phy Address, register address, and data intended |
3690 | * for the PHY register in the MDI Control register. The MAC will take | |
3691 | * care of interfacing with the PHY to send the desired data. | |
3692 | */ | |
3693 | mdic = (((uint32_t) phy_data) | | |
3694 | (reg_addr << E1000_MDIC_REG_SHIFT) | | |
3695 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3696 | (E1000_MDIC_OP_WRITE)); | |
3697 | ||
3698 | E1000_WRITE_REG(hw, MDIC, mdic); | |
3699 | ||
3700 | /* Poll the ready bit to see if the MDI read completed */ | |
8fc897b0 | 3701 | for (i = 0; i < 641; i++) { |
1da177e4 LT |
3702 | udelay(5); |
3703 | mdic = E1000_READ_REG(hw, MDIC); | |
8fc897b0 | 3704 | if (mdic & E1000_MDIC_READY) break; |
1da177e4 | 3705 | } |
8fc897b0 | 3706 | if (!(mdic & E1000_MDIC_READY)) { |
1da177e4 LT |
3707 | DEBUGOUT("MDI Write did not complete\n"); |
3708 | return -E1000_ERR_PHY; | |
3709 | } | |
3710 | } else { | |
3711 | /* We'll need to use the SW defined pins to shift the write command | |
3712 | * out to the PHY. We first send a preamble to the PHY to signal the | |
3713 | * beginning of the MII instruction. This is done by sending 32 | |
3714 | * consecutive "1" bits. | |
3715 | */ | |
3716 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3717 | ||
3718 | /* Now combine the remaining required fields that will indicate a | |
3719 | * write operation. We use this method instead of calling the | |
3720 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
3721 | * format of a MII write instruction is as follows: | |
3722 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
3723 | */ | |
3724 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
3725 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
3726 | mdic <<= 16; | |
3727 | mdic |= (uint32_t) phy_data; | |
3728 | ||
3729 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
3730 | } | |
3731 | ||
3732 | return E1000_SUCCESS; | |
3733 | } | |
3734 | ||
e4c780b1 | 3735 | static int32_t |
6418ecc6 JK |
3736 | e1000_read_kmrn_reg(struct e1000_hw *hw, |
3737 | uint32_t reg_addr, | |
3738 | uint16_t *data) | |
3739 | { | |
3740 | uint32_t reg_val; | |
3741 | uint16_t swfw; | |
3742 | DEBUGFUNC("e1000_read_kmrn_reg"); | |
3743 | ||
3744 | if ((hw->mac_type == e1000_80003es2lan) && | |
3745 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3746 | swfw = E1000_SWFW_PHY1_SM; | |
3747 | } else { | |
3748 | swfw = E1000_SWFW_PHY0_SM; | |
3749 | } | |
3750 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3751 | return -E1000_ERR_SWFW_SYNC; | |
3752 | ||
3753 | /* Write register address */ | |
3754 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3755 | E1000_KUMCTRLSTA_OFFSET) | | |
3756 | E1000_KUMCTRLSTA_REN; | |
3757 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
3758 | udelay(2); | |
3759 | ||
3760 | /* Read the data returned */ | |
3761 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); | |
3762 | *data = (uint16_t)reg_val; | |
3763 | ||
3764 | e1000_swfw_sync_release(hw, swfw); | |
3765 | return E1000_SUCCESS; | |
3766 | } | |
3767 | ||
e4c780b1 | 3768 | static int32_t |
6418ecc6 JK |
3769 | e1000_write_kmrn_reg(struct e1000_hw *hw, |
3770 | uint32_t reg_addr, | |
3771 | uint16_t data) | |
3772 | { | |
3773 | uint32_t reg_val; | |
3774 | uint16_t swfw; | |
3775 | DEBUGFUNC("e1000_write_kmrn_reg"); | |
3776 | ||
3777 | if ((hw->mac_type == e1000_80003es2lan) && | |
3778 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3779 | swfw = E1000_SWFW_PHY1_SM; | |
3780 | } else { | |
3781 | swfw = E1000_SWFW_PHY0_SM; | |
3782 | } | |
3783 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3784 | return -E1000_ERR_SWFW_SYNC; | |
3785 | ||
3786 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3787 | E1000_KUMCTRLSTA_OFFSET) | data; | |
3788 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
3789 | udelay(2); | |
3790 | ||
3791 | e1000_swfw_sync_release(hw, swfw); | |
3792 | return E1000_SUCCESS; | |
3793 | } | |
2d7edb92 | 3794 | |
1da177e4 LT |
3795 | /****************************************************************************** |
3796 | * Returns the PHY to the power-on reset state | |
3797 | * | |
3798 | * hw - Struct containing variables accessed by shared code | |
3799 | ******************************************************************************/ | |
2d7edb92 | 3800 | int32_t |
1da177e4 LT |
3801 | e1000_phy_hw_reset(struct e1000_hw *hw) |
3802 | { | |
3803 | uint32_t ctrl, ctrl_ext; | |
3804 | uint32_t led_ctrl; | |
2d7edb92 | 3805 | int32_t ret_val; |
6418ecc6 | 3806 | uint16_t swfw; |
1da177e4 LT |
3807 | |
3808 | DEBUGFUNC("e1000_phy_hw_reset"); | |
3809 | ||
2d7edb92 MC |
3810 | /* In the case of the phy reset being blocked, it's not an error, we |
3811 | * simply return success without performing the reset. */ | |
3812 | ret_val = e1000_check_phy_reset_block(hw); | |
3813 | if (ret_val) | |
3814 | return E1000_SUCCESS; | |
3815 | ||
1da177e4 LT |
3816 | DEBUGOUT("Resetting Phy...\n"); |
3817 | ||
8fc897b0 | 3818 | if (hw->mac_type > e1000_82543) { |
6418ecc6 JK |
3819 | if ((hw->mac_type == e1000_80003es2lan) && |
3820 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3821 | swfw = E1000_SWFW_PHY1_SM; | |
3822 | } else { | |
3823 | swfw = E1000_SWFW_PHY0_SM; | |
3824 | } | |
3825 | if (e1000_swfw_sync_acquire(hw, swfw)) { | |
2a88c173 | 3826 | DEBUGOUT("Unable to acquire swfw sync\n"); |
6418ecc6 JK |
3827 | return -E1000_ERR_SWFW_SYNC; |
3828 | } | |
1da177e4 LT |
3829 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
3830 | * bit. Then, take it out of reset. | |
76c224bc | 3831 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
fd803241 | 3832 | * and deassert. For e1000_82571 hardware and later, we instead delay |
0f15a8fa | 3833 | * for 50us between and 10ms after the deassertion. |
1da177e4 LT |
3834 | */ |
3835 | ctrl = E1000_READ_REG(hw, CTRL); | |
3836 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); | |
3837 | E1000_WRITE_FLUSH(hw); | |
76c224bc AK |
3838 | |
3839 | if (hw->mac_type < e1000_82571) | |
f8ec4733 | 3840 | msleep(10); |
b55ccb35 JK |
3841 | else |
3842 | udelay(100); | |
76c224bc | 3843 | |
1da177e4 LT |
3844 | E1000_WRITE_REG(hw, CTRL, ctrl); |
3845 | E1000_WRITE_FLUSH(hw); | |
76c224bc | 3846 | |
fd803241 | 3847 | if (hw->mac_type >= e1000_82571) |
f8ec4733 | 3848 | mdelay(10); |
35574764 | 3849 | |
6418ecc6 | 3850 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3851 | } else { |
3852 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
3853 | * bit to put the PHY into reset. Then, take it out of reset. | |
3854 | */ | |
3855 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
3856 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | |
3857 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
3858 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
3859 | E1000_WRITE_FLUSH(hw); | |
f8ec4733 | 3860 | msleep(10); |
1da177e4 LT |
3861 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
3862 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
3863 | E1000_WRITE_FLUSH(hw); | |
3864 | } | |
3865 | udelay(150); | |
3866 | ||
8fc897b0 | 3867 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1da177e4 LT |
3868 | /* Configure activity LED after PHY reset */ |
3869 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
3870 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
3871 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
3872 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
3873 | } | |
2d7edb92 MC |
3874 | |
3875 | /* Wait for FW to finish PHY configuration. */ | |
3876 | ret_val = e1000_get_phy_cfg_done(hw); | |
8fc897b0 AK |
3877 | if (ret_val != E1000_SUCCESS) |
3878 | return ret_val; | |
6418ecc6 | 3879 | e1000_release_software_semaphore(hw); |
2d7edb92 | 3880 | |
8fc897b0 AK |
3881 | if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) |
3882 | ret_val = e1000_init_lcd_from_nvm(hw); | |
3883 | ||
2d7edb92 | 3884 | return ret_val; |
1da177e4 LT |
3885 | } |
3886 | ||
3887 | /****************************************************************************** | |
3888 | * Resets the PHY | |
3889 | * | |
3890 | * hw - Struct containing variables accessed by shared code | |
3891 | * | |
0779bf2d | 3892 | * Sets bit 15 of the MII Control register |
1da177e4 LT |
3893 | ******************************************************************************/ |
3894 | int32_t | |
3895 | e1000_phy_reset(struct e1000_hw *hw) | |
3896 | { | |
3897 | int32_t ret_val; | |
3898 | uint16_t phy_data; | |
3899 | ||
3900 | DEBUGFUNC("e1000_phy_reset"); | |
3901 | ||
2d7edb92 MC |
3902 | /* In the case of the phy reset being blocked, it's not an error, we |
3903 | * simply return success without performing the reset. */ | |
3904 | ret_val = e1000_check_phy_reset_block(hw); | |
3905 | if (ret_val) | |
3906 | return E1000_SUCCESS; | |
3907 | ||
2a88c173 JK |
3908 | switch (hw->phy_type) { |
3909 | case e1000_phy_igp: | |
3910 | case e1000_phy_igp_2: | |
3911 | case e1000_phy_igp_3: | |
3912 | case e1000_phy_ife: | |
2d7edb92 | 3913 | ret_val = e1000_phy_hw_reset(hw); |
8fc897b0 | 3914 | if (ret_val) |
2d7edb92 MC |
3915 | return ret_val; |
3916 | break; | |
3917 | default: | |
1da177e4 | 3918 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
8fc897b0 | 3919 | if (ret_val) |
1da177e4 LT |
3920 | return ret_val; |
3921 | ||
3922 | phy_data |= MII_CR_RESET; | |
3923 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
8fc897b0 | 3924 | if (ret_val) |
1da177e4 LT |
3925 | return ret_val; |
3926 | ||
3927 | udelay(1); | |
2d7edb92 MC |
3928 | break; |
3929 | } | |
1da177e4 | 3930 | |
8fc897b0 | 3931 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
1da177e4 LT |
3932 | e1000_phy_init_script(hw); |
3933 | ||
3934 | return E1000_SUCCESS; | |
3935 | } | |
3936 | ||
d37ea5d5 AK |
3937 | /****************************************************************************** |
3938 | * Work-around for 82566 power-down: on D3 entry- | |
3939 | * 1) disable gigabit link | |
3940 | * 2) write VR power-down enable | |
3941 | * 3) read it back | |
3942 | * if successful continue, else issue LCD reset and repeat | |
3943 | * | |
3944 | * hw - struct containing variables accessed by shared code | |
3945 | ******************************************************************************/ | |
3946 | void | |
3947 | e1000_phy_powerdown_workaround(struct e1000_hw *hw) | |
3948 | { | |
3949 | int32_t reg; | |
3950 | uint16_t phy_data; | |
3951 | int32_t retry = 0; | |
3952 | ||
3953 | DEBUGFUNC("e1000_phy_powerdown_workaround"); | |
3954 | ||
3955 | if (hw->phy_type != e1000_phy_igp_3) | |
3956 | return; | |
3957 | ||
3958 | do { | |
3959 | /* Disable link */ | |
3960 | reg = E1000_READ_REG(hw, PHY_CTRL); | |
3961 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | |
3962 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
3963 | ||
070f6ffb | 3964 | /* Write VR power-down enable - bits 9:8 should be 10b */ |
d37ea5d5 | 3965 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
070f6ffb JK |
3966 | phy_data |= (1 << 9); |
3967 | phy_data &= ~(1 << 8); | |
3968 | e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); | |
d37ea5d5 AK |
3969 | |
3970 | /* Read it back and test */ | |
3971 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | |
070f6ffb | 3972 | if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) |
d37ea5d5 AK |
3973 | break; |
3974 | ||
3975 | /* Issue PHY reset and repeat at most one more time */ | |
3976 | reg = E1000_READ_REG(hw, CTRL); | |
3977 | E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); | |
3978 | retry++; | |
3979 | } while (retry); | |
3980 | ||
3981 | return; | |
3982 | ||
3983 | } | |
3984 | ||
3985 | /****************************************************************************** | |
3986 | * Work-around for 82566 Kumeran PCS lock loss: | |
3987 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
3988 | * speed is gigabit- | |
3989 | * 0) if workaround is optionally disabled do nothing | |
3990 | * 1) wait 1ms for Kumeran link to come up | |
3991 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
3992 | * 3) if not set the link is locked (all is good), otherwise... | |
3993 | * 4) reset the PHY | |
3994 | * 5) repeat up to 10 times | |
3995 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
3996 | * | |
3997 | * hw - struct containing variables accessed by shared code | |
3998 | ******************************************************************************/ | |
e4c780b1 | 3999 | static int32_t |
d37ea5d5 AK |
4000 | e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) |
4001 | { | |
4002 | int32_t ret_val; | |
4003 | int32_t reg; | |
4004 | int32_t cnt; | |
4005 | uint16_t phy_data; | |
4006 | ||
4007 | if (hw->kmrn_lock_loss_workaround_disabled) | |
4008 | return E1000_SUCCESS; | |
4009 | ||
8fc897b0 AK |
4010 | /* Make sure link is up before proceeding. If not just return. |
4011 | * Attempting this while link is negotiating fouled up link | |
d37ea5d5 AK |
4012 | * stability */ |
4013 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
4014 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
4015 | ||
4016 | if (phy_data & MII_SR_LINK_STATUS) { | |
4017 | for (cnt = 0; cnt < 10; cnt++) { | |
4018 | /* read once to clear */ | |
4019 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | |
4020 | if (ret_val) | |
4021 | return ret_val; | |
4022 | /* and again to get new status */ | |
4023 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | |
4024 | if (ret_val) | |
4025 | return ret_val; | |
4026 | ||
4027 | /* check for PCS lock */ | |
4028 | if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
4029 | return E1000_SUCCESS; | |
4030 | ||
4031 | /* Issue PHY reset */ | |
4032 | e1000_phy_hw_reset(hw); | |
f8ec4733 | 4033 | mdelay(5); |
d37ea5d5 AK |
4034 | } |
4035 | /* Disable GigE link negotiation */ | |
4036 | reg = E1000_READ_REG(hw, PHY_CTRL); | |
4037 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | |
4038 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
4039 | ||
4040 | /* unable to acquire PCS lock */ | |
4041 | return E1000_ERR_PHY; | |
4042 | } | |
4043 | ||
4044 | return E1000_SUCCESS; | |
4045 | } | |
4046 | ||
1da177e4 LT |
4047 | /****************************************************************************** |
4048 | * Probes the expected PHY address for known PHY IDs | |
4049 | * | |
4050 | * hw - Struct containing variables accessed by shared code | |
4051 | ******************************************************************************/ | |
35574764 | 4052 | static int32_t |
1da177e4 LT |
4053 | e1000_detect_gig_phy(struct e1000_hw *hw) |
4054 | { | |
4055 | int32_t phy_init_status, ret_val; | |
4056 | uint16_t phy_id_high, phy_id_low; | |
4057 | boolean_t match = FALSE; | |
4058 | ||
4059 | DEBUGFUNC("e1000_detect_gig_phy"); | |
4060 | ||
2a88c173 JK |
4061 | if (hw->phy_id != 0) |
4062 | return E1000_SUCCESS; | |
4063 | ||
868d5309 MC |
4064 | /* The 82571 firmware may still be configuring the PHY. In this |
4065 | * case, we cannot access the PHY until the configuration is done. So | |
4066 | * we explicitly set the PHY values. */ | |
cd94dd0b AK |
4067 | if (hw->mac_type == e1000_82571 || |
4068 | hw->mac_type == e1000_82572) { | |
868d5309 MC |
4069 | hw->phy_id = IGP01E1000_I_PHY_ID; |
4070 | hw->phy_type = e1000_phy_igp_2; | |
4071 | return E1000_SUCCESS; | |
4072 | } | |
4073 | ||
6418ecc6 JK |
4074 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
4075 | * around that forces PHY page 0 to be set or the reads fail. The rest of | |
4076 | * the code in this routine uses e1000_read_phy_reg to read the PHY ID. | |
4077 | * So for ESB-2 we need to have this set so our reads won't fail. If the | |
4078 | * attached PHY is not a e1000_phy_gg82563, the routines below will figure | |
4079 | * this out as well. */ | |
4080 | if (hw->mac_type == e1000_80003es2lan) | |
4081 | hw->phy_type = e1000_phy_gg82563; | |
4082 | ||
1da177e4 LT |
4083 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
4084 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
cd94dd0b | 4085 | if (ret_val) |
1da177e4 LT |
4086 | return ret_val; |
4087 | ||
4088 | hw->phy_id = (uint32_t) (phy_id_high << 16); | |
4089 | udelay(20); | |
4090 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
8fc897b0 | 4091 | if (ret_val) |
1da177e4 LT |
4092 | return ret_val; |
4093 | ||
4094 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); | |
4095 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; | |
4096 | ||
8fc897b0 | 4097 | switch (hw->mac_type) { |
1da177e4 | 4098 | case e1000_82543: |
8fc897b0 | 4099 | if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
1da177e4 LT |
4100 | break; |
4101 | case e1000_82544: | |
8fc897b0 | 4102 | if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
1da177e4 LT |
4103 | break; |
4104 | case e1000_82540: | |
4105 | case e1000_82545: | |
4106 | case e1000_82545_rev_3: | |
4107 | case e1000_82546: | |
4108 | case e1000_82546_rev_3: | |
8fc897b0 | 4109 | if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
1da177e4 LT |
4110 | break; |
4111 | case e1000_82541: | |
4112 | case e1000_82541_rev_2: | |
4113 | case e1000_82547: | |
4114 | case e1000_82547_rev_2: | |
8fc897b0 | 4115 | if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
1da177e4 | 4116 | break; |
2d7edb92 | 4117 | case e1000_82573: |
8fc897b0 | 4118 | if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
2d7edb92 | 4119 | break; |
6418ecc6 JK |
4120 | case e1000_80003es2lan: |
4121 | if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; | |
4122 | break; | |
cd94dd0b AK |
4123 | case e1000_ich8lan: |
4124 | if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; | |
4125 | if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; | |
4126 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; | |
4127 | if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; | |
4128 | break; | |
1da177e4 LT |
4129 | default: |
4130 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | |
4131 | return -E1000_ERR_CONFIG; | |
4132 | } | |
4133 | phy_init_status = e1000_set_phy_type(hw); | |
4134 | ||
4135 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
4136 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); | |
4137 | return E1000_SUCCESS; | |
4138 | } | |
4139 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); | |
4140 | return -E1000_ERR_PHY; | |
4141 | } | |
4142 | ||
4143 | /****************************************************************************** | |
4144 | * Resets the PHY's DSP | |
4145 | * | |
4146 | * hw - Struct containing variables accessed by shared code | |
4147 | ******************************************************************************/ | |
4148 | static int32_t | |
4149 | e1000_phy_reset_dsp(struct e1000_hw *hw) | |
4150 | { | |
4151 | int32_t ret_val; | |
4152 | DEBUGFUNC("e1000_phy_reset_dsp"); | |
4153 | ||
4154 | do { | |
6418ecc6 JK |
4155 | if (hw->phy_type != e1000_phy_gg82563) { |
4156 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); | |
8fc897b0 | 4157 | if (ret_val) break; |
6418ecc6 | 4158 | } |
1da177e4 | 4159 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
8fc897b0 | 4160 | if (ret_val) break; |
1da177e4 | 4161 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
8fc897b0 | 4162 | if (ret_val) break; |
1da177e4 | 4163 | ret_val = E1000_SUCCESS; |
8fc897b0 | 4164 | } while (0); |
1da177e4 LT |
4165 | |
4166 | return ret_val; | |
4167 | } | |
4168 | ||
4169 | /****************************************************************************** | |
4170 | * Get PHY information from various PHY registers for igp PHY only. | |
4171 | * | |
4172 | * hw - Struct containing variables accessed by shared code | |
4173 | * phy_info - PHY information structure | |
4174 | ******************************************************************************/ | |
cff93eb3 | 4175 | static int32_t |
1da177e4 LT |
4176 | e1000_phy_igp_get_info(struct e1000_hw *hw, |
4177 | struct e1000_phy_info *phy_info) | |
4178 | { | |
4179 | int32_t ret_val; | |
70c6f30a JK |
4180 | uint16_t phy_data, min_length, max_length, average; |
4181 | e1000_rev_polarity polarity; | |
1da177e4 LT |
4182 | |
4183 | DEBUGFUNC("e1000_phy_igp_get_info"); | |
4184 | ||
4185 | /* The downshift status is checked only once, after link is established, | |
4186 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 4187 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
4188 | |
4189 | /* IGP01E1000 does not need to support it. */ | |
4190 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
4191 | ||
4192 | /* IGP01E1000 always correct polarity reversal */ | |
4193 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; | |
4194 | ||
4195 | /* Check polarity status */ | |
4196 | ret_val = e1000_check_polarity(hw, &polarity); | |
8fc897b0 | 4197 | if (ret_val) |
1da177e4 LT |
4198 | return ret_val; |
4199 | ||
4200 | phy_info->cable_polarity = polarity; | |
4201 | ||
4202 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); | |
8fc897b0 | 4203 | if (ret_val) |
1da177e4 LT |
4204 | return ret_val; |
4205 | ||
70c6f30a JK |
4206 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> |
4207 | IGP01E1000_PSSR_MDIX_SHIFT); | |
1da177e4 | 4208 | |
8fc897b0 | 4209 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
1da177e4 LT |
4210 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
4211 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ | |
4212 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
8fc897b0 | 4213 | if (ret_val) |
1da177e4 LT |
4214 | return ret_val; |
4215 | ||
70c6f30a JK |
4216 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
4217 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | |
4218 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
4219 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
4220 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | |
4221 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
1da177e4 LT |
4222 | |
4223 | /* Get cable length */ | |
4224 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | |
8fc897b0 | 4225 | if (ret_val) |
1da177e4 LT |
4226 | return ret_val; |
4227 | ||
2d7edb92 | 4228 | /* Translate to old method */ |
1da177e4 LT |
4229 | average = (max_length + min_length) / 2; |
4230 | ||
8fc897b0 | 4231 | if (average <= e1000_igp_cable_length_50) |
1da177e4 | 4232 | phy_info->cable_length = e1000_cable_length_50; |
8fc897b0 | 4233 | else if (average <= e1000_igp_cable_length_80) |
1da177e4 | 4234 | phy_info->cable_length = e1000_cable_length_50_80; |
8fc897b0 | 4235 | else if (average <= e1000_igp_cable_length_110) |
1da177e4 | 4236 | phy_info->cable_length = e1000_cable_length_80_110; |
8fc897b0 | 4237 | else if (average <= e1000_igp_cable_length_140) |
1da177e4 LT |
4238 | phy_info->cable_length = e1000_cable_length_110_140; |
4239 | else | |
4240 | phy_info->cable_length = e1000_cable_length_140; | |
4241 | } | |
4242 | ||
4243 | return E1000_SUCCESS; | |
4244 | } | |
4245 | ||
d37ea5d5 AK |
4246 | /****************************************************************************** |
4247 | * Get PHY information from various PHY registers for ife PHY only. | |
4248 | * | |
4249 | * hw - Struct containing variables accessed by shared code | |
4250 | * phy_info - PHY information structure | |
4251 | ******************************************************************************/ | |
e4c780b1 | 4252 | static int32_t |
d37ea5d5 AK |
4253 | e1000_phy_ife_get_info(struct e1000_hw *hw, |
4254 | struct e1000_phy_info *phy_info) | |
4255 | { | |
4256 | int32_t ret_val; | |
70c6f30a JK |
4257 | uint16_t phy_data; |
4258 | e1000_rev_polarity polarity; | |
d37ea5d5 AK |
4259 | |
4260 | DEBUGFUNC("e1000_phy_ife_get_info"); | |
4261 | ||
4262 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | |
4263 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
4264 | ||
4265 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | |
4266 | if (ret_val) | |
4267 | return ret_val; | |
4268 | phy_info->polarity_correction = | |
70c6f30a JK |
4269 | ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> |
4270 | IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? | |
4271 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | |
d37ea5d5 AK |
4272 | |
4273 | if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { | |
4274 | ret_val = e1000_check_polarity(hw, &polarity); | |
4275 | if (ret_val) | |
4276 | return ret_val; | |
4277 | } else { | |
4278 | /* Polarity is forced. */ | |
70c6f30a JK |
4279 | polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> |
4280 | IFE_PSC_FORCE_POLARITY_SHIFT) ? | |
4281 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
d37ea5d5 AK |
4282 | } |
4283 | phy_info->cable_polarity = polarity; | |
4284 | ||
4285 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | |
4286 | if (ret_val) | |
4287 | return ret_val; | |
4288 | ||
70c6f30a JK |
4289 | phy_info->mdix_mode = (e1000_auto_x_mode) |
4290 | ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> | |
4291 | IFE_PMC_MDIX_MODE_SHIFT); | |
d37ea5d5 AK |
4292 | |
4293 | return E1000_SUCCESS; | |
4294 | } | |
4295 | ||
1da177e4 LT |
4296 | /****************************************************************************** |
4297 | * Get PHY information from various PHY registers fot m88 PHY only. | |
4298 | * | |
4299 | * hw - Struct containing variables accessed by shared code | |
4300 | * phy_info - PHY information structure | |
4301 | ******************************************************************************/ | |
3ad2cc67 | 4302 | static int32_t |
1da177e4 LT |
4303 | e1000_phy_m88_get_info(struct e1000_hw *hw, |
4304 | struct e1000_phy_info *phy_info) | |
4305 | { | |
4306 | int32_t ret_val; | |
70c6f30a JK |
4307 | uint16_t phy_data; |
4308 | e1000_rev_polarity polarity; | |
1da177e4 LT |
4309 | |
4310 | DEBUGFUNC("e1000_phy_m88_get_info"); | |
4311 | ||
4312 | /* The downshift status is checked only once, after link is established, | |
4313 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 4314 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
4315 | |
4316 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 4317 | if (ret_val) |
1da177e4 LT |
4318 | return ret_val; |
4319 | ||
4320 | phy_info->extended_10bt_distance = | |
70c6f30a JK |
4321 | ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
4322 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? | |
4323 | e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; | |
4324 | ||
1da177e4 | 4325 | phy_info->polarity_correction = |
70c6f30a JK |
4326 | ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
4327 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? | |
4328 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | |
1da177e4 LT |
4329 | |
4330 | /* Check polarity status */ | |
4331 | ret_val = e1000_check_polarity(hw, &polarity); | |
8fc897b0 | 4332 | if (ret_val) |
76c224bc | 4333 | return ret_val; |
1da177e4 LT |
4334 | phy_info->cable_polarity = polarity; |
4335 | ||
4336 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
8fc897b0 | 4337 | if (ret_val) |
1da177e4 LT |
4338 | return ret_val; |
4339 | ||
70c6f30a JK |
4340 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> |
4341 | M88E1000_PSSR_MDIX_SHIFT); | |
1da177e4 LT |
4342 | |
4343 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
4344 | /* Cable Length Estimation and Local/Remote Receiver Information | |
4345 | * are only valid at 1000 Mbps. | |
4346 | */ | |
6418ecc6 | 4347 | if (hw->phy_type != e1000_phy_gg82563) { |
70c6f30a | 4348 | phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
6418ecc6 JK |
4349 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
4350 | } else { | |
4351 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
4352 | &phy_data); | |
4353 | if (ret_val) | |
4354 | return ret_val; | |
4355 | ||
70c6f30a | 4356 | phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); |
6418ecc6 | 4357 | } |
1da177e4 LT |
4358 | |
4359 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
8fc897b0 | 4360 | if (ret_val) |
1da177e4 LT |
4361 | return ret_val; |
4362 | ||
70c6f30a JK |
4363 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
4364 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | |
4365 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
4366 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
4367 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | |
4368 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
1da177e4 | 4369 | |
1da177e4 LT |
4370 | } |
4371 | ||
4372 | return E1000_SUCCESS; | |
4373 | } | |
4374 | ||
4375 | /****************************************************************************** | |
4376 | * Get PHY information from various PHY registers | |
4377 | * | |
4378 | * hw - Struct containing variables accessed by shared code | |
4379 | * phy_info - PHY information structure | |
4380 | ******************************************************************************/ | |
4381 | int32_t | |
4382 | e1000_phy_get_info(struct e1000_hw *hw, | |
4383 | struct e1000_phy_info *phy_info) | |
4384 | { | |
4385 | int32_t ret_val; | |
4386 | uint16_t phy_data; | |
4387 | ||
4388 | DEBUGFUNC("e1000_phy_get_info"); | |
4389 | ||
4390 | phy_info->cable_length = e1000_cable_length_undefined; | |
4391 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; | |
4392 | phy_info->cable_polarity = e1000_rev_polarity_undefined; | |
4393 | phy_info->downshift = e1000_downshift_undefined; | |
4394 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; | |
4395 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; | |
4396 | phy_info->local_rx = e1000_1000t_rx_status_undefined; | |
4397 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; | |
4398 | ||
8fc897b0 | 4399 | if (hw->media_type != e1000_media_type_copper) { |
1da177e4 LT |
4400 | DEBUGOUT("PHY info is only valid for copper media\n"); |
4401 | return -E1000_ERR_CONFIG; | |
4402 | } | |
4403 | ||
4404 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 4405 | if (ret_val) |
1da177e4 LT |
4406 | return ret_val; |
4407 | ||
4408 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 4409 | if (ret_val) |
1da177e4 LT |
4410 | return ret_val; |
4411 | ||
8fc897b0 | 4412 | if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
1da177e4 LT |
4413 | DEBUGOUT("PHY info is only valid if link is up\n"); |
4414 | return -E1000_ERR_CONFIG; | |
4415 | } | |
4416 | ||
cd94dd0b AK |
4417 | if (hw->phy_type == e1000_phy_igp || |
4418 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 4419 | hw->phy_type == e1000_phy_igp_2) |
1da177e4 | 4420 | return e1000_phy_igp_get_info(hw, phy_info); |
cd94dd0b AK |
4421 | else if (hw->phy_type == e1000_phy_ife) |
4422 | return e1000_phy_ife_get_info(hw, phy_info); | |
1da177e4 LT |
4423 | else |
4424 | return e1000_phy_m88_get_info(hw, phy_info); | |
4425 | } | |
4426 | ||
4427 | int32_t | |
4428 | e1000_validate_mdi_setting(struct e1000_hw *hw) | |
4429 | { | |
4430 | DEBUGFUNC("e1000_validate_mdi_settings"); | |
4431 | ||
8fc897b0 | 4432 | if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
1da177e4 LT |
4433 | DEBUGOUT("Invalid MDI setting detected\n"); |
4434 | hw->mdix = 1; | |
4435 | return -E1000_ERR_CONFIG; | |
4436 | } | |
4437 | return E1000_SUCCESS; | |
4438 | } | |
4439 | ||
4440 | ||
4441 | /****************************************************************************** | |
4442 | * Sets up eeprom variables in the hw struct. Must be called after mac_type | |
0f15a8fa JK |
4443 | * is configured. Additionally, if this is ICH8, the flash controller GbE |
4444 | * registers must be mapped, or this will crash. | |
1da177e4 LT |
4445 | * |
4446 | * hw - Struct containing variables accessed by shared code | |
4447 | *****************************************************************************/ | |
2d7edb92 | 4448 | int32_t |
1da177e4 LT |
4449 | e1000_init_eeprom_params(struct e1000_hw *hw) |
4450 | { | |
4451 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4452 | uint32_t eecd = E1000_READ_REG(hw, EECD); | |
2d7edb92 | 4453 | int32_t ret_val = E1000_SUCCESS; |
1da177e4 LT |
4454 | uint16_t eeprom_size; |
4455 | ||
4456 | DEBUGFUNC("e1000_init_eeprom_params"); | |
4457 | ||
4458 | switch (hw->mac_type) { | |
4459 | case e1000_82542_rev2_0: | |
4460 | case e1000_82542_rev2_1: | |
4461 | case e1000_82543: | |
4462 | case e1000_82544: | |
4463 | eeprom->type = e1000_eeprom_microwire; | |
4464 | eeprom->word_size = 64; | |
4465 | eeprom->opcode_bits = 3; | |
4466 | eeprom->address_bits = 6; | |
4467 | eeprom->delay_usec = 50; | |
2d7edb92 MC |
4468 | eeprom->use_eerd = FALSE; |
4469 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
4470 | break; |
4471 | case e1000_82540: | |
4472 | case e1000_82545: | |
4473 | case e1000_82545_rev_3: | |
4474 | case e1000_82546: | |
4475 | case e1000_82546_rev_3: | |
4476 | eeprom->type = e1000_eeprom_microwire; | |
4477 | eeprom->opcode_bits = 3; | |
4478 | eeprom->delay_usec = 50; | |
8fc897b0 | 4479 | if (eecd & E1000_EECD_SIZE) { |
1da177e4 LT |
4480 | eeprom->word_size = 256; |
4481 | eeprom->address_bits = 8; | |
4482 | } else { | |
4483 | eeprom->word_size = 64; | |
4484 | eeprom->address_bits = 6; | |
4485 | } | |
2d7edb92 MC |
4486 | eeprom->use_eerd = FALSE; |
4487 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
4488 | break; |
4489 | case e1000_82541: | |
4490 | case e1000_82541_rev_2: | |
4491 | case e1000_82547: | |
4492 | case e1000_82547_rev_2: | |
4493 | if (eecd & E1000_EECD_TYPE) { | |
4494 | eeprom->type = e1000_eeprom_spi; | |
4495 | eeprom->opcode_bits = 8; | |
4496 | eeprom->delay_usec = 1; | |
4497 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4498 | eeprom->page_size = 32; | |
4499 | eeprom->address_bits = 16; | |
4500 | } else { | |
4501 | eeprom->page_size = 8; | |
4502 | eeprom->address_bits = 8; | |
4503 | } | |
4504 | } else { | |
4505 | eeprom->type = e1000_eeprom_microwire; | |
4506 | eeprom->opcode_bits = 3; | |
4507 | eeprom->delay_usec = 50; | |
4508 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4509 | eeprom->word_size = 256; | |
4510 | eeprom->address_bits = 8; | |
4511 | } else { | |
4512 | eeprom->word_size = 64; | |
4513 | eeprom->address_bits = 6; | |
4514 | } | |
4515 | } | |
2d7edb92 MC |
4516 | eeprom->use_eerd = FALSE; |
4517 | eeprom->use_eewr = FALSE; | |
4518 | break; | |
868d5309 MC |
4519 | case e1000_82571: |
4520 | case e1000_82572: | |
4521 | eeprom->type = e1000_eeprom_spi; | |
4522 | eeprom->opcode_bits = 8; | |
4523 | eeprom->delay_usec = 1; | |
4524 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4525 | eeprom->page_size = 32; | |
4526 | eeprom->address_bits = 16; | |
4527 | } else { | |
4528 | eeprom->page_size = 8; | |
4529 | eeprom->address_bits = 8; | |
4530 | } | |
4531 | eeprom->use_eerd = FALSE; | |
4532 | eeprom->use_eewr = FALSE; | |
4533 | break; | |
2d7edb92 MC |
4534 | case e1000_82573: |
4535 | eeprom->type = e1000_eeprom_spi; | |
4536 | eeprom->opcode_bits = 8; | |
4537 | eeprom->delay_usec = 1; | |
4538 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4539 | eeprom->page_size = 32; | |
4540 | eeprom->address_bits = 16; | |
4541 | } else { | |
4542 | eeprom->page_size = 8; | |
4543 | eeprom->address_bits = 8; | |
4544 | } | |
4545 | eeprom->use_eerd = TRUE; | |
4546 | eeprom->use_eewr = TRUE; | |
8fc897b0 | 4547 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
2d7edb92 MC |
4548 | eeprom->type = e1000_eeprom_flash; |
4549 | eeprom->word_size = 2048; | |
4550 | ||
4551 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
4552 | * Flash update issue on parts which use a FLASH for NVM. */ | |
4553 | eecd &= ~E1000_EECD_AUPDEN; | |
4554 | E1000_WRITE_REG(hw, EECD, eecd); | |
4555 | } | |
1da177e4 | 4556 | break; |
6418ecc6 JK |
4557 | case e1000_80003es2lan: |
4558 | eeprom->type = e1000_eeprom_spi; | |
4559 | eeprom->opcode_bits = 8; | |
4560 | eeprom->delay_usec = 1; | |
4561 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4562 | eeprom->page_size = 32; | |
4563 | eeprom->address_bits = 16; | |
4564 | } else { | |
4565 | eeprom->page_size = 8; | |
4566 | eeprom->address_bits = 8; | |
4567 | } | |
4568 | eeprom->use_eerd = TRUE; | |
4569 | eeprom->use_eewr = FALSE; | |
4570 | break; | |
cd94dd0b | 4571 | case e1000_ich8lan: |
35574764 | 4572 | { |
cd94dd0b | 4573 | int32_t i = 0; |
2df7d59f | 4574 | uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); |
cd94dd0b AK |
4575 | |
4576 | eeprom->type = e1000_eeprom_ich8; | |
4577 | eeprom->use_eerd = FALSE; | |
4578 | eeprom->use_eewr = FALSE; | |
4579 | eeprom->word_size = E1000_SHADOW_RAM_WORDS; | |
4580 | ||
4581 | /* Zero the shadow RAM structure. But don't load it from NVM | |
4582 | * so as to save time for driver init */ | |
4583 | if (hw->eeprom_shadow_ram != NULL) { | |
4584 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
4585 | hw->eeprom_shadow_ram[i].modified = FALSE; | |
4586 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; | |
4587 | } | |
4588 | } | |
4589 | ||
2df7d59f JK |
4590 | hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * |
4591 | ICH_FLASH_SECTOR_SIZE; | |
4592 | ||
4593 | hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; | |
4594 | hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); | |
4595 | ||
4596 | hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; | |
cd94dd0b | 4597 | |
cd94dd0b AK |
4598 | hw->flash_bank_size /= 2 * sizeof(uint16_t); |
4599 | ||
4600 | break; | |
35574764 | 4601 | } |
1da177e4 LT |
4602 | default: |
4603 | break; | |
4604 | } | |
4605 | ||
4606 | if (eeprom->type == e1000_eeprom_spi) { | |
2d7edb92 MC |
4607 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
4608 | * 32KB (incremented by powers of 2). | |
4609 | */ | |
8fc897b0 | 4610 | if (hw->mac_type <= e1000_82547_rev_2) { |
2d7edb92 MC |
4611 | /* Set to default value for initial eeprom read. */ |
4612 | eeprom->word_size = 64; | |
4613 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); | |
8fc897b0 | 4614 | if (ret_val) |
2d7edb92 MC |
4615 | return ret_val; |
4616 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; | |
4617 | /* 256B eeprom size was not supported in earlier hardware, so we | |
4618 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) | |
4619 | * is never the result used in the shifting logic below. */ | |
8fc897b0 | 4620 | if (eeprom_size) |
2d7edb92 MC |
4621 | eeprom_size++; |
4622 | } else { | |
4623 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
4624 | E1000_EECD_SIZE_EX_SHIFT); | |
1da177e4 | 4625 | } |
2d7edb92 MC |
4626 | |
4627 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
1da177e4 | 4628 | } |
2d7edb92 | 4629 | return ret_val; |
1da177e4 LT |
4630 | } |
4631 | ||
4632 | /****************************************************************************** | |
4633 | * Raises the EEPROM's clock input. | |
4634 | * | |
4635 | * hw - Struct containing variables accessed by shared code | |
4636 | * eecd - EECD's current value | |
4637 | *****************************************************************************/ | |
4638 | static void | |
4639 | e1000_raise_ee_clk(struct e1000_hw *hw, | |
4640 | uint32_t *eecd) | |
4641 | { | |
4642 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
4643 | * wait <delay> microseconds. | |
4644 | */ | |
4645 | *eecd = *eecd | E1000_EECD_SK; | |
4646 | E1000_WRITE_REG(hw, EECD, *eecd); | |
4647 | E1000_WRITE_FLUSH(hw); | |
4648 | udelay(hw->eeprom.delay_usec); | |
4649 | } | |
4650 | ||
4651 | /****************************************************************************** | |
4652 | * Lowers the EEPROM's clock input. | |
4653 | * | |
4654 | * hw - Struct containing variables accessed by shared code | |
4655 | * eecd - EECD's current value | |
4656 | *****************************************************************************/ | |
4657 | static void | |
4658 | e1000_lower_ee_clk(struct e1000_hw *hw, | |
4659 | uint32_t *eecd) | |
4660 | { | |
4661 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | |
4662 | * wait 50 microseconds. | |
4663 | */ | |
4664 | *eecd = *eecd & ~E1000_EECD_SK; | |
4665 | E1000_WRITE_REG(hw, EECD, *eecd); | |
4666 | E1000_WRITE_FLUSH(hw); | |
4667 | udelay(hw->eeprom.delay_usec); | |
4668 | } | |
4669 | ||
4670 | /****************************************************************************** | |
4671 | * Shift data bits out to the EEPROM. | |
4672 | * | |
4673 | * hw - Struct containing variables accessed by shared code | |
4674 | * data - data to send to the EEPROM | |
4675 | * count - number of bits to shift out | |
4676 | *****************************************************************************/ | |
4677 | static void | |
4678 | e1000_shift_out_ee_bits(struct e1000_hw *hw, | |
4679 | uint16_t data, | |
4680 | uint16_t count) | |
4681 | { | |
4682 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4683 | uint32_t eecd; | |
4684 | uint32_t mask; | |
4685 | ||
4686 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
4687 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
4688 | * In order to do this, "data" must be broken down into bits. | |
4689 | */ | |
4690 | mask = 0x01 << (count - 1); | |
4691 | eecd = E1000_READ_REG(hw, EECD); | |
4692 | if (eeprom->type == e1000_eeprom_microwire) { | |
4693 | eecd &= ~E1000_EECD_DO; | |
4694 | } else if (eeprom->type == e1000_eeprom_spi) { | |
4695 | eecd |= E1000_EECD_DO; | |
4696 | } | |
4697 | do { | |
4698 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
4699 | * and then raising and then lowering the clock (the SK bit controls | |
4700 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
4701 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
4702 | */ | |
4703 | eecd &= ~E1000_EECD_DI; | |
4704 | ||
8fc897b0 | 4705 | if (data & mask) |
1da177e4 LT |
4706 | eecd |= E1000_EECD_DI; |
4707 | ||
4708 | E1000_WRITE_REG(hw, EECD, eecd); | |
4709 | E1000_WRITE_FLUSH(hw); | |
4710 | ||
4711 | udelay(eeprom->delay_usec); | |
4712 | ||
4713 | e1000_raise_ee_clk(hw, &eecd); | |
4714 | e1000_lower_ee_clk(hw, &eecd); | |
4715 | ||
4716 | mask = mask >> 1; | |
4717 | ||
8fc897b0 | 4718 | } while (mask); |
1da177e4 LT |
4719 | |
4720 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
4721 | eecd &= ~E1000_EECD_DI; | |
4722 | E1000_WRITE_REG(hw, EECD, eecd); | |
4723 | } | |
4724 | ||
4725 | /****************************************************************************** | |
4726 | * Shift data bits in from the EEPROM | |
4727 | * | |
4728 | * hw - Struct containing variables accessed by shared code | |
4729 | *****************************************************************************/ | |
4730 | static uint16_t | |
4731 | e1000_shift_in_ee_bits(struct e1000_hw *hw, | |
4732 | uint16_t count) | |
4733 | { | |
4734 | uint32_t eecd; | |
4735 | uint32_t i; | |
4736 | uint16_t data; | |
4737 | ||
4738 | /* In order to read a register from the EEPROM, we need to shift 'count' | |
4739 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
4740 | * input to the EEPROM (setting the SK bit), and then reading the value of | |
4741 | * the "DO" bit. During this "shifting in" process the "DI" bit should | |
4742 | * always be clear. | |
4743 | */ | |
4744 | ||
4745 | eecd = E1000_READ_REG(hw, EECD); | |
4746 | ||
4747 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
4748 | data = 0; | |
4749 | ||
8fc897b0 | 4750 | for (i = 0; i < count; i++) { |
1da177e4 LT |
4751 | data = data << 1; |
4752 | e1000_raise_ee_clk(hw, &eecd); | |
4753 | ||
4754 | eecd = E1000_READ_REG(hw, EECD); | |
4755 | ||
4756 | eecd &= ~(E1000_EECD_DI); | |
8fc897b0 | 4757 | if (eecd & E1000_EECD_DO) |
1da177e4 LT |
4758 | data |= 1; |
4759 | ||
4760 | e1000_lower_ee_clk(hw, &eecd); | |
4761 | } | |
4762 | ||
4763 | return data; | |
4764 | } | |
4765 | ||
4766 | /****************************************************************************** | |
4767 | * Prepares EEPROM for access | |
4768 | * | |
4769 | * hw - Struct containing variables accessed by shared code | |
4770 | * | |
4771 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
4772 | * function should be called before issuing a command to the EEPROM. | |
4773 | *****************************************************************************/ | |
4774 | static int32_t | |
4775 | e1000_acquire_eeprom(struct e1000_hw *hw) | |
4776 | { | |
4777 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4778 | uint32_t eecd, i=0; | |
4779 | ||
4780 | DEBUGFUNC("e1000_acquire_eeprom"); | |
4781 | ||
6418ecc6 JK |
4782 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
4783 | return -E1000_ERR_SWFW_SYNC; | |
1da177e4 LT |
4784 | eecd = E1000_READ_REG(hw, EECD); |
4785 | ||
2d7edb92 | 4786 | if (hw->mac_type != e1000_82573) { |
868d5309 | 4787 | /* Request EEPROM Access */ |
8fc897b0 | 4788 | if (hw->mac_type > e1000_82544) { |
868d5309 | 4789 | eecd |= E1000_EECD_REQ; |
1da177e4 | 4790 | E1000_WRITE_REG(hw, EECD, eecd); |
868d5309 | 4791 | eecd = E1000_READ_REG(hw, EECD); |
8fc897b0 | 4792 | while ((!(eecd & E1000_EECD_GNT)) && |
868d5309 MC |
4793 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
4794 | i++; | |
4795 | udelay(5); | |
4796 | eecd = E1000_READ_REG(hw, EECD); | |
4797 | } | |
8fc897b0 | 4798 | if (!(eecd & E1000_EECD_GNT)) { |
868d5309 MC |
4799 | eecd &= ~E1000_EECD_REQ; |
4800 | E1000_WRITE_REG(hw, EECD, eecd); | |
4801 | DEBUGOUT("Could not acquire EEPROM grant\n"); | |
6418ecc6 | 4802 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
868d5309 MC |
4803 | return -E1000_ERR_EEPROM; |
4804 | } | |
1da177e4 LT |
4805 | } |
4806 | } | |
4807 | ||
4808 | /* Setup EEPROM for Read/Write */ | |
4809 | ||
4810 | if (eeprom->type == e1000_eeprom_microwire) { | |
4811 | /* Clear SK and DI */ | |
4812 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
4813 | E1000_WRITE_REG(hw, EECD, eecd); | |
4814 | ||
4815 | /* Set CS */ | |
4816 | eecd |= E1000_EECD_CS; | |
4817 | E1000_WRITE_REG(hw, EECD, eecd); | |
4818 | } else if (eeprom->type == e1000_eeprom_spi) { | |
4819 | /* Clear SK and CS */ | |
4820 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
4821 | E1000_WRITE_REG(hw, EECD, eecd); | |
4822 | udelay(1); | |
4823 | } | |
4824 | ||
4825 | return E1000_SUCCESS; | |
4826 | } | |
4827 | ||
4828 | /****************************************************************************** | |
4829 | * Returns EEPROM to a "standby" state | |
4830 | * | |
4831 | * hw - Struct containing variables accessed by shared code | |
4832 | *****************************************************************************/ | |
4833 | static void | |
4834 | e1000_standby_eeprom(struct e1000_hw *hw) | |
4835 | { | |
4836 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4837 | uint32_t eecd; | |
4838 | ||
4839 | eecd = E1000_READ_REG(hw, EECD); | |
4840 | ||
8fc897b0 | 4841 | if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 LT |
4842 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
4843 | E1000_WRITE_REG(hw, EECD, eecd); | |
4844 | E1000_WRITE_FLUSH(hw); | |
4845 | udelay(eeprom->delay_usec); | |
4846 | ||
4847 | /* Clock high */ | |
4848 | eecd |= E1000_EECD_SK; | |
4849 | E1000_WRITE_REG(hw, EECD, eecd); | |
4850 | E1000_WRITE_FLUSH(hw); | |
4851 | udelay(eeprom->delay_usec); | |
4852 | ||
4853 | /* Select EEPROM */ | |
4854 | eecd |= E1000_EECD_CS; | |
4855 | E1000_WRITE_REG(hw, EECD, eecd); | |
4856 | E1000_WRITE_FLUSH(hw); | |
4857 | udelay(eeprom->delay_usec); | |
4858 | ||
4859 | /* Clock low */ | |
4860 | eecd &= ~E1000_EECD_SK; | |
4861 | E1000_WRITE_REG(hw, EECD, eecd); | |
4862 | E1000_WRITE_FLUSH(hw); | |
4863 | udelay(eeprom->delay_usec); | |
8fc897b0 | 4864 | } else if (eeprom->type == e1000_eeprom_spi) { |
1da177e4 LT |
4865 | /* Toggle CS to flush commands */ |
4866 | eecd |= E1000_EECD_CS; | |
4867 | E1000_WRITE_REG(hw, EECD, eecd); | |
4868 | E1000_WRITE_FLUSH(hw); | |
4869 | udelay(eeprom->delay_usec); | |
4870 | eecd &= ~E1000_EECD_CS; | |
4871 | E1000_WRITE_REG(hw, EECD, eecd); | |
4872 | E1000_WRITE_FLUSH(hw); | |
4873 | udelay(eeprom->delay_usec); | |
4874 | } | |
4875 | } | |
4876 | ||
4877 | /****************************************************************************** | |
4878 | * Terminates a command by inverting the EEPROM's chip select pin | |
4879 | * | |
4880 | * hw - Struct containing variables accessed by shared code | |
4881 | *****************************************************************************/ | |
4882 | static void | |
4883 | e1000_release_eeprom(struct e1000_hw *hw) | |
4884 | { | |
4885 | uint32_t eecd; | |
4886 | ||
4887 | DEBUGFUNC("e1000_release_eeprom"); | |
4888 | ||
4889 | eecd = E1000_READ_REG(hw, EECD); | |
4890 | ||
4891 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
4892 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
4893 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
4894 | ||
4895 | E1000_WRITE_REG(hw, EECD, eecd); | |
4896 | ||
4897 | udelay(hw->eeprom.delay_usec); | |
8fc897b0 | 4898 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
1da177e4 LT |
4899 | /* cleanup eeprom */ |
4900 | ||
4901 | /* CS on Microwire is active-high */ | |
4902 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
4903 | ||
4904 | E1000_WRITE_REG(hw, EECD, eecd); | |
4905 | ||
4906 | /* Rising edge of clock */ | |
4907 | eecd |= E1000_EECD_SK; | |
4908 | E1000_WRITE_REG(hw, EECD, eecd); | |
4909 | E1000_WRITE_FLUSH(hw); | |
4910 | udelay(hw->eeprom.delay_usec); | |
4911 | ||
4912 | /* Falling edge of clock */ | |
4913 | eecd &= ~E1000_EECD_SK; | |
4914 | E1000_WRITE_REG(hw, EECD, eecd); | |
4915 | E1000_WRITE_FLUSH(hw); | |
4916 | udelay(hw->eeprom.delay_usec); | |
4917 | } | |
4918 | ||
4919 | /* Stop requesting EEPROM access */ | |
8fc897b0 | 4920 | if (hw->mac_type > e1000_82544) { |
1da177e4 LT |
4921 | eecd &= ~E1000_EECD_REQ; |
4922 | E1000_WRITE_REG(hw, EECD, eecd); | |
4923 | } | |
2d7edb92 | 4924 | |
6418ecc6 | 4925 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
1da177e4 LT |
4926 | } |
4927 | ||
4928 | /****************************************************************************** | |
4929 | * Reads a 16 bit word from the EEPROM. | |
4930 | * | |
4931 | * hw - Struct containing variables accessed by shared code | |
4932 | *****************************************************************************/ | |
35574764 | 4933 | static int32_t |
1da177e4 LT |
4934 | e1000_spi_eeprom_ready(struct e1000_hw *hw) |
4935 | { | |
4936 | uint16_t retry_count = 0; | |
4937 | uint8_t spi_stat_reg; | |
4938 | ||
4939 | DEBUGFUNC("e1000_spi_eeprom_ready"); | |
4940 | ||
4941 | /* Read "Status Register" repeatedly until the LSB is cleared. The | |
4942 | * EEPROM will signal that the command has been completed by clearing | |
4943 | * bit 0 of the internal status register. If it's not cleared within | |
4944 | * 5 milliseconds, then error out. | |
4945 | */ | |
4946 | retry_count = 0; | |
4947 | do { | |
4948 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
4949 | hw->eeprom.opcode_bits); | |
4950 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); | |
4951 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | |
4952 | break; | |
4953 | ||
4954 | udelay(5); | |
4955 | retry_count += 5; | |
4956 | ||
4957 | e1000_standby_eeprom(hw); | |
8fc897b0 | 4958 | } while (retry_count < EEPROM_MAX_RETRY_SPI); |
1da177e4 LT |
4959 | |
4960 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
4961 | * only 0-5mSec on 5V devices) | |
4962 | */ | |
8fc897b0 | 4963 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
1da177e4 LT |
4964 | DEBUGOUT("SPI EEPROM Status error\n"); |
4965 | return -E1000_ERR_EEPROM; | |
4966 | } | |
4967 | ||
4968 | return E1000_SUCCESS; | |
4969 | } | |
4970 | ||
4971 | /****************************************************************************** | |
4972 | * Reads a 16 bit word from the EEPROM. | |
4973 | * | |
4974 | * hw - Struct containing variables accessed by shared code | |
4975 | * offset - offset of word in the EEPROM to read | |
4976 | * data - word read from the EEPROM | |
4977 | * words - number of words to read | |
4978 | *****************************************************************************/ | |
4979 | int32_t | |
4980 | e1000_read_eeprom(struct e1000_hw *hw, | |
4981 | uint16_t offset, | |
4982 | uint16_t words, | |
4983 | uint16_t *data) | |
4984 | { | |
4985 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4986 | uint32_t i = 0; | |
4987 | ||
4988 | DEBUGFUNC("e1000_read_eeprom"); | |
2d7edb92 | 4989 | |
2a88c173 JK |
4990 | /* If eeprom is not yet detected, do so now */ |
4991 | if (eeprom->word_size == 0) | |
4992 | e1000_init_eeprom_params(hw); | |
4993 | ||
1da177e4 LT |
4994 | /* A check for invalid values: offset too large, too many words, and not |
4995 | * enough words. | |
4996 | */ | |
8fc897b0 | 4997 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
1da177e4 | 4998 | (words == 0)) { |
2a88c173 | 4999 | DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); |
1da177e4 LT |
5000 | return -E1000_ERR_EEPROM; |
5001 | } | |
5002 | ||
2a88c173 JK |
5003 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
5004 | * directly. In this case, we need to acquire the EEPROM so that | |
5005 | * FW or other port software does not interrupt. | |
5006 | */ | |
4d351858 | 5007 | if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && |
8fc897b0 | 5008 | hw->eeprom.use_eerd == FALSE) { |
2a88c173 JK |
5009 | /* Prepare the EEPROM for bit-bang reading */ |
5010 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
5011 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
5012 | } |
5013 | ||
2a88c173 JK |
5014 | /* Eerd register EEPROM access requires no eeprom aquire/release */ |
5015 | if (eeprom->use_eerd == TRUE) | |
5016 | return e1000_read_eeprom_eerd(hw, offset, words, data); | |
1da177e4 | 5017 | |
2a88c173 | 5018 | /* ICH EEPROM access is done via the ICH flash controller */ |
cd94dd0b AK |
5019 | if (eeprom->type == e1000_eeprom_ich8) |
5020 | return e1000_read_eeprom_ich8(hw, offset, words, data); | |
5021 | ||
2a88c173 JK |
5022 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
5023 | * acquired the EEPROM at this point, so any returns should relase it */ | |
cd94dd0b | 5024 | if (eeprom->type == e1000_eeprom_spi) { |
1da177e4 LT |
5025 | uint16_t word_in; |
5026 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; | |
5027 | ||
8fc897b0 | 5028 | if (e1000_spi_eeprom_ready(hw)) { |
1da177e4 LT |
5029 | e1000_release_eeprom(hw); |
5030 | return -E1000_ERR_EEPROM; | |
5031 | } | |
5032 | ||
5033 | e1000_standby_eeprom(hw); | |
5034 | ||
5035 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
8fc897b0 | 5036 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
1da177e4 LT |
5037 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
5038 | ||
5039 | /* Send the READ command (opcode + addr) */ | |
5040 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
5041 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); | |
5042 | ||
5043 | /* Read the data. The address of the eeprom internally increments with | |
5044 | * each byte (spi) being read, saving on the overhead of eeprom setup | |
5045 | * and tear-down. The address counter will roll over if reading beyond | |
5046 | * the size of the eeprom, thus allowing the entire memory to be read | |
5047 | * starting from any offset. */ | |
5048 | for (i = 0; i < words; i++) { | |
5049 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
5050 | data[i] = (word_in >> 8) | (word_in << 8); | |
5051 | } | |
8fc897b0 | 5052 | } else if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 LT |
5053 | for (i = 0; i < words; i++) { |
5054 | /* Send the READ command (opcode + addr) */ | |
5055 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, | |
5056 | eeprom->opcode_bits); | |
5057 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), | |
5058 | eeprom->address_bits); | |
5059 | ||
5060 | /* Read the data. For microwire, each word requires the overhead | |
5061 | * of eeprom setup and tear-down. */ | |
5062 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
5063 | e1000_standby_eeprom(hw); | |
5064 | } | |
5065 | } | |
5066 | ||
5067 | /* End this read operation */ | |
5068 | e1000_release_eeprom(hw); | |
5069 | ||
5070 | return E1000_SUCCESS; | |
5071 | } | |
5072 | ||
5073 | /****************************************************************************** | |
2d7edb92 | 5074 | * Reads a 16 bit word from the EEPROM using the EERD register. |
1da177e4 LT |
5075 | * |
5076 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
5077 | * offset - offset of word in the EEPROM to read |
5078 | * data - word read from the EEPROM | |
5079 | * words - number of words to read | |
1da177e4 | 5080 | *****************************************************************************/ |
3ad2cc67 | 5081 | static int32_t |
2d7edb92 MC |
5082 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
5083 | uint16_t offset, | |
5084 | uint16_t words, | |
5085 | uint16_t *data) | |
1da177e4 | 5086 | { |
2d7edb92 MC |
5087 | uint32_t i, eerd = 0; |
5088 | int32_t error = 0; | |
1da177e4 | 5089 | |
2d7edb92 MC |
5090 | for (i = 0; i < words; i++) { |
5091 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
5092 | E1000_EEPROM_RW_REG_START; | |
1da177e4 | 5093 | |
2d7edb92 MC |
5094 | E1000_WRITE_REG(hw, EERD, eerd); |
5095 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); | |
76c224bc | 5096 | |
8fc897b0 | 5097 | if (error) { |
2d7edb92 | 5098 | break; |
1da177e4 | 5099 | } |
2d7edb92 | 5100 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
76c224bc | 5101 | |
1da177e4 | 5102 | } |
76c224bc | 5103 | |
2d7edb92 | 5104 | return error; |
1da177e4 LT |
5105 | } |
5106 | ||
5107 | /****************************************************************************** | |
2d7edb92 | 5108 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
1da177e4 LT |
5109 | * |
5110 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
5111 | * offset - offset of word in the EEPROM to read |
5112 | * data - word read from the EEPROM | |
5113 | * words - number of words to read | |
1da177e4 | 5114 | *****************************************************************************/ |
3ad2cc67 | 5115 | static int32_t |
2d7edb92 MC |
5116 | e1000_write_eeprom_eewr(struct e1000_hw *hw, |
5117 | uint16_t offset, | |
5118 | uint16_t words, | |
5119 | uint16_t *data) | |
1da177e4 | 5120 | { |
2d7edb92 MC |
5121 | uint32_t register_value = 0; |
5122 | uint32_t i = 0; | |
5123 | int32_t error = 0; | |
1da177e4 | 5124 | |
6418ecc6 JK |
5125 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
5126 | return -E1000_ERR_SWFW_SYNC; | |
5127 | ||
2d7edb92 | 5128 | for (i = 0; i < words; i++) { |
76c224bc AK |
5129 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
5130 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | |
2d7edb92 | 5131 | E1000_EEPROM_RW_REG_START; |
1da177e4 | 5132 | |
2d7edb92 | 5133 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
8fc897b0 | 5134 | if (error) { |
2d7edb92 | 5135 | break; |
76c224bc | 5136 | } |
2d7edb92 MC |
5137 | |
5138 | E1000_WRITE_REG(hw, EEWR, register_value); | |
76c224bc | 5139 | |
2d7edb92 | 5140 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
76c224bc | 5141 | |
8fc897b0 | 5142 | if (error) { |
2d7edb92 | 5143 | break; |
76c224bc | 5144 | } |
2d7edb92 | 5145 | } |
76c224bc | 5146 | |
6418ecc6 | 5147 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
2d7edb92 MC |
5148 | return error; |
5149 | } | |
5150 | ||
5151 | /****************************************************************************** | |
5152 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
5153 | * | |
5154 | * hw - Struct containing variables accessed by shared code | |
5155 | *****************************************************************************/ | |
3ad2cc67 | 5156 | static int32_t |
2d7edb92 MC |
5157 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
5158 | { | |
5159 | uint32_t attempts = 100000; | |
5160 | uint32_t i, reg = 0; | |
5161 | int32_t done = E1000_ERR_EEPROM; | |
5162 | ||
8fc897b0 AK |
5163 | for (i = 0; i < attempts; i++) { |
5164 | if (eerd == E1000_EEPROM_POLL_READ) | |
2d7edb92 | 5165 | reg = E1000_READ_REG(hw, EERD); |
76c224bc | 5166 | else |
2d7edb92 MC |
5167 | reg = E1000_READ_REG(hw, EEWR); |
5168 | ||
8fc897b0 | 5169 | if (reg & E1000_EEPROM_RW_REG_DONE) { |
2d7edb92 MC |
5170 | done = E1000_SUCCESS; |
5171 | break; | |
5172 | } | |
5173 | udelay(5); | |
5174 | } | |
5175 | ||
5176 | return done; | |
5177 | } | |
5178 | ||
5179 | /*************************************************************************** | |
5180 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
5181 | * | |
5182 | * hw - Struct containing variables accessed by shared code | |
5183 | ****************************************************************************/ | |
3ad2cc67 | 5184 | static boolean_t |
2d7edb92 MC |
5185 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
5186 | { | |
5187 | uint32_t eecd = 0; | |
5188 | ||
6418ecc6 JK |
5189 | DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
5190 | ||
cd94dd0b AK |
5191 | if (hw->mac_type == e1000_ich8lan) |
5192 | return FALSE; | |
5193 | ||
5194 | if (hw->mac_type == e1000_82573) { | |
2d7edb92 MC |
5195 | eecd = E1000_READ_REG(hw, EECD); |
5196 | ||
5197 | /* Isolate bits 15 & 16 */ | |
5198 | eecd = ((eecd >> 15) & 0x03); | |
5199 | ||
5200 | /* If both bits are set, device is Flash type */ | |
8fc897b0 | 5201 | if (eecd == 0x03) { |
2d7edb92 MC |
5202 | return FALSE; |
5203 | } | |
5204 | } | |
5205 | return TRUE; | |
5206 | } | |
5207 | ||
5208 | /****************************************************************************** | |
5209 | * Verifies that the EEPROM has a valid checksum | |
5210 | * | |
5211 | * hw - Struct containing variables accessed by shared code | |
5212 | * | |
5213 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
5214 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
5215 | * valid. | |
5216 | *****************************************************************************/ | |
5217 | int32_t | |
5218 | e1000_validate_eeprom_checksum(struct e1000_hw *hw) | |
5219 | { | |
5220 | uint16_t checksum = 0; | |
5221 | uint16_t i, eeprom_data; | |
5222 | ||
5223 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | |
5224 | ||
5225 | if ((hw->mac_type == e1000_82573) && | |
5226 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { | |
5227 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | |
5228 | * 10h-12h. Checksum may need to be fixed. */ | |
5229 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | |
5230 | if ((eeprom_data & 0x10) == 0) { | |
5231 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | |
5232 | * has already been fixed. If the checksum is still wrong and this | |
5233 | * bit is a 1, we need to return bad checksum. Otherwise, we need | |
5234 | * to set this bit to a 1 and update the checksum. */ | |
5235 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | |
5236 | if ((eeprom_data & 0x8000) == 0) { | |
5237 | eeprom_data |= 0x8000; | |
5238 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | |
5239 | e1000_update_eeprom_checksum(hw); | |
5240 | } | |
5241 | } | |
5242 | } | |
5243 | ||
cd94dd0b AK |
5244 | if (hw->mac_type == e1000_ich8lan) { |
5245 | /* Drivers must allocate the shadow ram structure for the | |
5246 | * EEPROM checksum to be updated. Otherwise, this bit as well | |
5247 | * as the checksum must both be set correctly for this | |
5248 | * validation to pass. | |
5249 | */ | |
5250 | e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); | |
5251 | if ((eeprom_data & 0x40) == 0) { | |
5252 | eeprom_data |= 0x40; | |
5253 | e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); | |
5254 | e1000_update_eeprom_checksum(hw); | |
5255 | } | |
5256 | } | |
5257 | ||
5258 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | |
5259 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
2d7edb92 MC |
5260 | DEBUGOUT("EEPROM Read Error\n"); |
5261 | return -E1000_ERR_EEPROM; | |
5262 | } | |
5263 | checksum += eeprom_data; | |
5264 | } | |
5265 | ||
8fc897b0 | 5266 | if (checksum == (uint16_t) EEPROM_SUM) |
2d7edb92 MC |
5267 | return E1000_SUCCESS; |
5268 | else { | |
5269 | DEBUGOUT("EEPROM Checksum Invalid\n"); | |
5270 | return -E1000_ERR_EEPROM; | |
5271 | } | |
5272 | } | |
5273 | ||
5274 | /****************************************************************************** | |
5275 | * Calculates the EEPROM checksum and writes it to the EEPROM | |
5276 | * | |
5277 | * hw - Struct containing variables accessed by shared code | |
5278 | * | |
5279 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | |
5280 | * Writes the difference to word offset 63 of the EEPROM. | |
5281 | *****************************************************************************/ | |
5282 | int32_t | |
5283 | e1000_update_eeprom_checksum(struct e1000_hw *hw) | |
5284 | { | |
cd94dd0b | 5285 | uint32_t ctrl_ext; |
2d7edb92 MC |
5286 | uint16_t checksum = 0; |
5287 | uint16_t i, eeprom_data; | |
5288 | ||
5289 | DEBUGFUNC("e1000_update_eeprom_checksum"); | |
5290 | ||
8fc897b0 AK |
5291 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
5292 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
2d7edb92 MC |
5293 | DEBUGOUT("EEPROM Read Error\n"); |
5294 | return -E1000_ERR_EEPROM; | |
5295 | } | |
5296 | checksum += eeprom_data; | |
5297 | } | |
5298 | checksum = (uint16_t) EEPROM_SUM - checksum; | |
8fc897b0 | 5299 | if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
1da177e4 LT |
5300 | DEBUGOUT("EEPROM Write Error\n"); |
5301 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
5302 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
5303 | e1000_commit_shadow_ram(hw); | |
cd94dd0b AK |
5304 | } else if (hw->eeprom.type == e1000_eeprom_ich8) { |
5305 | e1000_commit_shadow_ram(hw); | |
5306 | /* Reload the EEPROM, or else modifications will not appear | |
5307 | * until after next adapter reset. */ | |
5308 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
5309 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
5310 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
f8ec4733 | 5311 | msleep(10); |
1da177e4 LT |
5312 | } |
5313 | return E1000_SUCCESS; | |
5314 | } | |
5315 | ||
5316 | /****************************************************************************** | |
5317 | * Parent function for writing words to the different EEPROM types. | |
5318 | * | |
5319 | * hw - Struct containing variables accessed by shared code | |
5320 | * offset - offset within the EEPROM to be written to | |
5321 | * words - number of words to write | |
5322 | * data - 16 bit word to be written to the EEPROM | |
5323 | * | |
5324 | * If e1000_update_eeprom_checksum is not called after this function, the | |
5325 | * EEPROM will most likely contain an invalid checksum. | |
5326 | *****************************************************************************/ | |
5327 | int32_t | |
5328 | e1000_write_eeprom(struct e1000_hw *hw, | |
5329 | uint16_t offset, | |
5330 | uint16_t words, | |
5331 | uint16_t *data) | |
5332 | { | |
5333 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
5334 | int32_t status = 0; | |
5335 | ||
5336 | DEBUGFUNC("e1000_write_eeprom"); | |
5337 | ||
2a88c173 JK |
5338 | /* If eeprom is not yet detected, do so now */ |
5339 | if (eeprom->word_size == 0) | |
5340 | e1000_init_eeprom_params(hw); | |
5341 | ||
1da177e4 LT |
5342 | /* A check for invalid values: offset too large, too many words, and not |
5343 | * enough words. | |
5344 | */ | |
8fc897b0 | 5345 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
1da177e4 LT |
5346 | (words == 0)) { |
5347 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
5348 | return -E1000_ERR_EEPROM; | |
5349 | } | |
5350 | ||
868d5309 | 5351 | /* 82573 writes only through eewr */ |
8fc897b0 | 5352 | if (eeprom->use_eewr == TRUE) |
2d7edb92 MC |
5353 | return e1000_write_eeprom_eewr(hw, offset, words, data); |
5354 | ||
cd94dd0b AK |
5355 | if (eeprom->type == e1000_eeprom_ich8) |
5356 | return e1000_write_eeprom_ich8(hw, offset, words, data); | |
5357 | ||
1da177e4 LT |
5358 | /* Prepare the EEPROM for writing */ |
5359 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
5360 | return -E1000_ERR_EEPROM; | |
5361 | ||
8fc897b0 | 5362 | if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 LT |
5363 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
5364 | } else { | |
5365 | status = e1000_write_eeprom_spi(hw, offset, words, data); | |
f8ec4733 | 5366 | msleep(10); |
1da177e4 LT |
5367 | } |
5368 | ||
5369 | /* Done with writing */ | |
5370 | e1000_release_eeprom(hw); | |
5371 | ||
5372 | return status; | |
5373 | } | |
5374 | ||
5375 | /****************************************************************************** | |
5376 | * Writes a 16 bit word to a given offset in an SPI EEPROM. | |
5377 | * | |
5378 | * hw - Struct containing variables accessed by shared code | |
5379 | * offset - offset within the EEPROM to be written to | |
5380 | * words - number of words to write | |
5381 | * data - pointer to array of 8 bit words to be written to the EEPROM | |
5382 | * | |
5383 | *****************************************************************************/ | |
35574764 | 5384 | static int32_t |
1da177e4 LT |
5385 | e1000_write_eeprom_spi(struct e1000_hw *hw, |
5386 | uint16_t offset, | |
5387 | uint16_t words, | |
5388 | uint16_t *data) | |
5389 | { | |
5390 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
5391 | uint16_t widx = 0; | |
5392 | ||
5393 | DEBUGFUNC("e1000_write_eeprom_spi"); | |
5394 | ||
5395 | while (widx < words) { | |
5396 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; | |
5397 | ||
8fc897b0 | 5398 | if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
1da177e4 LT |
5399 | |
5400 | e1000_standby_eeprom(hw); | |
5401 | ||
5402 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
5403 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, | |
5404 | eeprom->opcode_bits); | |
5405 | ||
5406 | e1000_standby_eeprom(hw); | |
5407 | ||
5408 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
8fc897b0 | 5409 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
1da177e4 LT |
5410 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
5411 | ||
5412 | /* Send the Write command (8-bit opcode + addr) */ | |
5413 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); | |
5414 | ||
5415 | e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), | |
5416 | eeprom->address_bits); | |
5417 | ||
5418 | /* Send the data */ | |
5419 | ||
5420 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ | |
5421 | while (widx < words) { | |
5422 | uint16_t word_out = data[widx]; | |
5423 | word_out = (word_out >> 8) | (word_out << 8); | |
5424 | e1000_shift_out_ee_bits(hw, word_out, 16); | |
5425 | widx++; | |
5426 | ||
5427 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE | |
5428 | * operation, while the smaller eeproms are capable of an 8-byte | |
5429 | * PAGE WRITE operation. Break the inner loop to pass new address | |
5430 | */ | |
8fc897b0 | 5431 | if ((((offset + widx)*2) % eeprom->page_size) == 0) { |
1da177e4 LT |
5432 | e1000_standby_eeprom(hw); |
5433 | break; | |
5434 | } | |
5435 | } | |
5436 | } | |
5437 | ||
5438 | return E1000_SUCCESS; | |
5439 | } | |
5440 | ||
5441 | /****************************************************************************** | |
5442 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. | |
5443 | * | |
5444 | * hw - Struct containing variables accessed by shared code | |
5445 | * offset - offset within the EEPROM to be written to | |
5446 | * words - number of words to write | |
5447 | * data - pointer to array of 16 bit words to be written to the EEPROM | |
5448 | * | |
5449 | *****************************************************************************/ | |
35574764 | 5450 | static int32_t |
1da177e4 LT |
5451 | e1000_write_eeprom_microwire(struct e1000_hw *hw, |
5452 | uint16_t offset, | |
5453 | uint16_t words, | |
5454 | uint16_t *data) | |
5455 | { | |
5456 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
5457 | uint32_t eecd; | |
5458 | uint16_t words_written = 0; | |
5459 | uint16_t i = 0; | |
5460 | ||
5461 | DEBUGFUNC("e1000_write_eeprom_microwire"); | |
5462 | ||
5463 | /* Send the write enable command to the EEPROM (3-bit opcode plus | |
5464 | * 6/8-bit dummy address beginning with 11). It's less work to include | |
5465 | * the 11 of the dummy address as part of the opcode than it is to shift | |
5466 | * it over the correct number of bits for the address. This puts the | |
5467 | * EEPROM into write/erase mode. | |
5468 | */ | |
5469 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, | |
5470 | (uint16_t)(eeprom->opcode_bits + 2)); | |
5471 | ||
5472 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
5473 | ||
5474 | /* Prepare the EEPROM */ | |
5475 | e1000_standby_eeprom(hw); | |
5476 | ||
5477 | while (words_written < words) { | |
5478 | /* Send the Write command (3-bit opcode + addr) */ | |
5479 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, | |
5480 | eeprom->opcode_bits); | |
5481 | ||
5482 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), | |
5483 | eeprom->address_bits); | |
5484 | ||
5485 | /* Send the data */ | |
5486 | e1000_shift_out_ee_bits(hw, data[words_written], 16); | |
5487 | ||
5488 | /* Toggle the CS line. This in effect tells the EEPROM to execute | |
5489 | * the previous command. | |
5490 | */ | |
5491 | e1000_standby_eeprom(hw); | |
5492 | ||
5493 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will | |
5494 | * signal that the command has been completed by raising the DO signal. | |
5495 | * If DO does not go high in 10 milliseconds, then error out. | |
5496 | */ | |
8fc897b0 | 5497 | for (i = 0; i < 200; i++) { |
1da177e4 | 5498 | eecd = E1000_READ_REG(hw, EECD); |
8fc897b0 | 5499 | if (eecd & E1000_EECD_DO) break; |
1da177e4 LT |
5500 | udelay(50); |
5501 | } | |
8fc897b0 | 5502 | if (i == 200) { |
1da177e4 LT |
5503 | DEBUGOUT("EEPROM Write did not complete\n"); |
5504 | return -E1000_ERR_EEPROM; | |
5505 | } | |
5506 | ||
5507 | /* Recover from write */ | |
5508 | e1000_standby_eeprom(hw); | |
5509 | ||
5510 | words_written++; | |
5511 | } | |
5512 | ||
5513 | /* Send the write disable command to the EEPROM (3-bit opcode plus | |
5514 | * 6/8-bit dummy address beginning with 10). It's less work to include | |
5515 | * the 10 of the dummy address as part of the opcode than it is to shift | |
5516 | * it over the correct number of bits for the address. This takes the | |
5517 | * EEPROM out of write/erase mode. | |
5518 | */ | |
5519 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, | |
5520 | (uint16_t)(eeprom->opcode_bits + 2)); | |
5521 | ||
5522 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
5523 | ||
5524 | return E1000_SUCCESS; | |
5525 | } | |
5526 | ||
2d7edb92 MC |
5527 | /****************************************************************************** |
5528 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | |
5529 | * in the eeprom cache and the non modified values in the currently active bank | |
5530 | * to the new bank. | |
5531 | * | |
5532 | * hw - Struct containing variables accessed by shared code | |
5533 | * offset - offset of word in the EEPROM to read | |
5534 | * data - word read from the EEPROM | |
5535 | * words - number of words to read | |
5536 | *****************************************************************************/ | |
3ad2cc67 | 5537 | static int32_t |
2d7edb92 MC |
5538 | e1000_commit_shadow_ram(struct e1000_hw *hw) |
5539 | { | |
5540 | uint32_t attempts = 100000; | |
5541 | uint32_t eecd = 0; | |
5542 | uint32_t flop = 0; | |
5543 | uint32_t i = 0; | |
5544 | int32_t error = E1000_SUCCESS; | |
cd94dd0b AK |
5545 | uint32_t old_bank_offset = 0; |
5546 | uint32_t new_bank_offset = 0; | |
cd94dd0b AK |
5547 | uint8_t low_byte = 0; |
5548 | uint8_t high_byte = 0; | |
cd94dd0b | 5549 | boolean_t sector_write_failed = FALSE; |
2d7edb92 MC |
5550 | |
5551 | if (hw->mac_type == e1000_82573) { | |
cd94dd0b AK |
5552 | /* The flop register will be used to determine if flash type is STM */ |
5553 | flop = E1000_READ_REG(hw, FLOP); | |
2d7edb92 MC |
5554 | for (i=0; i < attempts; i++) { |
5555 | eecd = E1000_READ_REG(hw, EECD); | |
5556 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
5557 | break; | |
5558 | } | |
5559 | udelay(5); | |
5560 | } | |
5561 | ||
5562 | if (i == attempts) { | |
5563 | return -E1000_ERR_EEPROM; | |
5564 | } | |
5565 | ||
96838a40 | 5566 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
2d7edb92 MC |
5567 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
5568 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); | |
5569 | } | |
5570 | ||
5571 | /* Perform the flash update */ | |
5572 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); | |
5573 | ||
96838a40 | 5574 | for (i=0; i < attempts; i++) { |
2d7edb92 MC |
5575 | eecd = E1000_READ_REG(hw, EECD); |
5576 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
5577 | break; | |
5578 | } | |
5579 | udelay(5); | |
5580 | } | |
5581 | ||
5582 | if (i == attempts) { | |
5583 | return -E1000_ERR_EEPROM; | |
5584 | } | |
5585 | } | |
5586 | ||
cd94dd0b AK |
5587 | if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { |
5588 | /* We're writing to the opposite bank so if we're on bank 1, | |
5589 | * write to bank 0 etc. We also need to erase the segment that | |
5590 | * is going to be written */ | |
5591 | if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { | |
5592 | new_bank_offset = hw->flash_bank_size * 2; | |
5593 | old_bank_offset = 0; | |
5594 | e1000_erase_ich8_4k_segment(hw, 1); | |
5595 | } else { | |
5596 | old_bank_offset = hw->flash_bank_size * 2; | |
5597 | new_bank_offset = 0; | |
5598 | e1000_erase_ich8_4k_segment(hw, 0); | |
5599 | } | |
5600 | ||
2a88c173 JK |
5601 | sector_write_failed = FALSE; |
5602 | /* Loop for every byte in the shadow RAM, | |
5603 | * which is in units of words. */ | |
5604 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
5605 | /* Determine whether to write the value stored | |
5606 | * in the other NVM bank or a modified value stored | |
5607 | * in the shadow RAM */ | |
5608 | if (hw->eeprom_shadow_ram[i].modified == TRUE) { | |
5609 | low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; | |
5610 | udelay(100); | |
5611 | error = e1000_verify_write_ich8_byte(hw, | |
5612 | (i << 1) + new_bank_offset, low_byte); | |
5613 | ||
5614 | if (error != E1000_SUCCESS) | |
5615 | sector_write_failed = TRUE; | |
5616 | else { | |
cd94dd0b AK |
5617 | high_byte = |
5618 | (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); | |
cd94dd0b | 5619 | udelay(100); |
2a88c173 JK |
5620 | } |
5621 | } else { | |
5622 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, | |
5623 | &low_byte); | |
5624 | udelay(100); | |
5625 | error = e1000_verify_write_ich8_byte(hw, | |
5626 | (i << 1) + new_bank_offset, low_byte); | |
5627 | ||
5628 | if (error != E1000_SUCCESS) | |
5629 | sector_write_failed = TRUE; | |
5630 | else { | |
cd94dd0b AK |
5631 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
5632 | &high_byte); | |
2a88c173 | 5633 | udelay(100); |
cd94dd0b | 5634 | } |
2a88c173 | 5635 | } |
cd94dd0b | 5636 | |
2a88c173 JK |
5637 | /* If the write of the low byte was successful, go ahread and |
5638 | * write the high byte while checking to make sure that if it | |
5639 | * is the signature byte, then it is handled properly */ | |
5640 | if (sector_write_failed == FALSE) { | |
cd94dd0b AK |
5641 | /* If the word is 0x13, then make sure the signature bits |
5642 | * (15:14) are 11b until the commit has completed. | |
5643 | * This will allow us to write 10b which indicates the | |
5644 | * signature is valid. We want to do this after the write | |
5645 | * has completed so that we don't mark the segment valid | |
5646 | * while the write is still in progress */ | |
2df7d59f JK |
5647 | if (i == E1000_ICH_NVM_SIG_WORD) |
5648 | high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; | |
cd94dd0b AK |
5649 | |
5650 | error = e1000_verify_write_ich8_byte(hw, | |
2a88c173 | 5651 | (i << 1) + new_bank_offset + 1, high_byte); |
cd94dd0b AK |
5652 | if (error != E1000_SUCCESS) |
5653 | sector_write_failed = TRUE; | |
5654 | ||
2a88c173 JK |
5655 | } else { |
5656 | /* If the write failed then break from the loop and | |
5657 | * return an error */ | |
5658 | break; | |
cd94dd0b | 5659 | } |
2a88c173 | 5660 | } |
cd94dd0b | 5661 | |
2a88c173 JK |
5662 | /* Don't bother writing the segment valid bits if sector |
5663 | * programming failed. */ | |
5664 | if (sector_write_failed == FALSE) { | |
5665 | /* Finally validate the new segment by setting bit 15:14 | |
5666 | * to 10b in word 0x13 , this can be done without an | |
5667 | * erase as well since these bits are 11 to start with | |
5668 | * and we need to change bit 14 to 0b */ | |
5669 | e1000_read_ich8_byte(hw, | |
2df7d59f | 5670 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
2a88c173 JK |
5671 | &high_byte); |
5672 | high_byte &= 0xBF; | |
5673 | error = e1000_verify_write_ich8_byte(hw, | |
2df7d59f | 5674 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); |
2a88c173 JK |
5675 | /* And invalidate the previously valid segment by setting |
5676 | * its signature word (0x13) high_byte to 0b. This can be | |
5677 | * done without an erase because flash erase sets all bits | |
5678 | * to 1's. We can write 1's to 0's without an erase */ | |
5679 | if (error == E1000_SUCCESS) { | |
cd94dd0b | 5680 | error = e1000_verify_write_ich8_byte(hw, |
2df7d59f | 5681 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); |
2a88c173 | 5682 | } |
cd94dd0b | 5683 | |
2a88c173 JK |
5684 | /* Clear the now not used entry in the cache */ |
5685 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
5686 | hw->eeprom_shadow_ram[i].modified = FALSE; | |
5687 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; | |
cd94dd0b | 5688 | } |
2a88c173 | 5689 | } |
cd94dd0b AK |
5690 | } |
5691 | ||
2d7edb92 MC |
5692 | return error; |
5693 | } | |
5694 | ||
1da177e4 LT |
5695 | /****************************************************************************** |
5696 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
5697 | * second function of dual function devices | |
5698 | * | |
5699 | * hw - Struct containing variables accessed by shared code | |
5700 | *****************************************************************************/ | |
5701 | int32_t | |
5702 | e1000_read_mac_addr(struct e1000_hw * hw) | |
5703 | { | |
5704 | uint16_t offset; | |
5705 | uint16_t eeprom_data, i; | |
5706 | ||
5707 | DEBUGFUNC("e1000_read_mac_addr"); | |
5708 | ||
8fc897b0 | 5709 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
1da177e4 | 5710 | offset = i >> 1; |
8fc897b0 | 5711 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
1da177e4 LT |
5712 | DEBUGOUT("EEPROM Read Error\n"); |
5713 | return -E1000_ERR_EEPROM; | |
5714 | } | |
5715 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); | |
5716 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); | |
5717 | } | |
96838a40 | 5718 | |
868d5309 MC |
5719 | switch (hw->mac_type) { |
5720 | default: | |
5721 | break; | |
5722 | case e1000_82546: | |
5723 | case e1000_82546_rev_3: | |
5724 | case e1000_82571: | |
6418ecc6 | 5725 | case e1000_80003es2lan: |
8fc897b0 | 5726 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
1da177e4 | 5727 | hw->perm_mac_addr[5] ^= 0x01; |
868d5309 MC |
5728 | break; |
5729 | } | |
1da177e4 | 5730 | |
8fc897b0 | 5731 | for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
1da177e4 LT |
5732 | hw->mac_addr[i] = hw->perm_mac_addr[i]; |
5733 | return E1000_SUCCESS; | |
5734 | } | |
5735 | ||
5736 | /****************************************************************************** | |
5737 | * Initializes receive address filters. | |
5738 | * | |
5739 | * hw - Struct containing variables accessed by shared code | |
5740 | * | |
5741 | * Places the MAC address in receive address register 0 and clears the rest | |
5742 | * of the receive addresss registers. Clears the multicast table. Assumes | |
5743 | * the receiver is in reset when the routine is called. | |
5744 | *****************************************************************************/ | |
3ad2cc67 | 5745 | static void |
1da177e4 LT |
5746 | e1000_init_rx_addrs(struct e1000_hw *hw) |
5747 | { | |
5748 | uint32_t i; | |
2d7edb92 | 5749 | uint32_t rar_num; |
1da177e4 LT |
5750 | |
5751 | DEBUGFUNC("e1000_init_rx_addrs"); | |
5752 | ||
5753 | /* Setup the receive address. */ | |
5754 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
5755 | ||
5756 | e1000_rar_set(hw, hw->mac_addr, 0); | |
5757 | ||
2d7edb92 | 5758 | rar_num = E1000_RAR_ENTRIES; |
868d5309 MC |
5759 | |
5760 | /* Reserve a spot for the Locally Administered Address to work around | |
5761 | * an 82571 issue in which a reset on one port will reload the MAC on | |
5762 | * the other port. */ | |
5763 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | |
5764 | rar_num -= 1; | |
cd94dd0b AK |
5765 | if (hw->mac_type == e1000_ich8lan) |
5766 | rar_num = E1000_RAR_ENTRIES_ICH8LAN; | |
5767 | ||
1da177e4 LT |
5768 | /* Zero out the other 15 receive addresses. */ |
5769 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
8fc897b0 | 5770 | for (i = 1; i < rar_num; i++) { |
1da177e4 | 5771 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
4ca213a6 | 5772 | E1000_WRITE_FLUSH(hw); |
1da177e4 | 5773 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
4ca213a6 | 5774 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5775 | } |
5776 | } | |
5777 | ||
1da177e4 LT |
5778 | /****************************************************************************** |
5779 | * Hashes an address to determine its location in the multicast table | |
5780 | * | |
5781 | * hw - Struct containing variables accessed by shared code | |
5782 | * mc_addr - the multicast address to hash | |
5783 | *****************************************************************************/ | |
5784 | uint32_t | |
5785 | e1000_hash_mc_addr(struct e1000_hw *hw, | |
5786 | uint8_t *mc_addr) | |
5787 | { | |
5788 | uint32_t hash_value = 0; | |
5789 | ||
5790 | /* The portion of the address that is used for the hash table is | |
5791 | * determined by the mc_filter_type setting. | |
5792 | */ | |
5793 | switch (hw->mc_filter_type) { | |
5794 | /* [0] [1] [2] [3] [4] [5] | |
5795 | * 01 AA 00 12 34 56 | |
5796 | * LSB MSB | |
5797 | */ | |
5798 | case 0: | |
cd94dd0b AK |
5799 | if (hw->mac_type == e1000_ich8lan) { |
5800 | /* [47:38] i.e. 0x158 for above example address */ | |
5801 | hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); | |
5802 | } else { | |
5803 | /* [47:36] i.e. 0x563 for above example address */ | |
5804 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); | |
5805 | } | |
1da177e4 LT |
5806 | break; |
5807 | case 1: | |
cd94dd0b AK |
5808 | if (hw->mac_type == e1000_ich8lan) { |
5809 | /* [46:37] i.e. 0x2B1 for above example address */ | |
5810 | hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); | |
5811 | } else { | |
5812 | /* [46:35] i.e. 0xAC6 for above example address */ | |
5813 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); | |
5814 | } | |
1da177e4 LT |
5815 | break; |
5816 | case 2: | |
cd94dd0b AK |
5817 | if (hw->mac_type == e1000_ich8lan) { |
5818 | /*[45:36] i.e. 0x163 for above example address */ | |
5819 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); | |
5820 | } else { | |
5821 | /* [45:34] i.e. 0x5D8 for above example address */ | |
5822 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); | |
5823 | } | |
1da177e4 LT |
5824 | break; |
5825 | case 3: | |
cd94dd0b AK |
5826 | if (hw->mac_type == e1000_ich8lan) { |
5827 | /* [43:34] i.e. 0x18D for above example address */ | |
5828 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); | |
5829 | } else { | |
5830 | /* [43:32] i.e. 0x634 for above example address */ | |
5831 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); | |
5832 | } | |
1da177e4 LT |
5833 | break; |
5834 | } | |
5835 | ||
5836 | hash_value &= 0xFFF; | |
cd94dd0b AK |
5837 | if (hw->mac_type == e1000_ich8lan) |
5838 | hash_value &= 0x3FF; | |
2d7edb92 | 5839 | |
1da177e4 LT |
5840 | return hash_value; |
5841 | } | |
5842 | ||
5843 | /****************************************************************************** | |
5844 | * Sets the bit in the multicast table corresponding to the hash value. | |
5845 | * | |
5846 | * hw - Struct containing variables accessed by shared code | |
5847 | * hash_value - Multicast address hash value | |
5848 | *****************************************************************************/ | |
5849 | void | |
5850 | e1000_mta_set(struct e1000_hw *hw, | |
5851 | uint32_t hash_value) | |
5852 | { | |
5853 | uint32_t hash_bit, hash_reg; | |
5854 | uint32_t mta; | |
5855 | uint32_t temp; | |
5856 | ||
5857 | /* The MTA is a register array of 128 32-bit registers. | |
5858 | * It is treated like an array of 4096 bits. We want to set | |
5859 | * bit BitArray[hash_value]. So we figure out what register | |
5860 | * the bit is in, read it, OR in the new bit, then write | |
5861 | * back the new value. The register is determined by the | |
5862 | * upper 7 bits of the hash value and the bit within that | |
5863 | * register are determined by the lower 5 bits of the value. | |
5864 | */ | |
5865 | hash_reg = (hash_value >> 5) & 0x7F; | |
cd94dd0b AK |
5866 | if (hw->mac_type == e1000_ich8lan) |
5867 | hash_reg &= 0x1F; | |
90fb5135 | 5868 | |
1da177e4 LT |
5869 | hash_bit = hash_value & 0x1F; |
5870 | ||
5871 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); | |
5872 | ||
5873 | mta |= (1 << hash_bit); | |
5874 | ||
5875 | /* If we are on an 82544 and we are trying to write an odd offset | |
5876 | * in the MTA, save off the previous entry before writing and | |
5877 | * restore the old value after writing. | |
5878 | */ | |
8fc897b0 | 5879 | if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { |
1da177e4 LT |
5880 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
5881 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
4ca213a6 | 5882 | E1000_WRITE_FLUSH(hw); |
1da177e4 | 5883 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
4ca213a6 | 5884 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5885 | } else { |
5886 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
4ca213a6 | 5887 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5888 | } |
5889 | } | |
5890 | ||
5891 | /****************************************************************************** | |
5892 | * Puts an ethernet address into a receive address register. | |
5893 | * | |
5894 | * hw - Struct containing variables accessed by shared code | |
5895 | * addr - Address to put into receive address register | |
5896 | * index - Receive address register to write | |
5897 | *****************************************************************************/ | |
5898 | void | |
5899 | e1000_rar_set(struct e1000_hw *hw, | |
5900 | uint8_t *addr, | |
5901 | uint32_t index) | |
5902 | { | |
5903 | uint32_t rar_low, rar_high; | |
5904 | ||
5905 | /* HW expects these in little endian so we reverse the byte order | |
5906 | * from network order (big endian) to little endian | |
5907 | */ | |
5908 | rar_low = ((uint32_t) addr[0] | | |
5909 | ((uint32_t) addr[1] << 8) | | |
5910 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); | |
8df06e50 | 5911 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); |
1da177e4 | 5912 | |
8df06e50 JK |
5913 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
5914 | * unit hang. | |
5915 | * | |
5916 | * Description: | |
5917 | * If there are any Rx frames queued up or otherwise present in the HW | |
5918 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will | |
5919 | * hang. To work around this issue, we have to disable receives and | |
5920 | * flush out all Rx frames before we enable RSS. To do so, we modify we | |
5921 | * redirect all Rx traffic to manageability and then reset the HW. | |
5922 | * This flushes away Rx frames, and (since the redirections to | |
5923 | * manageability persists across resets) keeps new ones from coming in | |
5924 | * while we work. Then, we clear the Address Valid AV bit for all MAC | |
5925 | * addresses and undo the re-direction to manageability. | |
5926 | * Now, frames are coming in again, but the MAC won't accept them, so | |
5927 | * far so good. We now proceed to initialize RSS (if necessary) and | |
5928 | * configure the Rx unit. Last, we re-enable the AV bits and continue | |
5929 | * on our merry way. | |
5930 | */ | |
5931 | switch (hw->mac_type) { | |
5932 | case e1000_82571: | |
5933 | case e1000_82572: | |
6418ecc6 | 5934 | case e1000_80003es2lan: |
8df06e50 JK |
5935 | if (hw->leave_av_bit_off == TRUE) |
5936 | break; | |
5937 | default: | |
5938 | /* Indicate to hardware the Address is Valid. */ | |
5939 | rar_high |= E1000_RAH_AV; | |
5940 | break; | |
5941 | } | |
1da177e4 LT |
5942 | |
5943 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); | |
4ca213a6 | 5944 | E1000_WRITE_FLUSH(hw); |
1da177e4 | 5945 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
4ca213a6 | 5946 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5947 | } |
5948 | ||
5949 | /****************************************************************************** | |
5950 | * Writes a value to the specified offset in the VLAN filter table. | |
5951 | * | |
5952 | * hw - Struct containing variables accessed by shared code | |
5953 | * offset - Offset in VLAN filer table to write | |
5954 | * value - Value to write into VLAN filter table | |
5955 | *****************************************************************************/ | |
5956 | void | |
5957 | e1000_write_vfta(struct e1000_hw *hw, | |
5958 | uint32_t offset, | |
5959 | uint32_t value) | |
5960 | { | |
5961 | uint32_t temp; | |
5962 | ||
cd94dd0b AK |
5963 | if (hw->mac_type == e1000_ich8lan) |
5964 | return; | |
5965 | ||
5966 | if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { | |
1da177e4 LT |
5967 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
5968 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
4ca213a6 | 5969 | E1000_WRITE_FLUSH(hw); |
1da177e4 | 5970 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
4ca213a6 | 5971 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5972 | } else { |
5973 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
4ca213a6 | 5974 | E1000_WRITE_FLUSH(hw); |
1da177e4 LT |
5975 | } |
5976 | } | |
5977 | ||
5978 | /****************************************************************************** | |
5979 | * Clears the VLAN filer table | |
5980 | * | |
5981 | * hw - Struct containing variables accessed by shared code | |
5982 | *****************************************************************************/ | |
3ad2cc67 | 5983 | static void |
1da177e4 LT |
5984 | e1000_clear_vfta(struct e1000_hw *hw) |
5985 | { | |
5986 | uint32_t offset; | |
2d7edb92 MC |
5987 | uint32_t vfta_value = 0; |
5988 | uint32_t vfta_offset = 0; | |
5989 | uint32_t vfta_bit_in_reg = 0; | |
5990 | ||
cd94dd0b AK |
5991 | if (hw->mac_type == e1000_ich8lan) |
5992 | return; | |
5993 | ||
2d7edb92 MC |
5994 | if (hw->mac_type == e1000_82573) { |
5995 | if (hw->mng_cookie.vlan_id != 0) { | |
5996 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | |
5997 | * ID. The following operations determine which 32b entry | |
5998 | * (i.e. offset) into the array we want to set the VLAN ID | |
5999 | * (i.e. bit) of the manageability unit. */ | |
6000 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
6001 | E1000_VFTA_ENTRY_SHIFT) & | |
6002 | E1000_VFTA_ENTRY_MASK; | |
6003 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
6004 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
6005 | } | |
6006 | } | |
6007 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
6008 | /* If the offset we want to clear is the same offset of the | |
6009 | * manageability VLAN ID, then clear all bits except that of the | |
6010 | * manageability unit */ | |
6011 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
6012 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | |
4ca213a6 | 6013 | E1000_WRITE_FLUSH(hw); |
2d7edb92 | 6014 | } |
1da177e4 LT |
6015 | } |
6016 | ||
3ad2cc67 | 6017 | static int32_t |
1da177e4 LT |
6018 | e1000_id_led_init(struct e1000_hw * hw) |
6019 | { | |
6020 | uint32_t ledctl; | |
6021 | const uint32_t ledctl_mask = 0x000000FF; | |
6022 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
6023 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
6024 | uint16_t eeprom_data, i, temp; | |
6025 | const uint16_t led_mask = 0x0F; | |
6026 | ||
6027 | DEBUGFUNC("e1000_id_led_init"); | |
6028 | ||
8fc897b0 | 6029 | if (hw->mac_type < e1000_82540) { |
1da177e4 LT |
6030 | /* Nothing to do */ |
6031 | return E1000_SUCCESS; | |
6032 | } | |
6033 | ||
6034 | ledctl = E1000_READ_REG(hw, LEDCTL); | |
6035 | hw->ledctl_default = ledctl; | |
6036 | hw->ledctl_mode1 = hw->ledctl_default; | |
6037 | hw->ledctl_mode2 = hw->ledctl_default; | |
6038 | ||
8fc897b0 | 6039 | if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
1da177e4 LT |
6040 | DEBUGOUT("EEPROM Read Error\n"); |
6041 | return -E1000_ERR_EEPROM; | |
6042 | } | |
cd94dd0b AK |
6043 | |
6044 | if ((hw->mac_type == e1000_82573) && | |
6045 | (eeprom_data == ID_LED_RESERVED_82573)) | |
6046 | eeprom_data = ID_LED_DEFAULT_82573; | |
6047 | else if ((eeprom_data == ID_LED_RESERVED_0000) || | |
6048 | (eeprom_data == ID_LED_RESERVED_FFFF)) { | |
6049 | if (hw->mac_type == e1000_ich8lan) | |
6050 | eeprom_data = ID_LED_DEFAULT_ICH8LAN; | |
6051 | else | |
6052 | eeprom_data = ID_LED_DEFAULT; | |
6053 | } | |
90fb5135 | 6054 | |
cd94dd0b | 6055 | for (i = 0; i < 4; i++) { |
1da177e4 | 6056 | temp = (eeprom_data >> (i << 2)) & led_mask; |
8fc897b0 | 6057 | switch (temp) { |
1da177e4 LT |
6058 | case ID_LED_ON1_DEF2: |
6059 | case ID_LED_ON1_ON2: | |
6060 | case ID_LED_ON1_OFF2: | |
6061 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
6062 | hw->ledctl_mode1 |= ledctl_on << (i << 3); | |
6063 | break; | |
6064 | case ID_LED_OFF1_DEF2: | |
6065 | case ID_LED_OFF1_ON2: | |
6066 | case ID_LED_OFF1_OFF2: | |
6067 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
6068 | hw->ledctl_mode1 |= ledctl_off << (i << 3); | |
6069 | break; | |
6070 | default: | |
6071 | /* Do nothing */ | |
6072 | break; | |
6073 | } | |
8fc897b0 | 6074 | switch (temp) { |
1da177e4 LT |
6075 | case ID_LED_DEF1_ON2: |
6076 | case ID_LED_ON1_ON2: | |
6077 | case ID_LED_OFF1_ON2: | |
6078 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
6079 | hw->ledctl_mode2 |= ledctl_on << (i << 3); | |
6080 | break; | |
6081 | case ID_LED_DEF1_OFF2: | |
6082 | case ID_LED_ON1_OFF2: | |
6083 | case ID_LED_OFF1_OFF2: | |
6084 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
6085 | hw->ledctl_mode2 |= ledctl_off << (i << 3); | |
6086 | break; | |
6087 | default: | |
6088 | /* Do nothing */ | |
6089 | break; | |
6090 | } | |
6091 | } | |
6092 | return E1000_SUCCESS; | |
6093 | } | |
6094 | ||
6095 | /****************************************************************************** | |
6096 | * Prepares SW controlable LED for use and saves the current state of the LED. | |
6097 | * | |
6098 | * hw - Struct containing variables accessed by shared code | |
6099 | *****************************************************************************/ | |
6100 | int32_t | |
6101 | e1000_setup_led(struct e1000_hw *hw) | |
6102 | { | |
6103 | uint32_t ledctl; | |
6104 | int32_t ret_val = E1000_SUCCESS; | |
6105 | ||
6106 | DEBUGFUNC("e1000_setup_led"); | |
6107 | ||
8fc897b0 | 6108 | switch (hw->mac_type) { |
1da177e4 LT |
6109 | case e1000_82542_rev2_0: |
6110 | case e1000_82542_rev2_1: | |
6111 | case e1000_82543: | |
6112 | case e1000_82544: | |
6113 | /* No setup necessary */ | |
6114 | break; | |
6115 | case e1000_82541: | |
6116 | case e1000_82547: | |
6117 | case e1000_82541_rev_2: | |
6118 | case e1000_82547_rev_2: | |
6119 | /* Turn off PHY Smart Power Down (if enabled) */ | |
6120 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
6121 | &hw->phy_spd_default); | |
8fc897b0 | 6122 | if (ret_val) |
1da177e4 LT |
6123 | return ret_val; |
6124 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
6125 | (uint16_t)(hw->phy_spd_default & | |
6126 | ~IGP01E1000_GMII_SPD)); | |
8fc897b0 | 6127 | if (ret_val) |
1da177e4 LT |
6128 | return ret_val; |
6129 | /* Fall Through */ | |
6130 | default: | |
8fc897b0 | 6131 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6132 | ledctl = E1000_READ_REG(hw, LEDCTL); |
6133 | /* Save current LEDCTL settings */ | |
6134 | hw->ledctl_default = ledctl; | |
6135 | /* Turn off LED0 */ | |
6136 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | | |
6137 | E1000_LEDCTL_LED0_BLINK | | |
6138 | E1000_LEDCTL_LED0_MODE_MASK); | |
6139 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
6140 | E1000_LEDCTL_LED0_MODE_SHIFT); | |
6141 | E1000_WRITE_REG(hw, LEDCTL, ledctl); | |
8fc897b0 | 6142 | } else if (hw->media_type == e1000_media_type_copper) |
1da177e4 LT |
6143 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
6144 | break; | |
6145 | } | |
6146 | ||
6147 | return E1000_SUCCESS; | |
6148 | } | |
6149 | ||
8fc897b0 | 6150 | |
f1b3a853 AK |
6151 | /****************************************************************************** |
6152 | * Used on 82571 and later Si that has LED blink bits. | |
6153 | * Callers must use their own timer and should have already called | |
6154 | * e1000_id_led_init() | |
6155 | * Call e1000_cleanup led() to stop blinking | |
6156 | * | |
6157 | * hw - Struct containing variables accessed by shared code | |
6158 | *****************************************************************************/ | |
6159 | int32_t | |
6160 | e1000_blink_led_start(struct e1000_hw *hw) | |
6161 | { | |
6162 | int16_t i; | |
6163 | uint32_t ledctl_blink = 0; | |
6164 | ||
6165 | DEBUGFUNC("e1000_id_led_blink_on"); | |
6166 | ||
6167 | if (hw->mac_type < e1000_82571) { | |
6168 | /* Nothing to do */ | |
6169 | return E1000_SUCCESS; | |
6170 | } | |
6171 | if (hw->media_type == e1000_media_type_fiber) { | |
6172 | /* always blink LED0 for PCI-E fiber */ | |
6173 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | | |
6174 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); | |
6175 | } else { | |
6176 | /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ | |
6177 | ledctl_blink = hw->ledctl_mode2; | |
6178 | for (i=0; i < 4; i++) | |
6179 | if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == | |
6180 | E1000_LEDCTL_MODE_LED_ON) | |
6181 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); | |
6182 | } | |
6183 | ||
6184 | E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); | |
6185 | ||
6186 | return E1000_SUCCESS; | |
6187 | } | |
6188 | ||
1da177e4 LT |
6189 | /****************************************************************************** |
6190 | * Restores the saved state of the SW controlable LED. | |
6191 | * | |
6192 | * hw - Struct containing variables accessed by shared code | |
6193 | *****************************************************************************/ | |
6194 | int32_t | |
6195 | e1000_cleanup_led(struct e1000_hw *hw) | |
6196 | { | |
6197 | int32_t ret_val = E1000_SUCCESS; | |
6198 | ||
6199 | DEBUGFUNC("e1000_cleanup_led"); | |
6200 | ||
8fc897b0 | 6201 | switch (hw->mac_type) { |
1da177e4 LT |
6202 | case e1000_82542_rev2_0: |
6203 | case e1000_82542_rev2_1: | |
6204 | case e1000_82543: | |
6205 | case e1000_82544: | |
6206 | /* No cleanup necessary */ | |
6207 | break; | |
6208 | case e1000_82541: | |
6209 | case e1000_82547: | |
6210 | case e1000_82541_rev_2: | |
6211 | case e1000_82547_rev_2: | |
6212 | /* Turn on PHY Smart Power Down (if previously enabled) */ | |
6213 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
6214 | hw->phy_spd_default); | |
8fc897b0 | 6215 | if (ret_val) |
1da177e4 LT |
6216 | return ret_val; |
6217 | /* Fall Through */ | |
6218 | default: | |
cd94dd0b AK |
6219 | if (hw->phy_type == e1000_phy_ife) { |
6220 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
6221 | break; | |
6222 | } | |
1da177e4 LT |
6223 | /* Restore LEDCTL settings */ |
6224 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); | |
6225 | break; | |
6226 | } | |
6227 | ||
6228 | return E1000_SUCCESS; | |
6229 | } | |
6230 | ||
6231 | /****************************************************************************** | |
6232 | * Turns on the software controllable LED | |
6233 | * | |
6234 | * hw - Struct containing variables accessed by shared code | |
6235 | *****************************************************************************/ | |
6236 | int32_t | |
6237 | e1000_led_on(struct e1000_hw *hw) | |
6238 | { | |
6239 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
6240 | ||
6241 | DEBUGFUNC("e1000_led_on"); | |
6242 | ||
8fc897b0 | 6243 | switch (hw->mac_type) { |
1da177e4 LT |
6244 | case e1000_82542_rev2_0: |
6245 | case e1000_82542_rev2_1: | |
6246 | case e1000_82543: | |
6247 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
6248 | ctrl |= E1000_CTRL_SWDPIN0; | |
6249 | ctrl |= E1000_CTRL_SWDPIO0; | |
6250 | break; | |
6251 | case e1000_82544: | |
8fc897b0 | 6252 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6253 | /* Set SW Defineable Pin 0 to turn on the LED */ |
6254 | ctrl |= E1000_CTRL_SWDPIN0; | |
6255 | ctrl |= E1000_CTRL_SWDPIO0; | |
6256 | } else { | |
6257 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
6258 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6259 | ctrl |= E1000_CTRL_SWDPIO0; | |
6260 | } | |
6261 | break; | |
6262 | default: | |
8fc897b0 | 6263 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6264 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
6265 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6266 | ctrl |= E1000_CTRL_SWDPIO0; | |
cd94dd0b AK |
6267 | } else if (hw->phy_type == e1000_phy_ife) { |
6268 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
6269 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
6270 | } else if (hw->media_type == e1000_media_type_copper) { | |
1da177e4 LT |
6271 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
6272 | return E1000_SUCCESS; | |
6273 | } | |
6274 | break; | |
6275 | } | |
6276 | ||
6277 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
6278 | ||
6279 | return E1000_SUCCESS; | |
6280 | } | |
6281 | ||
6282 | /****************************************************************************** | |
6283 | * Turns off the software controllable LED | |
6284 | * | |
6285 | * hw - Struct containing variables accessed by shared code | |
6286 | *****************************************************************************/ | |
6287 | int32_t | |
6288 | e1000_led_off(struct e1000_hw *hw) | |
6289 | { | |
6290 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
6291 | ||
6292 | DEBUGFUNC("e1000_led_off"); | |
6293 | ||
8fc897b0 | 6294 | switch (hw->mac_type) { |
1da177e4 LT |
6295 | case e1000_82542_rev2_0: |
6296 | case e1000_82542_rev2_1: | |
6297 | case e1000_82543: | |
6298 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
6299 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6300 | ctrl |= E1000_CTRL_SWDPIO0; | |
6301 | break; | |
6302 | case e1000_82544: | |
8fc897b0 | 6303 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6304 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
6305 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6306 | ctrl |= E1000_CTRL_SWDPIO0; | |
6307 | } else { | |
6308 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
6309 | ctrl |= E1000_CTRL_SWDPIN0; | |
6310 | ctrl |= E1000_CTRL_SWDPIO0; | |
6311 | } | |
6312 | break; | |
6313 | default: | |
8fc897b0 | 6314 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6315 | /* Set SW Defineable Pin 0 to turn off the LED */ |
6316 | ctrl |= E1000_CTRL_SWDPIN0; | |
6317 | ctrl |= E1000_CTRL_SWDPIO0; | |
cd94dd0b AK |
6318 | } else if (hw->phy_type == e1000_phy_ife) { |
6319 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
6320 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
6321 | } else if (hw->media_type == e1000_media_type_copper) { | |
1da177e4 LT |
6322 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
6323 | return E1000_SUCCESS; | |
6324 | } | |
6325 | break; | |
6326 | } | |
6327 | ||
6328 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
6329 | ||
6330 | return E1000_SUCCESS; | |
6331 | } | |
6332 | ||
6333 | /****************************************************************************** | |
6334 | * Clears all hardware statistics counters. | |
6335 | * | |
6336 | * hw - Struct containing variables accessed by shared code | |
6337 | *****************************************************************************/ | |
35574764 | 6338 | static void |
1da177e4 LT |
6339 | e1000_clear_hw_cntrs(struct e1000_hw *hw) |
6340 | { | |
6341 | volatile uint32_t temp; | |
6342 | ||
6343 | temp = E1000_READ_REG(hw, CRCERRS); | |
6344 | temp = E1000_READ_REG(hw, SYMERRS); | |
6345 | temp = E1000_READ_REG(hw, MPC); | |
6346 | temp = E1000_READ_REG(hw, SCC); | |
6347 | temp = E1000_READ_REG(hw, ECOL); | |
6348 | temp = E1000_READ_REG(hw, MCC); | |
6349 | temp = E1000_READ_REG(hw, LATECOL); | |
6350 | temp = E1000_READ_REG(hw, COLC); | |
6351 | temp = E1000_READ_REG(hw, DC); | |
6352 | temp = E1000_READ_REG(hw, SEC); | |
6353 | temp = E1000_READ_REG(hw, RLEC); | |
6354 | temp = E1000_READ_REG(hw, XONRXC); | |
6355 | temp = E1000_READ_REG(hw, XONTXC); | |
6356 | temp = E1000_READ_REG(hw, XOFFRXC); | |
6357 | temp = E1000_READ_REG(hw, XOFFTXC); | |
6358 | temp = E1000_READ_REG(hw, FCRUC); | |
cd94dd0b AK |
6359 | |
6360 | if (hw->mac_type != e1000_ich8lan) { | |
1da177e4 LT |
6361 | temp = E1000_READ_REG(hw, PRC64); |
6362 | temp = E1000_READ_REG(hw, PRC127); | |
6363 | temp = E1000_READ_REG(hw, PRC255); | |
6364 | temp = E1000_READ_REG(hw, PRC511); | |
6365 | temp = E1000_READ_REG(hw, PRC1023); | |
6366 | temp = E1000_READ_REG(hw, PRC1522); | |
cd94dd0b AK |
6367 | } |
6368 | ||
1da177e4 LT |
6369 | temp = E1000_READ_REG(hw, GPRC); |
6370 | temp = E1000_READ_REG(hw, BPRC); | |
6371 | temp = E1000_READ_REG(hw, MPRC); | |
6372 | temp = E1000_READ_REG(hw, GPTC); | |
6373 | temp = E1000_READ_REG(hw, GORCL); | |
6374 | temp = E1000_READ_REG(hw, GORCH); | |
6375 | temp = E1000_READ_REG(hw, GOTCL); | |
6376 | temp = E1000_READ_REG(hw, GOTCH); | |
6377 | temp = E1000_READ_REG(hw, RNBC); | |
6378 | temp = E1000_READ_REG(hw, RUC); | |
6379 | temp = E1000_READ_REG(hw, RFC); | |
6380 | temp = E1000_READ_REG(hw, ROC); | |
6381 | temp = E1000_READ_REG(hw, RJC); | |
6382 | temp = E1000_READ_REG(hw, TORL); | |
6383 | temp = E1000_READ_REG(hw, TORH); | |
6384 | temp = E1000_READ_REG(hw, TOTL); | |
6385 | temp = E1000_READ_REG(hw, TOTH); | |
6386 | temp = E1000_READ_REG(hw, TPR); | |
6387 | temp = E1000_READ_REG(hw, TPT); | |
cd94dd0b AK |
6388 | |
6389 | if (hw->mac_type != e1000_ich8lan) { | |
1da177e4 LT |
6390 | temp = E1000_READ_REG(hw, PTC64); |
6391 | temp = E1000_READ_REG(hw, PTC127); | |
6392 | temp = E1000_READ_REG(hw, PTC255); | |
6393 | temp = E1000_READ_REG(hw, PTC511); | |
6394 | temp = E1000_READ_REG(hw, PTC1023); | |
6395 | temp = E1000_READ_REG(hw, PTC1522); | |
cd94dd0b AK |
6396 | } |
6397 | ||
1da177e4 LT |
6398 | temp = E1000_READ_REG(hw, MPTC); |
6399 | temp = E1000_READ_REG(hw, BPTC); | |
6400 | ||
8fc897b0 | 6401 | if (hw->mac_type < e1000_82543) return; |
1da177e4 LT |
6402 | |
6403 | temp = E1000_READ_REG(hw, ALGNERRC); | |
6404 | temp = E1000_READ_REG(hw, RXERRC); | |
6405 | temp = E1000_READ_REG(hw, TNCRS); | |
6406 | temp = E1000_READ_REG(hw, CEXTERR); | |
6407 | temp = E1000_READ_REG(hw, TSCTC); | |
6408 | temp = E1000_READ_REG(hw, TSCTFC); | |
6409 | ||
8fc897b0 | 6410 | if (hw->mac_type <= e1000_82544) return; |
1da177e4 LT |
6411 | |
6412 | temp = E1000_READ_REG(hw, MGTPRC); | |
6413 | temp = E1000_READ_REG(hw, MGTPDC); | |
6414 | temp = E1000_READ_REG(hw, MGTPTC); | |
2d7edb92 | 6415 | |
8fc897b0 | 6416 | if (hw->mac_type <= e1000_82547_rev_2) return; |
2d7edb92 MC |
6417 | |
6418 | temp = E1000_READ_REG(hw, IAC); | |
6419 | temp = E1000_READ_REG(hw, ICRXOC); | |
cd94dd0b AK |
6420 | |
6421 | if (hw->mac_type == e1000_ich8lan) return; | |
6422 | ||
2d7edb92 MC |
6423 | temp = E1000_READ_REG(hw, ICRXPTC); |
6424 | temp = E1000_READ_REG(hw, ICRXATC); | |
6425 | temp = E1000_READ_REG(hw, ICTXPTC); | |
6426 | temp = E1000_READ_REG(hw, ICTXATC); | |
6427 | temp = E1000_READ_REG(hw, ICTXQEC); | |
6428 | temp = E1000_READ_REG(hw, ICTXQMTC); | |
6429 | temp = E1000_READ_REG(hw, ICRXDMTC); | |
1da177e4 LT |
6430 | } |
6431 | ||
6432 | /****************************************************************************** | |
6433 | * Resets Adaptive IFS to its default state. | |
6434 | * | |
6435 | * hw - Struct containing variables accessed by shared code | |
6436 | * | |
6437 | * Call this after e1000_init_hw. You may override the IFS defaults by setting | |
6438 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> | |
6439 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio | |
6440 | * before calling this function. | |
6441 | *****************************************************************************/ | |
6442 | void | |
6443 | e1000_reset_adaptive(struct e1000_hw *hw) | |
6444 | { | |
6445 | DEBUGFUNC("e1000_reset_adaptive"); | |
6446 | ||
8fc897b0 AK |
6447 | if (hw->adaptive_ifs) { |
6448 | if (!hw->ifs_params_forced) { | |
1da177e4 LT |
6449 | hw->current_ifs_val = 0; |
6450 | hw->ifs_min_val = IFS_MIN; | |
6451 | hw->ifs_max_val = IFS_MAX; | |
6452 | hw->ifs_step_size = IFS_STEP; | |
6453 | hw->ifs_ratio = IFS_RATIO; | |
6454 | } | |
6455 | hw->in_ifs_mode = FALSE; | |
6456 | E1000_WRITE_REG(hw, AIT, 0); | |
6457 | } else { | |
6458 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
6459 | } | |
6460 | } | |
6461 | ||
6462 | /****************************************************************************** | |
6463 | * Called during the callback/watchdog routine to update IFS value based on | |
6464 | * the ratio of transmits to collisions. | |
6465 | * | |
6466 | * hw - Struct containing variables accessed by shared code | |
6467 | * tx_packets - Number of transmits since last callback | |
6468 | * total_collisions - Number of collisions since last callback | |
6469 | *****************************************************************************/ | |
6470 | void | |
6471 | e1000_update_adaptive(struct e1000_hw *hw) | |
6472 | { | |
6473 | DEBUGFUNC("e1000_update_adaptive"); | |
6474 | ||
8fc897b0 AK |
6475 | if (hw->adaptive_ifs) { |
6476 | if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { | |
6477 | if (hw->tx_packet_delta > MIN_NUM_XMITS) { | |
1da177e4 | 6478 | hw->in_ifs_mode = TRUE; |
8fc897b0 AK |
6479 | if (hw->current_ifs_val < hw->ifs_max_val) { |
6480 | if (hw->current_ifs_val == 0) | |
1da177e4 LT |
6481 | hw->current_ifs_val = hw->ifs_min_val; |
6482 | else | |
6483 | hw->current_ifs_val += hw->ifs_step_size; | |
6484 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); | |
6485 | } | |
6486 | } | |
6487 | } else { | |
8fc897b0 | 6488 | if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
1da177e4 LT |
6489 | hw->current_ifs_val = 0; |
6490 | hw->in_ifs_mode = FALSE; | |
6491 | E1000_WRITE_REG(hw, AIT, 0); | |
6492 | } | |
6493 | } | |
6494 | } else { | |
6495 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
6496 | } | |
6497 | } | |
6498 | ||
6499 | /****************************************************************************** | |
6500 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT | |
6501 | * | |
6502 | * hw - Struct containing variables accessed by shared code | |
6503 | * frame_len - The length of the frame in question | |
6504 | * mac_addr - The Ethernet destination address of the frame in question | |
6505 | *****************************************************************************/ | |
6506 | void | |
6507 | e1000_tbi_adjust_stats(struct e1000_hw *hw, | |
6508 | struct e1000_hw_stats *stats, | |
6509 | uint32_t frame_len, | |
6510 | uint8_t *mac_addr) | |
6511 | { | |
6512 | uint64_t carry_bit; | |
6513 | ||
6514 | /* First adjust the frame length. */ | |
6515 | frame_len--; | |
6516 | /* We need to adjust the statistics counters, since the hardware | |
6517 | * counters overcount this packet as a CRC error and undercount | |
6518 | * the packet as a good packet | |
6519 | */ | |
6520 | /* This packet should not be counted as a CRC error. */ | |
6521 | stats->crcerrs--; | |
6522 | /* This packet does count as a Good Packet Received. */ | |
6523 | stats->gprc++; | |
6524 | ||
6525 | /* Adjust the Good Octets received counters */ | |
6526 | carry_bit = 0x80000000 & stats->gorcl; | |
6527 | stats->gorcl += frame_len; | |
6528 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets | |
6529 | * Received Count) was one before the addition, | |
6530 | * AND it is zero after, then we lost the carry out, | |
6531 | * need to add one to Gorch (Good Octets Received Count High). | |
6532 | * This could be simplified if all environments supported | |
6533 | * 64-bit integers. | |
6534 | */ | |
8fc897b0 | 6535 | if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
1da177e4 LT |
6536 | stats->gorch++; |
6537 | /* Is this a broadcast or multicast? Check broadcast first, | |
6538 | * since the test for a multicast frame will test positive on | |
6539 | * a broadcast frame. | |
6540 | */ | |
8fc897b0 | 6541 | if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
1da177e4 LT |
6542 | /* Broadcast packet */ |
6543 | stats->bprc++; | |
8fc897b0 | 6544 | else if (*mac_addr & 0x01) |
1da177e4 LT |
6545 | /* Multicast packet */ |
6546 | stats->mprc++; | |
6547 | ||
8fc897b0 | 6548 | if (frame_len == hw->max_frame_size) { |
1da177e4 LT |
6549 | /* In this case, the hardware has overcounted the number of |
6550 | * oversize frames. | |
6551 | */ | |
8fc897b0 | 6552 | if (stats->roc > 0) |
1da177e4 LT |
6553 | stats->roc--; |
6554 | } | |
6555 | ||
6556 | /* Adjust the bin counters when the extra byte put the frame in the | |
6557 | * wrong bin. Remember that the frame_len was adjusted above. | |
6558 | */ | |
8fc897b0 | 6559 | if (frame_len == 64) { |
1da177e4 LT |
6560 | stats->prc64++; |
6561 | stats->prc127--; | |
8fc897b0 | 6562 | } else if (frame_len == 127) { |
1da177e4 LT |
6563 | stats->prc127++; |
6564 | stats->prc255--; | |
8fc897b0 | 6565 | } else if (frame_len == 255) { |
1da177e4 LT |
6566 | stats->prc255++; |
6567 | stats->prc511--; | |
8fc897b0 | 6568 | } else if (frame_len == 511) { |
1da177e4 LT |
6569 | stats->prc511++; |
6570 | stats->prc1023--; | |
8fc897b0 | 6571 | } else if (frame_len == 1023) { |
1da177e4 LT |
6572 | stats->prc1023++; |
6573 | stats->prc1522--; | |
8fc897b0 | 6574 | } else if (frame_len == 1522) { |
1da177e4 LT |
6575 | stats->prc1522++; |
6576 | } | |
6577 | } | |
6578 | ||
6579 | /****************************************************************************** | |
6580 | * Gets the current PCI bus type, speed, and width of the hardware | |
6581 | * | |
6582 | * hw - Struct containing variables accessed by shared code | |
6583 | *****************************************************************************/ | |
6584 | void | |
6585 | e1000_get_bus_info(struct e1000_hw *hw) | |
6586 | { | |
caeccb68 JK |
6587 | int32_t ret_val; |
6588 | uint16_t pci_ex_link_status; | |
1da177e4 LT |
6589 | uint32_t status; |
6590 | ||
6591 | switch (hw->mac_type) { | |
6592 | case e1000_82542_rev2_0: | |
6593 | case e1000_82542_rev2_1: | |
c3813ae6 | 6594 | hw->bus_type = e1000_bus_type_pci; |
1da177e4 LT |
6595 | hw->bus_speed = e1000_bus_speed_unknown; |
6596 | hw->bus_width = e1000_bus_width_unknown; | |
6597 | break; | |
caeccb68 | 6598 | case e1000_82571: |
868d5309 | 6599 | case e1000_82572: |
2d7edb92 | 6600 | case e1000_82573: |
caeccb68 | 6601 | case e1000_80003es2lan: |
fd803241 JK |
6602 | hw->bus_type = e1000_bus_type_pci_express; |
6603 | hw->bus_speed = e1000_bus_speed_2500; | |
caeccb68 JK |
6604 | ret_val = e1000_read_pcie_cap_reg(hw, |
6605 | PCI_EX_LINK_STATUS, | |
6606 | &pci_ex_link_status); | |
6607 | if (ret_val) | |
6608 | hw->bus_width = e1000_bus_width_unknown; | |
6609 | else | |
6610 | hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> | |
6611 | PCI_EX_LINK_WIDTH_SHIFT; | |
fd803241 | 6612 | break; |
cd94dd0b | 6613 | case e1000_ich8lan: |
2d7edb92 MC |
6614 | hw->bus_type = e1000_bus_type_pci_express; |
6615 | hw->bus_speed = e1000_bus_speed_2500; | |
caeccb68 | 6616 | hw->bus_width = e1000_bus_width_pciex_1; |
2d7edb92 | 6617 | break; |
1da177e4 LT |
6618 | default: |
6619 | status = E1000_READ_REG(hw, STATUS); | |
6620 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | |
6621 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
6622 | ||
8fc897b0 | 6623 | if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
1da177e4 LT |
6624 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
6625 | e1000_bus_speed_66 : e1000_bus_speed_120; | |
8fc897b0 | 6626 | } else if (hw->bus_type == e1000_bus_type_pci) { |
1da177e4 LT |
6627 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
6628 | e1000_bus_speed_66 : e1000_bus_speed_33; | |
6629 | } else { | |
6630 | switch (status & E1000_STATUS_PCIX_SPEED) { | |
6631 | case E1000_STATUS_PCIX_SPEED_66: | |
6632 | hw->bus_speed = e1000_bus_speed_66; | |
6633 | break; | |
6634 | case E1000_STATUS_PCIX_SPEED_100: | |
6635 | hw->bus_speed = e1000_bus_speed_100; | |
6636 | break; | |
6637 | case E1000_STATUS_PCIX_SPEED_133: | |
6638 | hw->bus_speed = e1000_bus_speed_133; | |
6639 | break; | |
6640 | default: | |
6641 | hw->bus_speed = e1000_bus_speed_reserved; | |
6642 | break; | |
6643 | } | |
6644 | } | |
6645 | hw->bus_width = (status & E1000_STATUS_BUS64) ? | |
6646 | e1000_bus_width_64 : e1000_bus_width_32; | |
6647 | break; | |
6648 | } | |
6649 | } | |
1da177e4 LT |
6650 | |
6651 | /****************************************************************************** | |
6652 | * Writes a value to one of the devices registers using port I/O (as opposed to | |
6653 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
6654 | * | |
6655 | * hw - Struct containing variables accessed by shared code | |
6656 | * offset - offset to write to | |
6657 | * value - value to write | |
6658 | *****************************************************************************/ | |
3ad2cc67 | 6659 | static void |
1da177e4 LT |
6660 | e1000_write_reg_io(struct e1000_hw *hw, |
6661 | uint32_t offset, | |
6662 | uint32_t value) | |
6663 | { | |
6664 | unsigned long io_addr = hw->io_base; | |
6665 | unsigned long io_data = hw->io_base + 4; | |
6666 | ||
6667 | e1000_io_write(hw, io_addr, offset); | |
6668 | e1000_io_write(hw, io_data, value); | |
6669 | } | |
6670 | ||
1da177e4 LT |
6671 | /****************************************************************************** |
6672 | * Estimates the cable length. | |
6673 | * | |
6674 | * hw - Struct containing variables accessed by shared code | |
6675 | * min_length - The estimated minimum length | |
6676 | * max_length - The estimated maximum length | |
6677 | * | |
6678 | * returns: - E1000_ERR_XXX | |
6679 | * E1000_SUCCESS | |
6680 | * | |
6681 | * This function always returns a ranged length (minimum & maximum). | |
6682 | * So for M88 phy's, this function interprets the one value returned from the | |
6683 | * register to the minimum and maximum range. | |
6684 | * For IGP phy's, the function calculates the range by the AGC registers. | |
6685 | *****************************************************************************/ | |
3ad2cc67 | 6686 | static int32_t |
1da177e4 LT |
6687 | e1000_get_cable_length(struct e1000_hw *hw, |
6688 | uint16_t *min_length, | |
6689 | uint16_t *max_length) | |
6690 | { | |
6691 | int32_t ret_val; | |
6692 | uint16_t agc_value = 0; | |
1da177e4 LT |
6693 | uint16_t i, phy_data; |
6694 | uint16_t cable_length; | |
6695 | ||
6696 | DEBUGFUNC("e1000_get_cable_length"); | |
6697 | ||
6698 | *min_length = *max_length = 0; | |
6699 | ||
6700 | /* Use old method for Phy older than IGP */ | |
8fc897b0 | 6701 | if (hw->phy_type == e1000_phy_m88) { |
2d7edb92 | 6702 | |
1da177e4 LT |
6703 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6704 | &phy_data); | |
8fc897b0 | 6705 | if (ret_val) |
1da177e4 LT |
6706 | return ret_val; |
6707 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
6708 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
6709 | ||
6710 | /* Convert the enum value to ranged values */ | |
6711 | switch (cable_length) { | |
6712 | case e1000_cable_length_50: | |
6713 | *min_length = 0; | |
6714 | *max_length = e1000_igp_cable_length_50; | |
6715 | break; | |
6716 | case e1000_cable_length_50_80: | |
6717 | *min_length = e1000_igp_cable_length_50; | |
6718 | *max_length = e1000_igp_cable_length_80; | |
6719 | break; | |
6720 | case e1000_cable_length_80_110: | |
6721 | *min_length = e1000_igp_cable_length_80; | |
6722 | *max_length = e1000_igp_cable_length_110; | |
6723 | break; | |
6724 | case e1000_cable_length_110_140: | |
6725 | *min_length = e1000_igp_cable_length_110; | |
6726 | *max_length = e1000_igp_cable_length_140; | |
6727 | break; | |
6728 | case e1000_cable_length_140: | |
6729 | *min_length = e1000_igp_cable_length_140; | |
6730 | *max_length = e1000_igp_cable_length_170; | |
6731 | break; | |
6732 | default: | |
6733 | return -E1000_ERR_PHY; | |
6734 | break; | |
6735 | } | |
6418ecc6 JK |
6736 | } else if (hw->phy_type == e1000_phy_gg82563) { |
6737 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
6738 | &phy_data); | |
6739 | if (ret_val) | |
6740 | return ret_val; | |
6741 | cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
6742 | ||
6743 | switch (cable_length) { | |
6744 | case e1000_gg_cable_length_60: | |
6745 | *min_length = 0; | |
6746 | *max_length = e1000_igp_cable_length_60; | |
6747 | break; | |
6748 | case e1000_gg_cable_length_60_115: | |
6749 | *min_length = e1000_igp_cable_length_60; | |
6750 | *max_length = e1000_igp_cable_length_115; | |
6751 | break; | |
6752 | case e1000_gg_cable_length_115_150: | |
6753 | *min_length = e1000_igp_cable_length_115; | |
6754 | *max_length = e1000_igp_cable_length_150; | |
6755 | break; | |
6756 | case e1000_gg_cable_length_150: | |
6757 | *min_length = e1000_igp_cable_length_150; | |
6758 | *max_length = e1000_igp_cable_length_180; | |
6759 | break; | |
6760 | default: | |
6761 | return -E1000_ERR_PHY; | |
6762 | break; | |
6763 | } | |
8fc897b0 | 6764 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
cd94dd0b AK |
6765 | uint16_t cur_agc_value; |
6766 | uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | |
1da177e4 LT |
6767 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
6768 | {IGP01E1000_PHY_AGC_A, | |
6769 | IGP01E1000_PHY_AGC_B, | |
6770 | IGP01E1000_PHY_AGC_C, | |
6771 | IGP01E1000_PHY_AGC_D}; | |
6772 | /* Read the AGC registers for all channels */ | |
8fc897b0 | 6773 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 LT |
6774 | |
6775 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
8fc897b0 | 6776 | if (ret_val) |
1da177e4 LT |
6777 | return ret_val; |
6778 | ||
cd94dd0b | 6779 | cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
1da177e4 | 6780 | |
cd94dd0b AK |
6781 | /* Value bound check. */ |
6782 | if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || | |
6783 | (cur_agc_value == 0)) | |
1da177e4 LT |
6784 | return -E1000_ERR_PHY; |
6785 | ||
cd94dd0b | 6786 | agc_value += cur_agc_value; |
1da177e4 LT |
6787 | |
6788 | /* Update minimal AGC value. */ | |
cd94dd0b AK |
6789 | if (min_agc_value > cur_agc_value) |
6790 | min_agc_value = cur_agc_value; | |
1da177e4 LT |
6791 | } |
6792 | ||
6793 | /* Remove the minimal AGC result for length < 50m */ | |
cd94dd0b AK |
6794 | if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
6795 | agc_value -= min_agc_value; | |
1da177e4 LT |
6796 | |
6797 | /* Get the average length of the remaining 3 channels */ | |
6798 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | |
6799 | } else { | |
6800 | /* Get the average length of all the 4 channels. */ | |
6801 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; | |
6802 | } | |
6803 | ||
6804 | /* Set the range of the calculated length. */ | |
6805 | *min_length = ((e1000_igp_cable_length_table[agc_value] - | |
6806 | IGP01E1000_AGC_RANGE) > 0) ? | |
6807 | (e1000_igp_cable_length_table[agc_value] - | |
6808 | IGP01E1000_AGC_RANGE) : 0; | |
6809 | *max_length = e1000_igp_cable_length_table[agc_value] + | |
6810 | IGP01E1000_AGC_RANGE; | |
cd94dd0b AK |
6811 | } else if (hw->phy_type == e1000_phy_igp_2 || |
6812 | hw->phy_type == e1000_phy_igp_3) { | |
6813 | uint16_t cur_agc_index, max_agc_index = 0; | |
6814 | uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; | |
868d5309 MC |
6815 | uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
6816 | {IGP02E1000_PHY_AGC_A, | |
6817 | IGP02E1000_PHY_AGC_B, | |
6818 | IGP02E1000_PHY_AGC_C, | |
6819 | IGP02E1000_PHY_AGC_D}; | |
6820 | /* Read the AGC registers for all channels */ | |
6821 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
6822 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
6823 | if (ret_val) | |
6824 | return ret_val; | |
6825 | ||
8fc897b0 | 6826 | /* Getting bits 15:9, which represent the combination of course and |
868d5309 MC |
6827 | * fine gain values. The result is a number that can be put into |
6828 | * the lookup table to obtain the approximate cable length. */ | |
cd94dd0b AK |
6829 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
6830 | IGP02E1000_AGC_LENGTH_MASK; | |
868d5309 | 6831 | |
cd94dd0b AK |
6832 | /* Array index bound check. */ |
6833 | if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || | |
6834 | (cur_agc_index == 0)) | |
6835 | return -E1000_ERR_PHY; | |
868d5309 | 6836 | |
cd94dd0b AK |
6837 | /* Remove min & max AGC values from calculation. */ |
6838 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
6839 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
6840 | min_agc_index = cur_agc_index; | |
6841 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
6842 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
6843 | max_agc_index = cur_agc_index; | |
6844 | ||
6845 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
868d5309 MC |
6846 | } |
6847 | ||
cd94dd0b AK |
6848 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
6849 | e1000_igp_2_cable_length_table[max_agc_index]); | |
868d5309 MC |
6850 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
6851 | ||
6852 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
6853 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
6854 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
6855 | *max_length = agc_value + IGP02E1000_AGC_RANGE; | |
1da177e4 LT |
6856 | } |
6857 | ||
6858 | return E1000_SUCCESS; | |
6859 | } | |
6860 | ||
6861 | /****************************************************************************** | |
6862 | * Check the cable polarity | |
6863 | * | |
6864 | * hw - Struct containing variables accessed by shared code | |
6865 | * polarity - output parameter : 0 - Polarity is not reversed | |
6866 | * 1 - Polarity is reversed. | |
6867 | * | |
6868 | * returns: - E1000_ERR_XXX | |
6869 | * E1000_SUCCESS | |
6870 | * | |
6871 | * For phy's older then IGP, this function simply reads the polarity bit in the | |
6872 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is | |
6873 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will | |
6874 | * return 0. If the link speed is 1000 Mbps the polarity status is in the | |
6875 | * IGP01E1000_PHY_PCS_INIT_REG. | |
6876 | *****************************************************************************/ | |
3ad2cc67 | 6877 | static int32_t |
1da177e4 | 6878 | e1000_check_polarity(struct e1000_hw *hw, |
70c6f30a | 6879 | e1000_rev_polarity *polarity) |
1da177e4 LT |
6880 | { |
6881 | int32_t ret_val; | |
6882 | uint16_t phy_data; | |
6883 | ||
6884 | DEBUGFUNC("e1000_check_polarity"); | |
6885 | ||
6418ecc6 JK |
6886 | if ((hw->phy_type == e1000_phy_m88) || |
6887 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6888 | /* return the Polarity bit in the Status register. */ |
6889 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | |
6890 | &phy_data); | |
8fc897b0 | 6891 | if (ret_val) |
1da177e4 | 6892 | return ret_val; |
70c6f30a JK |
6893 | *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
6894 | M88E1000_PSSR_REV_POLARITY_SHIFT) ? | |
6895 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
6896 | ||
cd94dd0b AK |
6897 | } else if (hw->phy_type == e1000_phy_igp || |
6898 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 6899 | hw->phy_type == e1000_phy_igp_2) { |
1da177e4 LT |
6900 | /* Read the Status register to check the speed */ |
6901 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | |
6902 | &phy_data); | |
8fc897b0 | 6903 | if (ret_val) |
1da177e4 LT |
6904 | return ret_val; |
6905 | ||
6906 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to | |
6907 | * find the polarity status */ | |
8fc897b0 | 6908 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
1da177e4 LT |
6909 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
6910 | ||
6911 | /* Read the GIG initialization PCS register (0x00B4) */ | |
6912 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | |
6913 | &phy_data); | |
8fc897b0 | 6914 | if (ret_val) |
1da177e4 LT |
6915 | return ret_val; |
6916 | ||
6917 | /* Check the polarity bits */ | |
70c6f30a JK |
6918 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
6919 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 LT |
6920 | } else { |
6921 | /* For 10 Mbps, read the polarity bit in the status register. (for | |
6922 | * 100 Mbps this bit is always 0) */ | |
70c6f30a JK |
6923 | *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
6924 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 | 6925 | } |
cd94dd0b AK |
6926 | } else if (hw->phy_type == e1000_phy_ife) { |
6927 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, | |
6928 | &phy_data); | |
6929 | if (ret_val) | |
6930 | return ret_val; | |
70c6f30a JK |
6931 | *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> |
6932 | IFE_PESC_POLARITY_REVERSED_SHIFT) ? | |
6933 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 LT |
6934 | } |
6935 | return E1000_SUCCESS; | |
6936 | } | |
6937 | ||
6938 | /****************************************************************************** | |
6939 | * Check if Downshift occured | |
6940 | * | |
6941 | * hw - Struct containing variables accessed by shared code | |
6942 | * downshift - output parameter : 0 - No Downshift ocured. | |
6943 | * 1 - Downshift ocured. | |
6944 | * | |
6945 | * returns: - E1000_ERR_XXX | |
76c224bc | 6946 | * E1000_SUCCESS |
1da177e4 LT |
6947 | * |
6948 | * For phy's older then IGP, this function reads the Downshift bit in the Phy | |
6949 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the | |
6950 | * Link Health register. In IGP this bit is latched high, so the driver must | |
6951 | * read it immediately after link is established. | |
6952 | *****************************************************************************/ | |
3ad2cc67 | 6953 | static int32_t |
1da177e4 LT |
6954 | e1000_check_downshift(struct e1000_hw *hw) |
6955 | { | |
6956 | int32_t ret_val; | |
6957 | uint16_t phy_data; | |
6958 | ||
6959 | DEBUGFUNC("e1000_check_downshift"); | |
6960 | ||
cd94dd0b AK |
6961 | if (hw->phy_type == e1000_phy_igp || |
6962 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 6963 | hw->phy_type == e1000_phy_igp_2) { |
1da177e4 LT |
6964 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
6965 | &phy_data); | |
8fc897b0 | 6966 | if (ret_val) |
1da177e4 LT |
6967 | return ret_val; |
6968 | ||
6969 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; | |
6418ecc6 JK |
6970 | } else if ((hw->phy_type == e1000_phy_m88) || |
6971 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6972 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6973 | &phy_data); | |
8fc897b0 | 6974 | if (ret_val) |
1da177e4 LT |
6975 | return ret_val; |
6976 | ||
6977 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | |
6978 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | |
cd94dd0b AK |
6979 | } else if (hw->phy_type == e1000_phy_ife) { |
6980 | /* e1000_phy_ife supports 10/100 speed only */ | |
6981 | hw->speed_downgraded = FALSE; | |
1da177e4 | 6982 | } |
2d7edb92 | 6983 | |
1da177e4 LT |
6984 | return E1000_SUCCESS; |
6985 | } | |
6986 | ||
6987 | /***************************************************************************** | |
6988 | * | |
6989 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a | |
6990 | * gigabit link is achieved to improve link quality. | |
6991 | * | |
6992 | * hw: Struct containing variables accessed by shared code | |
6993 | * | |
6994 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
6995 | * E1000_SUCCESS at any other case. | |
6996 | * | |
6997 | ****************************************************************************/ | |
6998 | ||
3ad2cc67 | 6999 | static int32_t |
1da177e4 LT |
7000 | e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
7001 | boolean_t link_up) | |
7002 | { | |
7003 | int32_t ret_val; | |
7004 | uint16_t phy_data, phy_saved_data, speed, duplex, i; | |
7005 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
7006 | {IGP01E1000_PHY_AGC_PARAM_A, | |
7007 | IGP01E1000_PHY_AGC_PARAM_B, | |
7008 | IGP01E1000_PHY_AGC_PARAM_C, | |
7009 | IGP01E1000_PHY_AGC_PARAM_D}; | |
7010 | uint16_t min_length, max_length; | |
7011 | ||
7012 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | |
7013 | ||
8fc897b0 | 7014 | if (hw->phy_type != e1000_phy_igp) |
1da177e4 LT |
7015 | return E1000_SUCCESS; |
7016 | ||
8fc897b0 | 7017 | if (link_up) { |
1da177e4 | 7018 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
8fc897b0 | 7019 | if (ret_val) { |
1da177e4 LT |
7020 | DEBUGOUT("Error getting link speed and duplex\n"); |
7021 | return ret_val; | |
7022 | } | |
7023 | ||
8fc897b0 | 7024 | if (speed == SPEED_1000) { |
1da177e4 | 7025 | |
cd94dd0b AK |
7026 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
7027 | if (ret_val) | |
7028 | return ret_val; | |
1da177e4 | 7029 | |
8fc897b0 | 7030 | if ((hw->dsp_config_state == e1000_dsp_config_enabled) && |
1da177e4 LT |
7031 | min_length >= e1000_igp_cable_length_50) { |
7032 | ||
8fc897b0 | 7033 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 LT |
7034 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
7035 | &phy_data); | |
8fc897b0 | 7036 | if (ret_val) |
1da177e4 LT |
7037 | return ret_val; |
7038 | ||
7039 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
7040 | ||
7041 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], | |
7042 | phy_data); | |
8fc897b0 | 7043 | if (ret_val) |
1da177e4 LT |
7044 | return ret_val; |
7045 | } | |
7046 | hw->dsp_config_state = e1000_dsp_config_activated; | |
7047 | } | |
7048 | ||
8fc897b0 | 7049 | if ((hw->ffe_config_state == e1000_ffe_config_enabled) && |
1da177e4 LT |
7050 | (min_length < e1000_igp_cable_length_50)) { |
7051 | ||
7052 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; | |
7053 | uint32_t idle_errs = 0; | |
7054 | ||
7055 | /* clear previous idle error counts */ | |
7056 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
7057 | &phy_data); | |
8fc897b0 | 7058 | if (ret_val) |
1da177e4 LT |
7059 | return ret_val; |
7060 | ||
8fc897b0 | 7061 | for (i = 0; i < ffe_idle_err_timeout; i++) { |
1da177e4 LT |
7062 | udelay(1000); |
7063 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
7064 | &phy_data); | |
8fc897b0 | 7065 | if (ret_val) |
1da177e4 LT |
7066 | return ret_val; |
7067 | ||
7068 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); | |
8fc897b0 | 7069 | if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
1da177e4 LT |
7070 | hw->ffe_config_state = e1000_ffe_config_active; |
7071 | ||
7072 | ret_val = e1000_write_phy_reg(hw, | |
7073 | IGP01E1000_PHY_DSP_FFE, | |
7074 | IGP01E1000_PHY_DSP_FFE_CM_CP); | |
8fc897b0 | 7075 | if (ret_val) |
1da177e4 LT |
7076 | return ret_val; |
7077 | break; | |
7078 | } | |
7079 | ||
8fc897b0 | 7080 | if (idle_errs) |
1da177e4 LT |
7081 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
7082 | } | |
7083 | } | |
7084 | } | |
7085 | } else { | |
8fc897b0 | 7086 | if (hw->dsp_config_state == e1000_dsp_config_activated) { |
1da177e4 LT |
7087 | /* Save off the current value of register 0x2F5B to be restored at |
7088 | * the end of the routines. */ | |
7089 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
7090 | ||
8fc897b0 | 7091 | if (ret_val) |
1da177e4 LT |
7092 | return ret_val; |
7093 | ||
7094 | /* Disable the PHY transmitter */ | |
7095 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
7096 | ||
8fc897b0 | 7097 | if (ret_val) |
1da177e4 LT |
7098 | return ret_val; |
7099 | ||
f8ec4733 | 7100 | mdelay(20); |
1da177e4 LT |
7101 | |
7102 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
7103 | IGP01E1000_IEEE_FORCE_GIGA); | |
8fc897b0 | 7104 | if (ret_val) |
1da177e4 | 7105 | return ret_val; |
8fc897b0 | 7106 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 | 7107 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
8fc897b0 | 7108 | if (ret_val) |
1da177e4 LT |
7109 | return ret_val; |
7110 | ||
7111 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
7112 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | |
7113 | ||
7114 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); | |
8fc897b0 | 7115 | if (ret_val) |
1da177e4 LT |
7116 | return ret_val; |
7117 | } | |
7118 | ||
7119 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
7120 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
8fc897b0 | 7121 | if (ret_val) |
1da177e4 LT |
7122 | return ret_val; |
7123 | ||
f8ec4733 | 7124 | mdelay(20); |
1da177e4 LT |
7125 | |
7126 | /* Now enable the transmitter */ | |
7127 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
7128 | ||
8fc897b0 | 7129 | if (ret_val) |
1da177e4 LT |
7130 | return ret_val; |
7131 | ||
7132 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
7133 | } | |
7134 | ||
8fc897b0 | 7135 | if (hw->ffe_config_state == e1000_ffe_config_active) { |
1da177e4 LT |
7136 | /* Save off the current value of register 0x2F5B to be restored at |
7137 | * the end of the routines. */ | |
7138 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
7139 | ||
8fc897b0 | 7140 | if (ret_val) |
1da177e4 LT |
7141 | return ret_val; |
7142 | ||
7143 | /* Disable the PHY transmitter */ | |
7144 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
7145 | ||
8fc897b0 | 7146 | if (ret_val) |
1da177e4 LT |
7147 | return ret_val; |
7148 | ||
f8ec4733 | 7149 | mdelay(20); |
1da177e4 LT |
7150 | |
7151 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
7152 | IGP01E1000_IEEE_FORCE_GIGA); | |
8fc897b0 | 7153 | if (ret_val) |
1da177e4 LT |
7154 | return ret_val; |
7155 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | |
7156 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | |
8fc897b0 | 7157 | if (ret_val) |
1da177e4 LT |
7158 | return ret_val; |
7159 | ||
7160 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
7161 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
8fc897b0 | 7162 | if (ret_val) |
1da177e4 LT |
7163 | return ret_val; |
7164 | ||
f8ec4733 | 7165 | mdelay(20); |
1da177e4 LT |
7166 | |
7167 | /* Now enable the transmitter */ | |
7168 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
7169 | ||
8fc897b0 | 7170 | if (ret_val) |
1da177e4 LT |
7171 | return ret_val; |
7172 | ||
7173 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
7174 | } | |
7175 | } | |
7176 | return E1000_SUCCESS; | |
7177 | } | |
7178 | ||
7179 | /***************************************************************************** | |
7180 | * Set PHY to class A mode | |
7181 | * Assumes the following operations will follow to enable the new class mode. | |
7182 | * 1. Do a PHY soft reset | |
7183 | * 2. Restart auto-negotiation or force link. | |
7184 | * | |
7185 | * hw - Struct containing variables accessed by shared code | |
7186 | ****************************************************************************/ | |
7187 | static int32_t | |
7188 | e1000_set_phy_mode(struct e1000_hw *hw) | |
7189 | { | |
7190 | int32_t ret_val; | |
7191 | uint16_t eeprom_data; | |
7192 | ||
7193 | DEBUGFUNC("e1000_set_phy_mode"); | |
7194 | ||
8fc897b0 AK |
7195 | if ((hw->mac_type == e1000_82545_rev_3) && |
7196 | (hw->media_type == e1000_media_type_copper)) { | |
1da177e4 | 7197 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
8fc897b0 | 7198 | if (ret_val) { |
1da177e4 LT |
7199 | return ret_val; |
7200 | } | |
7201 | ||
8fc897b0 AK |
7202 | if ((eeprom_data != EEPROM_RESERVED_WORD) && |
7203 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
1da177e4 | 7204 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
8fc897b0 | 7205 | if (ret_val) |
1da177e4 LT |
7206 | return ret_val; |
7207 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); | |
8fc897b0 | 7208 | if (ret_val) |
1da177e4 LT |
7209 | return ret_val; |
7210 | ||
7211 | hw->phy_reset_disable = FALSE; | |
7212 | } | |
7213 | } | |
7214 | ||
7215 | return E1000_SUCCESS; | |
7216 | } | |
7217 | ||
7218 | /***************************************************************************** | |
7219 | * | |
7220 | * This function sets the lplu state according to the active flag. When | |
7221 | * activating lplu this function also disables smart speed and vise versa. | |
7222 | * lplu will not be activated unless the device autonegotiation advertisment | |
7223 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
7224 | * hw: Struct containing variables accessed by shared code | |
7225 | * active - true to enable lplu false to disable lplu. | |
7226 | * | |
7227 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
7228 | * E1000_SUCCESS at any other case. | |
7229 | * | |
7230 | ****************************************************************************/ | |
7231 | ||
3ad2cc67 | 7232 | static int32_t |
1da177e4 LT |
7233 | e1000_set_d3_lplu_state(struct e1000_hw *hw, |
7234 | boolean_t active) | |
7235 | { | |
cd94dd0b | 7236 | uint32_t phy_ctrl = 0; |
1da177e4 LT |
7237 | int32_t ret_val; |
7238 | uint16_t phy_data; | |
7239 | DEBUGFUNC("e1000_set_d3_lplu_state"); | |
7240 | ||
cd94dd0b AK |
7241 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
7242 | && hw->phy_type != e1000_phy_igp_3) | |
1da177e4 LT |
7243 | return E1000_SUCCESS; |
7244 | ||
7245 | /* During driver activity LPLU should not be used or it will attain link | |
7246 | * from the lowest speeds starting from 10Mbps. The capability is used for | |
7247 | * Dx transitions and states */ | |
cd94dd0b | 7248 | if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
2d7edb92 | 7249 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
cd94dd0b | 7250 | if (ret_val) |
2d7edb92 | 7251 | return ret_val; |
cd94dd0b AK |
7252 | } else if (hw->mac_type == e1000_ich8lan) { |
7253 | /* MAC writes into PHY register based on the state transition | |
7254 | * and start auto-negotiation. SW driver can overwrite the settings | |
7255 | * in CSR PHY power control E1000_PHY_CTRL register. */ | |
7256 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
2d7edb92 MC |
7257 | } else { |
7258 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
8fc897b0 | 7259 | if (ret_val) |
1da177e4 | 7260 | return ret_val; |
2d7edb92 MC |
7261 | } |
7262 | ||
8fc897b0 AK |
7263 | if (!active) { |
7264 | if (hw->mac_type == e1000_82541_rev_2 || | |
7265 | hw->mac_type == e1000_82547_rev_2) { | |
2d7edb92 MC |
7266 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
7267 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
8fc897b0 | 7268 | if (ret_val) |
2d7edb92 MC |
7269 | return ret_val; |
7270 | } else { | |
cd94dd0b AK |
7271 | if (hw->mac_type == e1000_ich8lan) { |
7272 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
7273 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
7274 | } else { | |
2d7edb92 MC |
7275 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
7276 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
7277 | phy_data); | |
7278 | if (ret_val) | |
7279 | return ret_val; | |
cd94dd0b | 7280 | } |
2d7edb92 | 7281 | } |
1da177e4 LT |
7282 | |
7283 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
7284 | * Dx states where the power conservation is most important. During | |
7285 | * driver activity we should enable SmartSpeed, so performance is | |
7286 | * maintained. */ | |
7287 | if (hw->smart_speed == e1000_smart_speed_on) { | |
7288 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7289 | &phy_data); | |
8fc897b0 | 7290 | if (ret_val) |
1da177e4 LT |
7291 | return ret_val; |
7292 | ||
7293 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
7294 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7295 | phy_data); | |
8fc897b0 | 7296 | if (ret_val) |
1da177e4 LT |
7297 | return ret_val; |
7298 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
7299 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7300 | &phy_data); | |
35574764 | 7301 | if (ret_val) |
1da177e4 LT |
7302 | return ret_val; |
7303 | ||
7304 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7305 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7306 | phy_data); | |
8fc897b0 | 7307 | if (ret_val) |
1da177e4 LT |
7308 | return ret_val; |
7309 | } | |
7310 | ||
8fc897b0 AK |
7311 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
7312 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | |
7313 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
1da177e4 | 7314 | |
8fc897b0 | 7315 | if (hw->mac_type == e1000_82541_rev_2 || |
cd94dd0b | 7316 | hw->mac_type == e1000_82547_rev_2) { |
2d7edb92 MC |
7317 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
7318 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
8fc897b0 | 7319 | if (ret_val) |
2d7edb92 MC |
7320 | return ret_val; |
7321 | } else { | |
cd94dd0b AK |
7322 | if (hw->mac_type == e1000_ich8lan) { |
7323 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
7324 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
7325 | } else { | |
2d7edb92 MC |
7326 | phy_data |= IGP02E1000_PM_D3_LPLU; |
7327 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
7328 | phy_data); | |
7329 | if (ret_val) | |
7330 | return ret_val; | |
cd94dd0b | 7331 | } |
2d7edb92 MC |
7332 | } |
7333 | ||
7334 | /* When LPLU is enabled we should disable SmartSpeed */ | |
7335 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
8fc897b0 | 7336 | if (ret_val) |
2d7edb92 MC |
7337 | return ret_val; |
7338 | ||
7339 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7340 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
8fc897b0 | 7341 | if (ret_val) |
2d7edb92 MC |
7342 | return ret_val; |
7343 | ||
7344 | } | |
7345 | return E1000_SUCCESS; | |
7346 | } | |
7347 | ||
7348 | /***************************************************************************** | |
7349 | * | |
7350 | * This function sets the lplu d0 state according to the active flag. When | |
7351 | * activating lplu this function also disables smart speed and vise versa. | |
7352 | * lplu will not be activated unless the device autonegotiation advertisment | |
7353 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
7354 | * hw: Struct containing variables accessed by shared code | |
7355 | * active - true to enable lplu false to disable lplu. | |
7356 | * | |
7357 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
7358 | * E1000_SUCCESS at any other case. | |
7359 | * | |
7360 | ****************************************************************************/ | |
7361 | ||
3ad2cc67 | 7362 | static int32_t |
2d7edb92 MC |
7363 | e1000_set_d0_lplu_state(struct e1000_hw *hw, |
7364 | boolean_t active) | |
7365 | { | |
cd94dd0b | 7366 | uint32_t phy_ctrl = 0; |
2d7edb92 MC |
7367 | int32_t ret_val; |
7368 | uint16_t phy_data; | |
7369 | DEBUGFUNC("e1000_set_d0_lplu_state"); | |
7370 | ||
8fc897b0 | 7371 | if (hw->mac_type <= e1000_82547_rev_2) |
2d7edb92 MC |
7372 | return E1000_SUCCESS; |
7373 | ||
cd94dd0b AK |
7374 | if (hw->mac_type == e1000_ich8lan) { |
7375 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
7376 | } else { | |
2d7edb92 | 7377 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
8fc897b0 | 7378 | if (ret_val) |
1da177e4 | 7379 | return ret_val; |
cd94dd0b | 7380 | } |
1da177e4 | 7381 | |
2d7edb92 | 7382 | if (!active) { |
cd94dd0b AK |
7383 | if (hw->mac_type == e1000_ich8lan) { |
7384 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
7385 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
7386 | } else { | |
2d7edb92 MC |
7387 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
7388 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
7389 | if (ret_val) | |
7390 | return ret_val; | |
cd94dd0b | 7391 | } |
2d7edb92 MC |
7392 | |
7393 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
7394 | * Dx states where the power conservation is most important. During | |
7395 | * driver activity we should enable SmartSpeed, so performance is | |
7396 | * maintained. */ | |
7397 | if (hw->smart_speed == e1000_smart_speed_on) { | |
7398 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7399 | &phy_data); | |
8fc897b0 | 7400 | if (ret_val) |
2d7edb92 MC |
7401 | return ret_val; |
7402 | ||
7403 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
7404 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7405 | phy_data); | |
8fc897b0 | 7406 | if (ret_val) |
2d7edb92 MC |
7407 | return ret_val; |
7408 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
7409 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7410 | &phy_data); | |
35574764 | 7411 | if (ret_val) |
2d7edb92 MC |
7412 | return ret_val; |
7413 | ||
7414 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7415 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7416 | phy_data); | |
8fc897b0 | 7417 | if (ret_val) |
2d7edb92 MC |
7418 | return ret_val; |
7419 | } | |
7420 | ||
7421 | ||
7422 | } else { | |
76c224bc | 7423 | |
cd94dd0b AK |
7424 | if (hw->mac_type == e1000_ich8lan) { |
7425 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
7426 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
7427 | } else { | |
76c224bc | 7428 | phy_data |= IGP02E1000_PM_D0_LPLU; |
2d7edb92 MC |
7429 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
7430 | if (ret_val) | |
7431 | return ret_val; | |
cd94dd0b | 7432 | } |
2d7edb92 | 7433 | |
1da177e4 LT |
7434 | /* When LPLU is enabled we should disable SmartSpeed */ |
7435 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
8fc897b0 | 7436 | if (ret_val) |
1da177e4 LT |
7437 | return ret_val; |
7438 | ||
7439 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7440 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
8fc897b0 | 7441 | if (ret_val) |
1da177e4 LT |
7442 | return ret_val; |
7443 | ||
7444 | } | |
7445 | return E1000_SUCCESS; | |
7446 | } | |
7447 | ||
7448 | /****************************************************************************** | |
7449 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. | |
7450 | * | |
7451 | * hw - Struct containing variables accessed by shared code | |
7452 | *****************************************************************************/ | |
7453 | static int32_t | |
7454 | e1000_set_vco_speed(struct e1000_hw *hw) | |
7455 | { | |
7456 | int32_t ret_val; | |
7457 | uint16_t default_page = 0; | |
7458 | uint16_t phy_data; | |
7459 | ||
7460 | DEBUGFUNC("e1000_set_vco_speed"); | |
7461 | ||
8fc897b0 | 7462 | switch (hw->mac_type) { |
1da177e4 LT |
7463 | case e1000_82545_rev_3: |
7464 | case e1000_82546_rev_3: | |
7465 | break; | |
7466 | default: | |
7467 | return E1000_SUCCESS; | |
7468 | } | |
7469 | ||
7470 | /* Set PHY register 30, page 5, bit 8 to 0 */ | |
7471 | ||
7472 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); | |
8fc897b0 | 7473 | if (ret_val) |
1da177e4 LT |
7474 | return ret_val; |
7475 | ||
7476 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); | |
8fc897b0 | 7477 | if (ret_val) |
1da177e4 LT |
7478 | return ret_val; |
7479 | ||
7480 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
8fc897b0 | 7481 | if (ret_val) |
1da177e4 LT |
7482 | return ret_val; |
7483 | ||
7484 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | |
7485 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
8fc897b0 | 7486 | if (ret_val) |
1da177e4 LT |
7487 | return ret_val; |
7488 | ||
7489 | /* Set PHY register 30, page 4, bit 11 to 1 */ | |
7490 | ||
7491 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | |
8fc897b0 | 7492 | if (ret_val) |
1da177e4 LT |
7493 | return ret_val; |
7494 | ||
7495 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
8fc897b0 | 7496 | if (ret_val) |
1da177e4 LT |
7497 | return ret_val; |
7498 | ||
7499 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; | |
7500 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
8fc897b0 | 7501 | if (ret_val) |
1da177e4 LT |
7502 | return ret_val; |
7503 | ||
7504 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); | |
8fc897b0 | 7505 | if (ret_val) |
1da177e4 LT |
7506 | return ret_val; |
7507 | ||
7508 | return E1000_SUCCESS; | |
7509 | } | |
7510 | ||
1da177e4 | 7511 | |
2d7edb92 MC |
7512 | /***************************************************************************** |
7513 | * This function reads the cookie from ARC ram. | |
7514 | * | |
7515 | * returns: - E1000_SUCCESS . | |
7516 | ****************************************************************************/ | |
35574764 | 7517 | static int32_t |
2d7edb92 MC |
7518 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
7519 | { | |
7520 | uint8_t i; | |
76c224bc | 7521 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
2d7edb92 | 7522 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
1da177e4 | 7523 | |
2d7edb92 MC |
7524 | length = (length >> 2); |
7525 | offset = (offset >> 2); | |
1da177e4 | 7526 | |
2d7edb92 MC |
7527 | for (i = 0; i < length; i++) { |
7528 | *((uint32_t *) buffer + i) = | |
7529 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); | |
7530 | } | |
7531 | return E1000_SUCCESS; | |
7532 | } | |
7533 | ||
7534 | ||
7535 | /***************************************************************************** | |
7536 | * This function checks whether the HOST IF is enabled for command operaton | |
7537 | * and also checks whether the previous command is completed. | |
7538 | * It busy waits in case of previous command is not completed. | |
7539 | * | |
76c224bc | 7540 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
2d7edb92 MC |
7541 | * timeout |
7542 | * - E1000_SUCCESS for success. | |
7543 | ****************************************************************************/ | |
3ad2cc67 | 7544 | static int32_t |
2d7edb92 MC |
7545 | e1000_mng_enable_host_if(struct e1000_hw * hw) |
7546 | { | |
7547 | uint32_t hicr; | |
7548 | uint8_t i; | |
7549 | ||
7550 | /* Check that the host interface is enabled. */ | |
7551 | hicr = E1000_READ_REG(hw, HICR); | |
7552 | if ((hicr & E1000_HICR_EN) == 0) { | |
7553 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | |
7554 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
7555 | } | |
7556 | /* check the previous command is completed */ | |
7557 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | |
7558 | hicr = E1000_READ_REG(hw, HICR); | |
7559 | if (!(hicr & E1000_HICR_C)) | |
7560 | break; | |
f8ec4733 | 7561 | mdelay(1); |
2d7edb92 MC |
7562 | } |
7563 | ||
76c224bc | 7564 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
2d7edb92 MC |
7565 | DEBUGOUT("Previous command timeout failed .\n"); |
7566 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
7567 | } | |
7568 | return E1000_SUCCESS; | |
7569 | } | |
7570 | ||
7571 | /***************************************************************************** | |
7572 | * This function writes the buffer content at the offset given on the host if. | |
7573 | * It also does alignment considerations to do the writes in most efficient way. | |
7574 | * Also fills up the sum of the buffer in *buffer parameter. | |
7575 | * | |
7576 | * returns - E1000_SUCCESS for success. | |
7577 | ****************************************************************************/ | |
3ad2cc67 | 7578 | static int32_t |
2d7edb92 MC |
7579 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
7580 | uint16_t length, uint16_t offset, uint8_t *sum) | |
7581 | { | |
7582 | uint8_t *tmp; | |
7583 | uint8_t *bufptr = buffer; | |
8fc897b0 | 7584 | uint32_t data = 0; |
2d7edb92 MC |
7585 | uint16_t remaining, i, j, prev_bytes; |
7586 | ||
7587 | /* sum = only sum of the data and it is not checksum */ | |
7588 | ||
7589 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | |
7590 | return -E1000_ERR_PARAM; | |
7591 | } | |
7592 | ||
7593 | tmp = (uint8_t *)&data; | |
7594 | prev_bytes = offset & 0x3; | |
7595 | offset &= 0xFFFC; | |
7596 | offset >>= 2; | |
7597 | ||
7598 | if (prev_bytes) { | |
7599 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | |
7600 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { | |
7601 | *(tmp + j) = *bufptr++; | |
7602 | *sum += *(tmp + j); | |
7603 | } | |
7604 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | |
7605 | length -= j - prev_bytes; | |
7606 | offset++; | |
7607 | } | |
7608 | ||
7609 | remaining = length & 0x3; | |
7610 | length -= remaining; | |
7611 | ||
7612 | /* Calculate length in DWORDs */ | |
7613 | length >>= 2; | |
7614 | ||
7615 | /* The device driver writes the relevant command block into the | |
7616 | * ram area. */ | |
7617 | for (i = 0; i < length; i++) { | |
7618 | for (j = 0; j < sizeof(uint32_t); j++) { | |
7619 | *(tmp + j) = *bufptr++; | |
7620 | *sum += *(tmp + j); | |
7621 | } | |
7622 | ||
7623 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
7624 | } | |
7625 | if (remaining) { | |
7626 | for (j = 0; j < sizeof(uint32_t); j++) { | |
7627 | if (j < remaining) | |
7628 | *(tmp + j) = *bufptr++; | |
7629 | else | |
7630 | *(tmp + j) = 0; | |
7631 | ||
7632 | *sum += *(tmp + j); | |
7633 | } | |
7634 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
7635 | } | |
7636 | ||
7637 | return E1000_SUCCESS; | |
7638 | } | |
7639 | ||
7640 | ||
7641 | /***************************************************************************** | |
7642 | * This function writes the command header after does the checksum calculation. | |
7643 | * | |
7644 | * returns - E1000_SUCCESS for success. | |
7645 | ****************************************************************************/ | |
3ad2cc67 | 7646 | static int32_t |
2d7edb92 MC |
7647 | e1000_mng_write_cmd_header(struct e1000_hw * hw, |
7648 | struct e1000_host_mng_command_header * hdr) | |
7649 | { | |
7650 | uint16_t i; | |
7651 | uint8_t sum; | |
7652 | uint8_t *buffer; | |
7653 | ||
7654 | /* Write the whole command header structure which includes sum of | |
7655 | * the buffer */ | |
7656 | ||
7657 | uint16_t length = sizeof(struct e1000_host_mng_command_header); | |
7658 | ||
7659 | sum = hdr->checksum; | |
7660 | hdr->checksum = 0; | |
7661 | ||
7662 | buffer = (uint8_t *) hdr; | |
7663 | i = length; | |
8fc897b0 | 7664 | while (i--) |
2d7edb92 MC |
7665 | sum += buffer[i]; |
7666 | ||
7667 | hdr->checksum = 0 - sum; | |
7668 | ||
7669 | length >>= 2; | |
7670 | /* The device driver writes the relevant command block into the ram area. */ | |
4ca213a6 | 7671 | for (i = 0; i < length; i++) { |
2d7edb92 | 7672 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
4ca213a6 AK |
7673 | E1000_WRITE_FLUSH(hw); |
7674 | } | |
2d7edb92 MC |
7675 | |
7676 | return E1000_SUCCESS; | |
7677 | } | |
7678 | ||
7679 | ||
7680 | /***************************************************************************** | |
7681 | * This function indicates to ARC that a new command is pending which completes | |
7682 | * one write operation by the driver. | |
7683 | * | |
7684 | * returns - E1000_SUCCESS for success. | |
7685 | ****************************************************************************/ | |
3ad2cc67 | 7686 | static int32_t |
8fc897b0 | 7687 | e1000_mng_write_commit(struct e1000_hw * hw) |
2d7edb92 MC |
7688 | { |
7689 | uint32_t hicr; | |
7690 | ||
7691 | hicr = E1000_READ_REG(hw, HICR); | |
7692 | /* Setting this bit tells the ARC that a new command is pending. */ | |
7693 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); | |
7694 | ||
7695 | return E1000_SUCCESS; | |
7696 | } | |
7697 | ||
7698 | ||
7699 | /***************************************************************************** | |
7700 | * This function checks the mode of the firmware. | |
7701 | * | |
7702 | * returns - TRUE when the mode is IAMT or FALSE. | |
7703 | ****************************************************************************/ | |
7704 | boolean_t | |
cd94dd0b | 7705 | e1000_check_mng_mode(struct e1000_hw *hw) |
2d7edb92 MC |
7706 | { |
7707 | uint32_t fwsm; | |
7708 | ||
7709 | fwsm = E1000_READ_REG(hw, FWSM); | |
7710 | ||
cd94dd0b AK |
7711 | if (hw->mac_type == e1000_ich8lan) { |
7712 | if ((fwsm & E1000_FWSM_MODE_MASK) == | |
7713 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
7714 | return TRUE; | |
7715 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == | |
7716 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
2d7edb92 MC |
7717 | return TRUE; |
7718 | ||
7719 | return FALSE; | |
7720 | } | |
7721 | ||
7722 | ||
7723 | /***************************************************************************** | |
7724 | * This function writes the dhcp info . | |
7725 | ****************************************************************************/ | |
7726 | int32_t | |
7727 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | |
35574764 | 7728 | uint16_t length) |
2d7edb92 MC |
7729 | { |
7730 | int32_t ret_val; | |
7731 | struct e1000_host_mng_command_header hdr; | |
7732 | ||
7733 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | |
7734 | hdr.command_length = length; | |
7735 | hdr.reserved1 = 0; | |
7736 | hdr.reserved2 = 0; | |
7737 | hdr.checksum = 0; | |
7738 | ||
7739 | ret_val = e1000_mng_enable_host_if(hw); | |
7740 | if (ret_val == E1000_SUCCESS) { | |
7741 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | |
7742 | &(hdr.checksum)); | |
7743 | if (ret_val == E1000_SUCCESS) { | |
7744 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | |
7745 | if (ret_val == E1000_SUCCESS) | |
7746 | ret_val = e1000_mng_write_commit(hw); | |
7747 | } | |
7748 | } | |
7749 | return ret_val; | |
7750 | } | |
7751 | ||
7752 | ||
7753 | /***************************************************************************** | |
7754 | * This function calculates the checksum. | |
7755 | * | |
7756 | * returns - checksum of buffer contents. | |
7757 | ****************************************************************************/ | |
35574764 | 7758 | static uint8_t |
2d7edb92 MC |
7759 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
7760 | { | |
7761 | uint8_t sum = 0; | |
7762 | uint32_t i; | |
7763 | ||
7764 | if (!buffer) | |
7765 | return 0; | |
7766 | ||
7767 | for (i=0; i < length; i++) | |
7768 | sum += buffer[i]; | |
7769 | ||
7770 | return (uint8_t) (0 - sum); | |
7771 | } | |
7772 | ||
7773 | /***************************************************************************** | |
7774 | * This function checks whether tx pkt filtering needs to be enabled or not. | |
7775 | * | |
7776 | * returns - TRUE for packet filtering or FALSE. | |
7777 | ****************************************************************************/ | |
7778 | boolean_t | |
7779 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) | |
7780 | { | |
7781 | /* called in init as well as watchdog timer functions */ | |
7782 | ||
7783 | int32_t ret_val, checksum; | |
7784 | boolean_t tx_filter = FALSE; | |
7785 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); | |
7786 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); | |
7787 | ||
7788 | if (e1000_check_mng_mode(hw)) { | |
7789 | ret_val = e1000_mng_enable_host_if(hw); | |
7790 | if (ret_val == E1000_SUCCESS) { | |
7791 | ret_val = e1000_host_if_read_cookie(hw, buffer); | |
7792 | if (ret_val == E1000_SUCCESS) { | |
7793 | checksum = hdr->checksum; | |
7794 | hdr->checksum = 0; | |
7795 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | |
7796 | checksum == e1000_calculate_mng_checksum((char *)buffer, | |
7797 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | |
7798 | if (hdr->status & | |
7799 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | |
7800 | tx_filter = TRUE; | |
7801 | } else | |
7802 | tx_filter = TRUE; | |
7803 | } else | |
7804 | tx_filter = TRUE; | |
7805 | } | |
7806 | } | |
7807 | ||
7808 | hw->tx_pkt_filtering = tx_filter; | |
7809 | return tx_filter; | |
7810 | } | |
7811 | ||
7812 | /****************************************************************************** | |
7813 | * Verifies the hardware needs to allow ARPs to be processed by the host | |
7814 | * | |
7815 | * hw - Struct containing variables accessed by shared code | |
7816 | * | |
7817 | * returns: - TRUE/FALSE | |
7818 | * | |
7819 | *****************************************************************************/ | |
7820 | uint32_t | |
7821 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) | |
7822 | { | |
7823 | uint32_t manc; | |
7824 | uint32_t fwsm, factps; | |
7825 | ||
7826 | if (hw->asf_firmware_present) { | |
7827 | manc = E1000_READ_REG(hw, MANC); | |
7828 | ||
7829 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | |
7830 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | |
7831 | return FALSE; | |
7832 | if (e1000_arc_subsystem_valid(hw) == TRUE) { | |
7833 | fwsm = E1000_READ_REG(hw, FWSM); | |
7834 | factps = E1000_READ_REG(hw, FACTPS); | |
7835 | ||
0fccd0e9 JG |
7836 | if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == |
7837 | e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) | |
2d7edb92 MC |
7838 | return TRUE; |
7839 | } else | |
7840 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | |
7841 | return TRUE; | |
7842 | } | |
7843 | return FALSE; | |
7844 | } | |
7845 | ||
7846 | static int32_t | |
7847 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |
7848 | { | |
7849 | int32_t ret_val; | |
7850 | uint16_t mii_status_reg; | |
7851 | uint16_t i; | |
7852 | ||
7853 | /* Polarity reversal workaround for forced 10F/10H links. */ | |
7854 | ||
7855 | /* Disable the transmitter on the PHY */ | |
7856 | ||
7857 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
8fc897b0 | 7858 | if (ret_val) |
1da177e4 LT |
7859 | return ret_val; |
7860 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); | |
8fc897b0 | 7861 | if (ret_val) |
1da177e4 LT |
7862 | return ret_val; |
7863 | ||
7864 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
8fc897b0 | 7865 | if (ret_val) |
1da177e4 LT |
7866 | return ret_val; |
7867 | ||
7868 | /* This loop will early-out if the NO link condition has been met. */ | |
8fc897b0 | 7869 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
7870 | /* Read the MII Status Register and wait for Link Status bit |
7871 | * to be clear. | |
7872 | */ | |
7873 | ||
7874 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7875 | if (ret_val) |
1da177e4 LT |
7876 | return ret_val; |
7877 | ||
7878 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7879 | if (ret_val) |
1da177e4 LT |
7880 | return ret_val; |
7881 | ||
8fc897b0 | 7882 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
f8ec4733 | 7883 | mdelay(100); |
1da177e4 LT |
7884 | } |
7885 | ||
7886 | /* Recommended delay time after link has been lost */ | |
f8ec4733 | 7887 | mdelay(1000); |
1da177e4 LT |
7888 | |
7889 | /* Now we will re-enable th transmitter on the PHY */ | |
7890 | ||
7891 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
8fc897b0 | 7892 | if (ret_val) |
1da177e4 | 7893 | return ret_val; |
f8ec4733 | 7894 | mdelay(50); |
1da177e4 | 7895 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
8fc897b0 | 7896 | if (ret_val) |
1da177e4 | 7897 | return ret_val; |
f8ec4733 | 7898 | mdelay(50); |
1da177e4 | 7899 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
8fc897b0 | 7900 | if (ret_val) |
1da177e4 | 7901 | return ret_val; |
f8ec4733 | 7902 | mdelay(50); |
1da177e4 | 7903 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
8fc897b0 | 7904 | if (ret_val) |
1da177e4 LT |
7905 | return ret_val; |
7906 | ||
7907 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
8fc897b0 | 7908 | if (ret_val) |
1da177e4 LT |
7909 | return ret_val; |
7910 | ||
7911 | /* This loop will early-out if the link condition has been met. */ | |
8fc897b0 | 7912 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
7913 | /* Read the MII Status Register and wait for Link Status bit |
7914 | * to be set. | |
7915 | */ | |
7916 | ||
7917 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7918 | if (ret_val) |
1da177e4 LT |
7919 | return ret_val; |
7920 | ||
7921 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7922 | if (ret_val) |
1da177e4 LT |
7923 | return ret_val; |
7924 | ||
8fc897b0 | 7925 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
f8ec4733 | 7926 | mdelay(100); |
1da177e4 LT |
7927 | } |
7928 | return E1000_SUCCESS; | |
7929 | } | |
7930 | ||
2d7edb92 MC |
7931 | /*************************************************************************** |
7932 | * | |
7933 | * Disables PCI-Express master access. | |
7934 | * | |
7935 | * hw: Struct containing variables accessed by shared code | |
7936 | * | |
7937 | * returns: - none. | |
7938 | * | |
7939 | ***************************************************************************/ | |
3ad2cc67 | 7940 | static void |
2d7edb92 MC |
7941 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
7942 | { | |
7943 | uint32_t ctrl; | |
7944 | ||
7945 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | |
7946 | ||
7947 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7948 | return; | |
7949 | ||
7950 | ctrl = E1000_READ_REG(hw, CTRL); | |
7951 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | |
7952 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
7953 | } | |
7954 | ||
2d7edb92 MC |
7955 | /******************************************************************************* |
7956 | * | |
7957 | * Disables PCI-Express master access and verifies there are no pending requests | |
7958 | * | |
7959 | * hw: Struct containing variables accessed by shared code | |
7960 | * | |
7961 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | |
7962 | * caused the master requests to be disabled. | |
7963 | * E1000_SUCCESS master requests disabled. | |
7964 | * | |
7965 | ******************************************************************************/ | |
7966 | int32_t | |
7967 | e1000_disable_pciex_master(struct e1000_hw *hw) | |
7968 | { | |
7969 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ | |
7970 | ||
7971 | DEBUGFUNC("e1000_disable_pciex_master"); | |
7972 | ||
7973 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7974 | return E1000_SUCCESS; | |
7975 | ||
7976 | e1000_set_pci_express_master_disable(hw); | |
7977 | ||
8fc897b0 AK |
7978 | while (timeout) { |
7979 | if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) | |
2d7edb92 MC |
7980 | break; |
7981 | else | |
7982 | udelay(100); | |
7983 | timeout--; | |
7984 | } | |
7985 | ||
8fc897b0 | 7986 | if (!timeout) { |
2d7edb92 MC |
7987 | DEBUGOUT("Master requests are pending.\n"); |
7988 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | |
7989 | } | |
7990 | ||
7991 | return E1000_SUCCESS; | |
7992 | } | |
7993 | ||
7994 | /******************************************************************************* | |
7995 | * | |
7996 | * Check for EEPROM Auto Read bit done. | |
7997 | * | |
7998 | * hw: Struct containing variables accessed by shared code | |
7999 | * | |
8000 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
8001 | * E1000_SUCCESS at any other case. | |
8002 | * | |
8003 | ******************************************************************************/ | |
3ad2cc67 | 8004 | static int32_t |
2d7edb92 MC |
8005 | e1000_get_auto_rd_done(struct e1000_hw *hw) |
8006 | { | |
8007 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; | |
8008 | ||
8009 | DEBUGFUNC("e1000_get_auto_rd_done"); | |
8010 | ||
8011 | switch (hw->mac_type) { | |
8012 | default: | |
f8ec4733 | 8013 | msleep(5); |
2d7edb92 | 8014 | break; |
868d5309 MC |
8015 | case e1000_82571: |
8016 | case e1000_82572: | |
2d7edb92 | 8017 | case e1000_82573: |
6418ecc6 | 8018 | case e1000_80003es2lan: |
cd94dd0b AK |
8019 | case e1000_ich8lan: |
8020 | while (timeout) { | |
8021 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) | |
8022 | break; | |
f8ec4733 | 8023 | else msleep(1); |
2d7edb92 MC |
8024 | timeout--; |
8025 | } | |
8026 | ||
8fc897b0 | 8027 | if (!timeout) { |
2d7edb92 MC |
8028 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
8029 | return -E1000_ERR_RESET; | |
8030 | } | |
8031 | break; | |
8032 | } | |
8033 | ||
fd803241 JK |
8034 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
8035 | * Need to wait for PHY configuration completion before accessing NVM | |
8036 | * and PHY. */ | |
8037 | if (hw->mac_type == e1000_82573) | |
f8ec4733 | 8038 | msleep(25); |
fd803241 | 8039 | |
2d7edb92 MC |
8040 | return E1000_SUCCESS; |
8041 | } | |
8042 | ||
8043 | /*************************************************************************** | |
8044 | * Checks if the PHY configuration is done | |
8045 | * | |
8046 | * hw: Struct containing variables accessed by shared code | |
8047 | * | |
8048 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
8049 | * E1000_SUCCESS at any other case. | |
8050 | * | |
8051 | ***************************************************************************/ | |
3ad2cc67 | 8052 | static int32_t |
2d7edb92 MC |
8053 | e1000_get_phy_cfg_done(struct e1000_hw *hw) |
8054 | { | |
868d5309 MC |
8055 | int32_t timeout = PHY_CFG_TIMEOUT; |
8056 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; | |
8057 | ||
2d7edb92 MC |
8058 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
8059 | ||
868d5309 MC |
8060 | switch (hw->mac_type) { |
8061 | default: | |
f8ec4733 | 8062 | mdelay(10); |
868d5309 | 8063 | break; |
6418ecc6 JK |
8064 | case e1000_80003es2lan: |
8065 | /* Separate *_CFG_DONE_* bit for each port */ | |
8066 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) | |
8067 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; | |
8068 | /* Fall Through */ | |
868d5309 MC |
8069 | case e1000_82571: |
8070 | case e1000_82572: | |
8071 | while (timeout) { | |
8072 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | |
8073 | break; | |
8074 | else | |
f8ec4733 | 8075 | msleep(1); |
868d5309 MC |
8076 | timeout--; |
8077 | } | |
868d5309 MC |
8078 | if (!timeout) { |
8079 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | |
8080 | return -E1000_ERR_RESET; | |
8081 | } | |
8082 | break; | |
8083 | } | |
2d7edb92 MC |
8084 | |
8085 | return E1000_SUCCESS; | |
8086 | } | |
8087 | ||
8088 | /*************************************************************************** | |
8089 | * | |
8090 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
8091 | * adapter or Eeprom access. | |
8092 | * | |
8093 | * hw: Struct containing variables accessed by shared code | |
8094 | * | |
8095 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
8096 | * E1000_SUCCESS at any other case. | |
8097 | * | |
8098 | ***************************************************************************/ | |
3ad2cc67 | 8099 | static int32_t |
2d7edb92 MC |
8100 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
8101 | { | |
8102 | int32_t timeout; | |
8103 | uint32_t swsm; | |
8104 | ||
8105 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | |
8106 | ||
8fc897b0 | 8107 | if (!hw->eeprom_semaphore_present) |
2d7edb92 MC |
8108 | return E1000_SUCCESS; |
8109 | ||
6418ecc6 JK |
8110 | if (hw->mac_type == e1000_80003es2lan) { |
8111 | /* Get the SW semaphore. */ | |
8112 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | |
8113 | return -E1000_ERR_EEPROM; | |
8114 | } | |
2d7edb92 MC |
8115 | |
8116 | /* Get the FW semaphore. */ | |
8117 | timeout = hw->eeprom.word_size + 1; | |
8fc897b0 | 8118 | while (timeout) { |
2d7edb92 MC |
8119 | swsm = E1000_READ_REG(hw, SWSM); |
8120 | swsm |= E1000_SWSM_SWESMBI; | |
8121 | E1000_WRITE_REG(hw, SWSM, swsm); | |
8122 | /* if we managed to set the bit we got the semaphore. */ | |
8123 | swsm = E1000_READ_REG(hw, SWSM); | |
8fc897b0 | 8124 | if (swsm & E1000_SWSM_SWESMBI) |
2d7edb92 MC |
8125 | break; |
8126 | ||
8127 | udelay(50); | |
8128 | timeout--; | |
8129 | } | |
8130 | ||
8fc897b0 | 8131 | if (!timeout) { |
2d7edb92 MC |
8132 | /* Release semaphores */ |
8133 | e1000_put_hw_eeprom_semaphore(hw); | |
8134 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | |
8135 | return -E1000_ERR_EEPROM; | |
8136 | } | |
8137 | ||
8138 | return E1000_SUCCESS; | |
8139 | } | |
8140 | ||
8141 | /*************************************************************************** | |
8142 | * This function clears HW semaphore bits. | |
8143 | * | |
8144 | * hw: Struct containing variables accessed by shared code | |
8145 | * | |
8146 | * returns: - None. | |
8147 | * | |
8148 | ***************************************************************************/ | |
3ad2cc67 | 8149 | static void |
2d7edb92 MC |
8150 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
8151 | { | |
8152 | uint32_t swsm; | |
8153 | ||
8154 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | |
8155 | ||
8fc897b0 | 8156 | if (!hw->eeprom_semaphore_present) |
2d7edb92 MC |
8157 | return; |
8158 | ||
8159 | swsm = E1000_READ_REG(hw, SWSM); | |
6418ecc6 JK |
8160 | if (hw->mac_type == e1000_80003es2lan) { |
8161 | /* Release both semaphores. */ | |
8162 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
8163 | } else | |
868d5309 | 8164 | swsm &= ~(E1000_SWSM_SWESMBI); |
2d7edb92 MC |
8165 | E1000_WRITE_REG(hw, SWSM, swsm); |
8166 | } | |
8167 | ||
6418ecc6 JK |
8168 | /*************************************************************************** |
8169 | * | |
8170 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | |
8171 | * | |
8172 | * hw: Struct containing variables accessed by shared code | |
8173 | * | |
8174 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | |
8175 | * E1000_SUCCESS at any other case. | |
8176 | * | |
8177 | ***************************************************************************/ | |
e4c780b1 | 8178 | static int32_t |
6418ecc6 JK |
8179 | e1000_get_software_semaphore(struct e1000_hw *hw) |
8180 | { | |
8181 | int32_t timeout = hw->eeprom.word_size + 1; | |
8182 | uint32_t swsm; | |
8183 | ||
8184 | DEBUGFUNC("e1000_get_software_semaphore"); | |
8185 | ||
35574764 | 8186 | if (hw->mac_type != e1000_80003es2lan) { |
6418ecc6 | 8187 | return E1000_SUCCESS; |
35574764 | 8188 | } |
6418ecc6 | 8189 | |
8fc897b0 | 8190 | while (timeout) { |
6418ecc6 JK |
8191 | swsm = E1000_READ_REG(hw, SWSM); |
8192 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ | |
8fc897b0 | 8193 | if (!(swsm & E1000_SWSM_SMBI)) |
6418ecc6 | 8194 | break; |
f8ec4733 | 8195 | mdelay(1); |
6418ecc6 JK |
8196 | timeout--; |
8197 | } | |
8198 | ||
8fc897b0 | 8199 | if (!timeout) { |
6418ecc6 JK |
8200 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
8201 | return -E1000_ERR_RESET; | |
8202 | } | |
8203 | ||
8204 | return E1000_SUCCESS; | |
8205 | } | |
8206 | ||
8207 | /*************************************************************************** | |
8208 | * | |
8209 | * Release semaphore bit (SMBI). | |
8210 | * | |
8211 | * hw: Struct containing variables accessed by shared code | |
8212 | * | |
8213 | ***************************************************************************/ | |
e4c780b1 | 8214 | static void |
6418ecc6 JK |
8215 | e1000_release_software_semaphore(struct e1000_hw *hw) |
8216 | { | |
8217 | uint32_t swsm; | |
8218 | ||
8219 | DEBUGFUNC("e1000_release_software_semaphore"); | |
8220 | ||
35574764 | 8221 | if (hw->mac_type != e1000_80003es2lan) { |
6418ecc6 | 8222 | return; |
35574764 | 8223 | } |
6418ecc6 JK |
8224 | |
8225 | swsm = E1000_READ_REG(hw, SWSM); | |
8226 | /* Release the SW semaphores.*/ | |
8227 | swsm &= ~E1000_SWSM_SMBI; | |
8228 | E1000_WRITE_REG(hw, SWSM, swsm); | |
8229 | } | |
8230 | ||
2d7edb92 MC |
8231 | /****************************************************************************** |
8232 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
8233 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
8234 | * the caller to figure out how to deal with it. | |
8235 | * | |
8236 | * hw - Struct containing variables accessed by shared code | |
8237 | * | |
8238 | * returns: - E1000_BLK_PHY_RESET | |
8239 | * E1000_SUCCESS | |
8240 | * | |
8241 | *****************************************************************************/ | |
8242 | int32_t | |
8243 | e1000_check_phy_reset_block(struct e1000_hw *hw) | |
8244 | { | |
8245 | uint32_t manc = 0; | |
cd94dd0b AK |
8246 | uint32_t fwsm = 0; |
8247 | ||
8248 | if (hw->mac_type == e1000_ich8lan) { | |
8249 | fwsm = E1000_READ_REG(hw, FWSM); | |
8250 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS | |
8251 | : E1000_BLK_PHY_RESET; | |
8252 | } | |
96838a40 JB |
8253 | |
8254 | if (hw->mac_type > e1000_82547_rev_2) | |
2d7edb92 MC |
8255 | manc = E1000_READ_REG(hw, MANC); |
8256 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
35574764 | 8257 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
2d7edb92 MC |
8258 | } |
8259 | ||
3ad2cc67 | 8260 | static uint8_t |
2d7edb92 MC |
8261 | e1000_arc_subsystem_valid(struct e1000_hw *hw) |
8262 | { | |
8263 | uint32_t fwsm; | |
8264 | ||
8265 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | |
8266 | * may not be provided a DMA clock when no manageability features are | |
8267 | * enabled. We do not want to perform any reads/writes to these registers | |
8268 | * if this is the case. We read FWSM to determine the manageability mode. | |
8269 | */ | |
8270 | switch (hw->mac_type) { | |
868d5309 MC |
8271 | case e1000_82571: |
8272 | case e1000_82572: | |
2d7edb92 | 8273 | case e1000_82573: |
6418ecc6 | 8274 | case e1000_80003es2lan: |
2d7edb92 | 8275 | fwsm = E1000_READ_REG(hw, FWSM); |
8fc897b0 | 8276 | if ((fwsm & E1000_FWSM_MODE_MASK) != 0) |
2d7edb92 MC |
8277 | return TRUE; |
8278 | break; | |
cd94dd0b AK |
8279 | case e1000_ich8lan: |
8280 | return TRUE; | |
2d7edb92 MC |
8281 | default: |
8282 | break; | |
8283 | } | |
8284 | return FALSE; | |
8285 | } | |
8286 | ||
8287 | ||
d37ea5d5 AK |
8288 | /****************************************************************************** |
8289 | * Configure PCI-Ex no-snoop | |
8290 | * | |
8291 | * hw - Struct containing variables accessed by shared code. | |
8292 | * no_snoop - Bitmap of no-snoop events. | |
8293 | * | |
8294 | * returns: E1000_SUCCESS | |
8295 | * | |
8296 | *****************************************************************************/ | |
e4c780b1 | 8297 | static int32_t |
d37ea5d5 AK |
8298 | e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) |
8299 | { | |
8300 | uint32_t gcr_reg = 0; | |
8301 | ||
8302 | DEBUGFUNC("e1000_set_pci_ex_no_snoop"); | |
8303 | ||
8304 | if (hw->bus_type == e1000_bus_type_unknown) | |
8305 | e1000_get_bus_info(hw); | |
8306 | ||
8307 | if (hw->bus_type != e1000_bus_type_pci_express) | |
8308 | return E1000_SUCCESS; | |
8309 | ||
8310 | if (no_snoop) { | |
8311 | gcr_reg = E1000_READ_REG(hw, GCR); | |
8312 | gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); | |
8313 | gcr_reg |= no_snoop; | |
8314 | E1000_WRITE_REG(hw, GCR, gcr_reg); | |
8315 | } | |
8316 | if (hw->mac_type == e1000_ich8lan) { | |
8317 | uint32_t ctrl_ext; | |
8318 | ||
8319 | E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); | |
8320 | ||
8321 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
8322 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
8323 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
8324 | } | |
8325 | ||
8326 | return E1000_SUCCESS; | |
8327 | } | |
8328 | ||
8329 | /*************************************************************************** | |
8330 | * | |
8331 | * Get software semaphore FLAG bit (SWFLAG). | |
8332 | * SWFLAG is used to synchronize the access to all shared resource between | |
8333 | * SW, FW and HW. | |
8334 | * | |
8335 | * hw: Struct containing variables accessed by shared code | |
8336 | * | |
8337 | ***************************************************************************/ | |
e4c780b1 | 8338 | static int32_t |
d37ea5d5 AK |
8339 | e1000_get_software_flag(struct e1000_hw *hw) |
8340 | { | |
8341 | int32_t timeout = PHY_CFG_TIMEOUT; | |
8342 | uint32_t extcnf_ctrl; | |
8343 | ||
8344 | DEBUGFUNC("e1000_get_software_flag"); | |
8345 | ||
8346 | if (hw->mac_type == e1000_ich8lan) { | |
8347 | while (timeout) { | |
8348 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
8349 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
8350 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | |
8351 | ||
8352 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
8353 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
8354 | break; | |
f8ec4733 | 8355 | mdelay(1); |
d37ea5d5 AK |
8356 | timeout--; |
8357 | } | |
8358 | ||
8359 | if (!timeout) { | |
8360 | DEBUGOUT("FW or HW locks the resource too long.\n"); | |
8361 | return -E1000_ERR_CONFIG; | |
8362 | } | |
8363 | } | |
8364 | ||
8365 | return E1000_SUCCESS; | |
8366 | } | |
8367 | ||
8368 | /*************************************************************************** | |
8369 | * | |
8370 | * Release software semaphore FLAG bit (SWFLAG). | |
8371 | * SWFLAG is used to synchronize the access to all shared resource between | |
8372 | * SW, FW and HW. | |
8373 | * | |
8374 | * hw: Struct containing variables accessed by shared code | |
8375 | * | |
8376 | ***************************************************************************/ | |
e4c780b1 | 8377 | static void |
d37ea5d5 AK |
8378 | e1000_release_software_flag(struct e1000_hw *hw) |
8379 | { | |
8380 | uint32_t extcnf_ctrl; | |
8381 | ||
8382 | DEBUGFUNC("e1000_release_software_flag"); | |
8383 | ||
8384 | if (hw->mac_type == e1000_ich8lan) { | |
8385 | extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); | |
8386 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
8387 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | |
8388 | } | |
8389 | ||
8390 | return; | |
8391 | } | |
8392 | ||
d37ea5d5 AK |
8393 | /****************************************************************************** |
8394 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access | |
8395 | * register. | |
8396 | * | |
8397 | * hw - Struct containing variables accessed by shared code | |
8398 | * offset - offset of word in the EEPROM to read | |
8399 | * data - word read from the EEPROM | |
8400 | * words - number of words to read | |
8401 | *****************************************************************************/ | |
e4c780b1 | 8402 | static int32_t |
d37ea5d5 AK |
8403 | e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
8404 | uint16_t *data) | |
8405 | { | |
8406 | int32_t error = E1000_SUCCESS; | |
8407 | uint32_t flash_bank = 0; | |
8408 | uint32_t act_offset = 0; | |
8409 | uint32_t bank_offset = 0; | |
8410 | uint16_t word = 0; | |
8411 | uint16_t i = 0; | |
8412 | ||
8413 | /* We need to know which is the valid flash bank. In the event | |
8414 | * that we didn't allocate eeprom_shadow_ram, we may not be | |
8415 | * managing flash_bank. So it cannot be trusted and needs | |
8416 | * to be updated with each read. | |
8417 | */ | |
8418 | /* Value of bit 22 corresponds to the flash bank we're on. */ | |
8419 | flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; | |
8420 | ||
8421 | /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ | |
8422 | bank_offset = flash_bank * (hw->flash_bank_size * 2); | |
8423 | ||
8424 | error = e1000_get_software_flag(hw); | |
8425 | if (error != E1000_SUCCESS) | |
8426 | return error; | |
8427 | ||
8428 | for (i = 0; i < words; i++) { | |
8429 | if (hw->eeprom_shadow_ram != NULL && | |
8430 | hw->eeprom_shadow_ram[offset+i].modified == TRUE) { | |
8431 | data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; | |
8432 | } else { | |
8433 | /* The NVM part needs a byte offset, hence * 2 */ | |
8434 | act_offset = bank_offset + ((offset + i) * 2); | |
8435 | error = e1000_read_ich8_word(hw, act_offset, &word); | |
8436 | if (error != E1000_SUCCESS) | |
8437 | break; | |
8438 | data[i] = word; | |
8439 | } | |
8440 | } | |
8441 | ||
8442 | e1000_release_software_flag(hw); | |
8443 | ||
8444 | return error; | |
8445 | } | |
8446 | ||
8447 | /****************************************************************************** | |
8448 | * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access | |
8449 | * register. Actually, writes are written to the shadow ram cache in the hw | |
8450 | * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to | |
8451 | * the NVM, which occurs when the NVM checksum is updated. | |
8452 | * | |
8453 | * hw - Struct containing variables accessed by shared code | |
8454 | * offset - offset of word in the EEPROM to write | |
8455 | * words - number of words to write | |
8456 | * data - words to write to the EEPROM | |
8457 | *****************************************************************************/ | |
e4c780b1 | 8458 | static int32_t |
d37ea5d5 AK |
8459 | e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
8460 | uint16_t *data) | |
8461 | { | |
8462 | uint32_t i = 0; | |
8463 | int32_t error = E1000_SUCCESS; | |
8464 | ||
8465 | error = e1000_get_software_flag(hw); | |
8466 | if (error != E1000_SUCCESS) | |
8467 | return error; | |
8468 | ||
8469 | /* A driver can write to the NVM only if it has eeprom_shadow_ram | |
8470 | * allocated. Subsequent reads to the modified words are read from | |
8471 | * this cached structure as well. Writes will only go into this | |
8472 | * cached structure unless it's followed by a call to | |
8473 | * e1000_update_eeprom_checksum() where it will commit the changes | |
8474 | * and clear the "modified" field. | |
8475 | */ | |
8476 | if (hw->eeprom_shadow_ram != NULL) { | |
8477 | for (i = 0; i < words; i++) { | |
8478 | if ((offset + i) < E1000_SHADOW_RAM_WORDS) { | |
8479 | hw->eeprom_shadow_ram[offset+i].modified = TRUE; | |
8480 | hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; | |
8481 | } else { | |
8482 | error = -E1000_ERR_EEPROM; | |
8483 | break; | |
8484 | } | |
8485 | } | |
8486 | } else { | |
8487 | /* Drivers have the option to not allocate eeprom_shadow_ram as long | |
8488 | * as they don't perform any NVM writes. An attempt in doing so | |
8489 | * will result in this error. | |
8490 | */ | |
8491 | error = -E1000_ERR_EEPROM; | |
8492 | } | |
8493 | ||
8494 | e1000_release_software_flag(hw); | |
8495 | ||
8496 | return error; | |
8497 | } | |
8498 | ||
8499 | /****************************************************************************** | |
8500 | * This function does initial flash setup so that a new read/write/erase cycle | |
8501 | * can be started. | |
8502 | * | |
8503 | * hw - The pointer to the hw structure | |
8504 | ****************************************************************************/ | |
e4c780b1 | 8505 | static int32_t |
d37ea5d5 AK |
8506 | e1000_ich8_cycle_init(struct e1000_hw *hw) |
8507 | { | |
8508 | union ich8_hws_flash_status hsfsts; | |
8509 | int32_t error = E1000_ERR_EEPROM; | |
8510 | int32_t i = 0; | |
8511 | ||
8512 | DEBUGFUNC("e1000_ich8_cycle_init"); | |
8513 | ||
2df7d59f | 8514 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8515 | |
8516 | /* May be check the Flash Des Valid bit in Hw status */ | |
8517 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
8518 | DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); | |
8519 | return error; | |
8520 | } | |
8521 | ||
8522 | /* Clear FCERR in Hw status by writing 1 */ | |
8523 | /* Clear DAEL in Hw status by writing a 1 */ | |
8524 | hsfsts.hsf_status.flcerr = 1; | |
8525 | hsfsts.hsf_status.dael = 1; | |
8526 | ||
2df7d59f | 8527 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8528 | |
8529 | /* Either we should have a hardware SPI cycle in progress bit to check | |
8530 | * against, in order to start a new cycle or FDONE bit should be changed | |
8531 | * in the hardware so that it is 1 after harware reset, which can then be | |
8532 | * used as an indication whether a cycle is in progress or has been | |
8533 | * completed .. we should also have some software semaphore mechanism to | |
8534 | * guard FDONE or the cycle in progress bit so that two threads access to | |
8535 | * those bits can be sequentiallized or a way so that 2 threads dont | |
8536 | * start the cycle at the same time */ | |
8537 | ||
8538 | if (hsfsts.hsf_status.flcinprog == 0) { | |
8539 | /* There is no cycle running at present, so we can start a cycle */ | |
8540 | /* Begin by setting Flash Cycle Done. */ | |
8541 | hsfsts.hsf_status.flcdone = 1; | |
2df7d59f | 8542 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8543 | error = E1000_SUCCESS; |
8544 | } else { | |
8545 | /* otherwise poll for sometime so the current cycle has a chance | |
8546 | * to end before giving up. */ | |
2df7d59f JK |
8547 | for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { |
8548 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | |
d37ea5d5 AK |
8549 | if (hsfsts.hsf_status.flcinprog == 0) { |
8550 | error = E1000_SUCCESS; | |
8551 | break; | |
8552 | } | |
8553 | udelay(1); | |
8554 | } | |
8555 | if (error == E1000_SUCCESS) { | |
8556 | /* Successful in waiting for previous cycle to timeout, | |
8557 | * now set the Flash Cycle Done. */ | |
8558 | hsfsts.hsf_status.flcdone = 1; | |
2df7d59f | 8559 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8560 | } else { |
8561 | DEBUGOUT("Flash controller busy, cannot get access"); | |
8562 | } | |
8563 | } | |
8564 | return error; | |
8565 | } | |
8566 | ||
8567 | /****************************************************************************** | |
8568 | * This function starts a flash cycle and waits for its completion | |
8569 | * | |
8570 | * hw - The pointer to the hw structure | |
8571 | ****************************************************************************/ | |
e4c780b1 | 8572 | static int32_t |
d37ea5d5 AK |
8573 | e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) |
8574 | { | |
8575 | union ich8_hws_flash_ctrl hsflctl; | |
8576 | union ich8_hws_flash_status hsfsts; | |
8577 | int32_t error = E1000_ERR_EEPROM; | |
8578 | uint32_t i = 0; | |
8579 | ||
8580 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
2df7d59f | 8581 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 | 8582 | hsflctl.hsf_ctrl.flcgo = 1; |
2df7d59f | 8583 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
d37ea5d5 AK |
8584 | |
8585 | /* wait till FDONE bit is set to 1 */ | |
8586 | do { | |
2df7d59f | 8587 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8588 | if (hsfsts.hsf_status.flcdone == 1) |
8589 | break; | |
8590 | udelay(1); | |
8591 | i++; | |
8592 | } while (i < timeout); | |
8593 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { | |
8594 | error = E1000_SUCCESS; | |
8595 | } | |
8596 | return error; | |
8597 | } | |
8598 | ||
8599 | /****************************************************************************** | |
8600 | * Reads a byte or word from the NVM using the ICH8 flash access registers. | |
8601 | * | |
8602 | * hw - The pointer to the hw structure | |
8603 | * index - The index of the byte or word to read. | |
8604 | * size - Size of data to read, 1=byte 2=word | |
8605 | * data - Pointer to the word to store the value read. | |
8606 | *****************************************************************************/ | |
e4c780b1 | 8607 | static int32_t |
d37ea5d5 AK |
8608 | e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, |
8609 | uint32_t size, uint16_t* data) | |
8610 | { | |
8611 | union ich8_hws_flash_status hsfsts; | |
8612 | union ich8_hws_flash_ctrl hsflctl; | |
8613 | uint32_t flash_linear_address; | |
8614 | uint32_t flash_data = 0; | |
8615 | int32_t error = -E1000_ERR_EEPROM; | |
8616 | int32_t count = 0; | |
8617 | ||
8618 | DEBUGFUNC("e1000_read_ich8_data"); | |
8619 | ||
8620 | if (size < 1 || size > 2 || data == 0x0 || | |
2df7d59f | 8621 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
d37ea5d5 AK |
8622 | return error; |
8623 | ||
2df7d59f | 8624 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
d37ea5d5 AK |
8625 | hw->flash_base_addr; |
8626 | ||
8627 | do { | |
8628 | udelay(1); | |
8629 | /* Steps */ | |
8630 | error = e1000_ich8_cycle_init(hw); | |
8631 | if (error != E1000_SUCCESS) | |
8632 | break; | |
8633 | ||
2df7d59f | 8634 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 AK |
8635 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
8636 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
2df7d59f JK |
8637 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
8638 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8639 | |
8640 | /* Write the last 24 bits of index into Flash Linear address field in | |
8641 | * Flash Address */ | |
8642 | /* TODO: TBD maybe check the index against the size of flash */ | |
8643 | ||
2df7d59f | 8644 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 | 8645 | |
2df7d59f | 8646 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
d37ea5d5 AK |
8647 | |
8648 | /* Check if FCERR is set to 1, if set to 1, clear it and try the whole | |
8649 | * sequence a few more times, else read in (shift in) the Flash Data0, | |
8650 | * the order is least significant byte first msb to lsb */ | |
8651 | if (error == E1000_SUCCESS) { | |
2df7d59f | 8652 | flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); |
d37ea5d5 AK |
8653 | if (size == 1) { |
8654 | *data = (uint8_t)(flash_data & 0x000000FF); | |
8655 | } else if (size == 2) { | |
8656 | *data = (uint16_t)(flash_data & 0x0000FFFF); | |
8657 | } | |
8658 | break; | |
8659 | } else { | |
8660 | /* If we've gotten here, then things are probably completely hosed, | |
8661 | * but if the error condition is detected, it won't hurt to give | |
2df7d59f | 8662 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
d37ea5d5 | 8663 | */ |
2df7d59f | 8664 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8665 | if (hsfsts.hsf_status.flcerr == 1) { |
8666 | /* Repeat for some time before giving up. */ | |
8667 | continue; | |
8668 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8669 | DEBUGOUT("Timeout error - flash cycle did not complete."); | |
8670 | break; | |
8671 | } | |
8672 | } | |
2df7d59f | 8673 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
d37ea5d5 AK |
8674 | |
8675 | return error; | |
8676 | } | |
8677 | ||
8678 | /****************************************************************************** | |
8679 | * Writes One /two bytes to the NVM using the ICH8 flash access registers. | |
8680 | * | |
8681 | * hw - The pointer to the hw structure | |
8682 | * index - The index of the byte/word to read. | |
8683 | * size - Size of data to read, 1=byte 2=word | |
8684 | * data - The byte(s) to write to the NVM. | |
8685 | *****************************************************************************/ | |
e4c780b1 | 8686 | static int32_t |
d37ea5d5 AK |
8687 | e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, |
8688 | uint16_t data) | |
8689 | { | |
8690 | union ich8_hws_flash_status hsfsts; | |
8691 | union ich8_hws_flash_ctrl hsflctl; | |
8692 | uint32_t flash_linear_address; | |
8693 | uint32_t flash_data = 0; | |
8694 | int32_t error = -E1000_ERR_EEPROM; | |
8695 | int32_t count = 0; | |
8696 | ||
8697 | DEBUGFUNC("e1000_write_ich8_data"); | |
8698 | ||
8699 | if (size < 1 || size > 2 || data > size * 0xff || | |
2df7d59f | 8700 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
d37ea5d5 AK |
8701 | return error; |
8702 | ||
2df7d59f | 8703 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
d37ea5d5 AK |
8704 | hw->flash_base_addr; |
8705 | ||
8706 | do { | |
8707 | udelay(1); | |
8708 | /* Steps */ | |
8709 | error = e1000_ich8_cycle_init(hw); | |
8710 | if (error != E1000_SUCCESS) | |
8711 | break; | |
8712 | ||
2df7d59f | 8713 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 AK |
8714 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
8715 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
2df7d59f JK |
8716 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
8717 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8718 | |
8719 | /* Write the last 24 bits of index into Flash Linear address field in | |
8720 | * Flash Address */ | |
2df7d59f | 8721 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 AK |
8722 | |
8723 | if (size == 1) | |
8724 | flash_data = (uint32_t)data & 0x00FF; | |
8725 | else | |
8726 | flash_data = (uint32_t)data; | |
8727 | ||
2df7d59f | 8728 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); |
d37ea5d5 AK |
8729 | |
8730 | /* check if FCERR is set to 1 , if set to 1, clear it and try the whole | |
8731 | * sequence a few more times else done */ | |
2df7d59f | 8732 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
d37ea5d5 AK |
8733 | if (error == E1000_SUCCESS) { |
8734 | break; | |
8735 | } else { | |
8736 | /* If we're here, then things are most likely completely hosed, | |
8737 | * but if the error condition is detected, it won't hurt to give | |
2df7d59f | 8738 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
d37ea5d5 | 8739 | */ |
2df7d59f | 8740 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8741 | if (hsfsts.hsf_status.flcerr == 1) { |
8742 | /* Repeat for some time before giving up. */ | |
8743 | continue; | |
8744 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8745 | DEBUGOUT("Timeout error - flash cycle did not complete."); | |
8746 | break; | |
8747 | } | |
8748 | } | |
2df7d59f | 8749 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
d37ea5d5 AK |
8750 | |
8751 | return error; | |
8752 | } | |
8753 | ||
8754 | /****************************************************************************** | |
8755 | * Reads a single byte from the NVM using the ICH8 flash access registers. | |
8756 | * | |
8757 | * hw - pointer to e1000_hw structure | |
8758 | * index - The index of the byte to read. | |
8759 | * data - Pointer to a byte to store the value read. | |
8760 | *****************************************************************************/ | |
e4c780b1 | 8761 | static int32_t |
d37ea5d5 AK |
8762 | e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) |
8763 | { | |
8764 | int32_t status = E1000_SUCCESS; | |
8765 | uint16_t word = 0; | |
8766 | ||
8767 | status = e1000_read_ich8_data(hw, index, 1, &word); | |
8768 | if (status == E1000_SUCCESS) { | |
8769 | *data = (uint8_t)word; | |
8770 | } | |
8771 | ||
8772 | return status; | |
8773 | } | |
8774 | ||
8775 | /****************************************************************************** | |
8776 | * Writes a single byte to the NVM using the ICH8 flash access registers. | |
8777 | * Performs verification by reading back the value and then going through | |
8778 | * a retry algorithm before giving up. | |
8779 | * | |
8780 | * hw - pointer to e1000_hw structure | |
8781 | * index - The index of the byte to write. | |
8782 | * byte - The byte to write to the NVM. | |
8783 | *****************************************************************************/ | |
e4c780b1 | 8784 | static int32_t |
d37ea5d5 AK |
8785 | e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) |
8786 | { | |
8787 | int32_t error = E1000_SUCCESS; | |
2a88c173 | 8788 | int32_t program_retries = 0; |
d37ea5d5 | 8789 | |
2a88c173 | 8790 | DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); |
d37ea5d5 | 8791 | |
2a88c173 JK |
8792 | error = e1000_write_ich8_byte(hw, index, byte); |
8793 | ||
8794 | if (error != E1000_SUCCESS) { | |
8795 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
8796 | DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); | |
8797 | error = e1000_write_ich8_byte(hw, index, byte); | |
8798 | udelay(100); | |
8799 | if (error == E1000_SUCCESS) | |
8800 | break; | |
8801 | } | |
d37ea5d5 | 8802 | } |
2a88c173 | 8803 | |
d37ea5d5 AK |
8804 | if (program_retries == 100) |
8805 | error = E1000_ERR_EEPROM; | |
8806 | ||
8807 | return error; | |
8808 | } | |
8809 | ||
8810 | /****************************************************************************** | |
8811 | * Writes a single byte to the NVM using the ICH8 flash access registers. | |
8812 | * | |
8813 | * hw - pointer to e1000_hw structure | |
8814 | * index - The index of the byte to read. | |
8815 | * data - The byte to write to the NVM. | |
8816 | *****************************************************************************/ | |
e4c780b1 | 8817 | static int32_t |
d37ea5d5 AK |
8818 | e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) |
8819 | { | |
8820 | int32_t status = E1000_SUCCESS; | |
8821 | uint16_t word = (uint16_t)data; | |
8822 | ||
8823 | status = e1000_write_ich8_data(hw, index, 1, word); | |
8824 | ||
8825 | return status; | |
8826 | } | |
8827 | ||
8828 | /****************************************************************************** | |
8829 | * Reads a word from the NVM using the ICH8 flash access registers. | |
8830 | * | |
8831 | * hw - pointer to e1000_hw structure | |
8832 | * index - The starting byte index of the word to read. | |
8833 | * data - Pointer to a word to store the value read. | |
8834 | *****************************************************************************/ | |
e4c780b1 | 8835 | static int32_t |
d37ea5d5 AK |
8836 | e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) |
8837 | { | |
8838 | int32_t status = E1000_SUCCESS; | |
8839 | status = e1000_read_ich8_data(hw, index, 2, data); | |
8840 | return status; | |
8841 | } | |
8842 | ||
8843 | /****************************************************************************** | |
2a88c173 JK |
8844 | * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 |
8845 | * based. | |
d37ea5d5 AK |
8846 | * |
8847 | * hw - pointer to e1000_hw structure | |
2a88c173 | 8848 | * bank - 0 for first bank, 1 for second bank |
d37ea5d5 | 8849 | * |
2a88c173 JK |
8850 | * Note that this function may actually erase as much as 8 or 64 KBytes. The |
8851 | * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the | |
8852 | * bank size may be 4, 8 or 64 KBytes | |
d37ea5d5 | 8853 | *****************************************************************************/ |
2a88c173 JK |
8854 | int32_t |
8855 | e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) | |
d37ea5d5 AK |
8856 | { |
8857 | union ich8_hws_flash_status hsfsts; | |
8858 | union ich8_hws_flash_ctrl hsflctl; | |
8859 | uint32_t flash_linear_address; | |
8860 | int32_t count = 0; | |
8861 | int32_t error = E1000_ERR_EEPROM; | |
2a88c173 JK |
8862 | int32_t iteration; |
8863 | int32_t sub_sector_size = 0; | |
8864 | int32_t bank_size; | |
d37ea5d5 AK |
8865 | int32_t j = 0; |
8866 | int32_t error_flag = 0; | |
8867 | ||
2df7d59f | 8868 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8869 | |
8870 | /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ | |
8871 | /* 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
8872 | * consecutive sectors. The start index for the nth Hw sector can be | |
2a88c173 | 8873 | * calculated as bank * 4096 + n * 256 |
d37ea5d5 AK |
8874 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
8875 | * The start index for the nth Hw sector can be calculated | |
2a88c173 JK |
8876 | * as bank * 4096 |
8877 | * 10: The HW sector is 8K bytes | |
8878 | * 11: The Hw sector size is 64K bytes */ | |
d37ea5d5 AK |
8879 | if (hsfsts.hsf_status.berasesz == 0x0) { |
8880 | /* Hw sector size 256 */ | |
2df7d59f JK |
8881 | sub_sector_size = ICH_FLASH_SEG_SIZE_256; |
8882 | bank_size = ICH_FLASH_SECTOR_SIZE; | |
8883 | iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; | |
d37ea5d5 | 8884 | } else if (hsfsts.hsf_status.berasesz == 0x1) { |
2df7d59f | 8885 | bank_size = ICH_FLASH_SEG_SIZE_4K; |
d37ea5d5 AK |
8886 | iteration = 1; |
8887 | } else if (hsfsts.hsf_status.berasesz == 0x3) { | |
2df7d59f | 8888 | bank_size = ICH_FLASH_SEG_SIZE_64K; |
d37ea5d5 AK |
8889 | iteration = 1; |
8890 | } else { | |
8891 | return error; | |
8892 | } | |
8893 | ||
8894 | for (j = 0; j < iteration ; j++) { | |
8895 | do { | |
8896 | count++; | |
8897 | /* Steps */ | |
8898 | error = e1000_ich8_cycle_init(hw); | |
8899 | if (error != E1000_SUCCESS) { | |
8900 | error_flag = 1; | |
8901 | break; | |
8902 | } | |
8903 | ||
8904 | /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash | |
8905 | * Control */ | |
2df7d59f JK |
8906 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
8907 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
8908 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8909 | |
8910 | /* Write the last 24 bits of an index within the block into Flash | |
8911 | * Linear address field in Flash Address. This probably needs to | |
2a88c173 JK |
8912 | * be calculated here based off the on-chip erase sector size and |
8913 | * the software bank size (4, 8 or 64 KBytes) */ | |
8914 | flash_linear_address = bank * bank_size + j * sub_sector_size; | |
d37ea5d5 | 8915 | flash_linear_address += hw->flash_base_addr; |
2df7d59f | 8916 | flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; |
d37ea5d5 | 8917 | |
2df7d59f | 8918 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 | 8919 | |
2df7d59f | 8920 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); |
d37ea5d5 AK |
8921 | /* Check if FCERR is set to 1. If 1, clear it and try the whole |
8922 | * sequence a few more times else Done */ | |
8923 | if (error == E1000_SUCCESS) { | |
8924 | break; | |
8925 | } else { | |
2df7d59f | 8926 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8927 | if (hsfsts.hsf_status.flcerr == 1) { |
8928 | /* repeat for some time before giving up */ | |
8929 | continue; | |
8930 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8931 | error_flag = 1; | |
8932 | break; | |
8933 | } | |
8934 | } | |
2df7d59f | 8935 | } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); |
d37ea5d5 AK |
8936 | if (error_flag == 1) |
8937 | break; | |
8938 | } | |
8939 | if (error_flag != 1) | |
8940 | error = E1000_SUCCESS; | |
8941 | return error; | |
8942 | } | |
8943 | ||
e4c780b1 | 8944 | static int32_t |
d37ea5d5 AK |
8945 | e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
8946 | uint32_t cnf_base_addr, uint32_t cnf_size) | |
8947 | { | |
8948 | uint32_t ret_val = E1000_SUCCESS; | |
8949 | uint16_t word_addr, reg_data, reg_addr; | |
8950 | uint16_t i; | |
8951 | ||
8952 | /* cnf_base_addr is in DWORD */ | |
8953 | word_addr = (uint16_t)(cnf_base_addr << 1); | |
8954 | ||
8955 | /* cnf_size is returned in size of dwords */ | |
8956 | for (i = 0; i < cnf_size; i++) { | |
8957 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); | |
8958 | if (ret_val) | |
8959 | return ret_val; | |
8960 | ||
8961 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); | |
8962 | if (ret_val) | |
8963 | return ret_val; | |
8964 | ||
8965 | ret_val = e1000_get_software_flag(hw); | |
8966 | if (ret_val != E1000_SUCCESS) | |
8967 | return ret_val; | |
8968 | ||
8969 | ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); | |
8970 | ||
8971 | e1000_release_software_flag(hw); | |
8972 | } | |
8973 | ||
8974 | return ret_val; | |
8975 | } | |
8976 | ||
8977 | ||
2a88c173 JK |
8978 | /****************************************************************************** |
8979 | * This function initializes the PHY from the NVM on ICH8 platforms. This | |
8980 | * is needed due to an issue where the NVM configuration is not properly | |
8981 | * autoloaded after power transitions. Therefore, after each PHY reset, we | |
8982 | * will load the configuration data out of the NVM manually. | |
8983 | * | |
8984 | * hw: Struct containing variables accessed by shared code | |
8985 | *****************************************************************************/ | |
e4c780b1 | 8986 | static int32_t |
d37ea5d5 AK |
8987 | e1000_init_lcd_from_nvm(struct e1000_hw *hw) |
8988 | { | |
8989 | uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; | |
8990 | ||
8991 | if (hw->phy_type != e1000_phy_igp_3) | |
8992 | return E1000_SUCCESS; | |
8993 | ||
8994 | /* Check if SW needs configure the PHY */ | |
8995 | reg_data = E1000_READ_REG(hw, FEXTNVM); | |
8996 | if (!(reg_data & FEXTNVM_SW_CONFIG)) | |
8997 | return E1000_SUCCESS; | |
8998 | ||
8999 | /* Wait for basic configuration completes before proceeding*/ | |
9000 | loop = 0; | |
9001 | do { | |
9002 | reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; | |
9003 | udelay(100); | |
9004 | loop++; | |
9005 | } while ((!reg_data) && (loop < 50)); | |
9006 | ||
9007 | /* Clear the Init Done bit for the next init event */ | |
9008 | reg_data = E1000_READ_REG(hw, STATUS); | |
9009 | reg_data &= ~E1000_STATUS_LAN_INIT_DONE; | |
9010 | E1000_WRITE_REG(hw, STATUS, reg_data); | |
9011 | ||
9012 | /* Make sure HW does not configure LCD from PHY extended configuration | |
9013 | before SW configuration */ | |
9014 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); | |
9015 | if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { | |
9016 | reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); | |
9017 | cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; | |
9018 | cnf_size >>= 16; | |
9019 | if (cnf_size) { | |
9020 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); | |
9021 | cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; | |
9022 | /* cnf_base_addr is in DWORD */ | |
9023 | cnf_base_addr >>= 16; | |
9024 | ||
9025 | /* Configure LCD from extended configuration region. */ | |
9026 | ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, | |
9027 | cnf_size); | |
9028 | if (ret_val) | |
9029 | return ret_val; | |
9030 | } | |
9031 | } | |
9032 | ||
9033 | return E1000_SUCCESS; | |
9034 | } | |
9035 |