Commit | Line | Data |
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1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
0abb6eb1 AK |
3 | Intel PRO/1000 Linux driver |
4 | Copyright(c) 1999 - 2006 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
1da177e4 | 13 | more details. |
0abb6eb1 | 14 | |
1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
1da177e4 LT |
22 | Contact Information: |
23 | Linux NICS <linux.nics@intel.com> | |
3d41e30a | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* e1000_hw.c | |
30 | * Shared functions for accessing and configuring the MAC | |
31 | */ | |
32 | ||
8fc897b0 | 33 | |
1da177e4 LT |
34 | #include "e1000_hw.h" |
35 | ||
406874a7 JP |
36 | static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask); |
37 | static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask); | |
38 | static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data); | |
39 | static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); | |
40 | static s32 e1000_get_software_semaphore(struct e1000_hw *hw); | |
35574764 NN |
41 | static void e1000_release_software_semaphore(struct e1000_hw *hw); |
42 | ||
406874a7 JP |
43 | static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw); |
44 | static s32 e1000_check_downshift(struct e1000_hw *hw); | |
64798845 JP |
45 | static s32 e1000_check_polarity(struct e1000_hw *hw, |
46 | e1000_rev_polarity *polarity); | |
35574764 NN |
47 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
48 | static void e1000_clear_vfta(struct e1000_hw *hw); | |
406874a7 JP |
49 | static s32 e1000_commit_shadow_ram(struct e1000_hw *hw); |
50 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |
64798845 | 51 | bool link_up); |
406874a7 JP |
52 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); |
53 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw); | |
54 | static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank); | |
55 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); | |
64798845 JP |
56 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
57 | u16 *max_length); | |
406874a7 JP |
58 | static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
59 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
60 | static s32 e1000_get_software_flag(struct e1000_hw *hw); | |
61 | static s32 e1000_ich8_cycle_init(struct e1000_hw *hw); | |
62 | static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout); | |
63 | static s32 e1000_id_led_init(struct e1000_hw *hw); | |
64798845 JP |
64 | static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
65 | u32 cnf_base_addr, | |
66 | u32 cnf_size); | |
406874a7 | 67 | static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw); |
35574764 | 68 | static void e1000_init_rx_addrs(struct e1000_hw *hw); |
09ae3e88 | 69 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw); |
c3033b01 | 70 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
406874a7 JP |
71 | static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); |
72 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw); | |
64798845 JP |
73 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, |
74 | u16 offset, u8 *sum); | |
75 | static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, | |
76 | struct e1000_host_mng_command_header | |
77 | *hdr); | |
406874a7 | 78 | static s32 e1000_mng_write_commit(struct e1000_hw *hw); |
64798845 JP |
79 | static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, |
80 | struct e1000_phy_info *phy_info); | |
81 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, | |
82 | struct e1000_phy_info *phy_info); | |
83 | static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, | |
84 | u16 *data); | |
85 | static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, | |
86 | u16 *data); | |
406874a7 | 87 | static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); |
64798845 JP |
88 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
89 | struct e1000_phy_info *phy_info); | |
35574764 | 90 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
406874a7 | 91 | static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data); |
64798845 JP |
92 | static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, |
93 | u8 byte); | |
406874a7 JP |
94 | static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); |
95 | static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data); | |
64798845 JP |
96 | static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, |
97 | u16 *data); | |
98 | static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, | |
99 | u16 data); | |
100 | static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | |
101 | u16 *data); | |
102 | static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | |
103 | u16 *data); | |
35574764 | 104 | static void e1000_release_software_flag(struct e1000_hw *hw); |
406874a7 JP |
105 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
106 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | |
107 | static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop); | |
35574764 | 108 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); |
406874a7 JP |
109 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
110 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); | |
111 | static s32 e1000_set_phy_type(struct e1000_hw *hw); | |
1da177e4 | 112 | static void e1000_phy_init_script(struct e1000_hw *hw); |
406874a7 JP |
113 | static s32 e1000_setup_copper_link(struct e1000_hw *hw); |
114 | static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); | |
115 | static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); | |
116 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
117 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); | |
118 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); | |
119 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); | |
120 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, | |
64798845 | 121 | u16 count); |
406874a7 JP |
122 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
123 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); | |
124 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, | |
125 | u16 words, u16 *data); | |
64798845 JP |
126 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
127 | u16 words, u16 *data); | |
406874a7 JP |
128 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); |
129 | static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); | |
130 | static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); | |
64798845 | 131 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); |
406874a7 | 132 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
64798845 | 133 | u16 phy_data); |
406874a7 | 134 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, |
64798845 | 135 | u16 *phy_data); |
406874a7 JP |
136 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); |
137 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw); | |
1da177e4 LT |
138 | static void e1000_release_eeprom(struct e1000_hw *hw); |
139 | static void e1000_standby_eeprom(struct e1000_hw *hw); | |
406874a7 JP |
140 | static s32 e1000_set_vco_speed(struct e1000_hw *hw); |
141 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); | |
142 | static s32 e1000_set_phy_mode(struct e1000_hw *hw); | |
143 | static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); | |
144 | static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); | |
64798845 | 145 | static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex); |
406874a7 | 146 | static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
78566fec CL |
147 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); |
148 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); | |
1da177e4 LT |
149 | |
150 | /* IGP cable length table */ | |
151 | static const | |
406874a7 | 152 | u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
1da177e4 LT |
153 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
154 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, | |
155 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, | |
156 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, | |
157 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, | |
158 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, | |
159 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | |
160 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | |
161 | ||
2d7edb92 | 162 | static const |
406874a7 | 163 | u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
868d5309 MC |
164 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
165 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
166 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
167 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
168 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
169 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
170 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
171 | 104, 109, 114, 118, 121, 124}; | |
2d7edb92 | 172 | |
78566fec CL |
173 | static DEFINE_SPINLOCK(e1000_eeprom_lock); |
174 | ||
1da177e4 LT |
175 | /****************************************************************************** |
176 | * Set the phy type member in the hw struct. | |
177 | * | |
178 | * hw - Struct containing variables accessed by shared code | |
179 | *****************************************************************************/ | |
64798845 | 180 | static s32 e1000_set_phy_type(struct e1000_hw *hw) |
1da177e4 LT |
181 | { |
182 | DEBUGFUNC("e1000_set_phy_type"); | |
183 | ||
8fc897b0 | 184 | if (hw->mac_type == e1000_undefined) |
2d7edb92 MC |
185 | return -E1000_ERR_PHY_TYPE; |
186 | ||
8fc897b0 | 187 | switch (hw->phy_id) { |
1da177e4 LT |
188 | case M88E1000_E_PHY_ID: |
189 | case M88E1000_I_PHY_ID: | |
190 | case M88E1011_I_PHY_ID: | |
2d7edb92 | 191 | case M88E1111_I_PHY_ID: |
1da177e4 LT |
192 | hw->phy_type = e1000_phy_m88; |
193 | break; | |
194 | case IGP01E1000_I_PHY_ID: | |
8fc897b0 AK |
195 | if (hw->mac_type == e1000_82541 || |
196 | hw->mac_type == e1000_82541_rev_2 || | |
197 | hw->mac_type == e1000_82547 || | |
198 | hw->mac_type == e1000_82547_rev_2) { | |
1da177e4 LT |
199 | hw->phy_type = e1000_phy_igp; |
200 | break; | |
201 | } | |
cd94dd0b AK |
202 | case IGP03E1000_E_PHY_ID: |
203 | hw->phy_type = e1000_phy_igp_3; | |
204 | break; | |
205 | case IFE_E_PHY_ID: | |
206 | case IFE_PLUS_E_PHY_ID: | |
207 | case IFE_C_E_PHY_ID: | |
208 | hw->phy_type = e1000_phy_ife; | |
209 | break; | |
6418ecc6 JK |
210 | case GG82563_E_PHY_ID: |
211 | if (hw->mac_type == e1000_80003es2lan) { | |
212 | hw->phy_type = e1000_phy_gg82563; | |
213 | break; | |
214 | } | |
1da177e4 LT |
215 | /* Fall Through */ |
216 | default: | |
217 | /* Should never have loaded on this device */ | |
218 | hw->phy_type = e1000_phy_undefined; | |
219 | return -E1000_ERR_PHY_TYPE; | |
220 | } | |
221 | ||
222 | return E1000_SUCCESS; | |
223 | } | |
224 | ||
225 | /****************************************************************************** | |
226 | * IGP phy init script - initializes the GbE PHY | |
227 | * | |
228 | * hw - Struct containing variables accessed by shared code | |
229 | *****************************************************************************/ | |
64798845 | 230 | static void e1000_phy_init_script(struct e1000_hw *hw) |
1da177e4 | 231 | { |
406874a7 JP |
232 | u32 ret_val; |
233 | u16 phy_saved_data; | |
1da177e4 LT |
234 | |
235 | DEBUGFUNC("e1000_phy_init_script"); | |
236 | ||
8fc897b0 | 237 | if (hw->phy_init_script) { |
f8ec4733 | 238 | msleep(20); |
1da177e4 LT |
239 | |
240 | /* Save off the current value of register 0x2F5B to be restored at | |
241 | * the end of this routine. */ | |
242 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
243 | ||
244 | /* Disabled the PHY transmitter */ | |
245 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
246 | ||
f8ec4733 | 247 | msleep(20); |
1da177e4 LT |
248 | |
249 | e1000_write_phy_reg(hw,0x0000,0x0140); | |
250 | ||
f8ec4733 | 251 | msleep(5); |
1da177e4 | 252 | |
8fc897b0 | 253 | switch (hw->mac_type) { |
1da177e4 LT |
254 | case e1000_82541: |
255 | case e1000_82547: | |
256 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
257 | ||
258 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
259 | ||
260 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
261 | ||
262 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
263 | ||
264 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
265 | ||
266 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
267 | ||
268 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
269 | ||
270 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
271 | ||
272 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
273 | break; | |
274 | ||
275 | case e1000_82541_rev_2: | |
276 | case e1000_82547_rev_2: | |
277 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
278 | break; | |
279 | default: | |
280 | break; | |
281 | } | |
282 | ||
283 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
284 | ||
f8ec4733 | 285 | msleep(20); |
1da177e4 LT |
286 | |
287 | /* Now enable the transmitter */ | |
288 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
289 | ||
8fc897b0 | 290 | if (hw->mac_type == e1000_82547) { |
406874a7 | 291 | u16 fused, fine, coarse; |
1da177e4 LT |
292 | |
293 | /* Move to analog registers page */ | |
294 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
295 | ||
8fc897b0 | 296 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
1da177e4 LT |
297 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
298 | ||
299 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
300 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
301 | ||
8fc897b0 | 302 | if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
1da177e4 LT |
303 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
304 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
8fc897b0 | 305 | } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
1da177e4 LT |
306 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
307 | ||
308 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
309 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
310 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
311 | ||
312 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
313 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, | |
314 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
315 | } | |
316 | } | |
317 | } | |
318 | } | |
319 | ||
320 | /****************************************************************************** | |
321 | * Set the mac type member in the hw struct. | |
322 | * | |
323 | * hw - Struct containing variables accessed by shared code | |
324 | *****************************************************************************/ | |
64798845 | 325 | s32 e1000_set_mac_type(struct e1000_hw *hw) |
1da177e4 | 326 | { |
bd2371eb JG |
327 | DEBUGFUNC("e1000_set_mac_type"); |
328 | ||
329 | switch (hw->device_id) { | |
330 | case E1000_DEV_ID_82542: | |
331 | switch (hw->revision_id) { | |
332 | case E1000_82542_2_0_REV_ID: | |
333 | hw->mac_type = e1000_82542_rev2_0; | |
334 | break; | |
335 | case E1000_82542_2_1_REV_ID: | |
336 | hw->mac_type = e1000_82542_rev2_1; | |
337 | break; | |
338 | default: | |
339 | /* Invalid 82542 revision ID */ | |
340 | return -E1000_ERR_MAC_TYPE; | |
341 | } | |
342 | break; | |
343 | case E1000_DEV_ID_82543GC_FIBER: | |
344 | case E1000_DEV_ID_82543GC_COPPER: | |
345 | hw->mac_type = e1000_82543; | |
346 | break; | |
347 | case E1000_DEV_ID_82544EI_COPPER: | |
348 | case E1000_DEV_ID_82544EI_FIBER: | |
349 | case E1000_DEV_ID_82544GC_COPPER: | |
350 | case E1000_DEV_ID_82544GC_LOM: | |
351 | hw->mac_type = e1000_82544; | |
352 | break; | |
353 | case E1000_DEV_ID_82540EM: | |
354 | case E1000_DEV_ID_82540EM_LOM: | |
355 | case E1000_DEV_ID_82540EP: | |
356 | case E1000_DEV_ID_82540EP_LOM: | |
357 | case E1000_DEV_ID_82540EP_LP: | |
358 | hw->mac_type = e1000_82540; | |
359 | break; | |
360 | case E1000_DEV_ID_82545EM_COPPER: | |
361 | case E1000_DEV_ID_82545EM_FIBER: | |
362 | hw->mac_type = e1000_82545; | |
363 | break; | |
364 | case E1000_DEV_ID_82545GM_COPPER: | |
365 | case E1000_DEV_ID_82545GM_FIBER: | |
366 | case E1000_DEV_ID_82545GM_SERDES: | |
367 | hw->mac_type = e1000_82545_rev_3; | |
368 | break; | |
369 | case E1000_DEV_ID_82546EB_COPPER: | |
370 | case E1000_DEV_ID_82546EB_FIBER: | |
371 | case E1000_DEV_ID_82546EB_QUAD_COPPER: | |
372 | hw->mac_type = e1000_82546; | |
373 | break; | |
374 | case E1000_DEV_ID_82546GB_COPPER: | |
375 | case E1000_DEV_ID_82546GB_FIBER: | |
376 | case E1000_DEV_ID_82546GB_SERDES: | |
377 | case E1000_DEV_ID_82546GB_PCIE: | |
378 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | |
379 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | |
380 | hw->mac_type = e1000_82546_rev_3; | |
381 | break; | |
382 | case E1000_DEV_ID_82541EI: | |
383 | case E1000_DEV_ID_82541EI_MOBILE: | |
384 | case E1000_DEV_ID_82541ER_LOM: | |
385 | hw->mac_type = e1000_82541; | |
386 | break; | |
387 | case E1000_DEV_ID_82541ER: | |
388 | case E1000_DEV_ID_82541GI: | |
389 | case E1000_DEV_ID_82541GI_LF: | |
390 | case E1000_DEV_ID_82541GI_MOBILE: | |
391 | hw->mac_type = e1000_82541_rev_2; | |
392 | break; | |
393 | case E1000_DEV_ID_82547EI: | |
394 | case E1000_DEV_ID_82547EI_MOBILE: | |
395 | hw->mac_type = e1000_82547; | |
396 | break; | |
397 | case E1000_DEV_ID_82547GI: | |
398 | hw->mac_type = e1000_82547_rev_2; | |
399 | break; | |
400 | case E1000_DEV_ID_82571EB_COPPER: | |
401 | case E1000_DEV_ID_82571EB_FIBER: | |
402 | case E1000_DEV_ID_82571EB_SERDES: | |
ce57a02c AK |
403 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
404 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
bd2371eb | 405 | case E1000_DEV_ID_82571EB_QUAD_COPPER: |
f4ec7f98 | 406 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
ce57a02c | 407 | case E1000_DEV_ID_82571EB_QUAD_FIBER: |
bd2371eb JG |
408 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: |
409 | hw->mac_type = e1000_82571; | |
410 | break; | |
411 | case E1000_DEV_ID_82572EI_COPPER: | |
412 | case E1000_DEV_ID_82572EI_FIBER: | |
413 | case E1000_DEV_ID_82572EI_SERDES: | |
414 | case E1000_DEV_ID_82572EI: | |
415 | hw->mac_type = e1000_82572; | |
416 | break; | |
417 | case E1000_DEV_ID_82573E: | |
418 | case E1000_DEV_ID_82573E_IAMT: | |
419 | case E1000_DEV_ID_82573L: | |
420 | hw->mac_type = e1000_82573; | |
421 | break; | |
422 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: | |
423 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: | |
424 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: | |
425 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
426 | hw->mac_type = e1000_80003es2lan; | |
427 | break; | |
428 | case E1000_DEV_ID_ICH8_IGP_M_AMT: | |
429 | case E1000_DEV_ID_ICH8_IGP_AMT: | |
430 | case E1000_DEV_ID_ICH8_IGP_C: | |
431 | case E1000_DEV_ID_ICH8_IFE: | |
432 | case E1000_DEV_ID_ICH8_IFE_GT: | |
433 | case E1000_DEV_ID_ICH8_IFE_G: | |
434 | case E1000_DEV_ID_ICH8_IGP_M: | |
435 | hw->mac_type = e1000_ich8lan; | |
436 | break; | |
437 | default: | |
438 | /* Should never have loaded on this device */ | |
439 | return -E1000_ERR_MAC_TYPE; | |
440 | } | |
441 | ||
442 | switch (hw->mac_type) { | |
443 | case e1000_ich8lan: | |
c3033b01 JP |
444 | hw->swfwhw_semaphore_present = true; |
445 | hw->asf_firmware_present = true; | |
bd2371eb JG |
446 | break; |
447 | case e1000_80003es2lan: | |
c3033b01 | 448 | hw->swfw_sync_present = true; |
bd2371eb JG |
449 | /* fall through */ |
450 | case e1000_82571: | |
451 | case e1000_82572: | |
452 | case e1000_82573: | |
c3033b01 | 453 | hw->eeprom_semaphore_present = true; |
bd2371eb JG |
454 | /* fall through */ |
455 | case e1000_82541: | |
456 | case e1000_82547: | |
457 | case e1000_82541_rev_2: | |
458 | case e1000_82547_rev_2: | |
c3033b01 | 459 | hw->asf_firmware_present = true; |
bd2371eb JG |
460 | break; |
461 | default: | |
462 | break; | |
463 | } | |
464 | ||
167fb284 JG |
465 | /* The 82543 chip does not count tx_carrier_errors properly in |
466 | * FD mode | |
467 | */ | |
468 | if (hw->mac_type == e1000_82543) | |
c3033b01 | 469 | hw->bad_tx_carr_stats_fd = true; |
167fb284 | 470 | |
0fccd0e9 JG |
471 | /* capable of receiving management packets to the host */ |
472 | if (hw->mac_type >= e1000_82571) | |
c3033b01 | 473 | hw->has_manc2h = true; |
0fccd0e9 | 474 | |
bb8e3311 JG |
475 | /* In rare occasions, ESB2 systems would end up started without |
476 | * the RX unit being turned on. | |
477 | */ | |
478 | if (hw->mac_type == e1000_80003es2lan) | |
c3033b01 | 479 | hw->rx_needs_kicking = true; |
15e376b4 JG |
480 | |
481 | if (hw->mac_type > e1000_82544) | |
c3033b01 | 482 | hw->has_smbus = true; |
bb8e3311 | 483 | |
bd2371eb | 484 | return E1000_SUCCESS; |
1da177e4 LT |
485 | } |
486 | ||
487 | /***************************************************************************** | |
488 | * Set media type and TBI compatibility. | |
489 | * | |
490 | * hw - Struct containing variables accessed by shared code | |
491 | * **************************************************************************/ | |
64798845 | 492 | void e1000_set_media_type(struct e1000_hw *hw) |
1da177e4 | 493 | { |
406874a7 | 494 | u32 status; |
1da177e4 LT |
495 | |
496 | DEBUGFUNC("e1000_set_media_type"); | |
497 | ||
8fc897b0 | 498 | if (hw->mac_type != e1000_82543) { |
1da177e4 | 499 | /* tbi_compatibility is only valid on 82543 */ |
c3033b01 | 500 | hw->tbi_compatibility_en = false; |
1da177e4 LT |
501 | } |
502 | ||
503 | switch (hw->device_id) { | |
504 | case E1000_DEV_ID_82545GM_SERDES: | |
505 | case E1000_DEV_ID_82546GB_SERDES: | |
868d5309 | 506 | case E1000_DEV_ID_82571EB_SERDES: |
ce57a02c AK |
507 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
508 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
868d5309 | 509 | case E1000_DEV_ID_82572EI_SERDES: |
6418ecc6 | 510 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
1da177e4 LT |
511 | hw->media_type = e1000_media_type_internal_serdes; |
512 | break; | |
513 | default: | |
3893d547 MC |
514 | switch (hw->mac_type) { |
515 | case e1000_82542_rev2_0: | |
516 | case e1000_82542_rev2_1: | |
517 | hw->media_type = e1000_media_type_fiber; | |
518 | break; | |
cd94dd0b | 519 | case e1000_ich8lan: |
3893d547 MC |
520 | case e1000_82573: |
521 | /* The STATUS_TBIMODE bit is reserved or reused for the this | |
522 | * device. | |
523 | */ | |
524 | hw->media_type = e1000_media_type_copper; | |
525 | break; | |
526 | default: | |
1dc32918 | 527 | status = er32(STATUS); |
3893d547 | 528 | if (status & E1000_STATUS_TBIMODE) { |
1da177e4 LT |
529 | hw->media_type = e1000_media_type_fiber; |
530 | /* tbi_compatibility not valid on fiber */ | |
c3033b01 | 531 | hw->tbi_compatibility_en = false; |
1da177e4 LT |
532 | } else { |
533 | hw->media_type = e1000_media_type_copper; | |
534 | } | |
3893d547 | 535 | break; |
1da177e4 LT |
536 | } |
537 | } | |
538 | } | |
539 | ||
540 | /****************************************************************************** | |
541 | * Reset the transmit and receive units; mask and clear all interrupts. | |
542 | * | |
543 | * hw - Struct containing variables accessed by shared code | |
544 | *****************************************************************************/ | |
64798845 | 545 | s32 e1000_reset_hw(struct e1000_hw *hw) |
1da177e4 | 546 | { |
406874a7 JP |
547 | u32 ctrl; |
548 | u32 ctrl_ext; | |
549 | u32 icr; | |
550 | u32 manc; | |
551 | u32 led_ctrl; | |
552 | u32 timeout; | |
553 | u32 extcnf_ctrl; | |
554 | s32 ret_val; | |
1da177e4 LT |
555 | |
556 | DEBUGFUNC("e1000_reset_hw"); | |
557 | ||
558 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ | |
8fc897b0 | 559 | if (hw->mac_type == e1000_82542_rev2_0) { |
1da177e4 LT |
560 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
561 | e1000_pci_clear_mwi(hw); | |
562 | } | |
563 | ||
8fc897b0 | 564 | if (hw->bus_type == e1000_bus_type_pci_express) { |
2d7edb92 MC |
565 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
566 | * on the last TLP read/write transaction when MAC is reset. | |
567 | */ | |
8fc897b0 | 568 | if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
2d7edb92 MC |
569 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
570 | } | |
571 | } | |
572 | ||
1da177e4 LT |
573 | /* Clear interrupt mask to stop board from generating interrupts */ |
574 | DEBUGOUT("Masking off all interrupts\n"); | |
1dc32918 | 575 | ew32(IMC, 0xffffffff); |
1da177e4 LT |
576 | |
577 | /* Disable the Transmit and Receive units. Then delay to allow | |
578 | * any pending transactions to complete before we hit the MAC with | |
579 | * the global reset. | |
580 | */ | |
1dc32918 JP |
581 | ew32(RCTL, 0); |
582 | ew32(TCTL, E1000_TCTL_PSP); | |
583 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
584 | |
585 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
c3033b01 | 586 | hw->tbi_compatibility_on = false; |
1da177e4 LT |
587 | |
588 | /* Delay to allow any outstanding PCI transactions to complete before | |
589 | * resetting the device | |
590 | */ | |
f8ec4733 | 591 | msleep(10); |
1da177e4 | 592 | |
1dc32918 | 593 | ctrl = er32(CTRL); |
1da177e4 LT |
594 | |
595 | /* Must reset the PHY before resetting the MAC */ | |
8fc897b0 | 596 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1dc32918 | 597 | ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
f8ec4733 | 598 | msleep(5); |
1da177e4 LT |
599 | } |
600 | ||
2d7edb92 MC |
601 | /* Must acquire the MDIO ownership before MAC reset. |
602 | * Ownership defaults to firmware after a reset. */ | |
8fc897b0 | 603 | if (hw->mac_type == e1000_82573) { |
2d7edb92 MC |
604 | timeout = 10; |
605 | ||
1dc32918 | 606 | extcnf_ctrl = er32(EXTCNF_CTRL); |
2d7edb92 MC |
607 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
608 | ||
609 | do { | |
1dc32918 JP |
610 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
611 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
2d7edb92 | 612 | |
8fc897b0 | 613 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
2d7edb92 MC |
614 | break; |
615 | else | |
616 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
617 | ||
f8ec4733 | 618 | msleep(2); |
2d7edb92 | 619 | timeout--; |
8fc897b0 | 620 | } while (timeout); |
2d7edb92 MC |
621 | } |
622 | ||
cd94dd0b AK |
623 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
624 | if (hw->mac_type == e1000_ich8lan) { | |
625 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
1dc32918 | 626 | ew32(PBA, E1000_PBA_8K); |
cd94dd0b | 627 | /* Set Packet Buffer Size to 16k. */ |
1dc32918 | 628 | ew32(PBS, E1000_PBS_16K); |
cd94dd0b AK |
629 | } |
630 | ||
1da177e4 LT |
631 | /* Issue a global reset to the MAC. This will reset the chip's |
632 | * transmit, receive, DMA, and link units. It will not effect | |
633 | * the current PCI configuration. The global reset bit is self- | |
634 | * clearing, and should clear within a microsecond. | |
635 | */ | |
636 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
637 | ||
8fc897b0 | 638 | switch (hw->mac_type) { |
1da177e4 LT |
639 | case e1000_82544: |
640 | case e1000_82540: | |
641 | case e1000_82545: | |
642 | case e1000_82546: | |
643 | case e1000_82541: | |
644 | case e1000_82541_rev_2: | |
645 | /* These controllers can't ack the 64-bit write when issuing the | |
646 | * reset, so use IO-mapping as a workaround to issue the reset */ | |
647 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
648 | break; | |
649 | case e1000_82545_rev_3: | |
650 | case e1000_82546_rev_3: | |
651 | /* Reset is performed on a shadow of the control register */ | |
1dc32918 | 652 | ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
1da177e4 | 653 | break; |
cd94dd0b AK |
654 | case e1000_ich8lan: |
655 | if (!hw->phy_reset_disable && | |
656 | e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { | |
657 | /* e1000_ich8lan PHY HW reset requires MAC CORE reset | |
658 | * at the same time to make sure the interface between | |
659 | * MAC and the external PHY is reset. | |
660 | */ | |
661 | ctrl |= E1000_CTRL_PHY_RST; | |
662 | } | |
663 | ||
664 | e1000_get_software_flag(hw); | |
1dc32918 | 665 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
f8ec4733 | 666 | msleep(5); |
cd94dd0b | 667 | break; |
1da177e4 | 668 | default: |
1dc32918 | 669 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
1da177e4 LT |
670 | break; |
671 | } | |
672 | ||
673 | /* After MAC reset, force reload of EEPROM to restore power-on settings to | |
674 | * device. Later controllers reload the EEPROM automatically, so just wait | |
675 | * for reload to complete. | |
676 | */ | |
8fc897b0 | 677 | switch (hw->mac_type) { |
1da177e4 LT |
678 | case e1000_82542_rev2_0: |
679 | case e1000_82542_rev2_1: | |
680 | case e1000_82543: | |
681 | case e1000_82544: | |
682 | /* Wait for reset to complete */ | |
683 | udelay(10); | |
1dc32918 | 684 | ctrl_ext = er32(CTRL_EXT); |
1da177e4 | 685 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
1dc32918 JP |
686 | ew32(CTRL_EXT, ctrl_ext); |
687 | E1000_WRITE_FLUSH(); | |
1da177e4 | 688 | /* Wait for EEPROM reload */ |
f8ec4733 | 689 | msleep(2); |
1da177e4 LT |
690 | break; |
691 | case e1000_82541: | |
692 | case e1000_82541_rev_2: | |
693 | case e1000_82547: | |
694 | case e1000_82547_rev_2: | |
695 | /* Wait for EEPROM reload */ | |
f8ec4733 | 696 | msleep(20); |
1da177e4 | 697 | break; |
2d7edb92 | 698 | case e1000_82573: |
c3033b01 | 699 | if (!e1000_is_onboard_nvm_eeprom(hw)) { |
fd803241 | 700 | udelay(10); |
1dc32918 | 701 | ctrl_ext = er32(CTRL_EXT); |
fd803241 | 702 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
1dc32918 JP |
703 | ew32(CTRL_EXT, ctrl_ext); |
704 | E1000_WRITE_FLUSH(); | |
fd803241 | 705 | } |
2d7edb92 | 706 | /* fall through */ |
2a88c173 JK |
707 | default: |
708 | /* Auto read done will delay 5ms or poll based on mac type */ | |
2d7edb92 | 709 | ret_val = e1000_get_auto_rd_done(hw); |
8fc897b0 | 710 | if (ret_val) |
2d7edb92 MC |
711 | return ret_val; |
712 | break; | |
1da177e4 LT |
713 | } |
714 | ||
715 | /* Disable HW ARPs on ASF enabled adapters */ | |
8fc897b0 | 716 | if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
1dc32918 | 717 | manc = er32(MANC); |
1da177e4 | 718 | manc &= ~(E1000_MANC_ARP_EN); |
1dc32918 | 719 | ew32(MANC, manc); |
1da177e4 LT |
720 | } |
721 | ||
8fc897b0 | 722 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1da177e4 LT |
723 | e1000_phy_init_script(hw); |
724 | ||
725 | /* Configure activity LED after PHY reset */ | |
1dc32918 | 726 | led_ctrl = er32(LEDCTL); |
1da177e4 LT |
727 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
728 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1dc32918 | 729 | ew32(LEDCTL, led_ctrl); |
1da177e4 LT |
730 | } |
731 | ||
732 | /* Clear interrupt mask to stop board from generating interrupts */ | |
733 | DEBUGOUT("Masking off all interrupts\n"); | |
1dc32918 | 734 | ew32(IMC, 0xffffffff); |
1da177e4 LT |
735 | |
736 | /* Clear any pending interrupt events. */ | |
1dc32918 | 737 | icr = er32(ICR); |
1da177e4 LT |
738 | |
739 | /* If MWI was previously enabled, reenable it. */ | |
8fc897b0 | 740 | if (hw->mac_type == e1000_82542_rev2_0) { |
f8ec4733 | 741 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
1da177e4 LT |
742 | e1000_pci_set_mwi(hw); |
743 | } | |
744 | ||
cd94dd0b | 745 | if (hw->mac_type == e1000_ich8lan) { |
1dc32918 | 746 | u32 kab = er32(KABGTXD); |
cd94dd0b | 747 | kab |= E1000_KABGTXD_BGSQLBIAS; |
1dc32918 | 748 | ew32(KABGTXD, kab); |
cd94dd0b AK |
749 | } |
750 | ||
1da177e4 LT |
751 | return E1000_SUCCESS; |
752 | } | |
753 | ||
09ae3e88 JK |
754 | /****************************************************************************** |
755 | * | |
756 | * Initialize a number of hardware-dependent bits | |
757 | * | |
758 | * hw: Struct containing variables accessed by shared code | |
759 | * | |
760 | * This function contains hardware limitation workarounds for PCI-E adapters | |
761 | * | |
762 | *****************************************************************************/ | |
64798845 | 763 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw) |
09ae3e88 JK |
764 | { |
765 | if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { | |
766 | /* Settings common to all PCI-express silicon */ | |
406874a7 JP |
767 | u32 reg_ctrl, reg_ctrl_ext; |
768 | u32 reg_tarc0, reg_tarc1; | |
769 | u32 reg_tctl; | |
770 | u32 reg_txdctl, reg_txdctl1; | |
09ae3e88 JK |
771 | |
772 | /* link autonegotiation/sync workarounds */ | |
1dc32918 | 773 | reg_tarc0 = er32(TARC0); |
09ae3e88 JK |
774 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
775 | ||
776 | /* Enable not-done TX descriptor counting */ | |
1dc32918 | 777 | reg_txdctl = er32(TXDCTL); |
09ae3e88 | 778 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; |
1dc32918 JP |
779 | ew32(TXDCTL, reg_txdctl); |
780 | reg_txdctl1 = er32(TXDCTL1); | |
09ae3e88 | 781 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; |
1dc32918 | 782 | ew32(TXDCTL1, reg_txdctl1); |
09ae3e88 JK |
783 | |
784 | switch (hw->mac_type) { | |
785 | case e1000_82571: | |
786 | case e1000_82572: | |
787 | /* Clear PHY TX compatible mode bits */ | |
1dc32918 | 788 | reg_tarc1 = er32(TARC1); |
09ae3e88 JK |
789 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); |
790 | ||
791 | /* link autonegotiation/sync workarounds */ | |
792 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); | |
793 | ||
794 | /* TX ring control fixes */ | |
795 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); | |
796 | ||
797 | /* Multiple read bit is reversed polarity */ | |
1dc32918 | 798 | reg_tctl = er32(TCTL); |
09ae3e88 JK |
799 | if (reg_tctl & E1000_TCTL_MULR) |
800 | reg_tarc1 &= ~(1 << 28); | |
801 | else | |
802 | reg_tarc1 |= (1 << 28); | |
803 | ||
1dc32918 | 804 | ew32(TARC1, reg_tarc1); |
09ae3e88 JK |
805 | break; |
806 | case e1000_82573: | |
1dc32918 | 807 | reg_ctrl_ext = er32(CTRL_EXT); |
09ae3e88 JK |
808 | reg_ctrl_ext &= ~(1 << 23); |
809 | reg_ctrl_ext |= (1 << 22); | |
810 | ||
811 | /* TX byte count fix */ | |
1dc32918 | 812 | reg_ctrl = er32(CTRL); |
09ae3e88 JK |
813 | reg_ctrl &= ~(1 << 29); |
814 | ||
1dc32918 JP |
815 | ew32(CTRL_EXT, reg_ctrl_ext); |
816 | ew32(CTRL, reg_ctrl); | |
09ae3e88 JK |
817 | break; |
818 | case e1000_80003es2lan: | |
819 | /* improve small packet performace for fiber/serdes */ | |
820 | if ((hw->media_type == e1000_media_type_fiber) || | |
821 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
822 | reg_tarc0 &= ~(1 << 20); | |
823 | } | |
824 | ||
825 | /* Multiple read bit is reversed polarity */ | |
1dc32918 JP |
826 | reg_tctl = er32(TCTL); |
827 | reg_tarc1 = er32(TARC1); | |
09ae3e88 JK |
828 | if (reg_tctl & E1000_TCTL_MULR) |
829 | reg_tarc1 &= ~(1 << 28); | |
830 | else | |
831 | reg_tarc1 |= (1 << 28); | |
832 | ||
1dc32918 | 833 | ew32(TARC1, reg_tarc1); |
09ae3e88 JK |
834 | break; |
835 | case e1000_ich8lan: | |
836 | /* Reduce concurrent DMA requests to 3 from 4 */ | |
837 | if ((hw->revision_id < 3) || | |
838 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
839 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) | |
840 | reg_tarc0 |= ((1 << 29)|(1 << 28)); | |
841 | ||
1dc32918 | 842 | reg_ctrl_ext = er32(CTRL_EXT); |
09ae3e88 | 843 | reg_ctrl_ext |= (1 << 22); |
1dc32918 | 844 | ew32(CTRL_EXT, reg_ctrl_ext); |
09ae3e88 JK |
845 | |
846 | /* workaround TX hang with TSO=on */ | |
847 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); | |
848 | ||
849 | /* Multiple read bit is reversed polarity */ | |
1dc32918 JP |
850 | reg_tctl = er32(TCTL); |
851 | reg_tarc1 = er32(TARC1); | |
09ae3e88 JK |
852 | if (reg_tctl & E1000_TCTL_MULR) |
853 | reg_tarc1 &= ~(1 << 28); | |
854 | else | |
855 | reg_tarc1 |= (1 << 28); | |
856 | ||
857 | /* workaround TX hang with TSO=on */ | |
858 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); | |
859 | ||
1dc32918 | 860 | ew32(TARC1, reg_tarc1); |
09ae3e88 JK |
861 | break; |
862 | default: | |
863 | break; | |
864 | } | |
865 | ||
1dc32918 | 866 | ew32(TARC0, reg_tarc0); |
09ae3e88 JK |
867 | } |
868 | } | |
869 | ||
1da177e4 LT |
870 | /****************************************************************************** |
871 | * Performs basic configuration of the adapter. | |
872 | * | |
873 | * hw - Struct containing variables accessed by shared code | |
874 | * | |
875 | * Assumes that the controller has previously been reset and is in a | |
876 | * post-reset uninitialized state. Initializes the receive address registers, | |
877 | * multicast table, and VLAN filter table. Calls routines to setup link | |
878 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
879 | * the transmit and receive units disabled and uninitialized. | |
880 | *****************************************************************************/ | |
64798845 | 881 | s32 e1000_init_hw(struct e1000_hw *hw) |
1da177e4 | 882 | { |
406874a7 JP |
883 | u32 ctrl; |
884 | u32 i; | |
885 | s32 ret_val; | |
886 | u32 mta_size; | |
887 | u32 reg_data; | |
888 | u32 ctrl_ext; | |
2d7edb92 | 889 | |
1da177e4 LT |
890 | DEBUGFUNC("e1000_init_hw"); |
891 | ||
7820d428 | 892 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
09ae3e88 JK |
893 | if ((hw->mac_type == e1000_ich8lan) && |
894 | ((hw->revision_id < 3) || | |
895 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
896 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { | |
1dc32918 | 897 | reg_data = er32(STATUS); |
09ae3e88 | 898 | reg_data &= ~0x80000000; |
1dc32918 | 899 | ew32(STATUS, reg_data); |
7820d428 JK |
900 | } |
901 | ||
1da177e4 LT |
902 | /* Initialize Identification LED */ |
903 | ret_val = e1000_id_led_init(hw); | |
8fc897b0 | 904 | if (ret_val) { |
1da177e4 LT |
905 | DEBUGOUT("Error Initializing Identification LED\n"); |
906 | return ret_val; | |
907 | } | |
908 | ||
909 | /* Set the media type and TBI compatibility */ | |
910 | e1000_set_media_type(hw); | |
911 | ||
09ae3e88 JK |
912 | /* Must be called after e1000_set_media_type because media_type is used */ |
913 | e1000_initialize_hardware_bits(hw); | |
914 | ||
1da177e4 LT |
915 | /* Disabling VLAN filtering. */ |
916 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
cd94dd0b AK |
917 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
918 | if (hw->mac_type != e1000_ich8lan) { | |
919 | if (hw->mac_type < e1000_82545_rev_3) | |
1dc32918 | 920 | ew32(VET, 0); |
cd94dd0b AK |
921 | e1000_clear_vfta(hw); |
922 | } | |
1da177e4 LT |
923 | |
924 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
8fc897b0 | 925 | if (hw->mac_type == e1000_82542_rev2_0) { |
1da177e4 LT |
926 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
927 | e1000_pci_clear_mwi(hw); | |
1dc32918 JP |
928 | ew32(RCTL, E1000_RCTL_RST); |
929 | E1000_WRITE_FLUSH(); | |
f8ec4733 | 930 | msleep(5); |
1da177e4 LT |
931 | } |
932 | ||
933 | /* Setup the receive address. This involves initializing all of the Receive | |
934 | * Address Registers (RARs 0 - 15). | |
935 | */ | |
936 | e1000_init_rx_addrs(hw); | |
937 | ||
938 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
8fc897b0 | 939 | if (hw->mac_type == e1000_82542_rev2_0) { |
1dc32918 JP |
940 | ew32(RCTL, 0); |
941 | E1000_WRITE_FLUSH(); | |
f8ec4733 JG |
942 | msleep(1); |
943 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) | |
1da177e4 LT |
944 | e1000_pci_set_mwi(hw); |
945 | } | |
946 | ||
947 | /* Zero out the Multicast HASH table */ | |
948 | DEBUGOUT("Zeroing the MTA\n"); | |
2d7edb92 | 949 | mta_size = E1000_MC_TBL_SIZE; |
cd94dd0b AK |
950 | if (hw->mac_type == e1000_ich8lan) |
951 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; | |
8fc897b0 | 952 | for (i = 0; i < mta_size; i++) { |
1da177e4 | 953 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
4ca213a6 AK |
954 | /* use write flush to prevent Memory Write Block (MWB) from |
955 | * occuring when accessing our register space */ | |
1dc32918 | 956 | E1000_WRITE_FLUSH(); |
4ca213a6 | 957 | } |
1da177e4 LT |
958 | |
959 | /* Set the PCI priority bit correctly in the CTRL register. This | |
960 | * determines if the adapter gives priority to receives, or if it | |
2d7edb92 MC |
961 | * gives equal priority to transmits and receives. Valid only on |
962 | * 82542 and 82543 silicon. | |
1da177e4 | 963 | */ |
8fc897b0 | 964 | if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
1dc32918 JP |
965 | ctrl = er32(CTRL); |
966 | ew32(CTRL, ctrl | E1000_CTRL_PRIOR); | |
1da177e4 LT |
967 | } |
968 | ||
8fc897b0 | 969 | switch (hw->mac_type) { |
1da177e4 LT |
970 | case e1000_82545_rev_3: |
971 | case e1000_82546_rev_3: | |
972 | break; | |
973 | default: | |
974 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ | |
007755eb PO |
975 | if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) |
976 | e1000_pcix_set_mmrbc(hw, 2048); | |
977 | break; | |
1da177e4 LT |
978 | } |
979 | ||
cd94dd0b AK |
980 | /* More time needed for PHY to initialize */ |
981 | if (hw->mac_type == e1000_ich8lan) | |
f8ec4733 | 982 | msleep(15); |
cd94dd0b | 983 | |
1da177e4 LT |
984 | /* Call a subroutine to configure the link and setup flow control. */ |
985 | ret_val = e1000_setup_link(hw); | |
986 | ||
987 | /* Set the transmit descriptor write-back policy */ | |
8fc897b0 | 988 | if (hw->mac_type > e1000_82544) { |
1dc32918 | 989 | ctrl = er32(TXDCTL); |
1da177e4 | 990 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
1dc32918 | 991 | ew32(TXDCTL, ctrl); |
1da177e4 LT |
992 | } |
993 | ||
2d7edb92 | 994 | if (hw->mac_type == e1000_82573) { |
76c224bc | 995 | e1000_enable_tx_pkt_filtering(hw); |
2d7edb92 MC |
996 | } |
997 | ||
868d5309 MC |
998 | switch (hw->mac_type) { |
999 | default: | |
1000 | break; | |
6418ecc6 JK |
1001 | case e1000_80003es2lan: |
1002 | /* Enable retransmit on late collisions */ | |
1dc32918 | 1003 | reg_data = er32(TCTL); |
6418ecc6 | 1004 | reg_data |= E1000_TCTL_RTLC; |
1dc32918 | 1005 | ew32(TCTL, reg_data); |
6418ecc6 JK |
1006 | |
1007 | /* Configure Gigabit Carry Extend Padding */ | |
1dc32918 | 1008 | reg_data = er32(TCTL_EXT); |
6418ecc6 JK |
1009 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
1010 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | |
1dc32918 | 1011 | ew32(TCTL_EXT, reg_data); |
6418ecc6 JK |
1012 | |
1013 | /* Configure Transmit Inter-Packet Gap */ | |
1dc32918 | 1014 | reg_data = er32(TIPG); |
6418ecc6 JK |
1015 | reg_data &= ~E1000_TIPG_IPGT_MASK; |
1016 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
1dc32918 | 1017 | ew32(TIPG, reg_data); |
6418ecc6 JK |
1018 | |
1019 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | |
1020 | reg_data &= ~0x00100000; | |
1021 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | |
1022 | /* Fall through */ | |
868d5309 | 1023 | case e1000_82571: |
a7990ba6 | 1024 | case e1000_82572: |
cd94dd0b | 1025 | case e1000_ich8lan: |
1dc32918 | 1026 | ctrl = er32(TXDCTL1); |
6418ecc6 | 1027 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
1dc32918 | 1028 | ew32(TXDCTL1, ctrl); |
868d5309 MC |
1029 | break; |
1030 | } | |
1031 | ||
1032 | ||
868d5309 | 1033 | if (hw->mac_type == e1000_82573) { |
1dc32918 | 1034 | u32 gcr = er32(GCR); |
868d5309 | 1035 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
1dc32918 | 1036 | ew32(GCR, gcr); |
868d5309 | 1037 | } |
2d7edb92 | 1038 | |
1da177e4 LT |
1039 | /* Clear all of the statistics registers (clear on read). It is |
1040 | * important that we do this after we have tried to establish link | |
1041 | * because the symbol error count will increment wildly if there | |
1042 | * is no link. | |
1043 | */ | |
1044 | e1000_clear_hw_cntrs(hw); | |
1045 | ||
cd94dd0b AK |
1046 | /* ICH8 No-snoop bits are opposite polarity. |
1047 | * Set to snoop by default after reset. */ | |
1048 | if (hw->mac_type == e1000_ich8lan) | |
1049 | e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); | |
1050 | ||
b7ee49db JK |
1051 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
1052 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | |
1dc32918 | 1053 | ctrl_ext = er32(CTRL_EXT); |
b7ee49db JK |
1054 | /* Relaxed ordering must be disabled to avoid a parity |
1055 | * error crash in a PCI slot. */ | |
1056 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
1dc32918 | 1057 | ew32(CTRL_EXT, ctrl_ext); |
b7ee49db JK |
1058 | } |
1059 | ||
1da177e4 LT |
1060 | return ret_val; |
1061 | } | |
1062 | ||
1063 | /****************************************************************************** | |
1064 | * Adjust SERDES output amplitude based on EEPROM setting. | |
1065 | * | |
1066 | * hw - Struct containing variables accessed by shared code. | |
1067 | *****************************************************************************/ | |
64798845 | 1068 | static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
1da177e4 | 1069 | { |
406874a7 JP |
1070 | u16 eeprom_data; |
1071 | s32 ret_val; | |
1da177e4 LT |
1072 | |
1073 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); | |
1074 | ||
8fc897b0 | 1075 | if (hw->media_type != e1000_media_type_internal_serdes) |
1da177e4 LT |
1076 | return E1000_SUCCESS; |
1077 | ||
8fc897b0 | 1078 | switch (hw->mac_type) { |
1da177e4 LT |
1079 | case e1000_82545_rev_3: |
1080 | case e1000_82546_rev_3: | |
1081 | break; | |
1082 | default: | |
1083 | return E1000_SUCCESS; | |
1084 | } | |
1085 | ||
1086 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); | |
1087 | if (ret_val) { | |
1088 | return ret_val; | |
1089 | } | |
1090 | ||
8fc897b0 | 1091 | if (eeprom_data != EEPROM_RESERVED_WORD) { |
1da177e4 | 1092 | /* Adjust SERDES output amplitude only. */ |
76c224bc | 1093 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
1da177e4 | 1094 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
8fc897b0 | 1095 | if (ret_val) |
1da177e4 LT |
1096 | return ret_val; |
1097 | } | |
1098 | ||
1099 | return E1000_SUCCESS; | |
1100 | } | |
1101 | ||
1102 | /****************************************************************************** | |
1103 | * Configures flow control and link settings. | |
1104 | * | |
1105 | * hw - Struct containing variables accessed by shared code | |
1106 | * | |
1107 | * Determines which flow control settings to use. Calls the apropriate media- | |
1108 | * specific link configuration function. Configures the flow control settings. | |
1109 | * Assuming the adapter has a valid link partner, a valid link should be | |
1110 | * established. Assumes the hardware has previously been reset and the | |
1111 | * transmitter and receiver are not enabled. | |
1112 | *****************************************************************************/ | |
64798845 | 1113 | s32 e1000_setup_link(struct e1000_hw *hw) |
1da177e4 | 1114 | { |
406874a7 JP |
1115 | u32 ctrl_ext; |
1116 | s32 ret_val; | |
1117 | u16 eeprom_data; | |
1da177e4 LT |
1118 | |
1119 | DEBUGFUNC("e1000_setup_link"); | |
1120 | ||
526f9957 JK |
1121 | /* In the case of the phy reset being blocked, we already have a link. |
1122 | * We do not have to set it up again. */ | |
1123 | if (e1000_check_phy_reset_block(hw)) | |
1124 | return E1000_SUCCESS; | |
1125 | ||
1da177e4 LT |
1126 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
1127 | * that determine the hardware's default PAUSE (flow control) mode, | |
1128 | * a bit that determines whether the HW defaults to enabling or | |
1129 | * disabling auto-negotiation, and the direction of the | |
1130 | * SW defined pins. If there is no SW over-ride of the flow | |
1131 | * control setting, then the variable hw->fc will | |
1132 | * be initialized based on a value in the EEPROM. | |
1133 | */ | |
11241b10 | 1134 | if (hw->fc == E1000_FC_DEFAULT) { |
fd803241 | 1135 | switch (hw->mac_type) { |
cd94dd0b | 1136 | case e1000_ich8lan: |
fd803241 | 1137 | case e1000_82573: |
11241b10 | 1138 | hw->fc = E1000_FC_FULL; |
fd803241 JK |
1139 | break; |
1140 | default: | |
1141 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | |
1142 | 1, &eeprom_data); | |
1143 | if (ret_val) { | |
1144 | DEBUGOUT("EEPROM Read Error\n"); | |
1145 | return -E1000_ERR_EEPROM; | |
1146 | } | |
1147 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) | |
11241b10 | 1148 | hw->fc = E1000_FC_NONE; |
fd803241 JK |
1149 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
1150 | EEPROM_WORD0F_ASM_DIR) | |
11241b10 | 1151 | hw->fc = E1000_FC_TX_PAUSE; |
fd803241 | 1152 | else |
11241b10 | 1153 | hw->fc = E1000_FC_FULL; |
fd803241 JK |
1154 | break; |
1155 | } | |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | /* We want to save off the original Flow Control configuration just | |
1159 | * in case we get disconnected and then reconnected into a different | |
1160 | * hub or switch with different Flow Control capabilities. | |
1161 | */ | |
8fc897b0 | 1162 | if (hw->mac_type == e1000_82542_rev2_0) |
11241b10 | 1163 | hw->fc &= (~E1000_FC_TX_PAUSE); |
1da177e4 | 1164 | |
8fc897b0 | 1165 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
11241b10 | 1166 | hw->fc &= (~E1000_FC_RX_PAUSE); |
1da177e4 LT |
1167 | |
1168 | hw->original_fc = hw->fc; | |
1169 | ||
1170 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | |
1171 | ||
1172 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial | |
1173 | * polarity value for the SW controlled pins, and setup the | |
1174 | * Extended Device Control reg with that info. | |
1175 | * This is needed because one of the SW controlled pins is used for | |
1176 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
1177 | * or e1000_phy_setup() is called. | |
1178 | */ | |
497fce5e | 1179 | if (hw->mac_type == e1000_82543) { |
8fc897b0 AK |
1180 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
1181 | 1, &eeprom_data); | |
1182 | if (ret_val) { | |
1183 | DEBUGOUT("EEPROM Read Error\n"); | |
1184 | return -E1000_ERR_EEPROM; | |
1185 | } | |
1da177e4 LT |
1186 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
1187 | SWDPIO__EXT_SHIFT); | |
1dc32918 | 1188 | ew32(CTRL_EXT, ctrl_ext); |
1da177e4 LT |
1189 | } |
1190 | ||
1191 | /* Call the necessary subroutine to configure the link. */ | |
1192 | ret_val = (hw->media_type == e1000_media_type_copper) ? | |
1193 | e1000_setup_copper_link(hw) : | |
1194 | e1000_setup_fiber_serdes_link(hw); | |
1195 | ||
1196 | /* Initialize the flow control address, type, and PAUSE timer | |
1197 | * registers to their default values. This is done even if flow | |
1198 | * control is disabled, because it does not hurt anything to | |
1199 | * initialize these registers. | |
1200 | */ | |
1201 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | |
1202 | ||
cd94dd0b AK |
1203 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
1204 | if (hw->mac_type != e1000_ich8lan) { | |
1dc32918 JP |
1205 | ew32(FCT, FLOW_CONTROL_TYPE); |
1206 | ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
1207 | ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
cd94dd0b | 1208 | } |
2d7edb92 | 1209 | |
1dc32918 | 1210 | ew32(FCTTV, hw->fc_pause_time); |
1da177e4 LT |
1211 | |
1212 | /* Set the flow control receive threshold registers. Normally, | |
1213 | * these registers will be set to a default threshold that may be | |
1214 | * adjusted later by the driver's runtime code. However, if the | |
1215 | * ability to transmit pause frames in not enabled, then these | |
1216 | * registers will be set to 0. | |
1217 | */ | |
11241b10 | 1218 | if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
1dc32918 JP |
1219 | ew32(FCRTL, 0); |
1220 | ew32(FCRTH, 0); | |
1da177e4 LT |
1221 | } else { |
1222 | /* We need to set up the Receive Threshold high and low water marks | |
1223 | * as well as (optionally) enabling the transmission of XON frames. | |
1224 | */ | |
8fc897b0 | 1225 | if (hw->fc_send_xon) { |
1dc32918 JP |
1226 | ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
1227 | ew32(FCRTH, hw->fc_high_water); | |
1da177e4 | 1228 | } else { |
1dc32918 JP |
1229 | ew32(FCRTL, hw->fc_low_water); |
1230 | ew32(FCRTH, hw->fc_high_water); | |
1da177e4 LT |
1231 | } |
1232 | } | |
1233 | return ret_val; | |
1234 | } | |
1235 | ||
1236 | /****************************************************************************** | |
1237 | * Sets up link for a fiber based or serdes based adapter | |
1238 | * | |
1239 | * hw - Struct containing variables accessed by shared code | |
1240 | * | |
1241 | * Manipulates Physical Coding Sublayer functions in order to configure | |
1242 | * link. Assumes the hardware has been previously reset and the transmitter | |
1243 | * and receiver are not enabled. | |
1244 | *****************************************************************************/ | |
64798845 | 1245 | static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
1da177e4 | 1246 | { |
406874a7 JP |
1247 | u32 ctrl; |
1248 | u32 status; | |
1249 | u32 txcw = 0; | |
1250 | u32 i; | |
1251 | u32 signal = 0; | |
1252 | s32 ret_val; | |
1da177e4 LT |
1253 | |
1254 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); | |
1255 | ||
868d5309 MC |
1256 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
1257 | * until explicitly turned off or a power cycle is performed. A read to | |
1258 | * the register does not indicate its status. Therefore, we ensure | |
1259 | * loopback mode is disabled during initialization. | |
1260 | */ | |
1261 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) | |
1dc32918 | 1262 | ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK); |
868d5309 | 1263 | |
09ae3e88 | 1264 | /* On adapters with a MAC newer than 82544, SWDP 1 will be |
1da177e4 LT |
1265 | * set when the optics detect a signal. On older adapters, it will be |
1266 | * cleared when there is a signal. This applies to fiber media only. | |
09ae3e88 JK |
1267 | * If we're on serdes media, adjust the output amplitude to value |
1268 | * set in the EEPROM. | |
1da177e4 | 1269 | */ |
1dc32918 | 1270 | ctrl = er32(CTRL); |
8fc897b0 | 1271 | if (hw->media_type == e1000_media_type_fiber) |
1da177e4 LT |
1272 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
1273 | ||
1274 | ret_val = e1000_adjust_serdes_amplitude(hw); | |
8fc897b0 | 1275 | if (ret_val) |
1da177e4 LT |
1276 | return ret_val; |
1277 | ||
1278 | /* Take the link out of reset */ | |
1279 | ctrl &= ~(E1000_CTRL_LRST); | |
1280 | ||
1281 | /* Adjust VCO speed to improve BER performance */ | |
1282 | ret_val = e1000_set_vco_speed(hw); | |
8fc897b0 | 1283 | if (ret_val) |
1da177e4 LT |
1284 | return ret_val; |
1285 | ||
1286 | e1000_config_collision_dist(hw); | |
1287 | ||
1288 | /* Check for a software override of the flow control settings, and setup | |
1289 | * the device accordingly. If auto-negotiation is enabled, then software | |
1290 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
1291 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
1292 | * auto-negotiation is disabled, then software will have to manually | |
1293 | * configure the two flow control enable bits in the CTRL register. | |
1294 | * | |
1295 | * The possible values of the "fc" parameter are: | |
1296 | * 0: Flow control is completely disabled | |
1297 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
1298 | * not send pause frames). | |
1299 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
1300 | * not support receiving pause frames). | |
1301 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1302 | */ | |
1303 | switch (hw->fc) { | |
11241b10 | 1304 | case E1000_FC_NONE: |
1da177e4 LT |
1305 | /* Flow control is completely disabled by a software over-ride. */ |
1306 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
1307 | break; | |
11241b10 | 1308 | case E1000_FC_RX_PAUSE: |
1da177e4 LT |
1309 | /* RX Flow control is enabled and TX Flow control is disabled by a |
1310 | * software over-ride. Since there really isn't a way to advertise | |
1311 | * that we are capable of RX Pause ONLY, we will advertise that we | |
1312 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
1313 | * disable the adapter's ability to send PAUSE frames. | |
1314 | */ | |
1315 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1316 | break; | |
11241b10 | 1317 | case E1000_FC_TX_PAUSE: |
1da177e4 LT |
1318 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
1319 | * software over-ride. | |
1320 | */ | |
1321 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
1322 | break; | |
11241b10 | 1323 | case E1000_FC_FULL: |
1da177e4 LT |
1324 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
1325 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1326 | break; | |
1327 | default: | |
1328 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1329 | return -E1000_ERR_CONFIG; | |
1330 | break; | |
1331 | } | |
1332 | ||
1333 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
1334 | * will be in reset, because we previously reset the chip). This will | |
1335 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
1336 | * link-up status bit will be set and the flow control enable bits (RFCE | |
1337 | * and TFCE) will be set according to their negotiated value. | |
1338 | */ | |
1339 | DEBUGOUT("Auto-negotiation enabled\n"); | |
1340 | ||
1dc32918 JP |
1341 | ew32(TXCW, txcw); |
1342 | ew32(CTRL, ctrl); | |
1343 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
1344 | |
1345 | hw->txcw = txcw; | |
f8ec4733 | 1346 | msleep(1); |
1da177e4 LT |
1347 | |
1348 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
1349 | * indication in the Device Status Register. Time-out if a link isn't | |
1350 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
1351 | * less than 500 milliseconds even if the other end is doing it in SW). | |
1352 | * For internal serdes, we just assume a signal is present, then poll. | |
1353 | */ | |
8fc897b0 | 1354 | if (hw->media_type == e1000_media_type_internal_serdes || |
1dc32918 | 1355 | (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
1da177e4 | 1356 | DEBUGOUT("Looking for Link\n"); |
8fc897b0 | 1357 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
f8ec4733 | 1358 | msleep(10); |
1dc32918 | 1359 | status = er32(STATUS); |
8fc897b0 | 1360 | if (status & E1000_STATUS_LU) break; |
1da177e4 | 1361 | } |
8fc897b0 | 1362 | if (i == (LINK_UP_TIMEOUT / 10)) { |
1da177e4 LT |
1363 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
1364 | hw->autoneg_failed = 1; | |
1365 | /* AutoNeg failed to achieve a link, so we'll call | |
1366 | * e1000_check_for_link. This routine will force the link up if | |
1367 | * we detect a signal. This will allow us to communicate with | |
1368 | * non-autonegotiating link partners. | |
1369 | */ | |
1370 | ret_val = e1000_check_for_link(hw); | |
8fc897b0 | 1371 | if (ret_val) { |
1da177e4 LT |
1372 | DEBUGOUT("Error while checking for link\n"); |
1373 | return ret_val; | |
1374 | } | |
1375 | hw->autoneg_failed = 0; | |
1376 | } else { | |
1377 | hw->autoneg_failed = 0; | |
1378 | DEBUGOUT("Valid Link Found\n"); | |
1379 | } | |
1380 | } else { | |
1381 | DEBUGOUT("No Signal Detected\n"); | |
1382 | } | |
1383 | return E1000_SUCCESS; | |
1384 | } | |
1385 | ||
1386 | /****************************************************************************** | |
2d7edb92 | 1387 | * Make sure we have a valid PHY and change PHY mode before link setup. |
1da177e4 LT |
1388 | * |
1389 | * hw - Struct containing variables accessed by shared code | |
1390 | ******************************************************************************/ | |
64798845 | 1391 | static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) |
1da177e4 | 1392 | { |
406874a7 JP |
1393 | u32 ctrl; |
1394 | s32 ret_val; | |
1395 | u16 phy_data; | |
1da177e4 | 1396 | |
2d7edb92 | 1397 | DEBUGFUNC("e1000_copper_link_preconfig"); |
1da177e4 | 1398 | |
1dc32918 | 1399 | ctrl = er32(CTRL); |
1da177e4 LT |
1400 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
1401 | * the PHY speed and duplex configuration is. In addition, we need to | |
1402 | * perform a hardware reset on the PHY to take it out of reset. | |
1403 | */ | |
8fc897b0 | 1404 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
1405 | ctrl |= E1000_CTRL_SLU; |
1406 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1dc32918 | 1407 | ew32(CTRL, ctrl); |
1da177e4 LT |
1408 | } else { |
1409 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | |
1dc32918 | 1410 | ew32(CTRL, ctrl); |
2d7edb92 | 1411 | ret_val = e1000_phy_hw_reset(hw); |
8fc897b0 | 1412 | if (ret_val) |
2d7edb92 | 1413 | return ret_val; |
1da177e4 LT |
1414 | } |
1415 | ||
1416 | /* Make sure we have a valid PHY */ | |
1417 | ret_val = e1000_detect_gig_phy(hw); | |
8fc897b0 | 1418 | if (ret_val) { |
1da177e4 LT |
1419 | DEBUGOUT("Error, did not detect valid phy.\n"); |
1420 | return ret_val; | |
1421 | } | |
1422 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); | |
1423 | ||
1424 | /* Set PHY to class A mode (if necessary) */ | |
1425 | ret_val = e1000_set_phy_mode(hw); | |
8fc897b0 | 1426 | if (ret_val) |
1da177e4 LT |
1427 | return ret_val; |
1428 | ||
8fc897b0 | 1429 | if ((hw->mac_type == e1000_82545_rev_3) || |
1da177e4 LT |
1430 | (hw->mac_type == e1000_82546_rev_3)) { |
1431 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1432 | phy_data |= 0x00000008; | |
1433 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1434 | } | |
1435 | ||
8fc897b0 AK |
1436 | if (hw->mac_type <= e1000_82543 || |
1437 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
1438 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | |
c3033b01 | 1439 | hw->phy_reset_disable = false; |
1da177e4 | 1440 | |
2d7edb92 MC |
1441 | return E1000_SUCCESS; |
1442 | } | |
1da177e4 | 1443 | |
1da177e4 | 1444 | |
2d7edb92 MC |
1445 | /******************************************************************** |
1446 | * Copper link setup for e1000_phy_igp series. | |
1447 | * | |
1448 | * hw - Struct containing variables accessed by shared code | |
1449 | *********************************************************************/ | |
64798845 | 1450 | static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
2d7edb92 | 1451 | { |
406874a7 JP |
1452 | u32 led_ctrl; |
1453 | s32 ret_val; | |
1454 | u16 phy_data; | |
1da177e4 | 1455 | |
2d7edb92 | 1456 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
1da177e4 | 1457 | |
2d7edb92 MC |
1458 | if (hw->phy_reset_disable) |
1459 | return E1000_SUCCESS; | |
76c224bc | 1460 | |
2d7edb92 MC |
1461 | ret_val = e1000_phy_reset(hw); |
1462 | if (ret_val) { | |
1463 | DEBUGOUT("Error Resetting the PHY\n"); | |
1464 | return ret_val; | |
1465 | } | |
1da177e4 | 1466 | |
8fc897b0 | 1467 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
f8ec4733 | 1468 | msleep(15); |
cd94dd0b | 1469 | if (hw->mac_type != e1000_ich8lan) { |
2d7edb92 | 1470 | /* Configure activity LED after PHY reset */ |
1dc32918 | 1471 | led_ctrl = er32(LEDCTL); |
2d7edb92 MC |
1472 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
1473 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1dc32918 | 1474 | ew32(LEDCTL, led_ctrl); |
cd94dd0b | 1475 | } |
1da177e4 | 1476 | |
c9c1b834 JK |
1477 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
1478 | if (hw->phy_type == e1000_phy_igp) { | |
1479 | /* disable lplu d3 during driver init */ | |
c3033b01 | 1480 | ret_val = e1000_set_d3_lplu_state(hw, false); |
c9c1b834 JK |
1481 | if (ret_val) { |
1482 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
1483 | return ret_val; | |
1484 | } | |
2d7edb92 | 1485 | } |
1da177e4 | 1486 | |
2d7edb92 | 1487 | /* disable lplu d0 during driver init */ |
c3033b01 | 1488 | ret_val = e1000_set_d0_lplu_state(hw, false); |
2d7edb92 MC |
1489 | if (ret_val) { |
1490 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
1491 | return ret_val; | |
1492 | } | |
1493 | /* Configure mdi-mdix settings */ | |
1494 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1495 | if (ret_val) | |
1496 | return ret_val; | |
1da177e4 | 1497 | |
2d7edb92 MC |
1498 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1499 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
1500 | /* Force MDI for earlier revs of the IGP PHY */ | |
1501 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
1502 | hw->mdix = 1; | |
1da177e4 | 1503 | |
2d7edb92 MC |
1504 | } else { |
1505 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1506 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1da177e4 | 1507 | |
2d7edb92 MC |
1508 | switch (hw->mdix) { |
1509 | case 1: | |
1510 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1511 | break; | |
1512 | case 2: | |
1513 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1514 | break; | |
1515 | case 0: | |
1516 | default: | |
1517 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
1518 | break; | |
1519 | } | |
1520 | } | |
1521 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
8fc897b0 | 1522 | if (ret_val) |
2d7edb92 | 1523 | return ret_val; |
1da177e4 | 1524 | |
2d7edb92 | 1525 | /* set auto-master slave resolution settings */ |
8fc897b0 | 1526 | if (hw->autoneg) { |
2d7edb92 | 1527 | e1000_ms_type phy_ms_setting = hw->master_slave; |
1da177e4 | 1528 | |
8fc897b0 | 1529 | if (hw->ffe_config_state == e1000_ffe_config_active) |
2d7edb92 | 1530 | hw->ffe_config_state = e1000_ffe_config_enabled; |
1da177e4 | 1531 | |
8fc897b0 | 1532 | if (hw->dsp_config_state == e1000_dsp_config_activated) |
2d7edb92 | 1533 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1da177e4 | 1534 | |
2d7edb92 MC |
1535 | /* when autonegotiation advertisment is only 1000Mbps then we |
1536 | * should disable SmartSpeed and enable Auto MasterSlave | |
1537 | * resolution as hardware default. */ | |
8fc897b0 | 1538 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
2d7edb92 | 1539 | /* Disable SmartSpeed */ |
8fc897b0 AK |
1540 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1541 | &phy_data); | |
1542 | if (ret_val) | |
1da177e4 | 1543 | return ret_val; |
2d7edb92 | 1544 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
8fc897b0 AK |
1545 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1546 | phy_data); | |
1547 | if (ret_val) | |
1da177e4 | 1548 | return ret_val; |
2d7edb92 MC |
1549 | /* Set auto Master/Slave resolution process */ |
1550 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
8fc897b0 | 1551 | if (ret_val) |
2d7edb92 MC |
1552 | return ret_val; |
1553 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1554 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
8fc897b0 | 1555 | if (ret_val) |
2d7edb92 MC |
1556 | return ret_val; |
1557 | } | |
1da177e4 | 1558 | |
2d7edb92 | 1559 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
8fc897b0 | 1560 | if (ret_val) |
2d7edb92 | 1561 | return ret_val; |
1da177e4 | 1562 | |
2d7edb92 MC |
1563 | /* load defaults for future use */ |
1564 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
1565 | ((phy_data & CR_1000T_MS_VALUE) ? | |
1566 | e1000_ms_force_master : | |
1567 | e1000_ms_force_slave) : | |
1568 | e1000_ms_auto; | |
1da177e4 | 1569 | |
2d7edb92 MC |
1570 | switch (phy_ms_setting) { |
1571 | case e1000_ms_force_master: | |
1572 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
1573 | break; | |
1574 | case e1000_ms_force_slave: | |
1575 | phy_data |= CR_1000T_MS_ENABLE; | |
1576 | phy_data &= ~(CR_1000T_MS_VALUE); | |
1577 | break; | |
1578 | case e1000_ms_auto: | |
1579 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1580 | default: | |
1581 | break; | |
1582 | } | |
1583 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
8fc897b0 | 1584 | if (ret_val) |
2d7edb92 | 1585 | return ret_val; |
2b02893e | 1586 | } |
1da177e4 | 1587 | |
2b02893e | 1588 | return E1000_SUCCESS; |
2d7edb92 | 1589 | } |
1da177e4 | 1590 | |
6418ecc6 JK |
1591 | /******************************************************************** |
1592 | * Copper link setup for e1000_phy_gg82563 series. | |
1593 | * | |
1594 | * hw - Struct containing variables accessed by shared code | |
1595 | *********************************************************************/ | |
64798845 | 1596 | static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw) |
6418ecc6 | 1597 | { |
406874a7 JP |
1598 | s32 ret_val; |
1599 | u16 phy_data; | |
1600 | u32 reg_data; | |
6418ecc6 JK |
1601 | |
1602 | DEBUGFUNC("e1000_copper_link_ggp_setup"); | |
1603 | ||
8fc897b0 | 1604 | if (!hw->phy_reset_disable) { |
76c224bc | 1605 | |
6418ecc6 JK |
1606 | /* Enable CRS on TX for half-duplex operation. */ |
1607 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1608 | &phy_data); | |
8fc897b0 | 1609 | if (ret_val) |
6418ecc6 JK |
1610 | return ret_val; |
1611 | ||
1612 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
1613 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | |
1614 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | |
1615 | ||
1616 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1617 | phy_data); | |
8fc897b0 | 1618 | if (ret_val) |
6418ecc6 JK |
1619 | return ret_val; |
1620 | ||
1621 | /* Options: | |
1622 | * MDI/MDI-X = 0 (default) | |
1623 | * 0 - Auto for all speeds | |
1624 | * 1 - MDI mode | |
1625 | * 2 - MDI-X mode | |
1626 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1627 | */ | |
1628 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 1629 | if (ret_val) |
6418ecc6 JK |
1630 | return ret_val; |
1631 | ||
1632 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
1633 | ||
1634 | switch (hw->mdix) { | |
1635 | case 1: | |
1636 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
1637 | break; | |
1638 | case 2: | |
1639 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
1640 | break; | |
1641 | case 0: | |
1642 | default: | |
1643 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
1644 | break; | |
1645 | } | |
1646 | ||
1647 | /* Options: | |
1648 | * disable_polarity_correction = 0 (default) | |
1649 | * Automatic Correction for Reversed Cable Polarity | |
1650 | * 0 - Disabled | |
1651 | * 1 - Enabled | |
1652 | */ | |
1653 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
8fc897b0 | 1654 | if (hw->disable_polarity_correction == 1) |
6418ecc6 JK |
1655 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
1656 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
1657 | ||
8fc897b0 | 1658 | if (ret_val) |
6418ecc6 JK |
1659 | return ret_val; |
1660 | ||
1661 | /* SW Reset the PHY so all changes take effect */ | |
1662 | ret_val = e1000_phy_reset(hw); | |
1663 | if (ret_val) { | |
1664 | DEBUGOUT("Error Resetting the PHY\n"); | |
1665 | return ret_val; | |
1666 | } | |
1667 | } /* phy_reset_disable */ | |
1668 | ||
1669 | if (hw->mac_type == e1000_80003es2lan) { | |
1670 | /* Bypass RX and TX FIFO's */ | |
1671 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | |
1672 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | | |
1673 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | |
1674 | if (ret_val) | |
1675 | return ret_val; | |
1676 | ||
1677 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); | |
1678 | if (ret_val) | |
1679 | return ret_val; | |
1680 | ||
1681 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1682 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); | |
1683 | ||
1684 | if (ret_val) | |
1685 | return ret_val; | |
1686 | ||
1dc32918 | 1687 | reg_data = er32(CTRL_EXT); |
6418ecc6 | 1688 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); |
1dc32918 | 1689 | ew32(CTRL_EXT, reg_data); |
6418ecc6 JK |
1690 | |
1691 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1692 | &phy_data); | |
1693 | if (ret_val) | |
1694 | return ret_val; | |
1695 | ||
1696 | /* Do not init these registers when the HW is in IAMT mode, since the | |
1697 | * firmware will have already initialized them. We only initialize | |
1698 | * them if the HW is not in IAMT mode. | |
1699 | */ | |
c3033b01 | 1700 | if (!e1000_check_mng_mode(hw)) { |
6418ecc6 JK |
1701 | /* Enable Electrical Idle on the PHY */ |
1702 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1703 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1704 | phy_data); | |
1705 | if (ret_val) | |
1706 | return ret_val; | |
1707 | ||
1708 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1709 | &phy_data); | |
1710 | if (ret_val) | |
1711 | return ret_val; | |
1712 | ||
cd94dd0b | 1713 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
6418ecc6 JK |
1714 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
1715 | phy_data); | |
8fc897b0 | 1716 | |
6418ecc6 JK |
1717 | if (ret_val) |
1718 | return ret_val; | |
1719 | } | |
1720 | ||
1721 | /* Workaround: Disable padding in Kumeran interface in the MAC | |
1722 | * and in the PHY to avoid CRC errors. | |
1723 | */ | |
1724 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1725 | &phy_data); | |
1726 | if (ret_val) | |
1727 | return ret_val; | |
1728 | phy_data |= GG82563_ICR_DIS_PADDING; | |
1729 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1730 | phy_data); | |
1731 | if (ret_val) | |
1732 | return ret_val; | |
1733 | } | |
1734 | ||
1735 | return E1000_SUCCESS; | |
1736 | } | |
1da177e4 | 1737 | |
2d7edb92 MC |
1738 | /******************************************************************** |
1739 | * Copper link setup for e1000_phy_m88 series. | |
1740 | * | |
1741 | * hw - Struct containing variables accessed by shared code | |
1742 | *********************************************************************/ | |
64798845 | 1743 | static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
2d7edb92 | 1744 | { |
406874a7 JP |
1745 | s32 ret_val; |
1746 | u16 phy_data; | |
1da177e4 | 1747 | |
2d7edb92 | 1748 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
1da177e4 | 1749 | |
8fc897b0 | 1750 | if (hw->phy_reset_disable) |
2d7edb92 | 1751 | return E1000_SUCCESS; |
76c224bc | 1752 | |
2d7edb92 MC |
1753 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
1754 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 1755 | if (ret_val) |
2d7edb92 | 1756 | return ret_val; |
1da177e4 | 1757 | |
2d7edb92 | 1758 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
1da177e4 | 1759 | |
2d7edb92 MC |
1760 | /* Options: |
1761 | * MDI/MDI-X = 0 (default) | |
1762 | * 0 - Auto for all speeds | |
1763 | * 1 - MDI mode | |
1764 | * 2 - MDI-X mode | |
1765 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1766 | */ | |
1767 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1da177e4 | 1768 | |
2d7edb92 MC |
1769 | switch (hw->mdix) { |
1770 | case 1: | |
1771 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
1772 | break; | |
1773 | case 2: | |
1774 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
1775 | break; | |
1776 | case 3: | |
1777 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
1778 | break; | |
1779 | case 0: | |
1780 | default: | |
1781 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
1782 | break; | |
1783 | } | |
1784 | ||
1785 | /* Options: | |
1786 | * disable_polarity_correction = 0 (default) | |
1787 | * Automatic Correction for Reversed Cable Polarity | |
1788 | * 0 - Disabled | |
1789 | * 1 - Enabled | |
1da177e4 | 1790 | */ |
2d7edb92 | 1791 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
8fc897b0 | 1792 | if (hw->disable_polarity_correction == 1) |
2d7edb92 | 1793 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
ee04022a AK |
1794 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
1795 | if (ret_val) | |
2d7edb92 MC |
1796 | return ret_val; |
1797 | ||
2d7edb92 | 1798 | if (hw->phy_revision < M88E1011_I_REV_4) { |
ee04022a AK |
1799 | /* Force TX_CLK in the Extended PHY Specific Control Register |
1800 | * to 25MHz clock. | |
1801 | */ | |
1802 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1803 | if (ret_val) | |
1804 | return ret_val; | |
1805 | ||
1806 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1807 | ||
1808 | if ((hw->phy_revision == E1000_REVISION_2) && | |
1809 | (hw->phy_id == M88E1111_I_PHY_ID)) { | |
1810 | /* Vidalia Phy, set the downshift counter to 5x */ | |
1811 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); | |
1812 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
1813 | ret_val = e1000_write_phy_reg(hw, | |
1814 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1815 | if (ret_val) | |
1816 | return ret_val; | |
1817 | } else { | |
1818 | /* Configure Master and Slave downshift values */ | |
1819 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
2d7edb92 | 1820 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
ee04022a | 1821 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
2d7edb92 | 1822 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
ee04022a AK |
1823 | ret_val = e1000_write_phy_reg(hw, |
1824 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1825 | if (ret_val) | |
1826 | return ret_val; | |
1827 | } | |
2d7edb92 | 1828 | } |
1da177e4 | 1829 | |
2d7edb92 MC |
1830 | /* SW Reset the PHY so all changes take effect */ |
1831 | ret_val = e1000_phy_reset(hw); | |
8fc897b0 | 1832 | if (ret_val) { |
2d7edb92 MC |
1833 | DEBUGOUT("Error Resetting the PHY\n"); |
1834 | return ret_val; | |
1da177e4 LT |
1835 | } |
1836 | ||
2d7edb92 | 1837 | return E1000_SUCCESS; |
1da177e4 LT |
1838 | } |
1839 | ||
2d7edb92 MC |
1840 | /******************************************************************** |
1841 | * Setup auto-negotiation and flow control advertisements, | |
1842 | * and then perform auto-negotiation. | |
1da177e4 LT |
1843 | * |
1844 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 | 1845 | *********************************************************************/ |
64798845 | 1846 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
1da177e4 | 1847 | { |
406874a7 JP |
1848 | s32 ret_val; |
1849 | u16 phy_data; | |
1da177e4 | 1850 | |
2d7edb92 | 1851 | DEBUGFUNC("e1000_copper_link_autoneg"); |
1da177e4 | 1852 | |
2d7edb92 MC |
1853 | /* Perform some bounds checking on the hw->autoneg_advertised |
1854 | * parameter. If this variable is zero, then set it to the default. | |
1855 | */ | |
1856 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1857 | ||
1858 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
1859 | * by the calling code so we set to advertise full capability. | |
1860 | */ | |
8fc897b0 | 1861 | if (hw->autoneg_advertised == 0) |
2d7edb92 MC |
1862 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
1863 | ||
cd94dd0b AK |
1864 | /* IFE phy only supports 10/100 */ |
1865 | if (hw->phy_type == e1000_phy_ife) | |
1866 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; | |
1867 | ||
2d7edb92 MC |
1868 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
1869 | ret_val = e1000_phy_setup_autoneg(hw); | |
8fc897b0 | 1870 | if (ret_val) { |
2d7edb92 MC |
1871 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
1872 | return ret_val; | |
1873 | } | |
1874 | DEBUGOUT("Restarting Auto-Neg\n"); | |
1875 | ||
1876 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
1877 | * the Auto Neg Restart bit in the PHY control register. | |
1878 | */ | |
1879 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
8fc897b0 | 1880 | if (ret_val) |
1da177e4 LT |
1881 | return ret_val; |
1882 | ||
2d7edb92 MC |
1883 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
1884 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
8fc897b0 | 1885 | if (ret_val) |
1da177e4 LT |
1886 | return ret_val; |
1887 | ||
2d7edb92 MC |
1888 | /* Does the user want to wait for Auto-Neg to complete here, or |
1889 | * check at a later time (for example, callback routine). | |
1890 | */ | |
8fc897b0 | 1891 | if (hw->wait_autoneg_complete) { |
2d7edb92 | 1892 | ret_val = e1000_wait_autoneg(hw); |
8fc897b0 | 1893 | if (ret_val) { |
2d7edb92 MC |
1894 | DEBUGOUT("Error while waiting for autoneg to complete\n"); |
1895 | return ret_val; | |
1896 | } | |
1897 | } | |
1898 | ||
c3033b01 | 1899 | hw->get_link_status = true; |
2d7edb92 MC |
1900 | |
1901 | return E1000_SUCCESS; | |
1902 | } | |
1903 | ||
2d7edb92 MC |
1904 | /****************************************************************************** |
1905 | * Config the MAC and the PHY after link is up. | |
1906 | * 1) Set up the MAC to the current PHY speed/duplex | |
1907 | * if we are on 82543. If we | |
1908 | * are on newer silicon, we only need to configure | |
1909 | * collision distance in the Transmit Control Register. | |
1910 | * 2) Set up flow control on the MAC to that established with | |
1911 | * the link partner. | |
76c224bc | 1912 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
2d7edb92 MC |
1913 | * |
1914 | * hw - Struct containing variables accessed by shared code | |
1915 | ******************************************************************************/ | |
64798845 | 1916 | static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) |
2d7edb92 | 1917 | { |
406874a7 | 1918 | s32 ret_val; |
2d7edb92 | 1919 | DEBUGFUNC("e1000_copper_link_postconfig"); |
76c224bc | 1920 | |
8fc897b0 | 1921 | if (hw->mac_type >= e1000_82544) { |
2d7edb92 MC |
1922 | e1000_config_collision_dist(hw); |
1923 | } else { | |
1924 | ret_val = e1000_config_mac_to_phy(hw); | |
8fc897b0 | 1925 | if (ret_val) { |
2d7edb92 MC |
1926 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
1927 | return ret_val; | |
1928 | } | |
1929 | } | |
1930 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 1931 | if (ret_val) { |
2d7edb92 MC |
1932 | DEBUGOUT("Error Configuring Flow Control\n"); |
1933 | return ret_val; | |
1934 | } | |
1935 | ||
1936 | /* Config DSP to improve Giga link quality */ | |
8fc897b0 | 1937 | if (hw->phy_type == e1000_phy_igp) { |
c3033b01 | 1938 | ret_val = e1000_config_dsp_after_link_change(hw, true); |
8fc897b0 | 1939 | if (ret_val) { |
2d7edb92 MC |
1940 | DEBUGOUT("Error Configuring DSP after link up\n"); |
1941 | return ret_val; | |
1942 | } | |
1943 | } | |
76c224bc | 1944 | |
2d7edb92 MC |
1945 | return E1000_SUCCESS; |
1946 | } | |
1947 | ||
1948 | /****************************************************************************** | |
1949 | * Detects which PHY is present and setup the speed and duplex | |
1950 | * | |
1951 | * hw - Struct containing variables accessed by shared code | |
1952 | ******************************************************************************/ | |
64798845 | 1953 | static s32 e1000_setup_copper_link(struct e1000_hw *hw) |
2d7edb92 | 1954 | { |
406874a7 JP |
1955 | s32 ret_val; |
1956 | u16 i; | |
1957 | u16 phy_data; | |
b7cb8c2c | 1958 | u16 reg_data = 0; |
2d7edb92 MC |
1959 | |
1960 | DEBUGFUNC("e1000_setup_copper_link"); | |
1961 | ||
cd94dd0b AK |
1962 | switch (hw->mac_type) { |
1963 | case e1000_80003es2lan: | |
1964 | case e1000_ich8lan: | |
1965 | /* Set the mac to wait the maximum time between each | |
1966 | * iteration and increase the max iterations when | |
1967 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ | |
1968 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); | |
1969 | if (ret_val) | |
1970 | return ret_val; | |
1971 | ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
1972 | if (ret_val) | |
1973 | return ret_val; | |
1974 | reg_data |= 0x3F; | |
1975 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
1976 | if (ret_val) | |
1977 | return ret_val; | |
1978 | default: | |
1979 | break; | |
1980 | } | |
1981 | ||
2d7edb92 MC |
1982 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
1983 | ret_val = e1000_copper_link_preconfig(hw); | |
8fc897b0 | 1984 | if (ret_val) |
2d7edb92 MC |
1985 | return ret_val; |
1986 | ||
6418ecc6 JK |
1987 | switch (hw->mac_type) { |
1988 | case e1000_80003es2lan: | |
cd94dd0b AK |
1989 | /* Kumeran registers are written-only */ |
1990 | reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; | |
6418ecc6 JK |
1991 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
1992 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, | |
1993 | reg_data); | |
1994 | if (ret_val) | |
1995 | return ret_val; | |
1996 | break; | |
1997 | default: | |
1998 | break; | |
1999 | } | |
2000 | ||
2d7edb92 | 2001 | if (hw->phy_type == e1000_phy_igp || |
cd94dd0b | 2002 | hw->phy_type == e1000_phy_igp_3 || |
2d7edb92 MC |
2003 | hw->phy_type == e1000_phy_igp_2) { |
2004 | ret_val = e1000_copper_link_igp_setup(hw); | |
8fc897b0 | 2005 | if (ret_val) |
2d7edb92 MC |
2006 | return ret_val; |
2007 | } else if (hw->phy_type == e1000_phy_m88) { | |
2008 | ret_val = e1000_copper_link_mgp_setup(hw); | |
8fc897b0 | 2009 | if (ret_val) |
2d7edb92 | 2010 | return ret_val; |
6418ecc6 JK |
2011 | } else if (hw->phy_type == e1000_phy_gg82563) { |
2012 | ret_val = e1000_copper_link_ggp_setup(hw); | |
8fc897b0 | 2013 | if (ret_val) |
6418ecc6 | 2014 | return ret_val; |
2d7edb92 MC |
2015 | } |
2016 | ||
8fc897b0 | 2017 | if (hw->autoneg) { |
76c224bc AK |
2018 | /* Setup autoneg and flow control advertisement |
2019 | * and perform autonegotiation */ | |
2d7edb92 | 2020 | ret_val = e1000_copper_link_autoneg(hw); |
8fc897b0 | 2021 | if (ret_val) |
76c224bc | 2022 | return ret_val; |
2d7edb92 MC |
2023 | } else { |
2024 | /* PHY will be set to 10H, 10F, 100H,or 100F | |
2025 | * depending on value from forced_speed_duplex. */ | |
2026 | DEBUGOUT("Forcing speed and duplex\n"); | |
2027 | ret_val = e1000_phy_force_speed_duplex(hw); | |
8fc897b0 | 2028 | if (ret_val) { |
2d7edb92 MC |
2029 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
2030 | return ret_val; | |
2031 | } | |
2032 | } | |
2033 | ||
2034 | /* Check link status. Wait up to 100 microseconds for link to become | |
2035 | * valid. | |
2036 | */ | |
8fc897b0 | 2037 | for (i = 0; i < 10; i++) { |
2d7edb92 | 2038 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
8fc897b0 | 2039 | if (ret_val) |
2d7edb92 MC |
2040 | return ret_val; |
2041 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2042 | if (ret_val) |
2d7edb92 MC |
2043 | return ret_val; |
2044 | ||
8fc897b0 | 2045 | if (phy_data & MII_SR_LINK_STATUS) { |
2d7edb92 MC |
2046 | /* Config the MAC and PHY after link is up */ |
2047 | ret_val = e1000_copper_link_postconfig(hw); | |
8fc897b0 | 2048 | if (ret_val) |
2d7edb92 | 2049 | return ret_val; |
76c224bc | 2050 | |
2d7edb92 MC |
2051 | DEBUGOUT("Valid link established!!!\n"); |
2052 | return E1000_SUCCESS; | |
2053 | } | |
2054 | udelay(10); | |
2055 | } | |
2056 | ||
2057 | DEBUGOUT("Unable to establish link!!!\n"); | |
2058 | return E1000_SUCCESS; | |
2059 | } | |
2060 | ||
6418ecc6 JK |
2061 | /****************************************************************************** |
2062 | * Configure the MAC-to-PHY interface for 10/100Mbps | |
2063 | * | |
2064 | * hw - Struct containing variables accessed by shared code | |
2065 | ******************************************************************************/ | |
64798845 | 2066 | static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex) |
6418ecc6 | 2067 | { |
406874a7 JP |
2068 | s32 ret_val = E1000_SUCCESS; |
2069 | u32 tipg; | |
2070 | u16 reg_data; | |
6418ecc6 JK |
2071 | |
2072 | DEBUGFUNC("e1000_configure_kmrn_for_10_100"); | |
2073 | ||
2074 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
2075 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
2076 | reg_data); | |
2077 | if (ret_val) | |
2078 | return ret_val; | |
2079 | ||
2080 | /* Configure Transmit Inter-Packet Gap */ | |
1dc32918 | 2081 | tipg = er32(TIPG); |
6418ecc6 JK |
2082 | tipg &= ~E1000_TIPG_IPGT_MASK; |
2083 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | |
1dc32918 | 2084 | ew32(TIPG, tipg); |
6418ecc6 | 2085 | |
cd94dd0b AK |
2086 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
2087 | ||
2088 | if (ret_val) | |
2089 | return ret_val; | |
2090 | ||
2091 | if (duplex == HALF_DUPLEX) | |
2092 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
2093 | else | |
2094 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2095 | ||
2096 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
2097 | ||
6418ecc6 JK |
2098 | return ret_val; |
2099 | } | |
2100 | ||
64798845 | 2101 | static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) |
6418ecc6 | 2102 | { |
406874a7 JP |
2103 | s32 ret_val = E1000_SUCCESS; |
2104 | u16 reg_data; | |
2105 | u32 tipg; | |
6418ecc6 JK |
2106 | |
2107 | DEBUGFUNC("e1000_configure_kmrn_for_1000"); | |
2108 | ||
2109 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | |
2110 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
2111 | reg_data); | |
2112 | if (ret_val) | |
2113 | return ret_val; | |
2114 | ||
2115 | /* Configure Transmit Inter-Packet Gap */ | |
1dc32918 | 2116 | tipg = er32(TIPG); |
6418ecc6 JK |
2117 | tipg &= ~E1000_TIPG_IPGT_MASK; |
2118 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
1dc32918 | 2119 | ew32(TIPG, tipg); |
6418ecc6 | 2120 | |
cd94dd0b AK |
2121 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
2122 | ||
2123 | if (ret_val) | |
2124 | return ret_val; | |
2125 | ||
2126 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2127 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
2128 | ||
6418ecc6 JK |
2129 | return ret_val; |
2130 | } | |
2131 | ||
2d7edb92 MC |
2132 | /****************************************************************************** |
2133 | * Configures PHY autoneg and flow control advertisement settings | |
2134 | * | |
2135 | * hw - Struct containing variables accessed by shared code | |
2136 | ******************************************************************************/ | |
64798845 | 2137 | s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
2d7edb92 | 2138 | { |
406874a7 JP |
2139 | s32 ret_val; |
2140 | u16 mii_autoneg_adv_reg; | |
2141 | u16 mii_1000t_ctrl_reg; | |
2d7edb92 MC |
2142 | |
2143 | DEBUGFUNC("e1000_phy_setup_autoneg"); | |
2144 | ||
2145 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
2146 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
8fc897b0 | 2147 | if (ret_val) |
2d7edb92 MC |
2148 | return ret_val; |
2149 | ||
cd94dd0b AK |
2150 | if (hw->phy_type != e1000_phy_ife) { |
2151 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
2152 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
2153 | if (ret_val) | |
2154 | return ret_val; | |
2155 | } else | |
2156 | mii_1000t_ctrl_reg=0; | |
2d7edb92 MC |
2157 | |
2158 | /* Need to parse both autoneg_advertised and fc and set up | |
2159 | * the appropriate PHY registers. First we will parse for | |
1da177e4 LT |
2160 | * autoneg_advertised software override. Since we can advertise |
2161 | * a plethora of combinations, we need to check each bit | |
2162 | * individually. | |
2163 | */ | |
2164 | ||
2165 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
2166 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
2167 | * the 1000Base-T Control Register (Address 9). | |
2168 | */ | |
2169 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
2170 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
2171 | ||
2172 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); | |
2173 | ||
2174 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
8fc897b0 | 2175 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
1da177e4 LT |
2176 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
2177 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
2178 | } | |
2179 | ||
2180 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
8fc897b0 | 2181 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
1da177e4 LT |
2182 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
2183 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
2184 | } | |
2185 | ||
2186 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
8fc897b0 | 2187 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
1da177e4 LT |
2188 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
2189 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
2190 | } | |
2191 | ||
2192 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
8fc897b0 | 2193 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
1da177e4 LT |
2194 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
2195 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
2196 | } | |
2197 | ||
2198 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
8fc897b0 | 2199 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
1da177e4 LT |
2200 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
2201 | } | |
2202 | ||
2203 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
8fc897b0 | 2204 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
1da177e4 LT |
2205 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
2206 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
cd94dd0b AK |
2207 | if (hw->phy_type == e1000_phy_ife) { |
2208 | DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); | |
2209 | } | |
1da177e4 LT |
2210 | } |
2211 | ||
2212 | /* Check for a software override of the flow control settings, and | |
2213 | * setup the PHY advertisement registers accordingly. If | |
2214 | * auto-negotiation is enabled, then software will have to set the | |
2215 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
2216 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
2217 | * | |
2218 | * The possible values of the "fc" parameter are: | |
2219 | * 0: Flow control is completely disabled | |
2220 | * 1: Rx flow control is enabled (we can receive pause frames | |
2221 | * but not send pause frames). | |
2222 | * 2: Tx flow control is enabled (we can send pause frames | |
2223 | * but we do not support receiving pause frames). | |
2224 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
2225 | * other: No software override. The flow control configuration | |
2226 | * in the EEPROM is used. | |
2227 | */ | |
2228 | switch (hw->fc) { | |
11241b10 | 2229 | case E1000_FC_NONE: /* 0 */ |
1da177e4 LT |
2230 | /* Flow control (RX & TX) is completely disabled by a |
2231 | * software over-ride. | |
2232 | */ | |
2233 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2234 | break; | |
11241b10 | 2235 | case E1000_FC_RX_PAUSE: /* 1 */ |
1da177e4 LT |
2236 | /* RX Flow control is enabled, and TX Flow control is |
2237 | * disabled, by a software over-ride. | |
2238 | */ | |
2239 | /* Since there really isn't a way to advertise that we are | |
2240 | * capable of RX Pause ONLY, we will advertise that we | |
2241 | * support both symmetric and asymmetric RX PAUSE. Later | |
2242 | * (in e1000_config_fc_after_link_up) we will disable the | |
2243 | *hw's ability to send PAUSE frames. | |
2244 | */ | |
2245 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2246 | break; | |
11241b10 | 2247 | case E1000_FC_TX_PAUSE: /* 2 */ |
1da177e4 LT |
2248 | /* TX Flow control is enabled, and RX Flow control is |
2249 | * disabled, by a software over-ride. | |
2250 | */ | |
2251 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
2252 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
2253 | break; | |
11241b10 | 2254 | case E1000_FC_FULL: /* 3 */ |
1da177e4 LT |
2255 | /* Flow control (both RX and TX) is enabled by a software |
2256 | * over-ride. | |
2257 | */ | |
2258 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
2259 | break; | |
2260 | default: | |
2261 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2262 | return -E1000_ERR_CONFIG; | |
2263 | } | |
2264 | ||
2265 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
8fc897b0 | 2266 | if (ret_val) |
1da177e4 LT |
2267 | return ret_val; |
2268 | ||
2269 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
2270 | ||
cd94dd0b AK |
2271 | if (hw->phy_type != e1000_phy_ife) { |
2272 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | |
2273 | if (ret_val) | |
2274 | return ret_val; | |
2275 | } | |
1da177e4 LT |
2276 | |
2277 | return E1000_SUCCESS; | |
2278 | } | |
2279 | ||
2280 | /****************************************************************************** | |
2281 | * Force PHY speed and duplex settings to hw->forced_speed_duplex | |
2282 | * | |
2283 | * hw - Struct containing variables accessed by shared code | |
2284 | ******************************************************************************/ | |
64798845 | 2285 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
1da177e4 | 2286 | { |
406874a7 JP |
2287 | u32 ctrl; |
2288 | s32 ret_val; | |
2289 | u16 mii_ctrl_reg; | |
2290 | u16 mii_status_reg; | |
2291 | u16 phy_data; | |
2292 | u16 i; | |
1da177e4 LT |
2293 | |
2294 | DEBUGFUNC("e1000_phy_force_speed_duplex"); | |
2295 | ||
2296 | /* Turn off Flow control if we are forcing speed and duplex. */ | |
11241b10 | 2297 | hw->fc = E1000_FC_NONE; |
1da177e4 LT |
2298 | |
2299 | DEBUGOUT1("hw->fc = %d\n", hw->fc); | |
2300 | ||
2301 | /* Read the Device Control Register. */ | |
1dc32918 | 2302 | ctrl = er32(CTRL); |
1da177e4 LT |
2303 | |
2304 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ | |
2305 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2306 | ctrl &= ~(DEVICE_SPEED_MASK); | |
2307 | ||
2308 | /* Clear the Auto Speed Detect Enable bit. */ | |
2309 | ctrl &= ~E1000_CTRL_ASDE; | |
2310 | ||
2311 | /* Read the MII Control Register. */ | |
2312 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); | |
8fc897b0 | 2313 | if (ret_val) |
1da177e4 LT |
2314 | return ret_val; |
2315 | ||
2316 | /* We need to disable autoneg in order to force link and duplex. */ | |
2317 | ||
2318 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; | |
2319 | ||
2320 | /* Are we forcing Full or Half Duplex? */ | |
8fc897b0 AK |
2321 | if (hw->forced_speed_duplex == e1000_100_full || |
2322 | hw->forced_speed_duplex == e1000_10_full) { | |
1da177e4 LT |
2323 | /* We want to force full duplex so we SET the full duplex bits in the |
2324 | * Device and MII Control Registers. | |
2325 | */ | |
2326 | ctrl |= E1000_CTRL_FD; | |
2327 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; | |
2328 | DEBUGOUT("Full Duplex\n"); | |
2329 | } else { | |
2330 | /* We want to force half duplex so we CLEAR the full duplex bits in | |
2331 | * the Device and MII Control Registers. | |
2332 | */ | |
2333 | ctrl &= ~E1000_CTRL_FD; | |
2334 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; | |
2335 | DEBUGOUT("Half Duplex\n"); | |
2336 | } | |
2337 | ||
2338 | /* Are we forcing 100Mbps??? */ | |
8fc897b0 | 2339 | if (hw->forced_speed_duplex == e1000_100_full || |
1da177e4 LT |
2340 | hw->forced_speed_duplex == e1000_100_half) { |
2341 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ | |
2342 | ctrl |= E1000_CTRL_SPD_100; | |
2343 | mii_ctrl_reg |= MII_CR_SPEED_100; | |
2344 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
2345 | DEBUGOUT("Forcing 100mb "); | |
2346 | } else { | |
2347 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ | |
2348 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
2349 | mii_ctrl_reg |= MII_CR_SPEED_10; | |
2350 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
2351 | DEBUGOUT("Forcing 10mb "); | |
2352 | } | |
2353 | ||
2354 | e1000_config_collision_dist(hw); | |
2355 | ||
2356 | /* Write the configured values back to the Device Control Reg. */ | |
1dc32918 | 2357 | ew32(CTRL, ctrl); |
1da177e4 | 2358 | |
6418ecc6 JK |
2359 | if ((hw->phy_type == e1000_phy_m88) || |
2360 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 | 2361 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
8fc897b0 | 2362 | if (ret_val) |
1da177e4 LT |
2363 | return ret_val; |
2364 | ||
2365 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
2366 | * forced whenever speed are duplex are forced. | |
2367 | */ | |
2368 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
2369 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2370 | if (ret_val) |
1da177e4 LT |
2371 | return ret_val; |
2372 | ||
2373 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | |
2374 | ||
2375 | /* Need to reset the PHY or these changes will be ignored */ | |
2376 | mii_ctrl_reg |= MII_CR_RESET; | |
90fb5135 | 2377 | |
cd94dd0b AK |
2378 | /* Disable MDI-X support for 10/100 */ |
2379 | } else if (hw->phy_type == e1000_phy_ife) { | |
2380 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | |
2381 | if (ret_val) | |
2382 | return ret_val; | |
2383 | ||
2384 | phy_data &= ~IFE_PMC_AUTO_MDIX; | |
2385 | phy_data &= ~IFE_PMC_FORCE_MDIX; | |
2386 | ||
2387 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); | |
2388 | if (ret_val) | |
2389 | return ret_val; | |
90fb5135 | 2390 | |
1da177e4 LT |
2391 | } else { |
2392 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
2393 | * forced whenever speed or duplex are forced. | |
2394 | */ | |
2395 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
8fc897b0 | 2396 | if (ret_val) |
1da177e4 LT |
2397 | return ret_val; |
2398 | ||
2399 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
2400 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2401 | ||
2402 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
8fc897b0 | 2403 | if (ret_val) |
1da177e4 LT |
2404 | return ret_val; |
2405 | } | |
2406 | ||
2407 | /* Write back the modified PHY MII control register. */ | |
2408 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); | |
8fc897b0 | 2409 | if (ret_val) |
1da177e4 LT |
2410 | return ret_val; |
2411 | ||
2412 | udelay(1); | |
2413 | ||
2414 | /* The wait_autoneg_complete flag may be a little misleading here. | |
2415 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | |
2416 | * But we do want to delay for a period while forcing only so we | |
2417 | * don't generate false No Link messages. So we will wait here | |
2418 | * only if the user has set wait_autoneg_complete to 1, which is | |
2419 | * the default. | |
2420 | */ | |
8fc897b0 | 2421 | if (hw->wait_autoneg_complete) { |
1da177e4 LT |
2422 | /* We will wait for autoneg to complete. */ |
2423 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); | |
2424 | mii_status_reg = 0; | |
2425 | ||
2426 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
8fc897b0 | 2427 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
2428 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2429 | * to be set. | |
2430 | */ | |
2431 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2432 | if (ret_val) |
1da177e4 LT |
2433 | return ret_val; |
2434 | ||
2435 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2436 | if (ret_val) |
1da177e4 LT |
2437 | return ret_val; |
2438 | ||
8fc897b0 | 2439 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
f8ec4733 | 2440 | msleep(100); |
1da177e4 | 2441 | } |
8fc897b0 | 2442 | if ((i == 0) && |
6418ecc6 JK |
2443 | ((hw->phy_type == e1000_phy_m88) || |
2444 | (hw->phy_type == e1000_phy_gg82563))) { | |
1da177e4 LT |
2445 | /* We didn't get link. Reset the DSP and wait again for link. */ |
2446 | ret_val = e1000_phy_reset_dsp(hw); | |
8fc897b0 | 2447 | if (ret_val) { |
1da177e4 LT |
2448 | DEBUGOUT("Error Resetting PHY DSP\n"); |
2449 | return ret_val; | |
2450 | } | |
2451 | } | |
2452 | /* This loop will early-out if the link condition has been met. */ | |
8fc897b0 AK |
2453 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
2454 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | |
f8ec4733 | 2455 | msleep(100); |
1da177e4 LT |
2456 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2457 | * to be set. | |
2458 | */ | |
2459 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2460 | if (ret_val) |
1da177e4 LT |
2461 | return ret_val; |
2462 | ||
2463 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2464 | if (ret_val) |
1da177e4 LT |
2465 | return ret_val; |
2466 | } | |
2467 | } | |
2468 | ||
2469 | if (hw->phy_type == e1000_phy_m88) { | |
2470 | /* Because we reset the PHY above, we need to re-force TX_CLK in the | |
2471 | * Extended PHY Specific Control Register to 25MHz clock. This value | |
2472 | * defaults back to a 2.5MHz clock when the PHY is reset. | |
2473 | */ | |
2474 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 2475 | if (ret_val) |
1da177e4 LT |
2476 | return ret_val; |
2477 | ||
2478 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
2479 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2480 | if (ret_val) |
1da177e4 LT |
2481 | return ret_val; |
2482 | ||
2483 | /* In addition, because of the s/w reset above, we need to enable CRS on | |
2484 | * TX. This must be set for both full and half duplex operation. | |
2485 | */ | |
2486 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 2487 | if (ret_val) |
1da177e4 LT |
2488 | return ret_val; |
2489 | ||
2490 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
2491 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
8fc897b0 | 2492 | if (ret_val) |
1da177e4 LT |
2493 | return ret_val; |
2494 | ||
8fc897b0 AK |
2495 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
2496 | (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || | |
2497 | hw->forced_speed_duplex == e1000_10_half)) { | |
1da177e4 | 2498 | ret_val = e1000_polarity_reversal_workaround(hw); |
8fc897b0 | 2499 | if (ret_val) |
1da177e4 LT |
2500 | return ret_val; |
2501 | } | |
6418ecc6 JK |
2502 | } else if (hw->phy_type == e1000_phy_gg82563) { |
2503 | /* The TX_CLK of the Extended PHY Specific Control Register defaults | |
2504 | * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if | |
2505 | * we're not in a forced 10/duplex configuration. */ | |
2506 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
2507 | if (ret_val) | |
2508 | return ret_val; | |
2509 | ||
2510 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
2511 | if ((hw->forced_speed_duplex == e1000_10_full) || | |
2512 | (hw->forced_speed_duplex == e1000_10_half)) | |
2513 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; | |
2514 | else | |
2515 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; | |
2516 | ||
2517 | /* Also due to the reset, we need to enable CRS on Tx. */ | |
2518 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
2519 | ||
2520 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
2521 | if (ret_val) | |
2522 | return ret_val; | |
1da177e4 LT |
2523 | } |
2524 | return E1000_SUCCESS; | |
2525 | } | |
2526 | ||
2527 | /****************************************************************************** | |
2528 | * Sets the collision distance in the Transmit Control register | |
2529 | * | |
2530 | * hw - Struct containing variables accessed by shared code | |
2531 | * | |
2532 | * Link should have been established previously. Reads the speed and duplex | |
2533 | * information from the Device Status register. | |
2534 | ******************************************************************************/ | |
64798845 | 2535 | void e1000_config_collision_dist(struct e1000_hw *hw) |
1da177e4 | 2536 | { |
406874a7 | 2537 | u32 tctl, coll_dist; |
1da177e4 LT |
2538 | |
2539 | DEBUGFUNC("e1000_config_collision_dist"); | |
2540 | ||
0fadb059 JK |
2541 | if (hw->mac_type < e1000_82543) |
2542 | coll_dist = E1000_COLLISION_DISTANCE_82542; | |
2543 | else | |
2544 | coll_dist = E1000_COLLISION_DISTANCE; | |
2545 | ||
1dc32918 | 2546 | tctl = er32(TCTL); |
1da177e4 LT |
2547 | |
2548 | tctl &= ~E1000_TCTL_COLD; | |
0fadb059 | 2549 | tctl |= coll_dist << E1000_COLD_SHIFT; |
1da177e4 | 2550 | |
1dc32918 JP |
2551 | ew32(TCTL, tctl); |
2552 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
2553 | } |
2554 | ||
2555 | /****************************************************************************** | |
2556 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
2557 | * | |
2558 | * hw - Struct containing variables accessed by shared code | |
2559 | * mii_reg - data to write to the MII control register | |
2560 | * | |
2561 | * The contents of the PHY register containing the needed information need to | |
2562 | * be passed in. | |
2563 | ******************************************************************************/ | |
64798845 | 2564 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) |
1da177e4 | 2565 | { |
406874a7 JP |
2566 | u32 ctrl; |
2567 | s32 ret_val; | |
2568 | u16 phy_data; | |
1da177e4 LT |
2569 | |
2570 | DEBUGFUNC("e1000_config_mac_to_phy"); | |
2571 | ||
76c224bc | 2572 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
2d7edb92 MC |
2573 | * MAC speed/duplex configuration.*/ |
2574 | if (hw->mac_type >= e1000_82544) | |
2575 | return E1000_SUCCESS; | |
2576 | ||
1da177e4 LT |
2577 | /* Read the Device Control Register and set the bits to Force Speed |
2578 | * and Duplex. | |
2579 | */ | |
1dc32918 | 2580 | ctrl = er32(CTRL); |
1da177e4 LT |
2581 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
2582 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); | |
2583 | ||
2584 | /* Set up duplex in the Device Control and Transmit Control | |
2585 | * registers depending on negotiated values. | |
2586 | */ | |
2d7edb92 | 2587 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
8fc897b0 | 2588 | if (ret_val) |
2d7edb92 | 2589 | return ret_val; |
1da177e4 | 2590 | |
8fc897b0 | 2591 | if (phy_data & M88E1000_PSSR_DPLX) |
2d7edb92 | 2592 | ctrl |= E1000_CTRL_FD; |
76c224bc | 2593 | else |
2d7edb92 | 2594 | ctrl &= ~E1000_CTRL_FD; |
1da177e4 | 2595 | |
2d7edb92 | 2596 | e1000_config_collision_dist(hw); |
1da177e4 | 2597 | |
2d7edb92 MC |
2598 | /* Set up speed in the Device Control register depending on |
2599 | * negotiated values. | |
2600 | */ | |
8fc897b0 | 2601 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
2d7edb92 | 2602 | ctrl |= E1000_CTRL_SPD_1000; |
8fc897b0 | 2603 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
2d7edb92 | 2604 | ctrl |= E1000_CTRL_SPD_100; |
1da177e4 | 2605 | |
1da177e4 | 2606 | /* Write the configured values back to the Device Control Reg. */ |
1dc32918 | 2607 | ew32(CTRL, ctrl); |
1da177e4 LT |
2608 | return E1000_SUCCESS; |
2609 | } | |
2610 | ||
2611 | /****************************************************************************** | |
2612 | * Forces the MAC's flow control settings. | |
2613 | * | |
2614 | * hw - Struct containing variables accessed by shared code | |
2615 | * | |
2616 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
2617 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
2618 | * software when a Copper PHY is used because autonegotiation is managed | |
2619 | * by the PHY rather than the MAC. Software must also configure these | |
2620 | * bits when link is forced on a fiber connection. | |
2621 | *****************************************************************************/ | |
64798845 | 2622 | s32 e1000_force_mac_fc(struct e1000_hw *hw) |
1da177e4 | 2623 | { |
406874a7 | 2624 | u32 ctrl; |
1da177e4 LT |
2625 | |
2626 | DEBUGFUNC("e1000_force_mac_fc"); | |
2627 | ||
2628 | /* Get the current configuration of the Device Control Register */ | |
1dc32918 | 2629 | ctrl = er32(CTRL); |
1da177e4 LT |
2630 | |
2631 | /* Because we didn't get link via the internal auto-negotiation | |
2632 | * mechanism (we either forced link or we got link via PHY | |
2633 | * auto-neg), we have to manually enable/disable transmit an | |
2634 | * receive flow control. | |
2635 | * | |
2636 | * The "Case" statement below enables/disable flow control | |
2637 | * according to the "hw->fc" parameter. | |
2638 | * | |
2639 | * The possible values of the "fc" parameter are: | |
2640 | * 0: Flow control is completely disabled | |
2641 | * 1: Rx flow control is enabled (we can receive pause | |
2642 | * frames but not send pause frames). | |
2643 | * 2: Tx flow control is enabled (we can send pause frames | |
2644 | * frames but we do not receive pause frames). | |
2645 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
2646 | * other: No other values should be possible at this point. | |
2647 | */ | |
2648 | ||
2649 | switch (hw->fc) { | |
11241b10 | 2650 | case E1000_FC_NONE: |
1da177e4 LT |
2651 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
2652 | break; | |
11241b10 | 2653 | case E1000_FC_RX_PAUSE: |
1da177e4 LT |
2654 | ctrl &= (~E1000_CTRL_TFCE); |
2655 | ctrl |= E1000_CTRL_RFCE; | |
2656 | break; | |
11241b10 | 2657 | case E1000_FC_TX_PAUSE: |
1da177e4 LT |
2658 | ctrl &= (~E1000_CTRL_RFCE); |
2659 | ctrl |= E1000_CTRL_TFCE; | |
2660 | break; | |
11241b10 | 2661 | case E1000_FC_FULL: |
1da177e4 LT |
2662 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
2663 | break; | |
2664 | default: | |
2665 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2666 | return -E1000_ERR_CONFIG; | |
2667 | } | |
2668 | ||
2669 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
8fc897b0 | 2670 | if (hw->mac_type == e1000_82542_rev2_0) |
1da177e4 LT |
2671 | ctrl &= (~E1000_CTRL_TFCE); |
2672 | ||
1dc32918 | 2673 | ew32(CTRL, ctrl); |
1da177e4 LT |
2674 | return E1000_SUCCESS; |
2675 | } | |
2676 | ||
2677 | /****************************************************************************** | |
2678 | * Configures flow control settings after link is established | |
2679 | * | |
2680 | * hw - Struct containing variables accessed by shared code | |
2681 | * | |
2682 | * Should be called immediately after a valid link has been established. | |
2683 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
2684 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
2685 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
2686 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
2687 | *****************************************************************************/ | |
64798845 | 2688 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
1da177e4 | 2689 | { |
406874a7 JP |
2690 | s32 ret_val; |
2691 | u16 mii_status_reg; | |
2692 | u16 mii_nway_adv_reg; | |
2693 | u16 mii_nway_lp_ability_reg; | |
2694 | u16 speed; | |
2695 | u16 duplex; | |
1da177e4 LT |
2696 | |
2697 | DEBUGFUNC("e1000_config_fc_after_link_up"); | |
2698 | ||
2699 | /* Check for the case where we have fiber media and auto-neg failed | |
2700 | * so we had to force link. In this case, we need to force the | |
2701 | * configuration of the MAC to match the "fc" parameter. | |
2702 | */ | |
8fc897b0 AK |
2703 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
2704 | ((hw->media_type == e1000_media_type_internal_serdes) && | |
2705 | (hw->autoneg_failed)) || | |
2706 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { | |
1da177e4 | 2707 | ret_val = e1000_force_mac_fc(hw); |
8fc897b0 | 2708 | if (ret_val) { |
1da177e4 LT |
2709 | DEBUGOUT("Error forcing flow control settings\n"); |
2710 | return ret_val; | |
2711 | } | |
2712 | } | |
2713 | ||
2714 | /* Check for the case where we have copper media and auto-neg is | |
2715 | * enabled. In this case, we need to check and see if Auto-Neg | |
2716 | * has completed, and if so, how the PHY and link partner has | |
2717 | * flow control configured. | |
2718 | */ | |
8fc897b0 | 2719 | if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
1da177e4 LT |
2720 | /* Read the MII Status Register and check to see if AutoNeg |
2721 | * has completed. We read this twice because this reg has | |
2722 | * some "sticky" (latched) bits. | |
2723 | */ | |
2724 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2725 | if (ret_val) |
1da177e4 LT |
2726 | return ret_val; |
2727 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 2728 | if (ret_val) |
1da177e4 LT |
2729 | return ret_val; |
2730 | ||
8fc897b0 | 2731 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
1da177e4 LT |
2732 | /* The AutoNeg process has completed, so we now need to |
2733 | * read both the Auto Negotiation Advertisement Register | |
2734 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
2735 | * Register (Address 5) to determine how flow control was | |
2736 | * negotiated. | |
2737 | */ | |
2738 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, | |
2739 | &mii_nway_adv_reg); | |
8fc897b0 | 2740 | if (ret_val) |
1da177e4 LT |
2741 | return ret_val; |
2742 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, | |
2743 | &mii_nway_lp_ability_reg); | |
8fc897b0 | 2744 | if (ret_val) |
1da177e4 LT |
2745 | return ret_val; |
2746 | ||
2747 | /* Two bits in the Auto Negotiation Advertisement Register | |
2748 | * (Address 4) and two bits in the Auto Negotiation Base | |
2749 | * Page Ability Register (Address 5) determine flow control | |
2750 | * for both the PHY and the link partner. The following | |
2751 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
2752 | * 1999, describes these PAUSE resolution bits and how flow | |
2753 | * control is determined based upon these settings. | |
2754 | * NOTE: DC = Don't Care | |
2755 | * | |
2756 | * LOCAL DEVICE | LINK PARTNER | |
2757 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
2758 | *-------|---------|-------|---------|-------------------- | |
11241b10 JK |
2759 | * 0 | 0 | DC | DC | E1000_FC_NONE |
2760 | * 0 | 1 | 0 | DC | E1000_FC_NONE | |
2761 | * 0 | 1 | 1 | 0 | E1000_FC_NONE | |
2762 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE | |
2763 | * 1 | 0 | 0 | DC | E1000_FC_NONE | |
2764 | * 1 | DC | 1 | DC | E1000_FC_FULL | |
2765 | * 1 | 1 | 0 | 0 | E1000_FC_NONE | |
2766 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE | |
1da177e4 LT |
2767 | * |
2768 | */ | |
2769 | /* Are both PAUSE bits set to 1? If so, this implies | |
2770 | * Symmetric Flow Control is enabled at both ends. The | |
2771 | * ASM_DIR bits are irrelevant per the spec. | |
2772 | * | |
2773 | * For Symmetric Flow Control: | |
2774 | * | |
2775 | * LOCAL DEVICE | LINK PARTNER | |
2776 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2777 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2778 | * 1 | DC | 1 | DC | E1000_FC_FULL |
1da177e4 LT |
2779 | * |
2780 | */ | |
8fc897b0 AK |
2781 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2782 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
1da177e4 LT |
2783 | /* Now we need to check if the user selected RX ONLY |
2784 | * of pause frames. In this case, we had to advertise | |
2785 | * FULL flow control because we could not advertise RX | |
2786 | * ONLY. Hence, we must now check to see if we need to | |
2787 | * turn OFF the TRANSMISSION of PAUSE frames. | |
2788 | */ | |
11241b10 JK |
2789 | if (hw->original_fc == E1000_FC_FULL) { |
2790 | hw->fc = E1000_FC_FULL; | |
a42a507c | 2791 | DEBUGOUT("Flow Control = FULL.\n"); |
1da177e4 | 2792 | } else { |
11241b10 | 2793 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2794 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2795 | } |
2796 | } | |
2797 | /* For receiving PAUSE frames ONLY. | |
2798 | * | |
2799 | * LOCAL DEVICE | LINK PARTNER | |
2800 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2801 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2802 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
1da177e4 LT |
2803 | * |
2804 | */ | |
8fc897b0 AK |
2805 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2806 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2807 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2808 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
11241b10 | 2809 | hw->fc = E1000_FC_TX_PAUSE; |
a42a507c | 2810 | DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
1da177e4 LT |
2811 | } |
2812 | /* For transmitting PAUSE frames ONLY. | |
2813 | * | |
2814 | * LOCAL DEVICE | LINK PARTNER | |
2815 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2816 | *-------|---------|-------|---------|-------------------- | |
11241b10 | 2817 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
1da177e4 LT |
2818 | * |
2819 | */ | |
8fc897b0 AK |
2820 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2821 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2822 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2823 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
11241b10 | 2824 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2825 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2826 | } |
2827 | /* Per the IEEE spec, at this point flow control should be | |
2828 | * disabled. However, we want to consider that we could | |
2829 | * be connected to a legacy switch that doesn't advertise | |
2830 | * desired flow control, but can be forced on the link | |
2831 | * partner. So if we advertised no flow control, that is | |
2832 | * what we will resolve to. If we advertised some kind of | |
2833 | * receive capability (Rx Pause Only or Full Flow Control) | |
2834 | * and the link partner advertised none, we will configure | |
2835 | * ourselves to enable Rx Flow Control only. We can do | |
2836 | * this safely for two reasons: If the link partner really | |
2837 | * didn't want flow control enabled, and we enable Rx, no | |
2838 | * harm done since we won't be receiving any PAUSE frames | |
2839 | * anyway. If the intent on the link partner was to have | |
2840 | * flow control enabled, then by us enabling RX only, we | |
2841 | * can at least receive pause frames and process them. | |
2842 | * This is a good idea because in most cases, since we are | |
2843 | * predominantly a server NIC, more times than not we will | |
2844 | * be asked to delay transmission of packets than asking | |
2845 | * our link partner to pause transmission of frames. | |
2846 | */ | |
11241b10 JK |
2847 | else if ((hw->original_fc == E1000_FC_NONE || |
2848 | hw->original_fc == E1000_FC_TX_PAUSE) || | |
8fc897b0 | 2849 | hw->fc_strict_ieee) { |
11241b10 | 2850 | hw->fc = E1000_FC_NONE; |
a42a507c | 2851 | DEBUGOUT("Flow Control = NONE.\n"); |
1da177e4 | 2852 | } else { |
11241b10 | 2853 | hw->fc = E1000_FC_RX_PAUSE; |
a42a507c | 2854 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2855 | } |
2856 | ||
2857 | /* Now we need to do one last check... If we auto- | |
2858 | * negotiated to HALF DUPLEX, flow control should not be | |
2859 | * enabled per IEEE 802.3 spec. | |
2860 | */ | |
2861 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
8fc897b0 | 2862 | if (ret_val) { |
1da177e4 LT |
2863 | DEBUGOUT("Error getting link speed and duplex\n"); |
2864 | return ret_val; | |
2865 | } | |
2866 | ||
8fc897b0 | 2867 | if (duplex == HALF_DUPLEX) |
11241b10 | 2868 | hw->fc = E1000_FC_NONE; |
1da177e4 LT |
2869 | |
2870 | /* Now we call a subroutine to actually force the MAC | |
2871 | * controller to use the correct flow control settings. | |
2872 | */ | |
2873 | ret_val = e1000_force_mac_fc(hw); | |
8fc897b0 | 2874 | if (ret_val) { |
1da177e4 LT |
2875 | DEBUGOUT("Error forcing flow control settings\n"); |
2876 | return ret_val; | |
2877 | } | |
2878 | } else { | |
a42a507c | 2879 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
1da177e4 LT |
2880 | } |
2881 | } | |
2882 | return E1000_SUCCESS; | |
2883 | } | |
2884 | ||
2885 | /****************************************************************************** | |
2886 | * Checks to see if the link status of the hardware has changed. | |
2887 | * | |
2888 | * hw - Struct containing variables accessed by shared code | |
2889 | * | |
2890 | * Called by any function that needs to check the link status of the adapter. | |
2891 | *****************************************************************************/ | |
64798845 | 2892 | s32 e1000_check_for_link(struct e1000_hw *hw) |
1da177e4 | 2893 | { |
406874a7 JP |
2894 | u32 rxcw = 0; |
2895 | u32 ctrl; | |
2896 | u32 status; | |
2897 | u32 rctl; | |
2898 | u32 icr; | |
2899 | u32 signal = 0; | |
2900 | s32 ret_val; | |
2901 | u16 phy_data; | |
1da177e4 LT |
2902 | |
2903 | DEBUGFUNC("e1000_check_for_link"); | |
2904 | ||
1dc32918 JP |
2905 | ctrl = er32(CTRL); |
2906 | status = er32(STATUS); | |
1da177e4 LT |
2907 | |
2908 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be | |
2909 | * set when the optics detect a signal. On older adapters, it will be | |
2910 | * cleared when there is a signal. This applies to fiber media only. | |
2911 | */ | |
8fc897b0 AK |
2912 | if ((hw->media_type == e1000_media_type_fiber) || |
2913 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
1dc32918 | 2914 | rxcw = er32(RXCW); |
1da177e4 | 2915 | |
8fc897b0 | 2916 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 | 2917 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
8fc897b0 | 2918 | if (status & E1000_STATUS_LU) |
c3033b01 | 2919 | hw->get_link_status = false; |
1da177e4 LT |
2920 | } |
2921 | } | |
2922 | ||
2923 | /* If we have a copper PHY then we only want to go out to the PHY | |
2924 | * registers to see if Auto-Neg has completed and/or if our link | |
2925 | * status has changed. The get_link_status flag will be set if we | |
2926 | * receive a Link Status Change interrupt or we have Rx Sequence | |
2927 | * Errors. | |
2928 | */ | |
8fc897b0 | 2929 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
1da177e4 LT |
2930 | /* First we want to see if the MII Status Register reports |
2931 | * link. If so, then we want to get the current speed/duplex | |
2932 | * of the PHY. | |
2933 | * Read the register twice since the link bit is sticky. | |
2934 | */ | |
2935 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2936 | if (ret_val) |
1da177e4 LT |
2937 | return ret_val; |
2938 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 2939 | if (ret_val) |
1da177e4 LT |
2940 | return ret_val; |
2941 | ||
8fc897b0 | 2942 | if (phy_data & MII_SR_LINK_STATUS) { |
c3033b01 | 2943 | hw->get_link_status = false; |
1da177e4 LT |
2944 | /* Check if there was DownShift, must be checked immediately after |
2945 | * link-up */ | |
2946 | e1000_check_downshift(hw); | |
2947 | ||
2948 | /* If we are on 82544 or 82543 silicon and speed/duplex | |
2949 | * are forced to 10H or 10F, then we will implement the polarity | |
2950 | * reversal workaround. We disable interrupts first, and upon | |
2951 | * returning, place the devices interrupt state to its previous | |
2952 | * value except for the link status change interrupt which will | |
2953 | * happen due to the execution of this workaround. | |
2954 | */ | |
2955 | ||
8fc897b0 AK |
2956 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
2957 | (!hw->autoneg) && | |
2958 | (hw->forced_speed_duplex == e1000_10_full || | |
2959 | hw->forced_speed_duplex == e1000_10_half)) { | |
1dc32918 | 2960 | ew32(IMC, 0xffffffff); |
1da177e4 | 2961 | ret_val = e1000_polarity_reversal_workaround(hw); |
1dc32918 JP |
2962 | icr = er32(ICR); |
2963 | ew32(ICS, (icr & ~E1000_ICS_LSC)); | |
2964 | ew32(IMS, IMS_ENABLE_MASK); | |
1da177e4 LT |
2965 | } |
2966 | ||
2967 | } else { | |
2968 | /* No link detected */ | |
c3033b01 | 2969 | e1000_config_dsp_after_link_change(hw, false); |
1da177e4 LT |
2970 | return 0; |
2971 | } | |
2972 | ||
2973 | /* If we are forcing speed/duplex, then we simply return since | |
2974 | * we have already determined whether we have link or not. | |
2975 | */ | |
8fc897b0 | 2976 | if (!hw->autoneg) return -E1000_ERR_CONFIG; |
1da177e4 LT |
2977 | |
2978 | /* optimize the dsp settings for the igp phy */ | |
c3033b01 | 2979 | e1000_config_dsp_after_link_change(hw, true); |
1da177e4 LT |
2980 | |
2981 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
2982 | * have Si on board that is 82544 or newer, Auto | |
2983 | * Speed Detection takes care of MAC speed/duplex | |
2984 | * configuration. So we only need to configure Collision | |
2985 | * Distance in the MAC. Otherwise, we need to force | |
2986 | * speed/duplex on the MAC to the current PHY speed/duplex | |
2987 | * settings. | |
2988 | */ | |
8fc897b0 | 2989 | if (hw->mac_type >= e1000_82544) |
1da177e4 LT |
2990 | e1000_config_collision_dist(hw); |
2991 | else { | |
2992 | ret_val = e1000_config_mac_to_phy(hw); | |
8fc897b0 | 2993 | if (ret_val) { |
1da177e4 LT |
2994 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
2995 | return ret_val; | |
2996 | } | |
2997 | } | |
2998 | ||
2999 | /* Configure Flow Control now that Auto-Neg has completed. First, we | |
3000 | * need to restore the desired flow control settings because we may | |
3001 | * have had to re-autoneg with a different link partner. | |
3002 | */ | |
3003 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 3004 | if (ret_val) { |
1da177e4 LT |
3005 | DEBUGOUT("Error configuring flow control\n"); |
3006 | return ret_val; | |
3007 | } | |
3008 | ||
3009 | /* At this point we know that we are on copper and we have | |
3010 | * auto-negotiated link. These are conditions for checking the link | |
3011 | * partner capability register. We use the link speed to determine if | |
3012 | * TBI compatibility needs to be turned on or off. If the link is not | |
3013 | * at gigabit speed, then TBI compatibility is not needed. If we are | |
3014 | * at gigabit speed, we turn on TBI compatibility. | |
3015 | */ | |
8fc897b0 | 3016 | if (hw->tbi_compatibility_en) { |
406874a7 | 3017 | u16 speed, duplex; |
592600a0 AK |
3018 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
3019 | if (ret_val) { | |
3020 | DEBUGOUT("Error getting link speed and duplex\n"); | |
3021 | return ret_val; | |
3022 | } | |
3023 | if (speed != SPEED_1000) { | |
1da177e4 LT |
3024 | /* If link speed is not set to gigabit speed, we do not need |
3025 | * to enable TBI compatibility. | |
3026 | */ | |
8fc897b0 | 3027 | if (hw->tbi_compatibility_on) { |
1da177e4 | 3028 | /* If we previously were in the mode, turn it off. */ |
1dc32918 | 3029 | rctl = er32(RCTL); |
1da177e4 | 3030 | rctl &= ~E1000_RCTL_SBP; |
1dc32918 | 3031 | ew32(RCTL, rctl); |
c3033b01 | 3032 | hw->tbi_compatibility_on = false; |
1da177e4 LT |
3033 | } |
3034 | } else { | |
3035 | /* If TBI compatibility is was previously off, turn it on. For | |
3036 | * compatibility with a TBI link partner, we will store bad | |
3037 | * packets. Some frames have an additional byte on the end and | |
3038 | * will look like CRC errors to to the hardware. | |
3039 | */ | |
8fc897b0 | 3040 | if (!hw->tbi_compatibility_on) { |
c3033b01 | 3041 | hw->tbi_compatibility_on = true; |
1dc32918 | 3042 | rctl = er32(RCTL); |
1da177e4 | 3043 | rctl |= E1000_RCTL_SBP; |
1dc32918 | 3044 | ew32(RCTL, rctl); |
1da177e4 LT |
3045 | } |
3046 | } | |
3047 | } | |
3048 | } | |
3049 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
3050 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
3051 | * link partner is not trying to auto-negotiate with us (we are receiving | |
3052 | * idles or data), we need to force link up. We also need to give | |
3053 | * auto-negotiation time to complete, in case the cable was just plugged | |
3054 | * in. The autoneg_failed flag does this. | |
3055 | */ | |
8fc897b0 | 3056 | else if ((((hw->media_type == e1000_media_type_fiber) && |
1da177e4 | 3057 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
8fc897b0 AK |
3058 | (hw->media_type == e1000_media_type_internal_serdes)) && |
3059 | (!(status & E1000_STATUS_LU)) && | |
3060 | (!(rxcw & E1000_RXCW_C))) { | |
3061 | if (hw->autoneg_failed == 0) { | |
1da177e4 LT |
3062 | hw->autoneg_failed = 1; |
3063 | return 0; | |
3064 | } | |
a42a507c | 3065 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
1da177e4 LT |
3066 | |
3067 | /* Disable auto-negotiation in the TXCW register */ | |
1dc32918 | 3068 | ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
1da177e4 LT |
3069 | |
3070 | /* Force link-up and also force full-duplex. */ | |
1dc32918 | 3071 | ctrl = er32(CTRL); |
1da177e4 | 3072 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1dc32918 | 3073 | ew32(CTRL, ctrl); |
1da177e4 LT |
3074 | |
3075 | /* Configure Flow Control after forcing link up. */ | |
3076 | ret_val = e1000_config_fc_after_link_up(hw); | |
8fc897b0 | 3077 | if (ret_val) { |
1da177e4 LT |
3078 | DEBUGOUT("Error configuring flow control\n"); |
3079 | return ret_val; | |
3080 | } | |
3081 | } | |
3082 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
3083 | * auto-negotiation in the TXCW register and disable forced link in the | |
3084 | * Device Control register in an attempt to auto-negotiate with our link | |
3085 | * partner. | |
3086 | */ | |
8fc897b0 AK |
3087 | else if (((hw->media_type == e1000_media_type_fiber) || |
3088 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
3089 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
a42a507c | 3090 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
1dc32918 JP |
3091 | ew32(TXCW, hw->txcw); |
3092 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
1da177e4 | 3093 | |
c3033b01 | 3094 | hw->serdes_link_down = false; |
1da177e4 LT |
3095 | } |
3096 | /* If we force link for non-auto-negotiation switch, check link status | |
3097 | * based on MAC synchronization for internal serdes media type. | |
3098 | */ | |
8fc897b0 | 3099 | else if ((hw->media_type == e1000_media_type_internal_serdes) && |
1dc32918 | 3100 | !(E1000_TXCW_ANE & er32(TXCW))) { |
1da177e4 LT |
3101 | /* SYNCH bit and IV bit are sticky. */ |
3102 | udelay(10); | |
1dc32918 | 3103 | if (E1000_RXCW_SYNCH & er32(RXCW)) { |
8fc897b0 | 3104 | if (!(rxcw & E1000_RXCW_IV)) { |
c3033b01 | 3105 | hw->serdes_link_down = false; |
1da177e4 LT |
3106 | DEBUGOUT("SERDES: Link is up.\n"); |
3107 | } | |
3108 | } else { | |
c3033b01 | 3109 | hw->serdes_link_down = true; |
1da177e4 LT |
3110 | DEBUGOUT("SERDES: Link is down.\n"); |
3111 | } | |
3112 | } | |
8fc897b0 | 3113 | if ((hw->media_type == e1000_media_type_internal_serdes) && |
1dc32918 JP |
3114 | (E1000_TXCW_ANE & er32(TXCW))) { |
3115 | hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS)); | |
1da177e4 LT |
3116 | } |
3117 | return E1000_SUCCESS; | |
3118 | } | |
3119 | ||
3120 | /****************************************************************************** | |
3121 | * Detects the current speed and duplex settings of the hardware. | |
3122 | * | |
3123 | * hw - Struct containing variables accessed by shared code | |
3124 | * speed - Speed of the connection | |
3125 | * duplex - Duplex setting of the connection | |
3126 | *****************************************************************************/ | |
64798845 | 3127 | s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
1da177e4 | 3128 | { |
406874a7 JP |
3129 | u32 status; |
3130 | s32 ret_val; | |
3131 | u16 phy_data; | |
1da177e4 LT |
3132 | |
3133 | DEBUGFUNC("e1000_get_speed_and_duplex"); | |
3134 | ||
8fc897b0 | 3135 | if (hw->mac_type >= e1000_82543) { |
1dc32918 | 3136 | status = er32(STATUS); |
8fc897b0 | 3137 | if (status & E1000_STATUS_SPEED_1000) { |
1da177e4 LT |
3138 | *speed = SPEED_1000; |
3139 | DEBUGOUT("1000 Mbs, "); | |
8fc897b0 | 3140 | } else if (status & E1000_STATUS_SPEED_100) { |
1da177e4 LT |
3141 | *speed = SPEED_100; |
3142 | DEBUGOUT("100 Mbs, "); | |
3143 | } else { | |
3144 | *speed = SPEED_10; | |
3145 | DEBUGOUT("10 Mbs, "); | |
3146 | } | |
3147 | ||
8fc897b0 | 3148 | if (status & E1000_STATUS_FD) { |
1da177e4 | 3149 | *duplex = FULL_DUPLEX; |
a42a507c | 3150 | DEBUGOUT("Full Duplex\n"); |
1da177e4 LT |
3151 | } else { |
3152 | *duplex = HALF_DUPLEX; | |
a42a507c | 3153 | DEBUGOUT(" Half Duplex\n"); |
1da177e4 LT |
3154 | } |
3155 | } else { | |
a42a507c | 3156 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
1da177e4 LT |
3157 | *speed = SPEED_1000; |
3158 | *duplex = FULL_DUPLEX; | |
3159 | } | |
3160 | ||
3161 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even | |
3162 | * if it is operating at half duplex. Here we set the duplex settings to | |
3163 | * match the duplex in the link partner's capabilities. | |
3164 | */ | |
8fc897b0 | 3165 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
1da177e4 | 3166 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
8fc897b0 | 3167 | if (ret_val) |
1da177e4 LT |
3168 | return ret_val; |
3169 | ||
8fc897b0 | 3170 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
1da177e4 LT |
3171 | *duplex = HALF_DUPLEX; |
3172 | else { | |
3173 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); | |
8fc897b0 | 3174 | if (ret_val) |
1da177e4 | 3175 | return ret_val; |
8fc897b0 | 3176 | if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
1da177e4 LT |
3177 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
3178 | *duplex = HALF_DUPLEX; | |
3179 | } | |
3180 | } | |
3181 | ||
76c224bc | 3182 | if ((hw->mac_type == e1000_80003es2lan) && |
6418ecc6 JK |
3183 | (hw->media_type == e1000_media_type_copper)) { |
3184 | if (*speed == SPEED_1000) | |
3185 | ret_val = e1000_configure_kmrn_for_1000(hw); | |
3186 | else | |
cd94dd0b AK |
3187 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
3188 | if (ret_val) | |
3189 | return ret_val; | |
3190 | } | |
3191 | ||
3192 | if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { | |
3193 | ret_val = e1000_kumeran_lock_loss_workaround(hw); | |
6418ecc6 JK |
3194 | if (ret_val) |
3195 | return ret_val; | |
3196 | } | |
3197 | ||
1da177e4 LT |
3198 | return E1000_SUCCESS; |
3199 | } | |
3200 | ||
3201 | /****************************************************************************** | |
3202 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
3203 | * | |
3204 | * hw - Struct containing variables accessed by shared code | |
3205 | ******************************************************************************/ | |
64798845 | 3206 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
1da177e4 | 3207 | { |
406874a7 JP |
3208 | s32 ret_val; |
3209 | u16 i; | |
3210 | u16 phy_data; | |
1da177e4 LT |
3211 | |
3212 | DEBUGFUNC("e1000_wait_autoneg"); | |
3213 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
3214 | ||
3215 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
8fc897b0 | 3216 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
1da177e4 LT |
3217 | /* Read the MII Status Register and wait for Auto-Neg |
3218 | * Complete bit to be set. | |
3219 | */ | |
3220 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 3221 | if (ret_val) |
1da177e4 LT |
3222 | return ret_val; |
3223 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 3224 | if (ret_val) |
1da177e4 | 3225 | return ret_val; |
8fc897b0 | 3226 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
1da177e4 LT |
3227 | return E1000_SUCCESS; |
3228 | } | |
f8ec4733 | 3229 | msleep(100); |
1da177e4 LT |
3230 | } |
3231 | return E1000_SUCCESS; | |
3232 | } | |
3233 | ||
3234 | /****************************************************************************** | |
3235 | * Raises the Management Data Clock | |
3236 | * | |
3237 | * hw - Struct containing variables accessed by shared code | |
3238 | * ctrl - Device control register's current value | |
3239 | ******************************************************************************/ | |
64798845 | 3240 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
1da177e4 LT |
3241 | { |
3242 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
3243 | * bit), and then delay 10 microseconds. | |
3244 | */ | |
1dc32918 JP |
3245 | ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); |
3246 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
3247 | udelay(10); |
3248 | } | |
3249 | ||
3250 | /****************************************************************************** | |
3251 | * Lowers the Management Data Clock | |
3252 | * | |
3253 | * hw - Struct containing variables accessed by shared code | |
3254 | * ctrl - Device control register's current value | |
3255 | ******************************************************************************/ | |
64798845 | 3256 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
1da177e4 LT |
3257 | { |
3258 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
3259 | * bit), and then delay 10 microseconds. | |
3260 | */ | |
1dc32918 JP |
3261 | ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
3262 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
3263 | udelay(10); |
3264 | } | |
3265 | ||
3266 | /****************************************************************************** | |
3267 | * Shifts data bits out to the PHY | |
3268 | * | |
3269 | * hw - Struct containing variables accessed by shared code | |
3270 | * data - Data to send out to the PHY | |
3271 | * count - Number of bits to shift out | |
3272 | * | |
3273 | * Bits are shifted out in MSB to LSB order. | |
3274 | ******************************************************************************/ | |
64798845 | 3275 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) |
1da177e4 | 3276 | { |
406874a7 JP |
3277 | u32 ctrl; |
3278 | u32 mask; | |
1da177e4 LT |
3279 | |
3280 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
3281 | * in the "data" parameter will be shifted out to the PHY one bit at a | |
3282 | * time. In order to do this, "data" must be broken down into bits. | |
3283 | */ | |
3284 | mask = 0x01; | |
3285 | mask <<= (count - 1); | |
3286 | ||
1dc32918 | 3287 | ctrl = er32(CTRL); |
1da177e4 LT |
3288 | |
3289 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
3290 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
3291 | ||
8fc897b0 | 3292 | while (mask) { |
1da177e4 LT |
3293 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
3294 | * then raising and lowering the Management Data Clock. A "0" is | |
3295 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
3296 | * raising and lowering the clock. | |
3297 | */ | |
8fc897b0 AK |
3298 | if (data & mask) |
3299 | ctrl |= E1000_CTRL_MDIO; | |
3300 | else | |
3301 | ctrl &= ~E1000_CTRL_MDIO; | |
1da177e4 | 3302 | |
1dc32918 JP |
3303 | ew32(CTRL, ctrl); |
3304 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
3305 | |
3306 | udelay(10); | |
3307 | ||
3308 | e1000_raise_mdi_clk(hw, &ctrl); | |
3309 | e1000_lower_mdi_clk(hw, &ctrl); | |
3310 | ||
3311 | mask = mask >> 1; | |
3312 | } | |
3313 | } | |
3314 | ||
3315 | /****************************************************************************** | |
3316 | * Shifts data bits in from the PHY | |
3317 | * | |
3318 | * hw - Struct containing variables accessed by shared code | |
3319 | * | |
3320 | * Bits are shifted in in MSB to LSB order. | |
3321 | ******************************************************************************/ | |
64798845 | 3322 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
1da177e4 | 3323 | { |
406874a7 JP |
3324 | u32 ctrl; |
3325 | u16 data = 0; | |
3326 | u8 i; | |
1da177e4 LT |
3327 | |
3328 | /* In order to read a register from the PHY, we need to shift in a total | |
3329 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
3330 | * to avoid contention on the MDIO pin when a read operation is performed. | |
3331 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
3332 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
3333 | * and then reading the value of the MDIO bit. | |
3334 | */ | |
1dc32918 | 3335 | ctrl = er32(CTRL); |
1da177e4 LT |
3336 | |
3337 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
3338 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
3339 | ctrl &= ~E1000_CTRL_MDIO; | |
3340 | ||
1dc32918 JP |
3341 | ew32(CTRL, ctrl); |
3342 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
3343 | |
3344 | /* Raise and Lower the clock before reading in the data. This accounts for | |
3345 | * the turnaround bits. The first clock occurred when we clocked out the | |
3346 | * last bit of the Register Address. | |
3347 | */ | |
3348 | e1000_raise_mdi_clk(hw, &ctrl); | |
3349 | e1000_lower_mdi_clk(hw, &ctrl); | |
3350 | ||
8fc897b0 | 3351 | for (data = 0, i = 0; i < 16; i++) { |
1da177e4 LT |
3352 | data = data << 1; |
3353 | e1000_raise_mdi_clk(hw, &ctrl); | |
1dc32918 | 3354 | ctrl = er32(CTRL); |
1da177e4 | 3355 | /* Check to see if we shifted in a "1". */ |
8fc897b0 AK |
3356 | if (ctrl & E1000_CTRL_MDIO) |
3357 | data |= 1; | |
1da177e4 LT |
3358 | e1000_lower_mdi_clk(hw, &ctrl); |
3359 | } | |
3360 | ||
3361 | e1000_raise_mdi_clk(hw, &ctrl); | |
3362 | e1000_lower_mdi_clk(hw, &ctrl); | |
3363 | ||
3364 | return data; | |
3365 | } | |
3366 | ||
64798845 | 3367 | static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask) |
6418ecc6 | 3368 | { |
406874a7 JP |
3369 | u32 swfw_sync = 0; |
3370 | u32 swmask = mask; | |
3371 | u32 fwmask = mask << 16; | |
3372 | s32 timeout = 200; | |
6418ecc6 JK |
3373 | |
3374 | DEBUGFUNC("e1000_swfw_sync_acquire"); | |
3375 | ||
cd94dd0b AK |
3376 | if (hw->swfwhw_semaphore_present) |
3377 | return e1000_get_software_flag(hw); | |
3378 | ||
6418ecc6 JK |
3379 | if (!hw->swfw_sync_present) |
3380 | return e1000_get_hw_eeprom_semaphore(hw); | |
3381 | ||
8fc897b0 | 3382 | while (timeout) { |
6418ecc6 JK |
3383 | if (e1000_get_hw_eeprom_semaphore(hw)) |
3384 | return -E1000_ERR_SWFW_SYNC; | |
3385 | ||
1dc32918 | 3386 | swfw_sync = er32(SW_FW_SYNC); |
6418ecc6 JK |
3387 | if (!(swfw_sync & (fwmask | swmask))) { |
3388 | break; | |
3389 | } | |
3390 | ||
3391 | /* firmware currently using resource (fwmask) */ | |
3392 | /* or other software thread currently using resource (swmask) */ | |
3393 | e1000_put_hw_eeprom_semaphore(hw); | |
f8ec4733 | 3394 | mdelay(5); |
6418ecc6 JK |
3395 | timeout--; |
3396 | } | |
3397 | ||
3398 | if (!timeout) { | |
3399 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
3400 | return -E1000_ERR_SWFW_SYNC; | |
3401 | } | |
3402 | ||
3403 | swfw_sync |= swmask; | |
1dc32918 | 3404 | ew32(SW_FW_SYNC, swfw_sync); |
6418ecc6 JK |
3405 | |
3406 | e1000_put_hw_eeprom_semaphore(hw); | |
3407 | return E1000_SUCCESS; | |
3408 | } | |
3409 | ||
64798845 | 3410 | static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask) |
6418ecc6 | 3411 | { |
406874a7 JP |
3412 | u32 swfw_sync; |
3413 | u32 swmask = mask; | |
6418ecc6 JK |
3414 | |
3415 | DEBUGFUNC("e1000_swfw_sync_release"); | |
3416 | ||
cd94dd0b AK |
3417 | if (hw->swfwhw_semaphore_present) { |
3418 | e1000_release_software_flag(hw); | |
3419 | return; | |
3420 | } | |
3421 | ||
6418ecc6 JK |
3422 | if (!hw->swfw_sync_present) { |
3423 | e1000_put_hw_eeprom_semaphore(hw); | |
3424 | return; | |
3425 | } | |
3426 | ||
3427 | /* if (e1000_get_hw_eeprom_semaphore(hw)) | |
3428 | * return -E1000_ERR_SWFW_SYNC; */ | |
3429 | while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); | |
3430 | /* empty */ | |
3431 | ||
1dc32918 | 3432 | swfw_sync = er32(SW_FW_SYNC); |
6418ecc6 | 3433 | swfw_sync &= ~swmask; |
1dc32918 | 3434 | ew32(SW_FW_SYNC, swfw_sync); |
6418ecc6 JK |
3435 | |
3436 | e1000_put_hw_eeprom_semaphore(hw); | |
3437 | } | |
3438 | ||
1da177e4 LT |
3439 | /***************************************************************************** |
3440 | * Reads the value from a PHY register, if the value is on a specific non zero | |
3441 | * page, sets the page first. | |
3442 | * hw - Struct containing variables accessed by shared code | |
3443 | * reg_addr - address of the PHY register to read | |
3444 | ******************************************************************************/ | |
64798845 | 3445 | s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) |
1da177e4 | 3446 | { |
406874a7 JP |
3447 | u32 ret_val; |
3448 | u16 swfw; | |
1da177e4 LT |
3449 | |
3450 | DEBUGFUNC("e1000_read_phy_reg"); | |
3451 | ||
6418ecc6 | 3452 | if ((hw->mac_type == e1000_80003es2lan) && |
1dc32918 | 3453 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { |
6418ecc6 JK |
3454 | swfw = E1000_SWFW_PHY1_SM; |
3455 | } else { | |
3456 | swfw = E1000_SWFW_PHY0_SM; | |
3457 | } | |
3458 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3459 | return -E1000_ERR_SWFW_SYNC; | |
3460 | ||
cd94dd0b AK |
3461 | if ((hw->phy_type == e1000_phy_igp || |
3462 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 3463 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3464 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3465 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
406874a7 | 3466 | (u16)reg_addr); |
8fc897b0 | 3467 | if (ret_val) { |
6418ecc6 | 3468 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3469 | return ret_val; |
3470 | } | |
6418ecc6 JK |
3471 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3472 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3473 | (hw->mac_type == e1000_80003es2lan)) { | |
3474 | /* Select Configuration Page */ | |
3475 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3476 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
406874a7 | 3477 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); |
6418ecc6 JK |
3478 | } else { |
3479 | /* Use Alternative Page Select register to access | |
3480 | * registers 30 and 31 | |
3481 | */ | |
3482 | ret_val = e1000_write_phy_reg_ex(hw, | |
3483 | GG82563_PHY_PAGE_SELECT_ALT, | |
406874a7 | 3484 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); |
6418ecc6 JK |
3485 | } |
3486 | ||
3487 | if (ret_val) { | |
3488 | e1000_swfw_sync_release(hw, swfw); | |
3489 | return ret_val; | |
3490 | } | |
3491 | } | |
1da177e4 LT |
3492 | } |
3493 | ||
3494 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3495 | phy_data); | |
3496 | ||
6418ecc6 | 3497 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3498 | return ret_val; |
3499 | } | |
3500 | ||
64798845 JP |
3501 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
3502 | u16 *phy_data) | |
1da177e4 | 3503 | { |
406874a7 JP |
3504 | u32 i; |
3505 | u32 mdic = 0; | |
3506 | const u32 phy_addr = 1; | |
1da177e4 LT |
3507 | |
3508 | DEBUGFUNC("e1000_read_phy_reg_ex"); | |
3509 | ||
8fc897b0 | 3510 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
1da177e4 LT |
3511 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3512 | return -E1000_ERR_PARAM; | |
3513 | } | |
3514 | ||
8fc897b0 | 3515 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
3516 | /* Set up Op-code, Phy Address, and register address in the MDI |
3517 | * Control register. The MAC will take care of interfacing with the | |
3518 | * PHY to retrieve the desired data. | |
3519 | */ | |
3520 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
3521 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3522 | (E1000_MDIC_OP_READ)); | |
3523 | ||
1dc32918 | 3524 | ew32(MDIC, mdic); |
1da177e4 LT |
3525 | |
3526 | /* Poll the ready bit to see if the MDI read completed */ | |
8fc897b0 | 3527 | for (i = 0; i < 64; i++) { |
1da177e4 | 3528 | udelay(50); |
1dc32918 | 3529 | mdic = er32(MDIC); |
8fc897b0 | 3530 | if (mdic & E1000_MDIC_READY) break; |
1da177e4 | 3531 | } |
8fc897b0 | 3532 | if (!(mdic & E1000_MDIC_READY)) { |
1da177e4 LT |
3533 | DEBUGOUT("MDI Read did not complete\n"); |
3534 | return -E1000_ERR_PHY; | |
3535 | } | |
8fc897b0 | 3536 | if (mdic & E1000_MDIC_ERROR) { |
1da177e4 LT |
3537 | DEBUGOUT("MDI Error\n"); |
3538 | return -E1000_ERR_PHY; | |
3539 | } | |
e982f17c | 3540 | *phy_data = (u16)mdic; |
1da177e4 LT |
3541 | } else { |
3542 | /* We must first send a preamble through the MDIO pin to signal the | |
3543 | * beginning of an MII instruction. This is done by sending 32 | |
3544 | * consecutive "1" bits. | |
3545 | */ | |
3546 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3547 | ||
3548 | /* Now combine the next few fields that are required for a read | |
3549 | * operation. We use this method instead of calling the | |
3550 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
3551 | * a MII read instruction consists of a shift out of 14 bits and is | |
3552 | * defined as follows: | |
3553 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
3554 | * followed by a shift in of 18 bits. This first two bits shifted in | |
3555 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
3556 | * READ operation is performed. These two bits are thrown away | |
3557 | * followed by a shift in of 16 bits which contains the desired data. | |
3558 | */ | |
3559 | mdic = ((reg_addr) | (phy_addr << 5) | | |
3560 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
3561 | ||
3562 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
3563 | ||
3564 | /* Now that we've shifted out the read command to the MII, we need to | |
3565 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
3566 | * register address. | |
3567 | */ | |
3568 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
3569 | } | |
3570 | return E1000_SUCCESS; | |
3571 | } | |
3572 | ||
3573 | /****************************************************************************** | |
3574 | * Writes a value to a PHY register | |
3575 | * | |
3576 | * hw - Struct containing variables accessed by shared code | |
3577 | * reg_addr - address of the PHY register to write | |
3578 | * data - data to write to the PHY | |
3579 | ******************************************************************************/ | |
64798845 | 3580 | s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) |
1da177e4 | 3581 | { |
406874a7 JP |
3582 | u32 ret_val; |
3583 | u16 swfw; | |
1da177e4 LT |
3584 | |
3585 | DEBUGFUNC("e1000_write_phy_reg"); | |
3586 | ||
6418ecc6 | 3587 | if ((hw->mac_type == e1000_80003es2lan) && |
1dc32918 | 3588 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { |
6418ecc6 JK |
3589 | swfw = E1000_SWFW_PHY1_SM; |
3590 | } else { | |
3591 | swfw = E1000_SWFW_PHY0_SM; | |
3592 | } | |
3593 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3594 | return -E1000_ERR_SWFW_SYNC; | |
3595 | ||
cd94dd0b AK |
3596 | if ((hw->phy_type == e1000_phy_igp || |
3597 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 3598 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3599 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3600 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
406874a7 | 3601 | (u16)reg_addr); |
8fc897b0 | 3602 | if (ret_val) { |
6418ecc6 | 3603 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3604 | return ret_val; |
3605 | } | |
6418ecc6 JK |
3606 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3607 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3608 | (hw->mac_type == e1000_80003es2lan)) { | |
3609 | /* Select Configuration Page */ | |
3610 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3611 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
406874a7 | 3612 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); |
6418ecc6 JK |
3613 | } else { |
3614 | /* Use Alternative Page Select register to access | |
3615 | * registers 30 and 31 | |
3616 | */ | |
3617 | ret_val = e1000_write_phy_reg_ex(hw, | |
3618 | GG82563_PHY_PAGE_SELECT_ALT, | |
406874a7 | 3619 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); |
6418ecc6 JK |
3620 | } |
3621 | ||
3622 | if (ret_val) { | |
3623 | e1000_swfw_sync_release(hw, swfw); | |
3624 | return ret_val; | |
3625 | } | |
3626 | } | |
1da177e4 LT |
3627 | } |
3628 | ||
3629 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3630 | phy_data); | |
3631 | ||
6418ecc6 | 3632 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3633 | return ret_val; |
3634 | } | |
3635 | ||
64798845 JP |
3636 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
3637 | u16 phy_data) | |
1da177e4 | 3638 | { |
406874a7 JP |
3639 | u32 i; |
3640 | u32 mdic = 0; | |
3641 | const u32 phy_addr = 1; | |
1da177e4 LT |
3642 | |
3643 | DEBUGFUNC("e1000_write_phy_reg_ex"); | |
3644 | ||
8fc897b0 | 3645 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
1da177e4 LT |
3646 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3647 | return -E1000_ERR_PARAM; | |
3648 | } | |
3649 | ||
8fc897b0 | 3650 | if (hw->mac_type > e1000_82543) { |
1da177e4 LT |
3651 | /* Set up Op-code, Phy Address, register address, and data intended |
3652 | * for the PHY register in the MDI Control register. The MAC will take | |
3653 | * care of interfacing with the PHY to send the desired data. | |
3654 | */ | |
e982f17c | 3655 | mdic = (((u32)phy_data) | |
1da177e4 LT |
3656 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
3657 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3658 | (E1000_MDIC_OP_WRITE)); | |
3659 | ||
1dc32918 | 3660 | ew32(MDIC, mdic); |
1da177e4 LT |
3661 | |
3662 | /* Poll the ready bit to see if the MDI read completed */ | |
8fc897b0 | 3663 | for (i = 0; i < 641; i++) { |
1da177e4 | 3664 | udelay(5); |
1dc32918 | 3665 | mdic = er32(MDIC); |
8fc897b0 | 3666 | if (mdic & E1000_MDIC_READY) break; |
1da177e4 | 3667 | } |
8fc897b0 | 3668 | if (!(mdic & E1000_MDIC_READY)) { |
1da177e4 LT |
3669 | DEBUGOUT("MDI Write did not complete\n"); |
3670 | return -E1000_ERR_PHY; | |
3671 | } | |
3672 | } else { | |
3673 | /* We'll need to use the SW defined pins to shift the write command | |
3674 | * out to the PHY. We first send a preamble to the PHY to signal the | |
3675 | * beginning of the MII instruction. This is done by sending 32 | |
3676 | * consecutive "1" bits. | |
3677 | */ | |
3678 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3679 | ||
3680 | /* Now combine the remaining required fields that will indicate a | |
3681 | * write operation. We use this method instead of calling the | |
3682 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
3683 | * format of a MII write instruction is as follows: | |
3684 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
3685 | */ | |
3686 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
3687 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
3688 | mdic <<= 16; | |
e982f17c | 3689 | mdic |= (u32)phy_data; |
1da177e4 LT |
3690 | |
3691 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
3692 | } | |
3693 | ||
3694 | return E1000_SUCCESS; | |
3695 | } | |
3696 | ||
64798845 | 3697 | static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data) |
6418ecc6 | 3698 | { |
406874a7 JP |
3699 | u32 reg_val; |
3700 | u16 swfw; | |
6418ecc6 JK |
3701 | DEBUGFUNC("e1000_read_kmrn_reg"); |
3702 | ||
3703 | if ((hw->mac_type == e1000_80003es2lan) && | |
1dc32918 | 3704 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { |
6418ecc6 JK |
3705 | swfw = E1000_SWFW_PHY1_SM; |
3706 | } else { | |
3707 | swfw = E1000_SWFW_PHY0_SM; | |
3708 | } | |
3709 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3710 | return -E1000_ERR_SWFW_SYNC; | |
3711 | ||
3712 | /* Write register address */ | |
3713 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3714 | E1000_KUMCTRLSTA_OFFSET) | | |
3715 | E1000_KUMCTRLSTA_REN; | |
1dc32918 | 3716 | ew32(KUMCTRLSTA, reg_val); |
6418ecc6 JK |
3717 | udelay(2); |
3718 | ||
3719 | /* Read the data returned */ | |
1dc32918 | 3720 | reg_val = er32(KUMCTRLSTA); |
406874a7 | 3721 | *data = (u16)reg_val; |
6418ecc6 JK |
3722 | |
3723 | e1000_swfw_sync_release(hw, swfw); | |
3724 | return E1000_SUCCESS; | |
3725 | } | |
3726 | ||
64798845 | 3727 | static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data) |
6418ecc6 | 3728 | { |
406874a7 JP |
3729 | u32 reg_val; |
3730 | u16 swfw; | |
6418ecc6 JK |
3731 | DEBUGFUNC("e1000_write_kmrn_reg"); |
3732 | ||
3733 | if ((hw->mac_type == e1000_80003es2lan) && | |
1dc32918 | 3734 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { |
6418ecc6 JK |
3735 | swfw = E1000_SWFW_PHY1_SM; |
3736 | } else { | |
3737 | swfw = E1000_SWFW_PHY0_SM; | |
3738 | } | |
3739 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3740 | return -E1000_ERR_SWFW_SYNC; | |
3741 | ||
3742 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3743 | E1000_KUMCTRLSTA_OFFSET) | data; | |
1dc32918 | 3744 | ew32(KUMCTRLSTA, reg_val); |
6418ecc6 JK |
3745 | udelay(2); |
3746 | ||
3747 | e1000_swfw_sync_release(hw, swfw); | |
3748 | return E1000_SUCCESS; | |
3749 | } | |
2d7edb92 | 3750 | |
1da177e4 LT |
3751 | /****************************************************************************** |
3752 | * Returns the PHY to the power-on reset state | |
3753 | * | |
3754 | * hw - Struct containing variables accessed by shared code | |
3755 | ******************************************************************************/ | |
64798845 | 3756 | s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
1da177e4 | 3757 | { |
406874a7 JP |
3758 | u32 ctrl, ctrl_ext; |
3759 | u32 led_ctrl; | |
3760 | s32 ret_val; | |
3761 | u16 swfw; | |
1da177e4 LT |
3762 | |
3763 | DEBUGFUNC("e1000_phy_hw_reset"); | |
3764 | ||
2d7edb92 MC |
3765 | /* In the case of the phy reset being blocked, it's not an error, we |
3766 | * simply return success without performing the reset. */ | |
3767 | ret_val = e1000_check_phy_reset_block(hw); | |
3768 | if (ret_val) | |
3769 | return E1000_SUCCESS; | |
3770 | ||
1da177e4 LT |
3771 | DEBUGOUT("Resetting Phy...\n"); |
3772 | ||
8fc897b0 | 3773 | if (hw->mac_type > e1000_82543) { |
6418ecc6 | 3774 | if ((hw->mac_type == e1000_80003es2lan) && |
1dc32918 | 3775 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { |
6418ecc6 JK |
3776 | swfw = E1000_SWFW_PHY1_SM; |
3777 | } else { | |
3778 | swfw = E1000_SWFW_PHY0_SM; | |
3779 | } | |
3780 | if (e1000_swfw_sync_acquire(hw, swfw)) { | |
2a88c173 | 3781 | DEBUGOUT("Unable to acquire swfw sync\n"); |
6418ecc6 JK |
3782 | return -E1000_ERR_SWFW_SYNC; |
3783 | } | |
1da177e4 LT |
3784 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
3785 | * bit. Then, take it out of reset. | |
76c224bc | 3786 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
fd803241 | 3787 | * and deassert. For e1000_82571 hardware and later, we instead delay |
0f15a8fa | 3788 | * for 50us between and 10ms after the deassertion. |
1da177e4 | 3789 | */ |
1dc32918 JP |
3790 | ctrl = er32(CTRL); |
3791 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
3792 | E1000_WRITE_FLUSH(); | |
76c224bc AK |
3793 | |
3794 | if (hw->mac_type < e1000_82571) | |
f8ec4733 | 3795 | msleep(10); |
b55ccb35 JK |
3796 | else |
3797 | udelay(100); | |
76c224bc | 3798 | |
1dc32918 JP |
3799 | ew32(CTRL, ctrl); |
3800 | E1000_WRITE_FLUSH(); | |
76c224bc | 3801 | |
fd803241 | 3802 | if (hw->mac_type >= e1000_82571) |
f8ec4733 | 3803 | mdelay(10); |
35574764 | 3804 | |
6418ecc6 | 3805 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3806 | } else { |
3807 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
3808 | * bit to put the PHY into reset. Then, take it out of reset. | |
3809 | */ | |
1dc32918 | 3810 | ctrl_ext = er32(CTRL_EXT); |
1da177e4 LT |
3811 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
3812 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
1dc32918 JP |
3813 | ew32(CTRL_EXT, ctrl_ext); |
3814 | E1000_WRITE_FLUSH(); | |
f8ec4733 | 3815 | msleep(10); |
1da177e4 | 3816 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
1dc32918 JP |
3817 | ew32(CTRL_EXT, ctrl_ext); |
3818 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
3819 | } |
3820 | udelay(150); | |
3821 | ||
8fc897b0 | 3822 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1da177e4 | 3823 | /* Configure activity LED after PHY reset */ |
1dc32918 | 3824 | led_ctrl = er32(LEDCTL); |
1da177e4 LT |
3825 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
3826 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1dc32918 | 3827 | ew32(LEDCTL, led_ctrl); |
1da177e4 | 3828 | } |
2d7edb92 MC |
3829 | |
3830 | /* Wait for FW to finish PHY configuration. */ | |
3831 | ret_val = e1000_get_phy_cfg_done(hw); | |
8fc897b0 AK |
3832 | if (ret_val != E1000_SUCCESS) |
3833 | return ret_val; | |
6418ecc6 | 3834 | e1000_release_software_semaphore(hw); |
2d7edb92 | 3835 | |
8fc897b0 AK |
3836 | if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) |
3837 | ret_val = e1000_init_lcd_from_nvm(hw); | |
3838 | ||
2d7edb92 | 3839 | return ret_val; |
1da177e4 LT |
3840 | } |
3841 | ||
3842 | /****************************************************************************** | |
3843 | * Resets the PHY | |
3844 | * | |
3845 | * hw - Struct containing variables accessed by shared code | |
3846 | * | |
0779bf2d | 3847 | * Sets bit 15 of the MII Control register |
1da177e4 | 3848 | ******************************************************************************/ |
64798845 | 3849 | s32 e1000_phy_reset(struct e1000_hw *hw) |
1da177e4 | 3850 | { |
406874a7 JP |
3851 | s32 ret_val; |
3852 | u16 phy_data; | |
1da177e4 LT |
3853 | |
3854 | DEBUGFUNC("e1000_phy_reset"); | |
3855 | ||
2d7edb92 MC |
3856 | /* In the case of the phy reset being blocked, it's not an error, we |
3857 | * simply return success without performing the reset. */ | |
3858 | ret_val = e1000_check_phy_reset_block(hw); | |
3859 | if (ret_val) | |
3860 | return E1000_SUCCESS; | |
3861 | ||
2a88c173 JK |
3862 | switch (hw->phy_type) { |
3863 | case e1000_phy_igp: | |
3864 | case e1000_phy_igp_2: | |
3865 | case e1000_phy_igp_3: | |
3866 | case e1000_phy_ife: | |
2d7edb92 | 3867 | ret_val = e1000_phy_hw_reset(hw); |
8fc897b0 | 3868 | if (ret_val) |
2d7edb92 MC |
3869 | return ret_val; |
3870 | break; | |
3871 | default: | |
1da177e4 | 3872 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
8fc897b0 | 3873 | if (ret_val) |
1da177e4 LT |
3874 | return ret_val; |
3875 | ||
3876 | phy_data |= MII_CR_RESET; | |
3877 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
8fc897b0 | 3878 | if (ret_val) |
1da177e4 LT |
3879 | return ret_val; |
3880 | ||
3881 | udelay(1); | |
2d7edb92 MC |
3882 | break; |
3883 | } | |
1da177e4 | 3884 | |
8fc897b0 | 3885 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
1da177e4 LT |
3886 | e1000_phy_init_script(hw); |
3887 | ||
3888 | return E1000_SUCCESS; | |
3889 | } | |
3890 | ||
d37ea5d5 AK |
3891 | /****************************************************************************** |
3892 | * Work-around for 82566 power-down: on D3 entry- | |
3893 | * 1) disable gigabit link | |
3894 | * 2) write VR power-down enable | |
3895 | * 3) read it back | |
3896 | * if successful continue, else issue LCD reset and repeat | |
3897 | * | |
3898 | * hw - struct containing variables accessed by shared code | |
3899 | ******************************************************************************/ | |
64798845 | 3900 | void e1000_phy_powerdown_workaround(struct e1000_hw *hw) |
d37ea5d5 | 3901 | { |
406874a7 JP |
3902 | s32 reg; |
3903 | u16 phy_data; | |
3904 | s32 retry = 0; | |
d37ea5d5 AK |
3905 | |
3906 | DEBUGFUNC("e1000_phy_powerdown_workaround"); | |
3907 | ||
3908 | if (hw->phy_type != e1000_phy_igp_3) | |
3909 | return; | |
3910 | ||
3911 | do { | |
3912 | /* Disable link */ | |
1dc32918 JP |
3913 | reg = er32(PHY_CTRL); |
3914 | ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | |
d37ea5d5 AK |
3915 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
3916 | ||
070f6ffb | 3917 | /* Write VR power-down enable - bits 9:8 should be 10b */ |
d37ea5d5 | 3918 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
070f6ffb JK |
3919 | phy_data |= (1 << 9); |
3920 | phy_data &= ~(1 << 8); | |
3921 | e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); | |
d37ea5d5 AK |
3922 | |
3923 | /* Read it back and test */ | |
3924 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | |
070f6ffb | 3925 | if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) |
d37ea5d5 AK |
3926 | break; |
3927 | ||
3928 | /* Issue PHY reset and repeat at most one more time */ | |
1dc32918 JP |
3929 | reg = er32(CTRL); |
3930 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
d37ea5d5 AK |
3931 | retry++; |
3932 | } while (retry); | |
3933 | ||
3934 | return; | |
3935 | ||
3936 | } | |
3937 | ||
3938 | /****************************************************************************** | |
3939 | * Work-around for 82566 Kumeran PCS lock loss: | |
3940 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
3941 | * speed is gigabit- | |
3942 | * 0) if workaround is optionally disabled do nothing | |
3943 | * 1) wait 1ms for Kumeran link to come up | |
3944 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
3945 | * 3) if not set the link is locked (all is good), otherwise... | |
3946 | * 4) reset the PHY | |
3947 | * 5) repeat up to 10 times | |
3948 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
3949 | * | |
3950 | * hw - struct containing variables accessed by shared code | |
3951 | ******************************************************************************/ | |
64798845 | 3952 | static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) |
d37ea5d5 | 3953 | { |
406874a7 JP |
3954 | s32 ret_val; |
3955 | s32 reg; | |
3956 | s32 cnt; | |
3957 | u16 phy_data; | |
d37ea5d5 AK |
3958 | |
3959 | if (hw->kmrn_lock_loss_workaround_disabled) | |
3960 | return E1000_SUCCESS; | |
3961 | ||
8fc897b0 AK |
3962 | /* Make sure link is up before proceeding. If not just return. |
3963 | * Attempting this while link is negotiating fouled up link | |
d37ea5d5 AK |
3964 | * stability */ |
3965 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3966 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3967 | ||
3968 | if (phy_data & MII_SR_LINK_STATUS) { | |
3969 | for (cnt = 0; cnt < 10; cnt++) { | |
3970 | /* read once to clear */ | |
3971 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | |
3972 | if (ret_val) | |
3973 | return ret_val; | |
3974 | /* and again to get new status */ | |
3975 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | |
3976 | if (ret_val) | |
3977 | return ret_val; | |
3978 | ||
3979 | /* check for PCS lock */ | |
3980 | if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
3981 | return E1000_SUCCESS; | |
3982 | ||
3983 | /* Issue PHY reset */ | |
3984 | e1000_phy_hw_reset(hw); | |
f8ec4733 | 3985 | mdelay(5); |
d37ea5d5 AK |
3986 | } |
3987 | /* Disable GigE link negotiation */ | |
1dc32918 JP |
3988 | reg = er32(PHY_CTRL); |
3989 | ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | |
d37ea5d5 AK |
3990 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
3991 | ||
3992 | /* unable to acquire PCS lock */ | |
3993 | return E1000_ERR_PHY; | |
3994 | } | |
3995 | ||
3996 | return E1000_SUCCESS; | |
3997 | } | |
3998 | ||
1da177e4 LT |
3999 | /****************************************************************************** |
4000 | * Probes the expected PHY address for known PHY IDs | |
4001 | * | |
4002 | * hw - Struct containing variables accessed by shared code | |
4003 | ******************************************************************************/ | |
64798845 | 4004 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw) |
1da177e4 | 4005 | { |
406874a7 JP |
4006 | s32 phy_init_status, ret_val; |
4007 | u16 phy_id_high, phy_id_low; | |
c3033b01 | 4008 | bool match = false; |
1da177e4 LT |
4009 | |
4010 | DEBUGFUNC("e1000_detect_gig_phy"); | |
4011 | ||
2a88c173 JK |
4012 | if (hw->phy_id != 0) |
4013 | return E1000_SUCCESS; | |
4014 | ||
868d5309 MC |
4015 | /* The 82571 firmware may still be configuring the PHY. In this |
4016 | * case, we cannot access the PHY until the configuration is done. So | |
4017 | * we explicitly set the PHY values. */ | |
cd94dd0b AK |
4018 | if (hw->mac_type == e1000_82571 || |
4019 | hw->mac_type == e1000_82572) { | |
868d5309 MC |
4020 | hw->phy_id = IGP01E1000_I_PHY_ID; |
4021 | hw->phy_type = e1000_phy_igp_2; | |
4022 | return E1000_SUCCESS; | |
4023 | } | |
4024 | ||
6418ecc6 JK |
4025 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
4026 | * around that forces PHY page 0 to be set or the reads fail. The rest of | |
4027 | * the code in this routine uses e1000_read_phy_reg to read the PHY ID. | |
4028 | * So for ESB-2 we need to have this set so our reads won't fail. If the | |
4029 | * attached PHY is not a e1000_phy_gg82563, the routines below will figure | |
4030 | * this out as well. */ | |
4031 | if (hw->mac_type == e1000_80003es2lan) | |
4032 | hw->phy_type = e1000_phy_gg82563; | |
4033 | ||
1da177e4 LT |
4034 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
4035 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
cd94dd0b | 4036 | if (ret_val) |
1da177e4 LT |
4037 | return ret_val; |
4038 | ||
e982f17c | 4039 | hw->phy_id = (u32)(phy_id_high << 16); |
1da177e4 LT |
4040 | udelay(20); |
4041 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
8fc897b0 | 4042 | if (ret_val) |
1da177e4 LT |
4043 | return ret_val; |
4044 | ||
e982f17c JP |
4045 | hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK); |
4046 | hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK; | |
1da177e4 | 4047 | |
8fc897b0 | 4048 | switch (hw->mac_type) { |
1da177e4 | 4049 | case e1000_82543: |
c3033b01 | 4050 | if (hw->phy_id == M88E1000_E_PHY_ID) match = true; |
1da177e4 LT |
4051 | break; |
4052 | case e1000_82544: | |
c3033b01 | 4053 | if (hw->phy_id == M88E1000_I_PHY_ID) match = true; |
1da177e4 LT |
4054 | break; |
4055 | case e1000_82540: | |
4056 | case e1000_82545: | |
4057 | case e1000_82545_rev_3: | |
4058 | case e1000_82546: | |
4059 | case e1000_82546_rev_3: | |
c3033b01 | 4060 | if (hw->phy_id == M88E1011_I_PHY_ID) match = true; |
1da177e4 LT |
4061 | break; |
4062 | case e1000_82541: | |
4063 | case e1000_82541_rev_2: | |
4064 | case e1000_82547: | |
4065 | case e1000_82547_rev_2: | |
c3033b01 | 4066 | if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; |
1da177e4 | 4067 | break; |
2d7edb92 | 4068 | case e1000_82573: |
c3033b01 | 4069 | if (hw->phy_id == M88E1111_I_PHY_ID) match = true; |
2d7edb92 | 4070 | break; |
6418ecc6 | 4071 | case e1000_80003es2lan: |
c3033b01 | 4072 | if (hw->phy_id == GG82563_E_PHY_ID) match = true; |
6418ecc6 | 4073 | break; |
cd94dd0b | 4074 | case e1000_ich8lan: |
c3033b01 JP |
4075 | if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true; |
4076 | if (hw->phy_id == IFE_E_PHY_ID) match = true; | |
4077 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true; | |
4078 | if (hw->phy_id == IFE_C_E_PHY_ID) match = true; | |
cd94dd0b | 4079 | break; |
1da177e4 LT |
4080 | default: |
4081 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | |
4082 | return -E1000_ERR_CONFIG; | |
4083 | } | |
4084 | phy_init_status = e1000_set_phy_type(hw); | |
4085 | ||
4086 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
4087 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); | |
4088 | return E1000_SUCCESS; | |
4089 | } | |
4090 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); | |
4091 | return -E1000_ERR_PHY; | |
4092 | } | |
4093 | ||
4094 | /****************************************************************************** | |
4095 | * Resets the PHY's DSP | |
4096 | * | |
4097 | * hw - Struct containing variables accessed by shared code | |
4098 | ******************************************************************************/ | |
64798845 | 4099 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) |
1da177e4 | 4100 | { |
406874a7 | 4101 | s32 ret_val; |
1da177e4 LT |
4102 | DEBUGFUNC("e1000_phy_reset_dsp"); |
4103 | ||
4104 | do { | |
6418ecc6 JK |
4105 | if (hw->phy_type != e1000_phy_gg82563) { |
4106 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); | |
8fc897b0 | 4107 | if (ret_val) break; |
6418ecc6 | 4108 | } |
1da177e4 | 4109 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
8fc897b0 | 4110 | if (ret_val) break; |
1da177e4 | 4111 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
8fc897b0 | 4112 | if (ret_val) break; |
1da177e4 | 4113 | ret_val = E1000_SUCCESS; |
8fc897b0 | 4114 | } while (0); |
1da177e4 LT |
4115 | |
4116 | return ret_val; | |
4117 | } | |
4118 | ||
4119 | /****************************************************************************** | |
4120 | * Get PHY information from various PHY registers for igp PHY only. | |
4121 | * | |
4122 | * hw - Struct containing variables accessed by shared code | |
4123 | * phy_info - PHY information structure | |
4124 | ******************************************************************************/ | |
64798845 JP |
4125 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
4126 | struct e1000_phy_info *phy_info) | |
1da177e4 | 4127 | { |
406874a7 JP |
4128 | s32 ret_val; |
4129 | u16 phy_data, min_length, max_length, average; | |
70c6f30a | 4130 | e1000_rev_polarity polarity; |
1da177e4 LT |
4131 | |
4132 | DEBUGFUNC("e1000_phy_igp_get_info"); | |
4133 | ||
4134 | /* The downshift status is checked only once, after link is established, | |
4135 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 4136 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
4137 | |
4138 | /* IGP01E1000 does not need to support it. */ | |
4139 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
4140 | ||
4141 | /* IGP01E1000 always correct polarity reversal */ | |
4142 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; | |
4143 | ||
4144 | /* Check polarity status */ | |
4145 | ret_val = e1000_check_polarity(hw, &polarity); | |
8fc897b0 | 4146 | if (ret_val) |
1da177e4 LT |
4147 | return ret_val; |
4148 | ||
4149 | phy_info->cable_polarity = polarity; | |
4150 | ||
4151 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); | |
8fc897b0 | 4152 | if (ret_val) |
1da177e4 LT |
4153 | return ret_val; |
4154 | ||
70c6f30a JK |
4155 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> |
4156 | IGP01E1000_PSSR_MDIX_SHIFT); | |
1da177e4 | 4157 | |
8fc897b0 | 4158 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
1da177e4 LT |
4159 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
4160 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ | |
4161 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
8fc897b0 | 4162 | if (ret_val) |
1da177e4 LT |
4163 | return ret_val; |
4164 | ||
70c6f30a JK |
4165 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
4166 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | |
4167 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
4168 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
4169 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | |
4170 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
1da177e4 LT |
4171 | |
4172 | /* Get cable length */ | |
4173 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | |
8fc897b0 | 4174 | if (ret_val) |
1da177e4 LT |
4175 | return ret_val; |
4176 | ||
2d7edb92 | 4177 | /* Translate to old method */ |
1da177e4 LT |
4178 | average = (max_length + min_length) / 2; |
4179 | ||
8fc897b0 | 4180 | if (average <= e1000_igp_cable_length_50) |
1da177e4 | 4181 | phy_info->cable_length = e1000_cable_length_50; |
8fc897b0 | 4182 | else if (average <= e1000_igp_cable_length_80) |
1da177e4 | 4183 | phy_info->cable_length = e1000_cable_length_50_80; |
8fc897b0 | 4184 | else if (average <= e1000_igp_cable_length_110) |
1da177e4 | 4185 | phy_info->cable_length = e1000_cable_length_80_110; |
8fc897b0 | 4186 | else if (average <= e1000_igp_cable_length_140) |
1da177e4 LT |
4187 | phy_info->cable_length = e1000_cable_length_110_140; |
4188 | else | |
4189 | phy_info->cable_length = e1000_cable_length_140; | |
4190 | } | |
4191 | ||
4192 | return E1000_SUCCESS; | |
4193 | } | |
4194 | ||
d37ea5d5 AK |
4195 | /****************************************************************************** |
4196 | * Get PHY information from various PHY registers for ife PHY only. | |
4197 | * | |
4198 | * hw - Struct containing variables accessed by shared code | |
4199 | * phy_info - PHY information structure | |
4200 | ******************************************************************************/ | |
64798845 JP |
4201 | static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, |
4202 | struct e1000_phy_info *phy_info) | |
d37ea5d5 | 4203 | { |
406874a7 JP |
4204 | s32 ret_val; |
4205 | u16 phy_data; | |
70c6f30a | 4206 | e1000_rev_polarity polarity; |
d37ea5d5 AK |
4207 | |
4208 | DEBUGFUNC("e1000_phy_ife_get_info"); | |
4209 | ||
4210 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | |
4211 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
4212 | ||
4213 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | |
4214 | if (ret_val) | |
4215 | return ret_val; | |
4216 | phy_info->polarity_correction = | |
70c6f30a JK |
4217 | ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> |
4218 | IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? | |
4219 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | |
d37ea5d5 AK |
4220 | |
4221 | if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { | |
4222 | ret_val = e1000_check_polarity(hw, &polarity); | |
4223 | if (ret_val) | |
4224 | return ret_val; | |
4225 | } else { | |
4226 | /* Polarity is forced. */ | |
70c6f30a JK |
4227 | polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> |
4228 | IFE_PSC_FORCE_POLARITY_SHIFT) ? | |
4229 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
d37ea5d5 AK |
4230 | } |
4231 | phy_info->cable_polarity = polarity; | |
4232 | ||
4233 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | |
4234 | if (ret_val) | |
4235 | return ret_val; | |
4236 | ||
70c6f30a JK |
4237 | phy_info->mdix_mode = (e1000_auto_x_mode) |
4238 | ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> | |
4239 | IFE_PMC_MDIX_MODE_SHIFT); | |
d37ea5d5 AK |
4240 | |
4241 | return E1000_SUCCESS; | |
4242 | } | |
4243 | ||
1da177e4 LT |
4244 | /****************************************************************************** |
4245 | * Get PHY information from various PHY registers fot m88 PHY only. | |
4246 | * | |
4247 | * hw - Struct containing variables accessed by shared code | |
4248 | * phy_info - PHY information structure | |
4249 | ******************************************************************************/ | |
64798845 JP |
4250 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
4251 | struct e1000_phy_info *phy_info) | |
1da177e4 | 4252 | { |
406874a7 JP |
4253 | s32 ret_val; |
4254 | u16 phy_data; | |
70c6f30a | 4255 | e1000_rev_polarity polarity; |
1da177e4 LT |
4256 | |
4257 | DEBUGFUNC("e1000_phy_m88_get_info"); | |
4258 | ||
4259 | /* The downshift status is checked only once, after link is established, | |
4260 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 4261 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
4262 | |
4263 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
8fc897b0 | 4264 | if (ret_val) |
1da177e4 LT |
4265 | return ret_val; |
4266 | ||
4267 | phy_info->extended_10bt_distance = | |
70c6f30a JK |
4268 | ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
4269 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? | |
4270 | e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; | |
4271 | ||
1da177e4 | 4272 | phy_info->polarity_correction = |
70c6f30a JK |
4273 | ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
4274 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? | |
4275 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | |
1da177e4 LT |
4276 | |
4277 | /* Check polarity status */ | |
4278 | ret_val = e1000_check_polarity(hw, &polarity); | |
8fc897b0 | 4279 | if (ret_val) |
76c224bc | 4280 | return ret_val; |
1da177e4 LT |
4281 | phy_info->cable_polarity = polarity; |
4282 | ||
4283 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
8fc897b0 | 4284 | if (ret_val) |
1da177e4 LT |
4285 | return ret_val; |
4286 | ||
70c6f30a JK |
4287 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> |
4288 | M88E1000_PSSR_MDIX_SHIFT); | |
1da177e4 LT |
4289 | |
4290 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
4291 | /* Cable Length Estimation and Local/Remote Receiver Information | |
4292 | * are only valid at 1000 Mbps. | |
4293 | */ | |
6418ecc6 | 4294 | if (hw->phy_type != e1000_phy_gg82563) { |
70c6f30a | 4295 | phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
6418ecc6 JK |
4296 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
4297 | } else { | |
4298 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
4299 | &phy_data); | |
4300 | if (ret_val) | |
4301 | return ret_val; | |
4302 | ||
70c6f30a | 4303 | phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); |
6418ecc6 | 4304 | } |
1da177e4 LT |
4305 | |
4306 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
8fc897b0 | 4307 | if (ret_val) |
1da177e4 LT |
4308 | return ret_val; |
4309 | ||
70c6f30a JK |
4310 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
4311 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | |
4312 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
4313 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
4314 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | |
4315 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
1da177e4 | 4316 | |
1da177e4 LT |
4317 | } |
4318 | ||
4319 | return E1000_SUCCESS; | |
4320 | } | |
4321 | ||
4322 | /****************************************************************************** | |
4323 | * Get PHY information from various PHY registers | |
4324 | * | |
4325 | * hw - Struct containing variables accessed by shared code | |
4326 | * phy_info - PHY information structure | |
4327 | ******************************************************************************/ | |
64798845 | 4328 | s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) |
1da177e4 | 4329 | { |
406874a7 JP |
4330 | s32 ret_val; |
4331 | u16 phy_data; | |
1da177e4 LT |
4332 | |
4333 | DEBUGFUNC("e1000_phy_get_info"); | |
4334 | ||
4335 | phy_info->cable_length = e1000_cable_length_undefined; | |
4336 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; | |
4337 | phy_info->cable_polarity = e1000_rev_polarity_undefined; | |
4338 | phy_info->downshift = e1000_downshift_undefined; | |
4339 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; | |
4340 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; | |
4341 | phy_info->local_rx = e1000_1000t_rx_status_undefined; | |
4342 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; | |
4343 | ||
8fc897b0 | 4344 | if (hw->media_type != e1000_media_type_copper) { |
1da177e4 LT |
4345 | DEBUGOUT("PHY info is only valid for copper media\n"); |
4346 | return -E1000_ERR_CONFIG; | |
4347 | } | |
4348 | ||
4349 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 4350 | if (ret_val) |
1da177e4 LT |
4351 | return ret_val; |
4352 | ||
4353 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
8fc897b0 | 4354 | if (ret_val) |
1da177e4 LT |
4355 | return ret_val; |
4356 | ||
8fc897b0 | 4357 | if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
1da177e4 LT |
4358 | DEBUGOUT("PHY info is only valid if link is up\n"); |
4359 | return -E1000_ERR_CONFIG; | |
4360 | } | |
4361 | ||
cd94dd0b AK |
4362 | if (hw->phy_type == e1000_phy_igp || |
4363 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 4364 | hw->phy_type == e1000_phy_igp_2) |
1da177e4 | 4365 | return e1000_phy_igp_get_info(hw, phy_info); |
cd94dd0b AK |
4366 | else if (hw->phy_type == e1000_phy_ife) |
4367 | return e1000_phy_ife_get_info(hw, phy_info); | |
1da177e4 LT |
4368 | else |
4369 | return e1000_phy_m88_get_info(hw, phy_info); | |
4370 | } | |
4371 | ||
64798845 | 4372 | s32 e1000_validate_mdi_setting(struct e1000_hw *hw) |
1da177e4 LT |
4373 | { |
4374 | DEBUGFUNC("e1000_validate_mdi_settings"); | |
4375 | ||
8fc897b0 | 4376 | if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
1da177e4 LT |
4377 | DEBUGOUT("Invalid MDI setting detected\n"); |
4378 | hw->mdix = 1; | |
4379 | return -E1000_ERR_CONFIG; | |
4380 | } | |
4381 | return E1000_SUCCESS; | |
4382 | } | |
4383 | ||
4384 | ||
4385 | /****************************************************************************** | |
4386 | * Sets up eeprom variables in the hw struct. Must be called after mac_type | |
0f15a8fa JK |
4387 | * is configured. Additionally, if this is ICH8, the flash controller GbE |
4388 | * registers must be mapped, or this will crash. | |
1da177e4 LT |
4389 | * |
4390 | * hw - Struct containing variables accessed by shared code | |
4391 | *****************************************************************************/ | |
64798845 | 4392 | s32 e1000_init_eeprom_params(struct e1000_hw *hw) |
1da177e4 LT |
4393 | { |
4394 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
1dc32918 | 4395 | u32 eecd = er32(EECD); |
406874a7 JP |
4396 | s32 ret_val = E1000_SUCCESS; |
4397 | u16 eeprom_size; | |
1da177e4 LT |
4398 | |
4399 | DEBUGFUNC("e1000_init_eeprom_params"); | |
4400 | ||
4401 | switch (hw->mac_type) { | |
4402 | case e1000_82542_rev2_0: | |
4403 | case e1000_82542_rev2_1: | |
4404 | case e1000_82543: | |
4405 | case e1000_82544: | |
4406 | eeprom->type = e1000_eeprom_microwire; | |
4407 | eeprom->word_size = 64; | |
4408 | eeprom->opcode_bits = 3; | |
4409 | eeprom->address_bits = 6; | |
4410 | eeprom->delay_usec = 50; | |
c3033b01 JP |
4411 | eeprom->use_eerd = false; |
4412 | eeprom->use_eewr = false; | |
1da177e4 LT |
4413 | break; |
4414 | case e1000_82540: | |
4415 | case e1000_82545: | |
4416 | case e1000_82545_rev_3: | |
4417 | case e1000_82546: | |
4418 | case e1000_82546_rev_3: | |
4419 | eeprom->type = e1000_eeprom_microwire; | |
4420 | eeprom->opcode_bits = 3; | |
4421 | eeprom->delay_usec = 50; | |
8fc897b0 | 4422 | if (eecd & E1000_EECD_SIZE) { |
1da177e4 LT |
4423 | eeprom->word_size = 256; |
4424 | eeprom->address_bits = 8; | |
4425 | } else { | |
4426 | eeprom->word_size = 64; | |
4427 | eeprom->address_bits = 6; | |
4428 | } | |
c3033b01 JP |
4429 | eeprom->use_eerd = false; |
4430 | eeprom->use_eewr = false; | |
1da177e4 LT |
4431 | break; |
4432 | case e1000_82541: | |
4433 | case e1000_82541_rev_2: | |
4434 | case e1000_82547: | |
4435 | case e1000_82547_rev_2: | |
4436 | if (eecd & E1000_EECD_TYPE) { | |
4437 | eeprom->type = e1000_eeprom_spi; | |
4438 | eeprom->opcode_bits = 8; | |
4439 | eeprom->delay_usec = 1; | |
4440 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4441 | eeprom->page_size = 32; | |
4442 | eeprom->address_bits = 16; | |
4443 | } else { | |
4444 | eeprom->page_size = 8; | |
4445 | eeprom->address_bits = 8; | |
4446 | } | |
4447 | } else { | |
4448 | eeprom->type = e1000_eeprom_microwire; | |
4449 | eeprom->opcode_bits = 3; | |
4450 | eeprom->delay_usec = 50; | |
4451 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4452 | eeprom->word_size = 256; | |
4453 | eeprom->address_bits = 8; | |
4454 | } else { | |
4455 | eeprom->word_size = 64; | |
4456 | eeprom->address_bits = 6; | |
4457 | } | |
4458 | } | |
c3033b01 JP |
4459 | eeprom->use_eerd = false; |
4460 | eeprom->use_eewr = false; | |
2d7edb92 | 4461 | break; |
868d5309 MC |
4462 | case e1000_82571: |
4463 | case e1000_82572: | |
4464 | eeprom->type = e1000_eeprom_spi; | |
4465 | eeprom->opcode_bits = 8; | |
4466 | eeprom->delay_usec = 1; | |
4467 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4468 | eeprom->page_size = 32; | |
4469 | eeprom->address_bits = 16; | |
4470 | } else { | |
4471 | eeprom->page_size = 8; | |
4472 | eeprom->address_bits = 8; | |
4473 | } | |
c3033b01 JP |
4474 | eeprom->use_eerd = false; |
4475 | eeprom->use_eewr = false; | |
868d5309 | 4476 | break; |
2d7edb92 MC |
4477 | case e1000_82573: |
4478 | eeprom->type = e1000_eeprom_spi; | |
4479 | eeprom->opcode_bits = 8; | |
4480 | eeprom->delay_usec = 1; | |
4481 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4482 | eeprom->page_size = 32; | |
4483 | eeprom->address_bits = 16; | |
4484 | } else { | |
4485 | eeprom->page_size = 8; | |
4486 | eeprom->address_bits = 8; | |
4487 | } | |
c3033b01 JP |
4488 | eeprom->use_eerd = true; |
4489 | eeprom->use_eewr = true; | |
4490 | if (!e1000_is_onboard_nvm_eeprom(hw)) { | |
2d7edb92 MC |
4491 | eeprom->type = e1000_eeprom_flash; |
4492 | eeprom->word_size = 2048; | |
4493 | ||
4494 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
4495 | * Flash update issue on parts which use a FLASH for NVM. */ | |
4496 | eecd &= ~E1000_EECD_AUPDEN; | |
1dc32918 | 4497 | ew32(EECD, eecd); |
2d7edb92 | 4498 | } |
1da177e4 | 4499 | break; |
6418ecc6 JK |
4500 | case e1000_80003es2lan: |
4501 | eeprom->type = e1000_eeprom_spi; | |
4502 | eeprom->opcode_bits = 8; | |
4503 | eeprom->delay_usec = 1; | |
4504 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4505 | eeprom->page_size = 32; | |
4506 | eeprom->address_bits = 16; | |
4507 | } else { | |
4508 | eeprom->page_size = 8; | |
4509 | eeprom->address_bits = 8; | |
4510 | } | |
c3033b01 JP |
4511 | eeprom->use_eerd = true; |
4512 | eeprom->use_eewr = false; | |
6418ecc6 | 4513 | break; |
cd94dd0b | 4514 | case e1000_ich8lan: |
35574764 | 4515 | { |
406874a7 JP |
4516 | s32 i = 0; |
4517 | u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); | |
cd94dd0b AK |
4518 | |
4519 | eeprom->type = e1000_eeprom_ich8; | |
c3033b01 JP |
4520 | eeprom->use_eerd = false; |
4521 | eeprom->use_eewr = false; | |
cd94dd0b AK |
4522 | eeprom->word_size = E1000_SHADOW_RAM_WORDS; |
4523 | ||
4524 | /* Zero the shadow RAM structure. But don't load it from NVM | |
4525 | * so as to save time for driver init */ | |
4526 | if (hw->eeprom_shadow_ram != NULL) { | |
4527 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
c3033b01 | 4528 | hw->eeprom_shadow_ram[i].modified = false; |
cd94dd0b AK |
4529 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
4530 | } | |
4531 | } | |
4532 | ||
2df7d59f JK |
4533 | hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * |
4534 | ICH_FLASH_SECTOR_SIZE; | |
4535 | ||
4536 | hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; | |
4537 | hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); | |
4538 | ||
4539 | hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; | |
cd94dd0b | 4540 | |
406874a7 | 4541 | hw->flash_bank_size /= 2 * sizeof(u16); |
cd94dd0b AK |
4542 | |
4543 | break; | |
35574764 | 4544 | } |
1da177e4 LT |
4545 | default: |
4546 | break; | |
4547 | } | |
4548 | ||
4549 | if (eeprom->type == e1000_eeprom_spi) { | |
2d7edb92 MC |
4550 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
4551 | * 32KB (incremented by powers of 2). | |
4552 | */ | |
8fc897b0 | 4553 | if (hw->mac_type <= e1000_82547_rev_2) { |
2d7edb92 MC |
4554 | /* Set to default value for initial eeprom read. */ |
4555 | eeprom->word_size = 64; | |
4556 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); | |
8fc897b0 | 4557 | if (ret_val) |
2d7edb92 MC |
4558 | return ret_val; |
4559 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; | |
4560 | /* 256B eeprom size was not supported in earlier hardware, so we | |
4561 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) | |
4562 | * is never the result used in the shifting logic below. */ | |
8fc897b0 | 4563 | if (eeprom_size) |
2d7edb92 MC |
4564 | eeprom_size++; |
4565 | } else { | |
406874a7 | 4566 | eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
2d7edb92 | 4567 | E1000_EECD_SIZE_EX_SHIFT); |
1da177e4 | 4568 | } |
2d7edb92 MC |
4569 | |
4570 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
1da177e4 | 4571 | } |
2d7edb92 | 4572 | return ret_val; |
1da177e4 LT |
4573 | } |
4574 | ||
4575 | /****************************************************************************** | |
4576 | * Raises the EEPROM's clock input. | |
4577 | * | |
4578 | * hw - Struct containing variables accessed by shared code | |
4579 | * eecd - EECD's current value | |
4580 | *****************************************************************************/ | |
64798845 | 4581 | static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) |
1da177e4 LT |
4582 | { |
4583 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
4584 | * wait <delay> microseconds. | |
4585 | */ | |
4586 | *eecd = *eecd | E1000_EECD_SK; | |
1dc32918 JP |
4587 | ew32(EECD, *eecd); |
4588 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4589 | udelay(hw->eeprom.delay_usec); |
4590 | } | |
4591 | ||
4592 | /****************************************************************************** | |
4593 | * Lowers the EEPROM's clock input. | |
4594 | * | |
4595 | * hw - Struct containing variables accessed by shared code | |
4596 | * eecd - EECD's current value | |
4597 | *****************************************************************************/ | |
64798845 | 4598 | static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) |
1da177e4 LT |
4599 | { |
4600 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | |
4601 | * wait 50 microseconds. | |
4602 | */ | |
4603 | *eecd = *eecd & ~E1000_EECD_SK; | |
1dc32918 JP |
4604 | ew32(EECD, *eecd); |
4605 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4606 | udelay(hw->eeprom.delay_usec); |
4607 | } | |
4608 | ||
4609 | /****************************************************************************** | |
4610 | * Shift data bits out to the EEPROM. | |
4611 | * | |
4612 | * hw - Struct containing variables accessed by shared code | |
4613 | * data - data to send to the EEPROM | |
4614 | * count - number of bits to shift out | |
4615 | *****************************************************************************/ | |
64798845 | 4616 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) |
1da177e4 LT |
4617 | { |
4618 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 JP |
4619 | u32 eecd; |
4620 | u32 mask; | |
1da177e4 LT |
4621 | |
4622 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
4623 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
4624 | * In order to do this, "data" must be broken down into bits. | |
4625 | */ | |
4626 | mask = 0x01 << (count - 1); | |
1dc32918 | 4627 | eecd = er32(EECD); |
1da177e4 LT |
4628 | if (eeprom->type == e1000_eeprom_microwire) { |
4629 | eecd &= ~E1000_EECD_DO; | |
4630 | } else if (eeprom->type == e1000_eeprom_spi) { | |
4631 | eecd |= E1000_EECD_DO; | |
4632 | } | |
4633 | do { | |
4634 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
4635 | * and then raising and then lowering the clock (the SK bit controls | |
4636 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
4637 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
4638 | */ | |
4639 | eecd &= ~E1000_EECD_DI; | |
4640 | ||
8fc897b0 | 4641 | if (data & mask) |
1da177e4 LT |
4642 | eecd |= E1000_EECD_DI; |
4643 | ||
1dc32918 JP |
4644 | ew32(EECD, eecd); |
4645 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4646 | |
4647 | udelay(eeprom->delay_usec); | |
4648 | ||
4649 | e1000_raise_ee_clk(hw, &eecd); | |
4650 | e1000_lower_ee_clk(hw, &eecd); | |
4651 | ||
4652 | mask = mask >> 1; | |
4653 | ||
8fc897b0 | 4654 | } while (mask); |
1da177e4 LT |
4655 | |
4656 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
4657 | eecd &= ~E1000_EECD_DI; | |
1dc32918 | 4658 | ew32(EECD, eecd); |
1da177e4 LT |
4659 | } |
4660 | ||
4661 | /****************************************************************************** | |
4662 | * Shift data bits in from the EEPROM | |
4663 | * | |
4664 | * hw - Struct containing variables accessed by shared code | |
4665 | *****************************************************************************/ | |
64798845 | 4666 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) |
1da177e4 | 4667 | { |
406874a7 JP |
4668 | u32 eecd; |
4669 | u32 i; | |
4670 | u16 data; | |
1da177e4 LT |
4671 | |
4672 | /* In order to read a register from the EEPROM, we need to shift 'count' | |
4673 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
4674 | * input to the EEPROM (setting the SK bit), and then reading the value of | |
4675 | * the "DO" bit. During this "shifting in" process the "DI" bit should | |
4676 | * always be clear. | |
4677 | */ | |
4678 | ||
1dc32918 | 4679 | eecd = er32(EECD); |
1da177e4 LT |
4680 | |
4681 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
4682 | data = 0; | |
4683 | ||
8fc897b0 | 4684 | for (i = 0; i < count; i++) { |
1da177e4 LT |
4685 | data = data << 1; |
4686 | e1000_raise_ee_clk(hw, &eecd); | |
4687 | ||
1dc32918 | 4688 | eecd = er32(EECD); |
1da177e4 LT |
4689 | |
4690 | eecd &= ~(E1000_EECD_DI); | |
8fc897b0 | 4691 | if (eecd & E1000_EECD_DO) |
1da177e4 LT |
4692 | data |= 1; |
4693 | ||
4694 | e1000_lower_ee_clk(hw, &eecd); | |
4695 | } | |
4696 | ||
4697 | return data; | |
4698 | } | |
4699 | ||
4700 | /****************************************************************************** | |
4701 | * Prepares EEPROM for access | |
4702 | * | |
4703 | * hw - Struct containing variables accessed by shared code | |
4704 | * | |
4705 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
4706 | * function should be called before issuing a command to the EEPROM. | |
4707 | *****************************************************************************/ | |
64798845 | 4708 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw) |
1da177e4 LT |
4709 | { |
4710 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 | 4711 | u32 eecd, i=0; |
1da177e4 LT |
4712 | |
4713 | DEBUGFUNC("e1000_acquire_eeprom"); | |
4714 | ||
6418ecc6 JK |
4715 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
4716 | return -E1000_ERR_SWFW_SYNC; | |
1dc32918 | 4717 | eecd = er32(EECD); |
1da177e4 | 4718 | |
2d7edb92 | 4719 | if (hw->mac_type != e1000_82573) { |
868d5309 | 4720 | /* Request EEPROM Access */ |
8fc897b0 | 4721 | if (hw->mac_type > e1000_82544) { |
868d5309 | 4722 | eecd |= E1000_EECD_REQ; |
1dc32918 JP |
4723 | ew32(EECD, eecd); |
4724 | eecd = er32(EECD); | |
8fc897b0 | 4725 | while ((!(eecd & E1000_EECD_GNT)) && |
868d5309 MC |
4726 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
4727 | i++; | |
4728 | udelay(5); | |
1dc32918 | 4729 | eecd = er32(EECD); |
868d5309 | 4730 | } |
8fc897b0 | 4731 | if (!(eecd & E1000_EECD_GNT)) { |
868d5309 | 4732 | eecd &= ~E1000_EECD_REQ; |
1dc32918 | 4733 | ew32(EECD, eecd); |
868d5309 | 4734 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
6418ecc6 | 4735 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
868d5309 MC |
4736 | return -E1000_ERR_EEPROM; |
4737 | } | |
1da177e4 LT |
4738 | } |
4739 | } | |
4740 | ||
4741 | /* Setup EEPROM for Read/Write */ | |
4742 | ||
4743 | if (eeprom->type == e1000_eeprom_microwire) { | |
4744 | /* Clear SK and DI */ | |
4745 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
1dc32918 | 4746 | ew32(EECD, eecd); |
1da177e4 LT |
4747 | |
4748 | /* Set CS */ | |
4749 | eecd |= E1000_EECD_CS; | |
1dc32918 | 4750 | ew32(EECD, eecd); |
1da177e4 LT |
4751 | } else if (eeprom->type == e1000_eeprom_spi) { |
4752 | /* Clear SK and CS */ | |
4753 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
1dc32918 | 4754 | ew32(EECD, eecd); |
1da177e4 LT |
4755 | udelay(1); |
4756 | } | |
4757 | ||
4758 | return E1000_SUCCESS; | |
4759 | } | |
4760 | ||
4761 | /****************************************************************************** | |
4762 | * Returns EEPROM to a "standby" state | |
4763 | * | |
4764 | * hw - Struct containing variables accessed by shared code | |
4765 | *****************************************************************************/ | |
64798845 | 4766 | static void e1000_standby_eeprom(struct e1000_hw *hw) |
1da177e4 LT |
4767 | { |
4768 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 | 4769 | u32 eecd; |
1da177e4 | 4770 | |
1dc32918 | 4771 | eecd = er32(EECD); |
1da177e4 | 4772 | |
8fc897b0 | 4773 | if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 | 4774 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
1dc32918 JP |
4775 | ew32(EECD, eecd); |
4776 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4777 | udelay(eeprom->delay_usec); |
4778 | ||
4779 | /* Clock high */ | |
4780 | eecd |= E1000_EECD_SK; | |
1dc32918 JP |
4781 | ew32(EECD, eecd); |
4782 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4783 | udelay(eeprom->delay_usec); |
4784 | ||
4785 | /* Select EEPROM */ | |
4786 | eecd |= E1000_EECD_CS; | |
1dc32918 JP |
4787 | ew32(EECD, eecd); |
4788 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4789 | udelay(eeprom->delay_usec); |
4790 | ||
4791 | /* Clock low */ | |
4792 | eecd &= ~E1000_EECD_SK; | |
1dc32918 JP |
4793 | ew32(EECD, eecd); |
4794 | E1000_WRITE_FLUSH(); | |
1da177e4 | 4795 | udelay(eeprom->delay_usec); |
8fc897b0 | 4796 | } else if (eeprom->type == e1000_eeprom_spi) { |
1da177e4 LT |
4797 | /* Toggle CS to flush commands */ |
4798 | eecd |= E1000_EECD_CS; | |
1dc32918 JP |
4799 | ew32(EECD, eecd); |
4800 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4801 | udelay(eeprom->delay_usec); |
4802 | eecd &= ~E1000_EECD_CS; | |
1dc32918 JP |
4803 | ew32(EECD, eecd); |
4804 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4805 | udelay(eeprom->delay_usec); |
4806 | } | |
4807 | } | |
4808 | ||
4809 | /****************************************************************************** | |
4810 | * Terminates a command by inverting the EEPROM's chip select pin | |
4811 | * | |
4812 | * hw - Struct containing variables accessed by shared code | |
4813 | *****************************************************************************/ | |
64798845 | 4814 | static void e1000_release_eeprom(struct e1000_hw *hw) |
1da177e4 | 4815 | { |
406874a7 | 4816 | u32 eecd; |
1da177e4 LT |
4817 | |
4818 | DEBUGFUNC("e1000_release_eeprom"); | |
4819 | ||
1dc32918 | 4820 | eecd = er32(EECD); |
1da177e4 LT |
4821 | |
4822 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
4823 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
4824 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
4825 | ||
1dc32918 | 4826 | ew32(EECD, eecd); |
1da177e4 LT |
4827 | |
4828 | udelay(hw->eeprom.delay_usec); | |
8fc897b0 | 4829 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
1da177e4 LT |
4830 | /* cleanup eeprom */ |
4831 | ||
4832 | /* CS on Microwire is active-high */ | |
4833 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
4834 | ||
1dc32918 | 4835 | ew32(EECD, eecd); |
1da177e4 LT |
4836 | |
4837 | /* Rising edge of clock */ | |
4838 | eecd |= E1000_EECD_SK; | |
1dc32918 JP |
4839 | ew32(EECD, eecd); |
4840 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4841 | udelay(hw->eeprom.delay_usec); |
4842 | ||
4843 | /* Falling edge of clock */ | |
4844 | eecd &= ~E1000_EECD_SK; | |
1dc32918 JP |
4845 | ew32(EECD, eecd); |
4846 | E1000_WRITE_FLUSH(); | |
1da177e4 LT |
4847 | udelay(hw->eeprom.delay_usec); |
4848 | } | |
4849 | ||
4850 | /* Stop requesting EEPROM access */ | |
8fc897b0 | 4851 | if (hw->mac_type > e1000_82544) { |
1da177e4 | 4852 | eecd &= ~E1000_EECD_REQ; |
1dc32918 | 4853 | ew32(EECD, eecd); |
1da177e4 | 4854 | } |
2d7edb92 | 4855 | |
6418ecc6 | 4856 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
1da177e4 LT |
4857 | } |
4858 | ||
4859 | /****************************************************************************** | |
4860 | * Reads a 16 bit word from the EEPROM. | |
4861 | * | |
4862 | * hw - Struct containing variables accessed by shared code | |
4863 | *****************************************************************************/ | |
64798845 | 4864 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
1da177e4 | 4865 | { |
406874a7 JP |
4866 | u16 retry_count = 0; |
4867 | u8 spi_stat_reg; | |
1da177e4 LT |
4868 | |
4869 | DEBUGFUNC("e1000_spi_eeprom_ready"); | |
4870 | ||
4871 | /* Read "Status Register" repeatedly until the LSB is cleared. The | |
4872 | * EEPROM will signal that the command has been completed by clearing | |
4873 | * bit 0 of the internal status register. If it's not cleared within | |
4874 | * 5 milliseconds, then error out. | |
4875 | */ | |
4876 | retry_count = 0; | |
4877 | do { | |
4878 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
4879 | hw->eeprom.opcode_bits); | |
406874a7 | 4880 | spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); |
1da177e4 LT |
4881 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
4882 | break; | |
4883 | ||
4884 | udelay(5); | |
4885 | retry_count += 5; | |
4886 | ||
4887 | e1000_standby_eeprom(hw); | |
8fc897b0 | 4888 | } while (retry_count < EEPROM_MAX_RETRY_SPI); |
1da177e4 LT |
4889 | |
4890 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
4891 | * only 0-5mSec on 5V devices) | |
4892 | */ | |
8fc897b0 | 4893 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
1da177e4 LT |
4894 | DEBUGOUT("SPI EEPROM Status error\n"); |
4895 | return -E1000_ERR_EEPROM; | |
4896 | } | |
4897 | ||
4898 | return E1000_SUCCESS; | |
4899 | } | |
4900 | ||
4901 | /****************************************************************************** | |
4902 | * Reads a 16 bit word from the EEPROM. | |
4903 | * | |
4904 | * hw - Struct containing variables accessed by shared code | |
4905 | * offset - offset of word in the EEPROM to read | |
4906 | * data - word read from the EEPROM | |
4907 | * words - number of words to read | |
4908 | *****************************************************************************/ | |
64798845 | 4909 | s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
78566fec CL |
4910 | { |
4911 | s32 ret; | |
4912 | spin_lock(&e1000_eeprom_lock); | |
4913 | ret = e1000_do_read_eeprom(hw, offset, words, data); | |
4914 | spin_unlock(&e1000_eeprom_lock); | |
4915 | return ret; | |
4916 | } | |
4917 | ||
4918 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
1da177e4 LT |
4919 | { |
4920 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 | 4921 | u32 i = 0; |
1da177e4 LT |
4922 | |
4923 | DEBUGFUNC("e1000_read_eeprom"); | |
2d7edb92 | 4924 | |
2a88c173 JK |
4925 | /* If eeprom is not yet detected, do so now */ |
4926 | if (eeprom->word_size == 0) | |
4927 | e1000_init_eeprom_params(hw); | |
4928 | ||
1da177e4 LT |
4929 | /* A check for invalid values: offset too large, too many words, and not |
4930 | * enough words. | |
4931 | */ | |
8fc897b0 | 4932 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
1da177e4 | 4933 | (words == 0)) { |
2a88c173 | 4934 | DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); |
1da177e4 LT |
4935 | return -E1000_ERR_EEPROM; |
4936 | } | |
4937 | ||
2a88c173 JK |
4938 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
4939 | * directly. In this case, we need to acquire the EEPROM so that | |
4940 | * FW or other port software does not interrupt. | |
4941 | */ | |
c3033b01 | 4942 | if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) { |
2a88c173 JK |
4943 | /* Prepare the EEPROM for bit-bang reading */ |
4944 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
4945 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
4946 | } |
4947 | ||
2a88c173 | 4948 | /* Eerd register EEPROM access requires no eeprom aquire/release */ |
c3033b01 | 4949 | if (eeprom->use_eerd) |
2a88c173 | 4950 | return e1000_read_eeprom_eerd(hw, offset, words, data); |
1da177e4 | 4951 | |
2a88c173 | 4952 | /* ICH EEPROM access is done via the ICH flash controller */ |
cd94dd0b AK |
4953 | if (eeprom->type == e1000_eeprom_ich8) |
4954 | return e1000_read_eeprom_ich8(hw, offset, words, data); | |
4955 | ||
2a88c173 JK |
4956 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
4957 | * acquired the EEPROM at this point, so any returns should relase it */ | |
cd94dd0b | 4958 | if (eeprom->type == e1000_eeprom_spi) { |
406874a7 JP |
4959 | u16 word_in; |
4960 | u8 read_opcode = EEPROM_READ_OPCODE_SPI; | |
1da177e4 | 4961 | |
8fc897b0 | 4962 | if (e1000_spi_eeprom_ready(hw)) { |
1da177e4 LT |
4963 | e1000_release_eeprom(hw); |
4964 | return -E1000_ERR_EEPROM; | |
4965 | } | |
4966 | ||
4967 | e1000_standby_eeprom(hw); | |
4968 | ||
4969 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
8fc897b0 | 4970 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
1da177e4 LT |
4971 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
4972 | ||
4973 | /* Send the READ command (opcode + addr) */ | |
4974 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
406874a7 | 4975 | e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits); |
1da177e4 LT |
4976 | |
4977 | /* Read the data. The address of the eeprom internally increments with | |
4978 | * each byte (spi) being read, saving on the overhead of eeprom setup | |
4979 | * and tear-down. The address counter will roll over if reading beyond | |
4980 | * the size of the eeprom, thus allowing the entire memory to be read | |
4981 | * starting from any offset. */ | |
4982 | for (i = 0; i < words; i++) { | |
4983 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
4984 | data[i] = (word_in >> 8) | (word_in << 8); | |
4985 | } | |
8fc897b0 | 4986 | } else if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 LT |
4987 | for (i = 0; i < words; i++) { |
4988 | /* Send the READ command (opcode + addr) */ | |
4989 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, | |
4990 | eeprom->opcode_bits); | |
406874a7 | 4991 | e1000_shift_out_ee_bits(hw, (u16)(offset + i), |
1da177e4 LT |
4992 | eeprom->address_bits); |
4993 | ||
4994 | /* Read the data. For microwire, each word requires the overhead | |
4995 | * of eeprom setup and tear-down. */ | |
4996 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
4997 | e1000_standby_eeprom(hw); | |
4998 | } | |
4999 | } | |
5000 | ||
5001 | /* End this read operation */ | |
5002 | e1000_release_eeprom(hw); | |
5003 | ||
5004 | return E1000_SUCCESS; | |
5005 | } | |
5006 | ||
5007 | /****************************************************************************** | |
2d7edb92 | 5008 | * Reads a 16 bit word from the EEPROM using the EERD register. |
1da177e4 LT |
5009 | * |
5010 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
5011 | * offset - offset of word in the EEPROM to read |
5012 | * data - word read from the EEPROM | |
5013 | * words - number of words to read | |
1da177e4 | 5014 | *****************************************************************************/ |
64798845 JP |
5015 | static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, |
5016 | u16 *data) | |
1da177e4 | 5017 | { |
406874a7 JP |
5018 | u32 i, eerd = 0; |
5019 | s32 error = 0; | |
1da177e4 | 5020 | |
2d7edb92 MC |
5021 | for (i = 0; i < words; i++) { |
5022 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
5023 | E1000_EEPROM_RW_REG_START; | |
1da177e4 | 5024 | |
1dc32918 | 5025 | ew32(EERD, eerd); |
2d7edb92 | 5026 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
76c224bc | 5027 | |
8fc897b0 | 5028 | if (error) { |
2d7edb92 | 5029 | break; |
1da177e4 | 5030 | } |
1dc32918 | 5031 | data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA); |
76c224bc | 5032 | |
1da177e4 | 5033 | } |
76c224bc | 5034 | |
2d7edb92 | 5035 | return error; |
1da177e4 LT |
5036 | } |
5037 | ||
5038 | /****************************************************************************** | |
2d7edb92 | 5039 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
1da177e4 LT |
5040 | * |
5041 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
5042 | * offset - offset of word in the EEPROM to read |
5043 | * data - word read from the EEPROM | |
5044 | * words - number of words to read | |
1da177e4 | 5045 | *****************************************************************************/ |
64798845 JP |
5046 | static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, |
5047 | u16 *data) | |
1da177e4 | 5048 | { |
406874a7 JP |
5049 | u32 register_value = 0; |
5050 | u32 i = 0; | |
5051 | s32 error = 0; | |
1da177e4 | 5052 | |
6418ecc6 JK |
5053 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
5054 | return -E1000_ERR_SWFW_SYNC; | |
5055 | ||
2d7edb92 | 5056 | for (i = 0; i < words; i++) { |
76c224bc AK |
5057 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
5058 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | |
2d7edb92 | 5059 | E1000_EEPROM_RW_REG_START; |
1da177e4 | 5060 | |
2d7edb92 | 5061 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
8fc897b0 | 5062 | if (error) { |
2d7edb92 | 5063 | break; |
76c224bc | 5064 | } |
2d7edb92 | 5065 | |
1dc32918 | 5066 | ew32(EEWR, register_value); |
76c224bc | 5067 | |
2d7edb92 | 5068 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
76c224bc | 5069 | |
8fc897b0 | 5070 | if (error) { |
2d7edb92 | 5071 | break; |
76c224bc | 5072 | } |
2d7edb92 | 5073 | } |
76c224bc | 5074 | |
6418ecc6 | 5075 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
2d7edb92 MC |
5076 | return error; |
5077 | } | |
5078 | ||
5079 | /****************************************************************************** | |
5080 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
5081 | * | |
5082 | * hw - Struct containing variables accessed by shared code | |
5083 | *****************************************************************************/ | |
64798845 | 5084 | static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
2d7edb92 | 5085 | { |
406874a7 JP |
5086 | u32 attempts = 100000; |
5087 | u32 i, reg = 0; | |
5088 | s32 done = E1000_ERR_EEPROM; | |
2d7edb92 | 5089 | |
8fc897b0 AK |
5090 | for (i = 0; i < attempts; i++) { |
5091 | if (eerd == E1000_EEPROM_POLL_READ) | |
1dc32918 | 5092 | reg = er32(EERD); |
76c224bc | 5093 | else |
1dc32918 | 5094 | reg = er32(EEWR); |
2d7edb92 | 5095 | |
8fc897b0 | 5096 | if (reg & E1000_EEPROM_RW_REG_DONE) { |
2d7edb92 MC |
5097 | done = E1000_SUCCESS; |
5098 | break; | |
5099 | } | |
5100 | udelay(5); | |
5101 | } | |
5102 | ||
5103 | return done; | |
5104 | } | |
5105 | ||
5106 | /*************************************************************************** | |
5107 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
5108 | * | |
5109 | * hw - Struct containing variables accessed by shared code | |
5110 | ****************************************************************************/ | |
64798845 | 5111 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
2d7edb92 | 5112 | { |
406874a7 | 5113 | u32 eecd = 0; |
2d7edb92 | 5114 | |
6418ecc6 JK |
5115 | DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
5116 | ||
cd94dd0b | 5117 | if (hw->mac_type == e1000_ich8lan) |
c3033b01 | 5118 | return false; |
cd94dd0b AK |
5119 | |
5120 | if (hw->mac_type == e1000_82573) { | |
1dc32918 | 5121 | eecd = er32(EECD); |
2d7edb92 MC |
5122 | |
5123 | /* Isolate bits 15 & 16 */ | |
5124 | eecd = ((eecd >> 15) & 0x03); | |
5125 | ||
5126 | /* If both bits are set, device is Flash type */ | |
8fc897b0 | 5127 | if (eecd == 0x03) { |
c3033b01 | 5128 | return false; |
2d7edb92 MC |
5129 | } |
5130 | } | |
c3033b01 | 5131 | return true; |
2d7edb92 MC |
5132 | } |
5133 | ||
5134 | /****************************************************************************** | |
5135 | * Verifies that the EEPROM has a valid checksum | |
5136 | * | |
5137 | * hw - Struct containing variables accessed by shared code | |
5138 | * | |
5139 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
5140 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
5141 | * valid. | |
5142 | *****************************************************************************/ | |
64798845 | 5143 | s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
2d7edb92 | 5144 | { |
406874a7 JP |
5145 | u16 checksum = 0; |
5146 | u16 i, eeprom_data; | |
2d7edb92 MC |
5147 | |
5148 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | |
5149 | ||
c3033b01 | 5150 | if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) { |
2d7edb92 MC |
5151 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
5152 | * 10h-12h. Checksum may need to be fixed. */ | |
5153 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | |
5154 | if ((eeprom_data & 0x10) == 0) { | |
5155 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | |
5156 | * has already been fixed. If the checksum is still wrong and this | |
5157 | * bit is a 1, we need to return bad checksum. Otherwise, we need | |
5158 | * to set this bit to a 1 and update the checksum. */ | |
5159 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | |
5160 | if ((eeprom_data & 0x8000) == 0) { | |
5161 | eeprom_data |= 0x8000; | |
5162 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | |
5163 | e1000_update_eeprom_checksum(hw); | |
5164 | } | |
5165 | } | |
5166 | } | |
5167 | ||
cd94dd0b AK |
5168 | if (hw->mac_type == e1000_ich8lan) { |
5169 | /* Drivers must allocate the shadow ram structure for the | |
5170 | * EEPROM checksum to be updated. Otherwise, this bit as well | |
5171 | * as the checksum must both be set correctly for this | |
5172 | * validation to pass. | |
5173 | */ | |
5174 | e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); | |
5175 | if ((eeprom_data & 0x40) == 0) { | |
5176 | eeprom_data |= 0x40; | |
5177 | e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); | |
5178 | e1000_update_eeprom_checksum(hw); | |
5179 | } | |
5180 | } | |
5181 | ||
5182 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | |
5183 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
2d7edb92 MC |
5184 | DEBUGOUT("EEPROM Read Error\n"); |
5185 | return -E1000_ERR_EEPROM; | |
5186 | } | |
5187 | checksum += eeprom_data; | |
5188 | } | |
5189 | ||
e982f17c | 5190 | if (checksum == (u16)EEPROM_SUM) |
2d7edb92 MC |
5191 | return E1000_SUCCESS; |
5192 | else { | |
5193 | DEBUGOUT("EEPROM Checksum Invalid\n"); | |
5194 | return -E1000_ERR_EEPROM; | |
5195 | } | |
5196 | } | |
5197 | ||
5198 | /****************************************************************************** | |
5199 | * Calculates the EEPROM checksum and writes it to the EEPROM | |
5200 | * | |
5201 | * hw - Struct containing variables accessed by shared code | |
5202 | * | |
5203 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | |
5204 | * Writes the difference to word offset 63 of the EEPROM. | |
5205 | *****************************************************************************/ | |
64798845 | 5206 | s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
2d7edb92 | 5207 | { |
406874a7 JP |
5208 | u32 ctrl_ext; |
5209 | u16 checksum = 0; | |
5210 | u16 i, eeprom_data; | |
2d7edb92 MC |
5211 | |
5212 | DEBUGFUNC("e1000_update_eeprom_checksum"); | |
5213 | ||
8fc897b0 AK |
5214 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
5215 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
2d7edb92 MC |
5216 | DEBUGOUT("EEPROM Read Error\n"); |
5217 | return -E1000_ERR_EEPROM; | |
5218 | } | |
5219 | checksum += eeprom_data; | |
5220 | } | |
e982f17c | 5221 | checksum = (u16)EEPROM_SUM - checksum; |
8fc897b0 | 5222 | if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
1da177e4 LT |
5223 | DEBUGOUT("EEPROM Write Error\n"); |
5224 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
5225 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
5226 | e1000_commit_shadow_ram(hw); | |
cd94dd0b AK |
5227 | } else if (hw->eeprom.type == e1000_eeprom_ich8) { |
5228 | e1000_commit_shadow_ram(hw); | |
5229 | /* Reload the EEPROM, or else modifications will not appear | |
5230 | * until after next adapter reset. */ | |
1dc32918 | 5231 | ctrl_ext = er32(CTRL_EXT); |
cd94dd0b | 5232 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
1dc32918 | 5233 | ew32(CTRL_EXT, ctrl_ext); |
f8ec4733 | 5234 | msleep(10); |
1da177e4 LT |
5235 | } |
5236 | return E1000_SUCCESS; | |
5237 | } | |
5238 | ||
5239 | /****************************************************************************** | |
5240 | * Parent function for writing words to the different EEPROM types. | |
5241 | * | |
5242 | * hw - Struct containing variables accessed by shared code | |
5243 | * offset - offset within the EEPROM to be written to | |
5244 | * words - number of words to write | |
5245 | * data - 16 bit word to be written to the EEPROM | |
5246 | * | |
5247 | * If e1000_update_eeprom_checksum is not called after this function, the | |
5248 | * EEPROM will most likely contain an invalid checksum. | |
5249 | *****************************************************************************/ | |
64798845 | 5250 | s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
78566fec CL |
5251 | { |
5252 | s32 ret; | |
5253 | spin_lock(&e1000_eeprom_lock); | |
5254 | ret = e1000_do_write_eeprom(hw, offset, words, data); | |
5255 | spin_unlock(&e1000_eeprom_lock); | |
5256 | return ret; | |
5257 | } | |
5258 | ||
5259 | ||
5260 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
1da177e4 LT |
5261 | { |
5262 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 | 5263 | s32 status = 0; |
1da177e4 LT |
5264 | |
5265 | DEBUGFUNC("e1000_write_eeprom"); | |
5266 | ||
2a88c173 JK |
5267 | /* If eeprom is not yet detected, do so now */ |
5268 | if (eeprom->word_size == 0) | |
5269 | e1000_init_eeprom_params(hw); | |
5270 | ||
1da177e4 LT |
5271 | /* A check for invalid values: offset too large, too many words, and not |
5272 | * enough words. | |
5273 | */ | |
8fc897b0 | 5274 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
1da177e4 LT |
5275 | (words == 0)) { |
5276 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
5277 | return -E1000_ERR_EEPROM; | |
5278 | } | |
5279 | ||
868d5309 | 5280 | /* 82573 writes only through eewr */ |
c3033b01 | 5281 | if (eeprom->use_eewr) |
2d7edb92 MC |
5282 | return e1000_write_eeprom_eewr(hw, offset, words, data); |
5283 | ||
cd94dd0b AK |
5284 | if (eeprom->type == e1000_eeprom_ich8) |
5285 | return e1000_write_eeprom_ich8(hw, offset, words, data); | |
5286 | ||
1da177e4 LT |
5287 | /* Prepare the EEPROM for writing */ |
5288 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
5289 | return -E1000_ERR_EEPROM; | |
5290 | ||
8fc897b0 | 5291 | if (eeprom->type == e1000_eeprom_microwire) { |
1da177e4 LT |
5292 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
5293 | } else { | |
5294 | status = e1000_write_eeprom_spi(hw, offset, words, data); | |
f8ec4733 | 5295 | msleep(10); |
1da177e4 LT |
5296 | } |
5297 | ||
5298 | /* Done with writing */ | |
5299 | e1000_release_eeprom(hw); | |
5300 | ||
5301 | return status; | |
5302 | } | |
5303 | ||
5304 | /****************************************************************************** | |
5305 | * Writes a 16 bit word to a given offset in an SPI EEPROM. | |
5306 | * | |
5307 | * hw - Struct containing variables accessed by shared code | |
5308 | * offset - offset within the EEPROM to be written to | |
5309 | * words - number of words to write | |
5310 | * data - pointer to array of 8 bit words to be written to the EEPROM | |
5311 | * | |
5312 | *****************************************************************************/ | |
64798845 JP |
5313 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, |
5314 | u16 *data) | |
1da177e4 LT |
5315 | { |
5316 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 | 5317 | u16 widx = 0; |
1da177e4 LT |
5318 | |
5319 | DEBUGFUNC("e1000_write_eeprom_spi"); | |
5320 | ||
5321 | while (widx < words) { | |
406874a7 | 5322 | u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; |
1da177e4 | 5323 | |
8fc897b0 | 5324 | if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
1da177e4 LT |
5325 | |
5326 | e1000_standby_eeprom(hw); | |
5327 | ||
5328 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
5329 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, | |
5330 | eeprom->opcode_bits); | |
5331 | ||
5332 | e1000_standby_eeprom(hw); | |
5333 | ||
5334 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
8fc897b0 | 5335 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
1da177e4 LT |
5336 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
5337 | ||
5338 | /* Send the Write command (8-bit opcode + addr) */ | |
5339 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); | |
5340 | ||
406874a7 | 5341 | e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), |
1da177e4 LT |
5342 | eeprom->address_bits); |
5343 | ||
5344 | /* Send the data */ | |
5345 | ||
5346 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ | |
5347 | while (widx < words) { | |
406874a7 | 5348 | u16 word_out = data[widx]; |
1da177e4 LT |
5349 | word_out = (word_out >> 8) | (word_out << 8); |
5350 | e1000_shift_out_ee_bits(hw, word_out, 16); | |
5351 | widx++; | |
5352 | ||
5353 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE | |
5354 | * operation, while the smaller eeproms are capable of an 8-byte | |
5355 | * PAGE WRITE operation. Break the inner loop to pass new address | |
5356 | */ | |
8fc897b0 | 5357 | if ((((offset + widx)*2) % eeprom->page_size) == 0) { |
1da177e4 LT |
5358 | e1000_standby_eeprom(hw); |
5359 | break; | |
5360 | } | |
5361 | } | |
5362 | } | |
5363 | ||
5364 | return E1000_SUCCESS; | |
5365 | } | |
5366 | ||
5367 | /****************************************************************************** | |
5368 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. | |
5369 | * | |
5370 | * hw - Struct containing variables accessed by shared code | |
5371 | * offset - offset within the EEPROM to be written to | |
5372 | * words - number of words to write | |
5373 | * data - pointer to array of 16 bit words to be written to the EEPROM | |
5374 | * | |
5375 | *****************************************************************************/ | |
64798845 JP |
5376 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
5377 | u16 words, u16 *data) | |
1da177e4 LT |
5378 | { |
5379 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
406874a7 JP |
5380 | u32 eecd; |
5381 | u16 words_written = 0; | |
5382 | u16 i = 0; | |
1da177e4 LT |
5383 | |
5384 | DEBUGFUNC("e1000_write_eeprom_microwire"); | |
5385 | ||
5386 | /* Send the write enable command to the EEPROM (3-bit opcode plus | |
5387 | * 6/8-bit dummy address beginning with 11). It's less work to include | |
5388 | * the 11 of the dummy address as part of the opcode than it is to shift | |
5389 | * it over the correct number of bits for the address. This puts the | |
5390 | * EEPROM into write/erase mode. | |
5391 | */ | |
5392 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, | |
406874a7 | 5393 | (u16)(eeprom->opcode_bits + 2)); |
1da177e4 | 5394 | |
406874a7 | 5395 | e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); |
1da177e4 LT |
5396 | |
5397 | /* Prepare the EEPROM */ | |
5398 | e1000_standby_eeprom(hw); | |
5399 | ||
5400 | while (words_written < words) { | |
5401 | /* Send the Write command (3-bit opcode + addr) */ | |
5402 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, | |
5403 | eeprom->opcode_bits); | |
5404 | ||
406874a7 | 5405 | e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), |
1da177e4 LT |
5406 | eeprom->address_bits); |
5407 | ||
5408 | /* Send the data */ | |
5409 | e1000_shift_out_ee_bits(hw, data[words_written], 16); | |
5410 | ||
5411 | /* Toggle the CS line. This in effect tells the EEPROM to execute | |
5412 | * the previous command. | |
5413 | */ | |
5414 | e1000_standby_eeprom(hw); | |
5415 | ||
5416 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will | |
5417 | * signal that the command has been completed by raising the DO signal. | |
5418 | * If DO does not go high in 10 milliseconds, then error out. | |
5419 | */ | |
8fc897b0 | 5420 | for (i = 0; i < 200; i++) { |
1dc32918 | 5421 | eecd = er32(EECD); |
8fc897b0 | 5422 | if (eecd & E1000_EECD_DO) break; |
1da177e4 LT |
5423 | udelay(50); |
5424 | } | |
8fc897b0 | 5425 | if (i == 200) { |
1da177e4 LT |
5426 | DEBUGOUT("EEPROM Write did not complete\n"); |
5427 | return -E1000_ERR_EEPROM; | |
5428 | } | |
5429 | ||
5430 | /* Recover from write */ | |
5431 | e1000_standby_eeprom(hw); | |
5432 | ||
5433 | words_written++; | |
5434 | } | |
5435 | ||
5436 | /* Send the write disable command to the EEPROM (3-bit opcode plus | |
5437 | * 6/8-bit dummy address beginning with 10). It's less work to include | |
5438 | * the 10 of the dummy address as part of the opcode than it is to shift | |
5439 | * it over the correct number of bits for the address. This takes the | |
5440 | * EEPROM out of write/erase mode. | |
5441 | */ | |
5442 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, | |
406874a7 | 5443 | (u16)(eeprom->opcode_bits + 2)); |
1da177e4 | 5444 | |
406874a7 | 5445 | e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); |
1da177e4 LT |
5446 | |
5447 | return E1000_SUCCESS; | |
5448 | } | |
5449 | ||
2d7edb92 MC |
5450 | /****************************************************************************** |
5451 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | |
5452 | * in the eeprom cache and the non modified values in the currently active bank | |
5453 | * to the new bank. | |
5454 | * | |
5455 | * hw - Struct containing variables accessed by shared code | |
5456 | * offset - offset of word in the EEPROM to read | |
5457 | * data - word read from the EEPROM | |
5458 | * words - number of words to read | |
5459 | *****************************************************************************/ | |
64798845 | 5460 | static s32 e1000_commit_shadow_ram(struct e1000_hw *hw) |
2d7edb92 | 5461 | { |
406874a7 JP |
5462 | u32 attempts = 100000; |
5463 | u32 eecd = 0; | |
5464 | u32 flop = 0; | |
5465 | u32 i = 0; | |
5466 | s32 error = E1000_SUCCESS; | |
5467 | u32 old_bank_offset = 0; | |
5468 | u32 new_bank_offset = 0; | |
5469 | u8 low_byte = 0; | |
5470 | u8 high_byte = 0; | |
c3033b01 | 5471 | bool sector_write_failed = false; |
2d7edb92 MC |
5472 | |
5473 | if (hw->mac_type == e1000_82573) { | |
cd94dd0b | 5474 | /* The flop register will be used to determine if flash type is STM */ |
1dc32918 | 5475 | flop = er32(FLOP); |
2d7edb92 | 5476 | for (i=0; i < attempts; i++) { |
1dc32918 | 5477 | eecd = er32(EECD); |
2d7edb92 MC |
5478 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
5479 | break; | |
5480 | } | |
5481 | udelay(5); | |
5482 | } | |
5483 | ||
5484 | if (i == attempts) { | |
5485 | return -E1000_ERR_EEPROM; | |
5486 | } | |
5487 | ||
96838a40 | 5488 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
2d7edb92 | 5489 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
1dc32918 | 5490 | ew32(HICR, E1000_HICR_FW_RESET); |
2d7edb92 MC |
5491 | } |
5492 | ||
5493 | /* Perform the flash update */ | |
1dc32918 | 5494 | ew32(EECD, eecd | E1000_EECD_FLUPD); |
2d7edb92 | 5495 | |
96838a40 | 5496 | for (i=0; i < attempts; i++) { |
1dc32918 | 5497 | eecd = er32(EECD); |
2d7edb92 MC |
5498 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
5499 | break; | |
5500 | } | |
5501 | udelay(5); | |
5502 | } | |
5503 | ||
5504 | if (i == attempts) { | |
5505 | return -E1000_ERR_EEPROM; | |
5506 | } | |
5507 | } | |
5508 | ||
cd94dd0b AK |
5509 | if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { |
5510 | /* We're writing to the opposite bank so if we're on bank 1, | |
5511 | * write to bank 0 etc. We also need to erase the segment that | |
5512 | * is going to be written */ | |
1dc32918 | 5513 | if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { |
cd94dd0b AK |
5514 | new_bank_offset = hw->flash_bank_size * 2; |
5515 | old_bank_offset = 0; | |
5516 | e1000_erase_ich8_4k_segment(hw, 1); | |
5517 | } else { | |
5518 | old_bank_offset = hw->flash_bank_size * 2; | |
5519 | new_bank_offset = 0; | |
5520 | e1000_erase_ich8_4k_segment(hw, 0); | |
5521 | } | |
5522 | ||
c3033b01 | 5523 | sector_write_failed = false; |
2a88c173 JK |
5524 | /* Loop for every byte in the shadow RAM, |
5525 | * which is in units of words. */ | |
5526 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
5527 | /* Determine whether to write the value stored | |
5528 | * in the other NVM bank or a modified value stored | |
5529 | * in the shadow RAM */ | |
c3033b01 | 5530 | if (hw->eeprom_shadow_ram[i].modified) { |
406874a7 | 5531 | low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word; |
2a88c173 JK |
5532 | udelay(100); |
5533 | error = e1000_verify_write_ich8_byte(hw, | |
5534 | (i << 1) + new_bank_offset, low_byte); | |
5535 | ||
5536 | if (error != E1000_SUCCESS) | |
c3033b01 | 5537 | sector_write_failed = true; |
2a88c173 | 5538 | else { |
cd94dd0b | 5539 | high_byte = |
406874a7 | 5540 | (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); |
cd94dd0b | 5541 | udelay(100); |
2a88c173 JK |
5542 | } |
5543 | } else { | |
5544 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, | |
5545 | &low_byte); | |
5546 | udelay(100); | |
5547 | error = e1000_verify_write_ich8_byte(hw, | |
5548 | (i << 1) + new_bank_offset, low_byte); | |
5549 | ||
5550 | if (error != E1000_SUCCESS) | |
c3033b01 | 5551 | sector_write_failed = true; |
2a88c173 | 5552 | else { |
cd94dd0b AK |
5553 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
5554 | &high_byte); | |
2a88c173 | 5555 | udelay(100); |
cd94dd0b | 5556 | } |
2a88c173 | 5557 | } |
cd94dd0b | 5558 | |
c3033b01 | 5559 | /* If the write of the low byte was successful, go ahead and |
2a88c173 JK |
5560 | * write the high byte while checking to make sure that if it |
5561 | * is the signature byte, then it is handled properly */ | |
c3033b01 | 5562 | if (!sector_write_failed) { |
cd94dd0b AK |
5563 | /* If the word is 0x13, then make sure the signature bits |
5564 | * (15:14) are 11b until the commit has completed. | |
5565 | * This will allow us to write 10b which indicates the | |
5566 | * signature is valid. We want to do this after the write | |
5567 | * has completed so that we don't mark the segment valid | |
5568 | * while the write is still in progress */ | |
2df7d59f JK |
5569 | if (i == E1000_ICH_NVM_SIG_WORD) |
5570 | high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; | |
cd94dd0b AK |
5571 | |
5572 | error = e1000_verify_write_ich8_byte(hw, | |
2a88c173 | 5573 | (i << 1) + new_bank_offset + 1, high_byte); |
cd94dd0b | 5574 | if (error != E1000_SUCCESS) |
c3033b01 | 5575 | sector_write_failed = true; |
cd94dd0b | 5576 | |
2a88c173 JK |
5577 | } else { |
5578 | /* If the write failed then break from the loop and | |
5579 | * return an error */ | |
5580 | break; | |
cd94dd0b | 5581 | } |
2a88c173 | 5582 | } |
cd94dd0b | 5583 | |
2a88c173 JK |
5584 | /* Don't bother writing the segment valid bits if sector |
5585 | * programming failed. */ | |
c3033b01 | 5586 | if (!sector_write_failed) { |
2a88c173 JK |
5587 | /* Finally validate the new segment by setting bit 15:14 |
5588 | * to 10b in word 0x13 , this can be done without an | |
5589 | * erase as well since these bits are 11 to start with | |
5590 | * and we need to change bit 14 to 0b */ | |
5591 | e1000_read_ich8_byte(hw, | |
2df7d59f | 5592 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
2a88c173 JK |
5593 | &high_byte); |
5594 | high_byte &= 0xBF; | |
5595 | error = e1000_verify_write_ich8_byte(hw, | |
2df7d59f | 5596 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); |
2a88c173 JK |
5597 | /* And invalidate the previously valid segment by setting |
5598 | * its signature word (0x13) high_byte to 0b. This can be | |
5599 | * done without an erase because flash erase sets all bits | |
5600 | * to 1's. We can write 1's to 0's without an erase */ | |
5601 | if (error == E1000_SUCCESS) { | |
cd94dd0b | 5602 | error = e1000_verify_write_ich8_byte(hw, |
2df7d59f | 5603 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); |
2a88c173 | 5604 | } |
cd94dd0b | 5605 | |
2a88c173 JK |
5606 | /* Clear the now not used entry in the cache */ |
5607 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | |
c3033b01 | 5608 | hw->eeprom_shadow_ram[i].modified = false; |
2a88c173 | 5609 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
cd94dd0b | 5610 | } |
2a88c173 | 5611 | } |
cd94dd0b AK |
5612 | } |
5613 | ||
2d7edb92 MC |
5614 | return error; |
5615 | } | |
5616 | ||
1da177e4 LT |
5617 | /****************************************************************************** |
5618 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
5619 | * second function of dual function devices | |
5620 | * | |
5621 | * hw - Struct containing variables accessed by shared code | |
5622 | *****************************************************************************/ | |
64798845 | 5623 | s32 e1000_read_mac_addr(struct e1000_hw *hw) |
1da177e4 | 5624 | { |
406874a7 JP |
5625 | u16 offset; |
5626 | u16 eeprom_data, i; | |
1da177e4 LT |
5627 | |
5628 | DEBUGFUNC("e1000_read_mac_addr"); | |
5629 | ||
8fc897b0 | 5630 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
1da177e4 | 5631 | offset = i >> 1; |
8fc897b0 | 5632 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
1da177e4 LT |
5633 | DEBUGOUT("EEPROM Read Error\n"); |
5634 | return -E1000_ERR_EEPROM; | |
5635 | } | |
e982f17c JP |
5636 | hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); |
5637 | hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8); | |
1da177e4 | 5638 | } |
96838a40 | 5639 | |
868d5309 MC |
5640 | switch (hw->mac_type) { |
5641 | default: | |
5642 | break; | |
5643 | case e1000_82546: | |
5644 | case e1000_82546_rev_3: | |
5645 | case e1000_82571: | |
6418ecc6 | 5646 | case e1000_80003es2lan: |
1dc32918 | 5647 | if (er32(STATUS) & E1000_STATUS_FUNC_1) |
1da177e4 | 5648 | hw->perm_mac_addr[5] ^= 0x01; |
868d5309 MC |
5649 | break; |
5650 | } | |
1da177e4 | 5651 | |
8fc897b0 | 5652 | for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
1da177e4 LT |
5653 | hw->mac_addr[i] = hw->perm_mac_addr[i]; |
5654 | return E1000_SUCCESS; | |
5655 | } | |
5656 | ||
5657 | /****************************************************************************** | |
5658 | * Initializes receive address filters. | |
5659 | * | |
5660 | * hw - Struct containing variables accessed by shared code | |
5661 | * | |
5662 | * Places the MAC address in receive address register 0 and clears the rest | |
5663 | * of the receive addresss registers. Clears the multicast table. Assumes | |
5664 | * the receiver is in reset when the routine is called. | |
5665 | *****************************************************************************/ | |
64798845 | 5666 | static void e1000_init_rx_addrs(struct e1000_hw *hw) |
1da177e4 | 5667 | { |
406874a7 JP |
5668 | u32 i; |
5669 | u32 rar_num; | |
1da177e4 LT |
5670 | |
5671 | DEBUGFUNC("e1000_init_rx_addrs"); | |
5672 | ||
5673 | /* Setup the receive address. */ | |
5674 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
5675 | ||
5676 | e1000_rar_set(hw, hw->mac_addr, 0); | |
5677 | ||
2d7edb92 | 5678 | rar_num = E1000_RAR_ENTRIES; |
868d5309 MC |
5679 | |
5680 | /* Reserve a spot for the Locally Administered Address to work around | |
5681 | * an 82571 issue in which a reset on one port will reload the MAC on | |
5682 | * the other port. */ | |
c3033b01 | 5683 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present)) |
868d5309 | 5684 | rar_num -= 1; |
cd94dd0b AK |
5685 | if (hw->mac_type == e1000_ich8lan) |
5686 | rar_num = E1000_RAR_ENTRIES_ICH8LAN; | |
5687 | ||
1da177e4 LT |
5688 | /* Zero out the other 15 receive addresses. */ |
5689 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
8fc897b0 | 5690 | for (i = 1; i < rar_num; i++) { |
1da177e4 | 5691 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
1dc32918 | 5692 | E1000_WRITE_FLUSH(); |
1da177e4 | 5693 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
1dc32918 | 5694 | E1000_WRITE_FLUSH(); |
1da177e4 LT |
5695 | } |
5696 | } | |
5697 | ||
1da177e4 LT |
5698 | /****************************************************************************** |
5699 | * Hashes an address to determine its location in the multicast table | |
5700 | * | |
5701 | * hw - Struct containing variables accessed by shared code | |
5702 | * mc_addr - the multicast address to hash | |
5703 | *****************************************************************************/ | |
64798845 | 5704 | u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
1da177e4 | 5705 | { |
406874a7 | 5706 | u32 hash_value = 0; |
1da177e4 LT |
5707 | |
5708 | /* The portion of the address that is used for the hash table is | |
5709 | * determined by the mc_filter_type setting. | |
5710 | */ | |
5711 | switch (hw->mc_filter_type) { | |
5712 | /* [0] [1] [2] [3] [4] [5] | |
5713 | * 01 AA 00 12 34 56 | |
5714 | * LSB MSB | |
5715 | */ | |
5716 | case 0: | |
cd94dd0b AK |
5717 | if (hw->mac_type == e1000_ich8lan) { |
5718 | /* [47:38] i.e. 0x158 for above example address */ | |
e982f17c | 5719 | hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2)); |
cd94dd0b AK |
5720 | } else { |
5721 | /* [47:36] i.e. 0x563 for above example address */ | |
e982f17c | 5722 | hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
cd94dd0b | 5723 | } |
1da177e4 LT |
5724 | break; |
5725 | case 1: | |
cd94dd0b AK |
5726 | if (hw->mac_type == e1000_ich8lan) { |
5727 | /* [46:37] i.e. 0x2B1 for above example address */ | |
e982f17c | 5728 | hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3)); |
cd94dd0b AK |
5729 | } else { |
5730 | /* [46:35] i.e. 0xAC6 for above example address */ | |
e982f17c | 5731 | hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
cd94dd0b | 5732 | } |
1da177e4 LT |
5733 | break; |
5734 | case 2: | |
cd94dd0b AK |
5735 | if (hw->mac_type == e1000_ich8lan) { |
5736 | /*[45:36] i.e. 0x163 for above example address */ | |
e982f17c | 5737 | hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
cd94dd0b AK |
5738 | } else { |
5739 | /* [45:34] i.e. 0x5D8 for above example address */ | |
e982f17c | 5740 | hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
cd94dd0b | 5741 | } |
1da177e4 LT |
5742 | break; |
5743 | case 3: | |
cd94dd0b AK |
5744 | if (hw->mac_type == e1000_ich8lan) { |
5745 | /* [43:34] i.e. 0x18D for above example address */ | |
e982f17c | 5746 | hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
cd94dd0b AK |
5747 | } else { |
5748 | /* [43:32] i.e. 0x634 for above example address */ | |
e982f17c | 5749 | hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
cd94dd0b | 5750 | } |
1da177e4 LT |
5751 | break; |
5752 | } | |
5753 | ||
5754 | hash_value &= 0xFFF; | |
cd94dd0b AK |
5755 | if (hw->mac_type == e1000_ich8lan) |
5756 | hash_value &= 0x3FF; | |
2d7edb92 | 5757 | |
1da177e4 LT |
5758 | return hash_value; |
5759 | } | |
5760 | ||
1da177e4 LT |
5761 | /****************************************************************************** |
5762 | * Puts an ethernet address into a receive address register. | |
5763 | * | |
5764 | * hw - Struct containing variables accessed by shared code | |
5765 | * addr - Address to put into receive address register | |
5766 | * index - Receive address register to write | |
5767 | *****************************************************************************/ | |
64798845 | 5768 | void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
1da177e4 | 5769 | { |
406874a7 | 5770 | u32 rar_low, rar_high; |
1da177e4 LT |
5771 | |
5772 | /* HW expects these in little endian so we reverse the byte order | |
5773 | * from network order (big endian) to little endian | |
5774 | */ | |
e982f17c JP |
5775 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | |
5776 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | |
5777 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | |
1da177e4 | 5778 | |
8df06e50 JK |
5779 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
5780 | * unit hang. | |
5781 | * | |
5782 | * Description: | |
5783 | * If there are any Rx frames queued up or otherwise present in the HW | |
5784 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will | |
5785 | * hang. To work around this issue, we have to disable receives and | |
5786 | * flush out all Rx frames before we enable RSS. To do so, we modify we | |
5787 | * redirect all Rx traffic to manageability and then reset the HW. | |
5788 | * This flushes away Rx frames, and (since the redirections to | |
5789 | * manageability persists across resets) keeps new ones from coming in | |
5790 | * while we work. Then, we clear the Address Valid AV bit for all MAC | |
5791 | * addresses and undo the re-direction to manageability. | |
5792 | * Now, frames are coming in again, but the MAC won't accept them, so | |
5793 | * far so good. We now proceed to initialize RSS (if necessary) and | |
5794 | * configure the Rx unit. Last, we re-enable the AV bits and continue | |
5795 | * on our merry way. | |
5796 | */ | |
5797 | switch (hw->mac_type) { | |
5798 | case e1000_82571: | |
5799 | case e1000_82572: | |
6418ecc6 | 5800 | case e1000_80003es2lan: |
c3033b01 | 5801 | if (hw->leave_av_bit_off) |
8df06e50 JK |
5802 | break; |
5803 | default: | |
5804 | /* Indicate to hardware the Address is Valid. */ | |
5805 | rar_high |= E1000_RAH_AV; | |
5806 | break; | |
5807 | } | |
1da177e4 LT |
5808 | |
5809 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); | |
1dc32918 | 5810 | E1000_WRITE_FLUSH(); |
1da177e4 | 5811 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
1dc32918 | 5812 | E1000_WRITE_FLUSH(); |
1da177e4 LT |
5813 | } |
5814 | ||
5815 | /****************************************************************************** | |
5816 | * Writes a value to the specified offset in the VLAN filter table. | |
5817 | * | |
5818 | * hw - Struct containing variables accessed by shared code | |
5819 | * offset - Offset in VLAN filer table to write | |
5820 | * value - Value to write into VLAN filter table | |
5821 | *****************************************************************************/ | |
64798845 | 5822 | void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
1da177e4 | 5823 | { |
406874a7 | 5824 | u32 temp; |
1da177e4 | 5825 | |
cd94dd0b AK |
5826 | if (hw->mac_type == e1000_ich8lan) |
5827 | return; | |
5828 | ||
5829 | if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { | |
1da177e4 LT |
5830 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
5831 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
1dc32918 | 5832 | E1000_WRITE_FLUSH(); |
1da177e4 | 5833 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
1dc32918 | 5834 | E1000_WRITE_FLUSH(); |
1da177e4 LT |
5835 | } else { |
5836 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
1dc32918 | 5837 | E1000_WRITE_FLUSH(); |
1da177e4 LT |
5838 | } |
5839 | } | |
5840 | ||
5841 | /****************************************************************************** | |
5842 | * Clears the VLAN filer table | |
5843 | * | |
5844 | * hw - Struct containing variables accessed by shared code | |
5845 | *****************************************************************************/ | |
64798845 | 5846 | static void e1000_clear_vfta(struct e1000_hw *hw) |
1da177e4 | 5847 | { |
406874a7 JP |
5848 | u32 offset; |
5849 | u32 vfta_value = 0; | |
5850 | u32 vfta_offset = 0; | |
5851 | u32 vfta_bit_in_reg = 0; | |
2d7edb92 | 5852 | |
cd94dd0b AK |
5853 | if (hw->mac_type == e1000_ich8lan) |
5854 | return; | |
5855 | ||
2d7edb92 MC |
5856 | if (hw->mac_type == e1000_82573) { |
5857 | if (hw->mng_cookie.vlan_id != 0) { | |
5858 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | |
5859 | * ID. The following operations determine which 32b entry | |
5860 | * (i.e. offset) into the array we want to set the VLAN ID | |
5861 | * (i.e. bit) of the manageability unit. */ | |
5862 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
5863 | E1000_VFTA_ENTRY_SHIFT) & | |
5864 | E1000_VFTA_ENTRY_MASK; | |
5865 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
5866 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
5867 | } | |
5868 | } | |
5869 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
5870 | /* If the offset we want to clear is the same offset of the | |
5871 | * manageability VLAN ID, then clear all bits except that of the | |
5872 | * manageability unit */ | |
5873 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
5874 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | |
1dc32918 | 5875 | E1000_WRITE_FLUSH(); |
2d7edb92 | 5876 | } |
1da177e4 LT |
5877 | } |
5878 | ||
64798845 | 5879 | static s32 e1000_id_led_init(struct e1000_hw *hw) |
1da177e4 | 5880 | { |
406874a7 JP |
5881 | u32 ledctl; |
5882 | const u32 ledctl_mask = 0x000000FF; | |
5883 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
5884 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
5885 | u16 eeprom_data, i, temp; | |
5886 | const u16 led_mask = 0x0F; | |
1da177e4 LT |
5887 | |
5888 | DEBUGFUNC("e1000_id_led_init"); | |
5889 | ||
8fc897b0 | 5890 | if (hw->mac_type < e1000_82540) { |
1da177e4 LT |
5891 | /* Nothing to do */ |
5892 | return E1000_SUCCESS; | |
5893 | } | |
5894 | ||
1dc32918 | 5895 | ledctl = er32(LEDCTL); |
1da177e4 LT |
5896 | hw->ledctl_default = ledctl; |
5897 | hw->ledctl_mode1 = hw->ledctl_default; | |
5898 | hw->ledctl_mode2 = hw->ledctl_default; | |
5899 | ||
8fc897b0 | 5900 | if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
1da177e4 LT |
5901 | DEBUGOUT("EEPROM Read Error\n"); |
5902 | return -E1000_ERR_EEPROM; | |
5903 | } | |
cd94dd0b AK |
5904 | |
5905 | if ((hw->mac_type == e1000_82573) && | |
5906 | (eeprom_data == ID_LED_RESERVED_82573)) | |
5907 | eeprom_data = ID_LED_DEFAULT_82573; | |
5908 | else if ((eeprom_data == ID_LED_RESERVED_0000) || | |
5909 | (eeprom_data == ID_LED_RESERVED_FFFF)) { | |
5910 | if (hw->mac_type == e1000_ich8lan) | |
5911 | eeprom_data = ID_LED_DEFAULT_ICH8LAN; | |
5912 | else | |
5913 | eeprom_data = ID_LED_DEFAULT; | |
5914 | } | |
90fb5135 | 5915 | |
cd94dd0b | 5916 | for (i = 0; i < 4; i++) { |
1da177e4 | 5917 | temp = (eeprom_data >> (i << 2)) & led_mask; |
8fc897b0 | 5918 | switch (temp) { |
1da177e4 LT |
5919 | case ID_LED_ON1_DEF2: |
5920 | case ID_LED_ON1_ON2: | |
5921 | case ID_LED_ON1_OFF2: | |
5922 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
5923 | hw->ledctl_mode1 |= ledctl_on << (i << 3); | |
5924 | break; | |
5925 | case ID_LED_OFF1_DEF2: | |
5926 | case ID_LED_OFF1_ON2: | |
5927 | case ID_LED_OFF1_OFF2: | |
5928 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
5929 | hw->ledctl_mode1 |= ledctl_off << (i << 3); | |
5930 | break; | |
5931 | default: | |
5932 | /* Do nothing */ | |
5933 | break; | |
5934 | } | |
8fc897b0 | 5935 | switch (temp) { |
1da177e4 LT |
5936 | case ID_LED_DEF1_ON2: |
5937 | case ID_LED_ON1_ON2: | |
5938 | case ID_LED_OFF1_ON2: | |
5939 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
5940 | hw->ledctl_mode2 |= ledctl_on << (i << 3); | |
5941 | break; | |
5942 | case ID_LED_DEF1_OFF2: | |
5943 | case ID_LED_ON1_OFF2: | |
5944 | case ID_LED_OFF1_OFF2: | |
5945 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
5946 | hw->ledctl_mode2 |= ledctl_off << (i << 3); | |
5947 | break; | |
5948 | default: | |
5949 | /* Do nothing */ | |
5950 | break; | |
5951 | } | |
5952 | } | |
5953 | return E1000_SUCCESS; | |
5954 | } | |
5955 | ||
5956 | /****************************************************************************** | |
5957 | * Prepares SW controlable LED for use and saves the current state of the LED. | |
5958 | * | |
5959 | * hw - Struct containing variables accessed by shared code | |
5960 | *****************************************************************************/ | |
64798845 | 5961 | s32 e1000_setup_led(struct e1000_hw *hw) |
1da177e4 | 5962 | { |
406874a7 JP |
5963 | u32 ledctl; |
5964 | s32 ret_val = E1000_SUCCESS; | |
1da177e4 LT |
5965 | |
5966 | DEBUGFUNC("e1000_setup_led"); | |
5967 | ||
8fc897b0 | 5968 | switch (hw->mac_type) { |
1da177e4 LT |
5969 | case e1000_82542_rev2_0: |
5970 | case e1000_82542_rev2_1: | |
5971 | case e1000_82543: | |
5972 | case e1000_82544: | |
5973 | /* No setup necessary */ | |
5974 | break; | |
5975 | case e1000_82541: | |
5976 | case e1000_82547: | |
5977 | case e1000_82541_rev_2: | |
5978 | case e1000_82547_rev_2: | |
5979 | /* Turn off PHY Smart Power Down (if enabled) */ | |
5980 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
5981 | &hw->phy_spd_default); | |
8fc897b0 | 5982 | if (ret_val) |
1da177e4 LT |
5983 | return ret_val; |
5984 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
406874a7 | 5985 | (u16)(hw->phy_spd_default & |
1da177e4 | 5986 | ~IGP01E1000_GMII_SPD)); |
8fc897b0 | 5987 | if (ret_val) |
1da177e4 LT |
5988 | return ret_val; |
5989 | /* Fall Through */ | |
5990 | default: | |
8fc897b0 | 5991 | if (hw->media_type == e1000_media_type_fiber) { |
1dc32918 | 5992 | ledctl = er32(LEDCTL); |
1da177e4 LT |
5993 | /* Save current LEDCTL settings */ |
5994 | hw->ledctl_default = ledctl; | |
5995 | /* Turn off LED0 */ | |
5996 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | | |
5997 | E1000_LEDCTL_LED0_BLINK | | |
5998 | E1000_LEDCTL_LED0_MODE_MASK); | |
5999 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
6000 | E1000_LEDCTL_LED0_MODE_SHIFT); | |
1dc32918 | 6001 | ew32(LEDCTL, ledctl); |
8fc897b0 | 6002 | } else if (hw->media_type == e1000_media_type_copper) |
1dc32918 | 6003 | ew32(LEDCTL, hw->ledctl_mode1); |
1da177e4 LT |
6004 | break; |
6005 | } | |
6006 | ||
6007 | return E1000_SUCCESS; | |
6008 | } | |
6009 | ||
8fc897b0 | 6010 | |
f1b3a853 AK |
6011 | /****************************************************************************** |
6012 | * Used on 82571 and later Si that has LED blink bits. | |
6013 | * Callers must use their own timer and should have already called | |
6014 | * e1000_id_led_init() | |
6015 | * Call e1000_cleanup led() to stop blinking | |
6016 | * | |
6017 | * hw - Struct containing variables accessed by shared code | |
6018 | *****************************************************************************/ | |
64798845 | 6019 | s32 e1000_blink_led_start(struct e1000_hw *hw) |
f1b3a853 | 6020 | { |
406874a7 JP |
6021 | s16 i; |
6022 | u32 ledctl_blink = 0; | |
f1b3a853 AK |
6023 | |
6024 | DEBUGFUNC("e1000_id_led_blink_on"); | |
6025 | ||
6026 | if (hw->mac_type < e1000_82571) { | |
6027 | /* Nothing to do */ | |
6028 | return E1000_SUCCESS; | |
6029 | } | |
6030 | if (hw->media_type == e1000_media_type_fiber) { | |
6031 | /* always blink LED0 for PCI-E fiber */ | |
6032 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | | |
6033 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); | |
6034 | } else { | |
6035 | /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ | |
6036 | ledctl_blink = hw->ledctl_mode2; | |
6037 | for (i=0; i < 4; i++) | |
6038 | if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == | |
6039 | E1000_LEDCTL_MODE_LED_ON) | |
6040 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); | |
6041 | } | |
6042 | ||
1dc32918 | 6043 | ew32(LEDCTL, ledctl_blink); |
f1b3a853 AK |
6044 | |
6045 | return E1000_SUCCESS; | |
6046 | } | |
6047 | ||
1da177e4 LT |
6048 | /****************************************************************************** |
6049 | * Restores the saved state of the SW controlable LED. | |
6050 | * | |
6051 | * hw - Struct containing variables accessed by shared code | |
6052 | *****************************************************************************/ | |
64798845 | 6053 | s32 e1000_cleanup_led(struct e1000_hw *hw) |
1da177e4 | 6054 | { |
406874a7 | 6055 | s32 ret_val = E1000_SUCCESS; |
1da177e4 LT |
6056 | |
6057 | DEBUGFUNC("e1000_cleanup_led"); | |
6058 | ||
8fc897b0 | 6059 | switch (hw->mac_type) { |
1da177e4 LT |
6060 | case e1000_82542_rev2_0: |
6061 | case e1000_82542_rev2_1: | |
6062 | case e1000_82543: | |
6063 | case e1000_82544: | |
6064 | /* No cleanup necessary */ | |
6065 | break; | |
6066 | case e1000_82541: | |
6067 | case e1000_82547: | |
6068 | case e1000_82541_rev_2: | |
6069 | case e1000_82547_rev_2: | |
6070 | /* Turn on PHY Smart Power Down (if previously enabled) */ | |
6071 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
6072 | hw->phy_spd_default); | |
8fc897b0 | 6073 | if (ret_val) |
1da177e4 LT |
6074 | return ret_val; |
6075 | /* Fall Through */ | |
6076 | default: | |
cd94dd0b AK |
6077 | if (hw->phy_type == e1000_phy_ife) { |
6078 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
6079 | break; | |
6080 | } | |
1da177e4 | 6081 | /* Restore LEDCTL settings */ |
1dc32918 | 6082 | ew32(LEDCTL, hw->ledctl_default); |
1da177e4 LT |
6083 | break; |
6084 | } | |
6085 | ||
6086 | return E1000_SUCCESS; | |
6087 | } | |
6088 | ||
6089 | /****************************************************************************** | |
6090 | * Turns on the software controllable LED | |
6091 | * | |
6092 | * hw - Struct containing variables accessed by shared code | |
6093 | *****************************************************************************/ | |
64798845 | 6094 | s32 e1000_led_on(struct e1000_hw *hw) |
1da177e4 | 6095 | { |
1dc32918 | 6096 | u32 ctrl = er32(CTRL); |
1da177e4 LT |
6097 | |
6098 | DEBUGFUNC("e1000_led_on"); | |
6099 | ||
8fc897b0 | 6100 | switch (hw->mac_type) { |
1da177e4 LT |
6101 | case e1000_82542_rev2_0: |
6102 | case e1000_82542_rev2_1: | |
6103 | case e1000_82543: | |
6104 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
6105 | ctrl |= E1000_CTRL_SWDPIN0; | |
6106 | ctrl |= E1000_CTRL_SWDPIO0; | |
6107 | break; | |
6108 | case e1000_82544: | |
8fc897b0 | 6109 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6110 | /* Set SW Defineable Pin 0 to turn on the LED */ |
6111 | ctrl |= E1000_CTRL_SWDPIN0; | |
6112 | ctrl |= E1000_CTRL_SWDPIO0; | |
6113 | } else { | |
6114 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
6115 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6116 | ctrl |= E1000_CTRL_SWDPIO0; | |
6117 | } | |
6118 | break; | |
6119 | default: | |
8fc897b0 | 6120 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6121 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
6122 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6123 | ctrl |= E1000_CTRL_SWDPIO0; | |
cd94dd0b AK |
6124 | } else if (hw->phy_type == e1000_phy_ife) { |
6125 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
6126 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
6127 | } else if (hw->media_type == e1000_media_type_copper) { | |
1dc32918 | 6128 | ew32(LEDCTL, hw->ledctl_mode2); |
1da177e4 LT |
6129 | return E1000_SUCCESS; |
6130 | } | |
6131 | break; | |
6132 | } | |
6133 | ||
1dc32918 | 6134 | ew32(CTRL, ctrl); |
1da177e4 LT |
6135 | |
6136 | return E1000_SUCCESS; | |
6137 | } | |
6138 | ||
6139 | /****************************************************************************** | |
6140 | * Turns off the software controllable LED | |
6141 | * | |
6142 | * hw - Struct containing variables accessed by shared code | |
6143 | *****************************************************************************/ | |
64798845 | 6144 | s32 e1000_led_off(struct e1000_hw *hw) |
1da177e4 | 6145 | { |
1dc32918 | 6146 | u32 ctrl = er32(CTRL); |
1da177e4 LT |
6147 | |
6148 | DEBUGFUNC("e1000_led_off"); | |
6149 | ||
8fc897b0 | 6150 | switch (hw->mac_type) { |
1da177e4 LT |
6151 | case e1000_82542_rev2_0: |
6152 | case e1000_82542_rev2_1: | |
6153 | case e1000_82543: | |
6154 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
6155 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6156 | ctrl |= E1000_CTRL_SWDPIO0; | |
6157 | break; | |
6158 | case e1000_82544: | |
8fc897b0 | 6159 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6160 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
6161 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
6162 | ctrl |= E1000_CTRL_SWDPIO0; | |
6163 | } else { | |
6164 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
6165 | ctrl |= E1000_CTRL_SWDPIN0; | |
6166 | ctrl |= E1000_CTRL_SWDPIO0; | |
6167 | } | |
6168 | break; | |
6169 | default: | |
8fc897b0 | 6170 | if (hw->media_type == e1000_media_type_fiber) { |
1da177e4 LT |
6171 | /* Set SW Defineable Pin 0 to turn off the LED */ |
6172 | ctrl |= E1000_CTRL_SWDPIN0; | |
6173 | ctrl |= E1000_CTRL_SWDPIO0; | |
cd94dd0b AK |
6174 | } else if (hw->phy_type == e1000_phy_ife) { |
6175 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
6176 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
6177 | } else if (hw->media_type == e1000_media_type_copper) { | |
1dc32918 | 6178 | ew32(LEDCTL, hw->ledctl_mode1); |
1da177e4 LT |
6179 | return E1000_SUCCESS; |
6180 | } | |
6181 | break; | |
6182 | } | |
6183 | ||
1dc32918 | 6184 | ew32(CTRL, ctrl); |
1da177e4 LT |
6185 | |
6186 | return E1000_SUCCESS; | |
6187 | } | |
6188 | ||
6189 | /****************************************************************************** | |
6190 | * Clears all hardware statistics counters. | |
6191 | * | |
6192 | * hw - Struct containing variables accessed by shared code | |
6193 | *****************************************************************************/ | |
64798845 | 6194 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw) |
1da177e4 | 6195 | { |
406874a7 | 6196 | volatile u32 temp; |
1da177e4 | 6197 | |
1dc32918 JP |
6198 | temp = er32(CRCERRS); |
6199 | temp = er32(SYMERRS); | |
6200 | temp = er32(MPC); | |
6201 | temp = er32(SCC); | |
6202 | temp = er32(ECOL); | |
6203 | temp = er32(MCC); | |
6204 | temp = er32(LATECOL); | |
6205 | temp = er32(COLC); | |
6206 | temp = er32(DC); | |
6207 | temp = er32(SEC); | |
6208 | temp = er32(RLEC); | |
6209 | temp = er32(XONRXC); | |
6210 | temp = er32(XONTXC); | |
6211 | temp = er32(XOFFRXC); | |
6212 | temp = er32(XOFFTXC); | |
6213 | temp = er32(FCRUC); | |
cd94dd0b AK |
6214 | |
6215 | if (hw->mac_type != e1000_ich8lan) { | |
1dc32918 JP |
6216 | temp = er32(PRC64); |
6217 | temp = er32(PRC127); | |
6218 | temp = er32(PRC255); | |
6219 | temp = er32(PRC511); | |
6220 | temp = er32(PRC1023); | |
6221 | temp = er32(PRC1522); | |
6222 | } | |
6223 | ||
6224 | temp = er32(GPRC); | |
6225 | temp = er32(BPRC); | |
6226 | temp = er32(MPRC); | |
6227 | temp = er32(GPTC); | |
6228 | temp = er32(GORCL); | |
6229 | temp = er32(GORCH); | |
6230 | temp = er32(GOTCL); | |
6231 | temp = er32(GOTCH); | |
6232 | temp = er32(RNBC); | |
6233 | temp = er32(RUC); | |
6234 | temp = er32(RFC); | |
6235 | temp = er32(ROC); | |
6236 | temp = er32(RJC); | |
6237 | temp = er32(TORL); | |
6238 | temp = er32(TORH); | |
6239 | temp = er32(TOTL); | |
6240 | temp = er32(TOTH); | |
6241 | temp = er32(TPR); | |
6242 | temp = er32(TPT); | |
cd94dd0b AK |
6243 | |
6244 | if (hw->mac_type != e1000_ich8lan) { | |
1dc32918 JP |
6245 | temp = er32(PTC64); |
6246 | temp = er32(PTC127); | |
6247 | temp = er32(PTC255); | |
6248 | temp = er32(PTC511); | |
6249 | temp = er32(PTC1023); | |
6250 | temp = er32(PTC1522); | |
cd94dd0b AK |
6251 | } |
6252 | ||
1dc32918 JP |
6253 | temp = er32(MPTC); |
6254 | temp = er32(BPTC); | |
1da177e4 | 6255 | |
8fc897b0 | 6256 | if (hw->mac_type < e1000_82543) return; |
1da177e4 | 6257 | |
1dc32918 JP |
6258 | temp = er32(ALGNERRC); |
6259 | temp = er32(RXERRC); | |
6260 | temp = er32(TNCRS); | |
6261 | temp = er32(CEXTERR); | |
6262 | temp = er32(TSCTC); | |
6263 | temp = er32(TSCTFC); | |
1da177e4 | 6264 | |
8fc897b0 | 6265 | if (hw->mac_type <= e1000_82544) return; |
1da177e4 | 6266 | |
1dc32918 JP |
6267 | temp = er32(MGTPRC); |
6268 | temp = er32(MGTPDC); | |
6269 | temp = er32(MGTPTC); | |
2d7edb92 | 6270 | |
8fc897b0 | 6271 | if (hw->mac_type <= e1000_82547_rev_2) return; |
2d7edb92 | 6272 | |
1dc32918 JP |
6273 | temp = er32(IAC); |
6274 | temp = er32(ICRXOC); | |
cd94dd0b AK |
6275 | |
6276 | if (hw->mac_type == e1000_ich8lan) return; | |
6277 | ||
1dc32918 JP |
6278 | temp = er32(ICRXPTC); |
6279 | temp = er32(ICRXATC); | |
6280 | temp = er32(ICTXPTC); | |
6281 | temp = er32(ICTXATC); | |
6282 | temp = er32(ICTXQEC); | |
6283 | temp = er32(ICTXQMTC); | |
6284 | temp = er32(ICRXDMTC); | |
1da177e4 LT |
6285 | } |
6286 | ||
6287 | /****************************************************************************** | |
6288 | * Resets Adaptive IFS to its default state. | |
6289 | * | |
6290 | * hw - Struct containing variables accessed by shared code | |
6291 | * | |
6292 | * Call this after e1000_init_hw. You may override the IFS defaults by setting | |
c3033b01 | 6293 | * hw->ifs_params_forced to true. However, you must initialize hw-> |
1da177e4 LT |
6294 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
6295 | * before calling this function. | |
6296 | *****************************************************************************/ | |
64798845 | 6297 | void e1000_reset_adaptive(struct e1000_hw *hw) |
1da177e4 LT |
6298 | { |
6299 | DEBUGFUNC("e1000_reset_adaptive"); | |
6300 | ||
8fc897b0 AK |
6301 | if (hw->adaptive_ifs) { |
6302 | if (!hw->ifs_params_forced) { | |
1da177e4 LT |
6303 | hw->current_ifs_val = 0; |
6304 | hw->ifs_min_val = IFS_MIN; | |
6305 | hw->ifs_max_val = IFS_MAX; | |
6306 | hw->ifs_step_size = IFS_STEP; | |
6307 | hw->ifs_ratio = IFS_RATIO; | |
6308 | } | |
c3033b01 | 6309 | hw->in_ifs_mode = false; |
1dc32918 | 6310 | ew32(AIT, 0); |
1da177e4 LT |
6311 | } else { |
6312 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
6313 | } | |
6314 | } | |
6315 | ||
6316 | /****************************************************************************** | |
6317 | * Called during the callback/watchdog routine to update IFS value based on | |
6318 | * the ratio of transmits to collisions. | |
6319 | * | |
6320 | * hw - Struct containing variables accessed by shared code | |
6321 | * tx_packets - Number of transmits since last callback | |
6322 | * total_collisions - Number of collisions since last callback | |
6323 | *****************************************************************************/ | |
64798845 | 6324 | void e1000_update_adaptive(struct e1000_hw *hw) |
1da177e4 LT |
6325 | { |
6326 | DEBUGFUNC("e1000_update_adaptive"); | |
6327 | ||
8fc897b0 AK |
6328 | if (hw->adaptive_ifs) { |
6329 | if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { | |
6330 | if (hw->tx_packet_delta > MIN_NUM_XMITS) { | |
c3033b01 | 6331 | hw->in_ifs_mode = true; |
8fc897b0 AK |
6332 | if (hw->current_ifs_val < hw->ifs_max_val) { |
6333 | if (hw->current_ifs_val == 0) | |
1da177e4 LT |
6334 | hw->current_ifs_val = hw->ifs_min_val; |
6335 | else | |
6336 | hw->current_ifs_val += hw->ifs_step_size; | |
1dc32918 | 6337 | ew32(AIT, hw->current_ifs_val); |
1da177e4 LT |
6338 | } |
6339 | } | |
6340 | } else { | |
8fc897b0 | 6341 | if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
1da177e4 | 6342 | hw->current_ifs_val = 0; |
c3033b01 | 6343 | hw->in_ifs_mode = false; |
1dc32918 | 6344 | ew32(AIT, 0); |
1da177e4 LT |
6345 | } |
6346 | } | |
6347 | } else { | |
6348 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
6349 | } | |
6350 | } | |
6351 | ||
6352 | /****************************************************************************** | |
6353 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT | |
6354 | * | |
6355 | * hw - Struct containing variables accessed by shared code | |
6356 | * frame_len - The length of the frame in question | |
6357 | * mac_addr - The Ethernet destination address of the frame in question | |
6358 | *****************************************************************************/ | |
64798845 JP |
6359 | void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, |
6360 | u32 frame_len, u8 *mac_addr) | |
1da177e4 | 6361 | { |
406874a7 | 6362 | u64 carry_bit; |
1da177e4 LT |
6363 | |
6364 | /* First adjust the frame length. */ | |
6365 | frame_len--; | |
6366 | /* We need to adjust the statistics counters, since the hardware | |
6367 | * counters overcount this packet as a CRC error and undercount | |
6368 | * the packet as a good packet | |
6369 | */ | |
6370 | /* This packet should not be counted as a CRC error. */ | |
6371 | stats->crcerrs--; | |
6372 | /* This packet does count as a Good Packet Received. */ | |
6373 | stats->gprc++; | |
6374 | ||
6375 | /* Adjust the Good Octets received counters */ | |
6376 | carry_bit = 0x80000000 & stats->gorcl; | |
6377 | stats->gorcl += frame_len; | |
6378 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets | |
6379 | * Received Count) was one before the addition, | |
6380 | * AND it is zero after, then we lost the carry out, | |
6381 | * need to add one to Gorch (Good Octets Received Count High). | |
6382 | * This could be simplified if all environments supported | |
6383 | * 64-bit integers. | |
6384 | */ | |
8fc897b0 | 6385 | if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
1da177e4 LT |
6386 | stats->gorch++; |
6387 | /* Is this a broadcast or multicast? Check broadcast first, | |
6388 | * since the test for a multicast frame will test positive on | |
6389 | * a broadcast frame. | |
6390 | */ | |
e982f17c | 6391 | if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff)) |
1da177e4 LT |
6392 | /* Broadcast packet */ |
6393 | stats->bprc++; | |
8fc897b0 | 6394 | else if (*mac_addr & 0x01) |
1da177e4 LT |
6395 | /* Multicast packet */ |
6396 | stats->mprc++; | |
6397 | ||
8fc897b0 | 6398 | if (frame_len == hw->max_frame_size) { |
1da177e4 LT |
6399 | /* In this case, the hardware has overcounted the number of |
6400 | * oversize frames. | |
6401 | */ | |
8fc897b0 | 6402 | if (stats->roc > 0) |
1da177e4 LT |
6403 | stats->roc--; |
6404 | } | |
6405 | ||
6406 | /* Adjust the bin counters when the extra byte put the frame in the | |
6407 | * wrong bin. Remember that the frame_len was adjusted above. | |
6408 | */ | |
8fc897b0 | 6409 | if (frame_len == 64) { |
1da177e4 LT |
6410 | stats->prc64++; |
6411 | stats->prc127--; | |
8fc897b0 | 6412 | } else if (frame_len == 127) { |
1da177e4 LT |
6413 | stats->prc127++; |
6414 | stats->prc255--; | |
8fc897b0 | 6415 | } else if (frame_len == 255) { |
1da177e4 LT |
6416 | stats->prc255++; |
6417 | stats->prc511--; | |
8fc897b0 | 6418 | } else if (frame_len == 511) { |
1da177e4 LT |
6419 | stats->prc511++; |
6420 | stats->prc1023--; | |
8fc897b0 | 6421 | } else if (frame_len == 1023) { |
1da177e4 LT |
6422 | stats->prc1023++; |
6423 | stats->prc1522--; | |
8fc897b0 | 6424 | } else if (frame_len == 1522) { |
1da177e4 LT |
6425 | stats->prc1522++; |
6426 | } | |
6427 | } | |
6428 | ||
6429 | /****************************************************************************** | |
6430 | * Gets the current PCI bus type, speed, and width of the hardware | |
6431 | * | |
6432 | * hw - Struct containing variables accessed by shared code | |
6433 | *****************************************************************************/ | |
64798845 | 6434 | void e1000_get_bus_info(struct e1000_hw *hw) |
1da177e4 | 6435 | { |
406874a7 JP |
6436 | s32 ret_val; |
6437 | u16 pci_ex_link_status; | |
6438 | u32 status; | |
1da177e4 LT |
6439 | |
6440 | switch (hw->mac_type) { | |
6441 | case e1000_82542_rev2_0: | |
6442 | case e1000_82542_rev2_1: | |
c3813ae6 | 6443 | hw->bus_type = e1000_bus_type_pci; |
1da177e4 LT |
6444 | hw->bus_speed = e1000_bus_speed_unknown; |
6445 | hw->bus_width = e1000_bus_width_unknown; | |
6446 | break; | |
caeccb68 | 6447 | case e1000_82571: |
868d5309 | 6448 | case e1000_82572: |
2d7edb92 | 6449 | case e1000_82573: |
caeccb68 | 6450 | case e1000_80003es2lan: |
fd803241 JK |
6451 | hw->bus_type = e1000_bus_type_pci_express; |
6452 | hw->bus_speed = e1000_bus_speed_2500; | |
caeccb68 JK |
6453 | ret_val = e1000_read_pcie_cap_reg(hw, |
6454 | PCI_EX_LINK_STATUS, | |
6455 | &pci_ex_link_status); | |
6456 | if (ret_val) | |
6457 | hw->bus_width = e1000_bus_width_unknown; | |
6458 | else | |
6459 | hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> | |
6460 | PCI_EX_LINK_WIDTH_SHIFT; | |
fd803241 | 6461 | break; |
cd94dd0b | 6462 | case e1000_ich8lan: |
2d7edb92 MC |
6463 | hw->bus_type = e1000_bus_type_pci_express; |
6464 | hw->bus_speed = e1000_bus_speed_2500; | |
caeccb68 | 6465 | hw->bus_width = e1000_bus_width_pciex_1; |
2d7edb92 | 6466 | break; |
1da177e4 | 6467 | default: |
1dc32918 | 6468 | status = er32(STATUS); |
1da177e4 LT |
6469 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
6470 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
6471 | ||
8fc897b0 | 6472 | if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
1da177e4 LT |
6473 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
6474 | e1000_bus_speed_66 : e1000_bus_speed_120; | |
8fc897b0 | 6475 | } else if (hw->bus_type == e1000_bus_type_pci) { |
1da177e4 LT |
6476 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
6477 | e1000_bus_speed_66 : e1000_bus_speed_33; | |
6478 | } else { | |
6479 | switch (status & E1000_STATUS_PCIX_SPEED) { | |
6480 | case E1000_STATUS_PCIX_SPEED_66: | |
6481 | hw->bus_speed = e1000_bus_speed_66; | |
6482 | break; | |
6483 | case E1000_STATUS_PCIX_SPEED_100: | |
6484 | hw->bus_speed = e1000_bus_speed_100; | |
6485 | break; | |
6486 | case E1000_STATUS_PCIX_SPEED_133: | |
6487 | hw->bus_speed = e1000_bus_speed_133; | |
6488 | break; | |
6489 | default: | |
6490 | hw->bus_speed = e1000_bus_speed_reserved; | |
6491 | break; | |
6492 | } | |
6493 | } | |
6494 | hw->bus_width = (status & E1000_STATUS_BUS64) ? | |
6495 | e1000_bus_width_64 : e1000_bus_width_32; | |
6496 | break; | |
6497 | } | |
6498 | } | |
1da177e4 LT |
6499 | |
6500 | /****************************************************************************** | |
6501 | * Writes a value to one of the devices registers using port I/O (as opposed to | |
6502 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
6503 | * | |
6504 | * hw - Struct containing variables accessed by shared code | |
6505 | * offset - offset to write to | |
6506 | * value - value to write | |
6507 | *****************************************************************************/ | |
64798845 | 6508 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) |
1da177e4 LT |
6509 | { |
6510 | unsigned long io_addr = hw->io_base; | |
6511 | unsigned long io_data = hw->io_base + 4; | |
6512 | ||
6513 | e1000_io_write(hw, io_addr, offset); | |
6514 | e1000_io_write(hw, io_data, value); | |
6515 | } | |
6516 | ||
1da177e4 LT |
6517 | /****************************************************************************** |
6518 | * Estimates the cable length. | |
6519 | * | |
6520 | * hw - Struct containing variables accessed by shared code | |
6521 | * min_length - The estimated minimum length | |
6522 | * max_length - The estimated maximum length | |
6523 | * | |
6524 | * returns: - E1000_ERR_XXX | |
6525 | * E1000_SUCCESS | |
6526 | * | |
6527 | * This function always returns a ranged length (minimum & maximum). | |
6528 | * So for M88 phy's, this function interprets the one value returned from the | |
6529 | * register to the minimum and maximum range. | |
6530 | * For IGP phy's, the function calculates the range by the AGC registers. | |
6531 | *****************************************************************************/ | |
64798845 JP |
6532 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
6533 | u16 *max_length) | |
1da177e4 | 6534 | { |
406874a7 JP |
6535 | s32 ret_val; |
6536 | u16 agc_value = 0; | |
6537 | u16 i, phy_data; | |
6538 | u16 cable_length; | |
1da177e4 LT |
6539 | |
6540 | DEBUGFUNC("e1000_get_cable_length"); | |
6541 | ||
6542 | *min_length = *max_length = 0; | |
6543 | ||
6544 | /* Use old method for Phy older than IGP */ | |
8fc897b0 | 6545 | if (hw->phy_type == e1000_phy_m88) { |
2d7edb92 | 6546 | |
1da177e4 LT |
6547 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6548 | &phy_data); | |
8fc897b0 | 6549 | if (ret_val) |
1da177e4 LT |
6550 | return ret_val; |
6551 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
6552 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
6553 | ||
6554 | /* Convert the enum value to ranged values */ | |
6555 | switch (cable_length) { | |
6556 | case e1000_cable_length_50: | |
6557 | *min_length = 0; | |
6558 | *max_length = e1000_igp_cable_length_50; | |
6559 | break; | |
6560 | case e1000_cable_length_50_80: | |
6561 | *min_length = e1000_igp_cable_length_50; | |
6562 | *max_length = e1000_igp_cable_length_80; | |
6563 | break; | |
6564 | case e1000_cable_length_80_110: | |
6565 | *min_length = e1000_igp_cable_length_80; | |
6566 | *max_length = e1000_igp_cable_length_110; | |
6567 | break; | |
6568 | case e1000_cable_length_110_140: | |
6569 | *min_length = e1000_igp_cable_length_110; | |
6570 | *max_length = e1000_igp_cable_length_140; | |
6571 | break; | |
6572 | case e1000_cable_length_140: | |
6573 | *min_length = e1000_igp_cable_length_140; | |
6574 | *max_length = e1000_igp_cable_length_170; | |
6575 | break; | |
6576 | default: | |
6577 | return -E1000_ERR_PHY; | |
6578 | break; | |
6579 | } | |
6418ecc6 JK |
6580 | } else if (hw->phy_type == e1000_phy_gg82563) { |
6581 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
6582 | &phy_data); | |
6583 | if (ret_val) | |
6584 | return ret_val; | |
6585 | cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
6586 | ||
6587 | switch (cable_length) { | |
6588 | case e1000_gg_cable_length_60: | |
6589 | *min_length = 0; | |
6590 | *max_length = e1000_igp_cable_length_60; | |
6591 | break; | |
6592 | case e1000_gg_cable_length_60_115: | |
6593 | *min_length = e1000_igp_cable_length_60; | |
6594 | *max_length = e1000_igp_cable_length_115; | |
6595 | break; | |
6596 | case e1000_gg_cable_length_115_150: | |
6597 | *min_length = e1000_igp_cable_length_115; | |
6598 | *max_length = e1000_igp_cable_length_150; | |
6599 | break; | |
6600 | case e1000_gg_cable_length_150: | |
6601 | *min_length = e1000_igp_cable_length_150; | |
6602 | *max_length = e1000_igp_cable_length_180; | |
6603 | break; | |
6604 | default: | |
6605 | return -E1000_ERR_PHY; | |
6606 | break; | |
6607 | } | |
8fc897b0 | 6608 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
406874a7 JP |
6609 | u16 cur_agc_value; |
6610 | u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | |
6611 | u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
1da177e4 LT |
6612 | {IGP01E1000_PHY_AGC_A, |
6613 | IGP01E1000_PHY_AGC_B, | |
6614 | IGP01E1000_PHY_AGC_C, | |
6615 | IGP01E1000_PHY_AGC_D}; | |
6616 | /* Read the AGC registers for all channels */ | |
8fc897b0 | 6617 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 LT |
6618 | |
6619 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
8fc897b0 | 6620 | if (ret_val) |
1da177e4 LT |
6621 | return ret_val; |
6622 | ||
cd94dd0b | 6623 | cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
1da177e4 | 6624 | |
cd94dd0b AK |
6625 | /* Value bound check. */ |
6626 | if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || | |
6627 | (cur_agc_value == 0)) | |
1da177e4 LT |
6628 | return -E1000_ERR_PHY; |
6629 | ||
cd94dd0b | 6630 | agc_value += cur_agc_value; |
1da177e4 LT |
6631 | |
6632 | /* Update minimal AGC value. */ | |
cd94dd0b AK |
6633 | if (min_agc_value > cur_agc_value) |
6634 | min_agc_value = cur_agc_value; | |
1da177e4 LT |
6635 | } |
6636 | ||
6637 | /* Remove the minimal AGC result for length < 50m */ | |
cd94dd0b AK |
6638 | if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
6639 | agc_value -= min_agc_value; | |
1da177e4 LT |
6640 | |
6641 | /* Get the average length of the remaining 3 channels */ | |
6642 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | |
6643 | } else { | |
6644 | /* Get the average length of all the 4 channels. */ | |
6645 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; | |
6646 | } | |
6647 | ||
6648 | /* Set the range of the calculated length. */ | |
6649 | *min_length = ((e1000_igp_cable_length_table[agc_value] - | |
6650 | IGP01E1000_AGC_RANGE) > 0) ? | |
6651 | (e1000_igp_cable_length_table[agc_value] - | |
6652 | IGP01E1000_AGC_RANGE) : 0; | |
6653 | *max_length = e1000_igp_cable_length_table[agc_value] + | |
6654 | IGP01E1000_AGC_RANGE; | |
cd94dd0b AK |
6655 | } else if (hw->phy_type == e1000_phy_igp_2 || |
6656 | hw->phy_type == e1000_phy_igp_3) { | |
406874a7 JP |
6657 | u16 cur_agc_index, max_agc_index = 0; |
6658 | u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; | |
6659 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
868d5309 MC |
6660 | {IGP02E1000_PHY_AGC_A, |
6661 | IGP02E1000_PHY_AGC_B, | |
6662 | IGP02E1000_PHY_AGC_C, | |
6663 | IGP02E1000_PHY_AGC_D}; | |
6664 | /* Read the AGC registers for all channels */ | |
6665 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
6666 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
6667 | if (ret_val) | |
6668 | return ret_val; | |
6669 | ||
8fc897b0 | 6670 | /* Getting bits 15:9, which represent the combination of course and |
868d5309 MC |
6671 | * fine gain values. The result is a number that can be put into |
6672 | * the lookup table to obtain the approximate cable length. */ | |
cd94dd0b AK |
6673 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
6674 | IGP02E1000_AGC_LENGTH_MASK; | |
868d5309 | 6675 | |
cd94dd0b AK |
6676 | /* Array index bound check. */ |
6677 | if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || | |
6678 | (cur_agc_index == 0)) | |
6679 | return -E1000_ERR_PHY; | |
868d5309 | 6680 | |
cd94dd0b AK |
6681 | /* Remove min & max AGC values from calculation. */ |
6682 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
6683 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
6684 | min_agc_index = cur_agc_index; | |
6685 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
6686 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
6687 | max_agc_index = cur_agc_index; | |
6688 | ||
6689 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
868d5309 MC |
6690 | } |
6691 | ||
cd94dd0b AK |
6692 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
6693 | e1000_igp_2_cable_length_table[max_agc_index]); | |
868d5309 MC |
6694 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
6695 | ||
6696 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
6697 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
6698 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
6699 | *max_length = agc_value + IGP02E1000_AGC_RANGE; | |
1da177e4 LT |
6700 | } |
6701 | ||
6702 | return E1000_SUCCESS; | |
6703 | } | |
6704 | ||
6705 | /****************************************************************************** | |
6706 | * Check the cable polarity | |
6707 | * | |
6708 | * hw - Struct containing variables accessed by shared code | |
6709 | * polarity - output parameter : 0 - Polarity is not reversed | |
6710 | * 1 - Polarity is reversed. | |
6711 | * | |
6712 | * returns: - E1000_ERR_XXX | |
6713 | * E1000_SUCCESS | |
6714 | * | |
025dfdaf | 6715 | * For phy's older than IGP, this function simply reads the polarity bit in the |
1da177e4 LT |
6716 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
6717 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will | |
6718 | * return 0. If the link speed is 1000 Mbps the polarity status is in the | |
6719 | * IGP01E1000_PHY_PCS_INIT_REG. | |
6720 | *****************************************************************************/ | |
64798845 JP |
6721 | static s32 e1000_check_polarity(struct e1000_hw *hw, |
6722 | e1000_rev_polarity *polarity) | |
1da177e4 | 6723 | { |
406874a7 JP |
6724 | s32 ret_val; |
6725 | u16 phy_data; | |
1da177e4 LT |
6726 | |
6727 | DEBUGFUNC("e1000_check_polarity"); | |
6728 | ||
6418ecc6 JK |
6729 | if ((hw->phy_type == e1000_phy_m88) || |
6730 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6731 | /* return the Polarity bit in the Status register. */ |
6732 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | |
6733 | &phy_data); | |
8fc897b0 | 6734 | if (ret_val) |
1da177e4 | 6735 | return ret_val; |
70c6f30a JK |
6736 | *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
6737 | M88E1000_PSSR_REV_POLARITY_SHIFT) ? | |
6738 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
6739 | ||
cd94dd0b AK |
6740 | } else if (hw->phy_type == e1000_phy_igp || |
6741 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 6742 | hw->phy_type == e1000_phy_igp_2) { |
1da177e4 LT |
6743 | /* Read the Status register to check the speed */ |
6744 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | |
6745 | &phy_data); | |
8fc897b0 | 6746 | if (ret_val) |
1da177e4 LT |
6747 | return ret_val; |
6748 | ||
6749 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to | |
6750 | * find the polarity status */ | |
8fc897b0 | 6751 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
1da177e4 LT |
6752 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
6753 | ||
6754 | /* Read the GIG initialization PCS register (0x00B4) */ | |
6755 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | |
6756 | &phy_data); | |
8fc897b0 | 6757 | if (ret_val) |
1da177e4 LT |
6758 | return ret_val; |
6759 | ||
6760 | /* Check the polarity bits */ | |
70c6f30a JK |
6761 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
6762 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 LT |
6763 | } else { |
6764 | /* For 10 Mbps, read the polarity bit in the status register. (for | |
6765 | * 100 Mbps this bit is always 0) */ | |
70c6f30a JK |
6766 | *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
6767 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 | 6768 | } |
cd94dd0b AK |
6769 | } else if (hw->phy_type == e1000_phy_ife) { |
6770 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, | |
6771 | &phy_data); | |
6772 | if (ret_val) | |
6773 | return ret_val; | |
70c6f30a JK |
6774 | *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> |
6775 | IFE_PESC_POLARITY_REVERSED_SHIFT) ? | |
6776 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | |
1da177e4 LT |
6777 | } |
6778 | return E1000_SUCCESS; | |
6779 | } | |
6780 | ||
6781 | /****************************************************************************** | |
6782 | * Check if Downshift occured | |
6783 | * | |
6784 | * hw - Struct containing variables accessed by shared code | |
6785 | * downshift - output parameter : 0 - No Downshift ocured. | |
6786 | * 1 - Downshift ocured. | |
6787 | * | |
6788 | * returns: - E1000_ERR_XXX | |
76c224bc | 6789 | * E1000_SUCCESS |
1da177e4 | 6790 | * |
025dfdaf | 6791 | * For phy's older than IGP, this function reads the Downshift bit in the Phy |
1da177e4 LT |
6792 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
6793 | * Link Health register. In IGP this bit is latched high, so the driver must | |
6794 | * read it immediately after link is established. | |
6795 | *****************************************************************************/ | |
64798845 | 6796 | static s32 e1000_check_downshift(struct e1000_hw *hw) |
1da177e4 | 6797 | { |
406874a7 JP |
6798 | s32 ret_val; |
6799 | u16 phy_data; | |
1da177e4 LT |
6800 | |
6801 | DEBUGFUNC("e1000_check_downshift"); | |
6802 | ||
cd94dd0b AK |
6803 | if (hw->phy_type == e1000_phy_igp || |
6804 | hw->phy_type == e1000_phy_igp_3 || | |
2d7edb92 | 6805 | hw->phy_type == e1000_phy_igp_2) { |
1da177e4 LT |
6806 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
6807 | &phy_data); | |
8fc897b0 | 6808 | if (ret_val) |
1da177e4 LT |
6809 | return ret_val; |
6810 | ||
6811 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; | |
6418ecc6 JK |
6812 | } else if ((hw->phy_type == e1000_phy_m88) || |
6813 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6814 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6815 | &phy_data); | |
8fc897b0 | 6816 | if (ret_val) |
1da177e4 LT |
6817 | return ret_val; |
6818 | ||
6819 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | |
6820 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | |
cd94dd0b AK |
6821 | } else if (hw->phy_type == e1000_phy_ife) { |
6822 | /* e1000_phy_ife supports 10/100 speed only */ | |
c3033b01 | 6823 | hw->speed_downgraded = false; |
1da177e4 | 6824 | } |
2d7edb92 | 6825 | |
1da177e4 LT |
6826 | return E1000_SUCCESS; |
6827 | } | |
6828 | ||
6829 | /***************************************************************************** | |
6830 | * | |
6831 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a | |
6832 | * gigabit link is achieved to improve link quality. | |
6833 | * | |
6834 | * hw: Struct containing variables accessed by shared code | |
6835 | * | |
6836 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
6837 | * E1000_SUCCESS at any other case. | |
6838 | * | |
6839 | ****************************************************************************/ | |
6840 | ||
64798845 | 6841 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) |
1da177e4 | 6842 | { |
406874a7 JP |
6843 | s32 ret_val; |
6844 | u16 phy_data, phy_saved_data, speed, duplex, i; | |
6845 | u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
1da177e4 LT |
6846 | {IGP01E1000_PHY_AGC_PARAM_A, |
6847 | IGP01E1000_PHY_AGC_PARAM_B, | |
6848 | IGP01E1000_PHY_AGC_PARAM_C, | |
6849 | IGP01E1000_PHY_AGC_PARAM_D}; | |
406874a7 | 6850 | u16 min_length, max_length; |
1da177e4 LT |
6851 | |
6852 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | |
6853 | ||
8fc897b0 | 6854 | if (hw->phy_type != e1000_phy_igp) |
1da177e4 LT |
6855 | return E1000_SUCCESS; |
6856 | ||
8fc897b0 | 6857 | if (link_up) { |
1da177e4 | 6858 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
8fc897b0 | 6859 | if (ret_val) { |
1da177e4 LT |
6860 | DEBUGOUT("Error getting link speed and duplex\n"); |
6861 | return ret_val; | |
6862 | } | |
6863 | ||
8fc897b0 | 6864 | if (speed == SPEED_1000) { |
1da177e4 | 6865 | |
cd94dd0b AK |
6866 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
6867 | if (ret_val) | |
6868 | return ret_val; | |
1da177e4 | 6869 | |
8fc897b0 | 6870 | if ((hw->dsp_config_state == e1000_dsp_config_enabled) && |
1da177e4 LT |
6871 | min_length >= e1000_igp_cable_length_50) { |
6872 | ||
8fc897b0 | 6873 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 LT |
6874 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
6875 | &phy_data); | |
8fc897b0 | 6876 | if (ret_val) |
1da177e4 LT |
6877 | return ret_val; |
6878 | ||
6879 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
6880 | ||
6881 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], | |
6882 | phy_data); | |
8fc897b0 | 6883 | if (ret_val) |
1da177e4 LT |
6884 | return ret_val; |
6885 | } | |
6886 | hw->dsp_config_state = e1000_dsp_config_activated; | |
6887 | } | |
6888 | ||
8fc897b0 | 6889 | if ((hw->ffe_config_state == e1000_ffe_config_enabled) && |
1da177e4 LT |
6890 | (min_length < e1000_igp_cable_length_50)) { |
6891 | ||
406874a7 JP |
6892 | u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
6893 | u32 idle_errs = 0; | |
1da177e4 LT |
6894 | |
6895 | /* clear previous idle error counts */ | |
6896 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
6897 | &phy_data); | |
8fc897b0 | 6898 | if (ret_val) |
1da177e4 LT |
6899 | return ret_val; |
6900 | ||
8fc897b0 | 6901 | for (i = 0; i < ffe_idle_err_timeout; i++) { |
1da177e4 LT |
6902 | udelay(1000); |
6903 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
6904 | &phy_data); | |
8fc897b0 | 6905 | if (ret_val) |
1da177e4 LT |
6906 | return ret_val; |
6907 | ||
6908 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); | |
8fc897b0 | 6909 | if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
1da177e4 LT |
6910 | hw->ffe_config_state = e1000_ffe_config_active; |
6911 | ||
6912 | ret_val = e1000_write_phy_reg(hw, | |
6913 | IGP01E1000_PHY_DSP_FFE, | |
6914 | IGP01E1000_PHY_DSP_FFE_CM_CP); | |
8fc897b0 | 6915 | if (ret_val) |
1da177e4 LT |
6916 | return ret_val; |
6917 | break; | |
6918 | } | |
6919 | ||
8fc897b0 | 6920 | if (idle_errs) |
1da177e4 LT |
6921 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
6922 | } | |
6923 | } | |
6924 | } | |
6925 | } else { | |
8fc897b0 | 6926 | if (hw->dsp_config_state == e1000_dsp_config_activated) { |
1da177e4 LT |
6927 | /* Save off the current value of register 0x2F5B to be restored at |
6928 | * the end of the routines. */ | |
6929 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
6930 | ||
8fc897b0 | 6931 | if (ret_val) |
1da177e4 LT |
6932 | return ret_val; |
6933 | ||
6934 | /* Disable the PHY transmitter */ | |
6935 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
6936 | ||
8fc897b0 | 6937 | if (ret_val) |
1da177e4 LT |
6938 | return ret_val; |
6939 | ||
f8ec4733 | 6940 | mdelay(20); |
1da177e4 LT |
6941 | |
6942 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6943 | IGP01E1000_IEEE_FORCE_GIGA); | |
8fc897b0 | 6944 | if (ret_val) |
1da177e4 | 6945 | return ret_val; |
8fc897b0 | 6946 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
1da177e4 | 6947 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
8fc897b0 | 6948 | if (ret_val) |
1da177e4 LT |
6949 | return ret_val; |
6950 | ||
6951 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
6952 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | |
6953 | ||
6954 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); | |
8fc897b0 | 6955 | if (ret_val) |
1da177e4 LT |
6956 | return ret_val; |
6957 | } | |
6958 | ||
6959 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6960 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
8fc897b0 | 6961 | if (ret_val) |
1da177e4 LT |
6962 | return ret_val; |
6963 | ||
f8ec4733 | 6964 | mdelay(20); |
1da177e4 LT |
6965 | |
6966 | /* Now enable the transmitter */ | |
6967 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
6968 | ||
8fc897b0 | 6969 | if (ret_val) |
1da177e4 LT |
6970 | return ret_val; |
6971 | ||
6972 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
6973 | } | |
6974 | ||
8fc897b0 | 6975 | if (hw->ffe_config_state == e1000_ffe_config_active) { |
1da177e4 LT |
6976 | /* Save off the current value of register 0x2F5B to be restored at |
6977 | * the end of the routines. */ | |
6978 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
6979 | ||
8fc897b0 | 6980 | if (ret_val) |
1da177e4 LT |
6981 | return ret_val; |
6982 | ||
6983 | /* Disable the PHY transmitter */ | |
6984 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
6985 | ||
8fc897b0 | 6986 | if (ret_val) |
1da177e4 LT |
6987 | return ret_val; |
6988 | ||
f8ec4733 | 6989 | mdelay(20); |
1da177e4 LT |
6990 | |
6991 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6992 | IGP01E1000_IEEE_FORCE_GIGA); | |
8fc897b0 | 6993 | if (ret_val) |
1da177e4 LT |
6994 | return ret_val; |
6995 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | |
6996 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | |
8fc897b0 | 6997 | if (ret_val) |
1da177e4 LT |
6998 | return ret_val; |
6999 | ||
7000 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
7001 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
8fc897b0 | 7002 | if (ret_val) |
1da177e4 LT |
7003 | return ret_val; |
7004 | ||
f8ec4733 | 7005 | mdelay(20); |
1da177e4 LT |
7006 | |
7007 | /* Now enable the transmitter */ | |
7008 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
7009 | ||
8fc897b0 | 7010 | if (ret_val) |
1da177e4 LT |
7011 | return ret_val; |
7012 | ||
7013 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
7014 | } | |
7015 | } | |
7016 | return E1000_SUCCESS; | |
7017 | } | |
7018 | ||
7019 | /***************************************************************************** | |
7020 | * Set PHY to class A mode | |
7021 | * Assumes the following operations will follow to enable the new class mode. | |
7022 | * 1. Do a PHY soft reset | |
7023 | * 2. Restart auto-negotiation or force link. | |
7024 | * | |
7025 | * hw - Struct containing variables accessed by shared code | |
7026 | ****************************************************************************/ | |
64798845 | 7027 | static s32 e1000_set_phy_mode(struct e1000_hw *hw) |
1da177e4 | 7028 | { |
406874a7 JP |
7029 | s32 ret_val; |
7030 | u16 eeprom_data; | |
1da177e4 LT |
7031 | |
7032 | DEBUGFUNC("e1000_set_phy_mode"); | |
7033 | ||
8fc897b0 AK |
7034 | if ((hw->mac_type == e1000_82545_rev_3) && |
7035 | (hw->media_type == e1000_media_type_copper)) { | |
1da177e4 | 7036 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
8fc897b0 | 7037 | if (ret_val) { |
1da177e4 LT |
7038 | return ret_val; |
7039 | } | |
7040 | ||
8fc897b0 AK |
7041 | if ((eeprom_data != EEPROM_RESERVED_WORD) && |
7042 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
1da177e4 | 7043 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
8fc897b0 | 7044 | if (ret_val) |
1da177e4 LT |
7045 | return ret_val; |
7046 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); | |
8fc897b0 | 7047 | if (ret_val) |
1da177e4 LT |
7048 | return ret_val; |
7049 | ||
c3033b01 | 7050 | hw->phy_reset_disable = false; |
1da177e4 LT |
7051 | } |
7052 | } | |
7053 | ||
7054 | return E1000_SUCCESS; | |
7055 | } | |
7056 | ||
7057 | /***************************************************************************** | |
7058 | * | |
7059 | * This function sets the lplu state according to the active flag. When | |
7060 | * activating lplu this function also disables smart speed and vise versa. | |
7061 | * lplu will not be activated unless the device autonegotiation advertisment | |
7062 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
7063 | * hw: Struct containing variables accessed by shared code | |
7064 | * active - true to enable lplu false to disable lplu. | |
7065 | * | |
7066 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
7067 | * E1000_SUCCESS at any other case. | |
7068 | * | |
7069 | ****************************************************************************/ | |
7070 | ||
64798845 | 7071 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
1da177e4 | 7072 | { |
406874a7 JP |
7073 | u32 phy_ctrl = 0; |
7074 | s32 ret_val; | |
7075 | u16 phy_data; | |
1da177e4 LT |
7076 | DEBUGFUNC("e1000_set_d3_lplu_state"); |
7077 | ||
cd94dd0b AK |
7078 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
7079 | && hw->phy_type != e1000_phy_igp_3) | |
1da177e4 LT |
7080 | return E1000_SUCCESS; |
7081 | ||
7082 | /* During driver activity LPLU should not be used or it will attain link | |
7083 | * from the lowest speeds starting from 10Mbps. The capability is used for | |
7084 | * Dx transitions and states */ | |
cd94dd0b | 7085 | if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
2d7edb92 | 7086 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
cd94dd0b | 7087 | if (ret_val) |
2d7edb92 | 7088 | return ret_val; |
cd94dd0b AK |
7089 | } else if (hw->mac_type == e1000_ich8lan) { |
7090 | /* MAC writes into PHY register based on the state transition | |
7091 | * and start auto-negotiation. SW driver can overwrite the settings | |
7092 | * in CSR PHY power control E1000_PHY_CTRL register. */ | |
1dc32918 | 7093 | phy_ctrl = er32(PHY_CTRL); |
2d7edb92 MC |
7094 | } else { |
7095 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
8fc897b0 | 7096 | if (ret_val) |
1da177e4 | 7097 | return ret_val; |
2d7edb92 MC |
7098 | } |
7099 | ||
8fc897b0 AK |
7100 | if (!active) { |
7101 | if (hw->mac_type == e1000_82541_rev_2 || | |
7102 | hw->mac_type == e1000_82547_rev_2) { | |
2d7edb92 MC |
7103 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
7104 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
8fc897b0 | 7105 | if (ret_val) |
2d7edb92 MC |
7106 | return ret_val; |
7107 | } else { | |
cd94dd0b AK |
7108 | if (hw->mac_type == e1000_ich8lan) { |
7109 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
1dc32918 | 7110 | ew32(PHY_CTRL, phy_ctrl); |
cd94dd0b | 7111 | } else { |
2d7edb92 MC |
7112 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
7113 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
7114 | phy_data); | |
7115 | if (ret_val) | |
7116 | return ret_val; | |
cd94dd0b | 7117 | } |
2d7edb92 | 7118 | } |
1da177e4 LT |
7119 | |
7120 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
7121 | * Dx states where the power conservation is most important. During | |
7122 | * driver activity we should enable SmartSpeed, so performance is | |
7123 | * maintained. */ | |
7124 | if (hw->smart_speed == e1000_smart_speed_on) { | |
7125 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7126 | &phy_data); | |
8fc897b0 | 7127 | if (ret_val) |
1da177e4 LT |
7128 | return ret_val; |
7129 | ||
7130 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
7131 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7132 | phy_data); | |
8fc897b0 | 7133 | if (ret_val) |
1da177e4 LT |
7134 | return ret_val; |
7135 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
7136 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7137 | &phy_data); | |
35574764 | 7138 | if (ret_val) |
1da177e4 LT |
7139 | return ret_val; |
7140 | ||
7141 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7142 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7143 | phy_data); | |
8fc897b0 | 7144 | if (ret_val) |
1da177e4 LT |
7145 | return ret_val; |
7146 | } | |
7147 | ||
8fc897b0 AK |
7148 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
7149 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | |
7150 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
1da177e4 | 7151 | |
8fc897b0 | 7152 | if (hw->mac_type == e1000_82541_rev_2 || |
cd94dd0b | 7153 | hw->mac_type == e1000_82547_rev_2) { |
2d7edb92 MC |
7154 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
7155 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
8fc897b0 | 7156 | if (ret_val) |
2d7edb92 MC |
7157 | return ret_val; |
7158 | } else { | |
cd94dd0b AK |
7159 | if (hw->mac_type == e1000_ich8lan) { |
7160 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
1dc32918 | 7161 | ew32(PHY_CTRL, phy_ctrl); |
cd94dd0b | 7162 | } else { |
2d7edb92 MC |
7163 | phy_data |= IGP02E1000_PM_D3_LPLU; |
7164 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
7165 | phy_data); | |
7166 | if (ret_val) | |
7167 | return ret_val; | |
cd94dd0b | 7168 | } |
2d7edb92 MC |
7169 | } |
7170 | ||
7171 | /* When LPLU is enabled we should disable SmartSpeed */ | |
7172 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
8fc897b0 | 7173 | if (ret_val) |
2d7edb92 MC |
7174 | return ret_val; |
7175 | ||
7176 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7177 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
8fc897b0 | 7178 | if (ret_val) |
2d7edb92 MC |
7179 | return ret_val; |
7180 | ||
7181 | } | |
7182 | return E1000_SUCCESS; | |
7183 | } | |
7184 | ||
7185 | /***************************************************************************** | |
7186 | * | |
7187 | * This function sets the lplu d0 state according to the active flag. When | |
7188 | * activating lplu this function also disables smart speed and vise versa. | |
7189 | * lplu will not be activated unless the device autonegotiation advertisment | |
7190 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
7191 | * hw: Struct containing variables accessed by shared code | |
7192 | * active - true to enable lplu false to disable lplu. | |
7193 | * | |
7194 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
7195 | * E1000_SUCCESS at any other case. | |
7196 | * | |
7197 | ****************************************************************************/ | |
7198 | ||
64798845 | 7199 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
2d7edb92 | 7200 | { |
406874a7 JP |
7201 | u32 phy_ctrl = 0; |
7202 | s32 ret_val; | |
7203 | u16 phy_data; | |
2d7edb92 MC |
7204 | DEBUGFUNC("e1000_set_d0_lplu_state"); |
7205 | ||
8fc897b0 | 7206 | if (hw->mac_type <= e1000_82547_rev_2) |
2d7edb92 MC |
7207 | return E1000_SUCCESS; |
7208 | ||
cd94dd0b | 7209 | if (hw->mac_type == e1000_ich8lan) { |
1dc32918 | 7210 | phy_ctrl = er32(PHY_CTRL); |
cd94dd0b | 7211 | } else { |
2d7edb92 | 7212 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
8fc897b0 | 7213 | if (ret_val) |
1da177e4 | 7214 | return ret_val; |
cd94dd0b | 7215 | } |
1da177e4 | 7216 | |
2d7edb92 | 7217 | if (!active) { |
cd94dd0b AK |
7218 | if (hw->mac_type == e1000_ich8lan) { |
7219 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
1dc32918 | 7220 | ew32(PHY_CTRL, phy_ctrl); |
cd94dd0b | 7221 | } else { |
2d7edb92 MC |
7222 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
7223 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
7224 | if (ret_val) | |
7225 | return ret_val; | |
cd94dd0b | 7226 | } |
2d7edb92 MC |
7227 | |
7228 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
7229 | * Dx states where the power conservation is most important. During | |
7230 | * driver activity we should enable SmartSpeed, so performance is | |
7231 | * maintained. */ | |
7232 | if (hw->smart_speed == e1000_smart_speed_on) { | |
7233 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7234 | &phy_data); | |
8fc897b0 | 7235 | if (ret_val) |
2d7edb92 MC |
7236 | return ret_val; |
7237 | ||
7238 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
7239 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7240 | phy_data); | |
8fc897b0 | 7241 | if (ret_val) |
2d7edb92 MC |
7242 | return ret_val; |
7243 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
7244 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7245 | &phy_data); | |
35574764 | 7246 | if (ret_val) |
2d7edb92 MC |
7247 | return ret_val; |
7248 | ||
7249 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7250 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
7251 | phy_data); | |
8fc897b0 | 7252 | if (ret_val) |
2d7edb92 MC |
7253 | return ret_val; |
7254 | } | |
7255 | ||
7256 | ||
7257 | } else { | |
76c224bc | 7258 | |
cd94dd0b AK |
7259 | if (hw->mac_type == e1000_ich8lan) { |
7260 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
1dc32918 | 7261 | ew32(PHY_CTRL, phy_ctrl); |
cd94dd0b | 7262 | } else { |
76c224bc | 7263 | phy_data |= IGP02E1000_PM_D0_LPLU; |
2d7edb92 MC |
7264 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
7265 | if (ret_val) | |
7266 | return ret_val; | |
cd94dd0b | 7267 | } |
2d7edb92 | 7268 | |
1da177e4 LT |
7269 | /* When LPLU is enabled we should disable SmartSpeed */ |
7270 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
8fc897b0 | 7271 | if (ret_val) |
1da177e4 LT |
7272 | return ret_val; |
7273 | ||
7274 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
7275 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
8fc897b0 | 7276 | if (ret_val) |
1da177e4 LT |
7277 | return ret_val; |
7278 | ||
7279 | } | |
7280 | return E1000_SUCCESS; | |
7281 | } | |
7282 | ||
7283 | /****************************************************************************** | |
7284 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. | |
7285 | * | |
7286 | * hw - Struct containing variables accessed by shared code | |
7287 | *****************************************************************************/ | |
64798845 | 7288 | static s32 e1000_set_vco_speed(struct e1000_hw *hw) |
1da177e4 | 7289 | { |
406874a7 JP |
7290 | s32 ret_val; |
7291 | u16 default_page = 0; | |
7292 | u16 phy_data; | |
1da177e4 LT |
7293 | |
7294 | DEBUGFUNC("e1000_set_vco_speed"); | |
7295 | ||
8fc897b0 | 7296 | switch (hw->mac_type) { |
1da177e4 LT |
7297 | case e1000_82545_rev_3: |
7298 | case e1000_82546_rev_3: | |
7299 | break; | |
7300 | default: | |
7301 | return E1000_SUCCESS; | |
7302 | } | |
7303 | ||
7304 | /* Set PHY register 30, page 5, bit 8 to 0 */ | |
7305 | ||
7306 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); | |
8fc897b0 | 7307 | if (ret_val) |
1da177e4 LT |
7308 | return ret_val; |
7309 | ||
7310 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); | |
8fc897b0 | 7311 | if (ret_val) |
1da177e4 LT |
7312 | return ret_val; |
7313 | ||
7314 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
8fc897b0 | 7315 | if (ret_val) |
1da177e4 LT |
7316 | return ret_val; |
7317 | ||
7318 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | |
7319 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
8fc897b0 | 7320 | if (ret_val) |
1da177e4 LT |
7321 | return ret_val; |
7322 | ||
7323 | /* Set PHY register 30, page 4, bit 11 to 1 */ | |
7324 | ||
7325 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | |
8fc897b0 | 7326 | if (ret_val) |
1da177e4 LT |
7327 | return ret_val; |
7328 | ||
7329 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
8fc897b0 | 7330 | if (ret_val) |
1da177e4 LT |
7331 | return ret_val; |
7332 | ||
7333 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; | |
7334 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
8fc897b0 | 7335 | if (ret_val) |
1da177e4 LT |
7336 | return ret_val; |
7337 | ||
7338 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); | |
8fc897b0 | 7339 | if (ret_val) |
1da177e4 LT |
7340 | return ret_val; |
7341 | ||
7342 | return E1000_SUCCESS; | |
7343 | } | |
7344 | ||
1da177e4 | 7345 | |
2d7edb92 MC |
7346 | /***************************************************************************** |
7347 | * This function reads the cookie from ARC ram. | |
7348 | * | |
7349 | * returns: - E1000_SUCCESS . | |
7350 | ****************************************************************************/ | |
64798845 | 7351 | static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer) |
2d7edb92 | 7352 | { |
406874a7 JP |
7353 | u8 i; |
7354 | u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; | |
7355 | u8 length = E1000_MNG_DHCP_COOKIE_LENGTH; | |
1da177e4 | 7356 | |
2d7edb92 MC |
7357 | length = (length >> 2); |
7358 | offset = (offset >> 2); | |
1da177e4 | 7359 | |
2d7edb92 | 7360 | for (i = 0; i < length; i++) { |
e982f17c | 7361 | *((u32 *)buffer + i) = |
2d7edb92 MC |
7362 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
7363 | } | |
7364 | return E1000_SUCCESS; | |
7365 | } | |
7366 | ||
7367 | ||
7368 | /***************************************************************************** | |
7369 | * This function checks whether the HOST IF is enabled for command operaton | |
7370 | * and also checks whether the previous command is completed. | |
7371 | * It busy waits in case of previous command is not completed. | |
7372 | * | |
76c224bc | 7373 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
2d7edb92 MC |
7374 | * timeout |
7375 | * - E1000_SUCCESS for success. | |
7376 | ****************************************************************************/ | |
64798845 | 7377 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) |
2d7edb92 | 7378 | { |
406874a7 JP |
7379 | u32 hicr; |
7380 | u8 i; | |
2d7edb92 MC |
7381 | |
7382 | /* Check that the host interface is enabled. */ | |
1dc32918 | 7383 | hicr = er32(HICR); |
2d7edb92 MC |
7384 | if ((hicr & E1000_HICR_EN) == 0) { |
7385 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | |
7386 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
7387 | } | |
7388 | /* check the previous command is completed */ | |
7389 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | |
1dc32918 | 7390 | hicr = er32(HICR); |
2d7edb92 MC |
7391 | if (!(hicr & E1000_HICR_C)) |
7392 | break; | |
f8ec4733 | 7393 | mdelay(1); |
2d7edb92 MC |
7394 | } |
7395 | ||
76c224bc | 7396 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
2d7edb92 MC |
7397 | DEBUGOUT("Previous command timeout failed .\n"); |
7398 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
7399 | } | |
7400 | return E1000_SUCCESS; | |
7401 | } | |
7402 | ||
7403 | /***************************************************************************** | |
7404 | * This function writes the buffer content at the offset given on the host if. | |
7405 | * It also does alignment considerations to do the writes in most efficient way. | |
7406 | * Also fills up the sum of the buffer in *buffer parameter. | |
7407 | * | |
7408 | * returns - E1000_SUCCESS for success. | |
7409 | ****************************************************************************/ | |
64798845 JP |
7410 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, |
7411 | u16 offset, u8 *sum) | |
2d7edb92 | 7412 | { |
406874a7 JP |
7413 | u8 *tmp; |
7414 | u8 *bufptr = buffer; | |
7415 | u32 data = 0; | |
7416 | u16 remaining, i, j, prev_bytes; | |
2d7edb92 MC |
7417 | |
7418 | /* sum = only sum of the data and it is not checksum */ | |
7419 | ||
7420 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | |
7421 | return -E1000_ERR_PARAM; | |
7422 | } | |
7423 | ||
406874a7 | 7424 | tmp = (u8 *)&data; |
2d7edb92 MC |
7425 | prev_bytes = offset & 0x3; |
7426 | offset &= 0xFFFC; | |
7427 | offset >>= 2; | |
7428 | ||
7429 | if (prev_bytes) { | |
7430 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | |
406874a7 | 7431 | for (j = prev_bytes; j < sizeof(u32); j++) { |
2d7edb92 MC |
7432 | *(tmp + j) = *bufptr++; |
7433 | *sum += *(tmp + j); | |
7434 | } | |
7435 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | |
7436 | length -= j - prev_bytes; | |
7437 | offset++; | |
7438 | } | |
7439 | ||
7440 | remaining = length & 0x3; | |
7441 | length -= remaining; | |
7442 | ||
7443 | /* Calculate length in DWORDs */ | |
7444 | length >>= 2; | |
7445 | ||
7446 | /* The device driver writes the relevant command block into the | |
7447 | * ram area. */ | |
7448 | for (i = 0; i < length; i++) { | |
406874a7 | 7449 | for (j = 0; j < sizeof(u32); j++) { |
2d7edb92 MC |
7450 | *(tmp + j) = *bufptr++; |
7451 | *sum += *(tmp + j); | |
7452 | } | |
7453 | ||
7454 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
7455 | } | |
7456 | if (remaining) { | |
406874a7 | 7457 | for (j = 0; j < sizeof(u32); j++) { |
2d7edb92 MC |
7458 | if (j < remaining) |
7459 | *(tmp + j) = *bufptr++; | |
7460 | else | |
7461 | *(tmp + j) = 0; | |
7462 | ||
7463 | *sum += *(tmp + j); | |
7464 | } | |
7465 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
7466 | } | |
7467 | ||
7468 | return E1000_SUCCESS; | |
7469 | } | |
7470 | ||
7471 | ||
7472 | /***************************************************************************** | |
7473 | * This function writes the command header after does the checksum calculation. | |
7474 | * | |
7475 | * returns - E1000_SUCCESS for success. | |
7476 | ****************************************************************************/ | |
64798845 JP |
7477 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, |
7478 | struct e1000_host_mng_command_header *hdr) | |
2d7edb92 | 7479 | { |
406874a7 JP |
7480 | u16 i; |
7481 | u8 sum; | |
7482 | u8 *buffer; | |
2d7edb92 MC |
7483 | |
7484 | /* Write the whole command header structure which includes sum of | |
7485 | * the buffer */ | |
7486 | ||
406874a7 | 7487 | u16 length = sizeof(struct e1000_host_mng_command_header); |
2d7edb92 MC |
7488 | |
7489 | sum = hdr->checksum; | |
7490 | hdr->checksum = 0; | |
7491 | ||
e982f17c | 7492 | buffer = (u8 *)hdr; |
2d7edb92 | 7493 | i = length; |
8fc897b0 | 7494 | while (i--) |
2d7edb92 MC |
7495 | sum += buffer[i]; |
7496 | ||
7497 | hdr->checksum = 0 - sum; | |
7498 | ||
7499 | length >>= 2; | |
7500 | /* The device driver writes the relevant command block into the ram area. */ | |
4ca213a6 | 7501 | for (i = 0; i < length; i++) { |
e982f17c | 7502 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i)); |
1dc32918 | 7503 | E1000_WRITE_FLUSH(); |
4ca213a6 | 7504 | } |
2d7edb92 MC |
7505 | |
7506 | return E1000_SUCCESS; | |
7507 | } | |
7508 | ||
7509 | ||
7510 | /***************************************************************************** | |
7511 | * This function indicates to ARC that a new command is pending which completes | |
7512 | * one write operation by the driver. | |
7513 | * | |
7514 | * returns - E1000_SUCCESS for success. | |
7515 | ****************************************************************************/ | |
64798845 | 7516 | static s32 e1000_mng_write_commit(struct e1000_hw *hw) |
2d7edb92 | 7517 | { |
406874a7 | 7518 | u32 hicr; |
2d7edb92 | 7519 | |
1dc32918 | 7520 | hicr = er32(HICR); |
2d7edb92 | 7521 | /* Setting this bit tells the ARC that a new command is pending. */ |
1dc32918 | 7522 | ew32(HICR, hicr | E1000_HICR_C); |
2d7edb92 MC |
7523 | |
7524 | return E1000_SUCCESS; | |
7525 | } | |
7526 | ||
7527 | ||
7528 | /***************************************************************************** | |
7529 | * This function checks the mode of the firmware. | |
7530 | * | |
c3033b01 | 7531 | * returns - true when the mode is IAMT or false. |
2d7edb92 | 7532 | ****************************************************************************/ |
64798845 | 7533 | bool e1000_check_mng_mode(struct e1000_hw *hw) |
2d7edb92 | 7534 | { |
406874a7 | 7535 | u32 fwsm; |
2d7edb92 | 7536 | |
1dc32918 | 7537 | fwsm = er32(FWSM); |
2d7edb92 | 7538 | |
cd94dd0b AK |
7539 | if (hw->mac_type == e1000_ich8lan) { |
7540 | if ((fwsm & E1000_FWSM_MODE_MASK) == | |
7541 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
c3033b01 | 7542 | return true; |
cd94dd0b AK |
7543 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
7544 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
c3033b01 | 7545 | return true; |
2d7edb92 | 7546 | |
c3033b01 | 7547 | return false; |
2d7edb92 MC |
7548 | } |
7549 | ||
7550 | ||
7551 | /***************************************************************************** | |
7552 | * This function writes the dhcp info . | |
7553 | ****************************************************************************/ | |
64798845 | 7554 | s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) |
2d7edb92 | 7555 | { |
406874a7 | 7556 | s32 ret_val; |
2d7edb92 MC |
7557 | struct e1000_host_mng_command_header hdr; |
7558 | ||
7559 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | |
7560 | hdr.command_length = length; | |
7561 | hdr.reserved1 = 0; | |
7562 | hdr.reserved2 = 0; | |
7563 | hdr.checksum = 0; | |
7564 | ||
7565 | ret_val = e1000_mng_enable_host_if(hw); | |
7566 | if (ret_val == E1000_SUCCESS) { | |
7567 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | |
7568 | &(hdr.checksum)); | |
7569 | if (ret_val == E1000_SUCCESS) { | |
7570 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | |
7571 | if (ret_val == E1000_SUCCESS) | |
7572 | ret_val = e1000_mng_write_commit(hw); | |
7573 | } | |
7574 | } | |
7575 | return ret_val; | |
7576 | } | |
7577 | ||
7578 | ||
7579 | /***************************************************************************** | |
7580 | * This function calculates the checksum. | |
7581 | * | |
7582 | * returns - checksum of buffer contents. | |
7583 | ****************************************************************************/ | |
64798845 | 7584 | static u8 e1000_calculate_mng_checksum(char *buffer, u32 length) |
2d7edb92 | 7585 | { |
406874a7 JP |
7586 | u8 sum = 0; |
7587 | u32 i; | |
2d7edb92 MC |
7588 | |
7589 | if (!buffer) | |
7590 | return 0; | |
7591 | ||
7592 | for (i=0; i < length; i++) | |
7593 | sum += buffer[i]; | |
7594 | ||
e982f17c | 7595 | return (u8)(0 - sum); |
2d7edb92 MC |
7596 | } |
7597 | ||
7598 | /***************************************************************************** | |
7599 | * This function checks whether tx pkt filtering needs to be enabled or not. | |
7600 | * | |
c3033b01 | 7601 | * returns - true for packet filtering or false. |
2d7edb92 | 7602 | ****************************************************************************/ |
64798845 | 7603 | bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) |
2d7edb92 MC |
7604 | { |
7605 | /* called in init as well as watchdog timer functions */ | |
7606 | ||
406874a7 | 7607 | s32 ret_val, checksum; |
c3033b01 | 7608 | bool tx_filter = false; |
2d7edb92 | 7609 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
406874a7 | 7610 | u8 *buffer = (u8 *) &(hw->mng_cookie); |
2d7edb92 MC |
7611 | |
7612 | if (e1000_check_mng_mode(hw)) { | |
7613 | ret_val = e1000_mng_enable_host_if(hw); | |
7614 | if (ret_val == E1000_SUCCESS) { | |
7615 | ret_val = e1000_host_if_read_cookie(hw, buffer); | |
7616 | if (ret_val == E1000_SUCCESS) { | |
7617 | checksum = hdr->checksum; | |
7618 | hdr->checksum = 0; | |
7619 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | |
7620 | checksum == e1000_calculate_mng_checksum((char *)buffer, | |
7621 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | |
7622 | if (hdr->status & | |
7623 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | |
c3033b01 | 7624 | tx_filter = true; |
2d7edb92 | 7625 | } else |
c3033b01 | 7626 | tx_filter = true; |
2d7edb92 | 7627 | } else |
c3033b01 | 7628 | tx_filter = true; |
2d7edb92 MC |
7629 | } |
7630 | } | |
7631 | ||
7632 | hw->tx_pkt_filtering = tx_filter; | |
7633 | return tx_filter; | |
7634 | } | |
7635 | ||
7636 | /****************************************************************************** | |
7637 | * Verifies the hardware needs to allow ARPs to be processed by the host | |
7638 | * | |
7639 | * hw - Struct containing variables accessed by shared code | |
7640 | * | |
c3033b01 | 7641 | * returns: - true/false |
2d7edb92 MC |
7642 | * |
7643 | *****************************************************************************/ | |
64798845 | 7644 | u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
2d7edb92 | 7645 | { |
406874a7 JP |
7646 | u32 manc; |
7647 | u32 fwsm, factps; | |
2d7edb92 MC |
7648 | |
7649 | if (hw->asf_firmware_present) { | |
1dc32918 | 7650 | manc = er32(MANC); |
2d7edb92 MC |
7651 | |
7652 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | |
7653 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | |
c3033b01 JP |
7654 | return false; |
7655 | if (e1000_arc_subsystem_valid(hw)) { | |
1dc32918 JP |
7656 | fwsm = er32(FWSM); |
7657 | factps = er32(FACTPS); | |
2d7edb92 | 7658 | |
0fccd0e9 JG |
7659 | if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == |
7660 | e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) | |
c3033b01 | 7661 | return true; |
2d7edb92 MC |
7662 | } else |
7663 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | |
c3033b01 | 7664 | return true; |
2d7edb92 | 7665 | } |
c3033b01 | 7666 | return false; |
2d7edb92 MC |
7667 | } |
7668 | ||
64798845 | 7669 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
2d7edb92 | 7670 | { |
406874a7 JP |
7671 | s32 ret_val; |
7672 | u16 mii_status_reg; | |
7673 | u16 i; | |
2d7edb92 MC |
7674 | |
7675 | /* Polarity reversal workaround for forced 10F/10H links. */ | |
7676 | ||
7677 | /* Disable the transmitter on the PHY */ | |
7678 | ||
7679 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
8fc897b0 | 7680 | if (ret_val) |
1da177e4 LT |
7681 | return ret_val; |
7682 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); | |
8fc897b0 | 7683 | if (ret_val) |
1da177e4 LT |
7684 | return ret_val; |
7685 | ||
7686 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
8fc897b0 | 7687 | if (ret_val) |
1da177e4 LT |
7688 | return ret_val; |
7689 | ||
7690 | /* This loop will early-out if the NO link condition has been met. */ | |
8fc897b0 | 7691 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
7692 | /* Read the MII Status Register and wait for Link Status bit |
7693 | * to be clear. | |
7694 | */ | |
7695 | ||
7696 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7697 | if (ret_val) |
1da177e4 LT |
7698 | return ret_val; |
7699 | ||
7700 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7701 | if (ret_val) |
1da177e4 LT |
7702 | return ret_val; |
7703 | ||
8fc897b0 | 7704 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
f8ec4733 | 7705 | mdelay(100); |
1da177e4 LT |
7706 | } |
7707 | ||
7708 | /* Recommended delay time after link has been lost */ | |
f8ec4733 | 7709 | mdelay(1000); |
1da177e4 LT |
7710 | |
7711 | /* Now we will re-enable th transmitter on the PHY */ | |
7712 | ||
7713 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
8fc897b0 | 7714 | if (ret_val) |
1da177e4 | 7715 | return ret_val; |
f8ec4733 | 7716 | mdelay(50); |
1da177e4 | 7717 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
8fc897b0 | 7718 | if (ret_val) |
1da177e4 | 7719 | return ret_val; |
f8ec4733 | 7720 | mdelay(50); |
1da177e4 | 7721 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
8fc897b0 | 7722 | if (ret_val) |
1da177e4 | 7723 | return ret_val; |
f8ec4733 | 7724 | mdelay(50); |
1da177e4 | 7725 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
8fc897b0 | 7726 | if (ret_val) |
1da177e4 LT |
7727 | return ret_val; |
7728 | ||
7729 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
8fc897b0 | 7730 | if (ret_val) |
1da177e4 LT |
7731 | return ret_val; |
7732 | ||
7733 | /* This loop will early-out if the link condition has been met. */ | |
8fc897b0 | 7734 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
1da177e4 LT |
7735 | /* Read the MII Status Register and wait for Link Status bit |
7736 | * to be set. | |
7737 | */ | |
7738 | ||
7739 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7740 | if (ret_val) |
1da177e4 LT |
7741 | return ret_val; |
7742 | ||
7743 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
8fc897b0 | 7744 | if (ret_val) |
1da177e4 LT |
7745 | return ret_val; |
7746 | ||
8fc897b0 | 7747 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
f8ec4733 | 7748 | mdelay(100); |
1da177e4 LT |
7749 | } |
7750 | return E1000_SUCCESS; | |
7751 | } | |
7752 | ||
2d7edb92 MC |
7753 | /*************************************************************************** |
7754 | * | |
7755 | * Disables PCI-Express master access. | |
7756 | * | |
7757 | * hw: Struct containing variables accessed by shared code | |
7758 | * | |
7759 | * returns: - none. | |
7760 | * | |
7761 | ***************************************************************************/ | |
64798845 | 7762 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
2d7edb92 | 7763 | { |
406874a7 | 7764 | u32 ctrl; |
2d7edb92 MC |
7765 | |
7766 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | |
7767 | ||
7768 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7769 | return; | |
7770 | ||
1dc32918 | 7771 | ctrl = er32(CTRL); |
2d7edb92 | 7772 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
1dc32918 | 7773 | ew32(CTRL, ctrl); |
2d7edb92 MC |
7774 | } |
7775 | ||
2d7edb92 MC |
7776 | /******************************************************************************* |
7777 | * | |
7778 | * Disables PCI-Express master access and verifies there are no pending requests | |
7779 | * | |
7780 | * hw: Struct containing variables accessed by shared code | |
7781 | * | |
7782 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | |
7783 | * caused the master requests to be disabled. | |
7784 | * E1000_SUCCESS master requests disabled. | |
7785 | * | |
7786 | ******************************************************************************/ | |
64798845 | 7787 | s32 e1000_disable_pciex_master(struct e1000_hw *hw) |
2d7edb92 | 7788 | { |
406874a7 | 7789 | s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
2d7edb92 MC |
7790 | |
7791 | DEBUGFUNC("e1000_disable_pciex_master"); | |
7792 | ||
7793 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7794 | return E1000_SUCCESS; | |
7795 | ||
7796 | e1000_set_pci_express_master_disable(hw); | |
7797 | ||
8fc897b0 | 7798 | while (timeout) { |
1dc32918 | 7799 | if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
2d7edb92 MC |
7800 | break; |
7801 | else | |
7802 | udelay(100); | |
7803 | timeout--; | |
7804 | } | |
7805 | ||
8fc897b0 | 7806 | if (!timeout) { |
2d7edb92 MC |
7807 | DEBUGOUT("Master requests are pending.\n"); |
7808 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | |
7809 | } | |
7810 | ||
7811 | return E1000_SUCCESS; | |
7812 | } | |
7813 | ||
7814 | /******************************************************************************* | |
7815 | * | |
7816 | * Check for EEPROM Auto Read bit done. | |
7817 | * | |
7818 | * hw: Struct containing variables accessed by shared code | |
7819 | * | |
7820 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
7821 | * E1000_SUCCESS at any other case. | |
7822 | * | |
7823 | ******************************************************************************/ | |
64798845 | 7824 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) |
2d7edb92 | 7825 | { |
406874a7 | 7826 | s32 timeout = AUTO_READ_DONE_TIMEOUT; |
2d7edb92 MC |
7827 | |
7828 | DEBUGFUNC("e1000_get_auto_rd_done"); | |
7829 | ||
7830 | switch (hw->mac_type) { | |
7831 | default: | |
f8ec4733 | 7832 | msleep(5); |
2d7edb92 | 7833 | break; |
868d5309 MC |
7834 | case e1000_82571: |
7835 | case e1000_82572: | |
2d7edb92 | 7836 | case e1000_82573: |
6418ecc6 | 7837 | case e1000_80003es2lan: |
cd94dd0b AK |
7838 | case e1000_ich8lan: |
7839 | while (timeout) { | |
1dc32918 | 7840 | if (er32(EECD) & E1000_EECD_AUTO_RD) |
cd94dd0b | 7841 | break; |
f8ec4733 | 7842 | else msleep(1); |
2d7edb92 MC |
7843 | timeout--; |
7844 | } | |
7845 | ||
8fc897b0 | 7846 | if (!timeout) { |
2d7edb92 MC |
7847 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
7848 | return -E1000_ERR_RESET; | |
7849 | } | |
7850 | break; | |
7851 | } | |
7852 | ||
fd803241 JK |
7853 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
7854 | * Need to wait for PHY configuration completion before accessing NVM | |
7855 | * and PHY. */ | |
7856 | if (hw->mac_type == e1000_82573) | |
f8ec4733 | 7857 | msleep(25); |
fd803241 | 7858 | |
2d7edb92 MC |
7859 | return E1000_SUCCESS; |
7860 | } | |
7861 | ||
7862 | /*************************************************************************** | |
7863 | * Checks if the PHY configuration is done | |
7864 | * | |
7865 | * hw: Struct containing variables accessed by shared code | |
7866 | * | |
7867 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
7868 | * E1000_SUCCESS at any other case. | |
7869 | * | |
7870 | ***************************************************************************/ | |
64798845 | 7871 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
2d7edb92 | 7872 | { |
406874a7 JP |
7873 | s32 timeout = PHY_CFG_TIMEOUT; |
7874 | u32 cfg_mask = E1000_EEPROM_CFG_DONE; | |
868d5309 | 7875 | |
2d7edb92 MC |
7876 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
7877 | ||
868d5309 MC |
7878 | switch (hw->mac_type) { |
7879 | default: | |
f8ec4733 | 7880 | mdelay(10); |
868d5309 | 7881 | break; |
6418ecc6 JK |
7882 | case e1000_80003es2lan: |
7883 | /* Separate *_CFG_DONE_* bit for each port */ | |
1dc32918 | 7884 | if (er32(STATUS) & E1000_STATUS_FUNC_1) |
6418ecc6 JK |
7885 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
7886 | /* Fall Through */ | |
868d5309 MC |
7887 | case e1000_82571: |
7888 | case e1000_82572: | |
7889 | while (timeout) { | |
1dc32918 | 7890 | if (er32(EEMNGCTL) & cfg_mask) |
868d5309 MC |
7891 | break; |
7892 | else | |
f8ec4733 | 7893 | msleep(1); |
868d5309 MC |
7894 | timeout--; |
7895 | } | |
868d5309 MC |
7896 | if (!timeout) { |
7897 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | |
7898 | return -E1000_ERR_RESET; | |
7899 | } | |
7900 | break; | |
7901 | } | |
2d7edb92 MC |
7902 | |
7903 | return E1000_SUCCESS; | |
7904 | } | |
7905 | ||
7906 | /*************************************************************************** | |
7907 | * | |
7908 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
7909 | * adapter or Eeprom access. | |
7910 | * | |
7911 | * hw: Struct containing variables accessed by shared code | |
7912 | * | |
7913 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
7914 | * E1000_SUCCESS at any other case. | |
7915 | * | |
7916 | ***************************************************************************/ | |
64798845 | 7917 | static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
2d7edb92 | 7918 | { |
406874a7 JP |
7919 | s32 timeout; |
7920 | u32 swsm; | |
2d7edb92 MC |
7921 | |
7922 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | |
7923 | ||
8fc897b0 | 7924 | if (!hw->eeprom_semaphore_present) |
2d7edb92 MC |
7925 | return E1000_SUCCESS; |
7926 | ||
6418ecc6 JK |
7927 | if (hw->mac_type == e1000_80003es2lan) { |
7928 | /* Get the SW semaphore. */ | |
7929 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | |
7930 | return -E1000_ERR_EEPROM; | |
7931 | } | |
2d7edb92 MC |
7932 | |
7933 | /* Get the FW semaphore. */ | |
7934 | timeout = hw->eeprom.word_size + 1; | |
8fc897b0 | 7935 | while (timeout) { |
1dc32918 | 7936 | swsm = er32(SWSM); |
2d7edb92 | 7937 | swsm |= E1000_SWSM_SWESMBI; |
1dc32918 | 7938 | ew32(SWSM, swsm); |
2d7edb92 | 7939 | /* if we managed to set the bit we got the semaphore. */ |
1dc32918 | 7940 | swsm = er32(SWSM); |
8fc897b0 | 7941 | if (swsm & E1000_SWSM_SWESMBI) |
2d7edb92 MC |
7942 | break; |
7943 | ||
7944 | udelay(50); | |
7945 | timeout--; | |
7946 | } | |
7947 | ||
8fc897b0 | 7948 | if (!timeout) { |
2d7edb92 MC |
7949 | /* Release semaphores */ |
7950 | e1000_put_hw_eeprom_semaphore(hw); | |
7951 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | |
7952 | return -E1000_ERR_EEPROM; | |
7953 | } | |
7954 | ||
7955 | return E1000_SUCCESS; | |
7956 | } | |
7957 | ||
7958 | /*************************************************************************** | |
7959 | * This function clears HW semaphore bits. | |
7960 | * | |
7961 | * hw: Struct containing variables accessed by shared code | |
7962 | * | |
7963 | * returns: - None. | |
7964 | * | |
7965 | ***************************************************************************/ | |
64798845 | 7966 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
2d7edb92 | 7967 | { |
406874a7 | 7968 | u32 swsm; |
2d7edb92 MC |
7969 | |
7970 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | |
7971 | ||
8fc897b0 | 7972 | if (!hw->eeprom_semaphore_present) |
2d7edb92 MC |
7973 | return; |
7974 | ||
1dc32918 | 7975 | swsm = er32(SWSM); |
6418ecc6 JK |
7976 | if (hw->mac_type == e1000_80003es2lan) { |
7977 | /* Release both semaphores. */ | |
7978 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
7979 | } else | |
868d5309 | 7980 | swsm &= ~(E1000_SWSM_SWESMBI); |
1dc32918 | 7981 | ew32(SWSM, swsm); |
2d7edb92 MC |
7982 | } |
7983 | ||
6418ecc6 JK |
7984 | /*************************************************************************** |
7985 | * | |
7986 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | |
7987 | * | |
7988 | * hw: Struct containing variables accessed by shared code | |
7989 | * | |
7990 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | |
7991 | * E1000_SUCCESS at any other case. | |
7992 | * | |
7993 | ***************************************************************************/ | |
64798845 | 7994 | static s32 e1000_get_software_semaphore(struct e1000_hw *hw) |
6418ecc6 | 7995 | { |
406874a7 JP |
7996 | s32 timeout = hw->eeprom.word_size + 1; |
7997 | u32 swsm; | |
6418ecc6 JK |
7998 | |
7999 | DEBUGFUNC("e1000_get_software_semaphore"); | |
8000 | ||
35574764 | 8001 | if (hw->mac_type != e1000_80003es2lan) { |
6418ecc6 | 8002 | return E1000_SUCCESS; |
35574764 | 8003 | } |
6418ecc6 | 8004 | |
8fc897b0 | 8005 | while (timeout) { |
1dc32918 | 8006 | swsm = er32(SWSM); |
6418ecc6 | 8007 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ |
8fc897b0 | 8008 | if (!(swsm & E1000_SWSM_SMBI)) |
6418ecc6 | 8009 | break; |
f8ec4733 | 8010 | mdelay(1); |
6418ecc6 JK |
8011 | timeout--; |
8012 | } | |
8013 | ||
8fc897b0 | 8014 | if (!timeout) { |
6418ecc6 JK |
8015 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
8016 | return -E1000_ERR_RESET; | |
8017 | } | |
8018 | ||
8019 | return E1000_SUCCESS; | |
8020 | } | |
8021 | ||
8022 | /*************************************************************************** | |
8023 | * | |
8024 | * Release semaphore bit (SMBI). | |
8025 | * | |
8026 | * hw: Struct containing variables accessed by shared code | |
8027 | * | |
8028 | ***************************************************************************/ | |
64798845 | 8029 | static void e1000_release_software_semaphore(struct e1000_hw *hw) |
6418ecc6 | 8030 | { |
406874a7 | 8031 | u32 swsm; |
6418ecc6 JK |
8032 | |
8033 | DEBUGFUNC("e1000_release_software_semaphore"); | |
8034 | ||
35574764 | 8035 | if (hw->mac_type != e1000_80003es2lan) { |
6418ecc6 | 8036 | return; |
35574764 | 8037 | } |
6418ecc6 | 8038 | |
1dc32918 | 8039 | swsm = er32(SWSM); |
6418ecc6 JK |
8040 | /* Release the SW semaphores.*/ |
8041 | swsm &= ~E1000_SWSM_SMBI; | |
1dc32918 | 8042 | ew32(SWSM, swsm); |
6418ecc6 JK |
8043 | } |
8044 | ||
2d7edb92 MC |
8045 | /****************************************************************************** |
8046 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
8047 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
8048 | * the caller to figure out how to deal with it. | |
8049 | * | |
8050 | * hw - Struct containing variables accessed by shared code | |
8051 | * | |
8052 | * returns: - E1000_BLK_PHY_RESET | |
8053 | * E1000_SUCCESS | |
8054 | * | |
8055 | *****************************************************************************/ | |
64798845 | 8056 | s32 e1000_check_phy_reset_block(struct e1000_hw *hw) |
2d7edb92 | 8057 | { |
406874a7 JP |
8058 | u32 manc = 0; |
8059 | u32 fwsm = 0; | |
cd94dd0b AK |
8060 | |
8061 | if (hw->mac_type == e1000_ich8lan) { | |
1dc32918 | 8062 | fwsm = er32(FWSM); |
cd94dd0b AK |
8063 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS |
8064 | : E1000_BLK_PHY_RESET; | |
8065 | } | |
96838a40 JB |
8066 | |
8067 | if (hw->mac_type > e1000_82547_rev_2) | |
1dc32918 | 8068 | manc = er32(MANC); |
2d7edb92 | 8069 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
35574764 | 8070 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
2d7edb92 MC |
8071 | } |
8072 | ||
64798845 | 8073 | static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw) |
2d7edb92 | 8074 | { |
406874a7 | 8075 | u32 fwsm; |
2d7edb92 MC |
8076 | |
8077 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | |
8078 | * may not be provided a DMA clock when no manageability features are | |
8079 | * enabled. We do not want to perform any reads/writes to these registers | |
8080 | * if this is the case. We read FWSM to determine the manageability mode. | |
8081 | */ | |
8082 | switch (hw->mac_type) { | |
868d5309 MC |
8083 | case e1000_82571: |
8084 | case e1000_82572: | |
2d7edb92 | 8085 | case e1000_82573: |
6418ecc6 | 8086 | case e1000_80003es2lan: |
1dc32918 | 8087 | fwsm = er32(FWSM); |
8fc897b0 | 8088 | if ((fwsm & E1000_FWSM_MODE_MASK) != 0) |
c3033b01 | 8089 | return true; |
2d7edb92 | 8090 | break; |
cd94dd0b | 8091 | case e1000_ich8lan: |
c3033b01 | 8092 | return true; |
2d7edb92 MC |
8093 | default: |
8094 | break; | |
8095 | } | |
c3033b01 | 8096 | return false; |
2d7edb92 MC |
8097 | } |
8098 | ||
8099 | ||
d37ea5d5 AK |
8100 | /****************************************************************************** |
8101 | * Configure PCI-Ex no-snoop | |
8102 | * | |
8103 | * hw - Struct containing variables accessed by shared code. | |
8104 | * no_snoop - Bitmap of no-snoop events. | |
8105 | * | |
8106 | * returns: E1000_SUCCESS | |
8107 | * | |
8108 | *****************************************************************************/ | |
64798845 | 8109 | static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop) |
d37ea5d5 | 8110 | { |
406874a7 | 8111 | u32 gcr_reg = 0; |
d37ea5d5 AK |
8112 | |
8113 | DEBUGFUNC("e1000_set_pci_ex_no_snoop"); | |
8114 | ||
8115 | if (hw->bus_type == e1000_bus_type_unknown) | |
8116 | e1000_get_bus_info(hw); | |
8117 | ||
8118 | if (hw->bus_type != e1000_bus_type_pci_express) | |
8119 | return E1000_SUCCESS; | |
8120 | ||
8121 | if (no_snoop) { | |
1dc32918 | 8122 | gcr_reg = er32(GCR); |
d37ea5d5 AK |
8123 | gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); |
8124 | gcr_reg |= no_snoop; | |
1dc32918 | 8125 | ew32(GCR, gcr_reg); |
d37ea5d5 AK |
8126 | } |
8127 | if (hw->mac_type == e1000_ich8lan) { | |
406874a7 | 8128 | u32 ctrl_ext; |
d37ea5d5 | 8129 | |
1dc32918 | 8130 | ew32(GCR, PCI_EX_82566_SNOOP_ALL); |
d37ea5d5 | 8131 | |
1dc32918 | 8132 | ctrl_ext = er32(CTRL_EXT); |
d37ea5d5 | 8133 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
1dc32918 | 8134 | ew32(CTRL_EXT, ctrl_ext); |
d37ea5d5 AK |
8135 | } |
8136 | ||
8137 | return E1000_SUCCESS; | |
8138 | } | |
8139 | ||
8140 | /*************************************************************************** | |
8141 | * | |
8142 | * Get software semaphore FLAG bit (SWFLAG). | |
8143 | * SWFLAG is used to synchronize the access to all shared resource between | |
8144 | * SW, FW and HW. | |
8145 | * | |
8146 | * hw: Struct containing variables accessed by shared code | |
8147 | * | |
8148 | ***************************************************************************/ | |
64798845 | 8149 | static s32 e1000_get_software_flag(struct e1000_hw *hw) |
d37ea5d5 | 8150 | { |
406874a7 JP |
8151 | s32 timeout = PHY_CFG_TIMEOUT; |
8152 | u32 extcnf_ctrl; | |
d37ea5d5 AK |
8153 | |
8154 | DEBUGFUNC("e1000_get_software_flag"); | |
8155 | ||
8156 | if (hw->mac_type == e1000_ich8lan) { | |
8157 | while (timeout) { | |
1dc32918 | 8158 | extcnf_ctrl = er32(EXTCNF_CTRL); |
d37ea5d5 | 8159 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
1dc32918 | 8160 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
d37ea5d5 | 8161 | |
1dc32918 | 8162 | extcnf_ctrl = er32(EXTCNF_CTRL); |
d37ea5d5 AK |
8163 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
8164 | break; | |
f8ec4733 | 8165 | mdelay(1); |
d37ea5d5 AK |
8166 | timeout--; |
8167 | } | |
8168 | ||
8169 | if (!timeout) { | |
8170 | DEBUGOUT("FW or HW locks the resource too long.\n"); | |
8171 | return -E1000_ERR_CONFIG; | |
8172 | } | |
8173 | } | |
8174 | ||
8175 | return E1000_SUCCESS; | |
8176 | } | |
8177 | ||
8178 | /*************************************************************************** | |
8179 | * | |
8180 | * Release software semaphore FLAG bit (SWFLAG). | |
8181 | * SWFLAG is used to synchronize the access to all shared resource between | |
8182 | * SW, FW and HW. | |
8183 | * | |
8184 | * hw: Struct containing variables accessed by shared code | |
8185 | * | |
8186 | ***************************************************************************/ | |
64798845 | 8187 | static void e1000_release_software_flag(struct e1000_hw *hw) |
d37ea5d5 | 8188 | { |
406874a7 | 8189 | u32 extcnf_ctrl; |
d37ea5d5 AK |
8190 | |
8191 | DEBUGFUNC("e1000_release_software_flag"); | |
8192 | ||
8193 | if (hw->mac_type == e1000_ich8lan) { | |
1dc32918 | 8194 | extcnf_ctrl= er32(EXTCNF_CTRL); |
d37ea5d5 | 8195 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
1dc32918 | 8196 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
d37ea5d5 AK |
8197 | } |
8198 | ||
8199 | return; | |
8200 | } | |
8201 | ||
d37ea5d5 AK |
8202 | /****************************************************************************** |
8203 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access | |
8204 | * register. | |
8205 | * | |
8206 | * hw - Struct containing variables accessed by shared code | |
8207 | * offset - offset of word in the EEPROM to read | |
8208 | * data - word read from the EEPROM | |
8209 | * words - number of words to read | |
8210 | *****************************************************************************/ | |
64798845 JP |
8211 | static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, |
8212 | u16 *data) | |
d37ea5d5 | 8213 | { |
406874a7 JP |
8214 | s32 error = E1000_SUCCESS; |
8215 | u32 flash_bank = 0; | |
8216 | u32 act_offset = 0; | |
8217 | u32 bank_offset = 0; | |
8218 | u16 word = 0; | |
8219 | u16 i = 0; | |
d37ea5d5 AK |
8220 | |
8221 | /* We need to know which is the valid flash bank. In the event | |
8222 | * that we didn't allocate eeprom_shadow_ram, we may not be | |
8223 | * managing flash_bank. So it cannot be trusted and needs | |
8224 | * to be updated with each read. | |
8225 | */ | |
8226 | /* Value of bit 22 corresponds to the flash bank we're on. */ | |
1dc32918 | 8227 | flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; |
d37ea5d5 AK |
8228 | |
8229 | /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ | |
8230 | bank_offset = flash_bank * (hw->flash_bank_size * 2); | |
8231 | ||
8232 | error = e1000_get_software_flag(hw); | |
8233 | if (error != E1000_SUCCESS) | |
8234 | return error; | |
8235 | ||
8236 | for (i = 0; i < words; i++) { | |
8237 | if (hw->eeprom_shadow_ram != NULL && | |
c3033b01 | 8238 | hw->eeprom_shadow_ram[offset+i].modified) { |
d37ea5d5 AK |
8239 | data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; |
8240 | } else { | |
8241 | /* The NVM part needs a byte offset, hence * 2 */ | |
8242 | act_offset = bank_offset + ((offset + i) * 2); | |
8243 | error = e1000_read_ich8_word(hw, act_offset, &word); | |
8244 | if (error != E1000_SUCCESS) | |
8245 | break; | |
8246 | data[i] = word; | |
8247 | } | |
8248 | } | |
8249 | ||
8250 | e1000_release_software_flag(hw); | |
8251 | ||
8252 | return error; | |
8253 | } | |
8254 | ||
8255 | /****************************************************************************** | |
8256 | * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access | |
8257 | * register. Actually, writes are written to the shadow ram cache in the hw | |
8258 | * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to | |
8259 | * the NVM, which occurs when the NVM checksum is updated. | |
8260 | * | |
8261 | * hw - Struct containing variables accessed by shared code | |
8262 | * offset - offset of word in the EEPROM to write | |
8263 | * words - number of words to write | |
8264 | * data - words to write to the EEPROM | |
8265 | *****************************************************************************/ | |
64798845 JP |
8266 | static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, |
8267 | u16 *data) | |
d37ea5d5 | 8268 | { |
406874a7 JP |
8269 | u32 i = 0; |
8270 | s32 error = E1000_SUCCESS; | |
d37ea5d5 AK |
8271 | |
8272 | error = e1000_get_software_flag(hw); | |
8273 | if (error != E1000_SUCCESS) | |
8274 | return error; | |
8275 | ||
8276 | /* A driver can write to the NVM only if it has eeprom_shadow_ram | |
8277 | * allocated. Subsequent reads to the modified words are read from | |
8278 | * this cached structure as well. Writes will only go into this | |
8279 | * cached structure unless it's followed by a call to | |
8280 | * e1000_update_eeprom_checksum() where it will commit the changes | |
8281 | * and clear the "modified" field. | |
8282 | */ | |
8283 | if (hw->eeprom_shadow_ram != NULL) { | |
8284 | for (i = 0; i < words; i++) { | |
8285 | if ((offset + i) < E1000_SHADOW_RAM_WORDS) { | |
c3033b01 | 8286 | hw->eeprom_shadow_ram[offset+i].modified = true; |
d37ea5d5 AK |
8287 | hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; |
8288 | } else { | |
8289 | error = -E1000_ERR_EEPROM; | |
8290 | break; | |
8291 | } | |
8292 | } | |
8293 | } else { | |
8294 | /* Drivers have the option to not allocate eeprom_shadow_ram as long | |
8295 | * as they don't perform any NVM writes. An attempt in doing so | |
8296 | * will result in this error. | |
8297 | */ | |
8298 | error = -E1000_ERR_EEPROM; | |
8299 | } | |
8300 | ||
8301 | e1000_release_software_flag(hw); | |
8302 | ||
8303 | return error; | |
8304 | } | |
8305 | ||
8306 | /****************************************************************************** | |
8307 | * This function does initial flash setup so that a new read/write/erase cycle | |
8308 | * can be started. | |
8309 | * | |
8310 | * hw - The pointer to the hw structure | |
8311 | ****************************************************************************/ | |
64798845 | 8312 | static s32 e1000_ich8_cycle_init(struct e1000_hw *hw) |
d37ea5d5 AK |
8313 | { |
8314 | union ich8_hws_flash_status hsfsts; | |
406874a7 JP |
8315 | s32 error = E1000_ERR_EEPROM; |
8316 | s32 i = 0; | |
d37ea5d5 AK |
8317 | |
8318 | DEBUGFUNC("e1000_ich8_cycle_init"); | |
8319 | ||
2df7d59f | 8320 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8321 | |
8322 | /* May be check the Flash Des Valid bit in Hw status */ | |
8323 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
8324 | DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); | |
8325 | return error; | |
8326 | } | |
8327 | ||
8328 | /* Clear FCERR in Hw status by writing 1 */ | |
8329 | /* Clear DAEL in Hw status by writing a 1 */ | |
8330 | hsfsts.hsf_status.flcerr = 1; | |
8331 | hsfsts.hsf_status.dael = 1; | |
8332 | ||
2df7d59f | 8333 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8334 | |
8335 | /* Either we should have a hardware SPI cycle in progress bit to check | |
8336 | * against, in order to start a new cycle or FDONE bit should be changed | |
8337 | * in the hardware so that it is 1 after harware reset, which can then be | |
8338 | * used as an indication whether a cycle is in progress or has been | |
8339 | * completed .. we should also have some software semaphore mechanism to | |
8340 | * guard FDONE or the cycle in progress bit so that two threads access to | |
8341 | * those bits can be sequentiallized or a way so that 2 threads dont | |
8342 | * start the cycle at the same time */ | |
8343 | ||
8344 | if (hsfsts.hsf_status.flcinprog == 0) { | |
8345 | /* There is no cycle running at present, so we can start a cycle */ | |
8346 | /* Begin by setting Flash Cycle Done. */ | |
8347 | hsfsts.hsf_status.flcdone = 1; | |
2df7d59f | 8348 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8349 | error = E1000_SUCCESS; |
8350 | } else { | |
8351 | /* otherwise poll for sometime so the current cycle has a chance | |
8352 | * to end before giving up. */ | |
2df7d59f JK |
8353 | for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { |
8354 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | |
d37ea5d5 AK |
8355 | if (hsfsts.hsf_status.flcinprog == 0) { |
8356 | error = E1000_SUCCESS; | |
8357 | break; | |
8358 | } | |
8359 | udelay(1); | |
8360 | } | |
8361 | if (error == E1000_SUCCESS) { | |
8362 | /* Successful in waiting for previous cycle to timeout, | |
8363 | * now set the Flash Cycle Done. */ | |
8364 | hsfsts.hsf_status.flcdone = 1; | |
2df7d59f | 8365 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
d37ea5d5 AK |
8366 | } else { |
8367 | DEBUGOUT("Flash controller busy, cannot get access"); | |
8368 | } | |
8369 | } | |
8370 | return error; | |
8371 | } | |
8372 | ||
8373 | /****************************************************************************** | |
8374 | * This function starts a flash cycle and waits for its completion | |
8375 | * | |
8376 | * hw - The pointer to the hw structure | |
8377 | ****************************************************************************/ | |
64798845 | 8378 | static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout) |
d37ea5d5 AK |
8379 | { |
8380 | union ich8_hws_flash_ctrl hsflctl; | |
8381 | union ich8_hws_flash_status hsfsts; | |
406874a7 JP |
8382 | s32 error = E1000_ERR_EEPROM; |
8383 | u32 i = 0; | |
d37ea5d5 AK |
8384 | |
8385 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
2df7d59f | 8386 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 | 8387 | hsflctl.hsf_ctrl.flcgo = 1; |
2df7d59f | 8388 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
d37ea5d5 AK |
8389 | |
8390 | /* wait till FDONE bit is set to 1 */ | |
8391 | do { | |
2df7d59f | 8392 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8393 | if (hsfsts.hsf_status.flcdone == 1) |
8394 | break; | |
8395 | udelay(1); | |
8396 | i++; | |
8397 | } while (i < timeout); | |
8398 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { | |
8399 | error = E1000_SUCCESS; | |
8400 | } | |
8401 | return error; | |
8402 | } | |
8403 | ||
8404 | /****************************************************************************** | |
8405 | * Reads a byte or word from the NVM using the ICH8 flash access registers. | |
8406 | * | |
8407 | * hw - The pointer to the hw structure | |
8408 | * index - The index of the byte or word to read. | |
8409 | * size - Size of data to read, 1=byte 2=word | |
8410 | * data - Pointer to the word to store the value read. | |
8411 | *****************************************************************************/ | |
64798845 JP |
8412 | static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, |
8413 | u16 *data) | |
d37ea5d5 AK |
8414 | { |
8415 | union ich8_hws_flash_status hsfsts; | |
8416 | union ich8_hws_flash_ctrl hsflctl; | |
406874a7 JP |
8417 | u32 flash_linear_address; |
8418 | u32 flash_data = 0; | |
8419 | s32 error = -E1000_ERR_EEPROM; | |
8420 | s32 count = 0; | |
d37ea5d5 AK |
8421 | |
8422 | DEBUGFUNC("e1000_read_ich8_data"); | |
8423 | ||
abec42a4 | 8424 | if (size < 1 || size > 2 || data == NULL || |
2df7d59f | 8425 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
d37ea5d5 AK |
8426 | return error; |
8427 | ||
2df7d59f | 8428 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
d37ea5d5 AK |
8429 | hw->flash_base_addr; |
8430 | ||
8431 | do { | |
8432 | udelay(1); | |
8433 | /* Steps */ | |
8434 | error = e1000_ich8_cycle_init(hw); | |
8435 | if (error != E1000_SUCCESS) | |
8436 | break; | |
8437 | ||
2df7d59f | 8438 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 AK |
8439 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
8440 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
2df7d59f JK |
8441 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
8442 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8443 | |
8444 | /* Write the last 24 bits of index into Flash Linear address field in | |
8445 | * Flash Address */ | |
8446 | /* TODO: TBD maybe check the index against the size of flash */ | |
8447 | ||
2df7d59f | 8448 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 | 8449 | |
2df7d59f | 8450 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
d37ea5d5 AK |
8451 | |
8452 | /* Check if FCERR is set to 1, if set to 1, clear it and try the whole | |
8453 | * sequence a few more times, else read in (shift in) the Flash Data0, | |
8454 | * the order is least significant byte first msb to lsb */ | |
8455 | if (error == E1000_SUCCESS) { | |
2df7d59f | 8456 | flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); |
d37ea5d5 | 8457 | if (size == 1) { |
406874a7 | 8458 | *data = (u8)(flash_data & 0x000000FF); |
d37ea5d5 | 8459 | } else if (size == 2) { |
406874a7 | 8460 | *data = (u16)(flash_data & 0x0000FFFF); |
d37ea5d5 AK |
8461 | } |
8462 | break; | |
8463 | } else { | |
8464 | /* If we've gotten here, then things are probably completely hosed, | |
8465 | * but if the error condition is detected, it won't hurt to give | |
2df7d59f | 8466 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
d37ea5d5 | 8467 | */ |
2df7d59f | 8468 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8469 | if (hsfsts.hsf_status.flcerr == 1) { |
8470 | /* Repeat for some time before giving up. */ | |
8471 | continue; | |
8472 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8473 | DEBUGOUT("Timeout error - flash cycle did not complete."); | |
8474 | break; | |
8475 | } | |
8476 | } | |
2df7d59f | 8477 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
d37ea5d5 AK |
8478 | |
8479 | return error; | |
8480 | } | |
8481 | ||
8482 | /****************************************************************************** | |
8483 | * Writes One /two bytes to the NVM using the ICH8 flash access registers. | |
8484 | * | |
8485 | * hw - The pointer to the hw structure | |
8486 | * index - The index of the byte/word to read. | |
8487 | * size - Size of data to read, 1=byte 2=word | |
8488 | * data - The byte(s) to write to the NVM. | |
8489 | *****************************************************************************/ | |
64798845 JP |
8490 | static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, |
8491 | u16 data) | |
d37ea5d5 AK |
8492 | { |
8493 | union ich8_hws_flash_status hsfsts; | |
8494 | union ich8_hws_flash_ctrl hsflctl; | |
406874a7 JP |
8495 | u32 flash_linear_address; |
8496 | u32 flash_data = 0; | |
8497 | s32 error = -E1000_ERR_EEPROM; | |
8498 | s32 count = 0; | |
d37ea5d5 AK |
8499 | |
8500 | DEBUGFUNC("e1000_write_ich8_data"); | |
8501 | ||
8502 | if (size < 1 || size > 2 || data > size * 0xff || | |
2df7d59f | 8503 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
d37ea5d5 AK |
8504 | return error; |
8505 | ||
2df7d59f | 8506 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
d37ea5d5 AK |
8507 | hw->flash_base_addr; |
8508 | ||
8509 | do { | |
8510 | udelay(1); | |
8511 | /* Steps */ | |
8512 | error = e1000_ich8_cycle_init(hw); | |
8513 | if (error != E1000_SUCCESS) | |
8514 | break; | |
8515 | ||
2df7d59f | 8516 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
d37ea5d5 AK |
8517 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
8518 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
2df7d59f JK |
8519 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
8520 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8521 | |
8522 | /* Write the last 24 bits of index into Flash Linear address field in | |
8523 | * Flash Address */ | |
2df7d59f | 8524 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 AK |
8525 | |
8526 | if (size == 1) | |
406874a7 | 8527 | flash_data = (u32)data & 0x00FF; |
d37ea5d5 | 8528 | else |
406874a7 | 8529 | flash_data = (u32)data; |
d37ea5d5 | 8530 | |
2df7d59f | 8531 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); |
d37ea5d5 AK |
8532 | |
8533 | /* check if FCERR is set to 1 , if set to 1, clear it and try the whole | |
8534 | * sequence a few more times else done */ | |
2df7d59f | 8535 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
d37ea5d5 AK |
8536 | if (error == E1000_SUCCESS) { |
8537 | break; | |
8538 | } else { | |
8539 | /* If we're here, then things are most likely completely hosed, | |
8540 | * but if the error condition is detected, it won't hurt to give | |
2df7d59f | 8541 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
d37ea5d5 | 8542 | */ |
2df7d59f | 8543 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8544 | if (hsfsts.hsf_status.flcerr == 1) { |
8545 | /* Repeat for some time before giving up. */ | |
8546 | continue; | |
8547 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8548 | DEBUGOUT("Timeout error - flash cycle did not complete."); | |
8549 | break; | |
8550 | } | |
8551 | } | |
2df7d59f | 8552 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
d37ea5d5 AK |
8553 | |
8554 | return error; | |
8555 | } | |
8556 | ||
8557 | /****************************************************************************** | |
8558 | * Reads a single byte from the NVM using the ICH8 flash access registers. | |
8559 | * | |
8560 | * hw - pointer to e1000_hw structure | |
8561 | * index - The index of the byte to read. | |
8562 | * data - Pointer to a byte to store the value read. | |
8563 | *****************************************************************************/ | |
64798845 | 8564 | static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data) |
d37ea5d5 | 8565 | { |
406874a7 JP |
8566 | s32 status = E1000_SUCCESS; |
8567 | u16 word = 0; | |
d37ea5d5 AK |
8568 | |
8569 | status = e1000_read_ich8_data(hw, index, 1, &word); | |
8570 | if (status == E1000_SUCCESS) { | |
406874a7 | 8571 | *data = (u8)word; |
d37ea5d5 AK |
8572 | } |
8573 | ||
8574 | return status; | |
8575 | } | |
8576 | ||
8577 | /****************************************************************************** | |
8578 | * Writes a single byte to the NVM using the ICH8 flash access registers. | |
8579 | * Performs verification by reading back the value and then going through | |
8580 | * a retry algorithm before giving up. | |
8581 | * | |
8582 | * hw - pointer to e1000_hw structure | |
8583 | * index - The index of the byte to write. | |
8584 | * byte - The byte to write to the NVM. | |
8585 | *****************************************************************************/ | |
64798845 | 8586 | static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte) |
d37ea5d5 | 8587 | { |
406874a7 JP |
8588 | s32 error = E1000_SUCCESS; |
8589 | s32 program_retries = 0; | |
d37ea5d5 | 8590 | |
2a88c173 | 8591 | DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); |
d37ea5d5 | 8592 | |
2a88c173 JK |
8593 | error = e1000_write_ich8_byte(hw, index, byte); |
8594 | ||
8595 | if (error != E1000_SUCCESS) { | |
8596 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
8597 | DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); | |
8598 | error = e1000_write_ich8_byte(hw, index, byte); | |
8599 | udelay(100); | |
8600 | if (error == E1000_SUCCESS) | |
8601 | break; | |
8602 | } | |
d37ea5d5 | 8603 | } |
2a88c173 | 8604 | |
d37ea5d5 AK |
8605 | if (program_retries == 100) |
8606 | error = E1000_ERR_EEPROM; | |
8607 | ||
8608 | return error; | |
8609 | } | |
8610 | ||
8611 | /****************************************************************************** | |
8612 | * Writes a single byte to the NVM using the ICH8 flash access registers. | |
8613 | * | |
8614 | * hw - pointer to e1000_hw structure | |
8615 | * index - The index of the byte to read. | |
8616 | * data - The byte to write to the NVM. | |
8617 | *****************************************************************************/ | |
64798845 | 8618 | static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data) |
d37ea5d5 | 8619 | { |
406874a7 JP |
8620 | s32 status = E1000_SUCCESS; |
8621 | u16 word = (u16)data; | |
d37ea5d5 AK |
8622 | |
8623 | status = e1000_write_ich8_data(hw, index, 1, word); | |
8624 | ||
8625 | return status; | |
8626 | } | |
8627 | ||
8628 | /****************************************************************************** | |
8629 | * Reads a word from the NVM using the ICH8 flash access registers. | |
8630 | * | |
8631 | * hw - pointer to e1000_hw structure | |
8632 | * index - The starting byte index of the word to read. | |
8633 | * data - Pointer to a word to store the value read. | |
8634 | *****************************************************************************/ | |
64798845 | 8635 | static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data) |
d37ea5d5 | 8636 | { |
406874a7 | 8637 | s32 status = E1000_SUCCESS; |
d37ea5d5 AK |
8638 | status = e1000_read_ich8_data(hw, index, 2, data); |
8639 | return status; | |
8640 | } | |
8641 | ||
8642 | /****************************************************************************** | |
2a88c173 JK |
8643 | * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 |
8644 | * based. | |
d37ea5d5 AK |
8645 | * |
8646 | * hw - pointer to e1000_hw structure | |
2a88c173 | 8647 | * bank - 0 for first bank, 1 for second bank |
d37ea5d5 | 8648 | * |
2a88c173 JK |
8649 | * Note that this function may actually erase as much as 8 or 64 KBytes. The |
8650 | * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the | |
8651 | * bank size may be 4, 8 or 64 KBytes | |
d37ea5d5 | 8652 | *****************************************************************************/ |
64798845 | 8653 | static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank) |
d37ea5d5 AK |
8654 | { |
8655 | union ich8_hws_flash_status hsfsts; | |
8656 | union ich8_hws_flash_ctrl hsflctl; | |
406874a7 JP |
8657 | u32 flash_linear_address; |
8658 | s32 count = 0; | |
8659 | s32 error = E1000_ERR_EEPROM; | |
8660 | s32 iteration; | |
8661 | s32 sub_sector_size = 0; | |
8662 | s32 bank_size; | |
8663 | s32 j = 0; | |
8664 | s32 error_flag = 0; | |
d37ea5d5 | 8665 | |
2df7d59f | 8666 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8667 | |
8668 | /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ | |
8669 | /* 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
8670 | * consecutive sectors. The start index for the nth Hw sector can be | |
2a88c173 | 8671 | * calculated as bank * 4096 + n * 256 |
d37ea5d5 AK |
8672 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
8673 | * The start index for the nth Hw sector can be calculated | |
2a88c173 JK |
8674 | * as bank * 4096 |
8675 | * 10: The HW sector is 8K bytes | |
8676 | * 11: The Hw sector size is 64K bytes */ | |
d37ea5d5 AK |
8677 | if (hsfsts.hsf_status.berasesz == 0x0) { |
8678 | /* Hw sector size 256 */ | |
2df7d59f JK |
8679 | sub_sector_size = ICH_FLASH_SEG_SIZE_256; |
8680 | bank_size = ICH_FLASH_SECTOR_SIZE; | |
8681 | iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; | |
d37ea5d5 | 8682 | } else if (hsfsts.hsf_status.berasesz == 0x1) { |
2df7d59f | 8683 | bank_size = ICH_FLASH_SEG_SIZE_4K; |
d37ea5d5 AK |
8684 | iteration = 1; |
8685 | } else if (hsfsts.hsf_status.berasesz == 0x3) { | |
2df7d59f | 8686 | bank_size = ICH_FLASH_SEG_SIZE_64K; |
d37ea5d5 AK |
8687 | iteration = 1; |
8688 | } else { | |
8689 | return error; | |
8690 | } | |
8691 | ||
8692 | for (j = 0; j < iteration ; j++) { | |
8693 | do { | |
8694 | count++; | |
8695 | /* Steps */ | |
8696 | error = e1000_ich8_cycle_init(hw); | |
8697 | if (error != E1000_SUCCESS) { | |
8698 | error_flag = 1; | |
8699 | break; | |
8700 | } | |
8701 | ||
8702 | /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash | |
8703 | * Control */ | |
2df7d59f JK |
8704 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
8705 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
8706 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | |
d37ea5d5 AK |
8707 | |
8708 | /* Write the last 24 bits of an index within the block into Flash | |
8709 | * Linear address field in Flash Address. This probably needs to | |
2a88c173 JK |
8710 | * be calculated here based off the on-chip erase sector size and |
8711 | * the software bank size (4, 8 or 64 KBytes) */ | |
8712 | flash_linear_address = bank * bank_size + j * sub_sector_size; | |
d37ea5d5 | 8713 | flash_linear_address += hw->flash_base_addr; |
2df7d59f | 8714 | flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; |
d37ea5d5 | 8715 | |
2df7d59f | 8716 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
d37ea5d5 | 8717 | |
2df7d59f | 8718 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); |
d37ea5d5 AK |
8719 | /* Check if FCERR is set to 1. If 1, clear it and try the whole |
8720 | * sequence a few more times else Done */ | |
8721 | if (error == E1000_SUCCESS) { | |
8722 | break; | |
8723 | } else { | |
2df7d59f | 8724 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
d37ea5d5 AK |
8725 | if (hsfsts.hsf_status.flcerr == 1) { |
8726 | /* repeat for some time before giving up */ | |
8727 | continue; | |
8728 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
8729 | error_flag = 1; | |
8730 | break; | |
8731 | } | |
8732 | } | |
2df7d59f | 8733 | } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); |
d37ea5d5 AK |
8734 | if (error_flag == 1) |
8735 | break; | |
8736 | } | |
8737 | if (error_flag != 1) | |
8738 | error = E1000_SUCCESS; | |
8739 | return error; | |
8740 | } | |
8741 | ||
64798845 JP |
8742 | static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
8743 | u32 cnf_base_addr, | |
8744 | u32 cnf_size) | |
d37ea5d5 | 8745 | { |
406874a7 JP |
8746 | u32 ret_val = E1000_SUCCESS; |
8747 | u16 word_addr, reg_data, reg_addr; | |
8748 | u16 i; | |
d37ea5d5 AK |
8749 | |
8750 | /* cnf_base_addr is in DWORD */ | |
406874a7 | 8751 | word_addr = (u16)(cnf_base_addr << 1); |
d37ea5d5 AK |
8752 | |
8753 | /* cnf_size is returned in size of dwords */ | |
8754 | for (i = 0; i < cnf_size; i++) { | |
8755 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); | |
8756 | if (ret_val) | |
8757 | return ret_val; | |
8758 | ||
8759 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); | |
8760 | if (ret_val) | |
8761 | return ret_val; | |
8762 | ||
8763 | ret_val = e1000_get_software_flag(hw); | |
8764 | if (ret_val != E1000_SUCCESS) | |
8765 | return ret_val; | |
8766 | ||
406874a7 | 8767 | ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data); |
d37ea5d5 AK |
8768 | |
8769 | e1000_release_software_flag(hw); | |
8770 | } | |
8771 | ||
8772 | return ret_val; | |
8773 | } | |
8774 | ||
8775 | ||
2a88c173 JK |
8776 | /****************************************************************************** |
8777 | * This function initializes the PHY from the NVM on ICH8 platforms. This | |
8778 | * is needed due to an issue where the NVM configuration is not properly | |
8779 | * autoloaded after power transitions. Therefore, after each PHY reset, we | |
8780 | * will load the configuration data out of the NVM manually. | |
8781 | * | |
8782 | * hw: Struct containing variables accessed by shared code | |
8783 | *****************************************************************************/ | |
64798845 | 8784 | static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw) |
d37ea5d5 | 8785 | { |
406874a7 | 8786 | u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop; |
d37ea5d5 AK |
8787 | |
8788 | if (hw->phy_type != e1000_phy_igp_3) | |
8789 | return E1000_SUCCESS; | |
8790 | ||
8791 | /* Check if SW needs configure the PHY */ | |
1dc32918 | 8792 | reg_data = er32(FEXTNVM); |
d37ea5d5 AK |
8793 | if (!(reg_data & FEXTNVM_SW_CONFIG)) |
8794 | return E1000_SUCCESS; | |
8795 | ||
8796 | /* Wait for basic configuration completes before proceeding*/ | |
8797 | loop = 0; | |
8798 | do { | |
1dc32918 | 8799 | reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE; |
d37ea5d5 AK |
8800 | udelay(100); |
8801 | loop++; | |
8802 | } while ((!reg_data) && (loop < 50)); | |
8803 | ||
8804 | /* Clear the Init Done bit for the next init event */ | |
1dc32918 | 8805 | reg_data = er32(STATUS); |
d37ea5d5 | 8806 | reg_data &= ~E1000_STATUS_LAN_INIT_DONE; |
1dc32918 | 8807 | ew32(STATUS, reg_data); |
d37ea5d5 AK |
8808 | |
8809 | /* Make sure HW does not configure LCD from PHY extended configuration | |
8810 | before SW configuration */ | |
1dc32918 | 8811 | reg_data = er32(EXTCNF_CTRL); |
d37ea5d5 | 8812 | if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { |
1dc32918 | 8813 | reg_data = er32(EXTCNF_SIZE); |
d37ea5d5 AK |
8814 | cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; |
8815 | cnf_size >>= 16; | |
8816 | if (cnf_size) { | |
1dc32918 | 8817 | reg_data = er32(EXTCNF_CTRL); |
d37ea5d5 AK |
8818 | cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; |
8819 | /* cnf_base_addr is in DWORD */ | |
8820 | cnf_base_addr >>= 16; | |
8821 | ||
8822 | /* Configure LCD from extended configuration region. */ | |
8823 | ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, | |
8824 | cnf_size); | |
8825 | if (ret_val) | |
8826 | return ret_val; | |
8827 | } | |
8828 | } | |
8829 | ||
8830 | return E1000_SUCCESS; | |
8831 | } | |
8832 |