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Fix typo in meth driver
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
8fc897b0 33
1da177e4
LT		 34#include "e1000_hw.h"
35
406874a7
JP		 36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
35574764
NN		 41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
406874a7
JP		 43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static s32 e1000_check_downshift(struct e1000_hw *hw);
45static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
35574764
NN		 46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw);
406874a7
JP		 48static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
49static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
c3033b01 50 bool link_up);
406874a7
JP		 51static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
52static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
53static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
54static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
55static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length);
56static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
57static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
58static s32 e1000_get_software_flag(struct e1000_hw *hw);
59static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
60static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
61static s32 e1000_id_led_init(struct e1000_hw *hw);
62static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size);
63static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
35574764 64static void e1000_init_rx_addrs(struct e1000_hw *hw);
09ae3e88 65static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
c3033b01 66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
406874a7
JP		 67static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
68static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
69static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum);
70static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
71static s32 e1000_mng_write_commit(struct e1000_hw *hw);
72static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
74static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
75static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
76static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
77static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
35574764 78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
406874a7
JP		 79static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
80static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
81static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
82static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
83static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data);
84static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data);
85static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
86static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
35574764 87static void e1000_release_software_flag(struct e1000_hw *hw);
406874a7
JP		 88static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
90static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
35574764 91static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
406874a7
JP		 92static s32 e1000_wait_autoneg(struct e1000_hw *hw);
93static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
94static s32 e1000_set_phy_type(struct e1000_hw *hw);
1da177e4 95static void e1000_phy_init_script(struct e1000_hw *hw);
406874a7
JP		 96static s32 e1000_setup_copper_link(struct e1000_hw *hw);
97static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
98static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
99static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
100static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
101static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
102static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
104 u16 count);
105static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
106static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
107static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
108 u16 words, u16 *data);
109static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw,
110 u16 offset, u16 words,
111 u16 *data);
112static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
113static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
114static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data,
116 u16 count);
117static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
118 u16 phy_data);
119static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
120 u16 *phy_data);
121static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
122static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
1da177e4
LT		 123static void e1000_release_eeprom(struct e1000_hw *hw);
124static void e1000_standby_eeprom(struct e1000_hw *hw);
406874a7
JP		 125static s32 e1000_set_vco_speed(struct e1000_hw *hw);
126static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
127static s32 e1000_set_phy_mode(struct e1000_hw *hw);
128static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
129static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
130static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
131 u16 duplex);
132static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
1da177e4
LT		 133
134/* IGP cable length table */
135static const
406874a7 136u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
1da177e4
LT		 137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
140 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
141 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
142 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
143 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
145
2d7edb92 146static const
406874a7 147u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
868d5309
MC		 148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
151 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
152 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
153 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
154 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
155 104, 109, 114, 118, 121, 124};
2d7edb92 156
1da177e4
LT		 157/******************************************************************************
158 * Set the phy type member in the hw struct.
159 *
160 * hw - Struct containing variables accessed by shared code
161 *****************************************************************************/
406874a7 162static s32
1da177e4
LT		 163e1000_set_phy_type(struct e1000_hw *hw)
164{
165 DEBUGFUNC("e1000_set_phy_type");
166
8fc897b0 167 if (hw->mac_type == e1000_undefined)
2d7edb92
MC		 168 return -E1000_ERR_PHY_TYPE;
169
8fc897b0 170 switch (hw->phy_id) {
1da177e4
LT		 171 case M88E1000_E_PHY_ID:
172 case M88E1000_I_PHY_ID:
173 case M88E1011_I_PHY_ID:
2d7edb92 174 case M88E1111_I_PHY_ID:
1da177e4
LT		 175 hw->phy_type = e1000_phy_m88;
176 break;
177 case IGP01E1000_I_PHY_ID:
8fc897b0
AK		 178 if (hw->mac_type == e1000_82541 ||
179 hw->mac_type == e1000_82541_rev_2 ||
180 hw->mac_type == e1000_82547 ||
181 hw->mac_type == e1000_82547_rev_2) {
1da177e4
LT		 182 hw->phy_type = e1000_phy_igp;
183 break;
184 }
cd94dd0b
AK		 185 case IGP03E1000_E_PHY_ID:
186 hw->phy_type = e1000_phy_igp_3;
187 break;
188 case IFE_E_PHY_ID:
189 case IFE_PLUS_E_PHY_ID:
190 case IFE_C_E_PHY_ID:
191 hw->phy_type = e1000_phy_ife;
192 break;
6418ecc6
JK		 193 case GG82563_E_PHY_ID:
194 if (hw->mac_type == e1000_80003es2lan) {
195 hw->phy_type = e1000_phy_gg82563;
196 break;
197 }
1da177e4
LT		 198 /* Fall Through */
199 default:
200 /* Should never have loaded on this device */
201 hw->phy_type = e1000_phy_undefined;
202 return -E1000_ERR_PHY_TYPE;
203 }
204
205 return E1000_SUCCESS;
206}
207
208/******************************************************************************
209 * IGP phy init script - initializes the GbE PHY
210 *
211 * hw - Struct containing variables accessed by shared code
212 *****************************************************************************/
213static void
214e1000_phy_init_script(struct e1000_hw *hw)
215{
406874a7
JP		 216 u32 ret_val;
217 u16 phy_saved_data;
1da177e4
LT		 218
219 DEBUGFUNC("e1000_phy_init_script");
220
8fc897b0 221 if (hw->phy_init_script) {
f8ec4733 222 msleep(20);
1da177e4
LT		 223
224 /* Save off the current value of register 0x2F5B to be restored at
225 * the end of this routine. */
226 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
227
228 /* Disabled the PHY transmitter */
229 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
230
f8ec4733 231 msleep(20);
1da177e4
LT		 232
233 e1000_write_phy_reg(hw,0x0000,0x0140);
234
f8ec4733 235 msleep(5);
1da177e4 236
8fc897b0 237 switch (hw->mac_type) {
1da177e4
LT		 238 case e1000_82541:
239 case e1000_82547:
240 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
241
242 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
243
244 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
245
246 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
247
248 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
249
250 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
251
252 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
253
254 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
255
256 e1000_write_phy_reg(hw, 0x2010, 0x0008);
257 break;
258
259 case e1000_82541_rev_2:
260 case e1000_82547_rev_2:
261 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
262 break;
263 default:
264 break;
265 }
266
267 e1000_write_phy_reg(hw, 0x0000, 0x3300);
268
f8ec4733 269 msleep(20);
1da177e4
LT		 270
271 /* Now enable the transmitter */
272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
273
8fc897b0 274 if (hw->mac_type == e1000_82547) {
406874a7 275 u16 fused, fine, coarse;
1da177e4
LT		 276
277 /* Move to analog registers page */
278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
279
8fc897b0 280 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1da177e4
LT		 281 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
282
283 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
284 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
285
8fc897b0 286 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1da177e4
LT		 287 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
288 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8fc897b0 289 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1da177e4
LT		 290 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
291
292 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
293 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
294 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
295
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
297 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
298 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
299 }
300 }
301 }
302}
303
304/******************************************************************************
305 * Set the mac type member in the hw struct.
306 *
307 * hw - Struct containing variables accessed by shared code
308 *****************************************************************************/
406874a7 309s32
1da177e4
LT		 310e1000_set_mac_type(struct e1000_hw *hw)
311{
bd2371eb
JG		 312 DEBUGFUNC("e1000_set_mac_type");
313
314 switch (hw->device_id) {
315 case E1000_DEV_ID_82542:
316 switch (hw->revision_id) {
317 case E1000_82542_2_0_REV_ID:
318 hw->mac_type = e1000_82542_rev2_0;
319 break;
320 case E1000_82542_2_1_REV_ID:
321 hw->mac_type = e1000_82542_rev2_1;
322 break;
323 default:
324 /* Invalid 82542 revision ID */
325 return -E1000_ERR_MAC_TYPE;
326 }
327 break;
328 case E1000_DEV_ID_82543GC_FIBER:
329 case E1000_DEV_ID_82543GC_COPPER:
330 hw->mac_type = e1000_82543;
331 break;
332 case E1000_DEV_ID_82544EI_COPPER:
333 case E1000_DEV_ID_82544EI_FIBER:
334 case E1000_DEV_ID_82544GC_COPPER:
335 case E1000_DEV_ID_82544GC_LOM:
336 hw->mac_type = e1000_82544;
337 break;
338 case E1000_DEV_ID_82540EM:
339 case E1000_DEV_ID_82540EM_LOM:
340 case E1000_DEV_ID_82540EP:
341 case E1000_DEV_ID_82540EP_LOM:
342 case E1000_DEV_ID_82540EP_LP:
343 hw->mac_type = e1000_82540;
344 break;
345 case E1000_DEV_ID_82545EM_COPPER:
346 case E1000_DEV_ID_82545EM_FIBER:
347 hw->mac_type = e1000_82545;
348 break;
349 case E1000_DEV_ID_82545GM_COPPER:
350 case E1000_DEV_ID_82545GM_FIBER:
351 case E1000_DEV_ID_82545GM_SERDES:
352 hw->mac_type = e1000_82545_rev_3;
353 break;
354 case E1000_DEV_ID_82546EB_COPPER:
355 case E1000_DEV_ID_82546EB_FIBER:
356 case E1000_DEV_ID_82546EB_QUAD_COPPER:
357 hw->mac_type = e1000_82546;
358 break;
359 case E1000_DEV_ID_82546GB_COPPER:
360 case E1000_DEV_ID_82546GB_FIBER:
361 case E1000_DEV_ID_82546GB_SERDES:
362 case E1000_DEV_ID_82546GB_PCIE:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER:
364 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
365 hw->mac_type = e1000_82546_rev_3;
366 break;
367 case E1000_DEV_ID_82541EI:
368 case E1000_DEV_ID_82541EI_MOBILE:
369 case E1000_DEV_ID_82541ER_LOM:
370 hw->mac_type = e1000_82541;
371 break;
372 case E1000_DEV_ID_82541ER:
373 case E1000_DEV_ID_82541GI:
374 case E1000_DEV_ID_82541GI_LF:
375 case E1000_DEV_ID_82541GI_MOBILE:
376 hw->mac_type = e1000_82541_rev_2;
377 break;
378 case E1000_DEV_ID_82547EI:
379 case E1000_DEV_ID_82547EI_MOBILE:
380 hw->mac_type = e1000_82547;
381 break;
382 case E1000_DEV_ID_82547GI:
383 hw->mac_type = e1000_82547_rev_2;
384 break;
385 case E1000_DEV_ID_82571EB_COPPER:
386 case E1000_DEV_ID_82571EB_FIBER:
387 case E1000_DEV_ID_82571EB_SERDES:
ce57a02c
AK		 388 case E1000_DEV_ID_82571EB_SERDES_DUAL:
389 case E1000_DEV_ID_82571EB_SERDES_QUAD:
bd2371eb 390 case E1000_DEV_ID_82571EB_QUAD_COPPER:
f4ec7f98 391 case E1000_DEV_ID_82571PT_QUAD_COPPER:
ce57a02c 392 case E1000_DEV_ID_82571EB_QUAD_FIBER:
bd2371eb
JG		 393 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
394 hw->mac_type = e1000_82571;
395 break;
396 case E1000_DEV_ID_82572EI_COPPER:
397 case E1000_DEV_ID_82572EI_FIBER:
398 case E1000_DEV_ID_82572EI_SERDES:
399 case E1000_DEV_ID_82572EI:
400 hw->mac_type = e1000_82572;
401 break;
402 case E1000_DEV_ID_82573E:
403 case E1000_DEV_ID_82573E_IAMT:
404 case E1000_DEV_ID_82573L:
405 hw->mac_type = e1000_82573;
406 break;
407 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
408 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
409 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
410 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
411 hw->mac_type = e1000_80003es2lan;
412 break;
413 case E1000_DEV_ID_ICH8_IGP_M_AMT:
414 case E1000_DEV_ID_ICH8_IGP_AMT:
415 case E1000_DEV_ID_ICH8_IGP_C:
416 case E1000_DEV_ID_ICH8_IFE:
417 case E1000_DEV_ID_ICH8_IFE_GT:
418 case E1000_DEV_ID_ICH8_IFE_G:
419 case E1000_DEV_ID_ICH8_IGP_M:
420 hw->mac_type = e1000_ich8lan;
421 break;
422 default:
423 /* Should never have loaded on this device */
424 return -E1000_ERR_MAC_TYPE;
425 }
426
427 switch (hw->mac_type) {
428 case e1000_ich8lan:
c3033b01
JP		 429 hw->swfwhw_semaphore_present = true;
430 hw->asf_firmware_present = true;
bd2371eb
JG		 431 break;
432 case e1000_80003es2lan:
c3033b01 433 hw->swfw_sync_present = true;
bd2371eb
JG		 434 /* fall through */
435 case e1000_82571:
436 case e1000_82572:
437 case e1000_82573:
c3033b01 438 hw->eeprom_semaphore_present = true;
bd2371eb
JG		 439 /* fall through */
440 case e1000_82541:
441 case e1000_82547:
442 case e1000_82541_rev_2:
443 case e1000_82547_rev_2:
c3033b01 444 hw->asf_firmware_present = true;
bd2371eb
JG		 445 break;
446 default:
447 break;
448 }
449
167fb284
JG		 450 /* The 82543 chip does not count tx_carrier_errors properly in
451 * FD mode
452 */
453 if (hw->mac_type == e1000_82543)
c3033b01 454 hw->bad_tx_carr_stats_fd = true;
167fb284 455
0fccd0e9
JG		 456 /* capable of receiving management packets to the host */
457 if (hw->mac_type >= e1000_82571)
c3033b01 458 hw->has_manc2h = true;
0fccd0e9 459
bb8e3311
JG		 460 /* In rare occasions, ESB2 systems would end up started without
461 * the RX unit being turned on.
462 */
463 if (hw->mac_type == e1000_80003es2lan)
c3033b01 464 hw->rx_needs_kicking = true;
15e376b4
JG		 465
466 if (hw->mac_type > e1000_82544)
c3033b01 467 hw->has_smbus = true;
bb8e3311 468
bd2371eb 469 return E1000_SUCCESS;
1da177e4
LT		 470}
471
472/*****************************************************************************
473 * Set media type and TBI compatibility.
474 *
475 * hw - Struct containing variables accessed by shared code
476 * **************************************************************************/
477void
478e1000_set_media_type(struct e1000_hw *hw)
479{
406874a7 480 u32 status;
1da177e4
LT		 481
482 DEBUGFUNC("e1000_set_media_type");
483
8fc897b0 484 if (hw->mac_type != e1000_82543) {
1da177e4 485 /* tbi_compatibility is only valid on 82543 */
c3033b01 486 hw->tbi_compatibility_en = false;
1da177e4
LT		 487 }
488
489 switch (hw->device_id) {
490 case E1000_DEV_ID_82545GM_SERDES:
491 case E1000_DEV_ID_82546GB_SERDES:
868d5309 492 case E1000_DEV_ID_82571EB_SERDES:
ce57a02c
AK		 493 case E1000_DEV_ID_82571EB_SERDES_DUAL:
494 case E1000_DEV_ID_82571EB_SERDES_QUAD:
868d5309 495 case E1000_DEV_ID_82572EI_SERDES:
6418ecc6 496 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1da177e4
LT		 497 hw->media_type = e1000_media_type_internal_serdes;
498 break;
499 default:
3893d547
MC		 500 switch (hw->mac_type) {
501 case e1000_82542_rev2_0:
502 case e1000_82542_rev2_1:
503 hw->media_type = e1000_media_type_fiber;
504 break;
cd94dd0b 505 case e1000_ich8lan:
3893d547
MC		 506 case e1000_82573:
507 /* The STATUS_TBIMODE bit is reserved or reused for the this
508 * device.
509 */
510 hw->media_type = e1000_media_type_copper;
511 break;
512 default:
1da177e4 513 status = E1000_READ_REG(hw, STATUS);
3893d547 514 if (status & E1000_STATUS_TBIMODE) {
1da177e4
LT		 515 hw->media_type = e1000_media_type_fiber;
516 /* tbi_compatibility not valid on fiber */
c3033b01 517 hw->tbi_compatibility_en = false;
1da177e4
LT		 518 } else {
519 hw->media_type = e1000_media_type_copper;
520 }
3893d547 521 break;
1da177e4
LT		 522 }
523 }
524}
525
526/******************************************************************************
527 * Reset the transmit and receive units; mask and clear all interrupts.
528 *
529 * hw - Struct containing variables accessed by shared code
530 *****************************************************************************/
406874a7 531s32
1da177e4
LT		 532e1000_reset_hw(struct e1000_hw *hw)
533{
406874a7
JP		 534 u32 ctrl;
535 u32 ctrl_ext;
536 u32 icr;
537 u32 manc;
538 u32 led_ctrl;
539 u32 timeout;
540 u32 extcnf_ctrl;
541 s32 ret_val;
1da177e4
LT		 542
543 DEBUGFUNC("e1000_reset_hw");
544
545 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
8fc897b0 546 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 547 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
548 e1000_pci_clear_mwi(hw);
549 }
550
8fc897b0 551 if (hw->bus_type == e1000_bus_type_pci_express) {
2d7edb92
MC		 552 /* Prevent the PCI-E bus from sticking if there is no TLP connection
553 * on the last TLP read/write transaction when MAC is reset.
554 */
8fc897b0 555 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
2d7edb92
MC		 556 DEBUGOUT("PCI-E Master disable polling has failed.\n");
557 }
558 }
559
1da177e4
LT		 560 /* Clear interrupt mask to stop board from generating interrupts */
561 DEBUGOUT("Masking off all interrupts\n");
562 E1000_WRITE_REG(hw, IMC, 0xffffffff);
563
564 /* Disable the Transmit and Receive units. Then delay to allow
565 * any pending transactions to complete before we hit the MAC with
566 * the global reset.
567 */
568 E1000_WRITE_REG(hw, RCTL, 0);
569 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
570 E1000_WRITE_FLUSH(hw);
571
572 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
c3033b01 573 hw->tbi_compatibility_on = false;
1da177e4
LT		 574
575 /* Delay to allow any outstanding PCI transactions to complete before
576 * resetting the device
577 */
f8ec4733 578 msleep(10);
1da177e4
LT		 579
580 ctrl = E1000_READ_REG(hw, CTRL);
581
582 /* Must reset the PHY before resetting the MAC */
8fc897b0 583 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2d7edb92 584 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
f8ec4733 585 msleep(5);
1da177e4
LT		 586 }
587
2d7edb92
MC		 588 /* Must acquire the MDIO ownership before MAC reset.
589 * Ownership defaults to firmware after a reset. */
8fc897b0 590 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 591 timeout = 10;
592
593 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
594 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
595
596 do {
597 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
598 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
599
8fc897b0 600 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2d7edb92
MC		 601 break;
602 else
603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
604
f8ec4733 605 msleep(2);
2d7edb92 606 timeout--;
8fc897b0 607 } while (timeout);
2d7edb92
MC		 608 }
609
cd94dd0b
AK		 610 /* Workaround for ICH8 bit corruption issue in FIFO memory */
611 if (hw->mac_type == e1000_ich8lan) {
612 /* Set Tx and Rx buffer allocation to 8k apiece. */
613 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
614 /* Set Packet Buffer Size to 16k. */
615 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
616 }
617
1da177e4
LT		 618 /* Issue a global reset to the MAC. This will reset the chip's
619 * transmit, receive, DMA, and link units. It will not effect
620 * the current PCI configuration. The global reset bit is self-
621 * clearing, and should clear within a microsecond.
622 */
623 DEBUGOUT("Issuing a global reset to MAC\n");
624
8fc897b0 625 switch (hw->mac_type) {
1da177e4
LT		 626 case e1000_82544:
627 case e1000_82540:
628 case e1000_82545:
629 case e1000_82546:
630 case e1000_82541:
631 case e1000_82541_rev_2:
632 /* These controllers can't ack the 64-bit write when issuing the
633 * reset, so use IO-mapping as a workaround to issue the reset */
634 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
635 break;
636 case e1000_82545_rev_3:
637 case e1000_82546_rev_3:
638 /* Reset is performed on a shadow of the control register */
639 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
640 break;
cd94dd0b
AK		 641 case e1000_ich8lan:
642 if (!hw->phy_reset_disable &&
643 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
644 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
645 * at the same time to make sure the interface between
646 * MAC and the external PHY is reset.
647 */
648 ctrl |= E1000_CTRL_PHY_RST;
649 }
650
651 e1000_get_software_flag(hw);
652 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
f8ec4733 653 msleep(5);
cd94dd0b 654 break;
1da177e4
LT		 655 default:
656 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
657 break;
658 }
659
660 /* After MAC reset, force reload of EEPROM to restore power-on settings to
661 * device. Later controllers reload the EEPROM automatically, so just wait
662 * for reload to complete.
663 */
8fc897b0 664 switch (hw->mac_type) {
1da177e4
LT		 665 case e1000_82542_rev2_0:
666 case e1000_82542_rev2_1:
667 case e1000_82543:
668 case e1000_82544:
669 /* Wait for reset to complete */
670 udelay(10);
671 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
672 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
673 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
674 E1000_WRITE_FLUSH(hw);
675 /* Wait for EEPROM reload */
f8ec4733 676 msleep(2);
1da177e4
LT		 677 break;
678 case e1000_82541:
679 case e1000_82541_rev_2:
680 case e1000_82547:
681 case e1000_82547_rev_2:
682 /* Wait for EEPROM reload */
f8ec4733 683 msleep(20);
1da177e4 684 break;
2d7edb92 685 case e1000_82573:
c3033b01 686 if (!e1000_is_onboard_nvm_eeprom(hw)) {
fd803241
JK		 687 udelay(10);
688 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
689 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
690 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
691 E1000_WRITE_FLUSH(hw);
692 }
2d7edb92 693 /* fall through */
2a88c173
JK		 694 default:
695 /* Auto read done will delay 5ms or poll based on mac type */
2d7edb92 696 ret_val = e1000_get_auto_rd_done(hw);
8fc897b0 697 if (ret_val)
2d7edb92
MC		 698 return ret_val;
699 break;
1da177e4
LT		 700 }
701
702 /* Disable HW ARPs on ASF enabled adapters */
8fc897b0 703 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
1da177e4
LT		 704 manc = E1000_READ_REG(hw, MANC);
705 manc &= ~(E1000_MANC_ARP_EN);
706 E1000_WRITE_REG(hw, MANC, manc);
707 }
708
8fc897b0 709 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 710 e1000_phy_init_script(hw);
711
712 /* Configure activity LED after PHY reset */
713 led_ctrl = E1000_READ_REG(hw, LEDCTL);
714 led_ctrl &= IGP_ACTIVITY_LED_MASK;
715 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
716 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
717 }
718
719 /* Clear interrupt mask to stop board from generating interrupts */
720 DEBUGOUT("Masking off all interrupts\n");
721 E1000_WRITE_REG(hw, IMC, 0xffffffff);
722
723 /* Clear any pending interrupt events. */
724 icr = E1000_READ_REG(hw, ICR);
725
726 /* If MWI was previously enabled, reenable it. */
8fc897b0 727 if (hw->mac_type == e1000_82542_rev2_0) {
f8ec4733 728 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 729 e1000_pci_set_mwi(hw);
730 }
731
cd94dd0b 732 if (hw->mac_type == e1000_ich8lan) {
406874a7 733 u32 kab = E1000_READ_REG(hw, KABGTXD);
cd94dd0b
AK		 734 kab |= E1000_KABGTXD_BGSQLBIAS;
735 E1000_WRITE_REG(hw, KABGTXD, kab);
736 }
737
1da177e4
LT		 738 return E1000_SUCCESS;
739}
740
09ae3e88
JK		 741/******************************************************************************
742 *
743 * Initialize a number of hardware-dependent bits
744 *
745 * hw: Struct containing variables accessed by shared code
746 *
747 * This function contains hardware limitation workarounds for PCI-E adapters
748 *
749 *****************************************************************************/
750static void
751e1000_initialize_hardware_bits(struct e1000_hw *hw)
752{
753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
754 /* Settings common to all PCI-express silicon */
406874a7
JP		 755 u32 reg_ctrl, reg_ctrl_ext;
756 u32 reg_tarc0, reg_tarc1;
757 u32 reg_tctl;
758 u32 reg_txdctl, reg_txdctl1;
09ae3e88
JK		 759
760 /* link autonegotiation/sync workarounds */
761 reg_tarc0 = E1000_READ_REG(hw, TARC0);
762 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
763
764 /* Enable not-done TX descriptor counting */
765 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
766 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
767 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
768 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
769 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
770 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
771
772 switch (hw->mac_type) {
773 case e1000_82571:
774 case e1000_82572:
775 /* Clear PHY TX compatible mode bits */
776 reg_tarc1 = E1000_READ_REG(hw, TARC1);
777 reg_tarc1 &= ~((1 << 30)|(1 << 29));
778
779 /* link autonegotiation/sync workarounds */
780 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
781
782 /* TX ring control fixes */
783 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
784
785 /* Multiple read bit is reversed polarity */
786 reg_tctl = E1000_READ_REG(hw, TCTL);
787 if (reg_tctl & E1000_TCTL_MULR)
788 reg_tarc1 &= ~(1 << 28);
789 else
790 reg_tarc1 |= (1 << 28);
791
792 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
793 break;
794 case e1000_82573:
795 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
796 reg_ctrl_ext &= ~(1 << 23);
797 reg_ctrl_ext |= (1 << 22);
798
799 /* TX byte count fix */
800 reg_ctrl = E1000_READ_REG(hw, CTRL);
801 reg_ctrl &= ~(1 << 29);
802
803 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
804 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
805 break;
806 case e1000_80003es2lan:
807 /* improve small packet performace for fiber/serdes */
808 if ((hw->media_type == e1000_media_type_fiber) ||
809 (hw->media_type == e1000_media_type_internal_serdes)) {
810 reg_tarc0 &= ~(1 << 20);
811 }
812
813 /* Multiple read bit is reversed polarity */
814 reg_tctl = E1000_READ_REG(hw, TCTL);
815 reg_tarc1 = E1000_READ_REG(hw, TARC1);
816 if (reg_tctl & E1000_TCTL_MULR)
817 reg_tarc1 &= ~(1 << 28);
818 else
819 reg_tarc1 |= (1 << 28);
820
821 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
822 break;
823 case e1000_ich8lan:
824 /* Reduce concurrent DMA requests to 3 from 4 */
825 if ((hw->revision_id < 3) ||
826 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
827 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
828 reg_tarc0 |= ((1 << 29)|(1 << 28));
829
830 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
831 reg_ctrl_ext |= (1 << 22);
832 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
833
834 /* workaround TX hang with TSO=on */
835 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
836
837 /* Multiple read bit is reversed polarity */
838 reg_tctl = E1000_READ_REG(hw, TCTL);
839 reg_tarc1 = E1000_READ_REG(hw, TARC1);
840 if (reg_tctl & E1000_TCTL_MULR)
841 reg_tarc1 &= ~(1 << 28);
842 else
843 reg_tarc1 |= (1 << 28);
844
845 /* workaround TX hang with TSO=on */
846 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
847
848 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
849 break;
850 default:
851 break;
852 }
853
854 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
855 }
856}
857
1da177e4
LT		 858/******************************************************************************
859 * Performs basic configuration of the adapter.
860 *
861 * hw - Struct containing variables accessed by shared code
862 *
863 * Assumes that the controller has previously been reset and is in a
864 * post-reset uninitialized state. Initializes the receive address registers,
865 * multicast table, and VLAN filter table. Calls routines to setup link
866 * configuration and flow control settings. Clears all on-chip counters. Leaves
867 * the transmit and receive units disabled and uninitialized.
868 *****************************************************************************/
406874a7 869s32
1da177e4
LT		 870e1000_init_hw(struct e1000_hw *hw)
871{
406874a7
JP		 872 u32 ctrl;
873 u32 i;
874 s32 ret_val;
875 u32 mta_size;
876 u32 reg_data;
877 u32 ctrl_ext;
2d7edb92 878
1da177e4
LT		 879 DEBUGFUNC("e1000_init_hw");
880
7820d428 881 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
09ae3e88
JK		 882 if ((hw->mac_type == e1000_ich8lan) &&
883 ((hw->revision_id < 3) ||
884 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
885 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
886 reg_data = E1000_READ_REG(hw, STATUS);
887 reg_data &= ~0x80000000;
888 E1000_WRITE_REG(hw, STATUS, reg_data);
7820d428
JK		 889 }
890
1da177e4
LT		 891 /* Initialize Identification LED */
892 ret_val = e1000_id_led_init(hw);
8fc897b0 893 if (ret_val) {
1da177e4
LT		 894 DEBUGOUT("Error Initializing Identification LED\n");
895 return ret_val;
896 }
897
898 /* Set the media type and TBI compatibility */
899 e1000_set_media_type(hw);
900
09ae3e88
JK		 901 /* Must be called after e1000_set_media_type because media_type is used */
902 e1000_initialize_hardware_bits(hw);
903
1da177e4
LT		 904 /* Disabling VLAN filtering. */
905 DEBUGOUT("Initializing the IEEE VLAN\n");
cd94dd0b
AK		 906 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
907 if (hw->mac_type != e1000_ich8lan) {
908 if (hw->mac_type < e1000_82545_rev_3)
909 E1000_WRITE_REG(hw, VET, 0);
910 e1000_clear_vfta(hw);
911 }
1da177e4
LT		 912
913 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
8fc897b0 914 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 915 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
916 e1000_pci_clear_mwi(hw);
917 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
918 E1000_WRITE_FLUSH(hw);
f8ec4733 919 msleep(5);
1da177e4
LT		 920 }
921
922 /* Setup the receive address. This involves initializing all of the Receive
923 * Address Registers (RARs 0 - 15).
924 */
925 e1000_init_rx_addrs(hw);
926
927 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
8fc897b0 928 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 929 E1000_WRITE_REG(hw, RCTL, 0);
930 E1000_WRITE_FLUSH(hw);
f8ec4733
JG		 931 msleep(1);
932 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 933 e1000_pci_set_mwi(hw);
934 }
935
936 /* Zero out the Multicast HASH table */
937 DEBUGOUT("Zeroing the MTA\n");
2d7edb92 938 mta_size = E1000_MC_TBL_SIZE;
cd94dd0b
AK		 939 if (hw->mac_type == e1000_ich8lan)
940 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
8fc897b0 941 for (i = 0; i < mta_size; i++) {
1da177e4 942 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 943 /* use write flush to prevent Memory Write Block (MWB) from
944 * occuring when accessing our register space */
945 E1000_WRITE_FLUSH(hw);
946 }
1da177e4
LT		 947
948 /* Set the PCI priority bit correctly in the CTRL register. This
949 * determines if the adapter gives priority to receives, or if it
2d7edb92
MC		 950 * gives equal priority to transmits and receives. Valid only on
951 * 82542 and 82543 silicon.
1da177e4 952 */
8fc897b0 953 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1da177e4
LT		 954 ctrl = E1000_READ_REG(hw, CTRL);
955 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
956 }
957
8fc897b0 958 switch (hw->mac_type) {
1da177e4
LT		 959 case e1000_82545_rev_3:
960 case e1000_82546_rev_3:
961 break;
962 default:
963 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
007755eb
PO		 964 if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
965 e1000_pcix_set_mmrbc(hw, 2048);
966 break;
1da177e4
LT		 967 }
968
cd94dd0b
AK		 969 /* More time needed for PHY to initialize */
970 if (hw->mac_type == e1000_ich8lan)
f8ec4733 971 msleep(15);
cd94dd0b 972
1da177e4
LT		 973 /* Call a subroutine to configure the link and setup flow control. */
974 ret_val = e1000_setup_link(hw);
975
976 /* Set the transmit descriptor write-back policy */
8fc897b0 977 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 978 ctrl = E1000_READ_REG(hw, TXDCTL);
979 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
980 E1000_WRITE_REG(hw, TXDCTL, ctrl);
981 }
982
2d7edb92 983 if (hw->mac_type == e1000_82573) {
76c224bc 984 e1000_enable_tx_pkt_filtering(hw);
2d7edb92
MC		 985 }
986
868d5309
MC		 987 switch (hw->mac_type) {
988 default:
989 break;
6418ecc6
JK		 990 case e1000_80003es2lan:
991 /* Enable retransmit on late collisions */
992 reg_data = E1000_READ_REG(hw, TCTL);
993 reg_data |= E1000_TCTL_RTLC;
994 E1000_WRITE_REG(hw, TCTL, reg_data);
995
996 /* Configure Gigabit Carry Extend Padding */
997 reg_data = E1000_READ_REG(hw, TCTL_EXT);
998 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
999 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1000 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1001
1002 /* Configure Transmit Inter-Packet Gap */
1003 reg_data = E1000_READ_REG(hw, TIPG);
1004 reg_data &= ~E1000_TIPG_IPGT_MASK;
1005 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1006 E1000_WRITE_REG(hw, TIPG, reg_data);
1007
1008 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1009 reg_data &= ~0x00100000;
1010 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1011 /* Fall through */
868d5309 1012 case e1000_82571:
a7990ba6 1013 case e1000_82572:
cd94dd0b 1014 case e1000_ich8lan:
868d5309 1015 ctrl = E1000_READ_REG(hw, TXDCTL1);
6418ecc6 1016 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
868d5309
MC		 1017 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1018 break;
1019 }
1020
1021
868d5309 1022 if (hw->mac_type == e1000_82573) {
406874a7 1023 u32 gcr = E1000_READ_REG(hw, GCR);
868d5309
MC		 1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1025 E1000_WRITE_REG(hw, GCR, gcr);
1026 }
2d7edb92 1027
1da177e4
LT		 1028 /* Clear all of the statistics registers (clear on read). It is
1029 * important that we do this after we have tried to establish link
1030 * because the symbol error count will increment wildly if there
1031 * is no link.
1032 */
1033 e1000_clear_hw_cntrs(hw);
1034
cd94dd0b
AK		 1035 /* ICH8 No-snoop bits are opposite polarity.
1036 * Set to snoop by default after reset. */
1037 if (hw->mac_type == e1000_ich8lan)
1038 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1039
b7ee49db
JK		 1040 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1041 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1042 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1043 /* Relaxed ordering must be disabled to avoid a parity
1044 * error crash in a PCI slot. */
1045 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1046 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1047 }
1048
1da177e4
LT		 1049 return ret_val;
1050}
1051
1052/******************************************************************************
1053 * Adjust SERDES output amplitude based on EEPROM setting.
1054 *
1055 * hw - Struct containing variables accessed by shared code.
1056 *****************************************************************************/
406874a7 1057static s32
1da177e4
LT		 1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1059{
406874a7
JP		 1060 u16 eeprom_data;
1061 s32 ret_val;
1da177e4
LT		 1062
1063 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1064
8fc897b0 1065 if (hw->media_type != e1000_media_type_internal_serdes)
1da177e4
LT		 1066 return E1000_SUCCESS;
1067
8fc897b0 1068 switch (hw->mac_type) {
1da177e4
LT		 1069 case e1000_82545_rev_3:
1070 case e1000_82546_rev_3:
1071 break;
1072 default:
1073 return E1000_SUCCESS;
1074 }
1075
1076 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1077 if (ret_val) {
1078 return ret_val;
1079 }
1080
8fc897b0 1081 if (eeprom_data != EEPROM_RESERVED_WORD) {
1da177e4 1082 /* Adjust SERDES output amplitude only. */
76c224bc 1083 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1da177e4 1084 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
8fc897b0 1085 if (ret_val)
1da177e4
LT		 1086 return ret_val;
1087 }
1088
1089 return E1000_SUCCESS;
1090}
1091
1092/******************************************************************************
1093 * Configures flow control and link settings.
1094 *
1095 * hw - Struct containing variables accessed by shared code
1096 *
1097 * Determines which flow control settings to use. Calls the apropriate media-
1098 * specific link configuration function. Configures the flow control settings.
1099 * Assuming the adapter has a valid link partner, a valid link should be
1100 * established. Assumes the hardware has previously been reset and the
1101 * transmitter and receiver are not enabled.
1102 *****************************************************************************/
406874a7 1103s32
1da177e4
LT		 1104e1000_setup_link(struct e1000_hw *hw)
1105{
406874a7
JP		 1106 u32 ctrl_ext;
1107 s32 ret_val;
1108 u16 eeprom_data;
1da177e4
LT		 1109
1110 DEBUGFUNC("e1000_setup_link");
1111
526f9957
JK		 1112 /* In the case of the phy reset being blocked, we already have a link.
1113 * We do not have to set it up again. */
1114 if (e1000_check_phy_reset_block(hw))
1115 return E1000_SUCCESS;
1116
1da177e4
LT		 1117 /* Read and store word 0x0F of the EEPROM. This word contains bits
1118 * that determine the hardware's default PAUSE (flow control) mode,
1119 * a bit that determines whether the HW defaults to enabling or
1120 * disabling auto-negotiation, and the direction of the
1121 * SW defined pins. If there is no SW over-ride of the flow
1122 * control setting, then the variable hw->fc will
1123 * be initialized based on a value in the EEPROM.
1124 */
11241b10 1125 if (hw->fc == E1000_FC_DEFAULT) {
fd803241 1126 switch (hw->mac_type) {
cd94dd0b 1127 case e1000_ich8lan:
fd803241 1128 case e1000_82573:
11241b10 1129 hw->fc = E1000_FC_FULL;
fd803241
JK		 1130 break;
1131 default:
1132 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1133 1, &eeprom_data);
1134 if (ret_val) {
1135 DEBUGOUT("EEPROM Read Error\n");
1136 return -E1000_ERR_EEPROM;
1137 }
1138 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
11241b10 1139 hw->fc = E1000_FC_NONE;
fd803241
JK		 1140 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1141 EEPROM_WORD0F_ASM_DIR)
11241b10 1142 hw->fc = E1000_FC_TX_PAUSE;
fd803241 1143 else
11241b10 1144 hw->fc = E1000_FC_FULL;
fd803241
JK		 1145 break;
1146 }
1da177e4
LT		 1147 }
1148
1149 /* We want to save off the original Flow Control configuration just
1150 * in case we get disconnected and then reconnected into a different
1151 * hub or switch with different Flow Control capabilities.
1152 */
8fc897b0 1153 if (hw->mac_type == e1000_82542_rev2_0)
11241b10 1154 hw->fc &= (~E1000_FC_TX_PAUSE);
1da177e4 1155
8fc897b0 1156 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
11241b10 1157 hw->fc &= (~E1000_FC_RX_PAUSE);
1da177e4
LT		 1158
1159 hw->original_fc = hw->fc;
1160
1161 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1162
1163 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1164 * polarity value for the SW controlled pins, and setup the
1165 * Extended Device Control reg with that info.
1166 * This is needed because one of the SW controlled pins is used for
1167 * signal detection. So this should be done before e1000_setup_pcs_link()
1168 * or e1000_phy_setup() is called.
1169 */
497fce5e 1170 if (hw->mac_type == e1000_82543) {
8fc897b0
AK		 1171 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1172 1, &eeprom_data);
1173 if (ret_val) {
1174 DEBUGOUT("EEPROM Read Error\n");
1175 return -E1000_ERR_EEPROM;
1176 }
1da177e4
LT		 1177 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1178 SWDPIO__EXT_SHIFT);
1179 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1180 }
1181
1182 /* Call the necessary subroutine to configure the link. */
1183 ret_val = (hw->media_type == e1000_media_type_copper) ?
1184 e1000_setup_copper_link(hw) :
1185 e1000_setup_fiber_serdes_link(hw);
1186
1187 /* Initialize the flow control address, type, and PAUSE timer
1188 * registers to their default values. This is done even if flow
1189 * control is disabled, because it does not hurt anything to
1190 * initialize these registers.
1191 */
1192 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1193
cd94dd0b
AK		 1194 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1195 if (hw->mac_type != e1000_ich8lan) {
1196 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1197 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1198 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1199 }
2d7edb92 1200
1da177e4
LT		 1201 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1202
1203 /* Set the flow control receive threshold registers. Normally,
1204 * these registers will be set to a default threshold that may be
1205 * adjusted later by the driver's runtime code. However, if the
1206 * ability to transmit pause frames in not enabled, then these
1207 * registers will be set to 0.
1208 */
11241b10 1209 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1da177e4
LT		 1210 E1000_WRITE_REG(hw, FCRTL, 0);
1211 E1000_WRITE_REG(hw, FCRTH, 0);
1212 } else {
1213 /* We need to set up the Receive Threshold high and low water marks
1214 * as well as (optionally) enabling the transmission of XON frames.
1215 */
8fc897b0 1216 if (hw->fc_send_xon) {
1da177e4
LT		 1217 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1218 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1219 } else {
1220 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1221 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1222 }
1223 }
1224 return ret_val;
1225}
1226
1227/******************************************************************************
1228 * Sets up link for a fiber based or serdes based adapter
1229 *
1230 * hw - Struct containing variables accessed by shared code
1231 *
1232 * Manipulates Physical Coding Sublayer functions in order to configure
1233 * link. Assumes the hardware has been previously reset and the transmitter
1234 * and receiver are not enabled.
1235 *****************************************************************************/
406874a7 1236static s32
1da177e4
LT		 1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1238{
406874a7
JP		 1239 u32 ctrl;
1240 u32 status;
1241 u32 txcw = 0;
1242 u32 i;
1243 u32 signal = 0;
1244 s32 ret_val;
1da177e4
LT		 1245
1246 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1247
868d5309
MC		 1248 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1249 * until explicitly turned off or a power cycle is performed. A read to
1250 * the register does not indicate its status. Therefore, we ensure
1251 * loopback mode is disabled during initialization.
1252 */
1253 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1254 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1255
09ae3e88 1256 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1da177e4
LT		 1257 * set when the optics detect a signal. On older adapters, it will be
1258 * cleared when there is a signal. This applies to fiber media only.
09ae3e88
JK		 1259 * If we're on serdes media, adjust the output amplitude to value
1260 * set in the EEPROM.
1da177e4
LT		 1261 */
1262 ctrl = E1000_READ_REG(hw, CTRL);
8fc897b0 1263 if (hw->media_type == e1000_media_type_fiber)
1da177e4
LT		 1264 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1265
1266 ret_val = e1000_adjust_serdes_amplitude(hw);
8fc897b0 1267 if (ret_val)
1da177e4
LT		 1268 return ret_val;
1269
1270 /* Take the link out of reset */
1271 ctrl &= ~(E1000_CTRL_LRST);
1272
1273 /* Adjust VCO speed to improve BER performance */
1274 ret_val = e1000_set_vco_speed(hw);
8fc897b0 1275 if (ret_val)
1da177e4
LT		 1276 return ret_val;
1277
1278 e1000_config_collision_dist(hw);
1279
1280 /* Check for a software override of the flow control settings, and setup
1281 * the device accordingly. If auto-negotiation is enabled, then software
1282 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1283 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1284 * auto-negotiation is disabled, then software will have to manually
1285 * configure the two flow control enable bits in the CTRL register.
1286 *
1287 * The possible values of the "fc" parameter are:
1288 * 0: Flow control is completely disabled
1289 * 1: Rx flow control is enabled (we can receive pause frames, but
1290 * not send pause frames).
1291 * 2: Tx flow control is enabled (we can send pause frames but we do
1292 * not support receiving pause frames).
1293 * 3: Both Rx and TX flow control (symmetric) are enabled.
1294 */
1295 switch (hw->fc) {
11241b10 1296 case E1000_FC_NONE:
1da177e4
LT		 1297 /* Flow control is completely disabled by a software over-ride. */
1298 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1299 break;
11241b10 1300 case E1000_FC_RX_PAUSE:
1da177e4
LT		 1301 /* RX Flow control is enabled and TX Flow control is disabled by a
1302 * software over-ride. Since there really isn't a way to advertise
1303 * that we are capable of RX Pause ONLY, we will advertise that we
1304 * support both symmetric and asymmetric RX PAUSE. Later, we will
1305 * disable the adapter's ability to send PAUSE frames.
1306 */
1307 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1308 break;
11241b10 1309 case E1000_FC_TX_PAUSE:
1da177e4
LT		 1310 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1311 * software over-ride.
1312 */
1313 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1314 break;
11241b10 1315 case E1000_FC_FULL:
1da177e4
LT		 1316 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1317 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1318 break;
1319 default:
1320 DEBUGOUT("Flow control param set incorrectly\n");
1321 return -E1000_ERR_CONFIG;
1322 break;
1323 }
1324
1325 /* Since auto-negotiation is enabled, take the link out of reset (the link
1326 * will be in reset, because we previously reset the chip). This will
1327 * restart auto-negotiation. If auto-neogtiation is successful then the
1328 * link-up status bit will be set and the flow control enable bits (RFCE
1329 * and TFCE) will be set according to their negotiated value.
1330 */
1331 DEBUGOUT("Auto-negotiation enabled\n");
1332
1333 E1000_WRITE_REG(hw, TXCW, txcw);
1334 E1000_WRITE_REG(hw, CTRL, ctrl);
1335 E1000_WRITE_FLUSH(hw);
1336
1337 hw->txcw = txcw;
f8ec4733 1338 msleep(1);
1da177e4
LT		 1339
1340 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1341 * indication in the Device Status Register. Time-out if a link isn't
1342 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1343 * less than 500 milliseconds even if the other end is doing it in SW).
1344 * For internal serdes, we just assume a signal is present, then poll.
1345 */
8fc897b0 1346 if (hw->media_type == e1000_media_type_internal_serdes ||
1da177e4
LT		 1347 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1348 DEBUGOUT("Looking for Link\n");
8fc897b0 1349 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
f8ec4733 1350 msleep(10);
1da177e4 1351 status = E1000_READ_REG(hw, STATUS);
8fc897b0 1352 if (status & E1000_STATUS_LU) break;
1da177e4 1353 }
8fc897b0 1354 if (i == (LINK_UP_TIMEOUT / 10)) {
1da177e4
LT		 1355 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1356 hw->autoneg_failed = 1;
1357 /* AutoNeg failed to achieve a link, so we'll call
1358 * e1000_check_for_link. This routine will force the link up if
1359 * we detect a signal. This will allow us to communicate with
1360 * non-autonegotiating link partners.
1361 */
1362 ret_val = e1000_check_for_link(hw);
8fc897b0 1363 if (ret_val) {
1da177e4
LT		 1364 DEBUGOUT("Error while checking for link\n");
1365 return ret_val;
1366 }
1367 hw->autoneg_failed = 0;
1368 } else {
1369 hw->autoneg_failed = 0;
1370 DEBUGOUT("Valid Link Found\n");
1371 }
1372 } else {
1373 DEBUGOUT("No Signal Detected\n");
1374 }
1375 return E1000_SUCCESS;
1376}
1377
1378/******************************************************************************
2d7edb92 1379* Make sure we have a valid PHY and change PHY mode before link setup.
1da177e4
LT		 1380*
1381* hw - Struct containing variables accessed by shared code
1382******************************************************************************/
406874a7 1383static s32
2d7edb92 1384e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4 1385{
406874a7
JP		 1386 u32 ctrl;
1387 s32 ret_val;
1388 u16 phy_data;
1da177e4 1389
2d7edb92 1390 DEBUGFUNC("e1000_copper_link_preconfig");
1da177e4
LT		 1391
1392 ctrl = E1000_READ_REG(hw, CTRL);
1393 /* With 82543, we need to force speed and duplex on the MAC equal to what
1394 * the PHY speed and duplex configuration is. In addition, we need to
1395 * perform a hardware reset on the PHY to take it out of reset.
1396 */
8fc897b0 1397 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 1398 ctrl |= E1000_CTRL_SLU;
1399 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1400 E1000_WRITE_REG(hw, CTRL, ctrl);
1401 } else {
1402 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1403 E1000_WRITE_REG(hw, CTRL, ctrl);
2d7edb92 1404 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 1405 if (ret_val)
2d7edb92 1406 return ret_val;
1da177e4
LT		 1407 }
1408
1409 /* Make sure we have a valid PHY */
1410 ret_val = e1000_detect_gig_phy(hw);
8fc897b0 1411 if (ret_val) {
1da177e4
LT		 1412 DEBUGOUT("Error, did not detect valid phy.\n");
1413 return ret_val;
1414 }
1415 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1416
1417 /* Set PHY to class A mode (if necessary) */
1418 ret_val = e1000_set_phy_mode(hw);
8fc897b0 1419 if (ret_val)
1da177e4
LT		 1420 return ret_val;
1421
8fc897b0 1422 if ((hw->mac_type == e1000_82545_rev_3) ||
1da177e4
LT		 1423 (hw->mac_type == e1000_82546_rev_3)) {
1424 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1425 phy_data |= 0x00000008;
1426 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1427 }
1428
8fc897b0
AK		 1429 if (hw->mac_type <= e1000_82543 ||
1430 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1431 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
c3033b01 1432 hw->phy_reset_disable = false;
1da177e4 1433
2d7edb92
MC		 1434 return E1000_SUCCESS;
1435}
1da177e4 1436
1da177e4 1437
2d7edb92
MC		 1438/********************************************************************
1439* Copper link setup for e1000_phy_igp series.
1440*
1441* hw - Struct containing variables accessed by shared code
1442*********************************************************************/
406874a7 1443static s32
2d7edb92
MC		 1444e1000_copper_link_igp_setup(struct e1000_hw *hw)
1445{
406874a7
JP		 1446 u32 led_ctrl;
1447 s32 ret_val;
1448 u16 phy_data;
1da177e4 1449
2d7edb92 1450 DEBUGFUNC("e1000_copper_link_igp_setup");
1da177e4 1451
2d7edb92
MC		 1452 if (hw->phy_reset_disable)
1453 return E1000_SUCCESS;
76c224bc 1454
2d7edb92
MC		 1455 ret_val = e1000_phy_reset(hw);
1456 if (ret_val) {
1457 DEBUGOUT("Error Resetting the PHY\n");
1458 return ret_val;
1459 }
1da177e4 1460
8fc897b0 1461 /* Wait 15ms for MAC to configure PHY from eeprom settings */
f8ec4733 1462 msleep(15);
cd94dd0b 1463 if (hw->mac_type != e1000_ich8lan) {
2d7edb92
MC		 1464 /* Configure activity LED after PHY reset */
1465 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1466 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1467 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1468 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
cd94dd0b 1469 }
1da177e4 1470
c9c1b834
JK		 1471 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1472 if (hw->phy_type == e1000_phy_igp) {
1473 /* disable lplu d3 during driver init */
c3033b01 1474 ret_val = e1000_set_d3_lplu_state(hw, false);
c9c1b834
JK		 1475 if (ret_val) {
1476 DEBUGOUT("Error Disabling LPLU D3\n");
1477 return ret_val;
1478 }
2d7edb92 1479 }
1da177e4 1480
2d7edb92 1481 /* disable lplu d0 during driver init */
c3033b01 1482 ret_val = e1000_set_d0_lplu_state(hw, false);
2d7edb92
MC		 1483 if (ret_val) {
1484 DEBUGOUT("Error Disabling LPLU D0\n");
1485 return ret_val;
1486 }
1487 /* Configure mdi-mdix settings */
1488 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1489 if (ret_val)
1490 return ret_val;
1da177e4 1491
2d7edb92
MC		 1492 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1493 hw->dsp_config_state = e1000_dsp_config_disabled;
1494 /* Force MDI for earlier revs of the IGP PHY */
1495 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1496 hw->mdix = 1;
1da177e4 1497
2d7edb92
MC		 1498 } else {
1499 hw->dsp_config_state = e1000_dsp_config_enabled;
1500 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1da177e4 1501
2d7edb92
MC		 1502 switch (hw->mdix) {
1503 case 1:
1504 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1505 break;
1506 case 2:
1507 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1508 break;
1509 case 0:
1510 default:
1511 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1512 break;
1513 }
1514 }
1515 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 1516 if (ret_val)
2d7edb92 1517 return ret_val;
1da177e4 1518
2d7edb92 1519 /* set auto-master slave resolution settings */
8fc897b0 1520 if (hw->autoneg) {
2d7edb92 1521 e1000_ms_type phy_ms_setting = hw->master_slave;
1da177e4 1522
8fc897b0 1523 if (hw->ffe_config_state == e1000_ffe_config_active)
2d7edb92 1524 hw->ffe_config_state = e1000_ffe_config_enabled;
1da177e4 1525
8fc897b0 1526 if (hw->dsp_config_state == e1000_dsp_config_activated)
2d7edb92 1527 hw->dsp_config_state = e1000_dsp_config_enabled;
1da177e4 1528
2d7edb92
MC		 1529 /* when autonegotiation advertisment is only 1000Mbps then we
1530 * should disable SmartSpeed and enable Auto MasterSlave
1531 * resolution as hardware default. */
8fc897b0 1532 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2d7edb92 1533 /* Disable SmartSpeed */
8fc897b0
AK		 1534 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1535 &phy_data);
1536 if (ret_val)
1da177e4 1537 return ret_val;
2d7edb92 1538 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8fc897b0
AK		 1539 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1540 phy_data);
1541 if (ret_val)
1da177e4 1542 return ret_val;
2d7edb92
MC		 1543 /* Set auto Master/Slave resolution process */
1544 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1545 if (ret_val)
2d7edb92
MC		 1546 return ret_val;
1547 phy_data &= ~CR_1000T_MS_ENABLE;
1548 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1549 if (ret_val)
2d7edb92
MC		 1550 return ret_val;
1551 }
1da177e4 1552
2d7edb92 1553 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1554 if (ret_val)
2d7edb92 1555 return ret_val;
1da177e4 1556
2d7edb92
MC		 1557 /* load defaults for future use */
1558 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1559 ((phy_data & CR_1000T_MS_VALUE) ?
1560 e1000_ms_force_master :
1561 e1000_ms_force_slave) :
1562 e1000_ms_auto;
1da177e4 1563
2d7edb92
MC		 1564 switch (phy_ms_setting) {
1565 case e1000_ms_force_master:
1566 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1567 break;
1568 case e1000_ms_force_slave:
1569 phy_data |= CR_1000T_MS_ENABLE;
1570 phy_data &= ~(CR_1000T_MS_VALUE);
1571 break;
1572 case e1000_ms_auto:
1573 phy_data &= ~CR_1000T_MS_ENABLE;
1574 default:
1575 break;
1576 }
1577 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1578 if (ret_val)
2d7edb92 1579 return ret_val;
2b02893e 1580 }
1da177e4 1581
2b02893e 1582 return E1000_SUCCESS;
2d7edb92 1583}
1da177e4 1584
6418ecc6
JK		 1585/********************************************************************
1586* Copper link setup for e1000_phy_gg82563 series.
1587*
1588* hw - Struct containing variables accessed by shared code
1589*********************************************************************/
406874a7 1590static s32
6418ecc6
JK		 1591e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1592{
406874a7
JP		 1593 s32 ret_val;
1594 u16 phy_data;
1595 u32 reg_data;
6418ecc6
JK		 1596
1597 DEBUGFUNC("e1000_copper_link_ggp_setup");
1598
8fc897b0 1599 if (!hw->phy_reset_disable) {
76c224bc 1600
6418ecc6
JK		 1601 /* Enable CRS on TX for half-duplex operation. */
1602 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1603 &phy_data);
8fc897b0 1604 if (ret_val)
6418ecc6
JK		 1605 return ret_val;
1606
1607 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1608 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1609 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1610
1611 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1612 phy_data);
8fc897b0 1613 if (ret_val)
6418ecc6
JK		 1614 return ret_val;
1615
1616 /* Options:
1617 * MDI/MDI-X = 0 (default)
1618 * 0 - Auto for all speeds
1619 * 1 - MDI mode
1620 * 2 - MDI-X mode
1621 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1622 */
1623 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1624 if (ret_val)
6418ecc6
JK		 1625 return ret_val;
1626
1627 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1628
1629 switch (hw->mdix) {
1630 case 1:
1631 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1632 break;
1633 case 2:
1634 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1635 break;
1636 case 0:
1637 default:
1638 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1639 break;
1640 }
1641
1642 /* Options:
1643 * disable_polarity_correction = 0 (default)
1644 * Automatic Correction for Reversed Cable Polarity
1645 * 0 - Disabled
1646 * 1 - Enabled
1647 */
1648 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
8fc897b0 1649 if (hw->disable_polarity_correction == 1)
6418ecc6
JK		 1650 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1651 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1652
8fc897b0 1653 if (ret_val)
6418ecc6
JK		 1654 return ret_val;
1655
1656 /* SW Reset the PHY so all changes take effect */
1657 ret_val = e1000_phy_reset(hw);
1658 if (ret_val) {
1659 DEBUGOUT("Error Resetting the PHY\n");
1660 return ret_val;
1661 }
1662 } /* phy_reset_disable */
1663
1664 if (hw->mac_type == e1000_80003es2lan) {
1665 /* Bypass RX and TX FIFO's */
1666 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1667 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1668 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1669 if (ret_val)
1670 return ret_val;
1671
1672 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1673 if (ret_val)
1674 return ret_val;
1675
1676 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1677 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1678
1679 if (ret_val)
1680 return ret_val;
1681
1682 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1683 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1684 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1685
1686 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1687 &phy_data);
1688 if (ret_val)
1689 return ret_val;
1690
1691 /* Do not init these registers when the HW is in IAMT mode, since the
1692 * firmware will have already initialized them. We only initialize
1693 * them if the HW is not in IAMT mode.
1694 */
c3033b01 1695 if (!e1000_check_mng_mode(hw)) {
6418ecc6
JK		 1696 /* Enable Electrical Idle on the PHY */
1697 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1698 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1699 phy_data);
1700 if (ret_val)
1701 return ret_val;
1702
1703 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1704 &phy_data);
1705 if (ret_val)
1706 return ret_val;
1707
cd94dd0b 1708 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
6418ecc6
JK		 1709 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1710 phy_data);
8fc897b0 1711
6418ecc6
JK		 1712 if (ret_val)
1713 return ret_val;
1714 }
1715
1716 /* Workaround: Disable padding in Kumeran interface in the MAC
1717 * and in the PHY to avoid CRC errors.
1718 */
1719 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1720 &phy_data);
1721 if (ret_val)
1722 return ret_val;
1723 phy_data |= GG82563_ICR_DIS_PADDING;
1724 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1725 phy_data);
1726 if (ret_val)
1727 return ret_val;
1728 }
1729
1730 return E1000_SUCCESS;
1731}
1da177e4 1732
2d7edb92
MC		 1733/********************************************************************
1734* Copper link setup for e1000_phy_m88 series.
1735*
1736* hw - Struct containing variables accessed by shared code
1737*********************************************************************/
406874a7 1738static s32
2d7edb92
MC		 1739e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1740{
406874a7
JP		 1741 s32 ret_val;
1742 u16 phy_data;
1da177e4 1743
2d7edb92 1744 DEBUGFUNC("e1000_copper_link_mgp_setup");
1da177e4 1745
8fc897b0 1746 if (hw->phy_reset_disable)
2d7edb92 1747 return E1000_SUCCESS;
76c224bc 1748
2d7edb92
MC		 1749 /* Enable CRS on TX. This must be set for half-duplex operation. */
1750 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1751 if (ret_val)
2d7edb92 1752 return ret_val;
1da177e4 1753
2d7edb92 1754 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1da177e4 1755
2d7edb92
MC		 1756 /* Options:
1757 * MDI/MDI-X = 0 (default)
1758 * 0 - Auto for all speeds
1759 * 1 - MDI mode
1760 * 2 - MDI-X mode
1761 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1762 */
1763 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1da177e4 1764
2d7edb92
MC		 1765 switch (hw->mdix) {
1766 case 1:
1767 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1768 break;
1769 case 2:
1770 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1771 break;
1772 case 3:
1773 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1774 break;
1775 case 0:
1776 default:
1777 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1778 break;
1779 }
1780
1781 /* Options:
1782 * disable_polarity_correction = 0 (default)
1783 * Automatic Correction for Reversed Cable Polarity
1784 * 0 - Disabled
1785 * 1 - Enabled
1da177e4 1786 */
2d7edb92 1787 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
8fc897b0 1788 if (hw->disable_polarity_correction == 1)
2d7edb92 1789 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ee04022a
AK		 1790 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1791 if (ret_val)
2d7edb92
MC		 1792 return ret_val;
1793
2d7edb92 1794 if (hw->phy_revision < M88E1011_I_REV_4) {
ee04022a
AK		 1795 /* Force TX_CLK in the Extended PHY Specific Control Register
1796 * to 25MHz clock.
1797 */
1798 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1799 if (ret_val)
1800 return ret_val;
1801
1802 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1803
1804 if ((hw->phy_revision == E1000_REVISION_2) &&
1805 (hw->phy_id == M88E1111_I_PHY_ID)) {
1806 /* Vidalia Phy, set the downshift counter to 5x */
1807 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1808 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1809 ret_val = e1000_write_phy_reg(hw,
1810 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1811 if (ret_val)
1812 return ret_val;
1813 } else {
1814 /* Configure Master and Slave downshift values */
1815 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2d7edb92 1816 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ee04022a 1817 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2d7edb92 1818 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ee04022a
AK		 1819 ret_val = e1000_write_phy_reg(hw,
1820 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1821 if (ret_val)
1822 return ret_val;
1823 }
2d7edb92 1824 }
1da177e4 1825
2d7edb92
MC		 1826 /* SW Reset the PHY so all changes take effect */
1827 ret_val = e1000_phy_reset(hw);
8fc897b0 1828 if (ret_val) {
2d7edb92
MC		 1829 DEBUGOUT("Error Resetting the PHY\n");
1830 return ret_val;
1da177e4
LT		 1831 }
1832
2d7edb92 1833 return E1000_SUCCESS;
1da177e4
LT		 1834}
1835
2d7edb92
MC		 1836/********************************************************************
1837* Setup auto-negotiation and flow control advertisements,
1838* and then perform auto-negotiation.
1da177e4
LT		 1839*
1840* hw - Struct containing variables accessed by shared code
2d7edb92 1841*********************************************************************/
406874a7 1842static s32
2d7edb92 1843e1000_copper_link_autoneg(struct e1000_hw *hw)
1da177e4 1844{
406874a7
JP		 1845 s32 ret_val;
1846 u16 phy_data;
1da177e4 1847
2d7edb92 1848 DEBUGFUNC("e1000_copper_link_autoneg");
1da177e4 1849
2d7edb92
MC		 1850 /* Perform some bounds checking on the hw->autoneg_advertised
1851 * parameter. If this variable is zero, then set it to the default.
1852 */
1853 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1854
1855 /* If autoneg_advertised is zero, we assume it was not defaulted
1856 * by the calling code so we set to advertise full capability.
1857 */
8fc897b0 1858 if (hw->autoneg_advertised == 0)
2d7edb92
MC		 1859 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1860
cd94dd0b
AK		 1861 /* IFE phy only supports 10/100 */
1862 if (hw->phy_type == e1000_phy_ife)
1863 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1864
2d7edb92
MC		 1865 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1866 ret_val = e1000_phy_setup_autoneg(hw);
8fc897b0 1867 if (ret_val) {
2d7edb92
MC		 1868 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1869 return ret_val;
1870 }
1871 DEBUGOUT("Restarting Auto-Neg\n");
1872
1873 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1874 * the Auto Neg Restart bit in the PHY control register.
1875 */
1876 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 1877 if (ret_val)
1da177e4
LT		 1878 return ret_val;
1879
2d7edb92
MC		 1880 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1881 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 1882 if (ret_val)
1da177e4
LT		 1883 return ret_val;
1884
2d7edb92
MC		 1885 /* Does the user want to wait for Auto-Neg to complete here, or
1886 * check at a later time (for example, callback routine).
1887 */
8fc897b0 1888 if (hw->wait_autoneg_complete) {
2d7edb92 1889 ret_val = e1000_wait_autoneg(hw);
8fc897b0 1890 if (ret_val) {
2d7edb92
MC		 1891 DEBUGOUT("Error while waiting for autoneg to complete\n");
1892 return ret_val;
1893 }
1894 }
1895
c3033b01 1896 hw->get_link_status = true;
2d7edb92
MC		 1897
1898 return E1000_SUCCESS;
1899}
1900
2d7edb92
MC		 1901/******************************************************************************
1902* Config the MAC and the PHY after link is up.
1903* 1) Set up the MAC to the current PHY speed/duplex
1904* if we are on 82543. If we
1905* are on newer silicon, we only need to configure
1906* collision distance in the Transmit Control Register.
1907* 2) Set up flow control on the MAC to that established with
1908* the link partner.
76c224bc 1909* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2d7edb92
MC		 1910*
1911* hw - Struct containing variables accessed by shared code
1912******************************************************************************/
406874a7 1913static s32
2d7edb92
MC		 1914e1000_copper_link_postconfig(struct e1000_hw *hw)
1915{
406874a7 1916 s32 ret_val;
2d7edb92 1917 DEBUGFUNC("e1000_copper_link_postconfig");
76c224bc 1918
8fc897b0 1919 if (hw->mac_type >= e1000_82544) {
2d7edb92
MC		 1920 e1000_config_collision_dist(hw);
1921 } else {
1922 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 1923 if (ret_val) {
2d7edb92
MC		 1924 DEBUGOUT("Error configuring MAC to PHY settings\n");
1925 return ret_val;
1926 }
1927 }
1928 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 1929 if (ret_val) {
2d7edb92
MC		 1930 DEBUGOUT("Error Configuring Flow Control\n");
1931 return ret_val;
1932 }
1933
1934 /* Config DSP to improve Giga link quality */
8fc897b0 1935 if (hw->phy_type == e1000_phy_igp) {
c3033b01 1936 ret_val = e1000_config_dsp_after_link_change(hw, true);
8fc897b0 1937 if (ret_val) {
2d7edb92
MC		 1938 DEBUGOUT("Error Configuring DSP after link up\n");
1939 return ret_val;
1940 }
1941 }
76c224bc 1942
2d7edb92
MC		 1943 return E1000_SUCCESS;
1944}
1945
1946/******************************************************************************
1947* Detects which PHY is present and setup the speed and duplex
1948*
1949* hw - Struct containing variables accessed by shared code
1950******************************************************************************/
406874a7 1951static s32
2d7edb92
MC		 1952e1000_setup_copper_link(struct e1000_hw *hw)
1953{
406874a7
JP		 1954 s32 ret_val;
1955 u16 i;
1956 u16 phy_data;
1957 u16 reg_data;
2d7edb92
MC		 1958
1959 DEBUGFUNC("e1000_setup_copper_link");
1960
cd94dd0b
AK		 1961 switch (hw->mac_type) {
1962 case e1000_80003es2lan:
1963 case e1000_ich8lan:
1964 /* Set the mac to wait the maximum time between each
1965 * iteration and increase the max iterations when
1966 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1967 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1968 if (ret_val)
1969 return ret_val;
1970 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1971 if (ret_val)
1972 return ret_val;
1973 reg_data |= 0x3F;
1974 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1975 if (ret_val)
1976 return ret_val;
1977 default:
1978 break;
1979 }
1980
2d7edb92
MC		 1981 /* Check if it is a valid PHY and set PHY mode if necessary. */
1982 ret_val = e1000_copper_link_preconfig(hw);
8fc897b0 1983 if (ret_val)
2d7edb92
MC		 1984 return ret_val;
1985
6418ecc6
JK		 1986 switch (hw->mac_type) {
1987 case e1000_80003es2lan:
cd94dd0b
AK		 1988 /* Kumeran registers are written-only */
1989 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
6418ecc6
JK		 1990 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1991 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1992 reg_data);
1993 if (ret_val)
1994 return ret_val;
1995 break;
1996 default:
1997 break;
1998 }
1999
2d7edb92 2000 if (hw->phy_type == e1000_phy_igp ||
cd94dd0b 2001 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92
MC		 2002 hw->phy_type == e1000_phy_igp_2) {
2003 ret_val = e1000_copper_link_igp_setup(hw);
8fc897b0 2004 if (ret_val)
2d7edb92
MC		 2005 return ret_val;
2006 } else if (hw->phy_type == e1000_phy_m88) {
2007 ret_val = e1000_copper_link_mgp_setup(hw);
8fc897b0 2008 if (ret_val)
2d7edb92 2009 return ret_val;
6418ecc6
JK		 2010 } else if (hw->phy_type == e1000_phy_gg82563) {
2011 ret_val = e1000_copper_link_ggp_setup(hw);
8fc897b0 2012 if (ret_val)
6418ecc6 2013 return ret_val;
2d7edb92
MC		 2014 }
2015
8fc897b0 2016 if (hw->autoneg) {
76c224bc
AK		 2017 /* Setup autoneg and flow control advertisement
2018 * and perform autonegotiation */
2d7edb92 2019 ret_val = e1000_copper_link_autoneg(hw);
8fc897b0 2020 if (ret_val)
76c224bc 2021 return ret_val;
2d7edb92
MC		 2022 } else {
2023 /* PHY will be set to 10H, 10F, 100H,or 100F
2024 * depending on value from forced_speed_duplex. */
2025 DEBUGOUT("Forcing speed and duplex\n");
2026 ret_val = e1000_phy_force_speed_duplex(hw);
8fc897b0 2027 if (ret_val) {
2d7edb92
MC		 2028 DEBUGOUT("Error Forcing Speed and Duplex\n");
2029 return ret_val;
2030 }
2031 }
2032
2033 /* Check link status. Wait up to 100 microseconds for link to become
2034 * valid.
2035 */
8fc897b0 2036 for (i = 0; i < 10; i++) {
2d7edb92 2037 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2038 if (ret_val)
2d7edb92
MC		 2039 return ret_val;
2040 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2041 if (ret_val)
2d7edb92
MC		 2042 return ret_val;
2043
8fc897b0 2044 if (phy_data & MII_SR_LINK_STATUS) {
2d7edb92
MC		 2045 /* Config the MAC and PHY after link is up */
2046 ret_val = e1000_copper_link_postconfig(hw);
8fc897b0 2047 if (ret_val)
2d7edb92 2048 return ret_val;
76c224bc 2049
2d7edb92
MC		 2050 DEBUGOUT("Valid link established!!!\n");
2051 return E1000_SUCCESS;
2052 }
2053 udelay(10);
2054 }
2055
2056 DEBUGOUT("Unable to establish link!!!\n");
2057 return E1000_SUCCESS;
2058}
2059
6418ecc6
JK		 2060/******************************************************************************
2061* Configure the MAC-to-PHY interface for 10/100Mbps
2062*
2063* hw - Struct containing variables accessed by shared code
2064******************************************************************************/
406874a7
JP		 2065static s32
2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
6418ecc6 2067{
406874a7
JP		 2068 s32 ret_val = E1000_SUCCESS;
2069 u32 tipg;
2070 u16 reg_data;
6418ecc6
JK		 2071
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073
2074 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2075 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2076 reg_data);
2077 if (ret_val)
2078 return ret_val;
2079
2080 /* Configure Transmit Inter-Packet Gap */
2081 tipg = E1000_READ_REG(hw, TIPG);
2082 tipg &= ~E1000_TIPG_IPGT_MASK;
2083 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2084 E1000_WRITE_REG(hw, TIPG, tipg);
2085
cd94dd0b
AK		 2086 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2087
2088 if (ret_val)
2089 return ret_val;
2090
2091 if (duplex == HALF_DUPLEX)
2092 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2093 else
2094 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2095
2096 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2097
6418ecc6
JK		 2098 return ret_val;
2099}
2100
406874a7 2101static s32
6418ecc6
JK		 2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2103{
406874a7
JP		 2104 s32 ret_val = E1000_SUCCESS;
2105 u16 reg_data;
2106 u32 tipg;
6418ecc6
JK		 2107
2108 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2109
2110 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2111 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2112 reg_data);
2113 if (ret_val)
2114 return ret_val;
2115
2116 /* Configure Transmit Inter-Packet Gap */
2117 tipg = E1000_READ_REG(hw, TIPG);
2118 tipg &= ~E1000_TIPG_IPGT_MASK;
2119 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2120 E1000_WRITE_REG(hw, TIPG, tipg);
2121
cd94dd0b
AK		 2122 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2123
2124 if (ret_val)
2125 return ret_val;
2126
2127 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2128 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2129
6418ecc6
JK		 2130 return ret_val;
2131}
2132
2d7edb92
MC		 2133/******************************************************************************
2134* Configures PHY autoneg and flow control advertisement settings
2135*
2136* hw - Struct containing variables accessed by shared code
2137******************************************************************************/
406874a7 2138s32
2d7edb92
MC		 2139e1000_phy_setup_autoneg(struct e1000_hw *hw)
2140{
406874a7
JP		 2141 s32 ret_val;
2142 u16 mii_autoneg_adv_reg;
2143 u16 mii_1000t_ctrl_reg;
2d7edb92
MC		 2144
2145 DEBUGFUNC("e1000_phy_setup_autoneg");
2146
2147 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2148 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
8fc897b0 2149 if (ret_val)
2d7edb92
MC		 2150 return ret_val;
2151
cd94dd0b
AK		 2152 if (hw->phy_type != e1000_phy_ife) {
2153 /* Read the MII 1000Base-T Control Register (Address 9). */
2154 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2155 if (ret_val)
2156 return ret_val;
2157 } else
2158 mii_1000t_ctrl_reg=0;
2d7edb92
MC		 2159
2160 /* Need to parse both autoneg_advertised and fc and set up
2161 * the appropriate PHY registers. First we will parse for
1da177e4
LT		 2162 * autoneg_advertised software override. Since we can advertise
2163 * a plethora of combinations, we need to check each bit
2164 * individually.
2165 */
2166
2167 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2168 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2169 * the 1000Base-T Control Register (Address 9).
2170 */
2171 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2172 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2173
2174 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2175
2176 /* Do we want to advertise 10 Mb Half Duplex? */
8fc897b0 2177 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1da177e4
LT		 2178 DEBUGOUT("Advertise 10mb Half duplex\n");
2179 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2180 }
2181
2182 /* Do we want to advertise 10 Mb Full Duplex? */
8fc897b0 2183 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1da177e4
LT		 2184 DEBUGOUT("Advertise 10mb Full duplex\n");
2185 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2186 }
2187
2188 /* Do we want to advertise 100 Mb Half Duplex? */
8fc897b0 2189 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1da177e4
LT		 2190 DEBUGOUT("Advertise 100mb Half duplex\n");
2191 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2192 }
2193
2194 /* Do we want to advertise 100 Mb Full Duplex? */
8fc897b0 2195 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1da177e4
LT		 2196 DEBUGOUT("Advertise 100mb Full duplex\n");
2197 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2198 }
2199
2200 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
8fc897b0 2201 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1da177e4
LT		 2202 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2203 }
2204
2205 /* Do we want to advertise 1000 Mb Full Duplex? */
8fc897b0 2206 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1da177e4
LT		 2207 DEBUGOUT("Advertise 1000mb Full duplex\n");
2208 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
cd94dd0b
AK		 2209 if (hw->phy_type == e1000_phy_ife) {
2210 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2211 }
1da177e4
LT		 2212 }
2213
2214 /* Check for a software override of the flow control settings, and
2215 * setup the PHY advertisement registers accordingly. If
2216 * auto-negotiation is enabled, then software will have to set the
2217 * "PAUSE" bits to the correct value in the Auto-Negotiation
2218 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2219 *
2220 * The possible values of the "fc" parameter are:
2221 * 0: Flow control is completely disabled
2222 * 1: Rx flow control is enabled (we can receive pause frames
2223 * but not send pause frames).
2224 * 2: Tx flow control is enabled (we can send pause frames
2225 * but we do not support receiving pause frames).
2226 * 3: Both Rx and TX flow control (symmetric) are enabled.
2227 * other: No software override. The flow control configuration
2228 * in the EEPROM is used.
2229 */
2230 switch (hw->fc) {
11241b10 2231 case E1000_FC_NONE: /* 0 */
1da177e4
LT		 2232 /* Flow control (RX & TX) is completely disabled by a
2233 * software over-ride.
2234 */
2235 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2236 break;
11241b10 2237 case E1000_FC_RX_PAUSE: /* 1 */
1da177e4
LT		 2238 /* RX Flow control is enabled, and TX Flow control is
2239 * disabled, by a software over-ride.
2240 */
2241 /* Since there really isn't a way to advertise that we are
2242 * capable of RX Pause ONLY, we will advertise that we
2243 * support both symmetric and asymmetric RX PAUSE. Later
2244 * (in e1000_config_fc_after_link_up) we will disable the
2245 *hw's ability to send PAUSE frames.
2246 */
2247 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2248 break;
11241b10 2249 case E1000_FC_TX_PAUSE: /* 2 */
1da177e4
LT		 2250 /* TX Flow control is enabled, and RX Flow control is
2251 * disabled, by a software over-ride.
2252 */
2253 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2254 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2255 break;
11241b10 2256 case E1000_FC_FULL: /* 3 */
1da177e4
LT		 2257 /* Flow control (both RX and TX) is enabled by a software
2258 * over-ride.
2259 */
2260 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2261 break;
2262 default:
2263 DEBUGOUT("Flow control param set incorrectly\n");
2264 return -E1000_ERR_CONFIG;
2265 }
2266
2267 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
8fc897b0 2268 if (ret_val)
1da177e4
LT		 2269 return ret_val;
2270
2271 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2272
cd94dd0b
AK		 2273 if (hw->phy_type != e1000_phy_ife) {
2274 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2275 if (ret_val)
2276 return ret_val;
2277 }
1da177e4
LT		 2278
2279 return E1000_SUCCESS;
2280}
2281
2282/******************************************************************************
2283* Force PHY speed and duplex settings to hw->forced_speed_duplex
2284*
2285* hw - Struct containing variables accessed by shared code
2286******************************************************************************/
406874a7 2287static s32
1da177e4
LT		 2288e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289{
406874a7
JP		 2290 u32 ctrl;
2291 s32 ret_val;
2292 u16 mii_ctrl_reg;
2293 u16 mii_status_reg;
2294 u16 phy_data;
2295 u16 i;
1da177e4
LT		 2296
2297 DEBUGFUNC("e1000_phy_force_speed_duplex");
2298
2299 /* Turn off Flow control if we are forcing speed and duplex. */
11241b10 2300 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2301
2302 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2303
2304 /* Read the Device Control Register. */
2305 ctrl = E1000_READ_REG(hw, CTRL);
2306
2307 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2308 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2309 ctrl &= ~(DEVICE_SPEED_MASK);
2310
2311 /* Clear the Auto Speed Detect Enable bit. */
2312 ctrl &= ~E1000_CTRL_ASDE;
2313
2314 /* Read the MII Control Register. */
2315 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
8fc897b0 2316 if (ret_val)
1da177e4
LT		 2317 return ret_val;
2318
2319 /* We need to disable autoneg in order to force link and duplex. */
2320
2321 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2322
2323 /* Are we forcing Full or Half Duplex? */
8fc897b0
AK		 2324 if (hw->forced_speed_duplex == e1000_100_full ||
2325 hw->forced_speed_duplex == e1000_10_full) {
1da177e4
LT		 2326 /* We want to force full duplex so we SET the full duplex bits in the
2327 * Device and MII Control Registers.
2328 */
2329 ctrl |= E1000_CTRL_FD;
2330 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2331 DEBUGOUT("Full Duplex\n");
2332 } else {
2333 /* We want to force half duplex so we CLEAR the full duplex bits in
2334 * the Device and MII Control Registers.
2335 */
2336 ctrl &= ~E1000_CTRL_FD;
2337 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2338 DEBUGOUT("Half Duplex\n");
2339 }
2340
2341 /* Are we forcing 100Mbps??? */
8fc897b0 2342 if (hw->forced_speed_duplex == e1000_100_full ||
1da177e4
LT		 2343 hw->forced_speed_duplex == e1000_100_half) {
2344 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2345 ctrl |= E1000_CTRL_SPD_100;
2346 mii_ctrl_reg |= MII_CR_SPEED_100;
2347 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2348 DEBUGOUT("Forcing 100mb ");
2349 } else {
2350 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2351 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2352 mii_ctrl_reg |= MII_CR_SPEED_10;
2353 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2354 DEBUGOUT("Forcing 10mb ");
2355 }
2356
2357 e1000_config_collision_dist(hw);
2358
2359 /* Write the configured values back to the Device Control Reg. */
2360 E1000_WRITE_REG(hw, CTRL, ctrl);
2361
6418ecc6
JK		 2362 if ((hw->phy_type == e1000_phy_m88) ||
2363 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4 2364 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2365 if (ret_val)
1da177e4
LT		 2366 return ret_val;
2367
2368 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2369 * forced whenever speed are duplex are forced.
2370 */
2371 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2372 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2373 if (ret_val)
1da177e4
LT		 2374 return ret_val;
2375
2376 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2377
2378 /* Need to reset the PHY or these changes will be ignored */
2379 mii_ctrl_reg |= MII_CR_RESET;
90fb5135 2380
cd94dd0b
AK		 2381 /* Disable MDI-X support for 10/100 */
2382 } else if (hw->phy_type == e1000_phy_ife) {
2383 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2384 if (ret_val)
2385 return ret_val;
2386
2387 phy_data &= ~IFE_PMC_AUTO_MDIX;
2388 phy_data &= ~IFE_PMC_FORCE_MDIX;
2389
2390 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2391 if (ret_val)
2392 return ret_val;
90fb5135 2393
1da177e4
LT		 2394 } else {
2395 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2396 * forced whenever speed or duplex are forced.
2397 */
2398 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
8fc897b0 2399 if (ret_val)
1da177e4
LT		 2400 return ret_val;
2401
2402 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2403 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2404
2405 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 2406 if (ret_val)
1da177e4
LT		 2407 return ret_val;
2408 }
2409
2410 /* Write back the modified PHY MII control register. */
2411 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
8fc897b0 2412 if (ret_val)
1da177e4
LT		 2413 return ret_val;
2414
2415 udelay(1);
2416
2417 /* The wait_autoneg_complete flag may be a little misleading here.
2418 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2419 * But we do want to delay for a period while forcing only so we
2420 * don't generate false No Link messages. So we will wait here
2421 * only if the user has set wait_autoneg_complete to 1, which is
2422 * the default.
2423 */
8fc897b0 2424 if (hw->wait_autoneg_complete) {
1da177e4
LT		 2425 /* We will wait for autoneg to complete. */
2426 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2427 mii_status_reg = 0;
2428
2429 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 2430 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 2431 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2432 * to be set.
2433 */
2434 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2435 if (ret_val)
1da177e4
LT		 2436 return ret_val;
2437
2438 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2439 if (ret_val)
1da177e4
LT		 2440 return ret_val;
2441
8fc897b0 2442 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2443 msleep(100);
1da177e4 2444 }
8fc897b0 2445 if ((i == 0) &&
6418ecc6
JK		 2446 ((hw->phy_type == e1000_phy_m88) ||
2447 (hw->phy_type == e1000_phy_gg82563))) {
1da177e4
LT		 2448 /* We didn't get link. Reset the DSP and wait again for link. */
2449 ret_val = e1000_phy_reset_dsp(hw);
8fc897b0 2450 if (ret_val) {
1da177e4
LT		 2451 DEBUGOUT("Error Resetting PHY DSP\n");
2452 return ret_val;
2453 }
2454 }
2455 /* This loop will early-out if the link condition has been met. */
8fc897b0
AK		 2456 for (i = PHY_FORCE_TIME; i > 0; i--) {
2457 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2458 msleep(100);
1da177e4
LT		 2459 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2460 * to be set.
2461 */
2462 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2463 if (ret_val)
1da177e4
LT		 2464 return ret_val;
2465
2466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2467 if (ret_val)
1da177e4
LT		 2468 return ret_val;
2469 }
2470 }
2471
2472 if (hw->phy_type == e1000_phy_m88) {
2473 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2474 * Extended PHY Specific Control Register to 25MHz clock. This value
2475 * defaults back to a 2.5MHz clock when the PHY is reset.
2476 */
2477 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2478 if (ret_val)
1da177e4
LT		 2479 return ret_val;
2480
2481 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2482 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
8fc897b0 2483 if (ret_val)
1da177e4
LT		 2484 return ret_val;
2485
2486 /* In addition, because of the s/w reset above, we need to enable CRS on
2487 * TX. This must be set for both full and half duplex operation.
2488 */
2489 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2490 if (ret_val)
1da177e4
LT		 2491 return ret_val;
2492
2493 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2495 if (ret_val)
1da177e4
LT		 2496 return ret_val;
2497
8fc897b0
AK		 2498 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2499 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2500 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4 2501 ret_val = e1000_polarity_reversal_workaround(hw);
8fc897b0 2502 if (ret_val)
1da177e4
LT		 2503 return ret_val;
2504 }
6418ecc6
JK		 2505 } else if (hw->phy_type == e1000_phy_gg82563) {
2506 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2507 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2508 * we're not in a forced 10/duplex configuration. */
2509 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2510 if (ret_val)
2511 return ret_val;
2512
2513 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2514 if ((hw->forced_speed_duplex == e1000_10_full) ||
2515 (hw->forced_speed_duplex == e1000_10_half))
2516 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2517 else
2518 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2519
2520 /* Also due to the reset, we need to enable CRS on Tx. */
2521 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2522
2523 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2524 if (ret_val)
2525 return ret_val;
1da177e4
LT		 2526 }
2527 return E1000_SUCCESS;
2528}
2529
2530/******************************************************************************
2531* Sets the collision distance in the Transmit Control register
2532*
2533* hw - Struct containing variables accessed by shared code
2534*
2535* Link should have been established previously. Reads the speed and duplex
2536* information from the Device Status register.
2537******************************************************************************/
2538void
2539e1000_config_collision_dist(struct e1000_hw *hw)
2540{
406874a7 2541 u32 tctl, coll_dist;
1da177e4
LT		 2542
2543 DEBUGFUNC("e1000_config_collision_dist");
2544
0fadb059
JK		 2545 if (hw->mac_type < e1000_82543)
2546 coll_dist = E1000_COLLISION_DISTANCE_82542;
2547 else
2548 coll_dist = E1000_COLLISION_DISTANCE;
2549
1da177e4
LT		 2550 tctl = E1000_READ_REG(hw, TCTL);
2551
2552 tctl &= ~E1000_TCTL_COLD;
0fadb059 2553 tctl |= coll_dist << E1000_COLD_SHIFT;
1da177e4
LT		 2554
2555 E1000_WRITE_REG(hw, TCTL, tctl);
2556 E1000_WRITE_FLUSH(hw);
2557}
2558
2559/******************************************************************************
2560* Sets MAC speed and duplex settings to reflect the those in the PHY
2561*
2562* hw - Struct containing variables accessed by shared code
2563* mii_reg - data to write to the MII control register
2564*
2565* The contents of the PHY register containing the needed information need to
2566* be passed in.
2567******************************************************************************/
406874a7 2568static s32
1da177e4
LT		 2569e1000_config_mac_to_phy(struct e1000_hw *hw)
2570{
406874a7
JP		 2571 u32 ctrl;
2572 s32 ret_val;
2573 u16 phy_data;
1da177e4
LT		 2574
2575 DEBUGFUNC("e1000_config_mac_to_phy");
2576
76c224bc 2577 /* 82544 or newer MAC, Auto Speed Detection takes care of
2d7edb92
MC		 2578 * MAC speed/duplex configuration.*/
2579 if (hw->mac_type >= e1000_82544)
2580 return E1000_SUCCESS;
2581
1da177e4
LT		 2582 /* Read the Device Control Register and set the bits to Force Speed
2583 * and Duplex.
2584 */
2585 ctrl = E1000_READ_REG(hw, CTRL);
2586 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2587 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2588
2589 /* Set up duplex in the Device Control and Transmit Control
2590 * registers depending on negotiated values.
2591 */
2d7edb92 2592 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 2593 if (ret_val)
2d7edb92 2594 return ret_val;
1da177e4 2595
8fc897b0 2596 if (phy_data & M88E1000_PSSR_DPLX)
2d7edb92 2597 ctrl |= E1000_CTRL_FD;
76c224bc 2598 else
2d7edb92 2599 ctrl &= ~E1000_CTRL_FD;
1da177e4 2600
2d7edb92 2601 e1000_config_collision_dist(hw);
1da177e4 2602
2d7edb92
MC		 2603 /* Set up speed in the Device Control register depending on
2604 * negotiated values.
2605 */
8fc897b0 2606 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2d7edb92 2607 ctrl |= E1000_CTRL_SPD_1000;
8fc897b0 2608 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2d7edb92 2609 ctrl |= E1000_CTRL_SPD_100;
1da177e4 2610
1da177e4
LT		 2611 /* Write the configured values back to the Device Control Reg. */
2612 E1000_WRITE_REG(hw, CTRL, ctrl);
2613 return E1000_SUCCESS;
2614}
2615
2616/******************************************************************************
2617 * Forces the MAC's flow control settings.
2618 *
2619 * hw - Struct containing variables accessed by shared code
2620 *
2621 * Sets the TFCE and RFCE bits in the device control register to reflect
2622 * the adapter settings. TFCE and RFCE need to be explicitly set by
2623 * software when a Copper PHY is used because autonegotiation is managed
2624 * by the PHY rather than the MAC. Software must also configure these
2625 * bits when link is forced on a fiber connection.
2626 *****************************************************************************/
406874a7 2627s32
1da177e4
LT		 2628e1000_force_mac_fc(struct e1000_hw *hw)
2629{
406874a7 2630 u32 ctrl;
1da177e4
LT		 2631
2632 DEBUGFUNC("e1000_force_mac_fc");
2633
2634 /* Get the current configuration of the Device Control Register */
2635 ctrl = E1000_READ_REG(hw, CTRL);
2636
2637 /* Because we didn't get link via the internal auto-negotiation
2638 * mechanism (we either forced link or we got link via PHY
2639 * auto-neg), we have to manually enable/disable transmit an
2640 * receive flow control.
2641 *
2642 * The "Case" statement below enables/disable flow control
2643 * according to the "hw->fc" parameter.
2644 *
2645 * The possible values of the "fc" parameter are:
2646 * 0: Flow control is completely disabled
2647 * 1: Rx flow control is enabled (we can receive pause
2648 * frames but not send pause frames).
2649 * 2: Tx flow control is enabled (we can send pause frames
2650 * frames but we do not receive pause frames).
2651 * 3: Both Rx and TX flow control (symmetric) is enabled.
2652 * other: No other values should be possible at this point.
2653 */
2654
2655 switch (hw->fc) {
11241b10 2656 case E1000_FC_NONE:
1da177e4
LT		 2657 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2658 break;
11241b10 2659 case E1000_FC_RX_PAUSE:
1da177e4
LT		 2660 ctrl &= (~E1000_CTRL_TFCE);
2661 ctrl |= E1000_CTRL_RFCE;
2662 break;
11241b10 2663 case E1000_FC_TX_PAUSE:
1da177e4
LT		 2664 ctrl &= (~E1000_CTRL_RFCE);
2665 ctrl |= E1000_CTRL_TFCE;
2666 break;
11241b10 2667 case E1000_FC_FULL:
1da177e4
LT		 2668 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2669 break;
2670 default:
2671 DEBUGOUT("Flow control param set incorrectly\n");
2672 return -E1000_ERR_CONFIG;
2673 }
2674
2675 /* Disable TX Flow Control for 82542 (rev 2.0) */
8fc897b0 2676 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2677 ctrl &= (~E1000_CTRL_TFCE);
2678
2679 E1000_WRITE_REG(hw, CTRL, ctrl);
2680 return E1000_SUCCESS;
2681}
2682
2683/******************************************************************************
2684 * Configures flow control settings after link is established
2685 *
2686 * hw - Struct containing variables accessed by shared code
2687 *
2688 * Should be called immediately after a valid link has been established.
2689 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2690 * and autonegotiation is enabled, the MAC flow control settings will be set
2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2693 *****************************************************************************/
406874a7 2694static s32
1da177e4
LT		 2695e1000_config_fc_after_link_up(struct e1000_hw *hw)
2696{
406874a7
JP		 2697 s32 ret_val;
2698 u16 mii_status_reg;
2699 u16 mii_nway_adv_reg;
2700 u16 mii_nway_lp_ability_reg;
2701 u16 speed;
2702 u16 duplex;
1da177e4
LT		 2703
2704 DEBUGFUNC("e1000_config_fc_after_link_up");
2705
2706 /* Check for the case where we have fiber media and auto-neg failed
2707 * so we had to force link. In this case, we need to force the
2708 * configuration of the MAC to match the "fc" parameter.
2709 */
8fc897b0
AK		 2710 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2711 ((hw->media_type == e1000_media_type_internal_serdes) &&
2712 (hw->autoneg_failed)) ||
2713 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1da177e4 2714 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2715 if (ret_val) {
1da177e4
LT		 2716 DEBUGOUT("Error forcing flow control settings\n");
2717 return ret_val;
2718 }
2719 }
2720
2721 /* Check for the case where we have copper media and auto-neg is
2722 * enabled. In this case, we need to check and see if Auto-Neg
2723 * has completed, and if so, how the PHY and link partner has
2724 * flow control configured.
2725 */
8fc897b0 2726 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1da177e4
LT		 2727 /* Read the MII Status Register and check to see if AutoNeg
2728 * has completed. We read this twice because this reg has
2729 * some "sticky" (latched) bits.
2730 */
2731 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2732 if (ret_val)
1da177e4
LT		 2733 return ret_val;
2734 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2735 if (ret_val)
1da177e4
LT		 2736 return ret_val;
2737
8fc897b0 2738 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 2739 /* The AutoNeg process has completed, so we now need to
2740 * read both the Auto Negotiation Advertisement Register
2741 * (Address 4) and the Auto_Negotiation Base Page Ability
2742 * Register (Address 5) to determine how flow control was
2743 * negotiated.
2744 */
2745 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2746 &mii_nway_adv_reg);
8fc897b0 2747 if (ret_val)
1da177e4
LT		 2748 return ret_val;
2749 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2750 &mii_nway_lp_ability_reg);
8fc897b0 2751 if (ret_val)
1da177e4
LT		 2752 return ret_val;
2753
2754 /* Two bits in the Auto Negotiation Advertisement Register
2755 * (Address 4) and two bits in the Auto Negotiation Base
2756 * Page Ability Register (Address 5) determine flow control
2757 * for both the PHY and the link partner. The following
2758 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2759 * 1999, describes these PAUSE resolution bits and how flow
2760 * control is determined based upon these settings.
2761 * NOTE: DC = Don't Care
2762 *
2763 * LOCAL DEVICE | LINK PARTNER
2764 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2765 *-------|---------|-------|---------|--------------------
11241b10
JK		 2766 * 0 | 0 | DC | DC | E1000_FC_NONE
2767 * 0 | 1 | 0 | DC | E1000_FC_NONE
2768 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2769 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2770 * 1 | 0 | 0 | DC | E1000_FC_NONE
2771 * 1 | DC | 1 | DC | E1000_FC_FULL
2772 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2773 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2774 *
2775 */
2776 /* Are both PAUSE bits set to 1? If so, this implies
2777 * Symmetric Flow Control is enabled at both ends. The
2778 * ASM_DIR bits are irrelevant per the spec.
2779 *
2780 * For Symmetric Flow Control:
2781 *
2782 * LOCAL DEVICE | LINK PARTNER
2783 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2784 *-------|---------|-------|---------|--------------------
11241b10 2785 * 1 | DC | 1 | DC | E1000_FC_FULL
1da177e4
LT		 2786 *
2787 */
8fc897b0
AK		 2788 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2789 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1da177e4
LT		 2790 /* Now we need to check if the user selected RX ONLY
2791 * of pause frames. In this case, we had to advertise
2792 * FULL flow control because we could not advertise RX
2793 * ONLY. Hence, we must now check to see if we need to
2794 * turn OFF the TRANSMISSION of PAUSE frames.
2795 */
11241b10
JK		 2796 if (hw->original_fc == E1000_FC_FULL) {
2797 hw->fc = E1000_FC_FULL;
a42a507c 2798 DEBUGOUT("Flow Control = FULL.\n");
1da177e4 2799 } else {
11241b10 2800 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2801 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2802 }
2803 }
2804 /* For receiving PAUSE frames ONLY.
2805 *
2806 * LOCAL DEVICE | LINK PARTNER
2807 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2808 *-------|---------|-------|---------|--------------------
11241b10 2809 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
1da177e4
LT		 2810 *
2811 */
8fc897b0
AK		 2812 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2813 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2814 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2815 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2816 hw->fc = E1000_FC_TX_PAUSE;
a42a507c 2817 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1da177e4
LT		 2818 }
2819 /* For transmitting PAUSE frames ONLY.
2820 *
2821 * LOCAL DEVICE | LINK PARTNER
2822 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2823 *-------|---------|-------|---------|--------------------
11241b10 2824 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2825 *
2826 */
8fc897b0
AK		 2827 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2828 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2829 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2830 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2831 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2832 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2833 }
2834 /* Per the IEEE spec, at this point flow control should be
2835 * disabled. However, we want to consider that we could
2836 * be connected to a legacy switch that doesn't advertise
2837 * desired flow control, but can be forced on the link
2838 * partner. So if we advertised no flow control, that is
2839 * what we will resolve to. If we advertised some kind of
2840 * receive capability (Rx Pause Only or Full Flow Control)
2841 * and the link partner advertised none, we will configure
2842 * ourselves to enable Rx Flow Control only. We can do
2843 * this safely for two reasons: If the link partner really
2844 * didn't want flow control enabled, and we enable Rx, no
2845 * harm done since we won't be receiving any PAUSE frames
2846 * anyway. If the intent on the link partner was to have
2847 * flow control enabled, then by us enabling RX only, we
2848 * can at least receive pause frames and process them.
2849 * This is a good idea because in most cases, since we are
2850 * predominantly a server NIC, more times than not we will
2851 * be asked to delay transmission of packets than asking
2852 * our link partner to pause transmission of frames.
2853 */
11241b10
JK		 2854 else if ((hw->original_fc == E1000_FC_NONE ||
2855 hw->original_fc == E1000_FC_TX_PAUSE) ||
8fc897b0 2856 hw->fc_strict_ieee) {
11241b10 2857 hw->fc = E1000_FC_NONE;
a42a507c 2858 DEBUGOUT("Flow Control = NONE.\n");
1da177e4 2859 } else {
11241b10 2860 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2861 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2862 }
2863
2864 /* Now we need to do one last check... If we auto-
2865 * negotiated to HALF DUPLEX, flow control should not be
2866 * enabled per IEEE 802.3 spec.
2867 */
2868 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 2869 if (ret_val) {
1da177e4
LT		 2870 DEBUGOUT("Error getting link speed and duplex\n");
2871 return ret_val;
2872 }
2873
8fc897b0 2874 if (duplex == HALF_DUPLEX)
11241b10 2875 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2876
2877 /* Now we call a subroutine to actually force the MAC
2878 * controller to use the correct flow control settings.
2879 */
2880 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2881 if (ret_val) {
1da177e4
LT		 2882 DEBUGOUT("Error forcing flow control settings\n");
2883 return ret_val;
2884 }
2885 } else {
a42a507c 2886 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1da177e4
LT		 2887 }
2888 }
2889 return E1000_SUCCESS;
2890}
2891
2892/******************************************************************************
2893 * Checks to see if the link status of the hardware has changed.
2894 *
2895 * hw - Struct containing variables accessed by shared code
2896 *
2897 * Called by any function that needs to check the link status of the adapter.
2898 *****************************************************************************/
406874a7 2899s32
1da177e4
LT		 2900e1000_check_for_link(struct e1000_hw *hw)
2901{
406874a7
JP		 2902 u32 rxcw = 0;
2903 u32 ctrl;
2904 u32 status;
2905 u32 rctl;
2906 u32 icr;
2907 u32 signal = 0;
2908 s32 ret_val;
2909 u16 phy_data;
1da177e4
LT		 2910
2911 DEBUGFUNC("e1000_check_for_link");
2912
2913 ctrl = E1000_READ_REG(hw, CTRL);
2914 status = E1000_READ_REG(hw, STATUS);
2915
2916 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2917 * set when the optics detect a signal. On older adapters, it will be
2918 * cleared when there is a signal. This applies to fiber media only.
2919 */
8fc897b0
AK		 2920 if ((hw->media_type == e1000_media_type_fiber) ||
2921 (hw->media_type == e1000_media_type_internal_serdes)) {
1da177e4
LT		 2922 rxcw = E1000_READ_REG(hw, RXCW);
2923
8fc897b0 2924 if (hw->media_type == e1000_media_type_fiber) {
1da177e4 2925 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
8fc897b0 2926 if (status & E1000_STATUS_LU)
c3033b01 2927 hw->get_link_status = false;
1da177e4
LT		 2928 }
2929 }
2930
2931 /* If we have a copper PHY then we only want to go out to the PHY
2932 * registers to see if Auto-Neg has completed and/or if our link
2933 * status has changed. The get_link_status flag will be set if we
2934 * receive a Link Status Change interrupt or we have Rx Sequence
2935 * Errors.
2936 */
8fc897b0 2937 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1da177e4
LT		 2938 /* First we want to see if the MII Status Register reports
2939 * link. If so, then we want to get the current speed/duplex
2940 * of the PHY.
2941 * Read the register twice since the link bit is sticky.
2942 */
2943 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2944 if (ret_val)
1da177e4
LT		 2945 return ret_val;
2946 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2947 if (ret_val)
1da177e4
LT		 2948 return ret_val;
2949
8fc897b0 2950 if (phy_data & MII_SR_LINK_STATUS) {
c3033b01 2951 hw->get_link_status = false;
1da177e4
LT		 2952 /* Check if there was DownShift, must be checked immediately after
2953 * link-up */
2954 e1000_check_downshift(hw);
2955
2956 /* If we are on 82544 or 82543 silicon and speed/duplex
2957 * are forced to 10H or 10F, then we will implement the polarity
2958 * reversal workaround. We disable interrupts first, and upon
2959 * returning, place the devices interrupt state to its previous
2960 * value except for the link status change interrupt which will
2961 * happen due to the execution of this workaround.
2962 */
2963
8fc897b0
AK		 2964 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2965 (!hw->autoneg) &&
2966 (hw->forced_speed_duplex == e1000_10_full ||
2967 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4
LT		 2968 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2969 ret_val = e1000_polarity_reversal_workaround(hw);
2970 icr = E1000_READ_REG(hw, ICR);
2971 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2972 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2973 }
2974
2975 } else {
2976 /* No link detected */
c3033b01 2977 e1000_config_dsp_after_link_change(hw, false);
1da177e4
LT		 2978 return 0;
2979 }
2980
2981 /* If we are forcing speed/duplex, then we simply return since
2982 * we have already determined whether we have link or not.
2983 */
8fc897b0 2984 if (!hw->autoneg) return -E1000_ERR_CONFIG;
1da177e4
LT		 2985
2986 /* optimize the dsp settings for the igp phy */
c3033b01 2987 e1000_config_dsp_after_link_change(hw, true);
1da177e4
LT		 2988
2989 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2990 * have Si on board that is 82544 or newer, Auto
2991 * Speed Detection takes care of MAC speed/duplex
2992 * configuration. So we only need to configure Collision
2993 * Distance in the MAC. Otherwise, we need to force
2994 * speed/duplex on the MAC to the current PHY speed/duplex
2995 * settings.
2996 */
8fc897b0 2997 if (hw->mac_type >= e1000_82544)
1da177e4
LT		 2998 e1000_config_collision_dist(hw);
2999 else {
3000 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 3001 if (ret_val) {
1da177e4
LT		 3002 DEBUGOUT("Error configuring MAC to PHY settings\n");
3003 return ret_val;
3004 }
3005 }
3006
3007 /* Configure Flow Control now that Auto-Neg has completed. First, we
3008 * need to restore the desired flow control settings because we may
3009 * have had to re-autoneg with a different link partner.
3010 */
3011 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3012 if (ret_val) {
1da177e4
LT		 3013 DEBUGOUT("Error configuring flow control\n");
3014 return ret_val;
3015 }
3016
3017 /* At this point we know that we are on copper and we have
3018 * auto-negotiated link. These are conditions for checking the link
3019 * partner capability register. We use the link speed to determine if
3020 * TBI compatibility needs to be turned on or off. If the link is not
3021 * at gigabit speed, then TBI compatibility is not needed. If we are
3022 * at gigabit speed, we turn on TBI compatibility.
3023 */
8fc897b0 3024 if (hw->tbi_compatibility_en) {
406874a7 3025 u16 speed, duplex;
592600a0
AK		 3026 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3027 if (ret_val) {
3028 DEBUGOUT("Error getting link speed and duplex\n");
3029 return ret_val;
3030 }
3031 if (speed != SPEED_1000) {
1da177e4
LT		 3032 /* If link speed is not set to gigabit speed, we do not need
3033 * to enable TBI compatibility.
3034 */
8fc897b0 3035 if (hw->tbi_compatibility_on) {
1da177e4
LT		 3036 /* If we previously were in the mode, turn it off. */
3037 rctl = E1000_READ_REG(hw, RCTL);
3038 rctl &= ~E1000_RCTL_SBP;
3039 E1000_WRITE_REG(hw, RCTL, rctl);
c3033b01 3040 hw->tbi_compatibility_on = false;
1da177e4
LT		 3041 }
3042 } else {
3043 /* If TBI compatibility is was previously off, turn it on. For
3044 * compatibility with a TBI link partner, we will store bad
3045 * packets. Some frames have an additional byte on the end and
3046 * will look like CRC errors to to the hardware.
3047 */
8fc897b0 3048 if (!hw->tbi_compatibility_on) {
c3033b01 3049 hw->tbi_compatibility_on = true;
1da177e4
LT		 3050 rctl = E1000_READ_REG(hw, RCTL);
3051 rctl |= E1000_RCTL_SBP;
3052 E1000_WRITE_REG(hw, RCTL, rctl);
3053 }
3054 }
3055 }
3056 }
3057 /* If we don't have link (auto-negotiation failed or link partner cannot
3058 * auto-negotiate), the cable is plugged in (we have signal), and our
3059 * link partner is not trying to auto-negotiate with us (we are receiving
3060 * idles or data), we need to force link up. We also need to give
3061 * auto-negotiation time to complete, in case the cable was just plugged
3062 * in. The autoneg_failed flag does this.
3063 */
8fc897b0 3064 else if ((((hw->media_type == e1000_media_type_fiber) &&
1da177e4 3065 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
8fc897b0
AK		 3066 (hw->media_type == e1000_media_type_internal_serdes)) &&
3067 (!(status & E1000_STATUS_LU)) &&
3068 (!(rxcw & E1000_RXCW_C))) {
3069 if (hw->autoneg_failed == 0) {
1da177e4
LT		 3070 hw->autoneg_failed = 1;
3071 return 0;
3072 }
a42a507c 3073 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1da177e4
LT		 3074
3075 /* Disable auto-negotiation in the TXCW register */
3076 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3077
3078 /* Force link-up and also force full-duplex. */
3079 ctrl = E1000_READ_REG(hw, CTRL);
3080 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3081 E1000_WRITE_REG(hw, CTRL, ctrl);
3082
3083 /* Configure Flow Control after forcing link up. */
3084 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3085 if (ret_val) {
1da177e4
LT		 3086 DEBUGOUT("Error configuring flow control\n");
3087 return ret_val;
3088 }
3089 }
3090 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3091 * auto-negotiation in the TXCW register and disable forced link in the
3092 * Device Control register in an attempt to auto-negotiate with our link
3093 * partner.
3094 */
8fc897b0
AK		 3095 else if (((hw->media_type == e1000_media_type_fiber) ||
3096 (hw->media_type == e1000_media_type_internal_serdes)) &&
3097 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
a42a507c 3098 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1da177e4
LT		 3099 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3100 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3101
c3033b01 3102 hw->serdes_link_down = false;
1da177e4
LT		 3103 }
3104 /* If we force link for non-auto-negotiation switch, check link status
3105 * based on MAC synchronization for internal serdes media type.
3106 */
8fc897b0
AK		 3107 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3108 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3109 /* SYNCH bit and IV bit are sticky. */
3110 udelay(10);
8fc897b0
AK		 3111 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3112 if (!(rxcw & E1000_RXCW_IV)) {
c3033b01 3113 hw->serdes_link_down = false;
1da177e4
LT		 3114 DEBUGOUT("SERDES: Link is up.\n");
3115 }
3116 } else {
c3033b01 3117 hw->serdes_link_down = true;
1da177e4
LT		 3118 DEBUGOUT("SERDES: Link is down.\n");
3119 }
3120 }
8fc897b0
AK		 3121 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3122 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3123 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3124 }
3125 return E1000_SUCCESS;
3126}
3127
3128/******************************************************************************
3129 * Detects the current speed and duplex settings of the hardware.
3130 *
3131 * hw - Struct containing variables accessed by shared code
3132 * speed - Speed of the connection
3133 * duplex - Duplex setting of the connection
3134 *****************************************************************************/
406874a7 3135s32
1da177e4 3136e1000_get_speed_and_duplex(struct e1000_hw *hw,
406874a7
JP		 3137 u16 *speed,
3138 u16 *duplex)
1da177e4 3139{
406874a7
JP		 3140 u32 status;
3141 s32 ret_val;
3142 u16 phy_data;
1da177e4
LT		 3143
3144 DEBUGFUNC("e1000_get_speed_and_duplex");
3145
8fc897b0 3146 if (hw->mac_type >= e1000_82543) {
1da177e4 3147 status = E1000_READ_REG(hw, STATUS);
8fc897b0 3148 if (status & E1000_STATUS_SPEED_1000) {
1da177e4
LT		 3149 *speed = SPEED_1000;
3150 DEBUGOUT("1000 Mbs, ");
8fc897b0 3151 } else if (status & E1000_STATUS_SPEED_100) {
1da177e4
LT		 3152 *speed = SPEED_100;
3153 DEBUGOUT("100 Mbs, ");
3154 } else {
3155 *speed = SPEED_10;
3156 DEBUGOUT("10 Mbs, ");
3157 }
3158
8fc897b0 3159 if (status & E1000_STATUS_FD) {
1da177e4 3160 *duplex = FULL_DUPLEX;
a42a507c 3161 DEBUGOUT("Full Duplex\n");
1da177e4
LT		 3162 } else {
3163 *duplex = HALF_DUPLEX;
a42a507c 3164 DEBUGOUT(" Half Duplex\n");
1da177e4
LT		 3165 }
3166 } else {
a42a507c 3167 DEBUGOUT("1000 Mbs, Full Duplex\n");
1da177e4
LT		 3168 *speed = SPEED_1000;
3169 *duplex = FULL_DUPLEX;
3170 }
3171
3172 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3173 * if it is operating at half duplex. Here we set the duplex settings to
3174 * match the duplex in the link partner's capabilities.
3175 */
8fc897b0 3176 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
1da177e4 3177 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
8fc897b0 3178 if (ret_val)
1da177e4
LT		 3179 return ret_val;
3180
8fc897b0 3181 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
1da177e4
LT		 3182 *duplex = HALF_DUPLEX;
3183 else {
3184 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
8fc897b0 3185 if (ret_val)
1da177e4 3186 return ret_val;
8fc897b0 3187 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
1da177e4
LT		 3188 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3189 *duplex = HALF_DUPLEX;
3190 }
3191 }
3192
76c224bc 3193 if ((hw->mac_type == e1000_80003es2lan) &&
6418ecc6
JK		 3194 (hw->media_type == e1000_media_type_copper)) {
3195 if (*speed == SPEED_1000)
3196 ret_val = e1000_configure_kmrn_for_1000(hw);
3197 else
cd94dd0b
AK		 3198 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3199 if (ret_val)
3200 return ret_val;
3201 }
3202
3203 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3204 ret_val = e1000_kumeran_lock_loss_workaround(hw);
6418ecc6
JK		 3205 if (ret_val)
3206 return ret_val;
3207 }
3208
1da177e4
LT		 3209 return E1000_SUCCESS;
3210}
3211
3212/******************************************************************************
3213* Blocks until autoneg completes or times out (~4.5 seconds)
3214*
3215* hw - Struct containing variables accessed by shared code
3216******************************************************************************/
406874a7 3217static s32
1da177e4
LT		 3218e1000_wait_autoneg(struct e1000_hw *hw)
3219{
406874a7
JP		 3220 s32 ret_val;
3221 u16 i;
3222 u16 phy_data;
1da177e4
LT		 3223
3224 DEBUGFUNC("e1000_wait_autoneg");
3225 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3226
3227 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 3228 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1da177e4
LT		 3229 /* Read the MII Status Register and wait for Auto-Neg
3230 * Complete bit to be set.
3231 */
3232 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3233 if (ret_val)
1da177e4
LT		 3234 return ret_val;
3235 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3236 if (ret_val)
1da177e4 3237 return ret_val;
8fc897b0 3238 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 3239 return E1000_SUCCESS;
3240 }
f8ec4733 3241 msleep(100);
1da177e4
LT		 3242 }
3243 return E1000_SUCCESS;
3244}
3245
3246/******************************************************************************
3247* Raises the Management Data Clock
3248*
3249* hw - Struct containing variables accessed by shared code
3250* ctrl - Device control register's current value
3251******************************************************************************/
3252static void
3253e1000_raise_mdi_clk(struct e1000_hw *hw,
406874a7 3254 u32 *ctrl)
1da177e4
LT		 3255{
3256 /* Raise the clock input to the Management Data Clock (by setting the MDC
3257 * bit), and then delay 10 microseconds.
3258 */
3259 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3260 E1000_WRITE_FLUSH(hw);
3261 udelay(10);
3262}
3263
3264/******************************************************************************
3265* Lowers the Management Data Clock
3266*
3267* hw - Struct containing variables accessed by shared code
3268* ctrl - Device control register's current value
3269******************************************************************************/
3270static void
3271e1000_lower_mdi_clk(struct e1000_hw *hw,
406874a7 3272 u32 *ctrl)
1da177e4
LT		 3273{
3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3275 * bit), and then delay 10 microseconds.
3276 */
3277 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3278 E1000_WRITE_FLUSH(hw);
3279 udelay(10);
3280}
3281
3282/******************************************************************************
3283* Shifts data bits out to the PHY
3284*
3285* hw - Struct containing variables accessed by shared code
3286* data - Data to send out to the PHY
3287* count - Number of bits to shift out
3288*
3289* Bits are shifted out in MSB to LSB order.
3290******************************************************************************/
3291static void
3292e1000_shift_out_mdi_bits(struct e1000_hw *hw,
406874a7
JP		 3293 u32 data,
3294 u16 count)
1da177e4 3295{
406874a7
JP		 3296 u32 ctrl;
3297 u32 mask;
1da177e4
LT		 3298
3299 /* We need to shift "count" number of bits out to the PHY. So, the value
3300 * in the "data" parameter will be shifted out to the PHY one bit at a
3301 * time. In order to do this, "data" must be broken down into bits.
3302 */
3303 mask = 0x01;
3304 mask <<= (count - 1);
3305
3306 ctrl = E1000_READ_REG(hw, CTRL);
3307
3308 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3309 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3310
8fc897b0 3311 while (mask) {
1da177e4
LT		 3312 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3313 * then raising and lowering the Management Data Clock. A "0" is
3314 * shifted out to the PHY by setting the MDIO bit to "0" and then
3315 * raising and lowering the clock.
3316 */
8fc897b0
AK		 3317 if (data & mask)
3318 ctrl |= E1000_CTRL_MDIO;
3319 else
3320 ctrl &= ~E1000_CTRL_MDIO;
1da177e4
LT		 3321
3322 E1000_WRITE_REG(hw, CTRL, ctrl);
3323 E1000_WRITE_FLUSH(hw);
3324
3325 udelay(10);
3326
3327 e1000_raise_mdi_clk(hw, &ctrl);
3328 e1000_lower_mdi_clk(hw, &ctrl);
3329
3330 mask = mask >> 1;
3331 }
3332}
3333
3334/******************************************************************************
3335* Shifts data bits in from the PHY
3336*
3337* hw - Struct containing variables accessed by shared code
3338*
3339* Bits are shifted in in MSB to LSB order.
3340******************************************************************************/
406874a7 3341static u16
1da177e4
LT		 3342e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3343{
406874a7
JP		 3344 u32 ctrl;
3345 u16 data = 0;
3346 u8 i;
1da177e4
LT		 3347
3348 /* In order to read a register from the PHY, we need to shift in a total
3349 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3350 * to avoid contention on the MDIO pin when a read operation is performed.
3351 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3352 * by raising the input to the Management Data Clock (setting the MDC bit),
3353 * and then reading the value of the MDIO bit.
3354 */
3355 ctrl = E1000_READ_REG(hw, CTRL);
3356
3357 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3358 ctrl &= ~E1000_CTRL_MDIO_DIR;
3359 ctrl &= ~E1000_CTRL_MDIO;
3360
3361 E1000_WRITE_REG(hw, CTRL, ctrl);
3362 E1000_WRITE_FLUSH(hw);
3363
3364 /* Raise and Lower the clock before reading in the data. This accounts for
3365 * the turnaround bits. The first clock occurred when we clocked out the
3366 * last bit of the Register Address.
3367 */
3368 e1000_raise_mdi_clk(hw, &ctrl);
3369 e1000_lower_mdi_clk(hw, &ctrl);
3370
8fc897b0 3371 for (data = 0, i = 0; i < 16; i++) {
1da177e4
LT		 3372 data = data << 1;
3373 e1000_raise_mdi_clk(hw, &ctrl);
3374 ctrl = E1000_READ_REG(hw, CTRL);
3375 /* Check to see if we shifted in a "1". */
8fc897b0
AK		 3376 if (ctrl & E1000_CTRL_MDIO)
3377 data |= 1;
1da177e4
LT		 3378 e1000_lower_mdi_clk(hw, &ctrl);
3379 }
3380
3381 e1000_raise_mdi_clk(hw, &ctrl);
3382 e1000_lower_mdi_clk(hw, &ctrl);
3383
3384 return data;
3385}
3386
406874a7
JP		 3387static s32
3388e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
6418ecc6 3389{
406874a7
JP		 3390 u32 swfw_sync = 0;
3391 u32 swmask = mask;
3392 u32 fwmask = mask << 16;
3393 s32 timeout = 200;
6418ecc6
JK		 3394
3395 DEBUGFUNC("e1000_swfw_sync_acquire");
3396
cd94dd0b
AK		 3397 if (hw->swfwhw_semaphore_present)
3398 return e1000_get_software_flag(hw);
3399
6418ecc6
JK		 3400 if (!hw->swfw_sync_present)
3401 return e1000_get_hw_eeprom_semaphore(hw);
3402
8fc897b0 3403 while (timeout) {
6418ecc6
JK		 3404 if (e1000_get_hw_eeprom_semaphore(hw))
3405 return -E1000_ERR_SWFW_SYNC;
3406
3407 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3408 if (!(swfw_sync & (fwmask | swmask))) {
3409 break;
3410 }
3411
3412 /* firmware currently using resource (fwmask) */
3413 /* or other software thread currently using resource (swmask) */
3414 e1000_put_hw_eeprom_semaphore(hw);
f8ec4733 3415 mdelay(5);
6418ecc6
JK		 3416 timeout--;
3417 }
3418
3419 if (!timeout) {
3420 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3421 return -E1000_ERR_SWFW_SYNC;
3422 }
3423
3424 swfw_sync |= swmask;
3425 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3426
3427 e1000_put_hw_eeprom_semaphore(hw);
3428 return E1000_SUCCESS;
3429}
3430
e4c780b1 3431static void
406874a7 3432e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
6418ecc6 3433{
406874a7
JP		 3434 u32 swfw_sync;
3435 u32 swmask = mask;
6418ecc6
JK		 3436
3437 DEBUGFUNC("e1000_swfw_sync_release");
3438
cd94dd0b
AK		 3439 if (hw->swfwhw_semaphore_present) {
3440 e1000_release_software_flag(hw);
3441 return;
3442 }
3443
6418ecc6
JK		 3444 if (!hw->swfw_sync_present) {
3445 e1000_put_hw_eeprom_semaphore(hw);
3446 return;
3447 }
3448
3449 /* if (e1000_get_hw_eeprom_semaphore(hw))
3450 * return -E1000_ERR_SWFW_SYNC; */
3451 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3452 /* empty */
3453
3454 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3455 swfw_sync &= ~swmask;
3456 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3457
3458 e1000_put_hw_eeprom_semaphore(hw);
3459}
3460
1da177e4
LT		 3461/*****************************************************************************
3462* Reads the value from a PHY register, if the value is on a specific non zero
3463* page, sets the page first.
3464* hw - Struct containing variables accessed by shared code
3465* reg_addr - address of the PHY register to read
3466******************************************************************************/
406874a7 3467s32
1da177e4 3468e1000_read_phy_reg(struct e1000_hw *hw,
406874a7
JP		 3469 u32 reg_addr,
3470 u16 *phy_data)
1da177e4 3471{
406874a7
JP		 3472 u32 ret_val;
3473 u16 swfw;
1da177e4
LT		 3474
3475 DEBUGFUNC("e1000_read_phy_reg");
3476
6418ecc6
JK		 3477 if ((hw->mac_type == e1000_80003es2lan) &&
3478 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3479 swfw = E1000_SWFW_PHY1_SM;
3480 } else {
3481 swfw = E1000_SWFW_PHY0_SM;
3482 }
3483 if (e1000_swfw_sync_acquire(hw, swfw))
3484 return -E1000_ERR_SWFW_SYNC;
3485
cd94dd0b
AK		 3486 if ((hw->phy_type == e1000_phy_igp ||
3487 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3488 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3490 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
406874a7 3491 (u16)reg_addr);
8fc897b0 3492 if (ret_val) {
6418ecc6 3493 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3494 return ret_val;
3495 }
6418ecc6
JK		 3496 } else if (hw->phy_type == e1000_phy_gg82563) {
3497 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3498 (hw->mac_type == e1000_80003es2lan)) {
3499 /* Select Configuration Page */
3500 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3501 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
406874a7 3502 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
6418ecc6
JK		 3503 } else {
3504 /* Use Alternative Page Select register to access
3505 * registers 30 and 31
3506 */
3507 ret_val = e1000_write_phy_reg_ex(hw,
3508 GG82563_PHY_PAGE_SELECT_ALT,
406874a7 3509 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
6418ecc6
JK		 3510 }
3511
3512 if (ret_val) {
3513 e1000_swfw_sync_release(hw, swfw);
3514 return ret_val;
3515 }
3516 }
1da177e4
LT		 3517 }
3518
3519 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3520 phy_data);
3521
6418ecc6 3522 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3523 return ret_val;
3524}
3525
406874a7
JP		 3526static s32
3527e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3528 u16 *phy_data)
1da177e4 3529{
406874a7
JP		 3530 u32 i;
3531 u32 mdic = 0;
3532 const u32 phy_addr = 1;
1da177e4
LT		 3533
3534 DEBUGFUNC("e1000_read_phy_reg_ex");
3535
8fc897b0 3536 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3537 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3538 return -E1000_ERR_PARAM;
3539 }
3540
8fc897b0 3541 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3542 /* Set up Op-code, Phy Address, and register address in the MDI
3543 * Control register. The MAC will take care of interfacing with the
3544 * PHY to retrieve the desired data.
3545 */
3546 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3547 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3548 (E1000_MDIC_OP_READ));
3549
3550 E1000_WRITE_REG(hw, MDIC, mdic);
3551
3552 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3553 for (i = 0; i < 64; i++) {
1da177e4
LT		 3554 udelay(50);
3555 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3556 if (mdic & E1000_MDIC_READY) break;
1da177e4 3557 }
8fc897b0 3558 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3559 DEBUGOUT("MDI Read did not complete\n");
3560 return -E1000_ERR_PHY;
3561 }
8fc897b0 3562 if (mdic & E1000_MDIC_ERROR) {
1da177e4
LT		 3563 DEBUGOUT("MDI Error\n");
3564 return -E1000_ERR_PHY;
3565 }
406874a7 3566 *phy_data = (u16) mdic;
1da177e4
LT		 3567 } else {
3568 /* We must first send a preamble through the MDIO pin to signal the
3569 * beginning of an MII instruction. This is done by sending 32
3570 * consecutive "1" bits.
3571 */
3572 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3573
3574 /* Now combine the next few fields that are required for a read
3575 * operation. We use this method instead of calling the
3576 * e1000_shift_out_mdi_bits routine five different times. The format of
3577 * a MII read instruction consists of a shift out of 14 bits and is
3578 * defined as follows:
3579 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3580 * followed by a shift in of 18 bits. This first two bits shifted in
3581 * are TurnAround bits used to avoid contention on the MDIO pin when a
3582 * READ operation is performed. These two bits are thrown away
3583 * followed by a shift in of 16 bits which contains the desired data.
3584 */
3585 mdic = ((reg_addr) | (phy_addr << 5) |
3586 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3587
3588 e1000_shift_out_mdi_bits(hw, mdic, 14);
3589
3590 /* Now that we've shifted out the read command to the MII, we need to
3591 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3592 * register address.
3593 */
3594 *phy_data = e1000_shift_in_mdi_bits(hw);
3595 }
3596 return E1000_SUCCESS;
3597}
3598
3599/******************************************************************************
3600* Writes a value to a PHY register
3601*
3602* hw - Struct containing variables accessed by shared code
3603* reg_addr - address of the PHY register to write
3604* data - data to write to the PHY
3605******************************************************************************/
406874a7
JP		 3606s32
3607e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3608 u16 phy_data)
1da177e4 3609{
406874a7
JP		 3610 u32 ret_val;
3611 u16 swfw;
1da177e4
LT		 3612
3613 DEBUGFUNC("e1000_write_phy_reg");
3614
6418ecc6
JK		 3615 if ((hw->mac_type == e1000_80003es2lan) &&
3616 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3617 swfw = E1000_SWFW_PHY1_SM;
3618 } else {
3619 swfw = E1000_SWFW_PHY0_SM;
3620 }
3621 if (e1000_swfw_sync_acquire(hw, swfw))
3622 return -E1000_ERR_SWFW_SYNC;
3623
cd94dd0b
AK		 3624 if ((hw->phy_type == e1000_phy_igp ||
3625 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3626 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3627 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3628 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
406874a7 3629 (u16)reg_addr);
8fc897b0 3630 if (ret_val) {
6418ecc6 3631 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3632 return ret_val;
3633 }
6418ecc6
JK		 3634 } else if (hw->phy_type == e1000_phy_gg82563) {
3635 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3636 (hw->mac_type == e1000_80003es2lan)) {
3637 /* Select Configuration Page */
3638 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3639 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
406874a7 3640 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
6418ecc6
JK		 3641 } else {
3642 /* Use Alternative Page Select register to access
3643 * registers 30 and 31
3644 */
3645 ret_val = e1000_write_phy_reg_ex(hw,
3646 GG82563_PHY_PAGE_SELECT_ALT,
406874a7 3647 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
6418ecc6
JK		 3648 }
3649
3650 if (ret_val) {
3651 e1000_swfw_sync_release(hw, swfw);
3652 return ret_val;
3653 }
3654 }
1da177e4
LT		 3655 }
3656
3657 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3658 phy_data);
3659
6418ecc6 3660 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3661 return ret_val;
3662}
3663
406874a7
JP		 3664static s32
3665e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3666 u16 phy_data)
1da177e4 3667{
406874a7
JP		 3668 u32 i;
3669 u32 mdic = 0;
3670 const u32 phy_addr = 1;
1da177e4
LT		 3671
3672 DEBUGFUNC("e1000_write_phy_reg_ex");
3673
8fc897b0 3674 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3675 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3676 return -E1000_ERR_PARAM;
3677 }
3678
8fc897b0 3679 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3680 /* Set up Op-code, Phy Address, register address, and data intended
3681 * for the PHY register in the MDI Control register. The MAC will take
3682 * care of interfacing with the PHY to send the desired data.
3683 */
406874a7 3684 mdic = (((u32) phy_data) |
1da177e4
LT		 3685 (reg_addr << E1000_MDIC_REG_SHIFT) |
3686 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3687 (E1000_MDIC_OP_WRITE));
3688
3689 E1000_WRITE_REG(hw, MDIC, mdic);
3690
3691 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3692 for (i = 0; i < 641; i++) {
1da177e4
LT		 3693 udelay(5);
3694 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3695 if (mdic & E1000_MDIC_READY) break;
1da177e4 3696 }
8fc897b0 3697 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3698 DEBUGOUT("MDI Write did not complete\n");
3699 return -E1000_ERR_PHY;
3700 }
3701 } else {
3702 /* We'll need to use the SW defined pins to shift the write command
3703 * out to the PHY. We first send a preamble to the PHY to signal the
3704 * beginning of the MII instruction. This is done by sending 32
3705 * consecutive "1" bits.
3706 */
3707 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3708
3709 /* Now combine the remaining required fields that will indicate a
3710 * write operation. We use this method instead of calling the
3711 * e1000_shift_out_mdi_bits routine for each field in the command. The
3712 * format of a MII write instruction is as follows:
3713 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3714 */
3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3717 mdic <<= 16;
406874a7 3718 mdic |= (u32) phy_data;
1da177e4
LT		 3719
3720 e1000_shift_out_mdi_bits(hw, mdic, 32);
3721 }
3722
3723 return E1000_SUCCESS;
3724}
3725
406874a7 3726static s32
6418ecc6 3727e1000_read_kmrn_reg(struct e1000_hw *hw,
406874a7
JP		 3728 u32 reg_addr,
3729 u16 *data)
6418ecc6 3730{
406874a7
JP		 3731 u32 reg_val;
3732 u16 swfw;
6418ecc6
JK		 3733 DEBUGFUNC("e1000_read_kmrn_reg");
3734
3735 if ((hw->mac_type == e1000_80003es2lan) &&
3736 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3737 swfw = E1000_SWFW_PHY1_SM;
3738 } else {
3739 swfw = E1000_SWFW_PHY0_SM;
3740 }
3741 if (e1000_swfw_sync_acquire(hw, swfw))
3742 return -E1000_ERR_SWFW_SYNC;
3743
3744 /* Write register address */
3745 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3746 E1000_KUMCTRLSTA_OFFSET) |
3747 E1000_KUMCTRLSTA_REN;
3748 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3749 udelay(2);
3750
3751 /* Read the data returned */
3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
406874a7 3753 *data = (u16)reg_val;
6418ecc6
JK		 3754
3755 e1000_swfw_sync_release(hw, swfw);
3756 return E1000_SUCCESS;
3757}
3758
406874a7 3759static s32
6418ecc6 3760e1000_write_kmrn_reg(struct e1000_hw *hw,
406874a7
JP		 3761 u32 reg_addr,
3762 u16 data)
6418ecc6 3763{
406874a7
JP		 3764 u32 reg_val;
3765 u16 swfw;
6418ecc6
JK		 3766 DEBUGFUNC("e1000_write_kmrn_reg");
3767
3768 if ((hw->mac_type == e1000_80003es2lan) &&
3769 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3770 swfw = E1000_SWFW_PHY1_SM;
3771 } else {
3772 swfw = E1000_SWFW_PHY0_SM;
3773 }
3774 if (e1000_swfw_sync_acquire(hw, swfw))
3775 return -E1000_ERR_SWFW_SYNC;
3776
3777 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3778 E1000_KUMCTRLSTA_OFFSET) | data;
3779 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3780 udelay(2);
3781
3782 e1000_swfw_sync_release(hw, swfw);
3783 return E1000_SUCCESS;
3784}
2d7edb92 3785
1da177e4
LT		 3786/******************************************************************************
3787* Returns the PHY to the power-on reset state
3788*
3789* hw - Struct containing variables accessed by shared code
3790******************************************************************************/
406874a7 3791s32
1da177e4
LT		 3792e1000_phy_hw_reset(struct e1000_hw *hw)
3793{
406874a7
JP		 3794 u32 ctrl, ctrl_ext;
3795 u32 led_ctrl;
3796 s32 ret_val;
3797 u16 swfw;
1da177e4
LT		 3798
3799 DEBUGFUNC("e1000_phy_hw_reset");
3800
2d7edb92
MC		 3801 /* In the case of the phy reset being blocked, it's not an error, we
3802 * simply return success without performing the reset. */
3803 ret_val = e1000_check_phy_reset_block(hw);
3804 if (ret_val)
3805 return E1000_SUCCESS;
3806
1da177e4
LT		 3807 DEBUGOUT("Resetting Phy...\n");
3808
8fc897b0 3809 if (hw->mac_type > e1000_82543) {
6418ecc6
JK		 3810 if ((hw->mac_type == e1000_80003es2lan) &&
3811 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3812 swfw = E1000_SWFW_PHY1_SM;
3813 } else {
3814 swfw = E1000_SWFW_PHY0_SM;
3815 }
3816 if (e1000_swfw_sync_acquire(hw, swfw)) {
2a88c173 3817 DEBUGOUT("Unable to acquire swfw sync\n");
6418ecc6
JK		 3818 return -E1000_ERR_SWFW_SYNC;
3819 }
1da177e4
LT		 3820 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3821 * bit. Then, take it out of reset.
76c224bc 3822 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
fd803241 3823 * and deassert. For e1000_82571 hardware and later, we instead delay
0f15a8fa 3824 * for 50us between and 10ms after the deassertion.
1da177e4
LT		 3825 */
3826 ctrl = E1000_READ_REG(hw, CTRL);
3827 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3828 E1000_WRITE_FLUSH(hw);
76c224bc
AK		 3829
3830 if (hw->mac_type < e1000_82571)
f8ec4733 3831 msleep(10);
b55ccb35
JK		 3832 else
3833 udelay(100);
76c224bc 3834
1da177e4
LT		 3835 E1000_WRITE_REG(hw, CTRL, ctrl);
3836 E1000_WRITE_FLUSH(hw);
76c224bc 3837
fd803241 3838 if (hw->mac_type >= e1000_82571)
f8ec4733 3839 mdelay(10);
35574764 3840
6418ecc6 3841 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3842 } else {
3843 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3844 * bit to put the PHY into reset. Then, take it out of reset.
3845 */
3846 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3847 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3848 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3849 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3850 E1000_WRITE_FLUSH(hw);
f8ec4733 3851 msleep(10);
1da177e4
LT		 3852 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3853 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3854 E1000_WRITE_FLUSH(hw);
3855 }
3856 udelay(150);
3857
8fc897b0 3858 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 3859 /* Configure activity LED after PHY reset */
3860 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3861 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3862 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3863 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3864 }
2d7edb92
MC		 3865
3866 /* Wait for FW to finish PHY configuration. */
3867 ret_val = e1000_get_phy_cfg_done(hw);
8fc897b0
AK		 3868 if (ret_val != E1000_SUCCESS)
3869 return ret_val;
6418ecc6 3870 e1000_release_software_semaphore(hw);
2d7edb92 3871
8fc897b0
AK		 3872 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3873 ret_val = e1000_init_lcd_from_nvm(hw);
3874
2d7edb92 3875 return ret_val;
1da177e4
LT		 3876}
3877
3878/******************************************************************************
3879* Resets the PHY
3880*
3881* hw - Struct containing variables accessed by shared code
3882*
0779bf2d 3883* Sets bit 15 of the MII Control register
1da177e4 3884******************************************************************************/
406874a7 3885s32
1da177e4
LT		 3886e1000_phy_reset(struct e1000_hw *hw)
3887{
406874a7
JP		 3888 s32 ret_val;
3889 u16 phy_data;
1da177e4
LT		 3890
3891 DEBUGFUNC("e1000_phy_reset");
3892
2d7edb92
MC		 3893 /* In the case of the phy reset being blocked, it's not an error, we
3894 * simply return success without performing the reset. */
3895 ret_val = e1000_check_phy_reset_block(hw);
3896 if (ret_val)
3897 return E1000_SUCCESS;
3898
2a88c173
JK		 3899 switch (hw->phy_type) {
3900 case e1000_phy_igp:
3901 case e1000_phy_igp_2:
3902 case e1000_phy_igp_3:
3903 case e1000_phy_ife:
2d7edb92 3904 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 3905 if (ret_val)
2d7edb92
MC		 3906 return ret_val;
3907 break;
3908 default:
1da177e4 3909 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 3910 if (ret_val)
1da177e4
LT		 3911 return ret_val;
3912
3913 phy_data |= MII_CR_RESET;
3914 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 3915 if (ret_val)
1da177e4
LT		 3916 return ret_val;
3917
3918 udelay(1);
2d7edb92
MC		 3919 break;
3920 }
1da177e4 3921
8fc897b0 3922 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
1da177e4
LT		 3923 e1000_phy_init_script(hw);
3924
3925 return E1000_SUCCESS;
3926}
3927
d37ea5d5
AK		 3928/******************************************************************************
3929* Work-around for 82566 power-down: on D3 entry-
3930* 1) disable gigabit link
3931* 2) write VR power-down enable
3932* 3) read it back
3933* if successful continue, else issue LCD reset and repeat
3934*
3935* hw - struct containing variables accessed by shared code
3936******************************************************************************/
3937void
3938e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3939{
406874a7
JP		 3940 s32 reg;
3941 u16 phy_data;
3942 s32 retry = 0;
d37ea5d5
AK		 3943
3944 DEBUGFUNC("e1000_phy_powerdown_workaround");
3945
3946 if (hw->phy_type != e1000_phy_igp_3)
3947 return;
3948
3949 do {
3950 /* Disable link */
3951 reg = E1000_READ_REG(hw, PHY_CTRL);
3952 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3953 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3954
070f6ffb 3955 /* Write VR power-down enable - bits 9:8 should be 10b */
d37ea5d5 3956 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
070f6ffb
JK		 3957 phy_data |= (1 << 9);
3958 phy_data &= ~(1 << 8);
3959 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
d37ea5d5
AK		 3960
3961 /* Read it back and test */
3962 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
070f6ffb 3963 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
d37ea5d5
AK		 3964 break;
3965
3966 /* Issue PHY reset and repeat at most one more time */
3967 reg = E1000_READ_REG(hw, CTRL);
3968 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3969 retry++;
3970 } while (retry);
3971
3972 return;
3973
3974}
3975
3976/******************************************************************************
3977* Work-around for 82566 Kumeran PCS lock loss:
3978* On link status change (i.e. PCI reset, speed change) and link is up and
3979* speed is gigabit-
3980* 0) if workaround is optionally disabled do nothing
3981* 1) wait 1ms for Kumeran link to come up
3982* 2) check Kumeran Diagnostic register PCS lock loss bit
3983* 3) if not set the link is locked (all is good), otherwise...
3984* 4) reset the PHY
3985* 5) repeat up to 10 times
3986* Note: this is only called for IGP3 copper when speed is 1gb.
3987*
3988* hw - struct containing variables accessed by shared code
3989******************************************************************************/
406874a7 3990static s32
d37ea5d5
AK		 3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3992{
406874a7
JP		 3993 s32 ret_val;
3994 s32 reg;
3995 s32 cnt;
3996 u16 phy_data;
d37ea5d5
AK		 3997
3998 if (hw->kmrn_lock_loss_workaround_disabled)
3999 return E1000_SUCCESS;
4000
8fc897b0
AK		 4001 /* Make sure link is up before proceeding. If not just return.
4002 * Attempting this while link is negotiating fouled up link
d37ea5d5
AK		 4003 * stability */
4004 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4005 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4006
4007 if (phy_data & MII_SR_LINK_STATUS) {
4008 for (cnt = 0; cnt < 10; cnt++) {
4009 /* read once to clear */
4010 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4011 if (ret_val)
4012 return ret_val;
4013 /* and again to get new status */
4014 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4015 if (ret_val)
4016 return ret_val;
4017
4018 /* check for PCS lock */
4019 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4020 return E1000_SUCCESS;
4021
4022 /* Issue PHY reset */
4023 e1000_phy_hw_reset(hw);
f8ec4733 4024 mdelay(5);
d37ea5d5
AK		 4025 }
4026 /* Disable GigE link negotiation */
4027 reg = E1000_READ_REG(hw, PHY_CTRL);
4028 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4029 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4030
4031 /* unable to acquire PCS lock */
4032 return E1000_ERR_PHY;
4033 }
4034
4035 return E1000_SUCCESS;
4036}
4037
1da177e4
LT		 4038/******************************************************************************
4039* Probes the expected PHY address for known PHY IDs
4040*
4041* hw - Struct containing variables accessed by shared code
4042******************************************************************************/
406874a7 4043static s32
1da177e4
LT		 4044e1000_detect_gig_phy(struct e1000_hw *hw)
4045{
406874a7
JP		 4046 s32 phy_init_status, ret_val;
4047 u16 phy_id_high, phy_id_low;
c3033b01 4048 bool match = false;
1da177e4
LT		 4049
4050 DEBUGFUNC("e1000_detect_gig_phy");
4051
2a88c173
JK		 4052 if (hw->phy_id != 0)
4053 return E1000_SUCCESS;
4054
868d5309
MC		 4055 /* The 82571 firmware may still be configuring the PHY. In this
4056 * case, we cannot access the PHY until the configuration is done. So
4057 * we explicitly set the PHY values. */
cd94dd0b
AK		 4058 if (hw->mac_type == e1000_82571 ||
4059 hw->mac_type == e1000_82572) {
868d5309
MC		 4060 hw->phy_id = IGP01E1000_I_PHY_ID;
4061 hw->phy_type = e1000_phy_igp_2;
4062 return E1000_SUCCESS;
4063 }
4064
6418ecc6
JK		 4065 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4066 * around that forces PHY page 0 to be set or the reads fail. The rest of
4067 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4068 * So for ESB-2 we need to have this set so our reads won't fail. If the
4069 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4070 * this out as well. */
4071 if (hw->mac_type == e1000_80003es2lan)
4072 hw->phy_type = e1000_phy_gg82563;
4073
1da177e4
LT		 4074 /* Read the PHY ID Registers to identify which PHY is onboard. */
4075 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
cd94dd0b 4076 if (ret_val)
1da177e4
LT		 4077 return ret_val;
4078
406874a7 4079 hw->phy_id = (u32) (phy_id_high << 16);
1da177e4
LT		 4080 udelay(20);
4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
8fc897b0 4082 if (ret_val)
1da177e4
LT		 4083 return ret_val;
4084
406874a7
JP		 4085 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
4086 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
1da177e4 4087
8fc897b0 4088 switch (hw->mac_type) {
1da177e4 4089 case e1000_82543:
c3033b01 4090 if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
1da177e4
LT		 4091 break;
4092 case e1000_82544:
c3033b01 4093 if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
1da177e4
LT		 4094 break;
4095 case e1000_82540:
4096 case e1000_82545:
4097 case e1000_82545_rev_3:
4098 case e1000_82546:
4099 case e1000_82546_rev_3:
c3033b01 4100 if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
1da177e4
LT		 4101 break;
4102 case e1000_82541:
4103 case e1000_82541_rev_2:
4104 case e1000_82547:
4105 case e1000_82547_rev_2:
c3033b01 4106 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
1da177e4 4107 break;
2d7edb92 4108 case e1000_82573:
c3033b01 4109 if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
2d7edb92 4110 break;
6418ecc6 4111 case e1000_80003es2lan:
c3033b01 4112 if (hw->phy_id == GG82563_E_PHY_ID) match = true;
6418ecc6 4113 break;
cd94dd0b 4114 case e1000_ich8lan:
c3033b01
JP		 4115 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
4116 if (hw->phy_id == IFE_E_PHY_ID) match = true;
4117 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
4118 if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
cd94dd0b 4119 break;
1da177e4
LT		 4120 default:
4121 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4122 return -E1000_ERR_CONFIG;
4123 }
4124 phy_init_status = e1000_set_phy_type(hw);
4125
4126 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4127 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4128 return E1000_SUCCESS;
4129 }
4130 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4131 return -E1000_ERR_PHY;
4132}
4133
4134/******************************************************************************
4135* Resets the PHY's DSP
4136*
4137* hw - Struct containing variables accessed by shared code
4138******************************************************************************/
406874a7 4139static s32
1da177e4
LT		 4140e1000_phy_reset_dsp(struct e1000_hw *hw)
4141{
406874a7 4142 s32 ret_val;
1da177e4
LT		 4143 DEBUGFUNC("e1000_phy_reset_dsp");
4144
4145 do {
6418ecc6
JK		 4146 if (hw->phy_type != e1000_phy_gg82563) {
4147 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
8fc897b0 4148 if (ret_val) break;
6418ecc6 4149 }
1da177e4 4150 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
8fc897b0 4151 if (ret_val) break;
1da177e4 4152 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
8fc897b0 4153 if (ret_val) break;
1da177e4 4154 ret_val = E1000_SUCCESS;
8fc897b0 4155 } while (0);
1da177e4
LT		 4156
4157 return ret_val;
4158}
4159
4160/******************************************************************************
4161* Get PHY information from various PHY registers for igp PHY only.
4162*
4163* hw - Struct containing variables accessed by shared code
4164* phy_info - PHY information structure
4165******************************************************************************/
406874a7 4166static s32
1da177e4
LT		 4167e1000_phy_igp_get_info(struct e1000_hw *hw,
4168 struct e1000_phy_info *phy_info)
4169{
406874a7
JP		 4170 s32 ret_val;
4171 u16 phy_data, min_length, max_length, average;
70c6f30a 4172 e1000_rev_polarity polarity;
1da177e4
LT		 4173
4174 DEBUGFUNC("e1000_phy_igp_get_info");
4175
4176 /* The downshift status is checked only once, after link is established,
4177 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4178 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4179
4180 /* IGP01E1000 does not need to support it. */
4181 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4182
4183 /* IGP01E1000 always correct polarity reversal */
4184 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4185
4186 /* Check polarity status */
4187 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4188 if (ret_val)
1da177e4
LT		 4189 return ret_val;
4190
4191 phy_info->cable_polarity = polarity;
4192
4193 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
8fc897b0 4194 if (ret_val)
1da177e4
LT		 4195 return ret_val;
4196
70c6f30a
JK		 4197 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4198 IGP01E1000_PSSR_MDIX_SHIFT);
1da177e4 4199
8fc897b0 4200 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 4201 IGP01E1000_PSSR_SPEED_1000MBPS) {
4202 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4203 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4204 if (ret_val)
1da177e4
LT		 4205 return ret_val;
4206
70c6f30a
JK		 4207 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4208 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4209 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4210 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4211 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4212 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4
LT		 4213
4214 /* Get cable length */
4215 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
8fc897b0 4216 if (ret_val)
1da177e4
LT		 4217 return ret_val;
4218
2d7edb92 4219 /* Translate to old method */
1da177e4
LT		 4220 average = (max_length + min_length) / 2;
4221
8fc897b0 4222 if (average <= e1000_igp_cable_length_50)
1da177e4 4223 phy_info->cable_length = e1000_cable_length_50;
8fc897b0 4224 else if (average <= e1000_igp_cable_length_80)
1da177e4 4225 phy_info->cable_length = e1000_cable_length_50_80;
8fc897b0 4226 else if (average <= e1000_igp_cable_length_110)
1da177e4 4227 phy_info->cable_length = e1000_cable_length_80_110;
8fc897b0 4228 else if (average <= e1000_igp_cable_length_140)
1da177e4
LT		 4229 phy_info->cable_length = e1000_cable_length_110_140;
4230 else
4231 phy_info->cable_length = e1000_cable_length_140;
4232 }
4233
4234 return E1000_SUCCESS;
4235}
4236
d37ea5d5
AK		 4237/******************************************************************************
4238* Get PHY information from various PHY registers for ife PHY only.
4239*
4240* hw - Struct containing variables accessed by shared code
4241* phy_info - PHY information structure
4242******************************************************************************/
406874a7 4243static s32
d37ea5d5
AK		 4244e1000_phy_ife_get_info(struct e1000_hw *hw,
4245 struct e1000_phy_info *phy_info)
4246{
406874a7
JP		 4247 s32 ret_val;
4248 u16 phy_data;
70c6f30a 4249 e1000_rev_polarity polarity;
d37ea5d5
AK		 4250
4251 DEBUGFUNC("e1000_phy_ife_get_info");
4252
4253 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4254 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4255
4256 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4257 if (ret_val)
4258 return ret_val;
4259 phy_info->polarity_correction =
70c6f30a
JK		 4260 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4261 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4262 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
d37ea5d5
AK		 4263
4264 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4265 ret_val = e1000_check_polarity(hw, &polarity);
4266 if (ret_val)
4267 return ret_val;
4268 } else {
4269 /* Polarity is forced. */
70c6f30a
JK		 4270 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4271 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4272 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
d37ea5d5
AK		 4273 }
4274 phy_info->cable_polarity = polarity;
4275
4276 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4277 if (ret_val)
4278 return ret_val;
4279
70c6f30a
JK		 4280 phy_info->mdix_mode = (e1000_auto_x_mode)
4281 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4282 IFE_PMC_MDIX_MODE_SHIFT);
d37ea5d5
AK		 4283
4284 return E1000_SUCCESS;
4285}
4286
1da177e4
LT		 4287/******************************************************************************
4288* Get PHY information from various PHY registers fot m88 PHY only.
4289*
4290* hw - Struct containing variables accessed by shared code
4291* phy_info - PHY information structure
4292******************************************************************************/
406874a7 4293static s32
1da177e4
LT		 4294e1000_phy_m88_get_info(struct e1000_hw *hw,
4295 struct e1000_phy_info *phy_info)
4296{
406874a7
JP		 4297 s32 ret_val;
4298 u16 phy_data;
70c6f30a 4299 e1000_rev_polarity polarity;
1da177e4
LT		 4300
4301 DEBUGFUNC("e1000_phy_m88_get_info");
4302
4303 /* The downshift status is checked only once, after link is established,
4304 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4305 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4306
4307 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 4308 if (ret_val)
1da177e4
LT		 4309 return ret_val;
4310
4311 phy_info->extended_10bt_distance =
70c6f30a
JK		 4312 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4313 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4314 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4315
1da177e4 4316 phy_info->polarity_correction =
70c6f30a
JK		 4317 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4318 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4319 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
1da177e4
LT		 4320
4321 /* Check polarity status */
4322 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4323 if (ret_val)
76c224bc 4324 return ret_val;
1da177e4
LT		 4325 phy_info->cable_polarity = polarity;
4326
4327 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 4328 if (ret_val)
1da177e4
LT		 4329 return ret_val;
4330
70c6f30a
JK		 4331 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4332 M88E1000_PSSR_MDIX_SHIFT);
1da177e4
LT		 4333
4334 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4335 /* Cable Length Estimation and Local/Remote Receiver Information
4336 * are only valid at 1000 Mbps.
4337 */
6418ecc6 4338 if (hw->phy_type != e1000_phy_gg82563) {
70c6f30a 4339 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6418ecc6
JK		 4340 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4341 } else {
4342 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4343 &phy_data);
4344 if (ret_val)
4345 return ret_val;
4346
70c6f30a 4347 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
6418ecc6 4348 }
1da177e4
LT		 4349
4350 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4351 if (ret_val)
1da177e4
LT		 4352 return ret_val;
4353
70c6f30a
JK		 4354 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4355 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4356 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4357 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4358 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4359 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4 4360
1da177e4
LT		 4361 }
4362
4363 return E1000_SUCCESS;
4364}
4365
4366/******************************************************************************
4367* Get PHY information from various PHY registers
4368*
4369* hw - Struct containing variables accessed by shared code
4370* phy_info - PHY information structure
4371******************************************************************************/
406874a7 4372s32
1da177e4
LT		 4373e1000_phy_get_info(struct e1000_hw *hw,
4374 struct e1000_phy_info *phy_info)
4375{
406874a7
JP		 4376 s32 ret_val;
4377 u16 phy_data;
1da177e4
LT		 4378
4379 DEBUGFUNC("e1000_phy_get_info");
4380
4381 phy_info->cable_length = e1000_cable_length_undefined;
4382 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4383 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4384 phy_info->downshift = e1000_downshift_undefined;
4385 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4386 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4387 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4388 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4389
8fc897b0 4390 if (hw->media_type != e1000_media_type_copper) {
1da177e4
LT		 4391 DEBUGOUT("PHY info is only valid for copper media\n");
4392 return -E1000_ERR_CONFIG;
4393 }
4394
4395 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4396 if (ret_val)
1da177e4
LT		 4397 return ret_val;
4398
4399 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4400 if (ret_val)
1da177e4
LT		 4401 return ret_val;
4402
8fc897b0 4403 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
1da177e4
LT		 4404 DEBUGOUT("PHY info is only valid if link is up\n");
4405 return -E1000_ERR_CONFIG;
4406 }
4407
cd94dd0b
AK		 4408 if (hw->phy_type == e1000_phy_igp ||
4409 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 4410 hw->phy_type == e1000_phy_igp_2)
1da177e4 4411 return e1000_phy_igp_get_info(hw, phy_info);
cd94dd0b
AK		 4412 else if (hw->phy_type == e1000_phy_ife)
4413 return e1000_phy_ife_get_info(hw, phy_info);
1da177e4
LT		 4414 else
4415 return e1000_phy_m88_get_info(hw, phy_info);
4416}
4417
406874a7 4418s32
1da177e4
LT		 4419e1000_validate_mdi_setting(struct e1000_hw *hw)
4420{
4421 DEBUGFUNC("e1000_validate_mdi_settings");
4422
8fc897b0 4423 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
1da177e4
LT		 4424 DEBUGOUT("Invalid MDI setting detected\n");
4425 hw->mdix = 1;
4426 return -E1000_ERR_CONFIG;
4427 }
4428 return E1000_SUCCESS;
4429}
4430
4431
4432/******************************************************************************
4433 * Sets up eeprom variables in the hw struct. Must be called after mac_type
0f15a8fa
JK		 4434 * is configured. Additionally, if this is ICH8, the flash controller GbE
4435 * registers must be mapped, or this will crash.
1da177e4
LT		 4436 *
4437 * hw - Struct containing variables accessed by shared code
4438 *****************************************************************************/
406874a7 4439s32
1da177e4
LT		 4440e1000_init_eeprom_params(struct e1000_hw *hw)
4441{
4442 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7
JP		 4443 u32 eecd = E1000_READ_REG(hw, EECD);
4444 s32 ret_val = E1000_SUCCESS;
4445 u16 eeprom_size;
1da177e4
LT		 4446
4447 DEBUGFUNC("e1000_init_eeprom_params");
4448
4449 switch (hw->mac_type) {
4450 case e1000_82542_rev2_0:
4451 case e1000_82542_rev2_1:
4452 case e1000_82543:
4453 case e1000_82544:
4454 eeprom->type = e1000_eeprom_microwire;
4455 eeprom->word_size = 64;
4456 eeprom->opcode_bits = 3;
4457 eeprom->address_bits = 6;
4458 eeprom->delay_usec = 50;
c3033b01
JP		 4459 eeprom->use_eerd = false;
4460 eeprom->use_eewr = false;
1da177e4
LT		 4461 break;
4462 case e1000_82540:
4463 case e1000_82545:
4464 case e1000_82545_rev_3:
4465 case e1000_82546:
4466 case e1000_82546_rev_3:
4467 eeprom->type = e1000_eeprom_microwire;
4468 eeprom->opcode_bits = 3;
4469 eeprom->delay_usec = 50;
8fc897b0 4470 if (eecd & E1000_EECD_SIZE) {
1da177e4
LT		 4471 eeprom->word_size = 256;
4472 eeprom->address_bits = 8;
4473 } else {
4474 eeprom->word_size = 64;
4475 eeprom->address_bits = 6;
4476 }
c3033b01
JP		 4477 eeprom->use_eerd = false;
4478 eeprom->use_eewr = false;
1da177e4
LT		 4479 break;
4480 case e1000_82541:
4481 case e1000_82541_rev_2:
4482 case e1000_82547:
4483 case e1000_82547_rev_2:
4484 if (eecd & E1000_EECD_TYPE) {
4485 eeprom->type = e1000_eeprom_spi;
4486 eeprom->opcode_bits = 8;
4487 eeprom->delay_usec = 1;
4488 if (eecd & E1000_EECD_ADDR_BITS) {
4489 eeprom->page_size = 32;
4490 eeprom->address_bits = 16;
4491 } else {
4492 eeprom->page_size = 8;
4493 eeprom->address_bits = 8;
4494 }
4495 } else {
4496 eeprom->type = e1000_eeprom_microwire;
4497 eeprom->opcode_bits = 3;
4498 eeprom->delay_usec = 50;
4499 if (eecd & E1000_EECD_ADDR_BITS) {
4500 eeprom->word_size = 256;
4501 eeprom->address_bits = 8;
4502 } else {
4503 eeprom->word_size = 64;
4504 eeprom->address_bits = 6;
4505 }
4506 }
c3033b01
JP		 4507 eeprom->use_eerd = false;
4508 eeprom->use_eewr = false;
2d7edb92 4509 break;
868d5309
MC		 4510 case e1000_82571:
4511 case e1000_82572:
4512 eeprom->type = e1000_eeprom_spi;
4513 eeprom->opcode_bits = 8;
4514 eeprom->delay_usec = 1;
4515 if (eecd & E1000_EECD_ADDR_BITS) {
4516 eeprom->page_size = 32;
4517 eeprom->address_bits = 16;
4518 } else {
4519 eeprom->page_size = 8;
4520 eeprom->address_bits = 8;
4521 }
c3033b01
JP		 4522 eeprom->use_eerd = false;
4523 eeprom->use_eewr = false;
868d5309 4524 break;
2d7edb92
MC		 4525 case e1000_82573:
4526 eeprom->type = e1000_eeprom_spi;
4527 eeprom->opcode_bits = 8;
4528 eeprom->delay_usec = 1;
4529 if (eecd & E1000_EECD_ADDR_BITS) {
4530 eeprom->page_size = 32;
4531 eeprom->address_bits = 16;
4532 } else {
4533 eeprom->page_size = 8;
4534 eeprom->address_bits = 8;
4535 }
c3033b01
JP		 4536 eeprom->use_eerd = true;
4537 eeprom->use_eewr = true;
4538 if (!e1000_is_onboard_nvm_eeprom(hw)) {
2d7edb92
MC		 4539 eeprom->type = e1000_eeprom_flash;
4540 eeprom->word_size = 2048;
4541
4542 /* Ensure that the Autonomous FLASH update bit is cleared due to
4543 * Flash update issue on parts which use a FLASH for NVM. */
4544 eecd &= ~E1000_EECD_AUPDEN;
4545 E1000_WRITE_REG(hw, EECD, eecd);
4546 }
1da177e4 4547 break;
6418ecc6
JK		 4548 case e1000_80003es2lan:
4549 eeprom->type = e1000_eeprom_spi;
4550 eeprom->opcode_bits = 8;
4551 eeprom->delay_usec = 1;
4552 if (eecd & E1000_EECD_ADDR_BITS) {
4553 eeprom->page_size = 32;
4554 eeprom->address_bits = 16;
4555 } else {
4556 eeprom->page_size = 8;
4557 eeprom->address_bits = 8;
4558 }
c3033b01
JP		 4559 eeprom->use_eerd = true;
4560 eeprom->use_eewr = false;
6418ecc6 4561 break;
cd94dd0b 4562 case e1000_ich8lan:
35574764 4563 {
406874a7
JP		 4564 s32 i = 0;
4565 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
cd94dd0b
AK		 4566
4567 eeprom->type = e1000_eeprom_ich8;
c3033b01
JP		 4568 eeprom->use_eerd = false;
4569 eeprom->use_eewr = false;
cd94dd0b
AK		 4570 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4571
4572 /* Zero the shadow RAM structure. But don't load it from NVM
4573 * so as to save time for driver init */
4574 if (hw->eeprom_shadow_ram != NULL) {
4575 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
c3033b01 4576 hw->eeprom_shadow_ram[i].modified = false;
cd94dd0b
AK		 4577 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4578 }
4579 }
4580
2df7d59f
JK		 4581 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4582 ICH_FLASH_SECTOR_SIZE;
4583
4584 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4585 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4586
4587 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
cd94dd0b 4588
406874a7 4589 hw->flash_bank_size /= 2 * sizeof(u16);
cd94dd0b
AK		 4590
4591 break;
35574764 4592 }
1da177e4
LT		 4593 default:
4594 break;
4595 }
4596
4597 if (eeprom->type == e1000_eeprom_spi) {
2d7edb92
MC		 4598 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4599 * 32KB (incremented by powers of 2).
4600 */
8fc897b0 4601 if (hw->mac_type <= e1000_82547_rev_2) {
2d7edb92
MC		 4602 /* Set to default value for initial eeprom read. */
4603 eeprom->word_size = 64;
4604 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
8fc897b0 4605 if (ret_val)
2d7edb92
MC		 4606 return ret_val;
4607 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4608 /* 256B eeprom size was not supported in earlier hardware, so we
4609 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4610 * is never the result used in the shifting logic below. */
8fc897b0 4611 if (eeprom_size)
2d7edb92
MC		 4612 eeprom_size++;
4613 } else {
406874a7 4614 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
2d7edb92 4615 E1000_EECD_SIZE_EX_SHIFT);
1da177e4 4616 }
2d7edb92
MC		 4617
4618 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
1da177e4 4619 }
2d7edb92 4620 return ret_val;
1da177e4
LT		 4621}
4622
4623/******************************************************************************
4624 * Raises the EEPROM's clock input.
4625 *
4626 * hw - Struct containing variables accessed by shared code
4627 * eecd - EECD's current value
4628 *****************************************************************************/
4629static void
4630e1000_raise_ee_clk(struct e1000_hw *hw,
406874a7 4631 u32 *eecd)
1da177e4
LT		 4632{
4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4634 * wait <delay> microseconds.
4635 */
4636 *eecd = *eecd | E1000_EECD_SK;
4637 E1000_WRITE_REG(hw, EECD, *eecd);
4638 E1000_WRITE_FLUSH(hw);
4639 udelay(hw->eeprom.delay_usec);
4640}
4641
4642/******************************************************************************
4643 * Lowers the EEPROM's clock input.
4644 *
4645 * hw - Struct containing variables accessed by shared code
4646 * eecd - EECD's current value
4647 *****************************************************************************/
4648static void
4649e1000_lower_ee_clk(struct e1000_hw *hw,
406874a7 4650 u32 *eecd)
1da177e4
LT		 4651{
4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4653 * wait 50 microseconds.
4654 */
4655 *eecd = *eecd & ~E1000_EECD_SK;
4656 E1000_WRITE_REG(hw, EECD, *eecd);
4657 E1000_WRITE_FLUSH(hw);
4658 udelay(hw->eeprom.delay_usec);
4659}
4660
4661/******************************************************************************
4662 * Shift data bits out to the EEPROM.
4663 *
4664 * hw - Struct containing variables accessed by shared code
4665 * data - data to send to the EEPROM
4666 * count - number of bits to shift out
4667 *****************************************************************************/
4668static void
4669e1000_shift_out_ee_bits(struct e1000_hw *hw,
406874a7
JP		 4670 u16 data,
4671 u16 count)
1da177e4
LT		 4672{
4673 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7
JP		 4674 u32 eecd;
4675 u32 mask;
1da177e4
LT		 4676
4677 /* We need to shift "count" bits out to the EEPROM. So, value in the
4678 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4679 * In order to do this, "data" must be broken down into bits.
4680 */
4681 mask = 0x01 << (count - 1);
4682 eecd = E1000_READ_REG(hw, EECD);
4683 if (eeprom->type == e1000_eeprom_microwire) {
4684 eecd &= ~E1000_EECD_DO;
4685 } else if (eeprom->type == e1000_eeprom_spi) {
4686 eecd |= E1000_EECD_DO;
4687 }
4688 do {
4689 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4690 * and then raising and then lowering the clock (the SK bit controls
4691 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4692 * by setting "DI" to "0" and then raising and then lowering the clock.
4693 */
4694 eecd &= ~E1000_EECD_DI;
4695
8fc897b0 4696 if (data & mask)
1da177e4
LT		 4697 eecd |= E1000_EECD_DI;
4698
4699 E1000_WRITE_REG(hw, EECD, eecd);
4700 E1000_WRITE_FLUSH(hw);
4701
4702 udelay(eeprom->delay_usec);
4703
4704 e1000_raise_ee_clk(hw, &eecd);
4705 e1000_lower_ee_clk(hw, &eecd);
4706
4707 mask = mask >> 1;
4708
8fc897b0 4709 } while (mask);
1da177e4
LT		 4710
4711 /* We leave the "DI" bit set to "0" when we leave this routine. */
4712 eecd &= ~E1000_EECD_DI;
4713 E1000_WRITE_REG(hw, EECD, eecd);
4714}
4715
4716/******************************************************************************
4717 * Shift data bits in from the EEPROM
4718 *
4719 * hw - Struct containing variables accessed by shared code
4720 *****************************************************************************/
406874a7 4721static u16
1da177e4 4722e1000_shift_in_ee_bits(struct e1000_hw *hw,
406874a7 4723 u16 count)
1da177e4 4724{
406874a7
JP		 4725 u32 eecd;
4726 u32 i;
4727 u16 data;
1da177e4
LT		 4728
4729 /* In order to read a register from the EEPROM, we need to shift 'count'
4730 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4731 * input to the EEPROM (setting the SK bit), and then reading the value of
4732 * the "DO" bit. During this "shifting in" process the "DI" bit should
4733 * always be clear.
4734 */
4735
4736 eecd = E1000_READ_REG(hw, EECD);
4737
4738 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4739 data = 0;
4740
8fc897b0 4741 for (i = 0; i < count; i++) {
1da177e4
LT		 4742 data = data << 1;
4743 e1000_raise_ee_clk(hw, &eecd);
4744
4745 eecd = E1000_READ_REG(hw, EECD);
4746
4747 eecd &= ~(E1000_EECD_DI);
8fc897b0 4748 if (eecd & E1000_EECD_DO)
1da177e4
LT		 4749 data |= 1;
4750
4751 e1000_lower_ee_clk(hw, &eecd);
4752 }
4753
4754 return data;
4755}
4756
4757/******************************************************************************
4758 * Prepares EEPROM for access
4759 *
4760 * hw - Struct containing variables accessed by shared code
4761 *
4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4763 * function should be called before issuing a command to the EEPROM.
4764 *****************************************************************************/
406874a7 4765static s32
1da177e4
LT		 4766e1000_acquire_eeprom(struct e1000_hw *hw)
4767{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7 4769 u32 eecd, i=0;
1da177e4
LT		 4770
4771 DEBUGFUNC("e1000_acquire_eeprom");
4772
6418ecc6
JK		 4773 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4774 return -E1000_ERR_SWFW_SYNC;
1da177e4
LT		 4775 eecd = E1000_READ_REG(hw, EECD);
4776
2d7edb92 4777 if (hw->mac_type != e1000_82573) {
868d5309 4778 /* Request EEPROM Access */
8fc897b0 4779 if (hw->mac_type > e1000_82544) {
868d5309 4780 eecd |= E1000_EECD_REQ;
1da177e4 4781 E1000_WRITE_REG(hw, EECD, eecd);
868d5309 4782 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 4783 while ((!(eecd & E1000_EECD_GNT)) &&
868d5309
MC		 4784 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4785 i++;
4786 udelay(5);
4787 eecd = E1000_READ_REG(hw, EECD);
4788 }
8fc897b0 4789 if (!(eecd & E1000_EECD_GNT)) {
868d5309
MC		 4790 eecd &= ~E1000_EECD_REQ;
4791 E1000_WRITE_REG(hw, EECD, eecd);
4792 DEBUGOUT("Could not acquire EEPROM grant\n");
6418ecc6 4793 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
868d5309
MC		 4794 return -E1000_ERR_EEPROM;
4795 }
1da177e4
LT		 4796 }
4797 }
4798
4799 /* Setup EEPROM for Read/Write */
4800
4801 if (eeprom->type == e1000_eeprom_microwire) {
4802 /* Clear SK and DI */
4803 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4804 E1000_WRITE_REG(hw, EECD, eecd);
4805
4806 /* Set CS */
4807 eecd |= E1000_EECD_CS;
4808 E1000_WRITE_REG(hw, EECD, eecd);
4809 } else if (eeprom->type == e1000_eeprom_spi) {
4810 /* Clear SK and CS */
4811 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4812 E1000_WRITE_REG(hw, EECD, eecd);
4813 udelay(1);
4814 }
4815
4816 return E1000_SUCCESS;
4817}
4818
4819/******************************************************************************
4820 * Returns EEPROM to a "standby" state
4821 *
4822 * hw - Struct containing variables accessed by shared code
4823 *****************************************************************************/
4824static void
4825e1000_standby_eeprom(struct e1000_hw *hw)
4826{
4827 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7 4828 u32 eecd;
1da177e4
LT		 4829
4830 eecd = E1000_READ_REG(hw, EECD);
4831
8fc897b0 4832 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4833 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4834 E1000_WRITE_REG(hw, EECD, eecd);
4835 E1000_WRITE_FLUSH(hw);
4836 udelay(eeprom->delay_usec);
4837
4838 /* Clock high */
4839 eecd |= E1000_EECD_SK;
4840 E1000_WRITE_REG(hw, EECD, eecd);
4841 E1000_WRITE_FLUSH(hw);
4842 udelay(eeprom->delay_usec);
4843
4844 /* Select EEPROM */
4845 eecd |= E1000_EECD_CS;
4846 E1000_WRITE_REG(hw, EECD, eecd);
4847 E1000_WRITE_FLUSH(hw);
4848 udelay(eeprom->delay_usec);
4849
4850 /* Clock low */
4851 eecd &= ~E1000_EECD_SK;
4852 E1000_WRITE_REG(hw, EECD, eecd);
4853 E1000_WRITE_FLUSH(hw);
4854 udelay(eeprom->delay_usec);
8fc897b0 4855 } else if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4856 /* Toggle CS to flush commands */
4857 eecd |= E1000_EECD_CS;
4858 E1000_WRITE_REG(hw, EECD, eecd);
4859 E1000_WRITE_FLUSH(hw);
4860 udelay(eeprom->delay_usec);
4861 eecd &= ~E1000_EECD_CS;
4862 E1000_WRITE_REG(hw, EECD, eecd);
4863 E1000_WRITE_FLUSH(hw);
4864 udelay(eeprom->delay_usec);
4865 }
4866}
4867
4868/******************************************************************************
4869 * Terminates a command by inverting the EEPROM's chip select pin
4870 *
4871 * hw - Struct containing variables accessed by shared code
4872 *****************************************************************************/
4873static void
4874e1000_release_eeprom(struct e1000_hw *hw)
4875{
406874a7 4876 u32 eecd;
1da177e4
LT		 4877
4878 DEBUGFUNC("e1000_release_eeprom");
4879
4880 eecd = E1000_READ_REG(hw, EECD);
4881
4882 if (hw->eeprom.type == e1000_eeprom_spi) {
4883 eecd |= E1000_EECD_CS; /* Pull CS high */
4884 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4885
4886 E1000_WRITE_REG(hw, EECD, eecd);
4887
4888 udelay(hw->eeprom.delay_usec);
8fc897b0 4889 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
1da177e4
LT		 4890 /* cleanup eeprom */
4891
4892 /* CS on Microwire is active-high */
4893 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4894
4895 E1000_WRITE_REG(hw, EECD, eecd);
4896
4897 /* Rising edge of clock */
4898 eecd |= E1000_EECD_SK;
4899 E1000_WRITE_REG(hw, EECD, eecd);
4900 E1000_WRITE_FLUSH(hw);
4901 udelay(hw->eeprom.delay_usec);
4902
4903 /* Falling edge of clock */
4904 eecd &= ~E1000_EECD_SK;
4905 E1000_WRITE_REG(hw, EECD, eecd);
4906 E1000_WRITE_FLUSH(hw);
4907 udelay(hw->eeprom.delay_usec);
4908 }
4909
4910 /* Stop requesting EEPROM access */
8fc897b0 4911 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 4912 eecd &= ~E1000_EECD_REQ;
4913 E1000_WRITE_REG(hw, EECD, eecd);
4914 }
2d7edb92 4915
6418ecc6 4916 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
1da177e4
LT		 4917}
4918
4919/******************************************************************************
4920 * Reads a 16 bit word from the EEPROM.
4921 *
4922 * hw - Struct containing variables accessed by shared code
4923 *****************************************************************************/
406874a7 4924static s32
1da177e4
LT		 4925e1000_spi_eeprom_ready(struct e1000_hw *hw)
4926{
406874a7
JP		 4927 u16 retry_count = 0;
4928 u8 spi_stat_reg;
1da177e4
LT		 4929
4930 DEBUGFUNC("e1000_spi_eeprom_ready");
4931
4932 /* Read "Status Register" repeatedly until the LSB is cleared. The
4933 * EEPROM will signal that the command has been completed by clearing
4934 * bit 0 of the internal status register. If it's not cleared within
4935 * 5 milliseconds, then error out.
4936 */
4937 retry_count = 0;
4938 do {
4939 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4940 hw->eeprom.opcode_bits);
406874a7 4941 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
1da177e4
LT		 4942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4943 break;
4944
4945 udelay(5);
4946 retry_count += 5;
4947
4948 e1000_standby_eeprom(hw);
8fc897b0 4949 } while (retry_count < EEPROM_MAX_RETRY_SPI);
1da177e4
LT		 4950
4951 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4952 * only 0-5mSec on 5V devices)
4953 */
8fc897b0 4954 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
1da177e4
LT		 4955 DEBUGOUT("SPI EEPROM Status error\n");
4956 return -E1000_ERR_EEPROM;
4957 }
4958
4959 return E1000_SUCCESS;
4960}
4961
4962/******************************************************************************
4963 * Reads a 16 bit word from the EEPROM.
4964 *
4965 * hw - Struct containing variables accessed by shared code
4966 * offset - offset of word in the EEPROM to read
4967 * data - word read from the EEPROM
4968 * words - number of words to read
4969 *****************************************************************************/
406874a7 4970s32
1da177e4 4971e1000_read_eeprom(struct e1000_hw *hw,
406874a7
JP		 4972 u16 offset,
4973 u16 words,
4974 u16 *data)
1da177e4
LT		 4975{
4976 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7 4977 u32 i = 0;
1da177e4
LT		 4978
4979 DEBUGFUNC("e1000_read_eeprom");
2d7edb92 4980
2a88c173
JK		 4981 /* If eeprom is not yet detected, do so now */
4982 if (eeprom->word_size == 0)
4983 e1000_init_eeprom_params(hw);
4984
1da177e4
LT		 4985 /* A check for invalid values: offset too large, too many words, and not
4986 * enough words.
4987 */
8fc897b0 4988 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4 4989 (words == 0)) {
2a88c173 4990 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
1da177e4
LT		 4991 return -E1000_ERR_EEPROM;
4992 }
4993
2a88c173
JK		 4994 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4995 * directly. In this case, we need to acquire the EEPROM so that
4996 * FW or other port software does not interrupt.
4997 */
c3033b01 4998 if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
2a88c173
JK		 4999 /* Prepare the EEPROM for bit-bang reading */
5000 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5001 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5002 }
5003
2a88c173 5004 /* Eerd register EEPROM access requires no eeprom aquire/release */
c3033b01 5005 if (eeprom->use_eerd)
2a88c173 5006 return e1000_read_eeprom_eerd(hw, offset, words, data);
1da177e4 5007
2a88c173 5008 /* ICH EEPROM access is done via the ICH flash controller */
cd94dd0b
AK		 5009 if (eeprom->type == e1000_eeprom_ich8)
5010 return e1000_read_eeprom_ich8(hw, offset, words, data);
5011
2a88c173
JK		 5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5013 * acquired the EEPROM at this point, so any returns should relase it */
cd94dd0b 5014 if (eeprom->type == e1000_eeprom_spi) {
406874a7
JP		 5015 u16 word_in;
5016 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
1da177e4 5017
8fc897b0 5018 if (e1000_spi_eeprom_ready(hw)) {
1da177e4
LT		 5019 e1000_release_eeprom(hw);
5020 return -E1000_ERR_EEPROM;
5021 }
5022
5023 e1000_standby_eeprom(hw);
5024
5025 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5026 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5027 read_opcode |= EEPROM_A8_OPCODE_SPI;
5028
5029 /* Send the READ command (opcode + addr) */
5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
406874a7 5031 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
1da177e4
LT		 5032
5033 /* Read the data. The address of the eeprom internally increments with
5034 * each byte (spi) being read, saving on the overhead of eeprom setup
5035 * and tear-down. The address counter will roll over if reading beyond
5036 * the size of the eeprom, thus allowing the entire memory to be read
5037 * starting from any offset. */
5038 for (i = 0; i < words; i++) {
5039 word_in = e1000_shift_in_ee_bits(hw, 16);
5040 data[i] = (word_in >> 8) | (word_in << 8);
5041 }
8fc897b0 5042 } else if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5043 for (i = 0; i < words; i++) {
5044 /* Send the READ command (opcode + addr) */
5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5046 eeprom->opcode_bits);
406874a7 5047 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
1da177e4
LT		 5048 eeprom->address_bits);
5049
5050 /* Read the data. For microwire, each word requires the overhead
5051 * of eeprom setup and tear-down. */
5052 data[i] = e1000_shift_in_ee_bits(hw, 16);
5053 e1000_standby_eeprom(hw);
5054 }
5055 }
5056
5057 /* End this read operation */
5058 e1000_release_eeprom(hw);
5059
5060 return E1000_SUCCESS;
5061}
5062
5063/******************************************************************************
2d7edb92 5064 * Reads a 16 bit word from the EEPROM using the EERD register.
1da177e4
LT		 5065 *
5066 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5067 * offset - offset of word in the EEPROM to read
5068 * data - word read from the EEPROM
5069 * words - number of words to read
1da177e4 5070 *****************************************************************************/
406874a7 5071static s32
2d7edb92 5072e1000_read_eeprom_eerd(struct e1000_hw *hw,
406874a7
JP		 5073 u16 offset,
5074 u16 words,
5075 u16 *data)
1da177e4 5076{
406874a7
JP		 5077 u32 i, eerd = 0;
5078 s32 error = 0;
1da177e4 5079
2d7edb92
MC		 5080 for (i = 0; i < words; i++) {
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5082 E1000_EEPROM_RW_REG_START;
1da177e4 5083
2d7edb92
MC		 5084 E1000_WRITE_REG(hw, EERD, eerd);
5085 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
76c224bc 5086
8fc897b0 5087 if (error) {
2d7edb92 5088 break;
1da177e4 5089 }
2d7edb92 5090 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
76c224bc 5091
1da177e4 5092 }
76c224bc 5093
2d7edb92 5094 return error;
1da177e4
LT		 5095}
5096
5097/******************************************************************************
2d7edb92 5098 * Writes a 16 bit word from the EEPROM using the EEWR register.
1da177e4
LT		 5099 *
5100 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5101 * offset - offset of word in the EEPROM to read
5102 * data - word read from the EEPROM
5103 * words - number of words to read
1da177e4 5104 *****************************************************************************/
406874a7 5105static s32
2d7edb92 5106e1000_write_eeprom_eewr(struct e1000_hw *hw,
406874a7
JP		 5107 u16 offset,
5108 u16 words,
5109 u16 *data)
1da177e4 5110{
406874a7
JP		 5111 u32 register_value = 0;
5112 u32 i = 0;
5113 s32 error = 0;
1da177e4 5114
6418ecc6
JK		 5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5116 return -E1000_ERR_SWFW_SYNC;
5117
2d7edb92 5118 for (i = 0; i < words; i++) {
76c224bc
AK		 5119 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5120 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
2d7edb92 5121 E1000_EEPROM_RW_REG_START;
1da177e4 5122
2d7edb92 5123 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
8fc897b0 5124 if (error) {
2d7edb92 5125 break;
76c224bc 5126 }
2d7edb92
MC		 5127
5128 E1000_WRITE_REG(hw, EEWR, register_value);
76c224bc 5129
2d7edb92 5130 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
76c224bc 5131
8fc897b0 5132 if (error) {
2d7edb92 5133 break;
76c224bc 5134 }
2d7edb92 5135 }
76c224bc 5136
6418ecc6 5137 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
2d7edb92
MC		 5138 return error;
5139}
5140
5141/******************************************************************************
5142 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5143 *
5144 * hw - Struct containing variables accessed by shared code
5145 *****************************************************************************/
406874a7 5146static s32
2d7edb92
MC		 5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5148{
406874a7
JP		 5149 u32 attempts = 100000;
5150 u32 i, reg = 0;
5151 s32 done = E1000_ERR_EEPROM;
2d7edb92 5152
8fc897b0
AK		 5153 for (i = 0; i < attempts; i++) {
5154 if (eerd == E1000_EEPROM_POLL_READ)
2d7edb92 5155 reg = E1000_READ_REG(hw, EERD);
76c224bc 5156 else
2d7edb92
MC		 5157 reg = E1000_READ_REG(hw, EEWR);
5158
8fc897b0 5159 if (reg & E1000_EEPROM_RW_REG_DONE) {
2d7edb92
MC		 5160 done = E1000_SUCCESS;
5161 break;
5162 }
5163 udelay(5);
5164 }
5165
5166 return done;
5167}
5168
5169/***************************************************************************
5170* Description: Determines if the onboard NVM is FLASH or EEPROM.
5171*
5172* hw - Struct containing variables accessed by shared code
5173****************************************************************************/
c3033b01 5174static bool
2d7edb92
MC		 5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5176{
406874a7 5177 u32 eecd = 0;
2d7edb92 5178
6418ecc6
JK		 5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5180
cd94dd0b 5181 if (hw->mac_type == e1000_ich8lan)
c3033b01 5182 return false;
cd94dd0b
AK		 5183
5184 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 5185 eecd = E1000_READ_REG(hw, EECD);
5186
5187 /* Isolate bits 15 & 16 */
5188 eecd = ((eecd >> 15) & 0x03);
5189
5190 /* If both bits are set, device is Flash type */
8fc897b0 5191 if (eecd == 0x03) {
c3033b01 5192 return false;
2d7edb92
MC		 5193 }
5194 }
c3033b01 5195 return true;
2d7edb92
MC		 5196}
5197
5198/******************************************************************************
5199 * Verifies that the EEPROM has a valid checksum
5200 *
5201 * hw - Struct containing variables accessed by shared code
5202 *
5203 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5205 * valid.
5206 *****************************************************************************/
406874a7 5207s32
2d7edb92
MC		 5208e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5209{
406874a7
JP		 5210 u16 checksum = 0;
5211 u16 i, eeprom_data;
2d7edb92
MC		 5212
5213 DEBUGFUNC("e1000_validate_eeprom_checksum");
5214
c3033b01 5215 if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
2d7edb92
MC		 5216 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5217 * 10h-12h. Checksum may need to be fixed. */
5218 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5219 if ((eeprom_data & 0x10) == 0) {
5220 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5221 * has already been fixed. If the checksum is still wrong and this
5222 * bit is a 1, we need to return bad checksum. Otherwise, we need
5223 * to set this bit to a 1 and update the checksum. */
5224 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5225 if ((eeprom_data & 0x8000) == 0) {
5226 eeprom_data |= 0x8000;
5227 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5228 e1000_update_eeprom_checksum(hw);
5229 }
5230 }
5231 }
5232
cd94dd0b
AK		 5233 if (hw->mac_type == e1000_ich8lan) {
5234 /* Drivers must allocate the shadow ram structure for the
5235 * EEPROM checksum to be updated. Otherwise, this bit as well
5236 * as the checksum must both be set correctly for this
5237 * validation to pass.
5238 */
5239 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5240 if ((eeprom_data & 0x40) == 0) {
5241 eeprom_data |= 0x40;
5242 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5243 e1000_update_eeprom_checksum(hw);
5244 }
5245 }
5246
5247 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5248 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5249 DEBUGOUT("EEPROM Read Error\n");
5250 return -E1000_ERR_EEPROM;
5251 }
5252 checksum += eeprom_data;
5253 }
5254
406874a7 5255 if (checksum == (u16) EEPROM_SUM)
2d7edb92
MC		 5256 return E1000_SUCCESS;
5257 else {
5258 DEBUGOUT("EEPROM Checksum Invalid\n");
5259 return -E1000_ERR_EEPROM;
5260 }
5261}
5262
5263/******************************************************************************
5264 * Calculates the EEPROM checksum and writes it to the EEPROM
5265 *
5266 * hw - Struct containing variables accessed by shared code
5267 *
5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5269 * Writes the difference to word offset 63 of the EEPROM.
5270 *****************************************************************************/
406874a7 5271s32
2d7edb92
MC		 5272e1000_update_eeprom_checksum(struct e1000_hw *hw)
5273{
406874a7
JP		 5274 u32 ctrl_ext;
5275 u16 checksum = 0;
5276 u16 i, eeprom_data;
2d7edb92
MC		 5277
5278 DEBUGFUNC("e1000_update_eeprom_checksum");
5279
8fc897b0
AK		 5280 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5281 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5282 DEBUGOUT("EEPROM Read Error\n");
5283 return -E1000_ERR_EEPROM;
5284 }
5285 checksum += eeprom_data;
5286 }
406874a7 5287 checksum = (u16) EEPROM_SUM - checksum;
8fc897b0 5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
1da177e4
LT		 5289 DEBUGOUT("EEPROM Write Error\n");
5290 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5291 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5292 e1000_commit_shadow_ram(hw);
cd94dd0b
AK		 5293 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5294 e1000_commit_shadow_ram(hw);
5295 /* Reload the EEPROM, or else modifications will not appear
5296 * until after next adapter reset. */
5297 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5298 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5299 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
f8ec4733 5300 msleep(10);
1da177e4
LT		 5301 }
5302 return E1000_SUCCESS;
5303}
5304
5305/******************************************************************************
5306 * Parent function for writing words to the different EEPROM types.
5307 *
5308 * hw - Struct containing variables accessed by shared code
5309 * offset - offset within the EEPROM to be written to
5310 * words - number of words to write
5311 * data - 16 bit word to be written to the EEPROM
5312 *
5313 * If e1000_update_eeprom_checksum is not called after this function, the
5314 * EEPROM will most likely contain an invalid checksum.
5315 *****************************************************************************/
406874a7 5316s32
1da177e4 5317e1000_write_eeprom(struct e1000_hw *hw,
406874a7
JP		 5318 u16 offset,
5319 u16 words,
5320 u16 *data)
1da177e4
LT		 5321{
5322 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7 5323 s32 status = 0;
1da177e4
LT		 5324
5325 DEBUGFUNC("e1000_write_eeprom");
5326
2a88c173
JK		 5327 /* If eeprom is not yet detected, do so now */
5328 if (eeprom->word_size == 0)
5329 e1000_init_eeprom_params(hw);
5330
1da177e4
LT		 5331 /* A check for invalid values: offset too large, too many words, and not
5332 * enough words.
5333 */
8fc897b0 5334 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 5335 (words == 0)) {
5336 DEBUGOUT("\"words\" parameter out of bounds\n");
5337 return -E1000_ERR_EEPROM;
5338 }
5339
868d5309 5340 /* 82573 writes only through eewr */
c3033b01 5341 if (eeprom->use_eewr)
2d7edb92
MC		 5342 return e1000_write_eeprom_eewr(hw, offset, words, data);
5343
cd94dd0b
AK		 5344 if (eeprom->type == e1000_eeprom_ich8)
5345 return e1000_write_eeprom_ich8(hw, offset, words, data);
5346
1da177e4
LT		 5347 /* Prepare the EEPROM for writing */
5348 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5349 return -E1000_ERR_EEPROM;
5350
8fc897b0 5351 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5352 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5353 } else {
5354 status = e1000_write_eeprom_spi(hw, offset, words, data);
f8ec4733 5355 msleep(10);
1da177e4
LT		 5356 }
5357
5358 /* Done with writing */
5359 e1000_release_eeprom(hw);
5360
5361 return status;
5362}
5363
5364/******************************************************************************
5365 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5366 *
5367 * hw - Struct containing variables accessed by shared code
5368 * offset - offset within the EEPROM to be written to
5369 * words - number of words to write
5370 * data - pointer to array of 8 bit words to be written to the EEPROM
5371 *
5372 *****************************************************************************/
406874a7 5373static s32
1da177e4 5374e1000_write_eeprom_spi(struct e1000_hw *hw,
406874a7
JP		 5375 u16 offset,
5376 u16 words,
5377 u16 *data)
1da177e4
LT		 5378{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7 5380 u16 widx = 0;
1da177e4
LT		 5381
5382 DEBUGFUNC("e1000_write_eeprom_spi");
5383
5384 while (widx < words) {
406874a7 5385 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
1da177e4 5386
8fc897b0 5387 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
1da177e4
LT		 5388
5389 e1000_standby_eeprom(hw);
5390
5391 /* Send the WRITE ENABLE command (8 bit opcode ) */
5392 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5393 eeprom->opcode_bits);
5394
5395 e1000_standby_eeprom(hw);
5396
5397 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5398 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5399 write_opcode |= EEPROM_A8_OPCODE_SPI;
5400
5401 /* Send the Write command (8-bit opcode + addr) */
5402 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5403
406874a7 5404 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
1da177e4
LT		 5405 eeprom->address_bits);
5406
5407 /* Send the data */
5408
5409 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5410 while (widx < words) {
406874a7 5411 u16 word_out = data[widx];
1da177e4
LT		 5412 word_out = (word_out >> 8) | (word_out << 8);
5413 e1000_shift_out_ee_bits(hw, word_out, 16);
5414 widx++;
5415
5416 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5417 * operation, while the smaller eeproms are capable of an 8-byte
5418 * PAGE WRITE operation. Break the inner loop to pass new address
5419 */
8fc897b0 5420 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
1da177e4
LT		 5421 e1000_standby_eeprom(hw);
5422 break;
5423 }
5424 }
5425 }
5426
5427 return E1000_SUCCESS;
5428}
5429
5430/******************************************************************************
5431 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5432 *
5433 * hw - Struct containing variables accessed by shared code
5434 * offset - offset within the EEPROM to be written to
5435 * words - number of words to write
5436 * data - pointer to array of 16 bit words to be written to the EEPROM
5437 *
5438 *****************************************************************************/
406874a7 5439static s32
1da177e4 5440e1000_write_eeprom_microwire(struct e1000_hw *hw,
406874a7
JP		 5441 u16 offset,
5442 u16 words,
5443 u16 *data)
1da177e4
LT		 5444{
5445 struct e1000_eeprom_info *eeprom = &hw->eeprom;
406874a7
JP		 5446 u32 eecd;
5447 u16 words_written = 0;
5448 u16 i = 0;
1da177e4
LT		 5449
5450 DEBUGFUNC("e1000_write_eeprom_microwire");
5451
5452 /* Send the write enable command to the EEPROM (3-bit opcode plus
5453 * 6/8-bit dummy address beginning with 11). It's less work to include
5454 * the 11 of the dummy address as part of the opcode than it is to shift
5455 * it over the correct number of bits for the address. This puts the
5456 * EEPROM into write/erase mode.
5457 */
5458 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
406874a7 5459 (u16)(eeprom->opcode_bits + 2));
1da177e4 5460
406874a7 5461 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
1da177e4
LT		 5462
5463 /* Prepare the EEPROM */
5464 e1000_standby_eeprom(hw);
5465
5466 while (words_written < words) {
5467 /* Send the Write command (3-bit opcode + addr) */
5468 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5469 eeprom->opcode_bits);
5470
406874a7 5471 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
1da177e4
LT		 5472 eeprom->address_bits);
5473
5474 /* Send the data */
5475 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5476
5477 /* Toggle the CS line. This in effect tells the EEPROM to execute
5478 * the previous command.
5479 */
5480 e1000_standby_eeprom(hw);
5481
5482 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5483 * signal that the command has been completed by raising the DO signal.
5484 * If DO does not go high in 10 milliseconds, then error out.
5485 */
8fc897b0 5486 for (i = 0; i < 200; i++) {
1da177e4 5487 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 5488 if (eecd & E1000_EECD_DO) break;
1da177e4
LT		 5489 udelay(50);
5490 }
8fc897b0 5491 if (i == 200) {
1da177e4
LT		 5492 DEBUGOUT("EEPROM Write did not complete\n");
5493 return -E1000_ERR_EEPROM;
5494 }
5495
5496 /* Recover from write */
5497 e1000_standby_eeprom(hw);
5498
5499 words_written++;
5500 }
5501
5502 /* Send the write disable command to the EEPROM (3-bit opcode plus
5503 * 6/8-bit dummy address beginning with 10). It's less work to include
5504 * the 10 of the dummy address as part of the opcode than it is to shift
5505 * it over the correct number of bits for the address. This takes the
5506 * EEPROM out of write/erase mode.
5507 */
5508 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
406874a7 5509 (u16)(eeprom->opcode_bits + 2));
1da177e4 5510
406874a7 5511 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
1da177e4
LT		 5512
5513 return E1000_SUCCESS;
5514}
5515
2d7edb92
MC		 5516/******************************************************************************
5517 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5518 * in the eeprom cache and the non modified values in the currently active bank
5519 * to the new bank.
5520 *
5521 * hw - Struct containing variables accessed by shared code
5522 * offset - offset of word in the EEPROM to read
5523 * data - word read from the EEPROM
5524 * words - number of words to read
5525 *****************************************************************************/
406874a7 5526static s32
2d7edb92
MC		 5527e1000_commit_shadow_ram(struct e1000_hw *hw)
5528{
406874a7
JP		 5529 u32 attempts = 100000;
5530 u32 eecd = 0;
5531 u32 flop = 0;
5532 u32 i = 0;
5533 s32 error = E1000_SUCCESS;
5534 u32 old_bank_offset = 0;
5535 u32 new_bank_offset = 0;
5536 u8 low_byte = 0;
5537 u8 high_byte = 0;
c3033b01 5538 bool sector_write_failed = false;
2d7edb92
MC		 5539
5540 if (hw->mac_type == e1000_82573) {
cd94dd0b
AK		 5541 /* The flop register will be used to determine if flash type is STM */
5542 flop = E1000_READ_REG(hw, FLOP);
2d7edb92
MC		 5543 for (i=0; i < attempts; i++) {
5544 eecd = E1000_READ_REG(hw, EECD);
5545 if ((eecd & E1000_EECD_FLUPD) == 0) {
5546 break;
5547 }
5548 udelay(5);
5549 }
5550
5551 if (i == attempts) {
5552 return -E1000_ERR_EEPROM;
5553 }
5554
96838a40 5555 /* If STM opcode located in bits 15:8 of flop, reset firmware */
2d7edb92
MC		 5556 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5557 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5558 }
5559
5560 /* Perform the flash update */
5561 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5562
96838a40 5563 for (i=0; i < attempts; i++) {
2d7edb92
MC		 5564 eecd = E1000_READ_REG(hw, EECD);
5565 if ((eecd & E1000_EECD_FLUPD) == 0) {
5566 break;
5567 }
5568 udelay(5);
5569 }
5570
5571 if (i == attempts) {
5572 return -E1000_ERR_EEPROM;
5573 }
5574 }
5575
cd94dd0b
AK		 5576 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5577 /* We're writing to the opposite bank so if we're on bank 1,
5578 * write to bank 0 etc. We also need to erase the segment that
5579 * is going to be written */
5580 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5581 new_bank_offset = hw->flash_bank_size * 2;
5582 old_bank_offset = 0;
5583 e1000_erase_ich8_4k_segment(hw, 1);
5584 } else {
5585 old_bank_offset = hw->flash_bank_size * 2;
5586 new_bank_offset = 0;
5587 e1000_erase_ich8_4k_segment(hw, 0);
5588 }
5589
c3033b01 5590 sector_write_failed = false;
2a88c173
JK		 5591 /* Loop for every byte in the shadow RAM,
5592 * which is in units of words. */
5593 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5594 /* Determine whether to write the value stored
5595 * in the other NVM bank or a modified value stored
5596 * in the shadow RAM */
c3033b01 5597 if (hw->eeprom_shadow_ram[i].modified) {
406874a7 5598 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
2a88c173
JK		 5599 udelay(100);
5600 error = e1000_verify_write_ich8_byte(hw,
5601 (i << 1) + new_bank_offset, low_byte);
5602
5603 if (error != E1000_SUCCESS)
c3033b01 5604 sector_write_failed = true;
2a88c173 5605 else {
cd94dd0b 5606 high_byte =
406874a7 5607 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
cd94dd0b 5608 udelay(100);
2a88c173
JK		 5609 }
5610 } else {
5611 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5612 &low_byte);
5613 udelay(100);
5614 error = e1000_verify_write_ich8_byte(hw,
5615 (i << 1) + new_bank_offset, low_byte);
5616
5617 if (error != E1000_SUCCESS)
c3033b01 5618 sector_write_failed = true;
2a88c173 5619 else {
cd94dd0b
AK		 5620 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5621 &high_byte);
2a88c173 5622 udelay(100);
cd94dd0b 5623 }
2a88c173 5624 }
cd94dd0b 5625
c3033b01 5626 /* If the write of the low byte was successful, go ahead and
2a88c173
JK		 5627 * write the high byte while checking to make sure that if it
5628 * is the signature byte, then it is handled properly */
c3033b01 5629 if (!sector_write_failed) {
cd94dd0b
AK		 5630 /* If the word is 0x13, then make sure the signature bits
5631 * (15:14) are 11b until the commit has completed.
5632 * This will allow us to write 10b which indicates the
5633 * signature is valid. We want to do this after the write
5634 * has completed so that we don't mark the segment valid
5635 * while the write is still in progress */
2df7d59f
JK		 5636 if (i == E1000_ICH_NVM_SIG_WORD)
5637 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
cd94dd0b
AK		 5638
5639 error = e1000_verify_write_ich8_byte(hw,
2a88c173 5640 (i << 1) + new_bank_offset + 1, high_byte);
cd94dd0b 5641 if (error != E1000_SUCCESS)
c3033b01 5642 sector_write_failed = true;
cd94dd0b 5643
2a88c173
JK		 5644 } else {
5645 /* If the write failed then break from the loop and
5646 * return an error */
5647 break;
cd94dd0b 5648 }
2a88c173 5649 }
cd94dd0b 5650
2a88c173
JK		 5651 /* Don't bother writing the segment valid bits if sector
5652 * programming failed. */
c3033b01 5653 if (!sector_write_failed) {
2a88c173
JK		 5654 /* Finally validate the new segment by setting bit 15:14
5655 * to 10b in word 0x13 , this can be done without an
5656 * erase as well since these bits are 11 to start with
5657 * and we need to change bit 14 to 0b */
5658 e1000_read_ich8_byte(hw,
2df7d59f 5659 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
2a88c173
JK		 5660 &high_byte);
5661 high_byte &= 0xBF;
5662 error = e1000_verify_write_ich8_byte(hw,
2df7d59f 5663 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
2a88c173
JK		 5664 /* And invalidate the previously valid segment by setting
5665 * its signature word (0x13) high_byte to 0b. This can be
5666 * done without an erase because flash erase sets all bits
5667 * to 1's. We can write 1's to 0's without an erase */
5668 if (error == E1000_SUCCESS) {
cd94dd0b 5669 error = e1000_verify_write_ich8_byte(hw,
2df7d59f 5670 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
2a88c173 5671 }
cd94dd0b 5672
2a88c173
JK		 5673 /* Clear the now not used entry in the cache */
5674 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
c3033b01 5675 hw->eeprom_shadow_ram[i].modified = false;
2a88c173 5676 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
cd94dd0b 5677 }
2a88c173 5678 }
cd94dd0b
AK		 5679 }
5680
2d7edb92
MC		 5681 return error;
5682}
5683
1da177e4
LT		 5684/******************************************************************************
5685 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5686 * second function of dual function devices
5687 *
5688 * hw - Struct containing variables accessed by shared code
5689 *****************************************************************************/
406874a7 5690s32
1da177e4
LT		 5691e1000_read_mac_addr(struct e1000_hw * hw)
5692{
406874a7
JP		 5693 u16 offset;
5694 u16 eeprom_data, i;
1da177e4
LT		 5695
5696 DEBUGFUNC("e1000_read_mac_addr");
5697
8fc897b0 5698 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1da177e4 5699 offset = i >> 1;
8fc897b0 5700 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1da177e4
LT		 5701 DEBUGOUT("EEPROM Read Error\n");
5702 return -E1000_ERR_EEPROM;
5703 }
406874a7
JP		 5704 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
5705 hw->perm_mac_addr[i+1] = (u8) (eeprom_data >> 8);
1da177e4 5706 }
96838a40 5707
868d5309
MC		 5708 switch (hw->mac_type) {
5709 default:
5710 break;
5711 case e1000_82546:
5712 case e1000_82546_rev_3:
5713 case e1000_82571:
6418ecc6 5714 case e1000_80003es2lan:
8fc897b0 5715 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1da177e4 5716 hw->perm_mac_addr[5] ^= 0x01;
868d5309
MC		 5717 break;
5718 }
1da177e4 5719
8fc897b0 5720 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
1da177e4
LT		 5721 hw->mac_addr[i] = hw->perm_mac_addr[i];
5722 return E1000_SUCCESS;
5723}
5724
5725/******************************************************************************
5726 * Initializes receive address filters.
5727 *
5728 * hw - Struct containing variables accessed by shared code
5729 *
5730 * Places the MAC address in receive address register 0 and clears the rest
5731 * of the receive addresss registers. Clears the multicast table. Assumes
5732 * the receiver is in reset when the routine is called.
5733 *****************************************************************************/
3ad2cc67 5734static void
1da177e4
LT		 5735e1000_init_rx_addrs(struct e1000_hw *hw)
5736{
406874a7
JP		 5737 u32 i;
5738 u32 rar_num;
1da177e4
LT		 5739
5740 DEBUGFUNC("e1000_init_rx_addrs");
5741
5742 /* Setup the receive address. */
5743 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5744
5745 e1000_rar_set(hw, hw->mac_addr, 0);
5746
2d7edb92 5747 rar_num = E1000_RAR_ENTRIES;
868d5309
MC		 5748
5749 /* Reserve a spot for the Locally Administered Address to work around
5750 * an 82571 issue in which a reset on one port will reload the MAC on
5751 * the other port. */
c3033b01 5752 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
868d5309 5753 rar_num -= 1;
cd94dd0b
AK		 5754 if (hw->mac_type == e1000_ich8lan)
5755 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5756
1da177e4
LT		 5757 /* Zero out the other 15 receive addresses. */
5758 DEBUGOUT("Clearing RAR[1-15]\n");
8fc897b0 5759 for (i = 1; i < rar_num; i++) {
1da177e4 5760 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5761 E1000_WRITE_FLUSH(hw);
1da177e4 5762 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5763 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5764 }
5765}
5766
1da177e4
LT		 5767/******************************************************************************
5768 * Hashes an address to determine its location in the multicast table
5769 *
5770 * hw - Struct containing variables accessed by shared code
5771 * mc_addr - the multicast address to hash
5772 *****************************************************************************/
406874a7 5773u32
1da177e4 5774e1000_hash_mc_addr(struct e1000_hw *hw,
406874a7 5775 u8 *mc_addr)
1da177e4 5776{
406874a7 5777 u32 hash_value = 0;
1da177e4
LT		 5778
5779 /* The portion of the address that is used for the hash table is
5780 * determined by the mc_filter_type setting.
5781 */
5782 switch (hw->mc_filter_type) {
5783 /* [0] [1] [2] [3] [4] [5]
5784 * 01 AA 00 12 34 56
5785 * LSB MSB
5786 */
5787 case 0:
cd94dd0b
AK		 5788 if (hw->mac_type == e1000_ich8lan) {
5789 /* [47:38] i.e. 0x158 for above example address */
406874a7 5790 hash_value = ((mc_addr[4] >> 6) | (((u16) mc_addr[5]) << 2));
cd94dd0b
AK		 5791 } else {
5792 /* [47:36] i.e. 0x563 for above example address */
406874a7 5793 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
cd94dd0b 5794 }
1da177e4
LT		 5795 break;
5796 case 1:
cd94dd0b
AK		 5797 if (hw->mac_type == e1000_ich8lan) {
5798 /* [46:37] i.e. 0x2B1 for above example address */
406874a7 5799 hash_value = ((mc_addr[4] >> 5) | (((u16) mc_addr[5]) << 3));
cd94dd0b
AK		 5800 } else {
5801 /* [46:35] i.e. 0xAC6 for above example address */
406874a7 5802 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
cd94dd0b 5803 }
1da177e4
LT		 5804 break;
5805 case 2:
cd94dd0b
AK		 5806 if (hw->mac_type == e1000_ich8lan) {
5807 /*[45:36] i.e. 0x163 for above example address */
406874a7 5808 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
cd94dd0b
AK		 5809 } else {
5810 /* [45:34] i.e. 0x5D8 for above example address */
406874a7 5811 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
cd94dd0b 5812 }
1da177e4
LT		 5813 break;
5814 case 3:
cd94dd0b
AK		 5815 if (hw->mac_type == e1000_ich8lan) {
5816 /* [43:34] i.e. 0x18D for above example address */
406874a7 5817 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
cd94dd0b
AK		 5818 } else {
5819 /* [43:32] i.e. 0x634 for above example address */
406874a7 5820 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
cd94dd0b 5821 }
1da177e4
LT		 5822 break;
5823 }
5824
5825 hash_value &= 0xFFF;
cd94dd0b
AK		 5826 if (hw->mac_type == e1000_ich8lan)
5827 hash_value &= 0x3FF;
2d7edb92 5828
1da177e4
LT		 5829 return hash_value;
5830}
5831
5832/******************************************************************************
5833 * Sets the bit in the multicast table corresponding to the hash value.
5834 *
5835 * hw - Struct containing variables accessed by shared code
5836 * hash_value - Multicast address hash value
5837 *****************************************************************************/
5838void
5839e1000_mta_set(struct e1000_hw *hw,
406874a7 5840 u32 hash_value)
1da177e4 5841{
406874a7
JP		 5842 u32 hash_bit, hash_reg;
5843 u32 mta;
5844 u32 temp;
1da177e4
LT		 5845
5846 /* The MTA is a register array of 128 32-bit registers.
5847 * It is treated like an array of 4096 bits. We want to set
5848 * bit BitArray[hash_value]. So we figure out what register
5849 * the bit is in, read it, OR in the new bit, then write
5850 * back the new value. The register is determined by the
5851 * upper 7 bits of the hash value and the bit within that
5852 * register are determined by the lower 5 bits of the value.
5853 */
5854 hash_reg = (hash_value >> 5) & 0x7F;
cd94dd0b
AK		 5855 if (hw->mac_type == e1000_ich8lan)
5856 hash_reg &= 0x1F;
90fb5135 5857
1da177e4
LT		 5858 hash_bit = hash_value & 0x1F;
5859
5860 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5861
5862 mta |= (1 << hash_bit);
5863
5864 /* If we are on an 82544 and we are trying to write an odd offset
5865 * in the MTA, save off the previous entry before writing and
5866 * restore the old value after writing.
5867 */
8fc897b0 5868 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
1da177e4
LT		 5869 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5870 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5871 E1000_WRITE_FLUSH(hw);
1da177e4 5872 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4ca213a6 5873 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5874 } else {
5875 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5876 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5877 }
5878}
5879
5880/******************************************************************************
5881 * Puts an ethernet address into a receive address register.
5882 *
5883 * hw - Struct containing variables accessed by shared code
5884 * addr - Address to put into receive address register
5885 * index - Receive address register to write
5886 *****************************************************************************/
5887void
5888e1000_rar_set(struct e1000_hw *hw,
406874a7
JP		 5889 u8 *addr,
5890 u32 index)
1da177e4 5891{
406874a7 5892 u32 rar_low, rar_high;
1da177e4
LT		 5893
5894 /* HW expects these in little endian so we reverse the byte order
5895 * from network order (big endian) to little endian
5896 */
406874a7
JP		 5897 rar_low = ((u32) addr[0] |
5898 ((u32) addr[1] << 8) |
5899 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5900 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1da177e4 5901
8df06e50
JK		 5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5903 * unit hang.
5904 *
5905 * Description:
5906 * If there are any Rx frames queued up or otherwise present in the HW
5907 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5908 * hang. To work around this issue, we have to disable receives and
5909 * flush out all Rx frames before we enable RSS. To do so, we modify we
5910 * redirect all Rx traffic to manageability and then reset the HW.
5911 * This flushes away Rx frames, and (since the redirections to
5912 * manageability persists across resets) keeps new ones from coming in
5913 * while we work. Then, we clear the Address Valid AV bit for all MAC
5914 * addresses and undo the re-direction to manageability.
5915 * Now, frames are coming in again, but the MAC won't accept them, so
5916 * far so good. We now proceed to initialize RSS (if necessary) and
5917 * configure the Rx unit. Last, we re-enable the AV bits and continue
5918 * on our merry way.
5919 */
5920 switch (hw->mac_type) {
5921 case e1000_82571:
5922 case e1000_82572:
6418ecc6 5923 case e1000_80003es2lan:
c3033b01 5924 if (hw->leave_av_bit_off)
8df06e50
JK		 5925 break;
5926 default:
5927 /* Indicate to hardware the Address is Valid. */
5928 rar_high |= E1000_RAH_AV;
5929 break;
5930 }
1da177e4
LT		 5931
5932 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4ca213a6 5933 E1000_WRITE_FLUSH(hw);
1da177e4 5934 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4ca213a6 5935 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5936}
5937
5938/******************************************************************************
5939 * Writes a value to the specified offset in the VLAN filter table.
5940 *
5941 * hw - Struct containing variables accessed by shared code
5942 * offset - Offset in VLAN filer table to write
5943 * value - Value to write into VLAN filter table
5944 *****************************************************************************/
5945void
5946e1000_write_vfta(struct e1000_hw *hw,
406874a7
JP		 5947 u32 offset,
5948 u32 value)
1da177e4 5949{
406874a7 5950 u32 temp;
1da177e4 5951
cd94dd0b
AK		 5952 if (hw->mac_type == e1000_ich8lan)
5953 return;
5954
5955 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
1da177e4
LT		 5956 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5957 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5958 E1000_WRITE_FLUSH(hw);
1da177e4 5959 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4ca213a6 5960 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5961 } else {
5962 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5963 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5964 }
5965}
5966
5967/******************************************************************************
5968 * Clears the VLAN filer table
5969 *
5970 * hw - Struct containing variables accessed by shared code
5971 *****************************************************************************/
3ad2cc67 5972static void
1da177e4
LT		 5973e1000_clear_vfta(struct e1000_hw *hw)
5974{
406874a7
JP		 5975 u32 offset;
5976 u32 vfta_value = 0;
5977 u32 vfta_offset = 0;
5978 u32 vfta_bit_in_reg = 0;
2d7edb92 5979
cd94dd0b
AK		 5980 if (hw->mac_type == e1000_ich8lan)
5981 return;
5982
2d7edb92
MC		 5983 if (hw->mac_type == e1000_82573) {
5984 if (hw->mng_cookie.vlan_id != 0) {
5985 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5986 * ID. The following operations determine which 32b entry
5987 * (i.e. offset) into the array we want to set the VLAN ID
5988 * (i.e. bit) of the manageability unit. */
5989 vfta_offset = (hw->mng_cookie.vlan_id >>
5990 E1000_VFTA_ENTRY_SHIFT) &
5991 E1000_VFTA_ENTRY_MASK;
5992 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5993 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5994 }
5995 }
5996 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5997 /* If the offset we want to clear is the same offset of the
5998 * manageability VLAN ID, then clear all bits except that of the
5999 * manageability unit */
6000 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6001 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4ca213a6 6002 E1000_WRITE_FLUSH(hw);
2d7edb92 6003 }
1da177e4
LT		 6004}
6005
406874a7 6006static s32
1da177e4
LT		 6007e1000_id_led_init(struct e1000_hw * hw)
6008{
406874a7
JP		 6009 u32 ledctl;
6010 const u32 ledctl_mask = 0x000000FF;
6011 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6012 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6013 u16 eeprom_data, i, temp;
6014 const u16 led_mask = 0x0F;
1da177e4
LT		 6015
6016 DEBUGFUNC("e1000_id_led_init");
6017
8fc897b0 6018 if (hw->mac_type < e1000_82540) {
1da177e4
LT		 6019 /* Nothing to do */
6020 return E1000_SUCCESS;
6021 }
6022
6023 ledctl = E1000_READ_REG(hw, LEDCTL);
6024 hw->ledctl_default = ledctl;
6025 hw->ledctl_mode1 = hw->ledctl_default;
6026 hw->ledctl_mode2 = hw->ledctl_default;
6027
8fc897b0 6028 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
1da177e4
LT		 6029 DEBUGOUT("EEPROM Read Error\n");
6030 return -E1000_ERR_EEPROM;
6031 }
cd94dd0b
AK		 6032
6033 if ((hw->mac_type == e1000_82573) &&
6034 (eeprom_data == ID_LED_RESERVED_82573))
6035 eeprom_data = ID_LED_DEFAULT_82573;
6036 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6037 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6038 if (hw->mac_type == e1000_ich8lan)
6039 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6040 else
6041 eeprom_data = ID_LED_DEFAULT;
6042 }
90fb5135 6043
cd94dd0b 6044 for (i = 0; i < 4; i++) {
1da177e4 6045 temp = (eeprom_data >> (i << 2)) & led_mask;
8fc897b0 6046 switch (temp) {
1da177e4
LT		 6047 case ID_LED_ON1_DEF2:
6048 case ID_LED_ON1_ON2:
6049 case ID_LED_ON1_OFF2:
6050 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6051 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6052 break;
6053 case ID_LED_OFF1_DEF2:
6054 case ID_LED_OFF1_ON2:
6055 case ID_LED_OFF1_OFF2:
6056 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6057 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6058 break;
6059 default:
6060 /* Do nothing */
6061 break;
6062 }
8fc897b0 6063 switch (temp) {
1da177e4
LT		 6064 case ID_LED_DEF1_ON2:
6065 case ID_LED_ON1_ON2:
6066 case ID_LED_OFF1_ON2:
6067 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6068 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6069 break;
6070 case ID_LED_DEF1_OFF2:
6071 case ID_LED_ON1_OFF2:
6072 case ID_LED_OFF1_OFF2:
6073 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6074 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6075 break;
6076 default:
6077 /* Do nothing */
6078 break;
6079 }
6080 }
6081 return E1000_SUCCESS;
6082}
6083
6084/******************************************************************************
6085 * Prepares SW controlable LED for use and saves the current state of the LED.
6086 *
6087 * hw - Struct containing variables accessed by shared code
6088 *****************************************************************************/
406874a7 6089s32
1da177e4
LT		 6090e1000_setup_led(struct e1000_hw *hw)
6091{
406874a7
JP		 6092 u32 ledctl;
6093 s32 ret_val = E1000_SUCCESS;
1da177e4
LT		 6094
6095 DEBUGFUNC("e1000_setup_led");
6096
8fc897b0 6097 switch (hw->mac_type) {
1da177e4
LT		 6098 case e1000_82542_rev2_0:
6099 case e1000_82542_rev2_1:
6100 case e1000_82543:
6101 case e1000_82544:
6102 /* No setup necessary */
6103 break;
6104 case e1000_82541:
6105 case e1000_82547:
6106 case e1000_82541_rev_2:
6107 case e1000_82547_rev_2:
6108 /* Turn off PHY Smart Power Down (if enabled) */
6109 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6110 &hw->phy_spd_default);
8fc897b0 6111 if (ret_val)
1da177e4
LT		 6112 return ret_val;
6113 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
406874a7 6114 (u16)(hw->phy_spd_default &
1da177e4 6115 ~IGP01E1000_GMII_SPD));
8fc897b0 6116 if (ret_val)
1da177e4
LT		 6117 return ret_val;
6118 /* Fall Through */
6119 default:
8fc897b0 6120 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6121 ledctl = E1000_READ_REG(hw, LEDCTL);
6122 /* Save current LEDCTL settings */
6123 hw->ledctl_default = ledctl;
6124 /* Turn off LED0 */
6125 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6126 E1000_LEDCTL_LED0_BLINK |
6127 E1000_LEDCTL_LED0_MODE_MASK);
6128 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6129 E1000_LEDCTL_LED0_MODE_SHIFT);
6130 E1000_WRITE_REG(hw, LEDCTL, ledctl);
8fc897b0 6131 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 6132 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6133 break;
6134 }
6135
6136 return E1000_SUCCESS;
6137}
6138
8fc897b0 6139
f1b3a853
AK		 6140/******************************************************************************
6141 * Used on 82571 and later Si that has LED blink bits.
6142 * Callers must use their own timer and should have already called
6143 * e1000_id_led_init()
6144 * Call e1000_cleanup led() to stop blinking
6145 *
6146 * hw - Struct containing variables accessed by shared code
6147 *****************************************************************************/
406874a7 6148s32
f1b3a853
AK		 6149e1000_blink_led_start(struct e1000_hw *hw)
6150{
406874a7
JP		 6151 s16 i;
6152 u32 ledctl_blink = 0;
f1b3a853
AK		 6153
6154 DEBUGFUNC("e1000_id_led_blink_on");
6155
6156 if (hw->mac_type < e1000_82571) {
6157 /* Nothing to do */
6158 return E1000_SUCCESS;
6159 }
6160 if (hw->media_type == e1000_media_type_fiber) {
6161 /* always blink LED0 for PCI-E fiber */
6162 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6163 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6164 } else {
6165 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6166 ledctl_blink = hw->ledctl_mode2;
6167 for (i=0; i < 4; i++)
6168 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6169 E1000_LEDCTL_MODE_LED_ON)
6170 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6171 }
6172
6173 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6174
6175 return E1000_SUCCESS;
6176}
6177
1da177e4
LT		 6178/******************************************************************************
6179 * Restores the saved state of the SW controlable LED.
6180 *
6181 * hw - Struct containing variables accessed by shared code
6182 *****************************************************************************/
406874a7 6183s32
1da177e4
LT		 6184e1000_cleanup_led(struct e1000_hw *hw)
6185{
406874a7 6186 s32 ret_val = E1000_SUCCESS;
1da177e4
LT		 6187
6188 DEBUGFUNC("e1000_cleanup_led");
6189
8fc897b0 6190 switch (hw->mac_type) {
1da177e4
LT		 6191 case e1000_82542_rev2_0:
6192 case e1000_82542_rev2_1:
6193 case e1000_82543:
6194 case e1000_82544:
6195 /* No cleanup necessary */
6196 break;
6197 case e1000_82541:
6198 case e1000_82547:
6199 case e1000_82541_rev_2:
6200 case e1000_82547_rev_2:
6201 /* Turn on PHY Smart Power Down (if previously enabled) */
6202 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6203 hw->phy_spd_default);
8fc897b0 6204 if (ret_val)
1da177e4
LT		 6205 return ret_val;
6206 /* Fall Through */
6207 default:
cd94dd0b
AK		 6208 if (hw->phy_type == e1000_phy_ife) {
6209 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6210 break;
6211 }
1da177e4
LT		 6212 /* Restore LEDCTL settings */
6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6214 break;
6215 }
6216
6217 return E1000_SUCCESS;
6218}
6219
6220/******************************************************************************
6221 * Turns on the software controllable LED
6222 *
6223 * hw - Struct containing variables accessed by shared code
6224 *****************************************************************************/
406874a7 6225s32
1da177e4
LT		 6226e1000_led_on(struct e1000_hw *hw)
6227{
406874a7 6228 u32 ctrl = E1000_READ_REG(hw, CTRL);
1da177e4
LT		 6229
6230 DEBUGFUNC("e1000_led_on");
6231
8fc897b0 6232 switch (hw->mac_type) {
1da177e4
LT		 6233 case e1000_82542_rev2_0:
6234 case e1000_82542_rev2_1:
6235 case e1000_82543:
6236 /* Set SW Defineable Pin 0 to turn on the LED */
6237 ctrl |= E1000_CTRL_SWDPIN0;
6238 ctrl |= E1000_CTRL_SWDPIO0;
6239 break;
6240 case e1000_82544:
8fc897b0 6241 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6242 /* Set SW Defineable Pin 0 to turn on the LED */
6243 ctrl |= E1000_CTRL_SWDPIN0;
6244 ctrl |= E1000_CTRL_SWDPIO0;
6245 } else {
6246 /* Clear SW Defineable Pin 0 to turn on the LED */
6247 ctrl &= ~E1000_CTRL_SWDPIN0;
6248 ctrl |= E1000_CTRL_SWDPIO0;
6249 }
6250 break;
6251 default:
8fc897b0 6252 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6253 /* Clear SW Defineable Pin 0 to turn on the LED */
6254 ctrl &= ~E1000_CTRL_SWDPIN0;
6255 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6256 } else if (hw->phy_type == e1000_phy_ife) {
6257 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6258 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6259 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6260 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6261 return E1000_SUCCESS;
6262 }
6263 break;
6264 }
6265
6266 E1000_WRITE_REG(hw, CTRL, ctrl);
6267
6268 return E1000_SUCCESS;
6269}
6270
6271/******************************************************************************
6272 * Turns off the software controllable LED
6273 *
6274 * hw - Struct containing variables accessed by shared code
6275 *****************************************************************************/
406874a7 6276s32
1da177e4
LT		 6277e1000_led_off(struct e1000_hw *hw)
6278{
406874a7 6279 u32 ctrl = E1000_READ_REG(hw, CTRL);
1da177e4
LT		 6280
6281 DEBUGFUNC("e1000_led_off");
6282
8fc897b0 6283 switch (hw->mac_type) {
1da177e4
LT		 6284 case e1000_82542_rev2_0:
6285 case e1000_82542_rev2_1:
6286 case e1000_82543:
6287 /* Clear SW Defineable Pin 0 to turn off the LED */
6288 ctrl &= ~E1000_CTRL_SWDPIN0;
6289 ctrl |= E1000_CTRL_SWDPIO0;
6290 break;
6291 case e1000_82544:
8fc897b0 6292 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6293 /* Clear SW Defineable Pin 0 to turn off the LED */
6294 ctrl &= ~E1000_CTRL_SWDPIN0;
6295 ctrl |= E1000_CTRL_SWDPIO0;
6296 } else {
6297 /* Set SW Defineable Pin 0 to turn off the LED */
6298 ctrl |= E1000_CTRL_SWDPIN0;
6299 ctrl |= E1000_CTRL_SWDPIO0;
6300 }
6301 break;
6302 default:
8fc897b0 6303 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6304 /* Set SW Defineable Pin 0 to turn off the LED */
6305 ctrl |= E1000_CTRL_SWDPIN0;
6306 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6307 } else if (hw->phy_type == e1000_phy_ife) {
6308 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6309 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6310 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6311 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6312 return E1000_SUCCESS;
6313 }
6314 break;
6315 }
6316
6317 E1000_WRITE_REG(hw, CTRL, ctrl);
6318
6319 return E1000_SUCCESS;
6320}
6321
6322/******************************************************************************
6323 * Clears all hardware statistics counters.
6324 *
6325 * hw - Struct containing variables accessed by shared code
6326 *****************************************************************************/
35574764 6327static void
1da177e4
LT		 6328e1000_clear_hw_cntrs(struct e1000_hw *hw)
6329{
406874a7 6330 volatile u32 temp;
1da177e4
LT		 6331
6332 temp = E1000_READ_REG(hw, CRCERRS);
6333 temp = E1000_READ_REG(hw, SYMERRS);
6334 temp = E1000_READ_REG(hw, MPC);
6335 temp = E1000_READ_REG(hw, SCC);
6336 temp = E1000_READ_REG(hw, ECOL);
6337 temp = E1000_READ_REG(hw, MCC);
6338 temp = E1000_READ_REG(hw, LATECOL);
6339 temp = E1000_READ_REG(hw, COLC);
6340 temp = E1000_READ_REG(hw, DC);
6341 temp = E1000_READ_REG(hw, SEC);
6342 temp = E1000_READ_REG(hw, RLEC);
6343 temp = E1000_READ_REG(hw, XONRXC);
6344 temp = E1000_READ_REG(hw, XONTXC);
6345 temp = E1000_READ_REG(hw, XOFFRXC);
6346 temp = E1000_READ_REG(hw, XOFFTXC);
6347 temp = E1000_READ_REG(hw, FCRUC);
cd94dd0b
AK		 6348
6349 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6350 temp = E1000_READ_REG(hw, PRC64);
6351 temp = E1000_READ_REG(hw, PRC127);
6352 temp = E1000_READ_REG(hw, PRC255);
6353 temp = E1000_READ_REG(hw, PRC511);
6354 temp = E1000_READ_REG(hw, PRC1023);
6355 temp = E1000_READ_REG(hw, PRC1522);
cd94dd0b
AK		 6356 }
6357
1da177e4
LT		 6358 temp = E1000_READ_REG(hw, GPRC);
6359 temp = E1000_READ_REG(hw, BPRC);
6360 temp = E1000_READ_REG(hw, MPRC);
6361 temp = E1000_READ_REG(hw, GPTC);
6362 temp = E1000_READ_REG(hw, GORCL);
6363 temp = E1000_READ_REG(hw, GORCH);
6364 temp = E1000_READ_REG(hw, GOTCL);
6365 temp = E1000_READ_REG(hw, GOTCH);
6366 temp = E1000_READ_REG(hw, RNBC);
6367 temp = E1000_READ_REG(hw, RUC);
6368 temp = E1000_READ_REG(hw, RFC);
6369 temp = E1000_READ_REG(hw, ROC);
6370 temp = E1000_READ_REG(hw, RJC);
6371 temp = E1000_READ_REG(hw, TORL);
6372 temp = E1000_READ_REG(hw, TORH);
6373 temp = E1000_READ_REG(hw, TOTL);
6374 temp = E1000_READ_REG(hw, TOTH);
6375 temp = E1000_READ_REG(hw, TPR);
6376 temp = E1000_READ_REG(hw, TPT);
cd94dd0b
AK		 6377
6378 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6379 temp = E1000_READ_REG(hw, PTC64);
6380 temp = E1000_READ_REG(hw, PTC127);
6381 temp = E1000_READ_REG(hw, PTC255);
6382 temp = E1000_READ_REG(hw, PTC511);
6383 temp = E1000_READ_REG(hw, PTC1023);
6384 temp = E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 6385 }
6386
1da177e4
LT		 6387 temp = E1000_READ_REG(hw, MPTC);
6388 temp = E1000_READ_REG(hw, BPTC);
6389
8fc897b0 6390 if (hw->mac_type < e1000_82543) return;
1da177e4
LT		 6391
6392 temp = E1000_READ_REG(hw, ALGNERRC);
6393 temp = E1000_READ_REG(hw, RXERRC);
6394 temp = E1000_READ_REG(hw, TNCRS);
6395 temp = E1000_READ_REG(hw, CEXTERR);
6396 temp = E1000_READ_REG(hw, TSCTC);
6397 temp = E1000_READ_REG(hw, TSCTFC);
6398
8fc897b0 6399 if (hw->mac_type <= e1000_82544) return;
1da177e4
LT		 6400
6401 temp = E1000_READ_REG(hw, MGTPRC);
6402 temp = E1000_READ_REG(hw, MGTPDC);
6403 temp = E1000_READ_REG(hw, MGTPTC);
2d7edb92 6404
8fc897b0 6405 if (hw->mac_type <= e1000_82547_rev_2) return;
2d7edb92
MC		 6406
6407 temp = E1000_READ_REG(hw, IAC);
6408 temp = E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 6409
6410 if (hw->mac_type == e1000_ich8lan) return;
6411
2d7edb92
MC		 6412 temp = E1000_READ_REG(hw, ICRXPTC);
6413 temp = E1000_READ_REG(hw, ICRXATC);
6414 temp = E1000_READ_REG(hw, ICTXPTC);
6415 temp = E1000_READ_REG(hw, ICTXATC);
6416 temp = E1000_READ_REG(hw, ICTXQEC);
6417 temp = E1000_READ_REG(hw, ICTXQMTC);
6418 temp = E1000_READ_REG(hw, ICRXDMTC);
1da177e4
LT		 6419}
6420
6421/******************************************************************************
6422 * Resets Adaptive IFS to its default state.
6423 *
6424 * hw - Struct containing variables accessed by shared code
6425 *
6426 * Call this after e1000_init_hw. You may override the IFS defaults by setting
c3033b01 6427 * hw->ifs_params_forced to true. However, you must initialize hw->
1da177e4
LT		 6428 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6429 * before calling this function.
6430 *****************************************************************************/
6431void
6432e1000_reset_adaptive(struct e1000_hw *hw)
6433{
6434 DEBUGFUNC("e1000_reset_adaptive");
6435
8fc897b0
AK		 6436 if (hw->adaptive_ifs) {
6437 if (!hw->ifs_params_forced) {
1da177e4
LT		 6438 hw->current_ifs_val = 0;
6439 hw->ifs_min_val = IFS_MIN;
6440 hw->ifs_max_val = IFS_MAX;
6441 hw->ifs_step_size = IFS_STEP;
6442 hw->ifs_ratio = IFS_RATIO;
6443 }
c3033b01 6444 hw->in_ifs_mode = false;
1da177e4
LT		 6445 E1000_WRITE_REG(hw, AIT, 0);
6446 } else {
6447 DEBUGOUT("Not in Adaptive IFS mode!\n");
6448 }
6449}
6450
6451/******************************************************************************
6452 * Called during the callback/watchdog routine to update IFS value based on
6453 * the ratio of transmits to collisions.
6454 *
6455 * hw - Struct containing variables accessed by shared code
6456 * tx_packets - Number of transmits since last callback
6457 * total_collisions - Number of collisions since last callback
6458 *****************************************************************************/
6459void
6460e1000_update_adaptive(struct e1000_hw *hw)
6461{
6462 DEBUGFUNC("e1000_update_adaptive");
6463
8fc897b0
AK		 6464 if (hw->adaptive_ifs) {
6465 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6466 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
c3033b01 6467 hw->in_ifs_mode = true;
8fc897b0
AK		 6468 if (hw->current_ifs_val < hw->ifs_max_val) {
6469 if (hw->current_ifs_val == 0)
1da177e4
LT		 6470 hw->current_ifs_val = hw->ifs_min_val;
6471 else
6472 hw->current_ifs_val += hw->ifs_step_size;
6473 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6474 }
6475 }
6476 } else {
8fc897b0 6477 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
1da177e4 6478 hw->current_ifs_val = 0;
c3033b01 6479 hw->in_ifs_mode = false;
1da177e4
LT		 6480 E1000_WRITE_REG(hw, AIT, 0);
6481 }
6482 }
6483 } else {
6484 DEBUGOUT("Not in Adaptive IFS mode!\n");
6485 }
6486}
6487
6488/******************************************************************************
6489 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6490 *
6491 * hw - Struct containing variables accessed by shared code
6492 * frame_len - The length of the frame in question
6493 * mac_addr - The Ethernet destination address of the frame in question
6494 *****************************************************************************/
6495void
6496e1000_tbi_adjust_stats(struct e1000_hw *hw,
6497 struct e1000_hw_stats *stats,
406874a7
JP		 6498 u32 frame_len,
6499 u8 *mac_addr)
1da177e4 6500{
406874a7 6501 u64 carry_bit;
1da177e4
LT		 6502
6503 /* First adjust the frame length. */
6504 frame_len--;
6505 /* We need to adjust the statistics counters, since the hardware
6506 * counters overcount this packet as a CRC error and undercount
6507 * the packet as a good packet
6508 */
6509 /* This packet should not be counted as a CRC error. */
6510 stats->crcerrs--;
6511 /* This packet does count as a Good Packet Received. */
6512 stats->gprc++;
6513
6514 /* Adjust the Good Octets received counters */
6515 carry_bit = 0x80000000 & stats->gorcl;
6516 stats->gorcl += frame_len;
6517 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6518 * Received Count) was one before the addition,
6519 * AND it is zero after, then we lost the carry out,
6520 * need to add one to Gorch (Good Octets Received Count High).
6521 * This could be simplified if all environments supported
6522 * 64-bit integers.
6523 */
8fc897b0 6524 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
1da177e4
LT		 6525 stats->gorch++;
6526 /* Is this a broadcast or multicast? Check broadcast first,
6527 * since the test for a multicast frame will test positive on
6528 * a broadcast frame.
6529 */
406874a7 6530 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
1da177e4
LT		 6531 /* Broadcast packet */
6532 stats->bprc++;
8fc897b0 6533 else if (*mac_addr & 0x01)
1da177e4
LT		 6534 /* Multicast packet */
6535 stats->mprc++;
6536
8fc897b0 6537 if (frame_len == hw->max_frame_size) {
1da177e4
LT		 6538 /* In this case, the hardware has overcounted the number of
6539 * oversize frames.
6540 */
8fc897b0 6541 if (stats->roc > 0)
1da177e4
LT		 6542 stats->roc--;
6543 }
6544
6545 /* Adjust the bin counters when the extra byte put the frame in the
6546 * wrong bin. Remember that the frame_len was adjusted above.
6547 */
8fc897b0 6548 if (frame_len == 64) {
1da177e4
LT		 6549 stats->prc64++;
6550 stats->prc127--;
8fc897b0 6551 } else if (frame_len == 127) {
1da177e4
LT		 6552 stats->prc127++;
6553 stats->prc255--;
8fc897b0 6554 } else if (frame_len == 255) {
1da177e4
LT		 6555 stats->prc255++;
6556 stats->prc511--;
8fc897b0 6557 } else if (frame_len == 511) {
1da177e4
LT		 6558 stats->prc511++;
6559 stats->prc1023--;
8fc897b0 6560 } else if (frame_len == 1023) {
1da177e4
LT		 6561 stats->prc1023++;
6562 stats->prc1522--;
8fc897b0 6563 } else if (frame_len == 1522) {
1da177e4
LT		 6564 stats->prc1522++;
6565 }
6566}
6567
6568/******************************************************************************
6569 * Gets the current PCI bus type, speed, and width of the hardware
6570 *
6571 * hw - Struct containing variables accessed by shared code
6572 *****************************************************************************/
6573void
6574e1000_get_bus_info(struct e1000_hw *hw)
6575{
406874a7
JP		 6576 s32 ret_val;
6577 u16 pci_ex_link_status;
6578 u32 status;
1da177e4
LT		 6579
6580 switch (hw->mac_type) {
6581 case e1000_82542_rev2_0:
6582 case e1000_82542_rev2_1:
c3813ae6 6583 hw->bus_type = e1000_bus_type_pci;
1da177e4
LT		 6584 hw->bus_speed = e1000_bus_speed_unknown;
6585 hw->bus_width = e1000_bus_width_unknown;
6586 break;
caeccb68 6587 case e1000_82571:
868d5309 6588 case e1000_82572:
2d7edb92 6589 case e1000_82573:
caeccb68 6590 case e1000_80003es2lan:
fd803241
JK		 6591 hw->bus_type = e1000_bus_type_pci_express;
6592 hw->bus_speed = e1000_bus_speed_2500;
caeccb68
JK		 6593 ret_val = e1000_read_pcie_cap_reg(hw,
6594 PCI_EX_LINK_STATUS,
6595 &pci_ex_link_status);
6596 if (ret_val)
6597 hw->bus_width = e1000_bus_width_unknown;
6598 else
6599 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6600 PCI_EX_LINK_WIDTH_SHIFT;
fd803241 6601 break;
cd94dd0b 6602 case e1000_ich8lan:
2d7edb92
MC		 6603 hw->bus_type = e1000_bus_type_pci_express;
6604 hw->bus_speed = e1000_bus_speed_2500;
caeccb68 6605 hw->bus_width = e1000_bus_width_pciex_1;
2d7edb92 6606 break;
1da177e4
LT		 6607 default:
6608 status = E1000_READ_REG(hw, STATUS);
6609 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6610 e1000_bus_type_pcix : e1000_bus_type_pci;
6611
8fc897b0 6612 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
1da177e4
LT		 6613 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6614 e1000_bus_speed_66 : e1000_bus_speed_120;
8fc897b0 6615 } else if (hw->bus_type == e1000_bus_type_pci) {
1da177e4
LT		 6616 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6617 e1000_bus_speed_66 : e1000_bus_speed_33;
6618 } else {
6619 switch (status & E1000_STATUS_PCIX_SPEED) {
6620 case E1000_STATUS_PCIX_SPEED_66:
6621 hw->bus_speed = e1000_bus_speed_66;
6622 break;
6623 case E1000_STATUS_PCIX_SPEED_100:
6624 hw->bus_speed = e1000_bus_speed_100;
6625 break;
6626 case E1000_STATUS_PCIX_SPEED_133:
6627 hw->bus_speed = e1000_bus_speed_133;
6628 break;
6629 default:
6630 hw->bus_speed = e1000_bus_speed_reserved;
6631 break;
6632 }
6633 }
6634 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6635 e1000_bus_width_64 : e1000_bus_width_32;
6636 break;
6637 }
6638}
1da177e4
LT		 6639
6640/******************************************************************************
6641 * Writes a value to one of the devices registers using port I/O (as opposed to
6642 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6643 *
6644 * hw - Struct containing variables accessed by shared code
6645 * offset - offset to write to
6646 * value - value to write
6647 *****************************************************************************/
3ad2cc67 6648static void
1da177e4 6649e1000_write_reg_io(struct e1000_hw *hw,
406874a7
JP		 6650 u32 offset,
6651 u32 value)
1da177e4
LT		 6652{
6653 unsigned long io_addr = hw->io_base;
6654 unsigned long io_data = hw->io_base + 4;
6655
6656 e1000_io_write(hw, io_addr, offset);
6657 e1000_io_write(hw, io_data, value);
6658}
6659
1da177e4
LT		 6660/******************************************************************************
6661 * Estimates the cable length.
6662 *
6663 * hw - Struct containing variables accessed by shared code
6664 * min_length - The estimated minimum length
6665 * max_length - The estimated maximum length
6666 *
6667 * returns: - E1000_ERR_XXX
6668 * E1000_SUCCESS
6669 *
6670 * This function always returns a ranged length (minimum & maximum).
6671 * So for M88 phy's, this function interprets the one value returned from the
6672 * register to the minimum and maximum range.
6673 * For IGP phy's, the function calculates the range by the AGC registers.
6674 *****************************************************************************/
406874a7 6675static s32
1da177e4 6676e1000_get_cable_length(struct e1000_hw *hw,
406874a7
JP		 6677 u16 *min_length,
6678 u16 *max_length)
1da177e4 6679{
406874a7
JP		 6680 s32 ret_val;
6681 u16 agc_value = 0;
6682 u16 i, phy_data;
6683 u16 cable_length;
1da177e4
LT		 6684
6685 DEBUGFUNC("e1000_get_cable_length");
6686
6687 *min_length = *max_length = 0;
6688
6689 /* Use old method for Phy older than IGP */
8fc897b0 6690 if (hw->phy_type == e1000_phy_m88) {
2d7edb92 6691
1da177e4
LT		 6692 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6693 &phy_data);
8fc897b0 6694 if (ret_val)
1da177e4
LT		 6695 return ret_val;
6696 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6697 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6698
6699 /* Convert the enum value to ranged values */
6700 switch (cable_length) {
6701 case e1000_cable_length_50:
6702 *min_length = 0;
6703 *max_length = e1000_igp_cable_length_50;
6704 break;
6705 case e1000_cable_length_50_80:
6706 *min_length = e1000_igp_cable_length_50;
6707 *max_length = e1000_igp_cable_length_80;
6708 break;
6709 case e1000_cable_length_80_110:
6710 *min_length = e1000_igp_cable_length_80;
6711 *max_length = e1000_igp_cable_length_110;
6712 break;
6713 case e1000_cable_length_110_140:
6714 *min_length = e1000_igp_cable_length_110;
6715 *max_length = e1000_igp_cable_length_140;
6716 break;
6717 case e1000_cable_length_140:
6718 *min_length = e1000_igp_cable_length_140;
6719 *max_length = e1000_igp_cable_length_170;
6720 break;
6721 default:
6722 return -E1000_ERR_PHY;
6723 break;
6724 }
6418ecc6
JK		 6725 } else if (hw->phy_type == e1000_phy_gg82563) {
6726 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6727 &phy_data);
6728 if (ret_val)
6729 return ret_val;
6730 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6731
6732 switch (cable_length) {
6733 case e1000_gg_cable_length_60:
6734 *min_length = 0;
6735 *max_length = e1000_igp_cable_length_60;
6736 break;
6737 case e1000_gg_cable_length_60_115:
6738 *min_length = e1000_igp_cable_length_60;
6739 *max_length = e1000_igp_cable_length_115;
6740 break;
6741 case e1000_gg_cable_length_115_150:
6742 *min_length = e1000_igp_cable_length_115;
6743 *max_length = e1000_igp_cable_length_150;
6744 break;
6745 case e1000_gg_cable_length_150:
6746 *min_length = e1000_igp_cable_length_150;
6747 *max_length = e1000_igp_cable_length_180;
6748 break;
6749 default:
6750 return -E1000_ERR_PHY;
6751 break;
6752 }
8fc897b0 6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
406874a7
JP		 6754 u16 cur_agc_value;
6755 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6756 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
1da177e4
LT		 6757 {IGP01E1000_PHY_AGC_A,
6758 IGP01E1000_PHY_AGC_B,
6759 IGP01E1000_PHY_AGC_C,
6760 IGP01E1000_PHY_AGC_D};
6761 /* Read the AGC registers for all channels */
8fc897b0 6762 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6763
6764 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
8fc897b0 6765 if (ret_val)
1da177e4
LT		 6766 return ret_val;
6767
cd94dd0b 6768 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
1da177e4 6769
cd94dd0b
AK		 6770 /* Value bound check. */
6771 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6772 (cur_agc_value == 0))
1da177e4
LT		 6773 return -E1000_ERR_PHY;
6774
cd94dd0b 6775 agc_value += cur_agc_value;
1da177e4
LT		 6776
6777 /* Update minimal AGC value. */
cd94dd0b
AK		 6778 if (min_agc_value > cur_agc_value)
6779 min_agc_value = cur_agc_value;
1da177e4
LT		 6780 }
6781
6782 /* Remove the minimal AGC result for length < 50m */
cd94dd0b
AK		 6783 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6784 agc_value -= min_agc_value;
1da177e4
LT		 6785
6786 /* Get the average length of the remaining 3 channels */
6787 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6788 } else {
6789 /* Get the average length of all the 4 channels. */
6790 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6791 }
6792
6793 /* Set the range of the calculated length. */
6794 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6795 IGP01E1000_AGC_RANGE) > 0) ?
6796 (e1000_igp_cable_length_table[agc_value] -
6797 IGP01E1000_AGC_RANGE) : 0;
6798 *max_length = e1000_igp_cable_length_table[agc_value] +
6799 IGP01E1000_AGC_RANGE;
cd94dd0b
AK		 6800 } else if (hw->phy_type == e1000_phy_igp_2 ||
6801 hw->phy_type == e1000_phy_igp_3) {
406874a7
JP		 6802 u16 cur_agc_index, max_agc_index = 0;
6803 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6804 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
868d5309
MC		 6805 {IGP02E1000_PHY_AGC_A,
6806 IGP02E1000_PHY_AGC_B,
6807 IGP02E1000_PHY_AGC_C,
6808 IGP02E1000_PHY_AGC_D};
6809 /* Read the AGC registers for all channels */
6810 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6811 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6812 if (ret_val)
6813 return ret_val;
6814
8fc897b0 6815 /* Getting bits 15:9, which represent the combination of course and
868d5309
MC		 6816 * fine gain values. The result is a number that can be put into
6817 * the lookup table to obtain the approximate cable length. */
cd94dd0b
AK		 6818 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6819 IGP02E1000_AGC_LENGTH_MASK;
868d5309 6820
cd94dd0b
AK		 6821 /* Array index bound check. */
6822 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6823 (cur_agc_index == 0))
6824 return -E1000_ERR_PHY;
868d5309 6825
cd94dd0b
AK		 6826 /* Remove min & max AGC values from calculation. */
6827 if (e1000_igp_2_cable_length_table[min_agc_index] >
6828 e1000_igp_2_cable_length_table[cur_agc_index])
6829 min_agc_index = cur_agc_index;
6830 if (e1000_igp_2_cable_length_table[max_agc_index] <
6831 e1000_igp_2_cable_length_table[cur_agc_index])
6832 max_agc_index = cur_agc_index;
6833
6834 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
868d5309
MC		 6835 }
6836
cd94dd0b
AK		 6837 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6838 e1000_igp_2_cable_length_table[max_agc_index]);
868d5309
MC		 6839 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6840
6841 /* Calculate cable length with the error range of +/- 10 meters. */
6842 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6843 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6844 *max_length = agc_value + IGP02E1000_AGC_RANGE;
1da177e4
LT		 6845 }
6846
6847 return E1000_SUCCESS;
6848}
6849
6850/******************************************************************************
6851 * Check the cable polarity
6852 *
6853 * hw - Struct containing variables accessed by shared code
6854 * polarity - output parameter : 0 - Polarity is not reversed
6855 * 1 - Polarity is reversed.
6856 *
6857 * returns: - E1000_ERR_XXX
6858 * E1000_SUCCESS
6859 *
6860 * For phy's older then IGP, this function simply reads the polarity bit in the
6861 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6862 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6864 * IGP01E1000_PHY_PCS_INIT_REG.
6865 *****************************************************************************/
406874a7 6866static s32
1da177e4 6867e1000_check_polarity(struct e1000_hw *hw,
70c6f30a 6868 e1000_rev_polarity *polarity)
1da177e4 6869{
406874a7
JP		 6870 s32 ret_val;
6871 u16 phy_data;
1da177e4
LT		 6872
6873 DEBUGFUNC("e1000_check_polarity");
6874
6418ecc6
JK		 6875 if ((hw->phy_type == e1000_phy_m88) ||
6876 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6877 /* return the Polarity bit in the Status register. */
6878 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6879 &phy_data);
8fc897b0 6880 if (ret_val)
1da177e4 6881 return ret_val;
70c6f30a
JK		 6882 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6883 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6884 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6885
cd94dd0b
AK		 6886 } else if (hw->phy_type == e1000_phy_igp ||
6887 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6888 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6889 /* Read the Status register to check the speed */
6890 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6891 &phy_data);
8fc897b0 6892 if (ret_val)
1da177e4
LT		 6893 return ret_val;
6894
6895 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6896 * find the polarity status */
8fc897b0 6897 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 6898 IGP01E1000_PSSR_SPEED_1000MBPS) {
6899
6900 /* Read the GIG initialization PCS register (0x00B4) */
6901 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6902 &phy_data);
8fc897b0 6903 if (ret_val)
1da177e4
LT		 6904 return ret_val;
6905
6906 /* Check the polarity bits */
70c6f30a
JK		 6907 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6908 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6909 } else {
6910 /* For 10 Mbps, read the polarity bit in the status register. (for
6911 * 100 Mbps this bit is always 0) */
70c6f30a
JK		 6912 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6913 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4 6914 }
cd94dd0b
AK		 6915 } else if (hw->phy_type == e1000_phy_ife) {
6916 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6917 &phy_data);
6918 if (ret_val)
6919 return ret_val;
70c6f30a
JK		 6920 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6921 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6922 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6923 }
6924 return E1000_SUCCESS;
6925}
6926
6927/******************************************************************************
6928 * Check if Downshift occured
6929 *
6930 * hw - Struct containing variables accessed by shared code
6931 * downshift - output parameter : 0 - No Downshift ocured.
6932 * 1 - Downshift ocured.
6933 *
6934 * returns: - E1000_ERR_XXX
76c224bc 6935 * E1000_SUCCESS
1da177e4
LT		 6936 *
6937 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6938 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6939 * Link Health register. In IGP this bit is latched high, so the driver must
6940 * read it immediately after link is established.
6941 *****************************************************************************/
406874a7 6942static s32
1da177e4
LT		 6943e1000_check_downshift(struct e1000_hw *hw)
6944{
406874a7
JP		 6945 s32 ret_val;
6946 u16 phy_data;
1da177e4
LT		 6947
6948 DEBUGFUNC("e1000_check_downshift");
6949
cd94dd0b
AK		 6950 if (hw->phy_type == e1000_phy_igp ||
6951 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6952 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6953 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6954 &phy_data);
8fc897b0 6955 if (ret_val)
1da177e4
LT		 6956 return ret_val;
6957
6958 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6418ecc6
JK		 6959 } else if ((hw->phy_type == e1000_phy_m88) ||
6960 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6961 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6962 &phy_data);
8fc897b0 6963 if (ret_val)
1da177e4
LT		 6964 return ret_val;
6965
6966 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6967 M88E1000_PSSR_DOWNSHIFT_SHIFT;
cd94dd0b
AK		 6968 } else if (hw->phy_type == e1000_phy_ife) {
6969 /* e1000_phy_ife supports 10/100 speed only */
c3033b01 6970 hw->speed_downgraded = false;
1da177e4 6971 }
2d7edb92 6972
1da177e4
LT		 6973 return E1000_SUCCESS;
6974}
6975
6976/*****************************************************************************
6977 *
6978 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6979 * gigabit link is achieved to improve link quality.
6980 *
6981 * hw: Struct containing variables accessed by shared code
6982 *
6983 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6984 * E1000_SUCCESS at any other case.
6985 *
6986 ****************************************************************************/
6987
406874a7 6988static s32
1da177e4 6989e1000_config_dsp_after_link_change(struct e1000_hw *hw,
c3033b01 6990 bool link_up)
1da177e4 6991{
406874a7
JP		 6992 s32 ret_val;
6993 u16 phy_data, phy_saved_data, speed, duplex, i;
6994 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
1da177e4
LT		 6995 {IGP01E1000_PHY_AGC_PARAM_A,
6996 IGP01E1000_PHY_AGC_PARAM_B,
6997 IGP01E1000_PHY_AGC_PARAM_C,
6998 IGP01E1000_PHY_AGC_PARAM_D};
406874a7 6999 u16 min_length, max_length;
1da177e4
LT		 7000
7001 DEBUGFUNC("e1000_config_dsp_after_link_change");
7002
8fc897b0 7003 if (hw->phy_type != e1000_phy_igp)
1da177e4
LT		 7004 return E1000_SUCCESS;
7005
8fc897b0 7006 if (link_up) {
1da177e4 7007 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 7008 if (ret_val) {
1da177e4
LT		 7009 DEBUGOUT("Error getting link speed and duplex\n");
7010 return ret_val;
7011 }
7012
8fc897b0 7013 if (speed == SPEED_1000) {
1da177e4 7014
cd94dd0b
AK		 7015 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7016 if (ret_val)
7017 return ret_val;
1da177e4 7018
8fc897b0 7019 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
1da177e4
LT		 7020 min_length >= e1000_igp_cable_length_50) {
7021
8fc897b0 7022 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 7023 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7024 &phy_data);
8fc897b0 7025 if (ret_val)
1da177e4
LT		 7026 return ret_val;
7027
7028 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7029
7030 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7031 phy_data);
8fc897b0 7032 if (ret_val)
1da177e4
LT		 7033 return ret_val;
7034 }
7035 hw->dsp_config_state = e1000_dsp_config_activated;
7036 }
7037
8fc897b0 7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
1da177e4
LT		 7039 (min_length < e1000_igp_cable_length_50)) {
7040
406874a7
JP		 7041 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7042 u32 idle_errs = 0;
1da177e4
LT		 7043
7044 /* clear previous idle error counts */
7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7046 &phy_data);
8fc897b0 7047 if (ret_val)
1da177e4
LT		 7048 return ret_val;
7049
8fc897b0 7050 for (i = 0; i < ffe_idle_err_timeout; i++) {
1da177e4
LT		 7051 udelay(1000);
7052 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7053 &phy_data);
8fc897b0 7054 if (ret_val)
1da177e4
LT		 7055 return ret_val;
7056
7057 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
8fc897b0 7058 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
1da177e4
LT		 7059 hw->ffe_config_state = e1000_ffe_config_active;
7060
7061 ret_val = e1000_write_phy_reg(hw,
7062 IGP01E1000_PHY_DSP_FFE,
7063 IGP01E1000_PHY_DSP_FFE_CM_CP);
8fc897b0 7064 if (ret_val)
1da177e4
LT		 7065 return ret_val;
7066 break;
7067 }
7068
8fc897b0 7069 if (idle_errs)
1da177e4
LT		 7070 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7071 }
7072 }
7073 }
7074 } else {
8fc897b0 7075 if (hw->dsp_config_state == e1000_dsp_config_activated) {
1da177e4
LT		 7076 /* Save off the current value of register 0x2F5B to be restored at
7077 * the end of the routines. */
7078 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7079
8fc897b0 7080 if (ret_val)
1da177e4
LT		 7081 return ret_val;
7082
7083 /* Disable the PHY transmitter */
7084 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7085
8fc897b0 7086 if (ret_val)
1da177e4
LT		 7087 return ret_val;
7088
f8ec4733 7089 mdelay(20);
1da177e4
LT		 7090
7091 ret_val = e1000_write_phy_reg(hw, 0x0000,
7092 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7093 if (ret_val)
1da177e4 7094 return ret_val;
8fc897b0 7095 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4 7096 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
8fc897b0 7097 if (ret_val)
1da177e4
LT		 7098 return ret_val;
7099
7100 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7101 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7102
7103 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
8fc897b0 7104 if (ret_val)
1da177e4
LT		 7105 return ret_val;
7106 }
7107
7108 ret_val = e1000_write_phy_reg(hw, 0x0000,
7109 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7110 if (ret_val)
1da177e4
LT		 7111 return ret_val;
7112
f8ec4733 7113 mdelay(20);
1da177e4
LT		 7114
7115 /* Now enable the transmitter */
7116 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7117
8fc897b0 7118 if (ret_val)
1da177e4
LT		 7119 return ret_val;
7120
7121 hw->dsp_config_state = e1000_dsp_config_enabled;
7122 }
7123
8fc897b0 7124 if (hw->ffe_config_state == e1000_ffe_config_active) {
1da177e4
LT		 7125 /* Save off the current value of register 0x2F5B to be restored at
7126 * the end of the routines. */
7127 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7128
8fc897b0 7129 if (ret_val)
1da177e4
LT		 7130 return ret_val;
7131
7132 /* Disable the PHY transmitter */
7133 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7134
8fc897b0 7135 if (ret_val)
1da177e4
LT		 7136 return ret_val;
7137
f8ec4733 7138 mdelay(20);
1da177e4
LT		 7139
7140 ret_val = e1000_write_phy_reg(hw, 0x0000,
7141 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7142 if (ret_val)
1da177e4
LT		 7143 return ret_val;
7144 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7145 IGP01E1000_PHY_DSP_FFE_DEFAULT);
8fc897b0 7146 if (ret_val)
1da177e4
LT		 7147 return ret_val;
7148
7149 ret_val = e1000_write_phy_reg(hw, 0x0000,
7150 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7151 if (ret_val)
1da177e4
LT		 7152 return ret_val;
7153
f8ec4733 7154 mdelay(20);
1da177e4
LT		 7155
7156 /* Now enable the transmitter */
7157 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7158
8fc897b0 7159 if (ret_val)
1da177e4
LT		 7160 return ret_val;
7161
7162 hw->ffe_config_state = e1000_ffe_config_enabled;
7163 }
7164 }
7165 return E1000_SUCCESS;
7166}
7167
7168/*****************************************************************************
7169 * Set PHY to class A mode
7170 * Assumes the following operations will follow to enable the new class mode.
7171 * 1. Do a PHY soft reset
7172 * 2. Restart auto-negotiation or force link.
7173 *
7174 * hw - Struct containing variables accessed by shared code
7175 ****************************************************************************/
406874a7 7176static s32
1da177e4
LT		 7177e1000_set_phy_mode(struct e1000_hw *hw)
7178{
406874a7
JP		 7179 s32 ret_val;
7180 u16 eeprom_data;
1da177e4
LT		 7181
7182 DEBUGFUNC("e1000_set_phy_mode");
7183
8fc897b0
AK		 7184 if ((hw->mac_type == e1000_82545_rev_3) &&
7185 (hw->media_type == e1000_media_type_copper)) {
1da177e4 7186 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
8fc897b0 7187 if (ret_val) {
1da177e4
LT		 7188 return ret_val;
7189 }
7190
8fc897b0
AK		 7191 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7192 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1da177e4 7193 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
8fc897b0 7194 if (ret_val)
1da177e4
LT		 7195 return ret_val;
7196 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
8fc897b0 7197 if (ret_val)
1da177e4
LT		 7198 return ret_val;
7199
c3033b01 7200 hw->phy_reset_disable = false;
1da177e4
LT		 7201 }
7202 }
7203
7204 return E1000_SUCCESS;
7205}
7206
7207/*****************************************************************************
7208 *
7209 * This function sets the lplu state according to the active flag. When
7210 * activating lplu this function also disables smart speed and vise versa.
7211 * lplu will not be activated unless the device autonegotiation advertisment
7212 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7213 * hw: Struct containing variables accessed by shared code
7214 * active - true to enable lplu false to disable lplu.
7215 *
7216 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7217 * E1000_SUCCESS at any other case.
7218 *
7219 ****************************************************************************/
7220
406874a7 7221static s32
1da177e4 7222e1000_set_d3_lplu_state(struct e1000_hw *hw,
c3033b01 7223 bool active)
1da177e4 7224{
406874a7
JP		 7225 u32 phy_ctrl = 0;
7226 s32 ret_val;
7227 u16 phy_data;
1da177e4
LT		 7228 DEBUGFUNC("e1000_set_d3_lplu_state");
7229
cd94dd0b
AK		 7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7231 && hw->phy_type != e1000_phy_igp_3)
1da177e4
LT		 7232 return E1000_SUCCESS;
7233
7234 /* During driver activity LPLU should not be used or it will attain link
7235 * from the lowest speeds starting from 10Mbps. The capability is used for
7236 * Dx transitions and states */
cd94dd0b 7237 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
2d7edb92 7238 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
cd94dd0b 7239 if (ret_val)
2d7edb92 7240 return ret_val;
cd94dd0b
AK		 7241 } else if (hw->mac_type == e1000_ich8lan) {
7242 /* MAC writes into PHY register based on the state transition
7243 * and start auto-negotiation. SW driver can overwrite the settings
7244 * in CSR PHY power control E1000_PHY_CTRL register. */
7245 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2d7edb92
MC		 7246 } else {
7247 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7248 if (ret_val)
1da177e4 7249 return ret_val;
2d7edb92
MC		 7250 }
7251
8fc897b0
AK		 7252 if (!active) {
7253 if (hw->mac_type == e1000_82541_rev_2 ||
7254 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7255 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7256 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7257 if (ret_val)
2d7edb92
MC		 7258 return ret_val;
7259 } else {
cd94dd0b
AK		 7260 if (hw->mac_type == e1000_ich8lan) {
7261 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7262 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7263 } else {
2d7edb92
MC		 7264 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7265 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7266 phy_data);
7267 if (ret_val)
7268 return ret_val;
cd94dd0b 7269 }
2d7edb92 7270 }
1da177e4
LT		 7271
7272 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7273 * Dx states where the power conservation is most important. During
7274 * driver activity we should enable SmartSpeed, so performance is
7275 * maintained. */
7276 if (hw->smart_speed == e1000_smart_speed_on) {
7277 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7278 &phy_data);
8fc897b0 7279 if (ret_val)
1da177e4
LT		 7280 return ret_val;
7281
7282 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7283 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7284 phy_data);
8fc897b0 7285 if (ret_val)
1da177e4
LT		 7286 return ret_val;
7287 } else if (hw->smart_speed == e1000_smart_speed_off) {
7288 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7289 &phy_data);
35574764 7290 if (ret_val)
1da177e4
LT		 7291 return ret_val;
7292
7293 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7294 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7295 phy_data);
8fc897b0 7296 if (ret_val)
1da177e4
LT		 7297 return ret_val;
7298 }
7299
8fc897b0
AK		 7300 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7301 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7302 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
1da177e4 7303
8fc897b0 7304 if (hw->mac_type == e1000_82541_rev_2 ||
cd94dd0b 7305 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7306 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7307 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7308 if (ret_val)
2d7edb92
MC		 7309 return ret_val;
7310 } else {
cd94dd0b
AK		 7311 if (hw->mac_type == e1000_ich8lan) {
7312 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7313 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7314 } else {
2d7edb92
MC		 7315 phy_data |= IGP02E1000_PM_D3_LPLU;
7316 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7317 phy_data);
7318 if (ret_val)
7319 return ret_val;
cd94dd0b 7320 }
2d7edb92
MC		 7321 }
7322
7323 /* When LPLU is enabled we should disable SmartSpeed */
7324 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7325 if (ret_val)
2d7edb92
MC		 7326 return ret_val;
7327
7328 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7329 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7330 if (ret_val)
2d7edb92
MC		 7331 return ret_val;
7332
7333 }
7334 return E1000_SUCCESS;
7335}
7336
7337/*****************************************************************************
7338 *
7339 * This function sets the lplu d0 state according to the active flag. When
7340 * activating lplu this function also disables smart speed and vise versa.
7341 * lplu will not be activated unless the device autonegotiation advertisment
7342 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7343 * hw: Struct containing variables accessed by shared code
7344 * active - true to enable lplu false to disable lplu.
7345 *
7346 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7347 * E1000_SUCCESS at any other case.
7348 *
7349 ****************************************************************************/
7350
406874a7 7351static s32
2d7edb92 7352e1000_set_d0_lplu_state(struct e1000_hw *hw,
c3033b01 7353 bool active)
2d7edb92 7354{
406874a7
JP		 7355 u32 phy_ctrl = 0;
7356 s32 ret_val;
7357 u16 phy_data;
2d7edb92
MC		 7358 DEBUGFUNC("e1000_set_d0_lplu_state");
7359
8fc897b0 7360 if (hw->mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 7361 return E1000_SUCCESS;
7362
cd94dd0b
AK		 7363 if (hw->mac_type == e1000_ich8lan) {
7364 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7365 } else {
2d7edb92 7366 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7367 if (ret_val)
1da177e4 7368 return ret_val;
cd94dd0b 7369 }
1da177e4 7370
2d7edb92 7371 if (!active) {
cd94dd0b
AK		 7372 if (hw->mac_type == e1000_ich8lan) {
7373 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7374 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7375 } else {
2d7edb92
MC		 7376 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7377 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7378 if (ret_val)
7379 return ret_val;
cd94dd0b 7380 }
2d7edb92
MC		 7381
7382 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7383 * Dx states where the power conservation is most important. During
7384 * driver activity we should enable SmartSpeed, so performance is
7385 * maintained. */
7386 if (hw->smart_speed == e1000_smart_speed_on) {
7387 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7388 &phy_data);
8fc897b0 7389 if (ret_val)
2d7edb92
MC		 7390 return ret_val;
7391
7392 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7393 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7394 phy_data);
8fc897b0 7395 if (ret_val)
2d7edb92
MC		 7396 return ret_val;
7397 } else if (hw->smart_speed == e1000_smart_speed_off) {
7398 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7399 &phy_data);
35574764 7400 if (ret_val)
2d7edb92
MC		 7401 return ret_val;
7402
7403 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7404 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7405 phy_data);
8fc897b0 7406 if (ret_val)
2d7edb92
MC		 7407 return ret_val;
7408 }
7409
7410
7411 } else {
76c224bc 7412
cd94dd0b
AK		 7413 if (hw->mac_type == e1000_ich8lan) {
7414 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7415 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7416 } else {
76c224bc 7417 phy_data |= IGP02E1000_PM_D0_LPLU;
2d7edb92
MC		 7418 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7419 if (ret_val)
7420 return ret_val;
cd94dd0b 7421 }
2d7edb92 7422
1da177e4
LT		 7423 /* When LPLU is enabled we should disable SmartSpeed */
7424 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7425 if (ret_val)
1da177e4
LT		 7426 return ret_val;
7427
7428 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7429 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7430 if (ret_val)
1da177e4
LT		 7431 return ret_val;
7432
7433 }
7434 return E1000_SUCCESS;
7435}
7436
7437/******************************************************************************
7438 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7439 *
7440 * hw - Struct containing variables accessed by shared code
7441 *****************************************************************************/
406874a7 7442static s32
1da177e4
LT		 7443e1000_set_vco_speed(struct e1000_hw *hw)
7444{
406874a7
JP		 7445 s32 ret_val;
7446 u16 default_page = 0;
7447 u16 phy_data;
1da177e4
LT		 7448
7449 DEBUGFUNC("e1000_set_vco_speed");
7450
8fc897b0 7451 switch (hw->mac_type) {
1da177e4
LT		 7452 case e1000_82545_rev_3:
7453 case e1000_82546_rev_3:
7454 break;
7455 default:
7456 return E1000_SUCCESS;
7457 }
7458
7459 /* Set PHY register 30, page 5, bit 8 to 0 */
7460
7461 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8fc897b0 7462 if (ret_val)
1da177e4
LT		 7463 return ret_val;
7464
7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8fc897b0 7466 if (ret_val)
1da177e4
LT		 7467 return ret_val;
7468
7469 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7470 if (ret_val)
1da177e4
LT		 7471 return ret_val;
7472
7473 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7475 if (ret_val)
1da177e4
LT		 7476 return ret_val;
7477
7478 /* Set PHY register 30, page 4, bit 11 to 1 */
7479
7480 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8fc897b0 7481 if (ret_val)
1da177e4
LT		 7482 return ret_val;
7483
7484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7485 if (ret_val)
1da177e4
LT		 7486 return ret_val;
7487
7488 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7489 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7490 if (ret_val)
1da177e4
LT		 7491 return ret_val;
7492
7493 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8fc897b0 7494 if (ret_val)
1da177e4
LT		 7495 return ret_val;
7496
7497 return E1000_SUCCESS;
7498}
7499
1da177e4 7500
2d7edb92
MC		 7501/*****************************************************************************
7502 * This function reads the cookie from ARC ram.
7503 *
7504 * returns: - E1000_SUCCESS .
7505 ****************************************************************************/
406874a7
JP		 7506static s32
7507e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
2d7edb92 7508{
406874a7
JP		 7509 u8 i;
7510 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7511 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
1da177e4 7512
2d7edb92
MC		 7513 length = (length >> 2);
7514 offset = (offset >> 2);
1da177e4 7515
2d7edb92 7516 for (i = 0; i < length; i++) {
406874a7 7517 *((u32 *) buffer + i) =
2d7edb92
MC		 7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7519 }
7520 return E1000_SUCCESS;
7521}
7522
7523
7524/*****************************************************************************
7525 * This function checks whether the HOST IF is enabled for command operaton
7526 * and also checks whether the previous command is completed.
7527 * It busy waits in case of previous command is not completed.
7528 *
76c224bc 7529 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
2d7edb92
MC		 7530 * timeout
7531 * - E1000_SUCCESS for success.
7532 ****************************************************************************/
406874a7 7533static s32
2d7edb92
MC		 7534e1000_mng_enable_host_if(struct e1000_hw * hw)
7535{
406874a7
JP		 7536 u32 hicr;
7537 u8 i;
2d7edb92
MC		 7538
7539 /* Check that the host interface is enabled. */
7540 hicr = E1000_READ_REG(hw, HICR);
7541 if ((hicr & E1000_HICR_EN) == 0) {
7542 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7543 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7544 }
7545 /* check the previous command is completed */
7546 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7547 hicr = E1000_READ_REG(hw, HICR);
7548 if (!(hicr & E1000_HICR_C))
7549 break;
f8ec4733 7550 mdelay(1);
2d7edb92
MC		 7551 }
7552
76c224bc 7553 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2d7edb92
MC		 7554 DEBUGOUT("Previous command timeout failed .\n");
7555 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7556 }
7557 return E1000_SUCCESS;
7558}
7559
7560/*****************************************************************************
7561 * This function writes the buffer content at the offset given on the host if.
7562 * It also does alignment considerations to do the writes in most efficient way.
7563 * Also fills up the sum of the buffer in *buffer parameter.
7564 *
7565 * returns - E1000_SUCCESS for success.
7566 ****************************************************************************/
406874a7
JP		 7567static s32
7568e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer,
7569 u16 length, u16 offset, u8 *sum)
2d7edb92 7570{
406874a7
JP		 7571 u8 *tmp;
7572 u8 *bufptr = buffer;
7573 u32 data = 0;
7574 u16 remaining, i, j, prev_bytes;
2d7edb92
MC		 7575
7576 /* sum = only sum of the data and it is not checksum */
7577
7578 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7579 return -E1000_ERR_PARAM;
7580 }
7581
406874a7 7582 tmp = (u8 *)&data;
2d7edb92
MC		 7583 prev_bytes = offset & 0x3;
7584 offset &= 0xFFFC;
7585 offset >>= 2;
7586
7587 if (prev_bytes) {
7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
406874a7 7589 for (j = prev_bytes; j < sizeof(u32); j++) {
2d7edb92
MC		 7590 *(tmp + j) = *bufptr++;
7591 *sum += *(tmp + j);
7592 }
7593 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7594 length -= j - prev_bytes;
7595 offset++;
7596 }
7597
7598 remaining = length & 0x3;
7599 length -= remaining;
7600
7601 /* Calculate length in DWORDs */
7602 length >>= 2;
7603
7604 /* The device driver writes the relevant command block into the
7605 * ram area. */
7606 for (i = 0; i < length; i++) {
406874a7 7607 for (j = 0; j < sizeof(u32); j++) {
2d7edb92
MC		 7608 *(tmp + j) = *bufptr++;
7609 *sum += *(tmp + j);
7610 }
7611
7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7613 }
7614 if (remaining) {
406874a7 7615 for (j = 0; j < sizeof(u32); j++) {
2d7edb92
MC		 7616 if (j < remaining)
7617 *(tmp + j) = *bufptr++;
7618 else
7619 *(tmp + j) = 0;
7620
7621 *sum += *(tmp + j);
7622 }
7623 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7624 }
7625
7626 return E1000_SUCCESS;
7627}
7628
7629
7630/*****************************************************************************
7631 * This function writes the command header after does the checksum calculation.
7632 *
7633 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/
406874a7 7635static s32
2d7edb92
MC		 7636e1000_mng_write_cmd_header(struct e1000_hw * hw,
7637 struct e1000_host_mng_command_header * hdr)
7638{
406874a7
JP		 7639 u16 i;
7640 u8 sum;
7641 u8 *buffer;
2d7edb92
MC		 7642
7643 /* Write the whole command header structure which includes sum of
7644 * the buffer */
7645
406874a7 7646 u16 length = sizeof(struct e1000_host_mng_command_header);
2d7edb92
MC		 7647
7648 sum = hdr->checksum;
7649 hdr->checksum = 0;
7650
406874a7 7651 buffer = (u8 *) hdr;
2d7edb92 7652 i = length;
8fc897b0 7653 while (i--)
2d7edb92
MC		 7654 sum += buffer[i];
7655
7656 hdr->checksum = 0 - sum;
7657
7658 length >>= 2;
7659 /* The device driver writes the relevant command block into the ram area. */
4ca213a6 7660 for (i = 0; i < length; i++) {
406874a7 7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i));
4ca213a6
AK		 7662 E1000_WRITE_FLUSH(hw);
7663 }
2d7edb92
MC		 7664
7665 return E1000_SUCCESS;
7666}
7667
7668
7669/*****************************************************************************
7670 * This function indicates to ARC that a new command is pending which completes
7671 * one write operation by the driver.
7672 *
7673 * returns - E1000_SUCCESS for success.
7674 ****************************************************************************/
406874a7 7675static s32
8fc897b0 7676e1000_mng_write_commit(struct e1000_hw * hw)
2d7edb92 7677{
406874a7 7678 u32 hicr;
2d7edb92
MC		 7679
7680 hicr = E1000_READ_REG(hw, HICR);
7681 /* Setting this bit tells the ARC that a new command is pending. */
7682 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7683
7684 return E1000_SUCCESS;
7685}
7686
7687
7688/*****************************************************************************
7689 * This function checks the mode of the firmware.
7690 *
c3033b01 7691 * returns - true when the mode is IAMT or false.
2d7edb92 7692 ****************************************************************************/
c3033b01 7693bool
cd94dd0b 7694e1000_check_mng_mode(struct e1000_hw *hw)
2d7edb92 7695{
406874a7 7696 u32 fwsm;
2d7edb92
MC		 7697
7698 fwsm = E1000_READ_REG(hw, FWSM);
7699
cd94dd0b
AK		 7700 if (hw->mac_type == e1000_ich8lan) {
7701 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7702 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
c3033b01 7703 return true;
cd94dd0b
AK		 7704 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7705 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
c3033b01 7706 return true;
2d7edb92 7707
c3033b01 7708 return false;
2d7edb92
MC		 7709}
7710
7711
7712/*****************************************************************************
7713 * This function writes the dhcp info .
7714 ****************************************************************************/
406874a7
JP		 7715s32
7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer,
7717 u16 length)
2d7edb92 7718{
406874a7 7719 s32 ret_val;
2d7edb92
MC		 7720 struct e1000_host_mng_command_header hdr;
7721
7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7723 hdr.command_length = length;
7724 hdr.reserved1 = 0;
7725 hdr.reserved2 = 0;
7726 hdr.checksum = 0;
7727
7728 ret_val = e1000_mng_enable_host_if(hw);
7729 if (ret_val == E1000_SUCCESS) {
7730 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7731 &(hdr.checksum));
7732 if (ret_val == E1000_SUCCESS) {
7733 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7734 if (ret_val == E1000_SUCCESS)
7735 ret_val = e1000_mng_write_commit(hw);
7736 }
7737 }
7738 return ret_val;
7739}
7740
7741
7742/*****************************************************************************
7743 * This function calculates the checksum.
7744 *
7745 * returns - checksum of buffer contents.
7746 ****************************************************************************/
406874a7
JP		 7747static u8
7748e1000_calculate_mng_checksum(char *buffer, u32 length)
2d7edb92 7749{
406874a7
JP		 7750 u8 sum = 0;
7751 u32 i;
2d7edb92
MC		 7752
7753 if (!buffer)
7754 return 0;
7755
7756 for (i=0; i < length; i++)
7757 sum += buffer[i];
7758
406874a7 7759 return (u8) (0 - sum);
2d7edb92
MC		 7760}
7761
7762/*****************************************************************************
7763 * This function checks whether tx pkt filtering needs to be enabled or not.
7764 *
c3033b01 7765 * returns - true for packet filtering or false.
2d7edb92 7766 ****************************************************************************/
c3033b01 7767bool
2d7edb92
MC		 7768e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7769{
7770 /* called in init as well as watchdog timer functions */
7771
406874a7 7772 s32 ret_val, checksum;
c3033b01 7773 bool tx_filter = false;
2d7edb92 7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
406874a7 7775 u8 *buffer = (u8 *) &(hw->mng_cookie);
2d7edb92
MC		 7776
7777 if (e1000_check_mng_mode(hw)) {
7778 ret_val = e1000_mng_enable_host_if(hw);
7779 if (ret_val == E1000_SUCCESS) {
7780 ret_val = e1000_host_if_read_cookie(hw, buffer);
7781 if (ret_val == E1000_SUCCESS) {
7782 checksum = hdr->checksum;
7783 hdr->checksum = 0;
7784 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7785 checksum == e1000_calculate_mng_checksum((char *)buffer,
7786 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7787 if (hdr->status &
7788 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
c3033b01 7789 tx_filter = true;
2d7edb92 7790 } else
c3033b01 7791 tx_filter = true;
2d7edb92 7792 } else
c3033b01 7793 tx_filter = true;
2d7edb92
MC		 7794 }
7795 }
7796
7797 hw->tx_pkt_filtering = tx_filter;
7798 return tx_filter;
7799}
7800
7801/******************************************************************************
7802 * Verifies the hardware needs to allow ARPs to be processed by the host
7803 *
7804 * hw - Struct containing variables accessed by shared code
7805 *
c3033b01 7806 * returns: - true/false
2d7edb92
MC		 7807 *
7808 *****************************************************************************/
406874a7 7809u32
2d7edb92
MC		 7810e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7811{
406874a7
JP		 7812 u32 manc;
7813 u32 fwsm, factps;
2d7edb92
MC		 7814
7815 if (hw->asf_firmware_present) {
7816 manc = E1000_READ_REG(hw, MANC);
7817
7818 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7819 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
c3033b01
JP		 7820 return false;
7821 if (e1000_arc_subsystem_valid(hw)) {
2d7edb92
MC		 7822 fwsm = E1000_READ_REG(hw, FWSM);
7823 factps = E1000_READ_REG(hw, FACTPS);
7824
0fccd0e9
JG		 7825 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7826 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
c3033b01 7827 return true;
2d7edb92
MC		 7828 } else
7829 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
c3033b01 7830 return true;
2d7edb92 7831 }
c3033b01 7832 return false;
2d7edb92
MC		 7833}
7834
406874a7 7835static s32
2d7edb92
MC		 7836e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7837{
406874a7
JP		 7838 s32 ret_val;
7839 u16 mii_status_reg;
7840 u16 i;
2d7edb92
MC		 7841
7842 /* Polarity reversal workaround for forced 10F/10H links. */
7843
7844 /* Disable the transmitter on the PHY */
7845
7846 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7847 if (ret_val)
1da177e4
LT		 7848 return ret_val;
7849 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
8fc897b0 7850 if (ret_val)
1da177e4
LT		 7851 return ret_val;
7852
7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7854 if (ret_val)
1da177e4
LT		 7855 return ret_val;
7856
7857 /* This loop will early-out if the NO link condition has been met. */
8fc897b0 7858 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7859 /* Read the MII Status Register and wait for Link Status bit
7860 * to be clear.
7861 */
7862
7863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7864 if (ret_val)
1da177e4
LT		 7865 return ret_val;
7866
7867 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7868 if (ret_val)
1da177e4
LT		 7869 return ret_val;
7870
8fc897b0 7871 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
f8ec4733 7872 mdelay(100);
1da177e4
LT		 7873 }
7874
7875 /* Recommended delay time after link has been lost */
f8ec4733 7876 mdelay(1000);
1da177e4
LT		 7877
7878 /* Now we will re-enable th transmitter on the PHY */
7879
7880 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7881 if (ret_val)
1da177e4 7882 return ret_val;
f8ec4733 7883 mdelay(50);
1da177e4 7884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8fc897b0 7885 if (ret_val)
1da177e4 7886 return ret_val;
f8ec4733 7887 mdelay(50);
1da177e4 7888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8fc897b0 7889 if (ret_val)
1da177e4 7890 return ret_val;
f8ec4733 7891 mdelay(50);
1da177e4 7892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8fc897b0 7893 if (ret_val)
1da177e4
LT		 7894 return ret_val;
7895
7896 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7897 if (ret_val)
1da177e4
LT		 7898 return ret_val;
7899
7900 /* This loop will early-out if the link condition has been met. */
8fc897b0 7901 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7902 /* Read the MII Status Register and wait for Link Status bit
7903 * to be set.
7904 */
7905
7906 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7907 if (ret_val)
1da177e4
LT		 7908 return ret_val;
7909
7910 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7911 if (ret_val)
1da177e4
LT		 7912 return ret_val;
7913
8fc897b0 7914 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 7915 mdelay(100);
1da177e4
LT		 7916 }
7917 return E1000_SUCCESS;
7918}
7919
2d7edb92
MC		 7920/***************************************************************************
7921 *
7922 * Disables PCI-Express master access.
7923 *
7924 * hw: Struct containing variables accessed by shared code
7925 *
7926 * returns: - none.
7927 *
7928 ***************************************************************************/
3ad2cc67 7929static void
2d7edb92
MC		 7930e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7931{
406874a7 7932 u32 ctrl;
2d7edb92
MC		 7933
7934 DEBUGFUNC("e1000_set_pci_express_master_disable");
7935
7936 if (hw->bus_type != e1000_bus_type_pci_express)
7937 return;
7938
7939 ctrl = E1000_READ_REG(hw, CTRL);
7940 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7941 E1000_WRITE_REG(hw, CTRL, ctrl);
7942}
7943
2d7edb92
MC		 7944/*******************************************************************************
7945 *
7946 * Disables PCI-Express master access and verifies there are no pending requests
7947 *
7948 * hw: Struct containing variables accessed by shared code
7949 *
7950 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7951 * caused the master requests to be disabled.
7952 * E1000_SUCCESS master requests disabled.
7953 *
7954 ******************************************************************************/
406874a7 7955s32
2d7edb92
MC		 7956e1000_disable_pciex_master(struct e1000_hw *hw)
7957{
406874a7 7958 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
2d7edb92
MC		 7959
7960 DEBUGFUNC("e1000_disable_pciex_master");
7961
7962 if (hw->bus_type != e1000_bus_type_pci_express)
7963 return E1000_SUCCESS;
7964
7965 e1000_set_pci_express_master_disable(hw);
7966
8fc897b0
AK		 7967 while (timeout) {
7968 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
2d7edb92
MC		 7969 break;
7970 else
7971 udelay(100);
7972 timeout--;
7973 }
7974
8fc897b0 7975 if (!timeout) {
2d7edb92
MC		 7976 DEBUGOUT("Master requests are pending.\n");
7977 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7978 }
7979
7980 return E1000_SUCCESS;
7981}
7982
7983/*******************************************************************************
7984 *
7985 * Check for EEPROM Auto Read bit done.
7986 *
7987 * hw: Struct containing variables accessed by shared code
7988 *
7989 * returns: - E1000_ERR_RESET if fail to reset MAC
7990 * E1000_SUCCESS at any other case.
7991 *
7992 ******************************************************************************/
406874a7 7993static s32
2d7edb92
MC		 7994e1000_get_auto_rd_done(struct e1000_hw *hw)
7995{
406874a7 7996 s32 timeout = AUTO_READ_DONE_TIMEOUT;
2d7edb92
MC		 7997
7998 DEBUGFUNC("e1000_get_auto_rd_done");
7999
8000 switch (hw->mac_type) {
8001 default:
f8ec4733 8002 msleep(5);
2d7edb92 8003 break;
868d5309
MC		 8004 case e1000_82571:
8005 case e1000_82572:
2d7edb92 8006 case e1000_82573:
6418ecc6 8007 case e1000_80003es2lan:
cd94dd0b
AK		 8008 case e1000_ich8lan:
8009 while (timeout) {
8010 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8011 break;
f8ec4733 8012 else msleep(1);
2d7edb92
MC		 8013 timeout--;
8014 }
8015
8fc897b0 8016 if (!timeout) {
2d7edb92
MC		 8017 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8018 return -E1000_ERR_RESET;
8019 }
8020 break;
8021 }
8022
fd803241
JK		 8023 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8024 * Need to wait for PHY configuration completion before accessing NVM
8025 * and PHY. */
8026 if (hw->mac_type == e1000_82573)
f8ec4733 8027 msleep(25);
fd803241 8028
2d7edb92
MC		 8029 return E1000_SUCCESS;
8030}
8031
8032/***************************************************************************
8033 * Checks if the PHY configuration is done
8034 *
8035 * hw: Struct containing variables accessed by shared code
8036 *
8037 * returns: - E1000_ERR_RESET if fail to reset MAC
8038 * E1000_SUCCESS at any other case.
8039 *
8040 ***************************************************************************/
406874a7 8041static s32
2d7edb92
MC		 8042e1000_get_phy_cfg_done(struct e1000_hw *hw)
8043{
406874a7
JP		 8044 s32 timeout = PHY_CFG_TIMEOUT;
8045 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
868d5309 8046
2d7edb92
MC		 8047 DEBUGFUNC("e1000_get_phy_cfg_done");
8048
868d5309
MC		 8049 switch (hw->mac_type) {
8050 default:
f8ec4733 8051 mdelay(10);
868d5309 8052 break;
6418ecc6
JK		 8053 case e1000_80003es2lan:
8054 /* Separate *_CFG_DONE_* bit for each port */
8055 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8056 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8057 /* Fall Through */
868d5309
MC		 8058 case e1000_82571:
8059 case e1000_82572:
8060 while (timeout) {
8061 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8062 break;
8063 else
f8ec4733 8064 msleep(1);
868d5309
MC		 8065 timeout--;
8066 }
868d5309
MC		 8067 if (!timeout) {
8068 DEBUGOUT("MNG configuration cycle has not completed.\n");
8069 return -E1000_ERR_RESET;
8070 }
8071 break;
8072 }
2d7edb92
MC		 8073
8074 return E1000_SUCCESS;
8075}
8076
8077/***************************************************************************
8078 *
8079 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8080 * adapter or Eeprom access.
8081 *
8082 * hw: Struct containing variables accessed by shared code
8083 *
8084 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8085 * E1000_SUCCESS at any other case.
8086 *
8087 ***************************************************************************/
406874a7 8088static s32
2d7edb92
MC		 8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090{
406874a7
JP		 8091 s32 timeout;
8092 u32 swsm;
2d7edb92
MC		 8093
8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8095
8fc897b0 8096 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8097 return E1000_SUCCESS;
8098
6418ecc6
JK		 8099 if (hw->mac_type == e1000_80003es2lan) {
8100 /* Get the SW semaphore. */
8101 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8102 return -E1000_ERR_EEPROM;
8103 }
2d7edb92
MC		 8104
8105 /* Get the FW semaphore. */
8106 timeout = hw->eeprom.word_size + 1;
8fc897b0 8107 while (timeout) {
2d7edb92
MC		 8108 swsm = E1000_READ_REG(hw, SWSM);
8109 swsm |= E1000_SWSM_SWESMBI;
8110 E1000_WRITE_REG(hw, SWSM, swsm);
8111 /* if we managed to set the bit we got the semaphore. */
8112 swsm = E1000_READ_REG(hw, SWSM);
8fc897b0 8113 if (swsm & E1000_SWSM_SWESMBI)
2d7edb92
MC		 8114 break;
8115
8116 udelay(50);
8117 timeout--;
8118 }
8119
8fc897b0 8120 if (!timeout) {
2d7edb92
MC		 8121 /* Release semaphores */
8122 e1000_put_hw_eeprom_semaphore(hw);
8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8124 return -E1000_ERR_EEPROM;
8125 }
8126
8127 return E1000_SUCCESS;
8128}
8129
8130/***************************************************************************
8131 * This function clears HW semaphore bits.
8132 *
8133 * hw: Struct containing variables accessed by shared code
8134 *
8135 * returns: - None.
8136 *
8137 ***************************************************************************/
3ad2cc67 8138static void
2d7edb92
MC		 8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140{
406874a7 8141 u32 swsm;
2d7edb92
MC		 8142
8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8144
8fc897b0 8145 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8146 return;
8147
8148 swsm = E1000_READ_REG(hw, SWSM);
6418ecc6
JK		 8149 if (hw->mac_type == e1000_80003es2lan) {
8150 /* Release both semaphores. */
8151 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8152 } else
868d5309 8153 swsm &= ~(E1000_SWSM_SWESMBI);
2d7edb92
MC		 8154 E1000_WRITE_REG(hw, SWSM, swsm);
8155}
8156
6418ecc6
JK		 8157/***************************************************************************
8158 *
8159 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8160 *
8161 * hw: Struct containing variables accessed by shared code
8162 *
8163 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8164 * E1000_SUCCESS at any other case.
8165 *
8166 ***************************************************************************/
406874a7 8167static s32
6418ecc6
JK		 8168e1000_get_software_semaphore(struct e1000_hw *hw)
8169{
406874a7
JP		 8170 s32 timeout = hw->eeprom.word_size + 1;
8171 u32 swsm;
6418ecc6
JK		 8172
8173 DEBUGFUNC("e1000_get_software_semaphore");
8174
35574764 8175 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8176 return E1000_SUCCESS;
35574764 8177 }
6418ecc6 8178
8fc897b0 8179 while (timeout) {
6418ecc6
JK		 8180 swsm = E1000_READ_REG(hw, SWSM);
8181 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8fc897b0 8182 if (!(swsm & E1000_SWSM_SMBI))
6418ecc6 8183 break;
f8ec4733 8184 mdelay(1);
6418ecc6
JK		 8185 timeout--;
8186 }
8187
8fc897b0 8188 if (!timeout) {
6418ecc6
JK		 8189 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8190 return -E1000_ERR_RESET;
8191 }
8192
8193 return E1000_SUCCESS;
8194}
8195
8196/***************************************************************************
8197 *
8198 * Release semaphore bit (SMBI).
8199 *
8200 * hw: Struct containing variables accessed by shared code
8201 *
8202 ***************************************************************************/
e4c780b1 8203static void
6418ecc6
JK		 8204e1000_release_software_semaphore(struct e1000_hw *hw)
8205{
406874a7 8206 u32 swsm;
6418ecc6
JK		 8207
8208 DEBUGFUNC("e1000_release_software_semaphore");
8209
35574764 8210 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8211 return;
35574764 8212 }
6418ecc6
JK		 8213
8214 swsm = E1000_READ_REG(hw, SWSM);
8215 /* Release the SW semaphores.*/
8216 swsm &= ~E1000_SWSM_SMBI;
8217 E1000_WRITE_REG(hw, SWSM, swsm);
8218}
8219
2d7edb92
MC		 8220/******************************************************************************
8221 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8222 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8223 * the caller to figure out how to deal with it.
8224 *
8225 * hw - Struct containing variables accessed by shared code
8226 *
8227 * returns: - E1000_BLK_PHY_RESET
8228 * E1000_SUCCESS
8229 *
8230 *****************************************************************************/
406874a7 8231s32
2d7edb92
MC		 8232e1000_check_phy_reset_block(struct e1000_hw *hw)
8233{
406874a7
JP		 8234 u32 manc = 0;
8235 u32 fwsm = 0;
cd94dd0b
AK		 8236
8237 if (hw->mac_type == e1000_ich8lan) {
8238 fwsm = E1000_READ_REG(hw, FWSM);
8239 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8240 : E1000_BLK_PHY_RESET;
8241 }
96838a40
JB		 8242
8243 if (hw->mac_type > e1000_82547_rev_2)
2d7edb92
MC		 8244 manc = E1000_READ_REG(hw, MANC);
8245 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
35574764 8246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
2d7edb92
MC		 8247}
8248
406874a7 8249static u8
2d7edb92
MC		 8250e1000_arc_subsystem_valid(struct e1000_hw *hw)
8251{
406874a7 8252 u32 fwsm;
2d7edb92
MC		 8253
8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8255 * may not be provided a DMA clock when no manageability features are
8256 * enabled. We do not want to perform any reads/writes to these registers
8257 * if this is the case. We read FWSM to determine the manageability mode.
8258 */
8259 switch (hw->mac_type) {
868d5309
MC		 8260 case e1000_82571:
8261 case e1000_82572:
2d7edb92 8262 case e1000_82573:
6418ecc6 8263 case e1000_80003es2lan:
2d7edb92 8264 fwsm = E1000_READ_REG(hw, FWSM);
8fc897b0 8265 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
c3033b01 8266 return true;
2d7edb92 8267 break;
cd94dd0b 8268 case e1000_ich8lan:
c3033b01 8269 return true;
2d7edb92
MC		 8270 default:
8271 break;
8272 }
c3033b01 8273 return false;
2d7edb92
MC		 8274}
8275
8276
d37ea5d5
AK		 8277/******************************************************************************
8278 * Configure PCI-Ex no-snoop
8279 *
8280 * hw - Struct containing variables accessed by shared code.
8281 * no_snoop - Bitmap of no-snoop events.
8282 *
8283 * returns: E1000_SUCCESS
8284 *
8285 *****************************************************************************/
406874a7
JP		 8286static s32
8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
d37ea5d5 8288{
406874a7 8289 u32 gcr_reg = 0;
d37ea5d5
AK		 8290
8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8292
8293 if (hw->bus_type == e1000_bus_type_unknown)
8294 e1000_get_bus_info(hw);
8295
8296 if (hw->bus_type != e1000_bus_type_pci_express)
8297 return E1000_SUCCESS;
8298
8299 if (no_snoop) {
8300 gcr_reg = E1000_READ_REG(hw, GCR);
8301 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8302 gcr_reg |= no_snoop;
8303 E1000_WRITE_REG(hw, GCR, gcr_reg);
8304 }
8305 if (hw->mac_type == e1000_ich8lan) {
406874a7 8306 u32 ctrl_ext;
d37ea5d5
AK		 8307
8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8309
8310 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8311 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8312 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8313 }
8314
8315 return E1000_SUCCESS;
8316}
8317
8318/***************************************************************************
8319 *
8320 * Get software semaphore FLAG bit (SWFLAG).
8321 * SWFLAG is used to synchronize the access to all shared resource between
8322 * SW, FW and HW.
8323 *
8324 * hw: Struct containing variables accessed by shared code
8325 *
8326 ***************************************************************************/
406874a7 8327static s32
d37ea5d5
AK		 8328e1000_get_software_flag(struct e1000_hw *hw)
8329{
406874a7
JP		 8330 s32 timeout = PHY_CFG_TIMEOUT;
8331 u32 extcnf_ctrl;
d37ea5d5
AK		 8332
8333 DEBUGFUNC("e1000_get_software_flag");
8334
8335 if (hw->mac_type == e1000_ich8lan) {
8336 while (timeout) {
8337 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8338 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8339 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8340
8341 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8342 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8343 break;
f8ec4733 8344 mdelay(1);
d37ea5d5
AK		 8345 timeout--;
8346 }
8347
8348 if (!timeout) {
8349 DEBUGOUT("FW or HW locks the resource too long.\n");
8350 return -E1000_ERR_CONFIG;
8351 }
8352 }
8353
8354 return E1000_SUCCESS;
8355}
8356
8357/***************************************************************************
8358 *
8359 * Release software semaphore FLAG bit (SWFLAG).
8360 * SWFLAG is used to synchronize the access to all shared resource between
8361 * SW, FW and HW.
8362 *
8363 * hw: Struct containing variables accessed by shared code
8364 *
8365 ***************************************************************************/
e4c780b1 8366static void
d37ea5d5
AK		 8367e1000_release_software_flag(struct e1000_hw *hw)
8368{
406874a7 8369 u32 extcnf_ctrl;
d37ea5d5
AK		 8370
8371 DEBUGFUNC("e1000_release_software_flag");
8372
8373 if (hw->mac_type == e1000_ich8lan) {
8374 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8375 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8376 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8377 }
8378
8379 return;
8380}
8381
d37ea5d5
AK		 8382/******************************************************************************
8383 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8384 * register.
8385 *
8386 * hw - Struct containing variables accessed by shared code
8387 * offset - offset of word in the EEPROM to read
8388 * data - word read from the EEPROM
8389 * words - number of words to read
8390 *****************************************************************************/
406874a7
JP		 8391static s32
8392e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8393 u16 *data)
d37ea5d5 8394{
406874a7
JP		 8395 s32 error = E1000_SUCCESS;
8396 u32 flash_bank = 0;
8397 u32 act_offset = 0;
8398 u32 bank_offset = 0;
8399 u16 word = 0;
8400 u16 i = 0;
d37ea5d5
AK		 8401
8402 /* We need to know which is the valid flash bank. In the event
8403 * that we didn't allocate eeprom_shadow_ram, we may not be
8404 * managing flash_bank. So it cannot be trusted and needs
8405 * to be updated with each read.
8406 */
8407 /* Value of bit 22 corresponds to the flash bank we're on. */
8408 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8409
8410 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8411 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8412
8413 error = e1000_get_software_flag(hw);
8414 if (error != E1000_SUCCESS)
8415 return error;
8416
8417 for (i = 0; i < words; i++) {
8418 if (hw->eeprom_shadow_ram != NULL &&
c3033b01 8419 hw->eeprom_shadow_ram[offset+i].modified) {
d37ea5d5
AK		 8420 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8421 } else {
8422 /* The NVM part needs a byte offset, hence * 2 */
8423 act_offset = bank_offset + ((offset + i) * 2);
8424 error = e1000_read_ich8_word(hw, act_offset, &word);
8425 if (error != E1000_SUCCESS)
8426 break;
8427 data[i] = word;
8428 }
8429 }
8430
8431 e1000_release_software_flag(hw);
8432
8433 return error;
8434}
8435
8436/******************************************************************************
8437 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8438 * register. Actually, writes are written to the shadow ram cache in the hw
8439 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8440 * the NVM, which occurs when the NVM checksum is updated.
8441 *
8442 * hw - Struct containing variables accessed by shared code
8443 * offset - offset of word in the EEPROM to write
8444 * words - number of words to write
8445 * data - words to write to the EEPROM
8446 *****************************************************************************/
406874a7
JP		 8447static s32
8448e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8449 u16 *data)
d37ea5d5 8450{
406874a7
JP		 8451 u32 i = 0;
8452 s32 error = E1000_SUCCESS;
d37ea5d5
AK		 8453
8454 error = e1000_get_software_flag(hw);
8455 if (error != E1000_SUCCESS)
8456 return error;
8457
8458 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8459 * allocated. Subsequent reads to the modified words are read from
8460 * this cached structure as well. Writes will only go into this
8461 * cached structure unless it's followed by a call to
8462 * e1000_update_eeprom_checksum() where it will commit the changes
8463 * and clear the "modified" field.
8464 */
8465 if (hw->eeprom_shadow_ram != NULL) {
8466 for (i = 0; i < words; i++) {
8467 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
c3033b01 8468 hw->eeprom_shadow_ram[offset+i].modified = true;
d37ea5d5
AK		 8469 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8470 } else {
8471 error = -E1000_ERR_EEPROM;
8472 break;
8473 }
8474 }
8475 } else {
8476 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8477 * as they don't perform any NVM writes. An attempt in doing so
8478 * will result in this error.
8479 */
8480 error = -E1000_ERR_EEPROM;
8481 }
8482
8483 e1000_release_software_flag(hw);
8484
8485 return error;
8486}
8487
8488/******************************************************************************
8489 * This function does initial flash setup so that a new read/write/erase cycle
8490 * can be started.
8491 *
8492 * hw - The pointer to the hw structure
8493 ****************************************************************************/
406874a7 8494static s32
d37ea5d5
AK		 8495e1000_ich8_cycle_init(struct e1000_hw *hw)
8496{
8497 union ich8_hws_flash_status hsfsts;
406874a7
JP		 8498 s32 error = E1000_ERR_EEPROM;
8499 s32 i = 0;
d37ea5d5
AK		 8500
8501 DEBUGFUNC("e1000_ich8_cycle_init");
8502
2df7d59f 8503 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8504
8505 /* May be check the Flash Des Valid bit in Hw status */
8506 if (hsfsts.hsf_status.fldesvalid == 0) {
8507 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8508 return error;
8509 }
8510
8511 /* Clear FCERR in Hw status by writing 1 */
8512 /* Clear DAEL in Hw status by writing a 1 */
8513 hsfsts.hsf_status.flcerr = 1;
8514 hsfsts.hsf_status.dael = 1;
8515
2df7d59f 8516 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8517
8518 /* Either we should have a hardware SPI cycle in progress bit to check
8519 * against, in order to start a new cycle or FDONE bit should be changed
8520 * in the hardware so that it is 1 after harware reset, which can then be
8521 * used as an indication whether a cycle is in progress or has been
8522 * completed .. we should also have some software semaphore mechanism to
8523 * guard FDONE or the cycle in progress bit so that two threads access to
8524 * those bits can be sequentiallized or a way so that 2 threads dont
8525 * start the cycle at the same time */
8526
8527 if (hsfsts.hsf_status.flcinprog == 0) {
8528 /* There is no cycle running at present, so we can start a cycle */
8529 /* Begin by setting Flash Cycle Done. */
8530 hsfsts.hsf_status.flcdone = 1;
2df7d59f 8531 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8532 error = E1000_SUCCESS;
8533 } else {
8534 /* otherwise poll for sometime so the current cycle has a chance
8535 * to end before giving up. */
2df7d59f
JK		 8536 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8537 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8538 if (hsfsts.hsf_status.flcinprog == 0) {
8539 error = E1000_SUCCESS;
8540 break;
8541 }
8542 udelay(1);
8543 }
8544 if (error == E1000_SUCCESS) {
8545 /* Successful in waiting for previous cycle to timeout,
8546 * now set the Flash Cycle Done. */
8547 hsfsts.hsf_status.flcdone = 1;
2df7d59f 8548 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8549 } else {
8550 DEBUGOUT("Flash controller busy, cannot get access");
8551 }
8552 }
8553 return error;
8554}
8555
8556/******************************************************************************
8557 * This function starts a flash cycle and waits for its completion
8558 *
8559 * hw - The pointer to the hw structure
8560 ****************************************************************************/
406874a7
JP		 8561static s32
8562e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
d37ea5d5
AK		 8563{
8564 union ich8_hws_flash_ctrl hsflctl;
8565 union ich8_hws_flash_status hsfsts;
406874a7
JP		 8566 s32 error = E1000_ERR_EEPROM;
8567 u32 i = 0;
d37ea5d5
AK		 8568
8569 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2df7d59f 8570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5 8571 hsflctl.hsf_ctrl.flcgo = 1;
2df7d59f 8572 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8573
8574 /* wait till FDONE bit is set to 1 */
8575 do {
2df7d59f 8576 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8577 if (hsfsts.hsf_status.flcdone == 1)
8578 break;
8579 udelay(1);
8580 i++;
8581 } while (i < timeout);
8582 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8583 error = E1000_SUCCESS;
8584 }
8585 return error;
8586}
8587
8588/******************************************************************************
8589 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8590 *
8591 * hw - The pointer to the hw structure
8592 * index - The index of the byte or word to read.
8593 * size - Size of data to read, 1=byte 2=word
8594 * data - Pointer to the word to store the value read.
8595 *****************************************************************************/
406874a7
JP		 8596static s32
8597e1000_read_ich8_data(struct e1000_hw *hw, u32 index,
8598 u32 size, u16* data)
d37ea5d5
AK		 8599{
8600 union ich8_hws_flash_status hsfsts;
8601 union ich8_hws_flash_ctrl hsflctl;
406874a7
JP		 8602 u32 flash_linear_address;
8603 u32 flash_data = 0;
8604 s32 error = -E1000_ERR_EEPROM;
8605 s32 count = 0;
d37ea5d5
AK		 8606
8607 DEBUGFUNC("e1000_read_ich8_data");
8608
abec42a4 8609 if (size < 1 || size > 2 || data == NULL ||
2df7d59f 8610 index > ICH_FLASH_LINEAR_ADDR_MASK)
d37ea5d5
AK		 8611 return error;
8612
2df7d59f 8613 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
d37ea5d5
AK		 8614 hw->flash_base_addr;
8615
8616 do {
8617 udelay(1);
8618 /* Steps */
8619 error = e1000_ich8_cycle_init(hw);
8620 if (error != E1000_SUCCESS)
8621 break;
8622
2df7d59f 8623 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5
AK		 8624 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8625 hsflctl.hsf_ctrl.fldbcount = size - 1;
2df7d59f
JK		 8626 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8627 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8628
8629 /* Write the last 24 bits of index into Flash Linear address field in
8630 * Flash Address */
8631 /* TODO: TBD maybe check the index against the size of flash */
8632
2df7d59f 8633 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5 8634
2df7d59f 8635 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
d37ea5d5
AK		 8636
8637 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8638 * sequence a few more times, else read in (shift in) the Flash Data0,
8639 * the order is least significant byte first msb to lsb */
8640 if (error == E1000_SUCCESS) {
2df7d59f 8641 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
d37ea5d5 8642 if (size == 1) {
406874a7 8643 *data = (u8)(flash_data & 0x000000FF);
d37ea5d5 8644 } else if (size == 2) {
406874a7 8645 *data = (u16)(flash_data & 0x0000FFFF);
d37ea5d5
AK		 8646 }
8647 break;
8648 } else {
8649 /* If we've gotten here, then things are probably completely hosed,
8650 * but if the error condition is detected, it won't hurt to give
2df7d59f 8651 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
d37ea5d5 8652 */
2df7d59f 8653 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8654 if (hsfsts.hsf_status.flcerr == 1) {
8655 /* Repeat for some time before giving up. */
8656 continue;
8657 } else if (hsfsts.hsf_status.flcdone == 0) {
8658 DEBUGOUT("Timeout error - flash cycle did not complete.");
8659 break;
8660 }
8661 }
2df7d59f 8662 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
d37ea5d5
AK		 8663
8664 return error;
8665}
8666
8667/******************************************************************************
8668 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8669 *
8670 * hw - The pointer to the hw structure
8671 * index - The index of the byte/word to read.
8672 * size - Size of data to read, 1=byte 2=word
8673 * data - The byte(s) to write to the NVM.
8674 *****************************************************************************/
406874a7
JP		 8675static s32
8676e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8677 u16 data)
d37ea5d5
AK		 8678{
8679 union ich8_hws_flash_status hsfsts;
8680 union ich8_hws_flash_ctrl hsflctl;
406874a7
JP		 8681 u32 flash_linear_address;
8682 u32 flash_data = 0;
8683 s32 error = -E1000_ERR_EEPROM;
8684 s32 count = 0;
d37ea5d5
AK		 8685
8686 DEBUGFUNC("e1000_write_ich8_data");
8687
8688 if (size < 1 || size > 2 || data > size * 0xff ||
2df7d59f 8689 index > ICH_FLASH_LINEAR_ADDR_MASK)
d37ea5d5
AK		 8690 return error;
8691
2df7d59f 8692 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
d37ea5d5
AK		 8693 hw->flash_base_addr;
8694
8695 do {
8696 udelay(1);
8697 /* Steps */
8698 error = e1000_ich8_cycle_init(hw);
8699 if (error != E1000_SUCCESS)
8700 break;
8701
2df7d59f 8702 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5
AK		 8703 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8704 hsflctl.hsf_ctrl.fldbcount = size -1;
2df7d59f
JK		 8705 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8706 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8707
8708 /* Write the last 24 bits of index into Flash Linear address field in
8709 * Flash Address */
2df7d59f 8710 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5
AK		 8711
8712 if (size == 1)
406874a7 8713 flash_data = (u32)data & 0x00FF;
d37ea5d5 8714 else
406874a7 8715 flash_data = (u32)data;
d37ea5d5 8716
2df7d59f 8717 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
d37ea5d5
AK		 8718
8719 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8720 * sequence a few more times else done */
2df7d59f 8721 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
d37ea5d5
AK		 8722 if (error == E1000_SUCCESS) {
8723 break;
8724 } else {
8725 /* If we're here, then things are most likely completely hosed,
8726 * but if the error condition is detected, it won't hurt to give
2df7d59f 8727 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
d37ea5d5 8728 */
2df7d59f 8729 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8730 if (hsfsts.hsf_status.flcerr == 1) {
8731 /* Repeat for some time before giving up. */
8732 continue;
8733 } else if (hsfsts.hsf_status.flcdone == 0) {
8734 DEBUGOUT("Timeout error - flash cycle did not complete.");
8735 break;
8736 }
8737 }
2df7d59f 8738 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
d37ea5d5
AK		 8739
8740 return error;
8741}
8742
8743/******************************************************************************
8744 * Reads a single byte from the NVM using the ICH8 flash access registers.
8745 *
8746 * hw - pointer to e1000_hw structure
8747 * index - The index of the byte to read.
8748 * data - Pointer to a byte to store the value read.
8749 *****************************************************************************/
406874a7
JP		 8750static s32
8751e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data)
d37ea5d5 8752{
406874a7
JP		 8753 s32 status = E1000_SUCCESS;
8754 u16 word = 0;
d37ea5d5
AK		 8755
8756 status = e1000_read_ich8_data(hw, index, 1, &word);
8757 if (status == E1000_SUCCESS) {
406874a7 8758 *data = (u8)word;
d37ea5d5
AK		 8759 }
8760
8761 return status;
8762}
8763
8764/******************************************************************************
8765 * Writes a single byte to the NVM using the ICH8 flash access registers.
8766 * Performs verification by reading back the value and then going through
8767 * a retry algorithm before giving up.
8768 *
8769 * hw - pointer to e1000_hw structure
8770 * index - The index of the byte to write.
8771 * byte - The byte to write to the NVM.
8772 *****************************************************************************/
406874a7
JP		 8773static s32
8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
d37ea5d5 8775{
406874a7
JP		 8776 s32 error = E1000_SUCCESS;
8777 s32 program_retries = 0;
d37ea5d5 8778
2a88c173 8779 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
d37ea5d5 8780
2a88c173
JK		 8781 error = e1000_write_ich8_byte(hw, index, byte);
8782
8783 if (error != E1000_SUCCESS) {
8784 for (program_retries = 0; program_retries < 100; program_retries++) {
8785 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8786 error = e1000_write_ich8_byte(hw, index, byte);
8787 udelay(100);
8788 if (error == E1000_SUCCESS)
8789 break;
8790 }
d37ea5d5 8791 }
2a88c173 8792
d37ea5d5
AK		 8793 if (program_retries == 100)
8794 error = E1000_ERR_EEPROM;
8795
8796 return error;
8797}
8798
8799/******************************************************************************
8800 * Writes a single byte to the NVM using the ICH8 flash access registers.
8801 *
8802 * hw - pointer to e1000_hw structure
8803 * index - The index of the byte to read.
8804 * data - The byte to write to the NVM.
8805 *****************************************************************************/
406874a7
JP		 8806static s32
8807e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
d37ea5d5 8808{
406874a7
JP		 8809 s32 status = E1000_SUCCESS;
8810 u16 word = (u16)data;
d37ea5d5
AK		 8811
8812 status = e1000_write_ich8_data(hw, index, 1, word);
8813
8814 return status;
8815}
8816
8817/******************************************************************************
8818 * Reads a word from the NVM using the ICH8 flash access registers.
8819 *
8820 * hw - pointer to e1000_hw structure
8821 * index - The starting byte index of the word to read.
8822 * data - Pointer to a word to store the value read.
8823 *****************************************************************************/
406874a7
JP		 8824static s32
8825e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
d37ea5d5 8826{
406874a7 8827 s32 status = E1000_SUCCESS;
d37ea5d5
AK		 8828 status = e1000_read_ich8_data(hw, index, 2, data);
8829 return status;
8830}
8831
8832/******************************************************************************
2a88c173
JK		 8833 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8834 * based.
d37ea5d5
AK		 8835 *
8836 * hw - pointer to e1000_hw structure
2a88c173 8837 * bank - 0 for first bank, 1 for second bank
d37ea5d5 8838 *
2a88c173
JK		 8839 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8841 * bank size may be 4, 8 or 64 KBytes
d37ea5d5 8842 *****************************************************************************/
406874a7
JP		 8843static s32
8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
d37ea5d5
AK		 8845{
8846 union ich8_hws_flash_status hsfsts;
8847 union ich8_hws_flash_ctrl hsflctl;
406874a7
JP		 8848 u32 flash_linear_address;
8849 s32 count = 0;
8850 s32 error = E1000_ERR_EEPROM;
8851 s32 iteration;
8852 s32 sub_sector_size = 0;
8853 s32 bank_size;
8854 s32 j = 0;
8855 s32 error_flag = 0;
d37ea5d5 8856
2df7d59f 8857 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8858
8859 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8860 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8861 * consecutive sectors. The start index for the nth Hw sector can be
2a88c173 8862 * calculated as bank * 4096 + n * 256
d37ea5d5
AK		 8863 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8864 * The start index for the nth Hw sector can be calculated
2a88c173
JK		 8865 * as bank * 4096
8866 * 10: The HW sector is 8K bytes
8867 * 11: The Hw sector size is 64K bytes */
d37ea5d5
AK		 8868 if (hsfsts.hsf_status.berasesz == 0x0) {
8869 /* Hw sector size 256 */
2df7d59f
JK		 8870 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8871 bank_size = ICH_FLASH_SECTOR_SIZE;
8872 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
d37ea5d5 8873 } else if (hsfsts.hsf_status.berasesz == 0x1) {
2df7d59f 8874 bank_size = ICH_FLASH_SEG_SIZE_4K;
d37ea5d5
AK		 8875 iteration = 1;
8876 } else if (hsfsts.hsf_status.berasesz == 0x3) {
2df7d59f 8877 bank_size = ICH_FLASH_SEG_SIZE_64K;
d37ea5d5
AK		 8878 iteration = 1;
8879 } else {
8880 return error;
8881 }
8882
8883 for (j = 0; j < iteration ; j++) {
8884 do {
8885 count++;
8886 /* Steps */
8887 error = e1000_ich8_cycle_init(hw);
8888 if (error != E1000_SUCCESS) {
8889 error_flag = 1;
8890 break;
8891 }
8892
8893 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8894 * Control */
2df7d59f
JK		 8895 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8896 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8897 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8898
8899 /* Write the last 24 bits of an index within the block into Flash
8900 * Linear address field in Flash Address. This probably needs to
2a88c173
JK		 8901 * be calculated here based off the on-chip erase sector size and
8902 * the software bank size (4, 8 or 64 KBytes) */
8903 flash_linear_address = bank * bank_size + j * sub_sector_size;
d37ea5d5 8904 flash_linear_address += hw->flash_base_addr;
2df7d59f 8905 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
d37ea5d5 8906
2df7d59f 8907 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5 8908
2df7d59f 8909 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
d37ea5d5
AK		 8910 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8911 * sequence a few more times else Done */
8912 if (error == E1000_SUCCESS) {
8913 break;
8914 } else {
2df7d59f 8915 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8916 if (hsfsts.hsf_status.flcerr == 1) {
8917 /* repeat for some time before giving up */
8918 continue;
8919 } else if (hsfsts.hsf_status.flcdone == 0) {
8920 error_flag = 1;
8921 break;
8922 }
8923 }
2df7d59f 8924 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
d37ea5d5
AK		 8925 if (error_flag == 1)
8926 break;
8927 }
8928 if (error_flag != 1)
8929 error = E1000_SUCCESS;
8930 return error;
8931}
8932
406874a7 8933static s32
d37ea5d5 8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
406874a7 8935 u32 cnf_base_addr, u32 cnf_size)
d37ea5d5 8936{
406874a7
JP		 8937 u32 ret_val = E1000_SUCCESS;
8938 u16 word_addr, reg_data, reg_addr;
8939 u16 i;
d37ea5d5
AK		 8940
8941 /* cnf_base_addr is in DWORD */
406874a7 8942 word_addr = (u16)(cnf_base_addr << 1);
d37ea5d5
AK		 8943
8944 /* cnf_size is returned in size of dwords */
8945 for (i = 0; i < cnf_size; i++) {
8946 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8947 if (ret_val)
8948 return ret_val;
8949
8950 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8951 if (ret_val)
8952 return ret_val;
8953
8954 ret_val = e1000_get_software_flag(hw);
8955 if (ret_val != E1000_SUCCESS)
8956 return ret_val;
8957
406874a7 8958 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
d37ea5d5
AK		 8959
8960 e1000_release_software_flag(hw);
8961 }
8962
8963 return ret_val;
8964}
8965
8966
2a88c173
JK		 8967/******************************************************************************
8968 * This function initializes the PHY from the NVM on ICH8 platforms. This
8969 * is needed due to an issue where the NVM configuration is not properly
8970 * autoloaded after power transitions. Therefore, after each PHY reset, we
8971 * will load the configuration data out of the NVM manually.
8972 *
8973 * hw: Struct containing variables accessed by shared code
8974 *****************************************************************************/
406874a7 8975static s32
d37ea5d5
AK		 8976e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8977{
406874a7 8978 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
d37ea5d5
AK		 8979
8980 if (hw->phy_type != e1000_phy_igp_3)
8981 return E1000_SUCCESS;
8982
8983 /* Check if SW needs configure the PHY */
8984 reg_data = E1000_READ_REG(hw, FEXTNVM);
8985 if (!(reg_data & FEXTNVM_SW_CONFIG))
8986 return E1000_SUCCESS;
8987
8988 /* Wait for basic configuration completes before proceeding*/
8989 loop = 0;
8990 do {
8991 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8992 udelay(100);
8993 loop++;
8994 } while ((!reg_data) && (loop < 50));
8995
8996 /* Clear the Init Done bit for the next init event */
8997 reg_data = E1000_READ_REG(hw, STATUS);
8998 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8999 E1000_WRITE_REG(hw, STATUS, reg_data);
9000
9001 /* Make sure HW does not configure LCD from PHY extended configuration
9002 before SW configuration */
9003 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9004 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9005 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9006 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9007 cnf_size >>= 16;
9008 if (cnf_size) {
9009 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9010 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9011 /* cnf_base_addr is in DWORD */
9012 cnf_base_addr >>= 16;
9013
9014 /* Configure LCD from extended configuration region. */
9015 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9016 cnf_size);
9017 if (ret_val)
9018 return ret_val;
9019 }
9020 }
9021
9022 return E1000_SUCCESS;
9023}
9024
Linux kernel - Deliverables
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