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[NET]: Stop polling when napi_disable() is pending.
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
d0bb53e1 30#include <net/ip6_checksum.h>
1da177e4 31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
7e721579 39#define DRV_VERSION "7.3.20-k2"DRIVERNAPI
abec42a4
SH		 40const char e1000_driver_version[] = DRV_VERSION;
41static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 76 INTEL_E1000_ETHERNET_DEVICE(0x1049),
77 INTEL_E1000_ETHERNET_DEVICE(0x104A),
78 INTEL_E1000_ETHERNET_DEVICE(0x104B),
79 INTEL_E1000_ETHERNET_DEVICE(0x104C),
80 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 81 INTEL_E1000_ETHERNET_DEVICE(0x105E),
82 INTEL_E1000_ETHERNET_DEVICE(0x105F),
83 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 84 INTEL_E1000_ETHERNET_DEVICE(0x1075),
85 INTEL_E1000_ETHERNET_DEVICE(0x1076),
86 INTEL_E1000_ETHERNET_DEVICE(0x1077),
87 INTEL_E1000_ETHERNET_DEVICE(0x1078),
88 INTEL_E1000_ETHERNET_DEVICE(0x1079),
89 INTEL_E1000_ETHERNET_DEVICE(0x107A),
90 INTEL_E1000_ETHERNET_DEVICE(0x107B),
91 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 92 INTEL_E1000_ETHERNET_DEVICE(0x107D),
93 INTEL_E1000_ETHERNET_DEVICE(0x107E),
94 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 95 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 96 INTEL_E1000_ETHERNET_DEVICE(0x108B),
97 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 98 INTEL_E1000_ETHERNET_DEVICE(0x1096),
99 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
5881cde8 102 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
ce57a02c 103 INTEL_E1000_ETHERNET_DEVICE(0x10A5),
b7ee49db 104 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 105 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 106 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
107 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
fc2307d0
AK		 108 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
109 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
110 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
f4ec7f98 111 INTEL_E1000_ETHERNET_DEVICE(0x10D5),
ce57a02c
AK		 112 INTEL_E1000_ETHERNET_DEVICE(0x10D9),
113 INTEL_E1000_ETHERNET_DEVICE(0x10DA),
1da177e4
LT		 114 /* required last entry */
115 {0,}
116};
117
118MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
119
35574764
NN		 120int e1000_up(struct e1000_adapter *adapter);
121void e1000_down(struct e1000_adapter *adapter);
122void e1000_reinit_locked(struct e1000_adapter *adapter);
123void e1000_reset(struct e1000_adapter *adapter);
124int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
125int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
126int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
127void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
128void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 129static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 130 struct e1000_tx_ring *txdr);
3ad2cc67 131static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 132 struct e1000_rx_ring *rxdr);
3ad2cc67 133static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 134 struct e1000_tx_ring *tx_ring);
3ad2cc67 135static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 136 struct e1000_rx_ring *rx_ring);
137void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 138
139static int e1000_init_module(void);
140static void e1000_exit_module(void);
141static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
142static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 143static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 144static int e1000_sw_init(struct e1000_adapter *adapter);
145static int e1000_open(struct net_device *netdev);
146static int e1000_close(struct net_device *netdev);
147static void e1000_configure_tx(struct e1000_adapter *adapter);
148static void e1000_configure_rx(struct e1000_adapter *adapter);
149static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 150static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
151static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
152static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
153 struct e1000_tx_ring *tx_ring);
154static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
155 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 156static void e1000_set_multi(struct net_device *netdev);
157static void e1000_update_phy_info(unsigned long data);
158static void e1000_watchdog(unsigned long data);
1da177e4
LT		 159static void e1000_82547_tx_fifo_stall(unsigned long data);
160static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
161static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
162static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
163static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 164static irqreturn_t e1000_intr(int irq, void *data);
9ac98284 165static irqreturn_t e1000_intr_msi(int irq, void *data);
581d708e
MC		 166static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
167 struct e1000_tx_ring *tx_ring);
1da177e4 168#ifdef CONFIG_E1000_NAPI
bea3348e 169static int e1000_clean(struct napi_struct *napi, int budget);
1da177e4 170static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 171 struct e1000_rx_ring *rx_ring,
1da177e4 172 int *work_done, int work_to_do);
2d7edb92 173static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 174 struct e1000_rx_ring *rx_ring,
2d7edb92 175 int *work_done, int work_to_do);
1da177e4 176#else
581d708e
MC		 177static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
178 struct e1000_rx_ring *rx_ring);
179static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
180 struct e1000_rx_ring *rx_ring);
1da177e4 181#endif
581d708e 182static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 183 struct e1000_rx_ring *rx_ring,
184 int cleaned_count);
581d708e 185static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 186 struct e1000_rx_ring *rx_ring,
187 int cleaned_count);
1da177e4
LT		 188static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
189static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
190 int cmd);
1da177e4
LT		 191static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
192static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
193static void e1000_tx_timeout(struct net_device *dev);
65f27f38 194static void e1000_reset_task(struct work_struct *work);
1da177e4 195static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 196static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
197 struct sk_buff *skb);
1da177e4
LT		 198
199static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
200static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
201static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
202static void e1000_restore_vlan(struct e1000_adapter *adapter);
203
977e74b5 204static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 205#ifdef CONFIG_PM
1da177e4
LT		 206static int e1000_resume(struct pci_dev *pdev);
207#endif
c653e635 208static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 209
210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void e1000_netpoll (struct net_device *netdev);
213#endif
214
1f753861
JB		 215#define COPYBREAK_DEFAULT 256
216static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
217module_param(copybreak, uint, 0644);
218MODULE_PARM_DESC(copybreak,
219 "Maximum size of packet that is copied to a new buffer on receive");
220
9026729b
AK		 221static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
222 pci_channel_state_t state);
223static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
224static void e1000_io_resume(struct pci_dev *pdev);
225
226static struct pci_error_handlers e1000_err_handler = {
227 .error_detected = e1000_io_error_detected,
228 .slot_reset = e1000_io_slot_reset,
229 .resume = e1000_io_resume,
230};
24025e4e 231
1da177e4
LT		 232static struct pci_driver e1000_driver = {
233 .name = e1000_driver_name,
234 .id_table = e1000_pci_tbl,
235 .probe = e1000_probe,
236 .remove = __devexit_p(e1000_remove),
c4e24f01 237#ifdef CONFIG_PM
1da177e4 238 /* Power Managment Hooks */
1da177e4 239 .suspend = e1000_suspend,
c653e635 240 .resume = e1000_resume,
1da177e4 241#endif
9026729b
AK		 242 .shutdown = e1000_shutdown,
243 .err_handler = &e1000_err_handler
1da177e4
LT		 244};
245
246MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
247MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
251static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
252module_param(debug, int, 0);
253MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
254
255/**
256 * e1000_init_module - Driver Registration Routine
257 *
258 * e1000_init_module is the first routine called when the driver is
259 * loaded. All it does is register with the PCI subsystem.
260 **/
261
262static int __init
263e1000_init_module(void)
264{
265 int ret;
266 printk(KERN_INFO "%s - version %s\n",
267 e1000_driver_string, e1000_driver_version);
268
269 printk(KERN_INFO "%s\n", e1000_copyright);
270
29917620 271 ret = pci_register_driver(&e1000_driver);
1f753861
JB		 272 if (copybreak != COPYBREAK_DEFAULT) {
273 if (copybreak == 0)
274 printk(KERN_INFO "e1000: copybreak disabled\n");
275 else
276 printk(KERN_INFO "e1000: copybreak enabled for "
277 "packets <= %u bytes\n", copybreak);
278 }
1da177e4
LT		 279 return ret;
280}
281
282module_init(e1000_init_module);
283
284/**
285 * e1000_exit_module - Driver Exit Cleanup Routine
286 *
287 * e1000_exit_module is called just before the driver is removed
288 * from memory.
289 **/
290
291static void __exit
292e1000_exit_module(void)
293{
1da177e4
LT		 294 pci_unregister_driver(&e1000_driver);
295}
296
297module_exit(e1000_exit_module);
298
2db10a08
AK		 299static int e1000_request_irq(struct e1000_adapter *adapter)
300{
301 struct net_device *netdev = adapter->netdev;
e94bd23f
AK		 302 void (*handler) = &e1000_intr;
303 int irq_flags = IRQF_SHARED;
304 int err;
2db10a08 305
9ac98284 306 if (adapter->hw.mac_type >= e1000_82571) {
e94bd23f
AK		 307 adapter->have_msi = !pci_enable_msi(adapter->pdev);
308 if (adapter->have_msi) {
309 handler = &e1000_intr_msi;
310 irq_flags = 0;
2db10a08
AK		 311 }
312 }
e94bd23f
AK		 313
314 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
315 netdev);
316 if (err) {
317 if (adapter->have_msi)
318 pci_disable_msi(adapter->pdev);
2db10a08
AK		 319 DPRINTK(PROBE, ERR,
320 "Unable to allocate interrupt Error: %d\n", err);
e94bd23f 321 }
2db10a08
AK		 322
323 return err;
324}
325
326static void e1000_free_irq(struct e1000_adapter *adapter)
327{
328 struct net_device *netdev = adapter->netdev;
329
330 free_irq(adapter->pdev->irq, netdev);
331
2db10a08
AK		 332 if (adapter->have_msi)
333 pci_disable_msi(adapter->pdev);
2db10a08
AK		 334}
335
1da177e4
LT		 336/**
337 * e1000_irq_disable - Mask off interrupt generation on the NIC
338 * @adapter: board private structure
339 **/
340
e619d523 341static void
1da177e4
LT		 342e1000_irq_disable(struct e1000_adapter *adapter)
343{
344 atomic_inc(&adapter->irq_sem);
345 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
346 E1000_WRITE_FLUSH(&adapter->hw);
347 synchronize_irq(adapter->pdev->irq);
348}
349
350/**
351 * e1000_irq_enable - Enable default interrupt generation settings
352 * @adapter: board private structure
353 **/
354
e619d523 355static void
1da177e4
LT		 356e1000_irq_enable(struct e1000_adapter *adapter)
357{
96838a40 358 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 359 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
360 E1000_WRITE_FLUSH(&adapter->hw);
361 }
362}
3ad2cc67
AB		 363
364static void
2d7edb92
MC		 365e1000_update_mng_vlan(struct e1000_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
369 uint16_t old_vid = adapter->mng_vlan_id;
96838a40 370 if (adapter->vlgrp) {
5c15bdec 371 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
96838a40 372 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 373 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
374 e1000_vlan_rx_add_vid(netdev, vid);
375 adapter->mng_vlan_id = vid;
376 } else
377 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 378
379 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
380 (vid != old_vid) &&
5c15bdec 381 !vlan_group_get_device(adapter->vlgrp, old_vid))
2d7edb92 382 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 383 } else
384 adapter->mng_vlan_id = vid;
2d7edb92
MC		 385 }
386}
b55ccb35
JK		 387
388/**
389 * e1000_release_hw_control - release control of the h/w to f/w
390 * @adapter: address of board private structure
391 *
392 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
393 * For ASF and Pass Through versions of f/w this means that the
394 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 395 * of the f/w this means that the network i/f is closed.
76c224bc 396 *
b55ccb35
JK		 397 **/
398
e619d523 399static void
b55ccb35
JK		 400e1000_release_hw_control(struct e1000_adapter *adapter)
401{
402 uint32_t ctrl_ext;
403 uint32_t swsm;
404
405 /* Let firmware taken over control of h/w */
406 switch (adapter->hw.mac_type) {
b55ccb35
JK		 407 case e1000_82573:
408 swsm = E1000_READ_REG(&adapter->hw, SWSM);
409 E1000_WRITE_REG(&adapter->hw, SWSM,
410 swsm & ~E1000_SWSM_DRV_LOAD);
31d76442
BA		 411 break;
412 case e1000_82571:
413 case e1000_82572:
414 case e1000_80003es2lan:
cd94dd0b 415 case e1000_ich8lan:
31d76442 416 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
cd94dd0b 417 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
31d76442 418 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 419 break;
b55ccb35
JK		 420 default:
421 break;
422 }
423}
424
425/**
426 * e1000_get_hw_control - get control of the h/w from f/w
427 * @adapter: address of board private structure
428 *
429 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 430 * For ASF and Pass Through versions of f/w this means that
431 * the driver is loaded. For AMT version (only with 82573)
90fb5135 432 * of the f/w this means that the network i/f is open.
76c224bc 433 *
b55ccb35
JK		 434 **/
435
e619d523 436static void
b55ccb35
JK		 437e1000_get_hw_control(struct e1000_adapter *adapter)
438{
439 uint32_t ctrl_ext;
440 uint32_t swsm;
90fb5135 441
b55ccb35
JK		 442 /* Let firmware know the driver has taken over */
443 switch (adapter->hw.mac_type) {
b55ccb35
JK		 444 case e1000_82573:
445 swsm = E1000_READ_REG(&adapter->hw, SWSM);
446 E1000_WRITE_REG(&adapter->hw, SWSM,
447 swsm | E1000_SWSM_DRV_LOAD);
448 break;
31d76442
BA		 449 case e1000_82571:
450 case e1000_82572:
451 case e1000_80003es2lan:
cd94dd0b 452 case e1000_ich8lan:
31d76442
BA		 453 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
454 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
455 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 456 break;
b55ccb35
JK		 457 default:
458 break;
459 }
460}
461
0fccd0e9
JG		 462static void
463e1000_init_manageability(struct e1000_adapter *adapter)
464{
465 if (adapter->en_mng_pt) {
466 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
467
468 /* disable hardware interception of ARP */
469 manc &= ~(E1000_MANC_ARP_EN);
470
471 /* enable receiving management packets to the host */
472 /* this will probably generate destination unreachable messages
473 * from the host OS, but the packets will be handled on SMBUS */
474 if (adapter->hw.has_manc2h) {
475 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
476
477 manc |= E1000_MANC_EN_MNG2HOST;
478#define E1000_MNG2HOST_PORT_623 (1 << 5)
479#define E1000_MNG2HOST_PORT_664 (1 << 6)
480 manc2h |= E1000_MNG2HOST_PORT_623;
481 manc2h |= E1000_MNG2HOST_PORT_664;
482 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
483 }
484
485 E1000_WRITE_REG(&adapter->hw, MANC, manc);
486 }
487}
488
489static void
490e1000_release_manageability(struct e1000_adapter *adapter)
491{
492 if (adapter->en_mng_pt) {
493 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
494
495 /* re-enable hardware interception of ARP */
496 manc |= E1000_MANC_ARP_EN;
497
498 if (adapter->hw.has_manc2h)
499 manc &= ~E1000_MANC_EN_MNG2HOST;
500
501 /* don't explicitly have to mess with MANC2H since
502 * MANC has an enable disable that gates MANC2H */
503
504 E1000_WRITE_REG(&adapter->hw, MANC, manc);
505 }
506}
507
e0aac5a2
AK		 508/**
509 * e1000_configure - configure the hardware for RX and TX
510 * @adapter = private board structure
511 **/
512static void e1000_configure(struct e1000_adapter *adapter)
1da177e4
LT		 513{
514 struct net_device *netdev = adapter->netdev;
2db10a08 515 int i;
1da177e4 516
1da177e4
LT		 517 e1000_set_multi(netdev);
518
519 e1000_restore_vlan(adapter);
0fccd0e9 520 e1000_init_manageability(adapter);
1da177e4
LT		 521
522 e1000_configure_tx(adapter);
523 e1000_setup_rctl(adapter);
524 e1000_configure_rx(adapter);
72d64a43
JK		 525 /* call E1000_DESC_UNUSED which always leaves
526 * at least 1 descriptor unused to make sure
527 * next_to_use != next_to_clean */
f56799ea 528 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 529 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 530 adapter->alloc_rx_buf(adapter, ring,
531 E1000_DESC_UNUSED(ring));
f56799ea 532 }
1da177e4 533
7bfa4816 534 adapter->tx_queue_len = netdev->tx_queue_len;
e0aac5a2
AK		 535}
536
537int e1000_up(struct e1000_adapter *adapter)
538{
539 /* hardware has been reset, we need to reload some things */
540 e1000_configure(adapter);
541
542 clear_bit(__E1000_DOWN, &adapter->flags);
7bfa4816 543
1da177e4 544#ifdef CONFIG_E1000_NAPI
bea3348e 545 napi_enable(&adapter->napi);
1da177e4 546#endif
5de55624
MC		 547 e1000_irq_enable(adapter);
548
79f3d399
JB		 549 /* fire a link change interrupt to start the watchdog */
550 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1da177e4
LT		 551 return 0;
552}
553
79f05bf0
AK		 554/**
555 * e1000_power_up_phy - restore link in case the phy was powered down
556 * @adapter: address of board private structure
557 *
558 * The phy may be powered down to save power and turn off link when the
559 * driver is unloaded and wake on lan is not enabled (among others)
560 * *** this routine MUST be followed by a call to e1000_reset ***
561 *
562 **/
563
d658266e 564void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 565{
566 uint16_t mii_reg = 0;
567
568 /* Just clear the power down bit to wake the phy back up */
569 if (adapter->hw.media_type == e1000_media_type_copper) {
570 /* according to the manual, the phy will retain its
571 * settings across a power-down/up cycle */
572 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
573 mii_reg &= ~MII_CR_POWER_DOWN;
574 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
575 }
576}
577
578static void e1000_power_down_phy(struct e1000_adapter *adapter)
579{
61c2505f
BA		 580 /* Power down the PHY so no link is implied when interface is down *
581 * The PHY cannot be powered down if any of the following is TRUE *
79f05bf0
AK		 582 * (a) WoL is enabled
583 * (b) AMT is active
584 * (c) SoL/IDER session is active */
585 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 586 adapter->hw.media_type == e1000_media_type_copper) {
79f05bf0 587 uint16_t mii_reg = 0;
61c2505f
BA		 588
589 switch (adapter->hw.mac_type) {
590 case e1000_82540:
591 case e1000_82545:
592 case e1000_82545_rev_3:
593 case e1000_82546:
594 case e1000_82546_rev_3:
595 case e1000_82541:
596 case e1000_82541_rev_2:
597 case e1000_82547:
598 case e1000_82547_rev_2:
599 if (E1000_READ_REG(&adapter->hw, MANC) &
600 E1000_MANC_SMBUS_EN)
601 goto out;
602 break;
603 case e1000_82571:
604 case e1000_82572:
605 case e1000_82573:
606 case e1000_80003es2lan:
607 case e1000_ich8lan:
608 if (e1000_check_mng_mode(&adapter->hw) ||
609 e1000_check_phy_reset_block(&adapter->hw))
610 goto out;
611 break;
612 default:
613 goto out;
614 }
79f05bf0
AK		 615 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
616 mii_reg |= MII_CR_POWER_DOWN;
617 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
618 mdelay(1);
619 }
61c2505f
BA		 620out:
621 return;
79f05bf0
AK		 622}
623
1da177e4
LT		 624void
625e1000_down(struct e1000_adapter *adapter)
626{
627 struct net_device *netdev = adapter->netdev;
628
1314bbf3
AK		 629 /* signal that we're down so the interrupt handler does not
630 * reschedule our watchdog timer */
631 set_bit(__E1000_DOWN, &adapter->flags);
632
e0aac5a2 633#ifdef CONFIG_E1000_NAPI
bea3348e 634 napi_disable(&adapter->napi);
e0aac5a2 635#endif
1da177e4 636 e1000_irq_disable(adapter);
c1605eb3 637
1da177e4
LT		 638 del_timer_sync(&adapter->tx_fifo_stall_timer);
639 del_timer_sync(&adapter->watchdog_timer);
640 del_timer_sync(&adapter->phy_info_timer);
641
7bfa4816 642 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 643 adapter->link_speed = 0;
644 adapter->link_duplex = 0;
645 netif_carrier_off(netdev);
646 netif_stop_queue(netdev);
647
648 e1000_reset(adapter);
581d708e
MC		 649 e1000_clean_all_tx_rings(adapter);
650 e1000_clean_all_rx_rings(adapter);
1da177e4 651}
1da177e4 652
2db10a08
AK		 653void
654e1000_reinit_locked(struct e1000_adapter *adapter)
655{
656 WARN_ON(in_interrupt());
657 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
658 msleep(1);
659 e1000_down(adapter);
660 e1000_up(adapter);
661 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 662}
663
664void
665e1000_reset(struct e1000_adapter *adapter)
666{
018ea44e 667 uint32_t pba = 0, tx_space, min_tx_space, min_rx_space;
1125ecbc 668 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
018ea44e 669 boolean_t legacy_pba_adjust = FALSE;
1da177e4
LT		 670
671 /* Repartition Pba for greater than 9k mtu
672 * To take effect CTRL.RST is required.
673 */
674
2d7edb92 675 switch (adapter->hw.mac_type) {
018ea44e
BA		 676 case e1000_82542_rev2_0:
677 case e1000_82542_rev2_1:
678 case e1000_82543:
679 case e1000_82544:
680 case e1000_82540:
681 case e1000_82541:
682 case e1000_82541_rev_2:
683 legacy_pba_adjust = TRUE;
684 pba = E1000_PBA_48K;
685 break;
686 case e1000_82545:
687 case e1000_82545_rev_3:
688 case e1000_82546:
689 case e1000_82546_rev_3:
690 pba = E1000_PBA_48K;
691 break;
2d7edb92 692 case e1000_82547:
0e6ef3e0 693 case e1000_82547_rev_2:
018ea44e 694 legacy_pba_adjust = TRUE;
2d7edb92
MC		 695 pba = E1000_PBA_30K;
696 break;
868d5309
MC		 697 case e1000_82571:
698 case e1000_82572:
6418ecc6 699 case e1000_80003es2lan:
868d5309
MC		 700 pba = E1000_PBA_38K;
701 break;
2d7edb92 702 case e1000_82573:
018ea44e 703 pba = E1000_PBA_20K;
2d7edb92 704 break;
cd94dd0b
AK		 705 case e1000_ich8lan:
706 pba = E1000_PBA_8K;
018ea44e
BA		 707 case e1000_undefined:
708 case e1000_num_macs:
2d7edb92
MC		 709 break;
710 }
711
018ea44e
BA		 712 if (legacy_pba_adjust == TRUE) {
713 if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
714 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92 715
018ea44e
BA		 716 if (adapter->hw.mac_type == e1000_82547) {
717 adapter->tx_fifo_head = 0;
718 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
719 adapter->tx_fifo_size =
720 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
721 atomic_set(&adapter->tx_fifo_stall, 0);
722 }
723 } else if (adapter->hw.max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) {
724 /* adjust PBA for jumbo frames */
725 E1000_WRITE_REG(&adapter->hw, PBA, pba);
726
727 /* To maintain wire speed transmits, the Tx FIFO should be
728 * large enough to accomodate two full transmit packets,
729 * rounded up to the next 1KB and expressed in KB. Likewise,
730 * the Rx FIFO should be large enough to accomodate at least
731 * one full receive packet and is similarly rounded up and
732 * expressed in KB. */
733 pba = E1000_READ_REG(&adapter->hw, PBA);
734 /* upper 16 bits has Tx packet buffer allocation size in KB */
735 tx_space = pba >> 16;
736 /* lower 16 bits has Rx packet buffer allocation size in KB */
737 pba &= 0xffff;
738 /* don't include ethernet FCS because hardware appends/strips */
739 min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE +
740 VLAN_TAG_SIZE;
741 min_tx_space = min_rx_space;
742 min_tx_space *= 2;
9099cfb9 743 min_tx_space = ALIGN(min_tx_space, 1024);
018ea44e 744 min_tx_space >>= 10;
9099cfb9 745 min_rx_space = ALIGN(min_rx_space, 1024);
018ea44e
BA		 746 min_rx_space >>= 10;
747
748 /* If current Tx allocation is less than the min Tx FIFO size,
749 * and the min Tx FIFO size is less than the current Rx FIFO
750 * allocation, take space away from current Rx allocation */
751 if (tx_space < min_tx_space &&
752 ((min_tx_space - tx_space) < pba)) {
753 pba = pba - (min_tx_space - tx_space);
754
755 /* PCI/PCIx hardware has PBA alignment constraints */
756 switch (adapter->hw.mac_type) {
757 case e1000_82545 ... e1000_82546_rev_3:
758 pba &= ~(E1000_PBA_8K - 1);
759 break;
760 default:
761 break;
762 }
763
764 /* if short on rx space, rx wins and must trump tx
765 * adjustment or use Early Receive if available */
766 if (pba < min_rx_space) {
767 switch (adapter->hw.mac_type) {
768 case e1000_82573:
769 /* ERT enabled in e1000_configure_rx */
770 break;
771 default:
772 pba = min_rx_space;
773 break;
774 }
775 }
776 }
1da177e4 777 }
2d7edb92 778
1da177e4
LT		 779 E1000_WRITE_REG(&adapter->hw, PBA, pba);
780
781 /* flow control settings */
f11b7f85
JK		 782 /* Set the FC high water mark to 90% of the FIFO size.
783 * Required to clear last 3 LSB */
784 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 785 /* We can't use 90% on small FIFOs because the remainder
786 * would be less than 1 full frame. In this case, we size
787 * it to allow at least a full frame above the high water
788 * mark. */
789 if (pba < E1000_PBA_16K)
790 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 791
792 adapter->hw.fc_high_water = fc_high_water_mark;
793 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 794 if (adapter->hw.mac_type == e1000_80003es2lan)
795 adapter->hw.fc_pause_time = 0xFFFF;
796 else
797 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 798 adapter->hw.fc_send_xon = 1;
799 adapter->hw.fc = adapter->hw.original_fc;
800
2d7edb92 801 /* Allow time for pending master requests to run */
1da177e4 802 e1000_reset_hw(&adapter->hw);
96838a40 803 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 804 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 805
96838a40 806 if (e1000_init_hw(&adapter->hw))
1da177e4 807 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 808 e1000_update_mng_vlan(adapter);
3d5460a0
JB		 809
810 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
811 if (adapter->hw.mac_type >= e1000_82544 &&
812 adapter->hw.mac_type <= e1000_82547_rev_2 &&
813 adapter->hw.autoneg == 1 &&
814 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
815 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
816 /* clear phy power management bit if we are in gig only mode,
817 * which if enabled will attempt negotiation to 100Mb, which
818 * can cause a loss of link at power off or driver unload */
819 ctrl &= ~E1000_CTRL_SWDPIN3;
820 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
821 }
822
1da177e4
LT		 823 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
824 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
825
826 e1000_reset_adaptive(&adapter->hw);
827 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 828
829 if (!adapter->smart_power_down &&
830 (adapter->hw.mac_type == e1000_82571 ||
831 adapter->hw.mac_type == e1000_82572)) {
832 uint16_t phy_data = 0;
833 /* speed up time to link by disabling smart power down, ignore
834 * the return value of this function because there is nothing
835 * different we would do if it failed */
836 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
837 &phy_data);
838 phy_data &= ~IGP02E1000_PM_SPD;
839 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
840 phy_data);
841 }
842
0fccd0e9 843 e1000_release_manageability(adapter);
1da177e4
LT		 844}
845
846/**
847 * e1000_probe - Device Initialization Routine
848 * @pdev: PCI device information struct
849 * @ent: entry in e1000_pci_tbl
850 *
851 * Returns 0 on success, negative on failure
852 *
853 * e1000_probe initializes an adapter identified by a pci_dev structure.
854 * The OS initialization, configuring of the adapter private structure,
855 * and a hardware reset occur.
856 **/
857
858static int __devinit
859e1000_probe(struct pci_dev *pdev,
860 const struct pci_device_id *ent)
861{
862 struct net_device *netdev;
863 struct e1000_adapter *adapter;
2d7edb92 864 unsigned long mmio_start, mmio_len;
cd94dd0b 865 unsigned long flash_start, flash_len;
2d7edb92 866
1da177e4 867 static int cards_found = 0;
120cd576 868 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 869 int i, err, pci_using_dac;
120cd576 870 uint16_t eeprom_data = 0;
1da177e4 871 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
0795af57
JP		 872 DECLARE_MAC_BUF(mac);
873
96838a40 874 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 875 return err;
876
cd94dd0b
AK		 877 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
878 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 879 pci_using_dac = 1;
880 } else {
cd94dd0b
AK		 881 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
882 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 883 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 884 goto err_dma;
1da177e4
LT		 885 }
886 pci_using_dac = 0;
887 }
888
96838a40 889 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 890 goto err_pci_reg;
1da177e4
LT		 891
892 pci_set_master(pdev);
893
6dd62ab0 894 err = -ENOMEM;
1da177e4 895 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 896 if (!netdev)
1da177e4 897 goto err_alloc_etherdev;
1da177e4 898
1da177e4
LT		 899 SET_NETDEV_DEV(netdev, &pdev->dev);
900
901 pci_set_drvdata(pdev, netdev);
60490fe0 902 adapter = netdev_priv(netdev);
1da177e4
LT		 903 adapter->netdev = netdev;
904 adapter->pdev = pdev;
905 adapter->hw.back = adapter;
906 adapter->msg_enable = (1 << debug) - 1;
907
908 mmio_start = pci_resource_start(pdev, BAR_0);
909 mmio_len = pci_resource_len(pdev, BAR_0);
910
6dd62ab0 911 err = -EIO;
1da177e4 912 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 913 if (!adapter->hw.hw_addr)
1da177e4 914 goto err_ioremap;
1da177e4 915
96838a40
JB		 916 for (i = BAR_1; i <= BAR_5; i++) {
917 if (pci_resource_len(pdev, i) == 0)
1da177e4 918 continue;
96838a40 919 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 920 adapter->hw.io_base = pci_resource_start(pdev, i);
921 break;
922 }
923 }
924
925 netdev->open = &e1000_open;
926 netdev->stop = &e1000_close;
927 netdev->hard_start_xmit = &e1000_xmit_frame;
928 netdev->get_stats = &e1000_get_stats;
929 netdev->set_multicast_list = &e1000_set_multi;
930 netdev->set_mac_address = &e1000_set_mac;
931 netdev->change_mtu = &e1000_change_mtu;
932 netdev->do_ioctl = &e1000_ioctl;
933 e1000_set_ethtool_ops(netdev);
934 netdev->tx_timeout = &e1000_tx_timeout;
935 netdev->watchdog_timeo = 5 * HZ;
936#ifdef CONFIG_E1000_NAPI
bea3348e 937 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
1da177e4
LT		 938#endif
939 netdev->vlan_rx_register = e1000_vlan_rx_register;
940 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
941 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
942#ifdef CONFIG_NET_POLL_CONTROLLER
943 netdev->poll_controller = e1000_netpoll;
944#endif
0eb5a34c 945 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 946
947 netdev->mem_start = mmio_start;
948 netdev->mem_end = mmio_start + mmio_len;
949 netdev->base_addr = adapter->hw.io_base;
950
951 adapter->bd_number = cards_found;
952
953 /* setup the private structure */
954
96838a40 955 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 956 goto err_sw_init;
957
6dd62ab0 958 err = -EIO;
cd94dd0b
AK		 959 /* Flash BAR mapping must happen after e1000_sw_init
960 * because it depends on mac_type */
961 if ((adapter->hw.mac_type == e1000_ich8lan) &&
962 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
963 flash_start = pci_resource_start(pdev, 1);
964 flash_len = pci_resource_len(pdev, 1);
965 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 966 if (!adapter->hw.flash_address)
cd94dd0b 967 goto err_flashmap;
cd94dd0b
AK		 968 }
969
6dd62ab0 970 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 971 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
972
96838a40 973 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 974 netdev->features = NETIF_F_SG |
975 NETIF_F_HW_CSUM |
976 NETIF_F_HW_VLAN_TX |
977 NETIF_F_HW_VLAN_RX |
978 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 979 if (adapter->hw.mac_type == e1000_ich8lan)
980 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 981 }
982
96838a40 983 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 984 (adapter->hw.mac_type != e1000_82547))
985 netdev->features |= NETIF_F_TSO;
2d7edb92 986
96838a40 987 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 988 netdev->features |= NETIF_F_TSO6;
96838a40 989 if (pci_using_dac)
1da177e4
LT		 990 netdev->features |= NETIF_F_HIGHDMA;
991
76c224bc
AK		 992 netdev->features |= NETIF_F_LLTX;
993
2d7edb92
MC		 994 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
995
cd94dd0b
AK		 996 /* initialize eeprom parameters */
997
998 if (e1000_init_eeprom_params(&adapter->hw)) {
999 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 1000 goto err_eeprom;
cd94dd0b
AK		 1001 }
1002
96838a40 1003 /* before reading the EEPROM, reset the controller to
1da177e4 1004 * put the device in a known good starting state */
96838a40 1005
1da177e4
LT		 1006 e1000_reset_hw(&adapter->hw);
1007
1008 /* make sure the EEPROM is good */
1009
96838a40 1010 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 1011 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 1012 goto err_eeprom;
1013 }
1014
1015 /* copy the MAC address out of the EEPROM */
1016
96838a40 1017 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 1018 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
1019 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 1020 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 1021
96838a40 1022 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 1023 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 1024 goto err_eeprom;
1025 }
1026
1da177e4
LT		 1027 e1000_get_bus_info(&adapter->hw);
1028
1029 init_timer(&adapter->tx_fifo_stall_timer);
1030 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
1031 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
1032
1033 init_timer(&adapter->watchdog_timer);
1034 adapter->watchdog_timer.function = &e1000_watchdog;
1035 adapter->watchdog_timer.data = (unsigned long) adapter;
1036
1da177e4
LT		 1037 init_timer(&adapter->phy_info_timer);
1038 adapter->phy_info_timer.function = &e1000_update_phy_info;
1039 adapter->phy_info_timer.data = (unsigned long) adapter;
1040
65f27f38 1041 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1da177e4 1042
1da177e4
LT		 1043 e1000_check_options(adapter);
1044
1045 /* Initial Wake on LAN setting
1046 * If APM wake is enabled in the EEPROM,
1047 * enable the ACPI Magic Packet filter
1048 */
1049
96838a40 1050 switch (adapter->hw.mac_type) {
1da177e4
LT		 1051 case e1000_82542_rev2_0:
1052 case e1000_82542_rev2_1:
1053 case e1000_82543:
1054 break;
1055 case e1000_82544:
1056 e1000_read_eeprom(&adapter->hw,
1057 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1058 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1059 break;
cd94dd0b
AK		 1060 case e1000_ich8lan:
1061 e1000_read_eeprom(&adapter->hw,
1062 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
1063 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
1064 break;
1da177e4
LT		 1065 case e1000_82546:
1066 case e1000_82546_rev_3:
fd803241 1067 case e1000_82571:
6418ecc6 1068 case e1000_80003es2lan:
96838a40 1069 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 1070 e1000_read_eeprom(&adapter->hw,
1071 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1072 break;
1073 }
1074 /* Fall Through */
1075 default:
1076 e1000_read_eeprom(&adapter->hw,
1077 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1078 break;
1079 }
96838a40 1080 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 1081 adapter->eeprom_wol |= E1000_WUFC_MAG;
1082
1083 /* now that we have the eeprom settings, apply the special cases
1084 * where the eeprom may be wrong or the board simply won't support
1085 * wake on lan on a particular port */
1086 switch (pdev->device) {
1087 case E1000_DEV_ID_82546GB_PCIE:
1088 adapter->eeprom_wol = 0;
1089 break;
1090 case E1000_DEV_ID_82546EB_FIBER:
1091 case E1000_DEV_ID_82546GB_FIBER:
1092 case E1000_DEV_ID_82571EB_FIBER:
1093 /* Wake events only supported on port A for dual fiber
1094 * regardless of eeprom setting */
1095 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
1096 adapter->eeprom_wol = 0;
1097 break;
1098 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 1099 case E1000_DEV_ID_82571EB_QUAD_COPPER:
ce57a02c 1100 case E1000_DEV_ID_82571EB_QUAD_FIBER:
fc2307d0 1101 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
f4ec7f98 1102 case E1000_DEV_ID_82571PT_QUAD_COPPER:
120cd576
JB		 1103 /* if quad port adapter, disable WoL on all but port A */
1104 if (global_quad_port_a != 0)
1105 adapter->eeprom_wol = 0;
1106 else
1107 adapter->quad_port_a = 1;
1108 /* Reset for multiple quad port adapters */
1109 if (++global_quad_port_a == 4)
1110 global_quad_port_a = 0;
1111 break;
1112 }
1113
1114 /* initialize the wol settings based on the eeprom settings */
1115 adapter->wol = adapter->eeprom_wol;
1da177e4 1116
fb3d47d4
JK		 1117 /* print bus type/speed/width info */
1118 {
1119 struct e1000_hw *hw = &adapter->hw;
1120 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
1121 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
1122 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
1123 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1124 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
1125 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
1126 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
1127 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
1128 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
1129 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
1130 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
1131 "32-bit"));
1132 }
1133
0795af57 1134 printk("%s\n", print_mac(mac, netdev->dev_addr));
fb3d47d4 1135
1da177e4
LT		 1136 /* reset the hardware with the new settings */
1137 e1000_reset(adapter);
1138
b55ccb35
JK		 1139 /* If the controller is 82573 and f/w is AMT, do not set
1140 * DRV_LOAD until the interface is up. For all other cases,
1141 * let the f/w know that the h/w is now under the control
1142 * of the driver. */
1143 if (adapter->hw.mac_type != e1000_82573 ||
1144 !e1000_check_mng_mode(&adapter->hw))
1145 e1000_get_hw_control(adapter);
2d7edb92 1146
1314bbf3
AK		 1147 /* tell the stack to leave us alone until e1000_open() is called */
1148 netif_carrier_off(netdev);
1149 netif_stop_queue(netdev);
416b5d10
AK		 1150
1151 strcpy(netdev->name, "eth%d");
1152 if ((err = register_netdev(netdev)))
1153 goto err_register;
1314bbf3 1154
1da177e4
LT		 1155 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1156
1157 cards_found++;
1158 return 0;
1159
1160err_register:
6dd62ab0
VA		 1161 e1000_release_hw_control(adapter);
1162err_eeprom:
1163 if (!e1000_check_phy_reset_block(&adapter->hw))
1164 e1000_phy_hw_reset(&adapter->hw);
1165
cd94dd0b
AK		 1166 if (adapter->hw.flash_address)
1167 iounmap(adapter->hw.flash_address);
1168err_flashmap:
6dd62ab0
VA		 1169#ifdef CONFIG_E1000_NAPI
1170 for (i = 0; i < adapter->num_rx_queues; i++)
1171 dev_put(&adapter->polling_netdev[i]);
1172#endif
1173
1174 kfree(adapter->tx_ring);
1175 kfree(adapter->rx_ring);
1176#ifdef CONFIG_E1000_NAPI
1177 kfree(adapter->polling_netdev);
1178#endif
1da177e4 1179err_sw_init:
1da177e4
LT		 1180 iounmap(adapter->hw.hw_addr);
1181err_ioremap:
1182 free_netdev(netdev);
1183err_alloc_etherdev:
1184 pci_release_regions(pdev);
6dd62ab0
VA		 1185err_pci_reg:
1186err_dma:
1187 pci_disable_device(pdev);
1da177e4
LT		 1188 return err;
1189}
1190
1191/**
1192 * e1000_remove - Device Removal Routine
1193 * @pdev: PCI device information struct
1194 *
1195 * e1000_remove is called by the PCI subsystem to alert the driver
1196 * that it should release a PCI device. The could be caused by a
1197 * Hot-Plug event, or because the driver is going to be removed from
1198 * memory.
1199 **/
1200
1201static void __devexit
1202e1000_remove(struct pci_dev *pdev)
1203{
1204 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1205 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e
MC		 1206#ifdef CONFIG_E1000_NAPI
1207 int i;
1208#endif
1da177e4 1209
28e53bdd 1210 cancel_work_sync(&adapter->reset_task);
be2b28ed 1211
0fccd0e9 1212 e1000_release_manageability(adapter);
1da177e4 1213
b55ccb35
JK		 1214 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1215 * would have already happened in close and is redundant. */
1216 e1000_release_hw_control(adapter);
2d7edb92 1217
581d708e 1218#ifdef CONFIG_E1000_NAPI
f56799ea 1219 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1220 dev_put(&adapter->polling_netdev[i]);
581d708e 1221#endif
1da177e4 1222
bea3348e
SH		 1223 unregister_netdev(netdev);
1224
96838a40 1225 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1226 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1227
24025e4e
MC		 1228 kfree(adapter->tx_ring);
1229 kfree(adapter->rx_ring);
1230#ifdef CONFIG_E1000_NAPI
1231 kfree(adapter->polling_netdev);
1232#endif
1233
1da177e4 1234 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1235 if (adapter->hw.flash_address)
1236 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1237 pci_release_regions(pdev);
1238
1239 free_netdev(netdev);
1240
1241 pci_disable_device(pdev);
1242}
1243
1244/**
1245 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1246 * @adapter: board private structure to initialize
1247 *
1248 * e1000_sw_init initializes the Adapter private data structure.
1249 * Fields are initialized based on PCI device information and
1250 * OS network device settings (MTU size).
1251 **/
1252
1253static int __devinit
1254e1000_sw_init(struct e1000_adapter *adapter)
1255{
1256 struct e1000_hw *hw = &adapter->hw;
1257 struct net_device *netdev = adapter->netdev;
1258 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1259#ifdef CONFIG_E1000_NAPI
1260 int i;
1261#endif
1da177e4
LT		 1262
1263 /* PCI config space info */
1264
1265 hw->vendor_id = pdev->vendor;
1266 hw->device_id = pdev->device;
1267 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1268 hw->subsystem_id = pdev->subsystem_device;
44c10138 1269 hw->revision_id = pdev->revision;
1da177e4
LT		 1270
1271 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1272
eb0f8054 1273 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1274 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1275 hw->max_frame_size = netdev->mtu +
1276 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1277 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1278
1279 /* identify the MAC */
1280
96838a40 1281 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1282 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1283 return -EIO;
1284 }
1285
96838a40 1286 switch (hw->mac_type) {
1da177e4
LT		 1287 default:
1288 break;
1289 case e1000_82541:
1290 case e1000_82547:
1291 case e1000_82541_rev_2:
1292 case e1000_82547_rev_2:
1293 hw->phy_init_script = 1;
1294 break;
1295 }
1296
1297 e1000_set_media_type(hw);
1298
1299 hw->wait_autoneg_complete = FALSE;
1300 hw->tbi_compatibility_en = TRUE;
1301 hw->adaptive_ifs = TRUE;
1302
1303 /* Copper options */
1304
96838a40 1305 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1306 hw->mdix = AUTO_ALL_MODES;
1307 hw->disable_polarity_correction = FALSE;
1308 hw->master_slave = E1000_MASTER_SLAVE;
1309 }
1310
f56799ea
JK		 1311 adapter->num_tx_queues = 1;
1312 adapter->num_rx_queues = 1;
581d708e
MC		 1313
1314 if (e1000_alloc_queues(adapter)) {
1315 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1316 return -ENOMEM;
1317 }
1318
1319#ifdef CONFIG_E1000_NAPI
f56799ea 1320 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 1321 adapter->polling_netdev[i].priv = adapter;
581d708e
MC		 1322 dev_hold(&adapter->polling_netdev[i]);
1323 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1324 }
7bfa4816 1325 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1326#endif
1327
47313054
HX		 1328 /* Explicitly disable IRQ since the NIC can be in any state. */
1329 atomic_set(&adapter->irq_sem, 0);
1330 e1000_irq_disable(adapter);
1331
1da177e4 1332 spin_lock_init(&adapter->stats_lock);
1da177e4 1333
1314bbf3
AK		 1334 set_bit(__E1000_DOWN, &adapter->flags);
1335
1da177e4
LT		 1336 return 0;
1337}
1338
581d708e
MC		 1339/**
1340 * e1000_alloc_queues - Allocate memory for all rings
1341 * @adapter: board private structure to initialize
1342 *
1343 * We allocate one ring per queue at run-time since we don't know the
1344 * number of queues at compile-time. The polling_netdev array is
1345 * intended for Multiqueue, but should work fine with a single queue.
1346 **/
1347
1348static int __devinit
1349e1000_alloc_queues(struct e1000_adapter *adapter)
1350{
1c7e5b12
YB		 1351 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1352 sizeof(struct e1000_tx_ring), GFP_KERNEL);
581d708e
MC		 1353 if (!adapter->tx_ring)
1354 return -ENOMEM;
581d708e 1355
1c7e5b12
YB		 1356 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1357 sizeof(struct e1000_rx_ring), GFP_KERNEL);
581d708e
MC		 1358 if (!adapter->rx_ring) {
1359 kfree(adapter->tx_ring);
1360 return -ENOMEM;
1361 }
581d708e
MC		 1362
1363#ifdef CONFIG_E1000_NAPI
1c7e5b12
YB		 1364 adapter->polling_netdev = kcalloc(adapter->num_rx_queues,
1365 sizeof(struct net_device),
1366 GFP_KERNEL);
581d708e
MC		 1367 if (!adapter->polling_netdev) {
1368 kfree(adapter->tx_ring);
1369 kfree(adapter->rx_ring);
1370 return -ENOMEM;
1371 }
581d708e
MC		 1372#endif
1373
1374 return E1000_SUCCESS;
1375}
1376
1da177e4
LT		 1377/**
1378 * e1000_open - Called when a network interface is made active
1379 * @netdev: network interface device structure
1380 *
1381 * Returns 0 on success, negative value on failure
1382 *
1383 * The open entry point is called when a network interface is made
1384 * active by the system (IFF_UP). At this point all resources needed
1385 * for transmit and receive operations are allocated, the interrupt
1386 * handler is registered with the OS, the watchdog timer is started,
1387 * and the stack is notified that the interface is ready.
1388 **/
1389
1390static int
1391e1000_open(struct net_device *netdev)
1392{
60490fe0 1393 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1394 int err;
1395
2db10a08 1396 /* disallow open during test */
1314bbf3 1397 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1398 return -EBUSY;
1399
1da177e4 1400 /* allocate transmit descriptors */
e0aac5a2
AK		 1401 err = e1000_setup_all_tx_resources(adapter);
1402 if (err)
1da177e4
LT		 1403 goto err_setup_tx;
1404
1405 /* allocate receive descriptors */
e0aac5a2 1406 err = e1000_setup_all_rx_resources(adapter);
b5bf28cd 1407 if (err)
e0aac5a2 1408 goto err_setup_rx;
b5bf28cd 1409
79f05bf0
AK		 1410 e1000_power_up_phy(adapter);
1411
2d7edb92 1412 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1413 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1414 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1415 e1000_update_mng_vlan(adapter);
1416 }
1da177e4 1417
b55ccb35
JK		 1418 /* If AMT is enabled, let the firmware know that the network
1419 * interface is now open */
1420 if (adapter->hw.mac_type == e1000_82573 &&
1421 e1000_check_mng_mode(&adapter->hw))
1422 e1000_get_hw_control(adapter);
1423
e0aac5a2
AK		 1424 /* before we allocate an interrupt, we must be ready to handle it.
1425 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1426 * as soon as we call pci_request_irq, so we have to setup our
1427 * clean_rx handler before we do so. */
1428 e1000_configure(adapter);
1429
1430 err = e1000_request_irq(adapter);
1431 if (err)
1432 goto err_req_irq;
1433
1434 /* From here on the code is the same as e1000_up() */
1435 clear_bit(__E1000_DOWN, &adapter->flags);
1436
47313054 1437#ifdef CONFIG_E1000_NAPI
bea3348e 1438 napi_enable(&adapter->napi);
47313054
HX		 1439#endif
1440
e0aac5a2
AK		 1441 e1000_irq_enable(adapter);
1442
1443 /* fire a link status change interrupt to start the watchdog */
1444 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1445
1da177e4
LT		 1446 return E1000_SUCCESS;
1447
b5bf28cd 1448err_req_irq:
e0aac5a2
AK		 1449 e1000_release_hw_control(adapter);
1450 e1000_power_down_phy(adapter);
581d708e 1451 e1000_free_all_rx_resources(adapter);
1da177e4 1452err_setup_rx:
581d708e 1453 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1454err_setup_tx:
1455 e1000_reset(adapter);
1456
1457 return err;
1458}
1459
1460/**
1461 * e1000_close - Disables a network interface
1462 * @netdev: network interface device structure
1463 *
1464 * Returns 0, this is not allowed to fail
1465 *
1466 * The close entry point is called when an interface is de-activated
1467 * by the OS. The hardware is still under the drivers control, but
1468 * needs to be disabled. A global MAC reset is issued to stop the
1469 * hardware, and all transmit and receive resources are freed.
1470 **/
1471
1472static int
1473e1000_close(struct net_device *netdev)
1474{
60490fe0 1475 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1476
2db10a08 1477 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1478 e1000_down(adapter);
79f05bf0 1479 e1000_power_down_phy(adapter);
2db10a08 1480 e1000_free_irq(adapter);
1da177e4 1481
581d708e
MC		 1482 e1000_free_all_tx_resources(adapter);
1483 e1000_free_all_rx_resources(adapter);
1da177e4 1484
4666560a
BA		 1485 /* kill manageability vlan ID if supported, but not if a vlan with
1486 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1487 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1488 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1489 !(adapter->vlgrp &&
5c15bdec 1490 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) {
2d7edb92
MC		 1491 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1492 }
b55ccb35
JK		 1493
1494 /* If AMT is enabled, let the firmware know that the network
1495 * interface is now closed */
1496 if (adapter->hw.mac_type == e1000_82573 &&
1497 e1000_check_mng_mode(&adapter->hw))
1498 e1000_release_hw_control(adapter);
1499
1da177e4
LT		 1500 return 0;
1501}
1502
1503/**
1504 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1505 * @adapter: address of board private structure
2d7edb92
MC		 1506 * @start: address of beginning of memory
1507 * @len: length of memory
1da177e4 1508 **/
e619d523 1509static boolean_t
1da177e4
LT		 1510e1000_check_64k_bound(struct e1000_adapter *adapter,
1511 void *start, unsigned long len)
1512{
1513 unsigned long begin = (unsigned long) start;
1514 unsigned long end = begin + len;
1515
2648345f
MC		 1516 /* First rev 82545 and 82546 need to not allow any memory
1517 * write location to cross 64k boundary due to errata 23 */
1da177e4 1518 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1519 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1520 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1521 }
1522
1523 return TRUE;
1524}
1525
1526/**
1527 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1528 * @adapter: board private structure
581d708e 1529 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1530 *
1531 * Return 0 on success, negative on failure
1532 **/
1533
3ad2cc67 1534static int
581d708e
MC		 1535e1000_setup_tx_resources(struct e1000_adapter *adapter,
1536 struct e1000_tx_ring *txdr)
1da177e4 1537{
1da177e4
LT		 1538 struct pci_dev *pdev = adapter->pdev;
1539 int size;
1540
1541 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1542 txdr->buffer_info = vmalloc(size);
96838a40 1543 if (!txdr->buffer_info) {
2648345f
MC		 1544 DPRINTK(PROBE, ERR,
1545 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1546 return -ENOMEM;
1547 }
1548 memset(txdr->buffer_info, 0, size);
1549
1550 /* round up to nearest 4K */
1551
1552 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9099cfb9 1553 txdr->size = ALIGN(txdr->size, 4096);
1da177e4
LT		 1554
1555 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1556 if (!txdr->desc) {
1da177e4 1557setup_tx_desc_die:
1da177e4 1558 vfree(txdr->buffer_info);
2648345f
MC		 1559 DPRINTK(PROBE, ERR,
1560 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1561 return -ENOMEM;
1562 }
1563
2648345f 1564 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1565 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1566 void *olddesc = txdr->desc;
1567 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1568 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1569 "at %p\n", txdr->size, txdr->desc);
1570 /* Try again, without freeing the previous */
1da177e4 1571 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1572 /* Failed allocation, critical failure */
96838a40 1573 if (!txdr->desc) {
1da177e4
LT		 1574 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1575 goto setup_tx_desc_die;
1576 }
1577
1578 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1579 /* give up */
2648345f
MC		 1580 pci_free_consistent(pdev, txdr->size, txdr->desc,
1581 txdr->dma);
1da177e4
LT		 1582 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1583 DPRINTK(PROBE, ERR,
2648345f
MC		 1584 "Unable to allocate aligned memory "
1585 "for the transmit descriptor ring\n");
1da177e4
LT		 1586 vfree(txdr->buffer_info);
1587 return -ENOMEM;
1588 } else {
2648345f 1589 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1590 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1591 }
1592 }
1593 memset(txdr->desc, 0, txdr->size);
1594
1595 txdr->next_to_use = 0;
1596 txdr->next_to_clean = 0;
2ae76d98 1597 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1598
1599 return 0;
1600}
1601
581d708e
MC		 1602/**
1603 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1604 * (Descriptors) for all queues
1605 * @adapter: board private structure
1606 *
581d708e
MC		 1607 * Return 0 on success, negative on failure
1608 **/
1609
1610int
1611e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1612{
1613 int i, err = 0;
1614
f56799ea 1615 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1616 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1617 if (err) {
1618 DPRINTK(PROBE, ERR,
1619 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1620 for (i-- ; i >= 0; i--)
1621 e1000_free_tx_resources(adapter,
1622 &adapter->tx_ring[i]);
581d708e
MC		 1623 break;
1624 }
1625 }
1626
1627 return err;
1628}
1629
1da177e4
LT		 1630/**
1631 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1632 * @adapter: board private structure
1633 *
1634 * Configure the Tx unit of the MAC after a reset.
1635 **/
1636
1637static void
1638e1000_configure_tx(struct e1000_adapter *adapter)
1639{
581d708e
MC		 1640 uint64_t tdba;
1641 struct e1000_hw *hw = &adapter->hw;
1642 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1643 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1644
1645 /* Setup the HW Tx Head and Tail descriptor pointers */
1646
f56799ea 1647 switch (adapter->num_tx_queues) {
24025e4e
MC		 1648 case 1:
1649 default:
581d708e
MC		 1650 tdba = adapter->tx_ring[0].dma;
1651 tdlen = adapter->tx_ring[0].count *
1652 sizeof(struct e1000_tx_desc);
581d708e 1653 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1654 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1655 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1656 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1657 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1658 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1659 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1660 break;
1661 }
1da177e4
LT		 1662
1663 /* Set the default values for the Tx Inter Packet Gap timer */
d89b6c67
JB		 1664 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
1665 (hw->media_type == e1000_media_type_fiber ||
1666 hw->media_type == e1000_media_type_internal_serdes))
0fadb059
JK		 1667 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1668 else
1669 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1670
581d708e 1671 switch (hw->mac_type) {
1da177e4
LT		 1672 case e1000_82542_rev2_0:
1673 case e1000_82542_rev2_1:
1674 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1675 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1676 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1677 break;
87041639
JK		 1678 case e1000_80003es2lan:
1679 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1680 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1681 break;
1da177e4 1682 default:
0fadb059
JK		 1683 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1684 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1685 break;
1da177e4 1686 }
0fadb059
JK		 1687 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1688 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1689 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1690
1691 /* Set the Tx Interrupt Delay register */
1692
581d708e
MC		 1693 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1694 if (hw->mac_type >= e1000_82540)
1695 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1696
1697 /* Program the Transmit Control Register */
1698
581d708e 1699 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1700 tctl &= ~E1000_TCTL_CT;
7e6c9861 1701 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1702 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1703
2ae76d98
MC		 1704 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1705 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1706 /* set the speed mode bit, we'll clear it if we're not at
1707 * gigabit link later */
09ae3e88 1708 tarc |= (1 << 21);
2ae76d98 1709 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1710 } else if (hw->mac_type == e1000_80003es2lan) {
1711 tarc = E1000_READ_REG(hw, TARC0);
1712 tarc |= 1;
87041639
JK		 1713 E1000_WRITE_REG(hw, TARC0, tarc);
1714 tarc = E1000_READ_REG(hw, TARC1);
1715 tarc |= 1;
1716 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1717 }
1718
581d708e 1719 e1000_config_collision_dist(hw);
1da177e4
LT		 1720
1721 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1722 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1723
1724 /* only set IDE if we are delaying interrupts using the timers */
1725 if (adapter->tx_int_delay)
1726 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1727
581d708e 1728 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1729 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1730 else
1731 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1732
1733 /* Cache if we're 82544 running in PCI-X because we'll
1734 * need this to apply a workaround later in the send path. */
581d708e
MC		 1735 if (hw->mac_type == e1000_82544 &&
1736 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1737 adapter->pcix_82544 = 1;
7e6c9861
JK		 1738
1739 E1000_WRITE_REG(hw, TCTL, tctl);
1740
1da177e4
LT		 1741}
1742
1743/**
1744 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1745 * @adapter: board private structure
581d708e 1746 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1747 *
1748 * Returns 0 on success, negative on failure
1749 **/
1750
3ad2cc67 1751static int
581d708e
MC		 1752e1000_setup_rx_resources(struct e1000_adapter *adapter,
1753 struct e1000_rx_ring *rxdr)
1da177e4 1754{
1da177e4 1755 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1756 int size, desc_len;
1da177e4
LT		 1757
1758 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1759 rxdr->buffer_info = vmalloc(size);
581d708e 1760 if (!rxdr->buffer_info) {
2648345f
MC		 1761 DPRINTK(PROBE, ERR,
1762 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1763 return -ENOMEM;
1764 }
1765 memset(rxdr->buffer_info, 0, size);
1766
1c7e5b12
YB		 1767 rxdr->ps_page = kcalloc(rxdr->count, sizeof(struct e1000_ps_page),
1768 GFP_KERNEL);
96838a40 1769 if (!rxdr->ps_page) {
2d7edb92
MC		 1770 vfree(rxdr->buffer_info);
1771 DPRINTK(PROBE, ERR,
1772 "Unable to allocate memory for the receive descriptor ring\n");
1773 return -ENOMEM;
1774 }
2d7edb92 1775
1c7e5b12
YB		 1776 rxdr->ps_page_dma = kcalloc(rxdr->count,
1777 sizeof(struct e1000_ps_page_dma),
1778 GFP_KERNEL);
96838a40 1779 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1780 vfree(rxdr->buffer_info);
1781 kfree(rxdr->ps_page);
1782 DPRINTK(PROBE, ERR,
1783 "Unable to allocate memory for the receive descriptor ring\n");
1784 return -ENOMEM;
1785 }
2d7edb92 1786
96838a40 1787 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1788 desc_len = sizeof(struct e1000_rx_desc);
1789 else
1790 desc_len = sizeof(union e1000_rx_desc_packet_split);
1791
1da177e4
LT		 1792 /* Round up to nearest 4K */
1793
2d7edb92 1794 rxdr->size = rxdr->count * desc_len;
9099cfb9 1795 rxdr->size = ALIGN(rxdr->size, 4096);
1da177e4
LT		 1796
1797 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1798
581d708e
MC		 1799 if (!rxdr->desc) {
1800 DPRINTK(PROBE, ERR,
1801 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1802setup_rx_desc_die:
1da177e4 1803 vfree(rxdr->buffer_info);
2d7edb92
MC		 1804 kfree(rxdr->ps_page);
1805 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1806 return -ENOMEM;
1807 }
1808
2648345f 1809 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1810 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1811 void *olddesc = rxdr->desc;
1812 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1813 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1814 "at %p\n", rxdr->size, rxdr->desc);
1815 /* Try again, without freeing the previous */
1da177e4 1816 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1817 /* Failed allocation, critical failure */
581d708e 1818 if (!rxdr->desc) {
1da177e4 1819 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1820 DPRINTK(PROBE, ERR,
1821 "Unable to allocate memory "
1822 "for the receive descriptor ring\n");
1da177e4
LT		 1823 goto setup_rx_desc_die;
1824 }
1825
1826 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1827 /* give up */
2648345f
MC		 1828 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1829 rxdr->dma);
1da177e4 1830 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1831 DPRINTK(PROBE, ERR,
1832 "Unable to allocate aligned memory "
1833 "for the receive descriptor ring\n");
581d708e 1834 goto setup_rx_desc_die;
1da177e4 1835 } else {
2648345f 1836 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1837 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1838 }
1839 }
1840 memset(rxdr->desc, 0, rxdr->size);
1841
1842 rxdr->next_to_clean = 0;
1843 rxdr->next_to_use = 0;
1844
1845 return 0;
1846}
1847
581d708e
MC		 1848/**
1849 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1850 * (Descriptors) for all queues
1851 * @adapter: board private structure
1852 *
581d708e
MC		 1853 * Return 0 on success, negative on failure
1854 **/
1855
1856int
1857e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1858{
1859 int i, err = 0;
1860
f56799ea 1861 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1862 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1863 if (err) {
1864 DPRINTK(PROBE, ERR,
1865 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1866 for (i-- ; i >= 0; i--)
1867 e1000_free_rx_resources(adapter,
1868 &adapter->rx_ring[i]);
581d708e
MC		 1869 break;
1870 }
1871 }
1872
1873 return err;
1874}
1875
1da177e4 1876/**
2648345f 1877 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1878 * @adapter: Board private structure
1879 **/
e4c811c9
MC		 1880#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1881 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1882static void
1883e1000_setup_rctl(struct e1000_adapter *adapter)
1884{
2d7edb92
MC		 1885 uint32_t rctl, rfctl;
1886 uint32_t psrctl = 0;
35ec56bb 1887#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1888 uint32_t pages = 0;
1889#endif
1da177e4
LT		 1890
1891 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1892
1893 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1894
1895 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1896 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1897 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1898
0fadb059 1899 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1900 rctl |= E1000_RCTL_SBP;
1901 else
1902 rctl &= ~E1000_RCTL_SBP;
1903
2d7edb92
MC		 1904 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1905 rctl &= ~E1000_RCTL_LPE;
1906 else
1907 rctl |= E1000_RCTL_LPE;
1908
1da177e4 1909 /* Setup buffer sizes */
9e2feace
AK		 1910 rctl &= ~E1000_RCTL_SZ_4096;
1911 rctl |= E1000_RCTL_BSEX;
1912 switch (adapter->rx_buffer_len) {
1913 case E1000_RXBUFFER_256:
1914 rctl |= E1000_RCTL_SZ_256;
1915 rctl &= ~E1000_RCTL_BSEX;
1916 break;
1917 case E1000_RXBUFFER_512:
1918 rctl |= E1000_RCTL_SZ_512;
1919 rctl &= ~E1000_RCTL_BSEX;
1920 break;
1921 case E1000_RXBUFFER_1024:
1922 rctl |= E1000_RCTL_SZ_1024;
1923 rctl &= ~E1000_RCTL_BSEX;
1924 break;
a1415ee6
JK		 1925 case E1000_RXBUFFER_2048:
1926 default:
1927 rctl |= E1000_RCTL_SZ_2048;
1928 rctl &= ~E1000_RCTL_BSEX;
1929 break;
1930 case E1000_RXBUFFER_4096:
1931 rctl |= E1000_RCTL_SZ_4096;
1932 break;
1933 case E1000_RXBUFFER_8192:
1934 rctl |= E1000_RCTL_SZ_8192;
1935 break;
1936 case E1000_RXBUFFER_16384:
1937 rctl |= E1000_RCTL_SZ_16384;
1938 break;
2d7edb92
MC		 1939 }
1940
35ec56bb 1941#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1942 /* 82571 and greater support packet-split where the protocol
1943 * header is placed in skb->data and the packet data is
1944 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1945 * In the case of a non-split, skb->data is linearly filled,
1946 * followed by the page buffers. Therefore, skb->data is
1947 * sized to hold the largest protocol header.
1948 */
e64d7d02
JB		 1949 /* allocations using alloc_page take too long for regular MTU
1950 * so only enable packet split for jumbo frames */
e4c811c9 1951 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1952 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1953 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1954 adapter->rx_ps_pages = pages;
1955 else
1956 adapter->rx_ps_pages = 0;
2d7edb92 1957#endif
e4c811c9 1958 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1959 /* Configure extra packet-split registers */
1960 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1961 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1962 /* disable packet split support for IPv6 extension headers,
1963 * because some malformed IPv6 headers can hang the RX */
1964 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1965 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1966
2d7edb92
MC		 1967 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1968
7dfee0cb 1969 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1970
2d7edb92
MC		 1971 psrctl |= adapter->rx_ps_bsize0 >>
1972 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1973
1974 switch (adapter->rx_ps_pages) {
1975 case 3:
1976 psrctl |= PAGE_SIZE <<
1977 E1000_PSRCTL_BSIZE3_SHIFT;
1978 case 2:
1979 psrctl |= PAGE_SIZE <<
1980 E1000_PSRCTL_BSIZE2_SHIFT;
1981 case 1:
1982 psrctl |= PAGE_SIZE >>
1983 E1000_PSRCTL_BSIZE1_SHIFT;
1984 break;
1985 }
2d7edb92
MC		 1986
1987 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1988 }
1989
1990 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1991}
1992
1993/**
1994 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1995 * @adapter: board private structure
1996 *
1997 * Configure the Rx unit of the MAC after a reset.
1998 **/
1999
2000static void
2001e1000_configure_rx(struct e1000_adapter *adapter)
2002{
581d708e
MC		 2003 uint64_t rdba;
2004 struct e1000_hw *hw = &adapter->hw;
2005 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 2006
e4c811c9 2007 if (adapter->rx_ps_pages) {
0f15a8fa 2008 /* this is a 32 byte descriptor */
581d708e 2009 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 2010 sizeof(union e1000_rx_desc_packet_split);
2011 adapter->clean_rx = e1000_clean_rx_irq_ps;
2012 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
2013 } else {
581d708e
MC		 2014 rdlen = adapter->rx_ring[0].count *
2015 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 2016 adapter->clean_rx = e1000_clean_rx_irq;
2017 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
2018 }
1da177e4
LT		 2019
2020 /* disable receives while setting up the descriptors */
581d708e
MC		 2021 rctl = E1000_READ_REG(hw, RCTL);
2022 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 2023
2024 /* set the Receive Delay Timer Register */
581d708e 2025 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 2026
581d708e
MC		 2027 if (hw->mac_type >= e1000_82540) {
2028 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
835bb129 2029 if (adapter->itr_setting != 0)
581d708e 2030 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 2031 1000000000 / (adapter->itr * 256));
2032 }
2033
2ae76d98 2034 if (hw->mac_type >= e1000_82571) {
2ae76d98 2035 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 2036 /* Reset delay timers after every interrupt */
6fc7a7ec 2037 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9 2038#ifdef CONFIG_E1000_NAPI
835bb129 2039 /* Auto-Mask interrupts upon ICR access */
1e613fd9 2040 ctrl_ext |= E1000_CTRL_EXT_IAME;
835bb129 2041 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1e613fd9 2042#endif
2ae76d98
MC		 2043 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2044 E1000_WRITE_FLUSH(hw);
2045 }
2046
581d708e
MC		 2047 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2048 * the Base and Length of the Rx Descriptor Ring */
f56799ea 2049 switch (adapter->num_rx_queues) {
24025e4e
MC		 2050 case 1:
2051 default:
581d708e 2052 rdba = adapter->rx_ring[0].dma;
581d708e 2053 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 2054 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
2055 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 2056 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 2057 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 2058 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
2059 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 2060 break;
24025e4e
MC		 2061 }
2062
1da177e4 2063 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 2064 if (hw->mac_type >= e1000_82543) {
2065 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 2066 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 2067 rxcsum |= E1000_RXCSUM_TUOFL;
2068
868d5309 2069 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 2070 * Must be used in conjunction with packet-split. */
96838a40
JB		 2071 if ((hw->mac_type >= e1000_82571) &&
2072 (adapter->rx_ps_pages)) {
2d7edb92
MC		 2073 rxcsum |= E1000_RXCSUM_IPPCSE;
2074 }
2075 } else {
2076 rxcsum &= ~E1000_RXCSUM_TUOFL;
2077 /* don't need to clear IPPCSE as it defaults to 0 */
2078 }
581d708e 2079 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 2080 }
2081
21c4d5e0
AK		 2082 /* enable early receives on 82573, only takes effect if using > 2048
2083 * byte total frame size. for example only for jumbo frames */
2084#define E1000_ERT_2048 0x100
2085 if (hw->mac_type == e1000_82573)
2086 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
2087
1da177e4 2088 /* Enable Receives */
581d708e 2089 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 2090}
2091
2092/**
581d708e 2093 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 2094 * @adapter: board private structure
581d708e 2095 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 2096 *
2097 * Free all transmit software resources
2098 **/
2099
3ad2cc67 2100static void
581d708e
MC		 2101e1000_free_tx_resources(struct e1000_adapter *adapter,
2102 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 2103{
2104 struct pci_dev *pdev = adapter->pdev;
2105
581d708e 2106 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 2107
581d708e
MC		 2108 vfree(tx_ring->buffer_info);
2109 tx_ring->buffer_info = NULL;
1da177e4 2110
581d708e 2111 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 2112
581d708e
MC		 2113 tx_ring->desc = NULL;
2114}
2115
2116/**
2117 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
2118 * @adapter: board private structure
2119 *
2120 * Free all transmit software resources
2121 **/
2122
2123void
2124e1000_free_all_tx_resources(struct e1000_adapter *adapter)
2125{
2126 int i;
2127
f56799ea 2128 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2129 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2130}
2131
e619d523 2132static void
1da177e4
LT		 2133e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
2134 struct e1000_buffer *buffer_info)
2135{
96838a40 2136 if (buffer_info->dma) {
2648345f
MC		 2137 pci_unmap_page(adapter->pdev,
2138 buffer_info->dma,
2139 buffer_info->length,
2140 PCI_DMA_TODEVICE);
a9ebadd6 2141 buffer_info->dma = 0;
1da177e4 2142 }
a9ebadd6 2143 if (buffer_info->skb) {
1da177e4 2144 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2145 buffer_info->skb = NULL;
2146 }
2147 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2148}
2149
2150/**
2151 * e1000_clean_tx_ring - Free Tx Buffers
2152 * @adapter: board private structure
581d708e 2153 * @tx_ring: ring to be cleaned
1da177e4
LT		 2154 **/
2155
2156static void
581d708e
MC		 2157e1000_clean_tx_ring(struct e1000_adapter *adapter,
2158 struct e1000_tx_ring *tx_ring)
1da177e4 2159{
1da177e4
LT		 2160 struct e1000_buffer *buffer_info;
2161 unsigned long size;
2162 unsigned int i;
2163
2164 /* Free all the Tx ring sk_buffs */
2165
96838a40 2166 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2167 buffer_info = &tx_ring->buffer_info[i];
2168 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2169 }
2170
2171 size = sizeof(struct e1000_buffer) * tx_ring->count;
2172 memset(tx_ring->buffer_info, 0, size);
2173
2174 /* Zero out the descriptor ring */
2175
2176 memset(tx_ring->desc, 0, tx_ring->size);
2177
2178 tx_ring->next_to_use = 0;
2179 tx_ring->next_to_clean = 0;
fd803241 2180 tx_ring->last_tx_tso = 0;
1da177e4 2181
581d708e
MC		 2182 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2183 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2184}
2185
2186/**
2187 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2188 * @adapter: board private structure
2189 **/
2190
2191static void
2192e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2193{
2194 int i;
2195
f56799ea 2196 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2197 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2198}
2199
2200/**
2201 * e1000_free_rx_resources - Free Rx Resources
2202 * @adapter: board private structure
581d708e 2203 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2204 *
2205 * Free all receive software resources
2206 **/
2207
3ad2cc67 2208static void
581d708e
MC		 2209e1000_free_rx_resources(struct e1000_adapter *adapter,
2210 struct e1000_rx_ring *rx_ring)
1da177e4 2211{
1da177e4
LT		 2212 struct pci_dev *pdev = adapter->pdev;
2213
581d708e 2214 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2215
2216 vfree(rx_ring->buffer_info);
2217 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2218 kfree(rx_ring->ps_page);
2219 rx_ring->ps_page = NULL;
2220 kfree(rx_ring->ps_page_dma);
2221 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2222
2223 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2224
2225 rx_ring->desc = NULL;
2226}
2227
2228/**
581d708e 2229 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2230 * @adapter: board private structure
581d708e
MC		 2231 *
2232 * Free all receive software resources
2233 **/
2234
2235void
2236e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2237{
2238 int i;
2239
f56799ea 2240 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2241 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2242}
2243
2244/**
2245 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2246 * @adapter: board private structure
2247 * @rx_ring: ring to free buffers from
1da177e4
LT		 2248 **/
2249
2250static void
581d708e
MC		 2251e1000_clean_rx_ring(struct e1000_adapter *adapter,
2252 struct e1000_rx_ring *rx_ring)
1da177e4 2253{
1da177e4 2254 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2255 struct e1000_ps_page *ps_page;
2256 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2257 struct pci_dev *pdev = adapter->pdev;
2258 unsigned long size;
2d7edb92 2259 unsigned int i, j;
1da177e4
LT		 2260
2261 /* Free all the Rx ring sk_buffs */
96838a40 2262 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2263 buffer_info = &rx_ring->buffer_info[i];
96838a40 2264 if (buffer_info->skb) {
1da177e4
LT		 2265 pci_unmap_single(pdev,
2266 buffer_info->dma,
2267 buffer_info->length,
2268 PCI_DMA_FROMDEVICE);
2269
2270 dev_kfree_skb(buffer_info->skb);
2271 buffer_info->skb = NULL;
997f5cbd
JK		 2272 }
2273 ps_page = &rx_ring->ps_page[i];
2274 ps_page_dma = &rx_ring->ps_page_dma[i];
2275 for (j = 0; j < adapter->rx_ps_pages; j++) {
2276 if (!ps_page->ps_page[j]) break;
2277 pci_unmap_page(pdev,
2278 ps_page_dma->ps_page_dma[j],
2279 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2280 ps_page_dma->ps_page_dma[j] = 0;
2281 put_page(ps_page->ps_page[j]);
2282 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2283 }
2284 }
2285
2286 size = sizeof(struct e1000_buffer) * rx_ring->count;
2287 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2288 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2289 memset(rx_ring->ps_page, 0, size);
2290 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2291 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2292
2293 /* Zero out the descriptor ring */
2294
2295 memset(rx_ring->desc, 0, rx_ring->size);
2296
2297 rx_ring->next_to_clean = 0;
2298 rx_ring->next_to_use = 0;
2299
581d708e
MC		 2300 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2301 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2302}
2303
2304/**
2305 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2306 * @adapter: board private structure
2307 **/
2308
2309static void
2310e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2311{
2312 int i;
2313
f56799ea 2314 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2315 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2316}
2317
2318/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2319 * and memory write and invalidate disabled for certain operations
2320 */
2321static void
2322e1000_enter_82542_rst(struct e1000_adapter *adapter)
2323{
2324 struct net_device *netdev = adapter->netdev;
2325 uint32_t rctl;
2326
2327 e1000_pci_clear_mwi(&adapter->hw);
2328
2329 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2330 rctl |= E1000_RCTL_RST;
2331 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2332 E1000_WRITE_FLUSH(&adapter->hw);
2333 mdelay(5);
2334
96838a40 2335 if (netif_running(netdev))
581d708e 2336 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2337}
2338
2339static void
2340e1000_leave_82542_rst(struct e1000_adapter *adapter)
2341{
2342 struct net_device *netdev = adapter->netdev;
2343 uint32_t rctl;
2344
2345 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2346 rctl &= ~E1000_RCTL_RST;
2347 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2348 E1000_WRITE_FLUSH(&adapter->hw);
2349 mdelay(5);
2350
96838a40 2351 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2352 e1000_pci_set_mwi(&adapter->hw);
2353
96838a40 2354 if (netif_running(netdev)) {
72d64a43
JK		 2355 /* No need to loop, because 82542 supports only 1 queue */
2356 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2357 e1000_configure_rx(adapter);
72d64a43 2358 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2359 }
2360}
2361
2362/**
2363 * e1000_set_mac - Change the Ethernet Address of the NIC
2364 * @netdev: network interface device structure
2365 * @p: pointer to an address structure
2366 *
2367 * Returns 0 on success, negative on failure
2368 **/
2369
2370static int
2371e1000_set_mac(struct net_device *netdev, void *p)
2372{
60490fe0 2373 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2374 struct sockaddr *addr = p;
2375
96838a40 2376 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2377 return -EADDRNOTAVAIL;
2378
2379 /* 82542 2.0 needs to be in reset to write receive address registers */
2380
96838a40 2381 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2382 e1000_enter_82542_rst(adapter);
2383
2384 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2385 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2386
2387 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2388
868d5309
MC		 2389 /* With 82571 controllers, LAA may be overwritten (with the default)
2390 * due to controller reset from the other port. */
2391 if (adapter->hw.mac_type == e1000_82571) {
2392 /* activate the work around */
2393 adapter->hw.laa_is_present = 1;
2394
96838a40
JB		 2395 /* Hold a copy of the LAA in RAR[14] This is done so that
2396 * between the time RAR[0] gets clobbered and the time it
2397 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2398 * of the RARs and no incoming packets directed to this port
96838a40 2399 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2400 * RAR[14] */
96838a40 2401 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2402 E1000_RAR_ENTRIES - 1);
2403 }
2404
96838a40 2405 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2406 e1000_leave_82542_rst(adapter);
2407
2408 return 0;
2409}
2410
2411/**
2412 * e1000_set_multi - Multicast and Promiscuous mode set
2413 * @netdev: network interface device structure
2414 *
2415 * The set_multi entry point is called whenever the multicast address
2416 * list or the network interface flags are updated. This routine is
2417 * responsible for configuring the hardware for proper multicast,
2418 * promiscuous mode, and all-multi behavior.
2419 **/
2420
2421static void
2422e1000_set_multi(struct net_device *netdev)
2423{
60490fe0 2424 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2425 struct e1000_hw *hw = &adapter->hw;
2426 struct dev_mc_list *mc_ptr;
2427 uint32_t rctl;
2428 uint32_t hash_value;
868d5309 2429 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2430 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2431 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2432 E1000_NUM_MTA_REGISTERS;
2433
2434 if (adapter->hw.mac_type == e1000_ich8lan)
2435 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2436
868d5309
MC		 2437 /* reserve RAR[14] for LAA over-write work-around */
2438 if (adapter->hw.mac_type == e1000_82571)
2439 rar_entries--;
1da177e4 2440
2648345f
MC		 2441 /* Check for Promiscuous and All Multicast modes */
2442
1da177e4
LT		 2443 rctl = E1000_READ_REG(hw, RCTL);
2444
96838a40 2445 if (netdev->flags & IFF_PROMISC) {
1da177e4 2446 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2447 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2448 rctl |= E1000_RCTL_MPE;
2449 rctl &= ~E1000_RCTL_UPE;
2450 } else {
2451 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2452 }
2453
2454 E1000_WRITE_REG(hw, RCTL, rctl);
2455
2456 /* 82542 2.0 needs to be in reset to write receive address registers */
2457
96838a40 2458 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2459 e1000_enter_82542_rst(adapter);
2460
2461 /* load the first 14 multicast address into the exact filters 1-14
2462 * RAR 0 is used for the station MAC adddress
2463 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2464 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2465 */
2466 mc_ptr = netdev->mc_list;
2467
96838a40 2468 for (i = 1; i < rar_entries; i++) {
868d5309 2469 if (mc_ptr) {
1da177e4
LT		 2470 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2471 mc_ptr = mc_ptr->next;
2472 } else {
2473 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2474 E1000_WRITE_FLUSH(hw);
1da177e4 2475 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2476 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2477 }
2478 }
2479
2480 /* clear the old settings from the multicast hash table */
2481
cd94dd0b 2482 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2483 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2484 E1000_WRITE_FLUSH(hw);
2485 }
1da177e4
LT		 2486
2487 /* load any remaining addresses into the hash table */
2488
96838a40 2489 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2490 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2491 e1000_mta_set(hw, hash_value);
2492 }
2493
96838a40 2494 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2495 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2496}
2497
2498/* Need to wait a few seconds after link up to get diagnostic information from
2499 * the phy */
2500
2501static void
2502e1000_update_phy_info(unsigned long data)
2503{
2504 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2505 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2506}
2507
2508/**
2509 * e1000_82547_tx_fifo_stall - Timer Call-back
2510 * @data: pointer to adapter cast into an unsigned long
2511 **/
2512
2513static void
2514e1000_82547_tx_fifo_stall(unsigned long data)
2515{
2516 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2517 struct net_device *netdev = adapter->netdev;
2518 uint32_t tctl;
2519
96838a40
JB		 2520 if (atomic_read(&adapter->tx_fifo_stall)) {
2521 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2522 E1000_READ_REG(&adapter->hw, TDH)) &&
2523 (E1000_READ_REG(&adapter->hw, TDFT) ==
2524 E1000_READ_REG(&adapter->hw, TDFH)) &&
2525 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2526 E1000_READ_REG(&adapter->hw, TDFHS))) {
2527 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2528 E1000_WRITE_REG(&adapter->hw, TCTL,
2529 tctl & ~E1000_TCTL_EN);
2530 E1000_WRITE_REG(&adapter->hw, TDFT,
2531 adapter->tx_head_addr);
2532 E1000_WRITE_REG(&adapter->hw, TDFH,
2533 adapter->tx_head_addr);
2534 E1000_WRITE_REG(&adapter->hw, TDFTS,
2535 adapter->tx_head_addr);
2536 E1000_WRITE_REG(&adapter->hw, TDFHS,
2537 adapter->tx_head_addr);
2538 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2539 E1000_WRITE_FLUSH(&adapter->hw);
2540
2541 adapter->tx_fifo_head = 0;
2542 atomic_set(&adapter->tx_fifo_stall, 0);
2543 netif_wake_queue(netdev);
2544 } else {
2545 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2546 }
2547 }
2548}
2549
2550/**
2551 * e1000_watchdog - Timer Call-back
2552 * @data: pointer to adapter cast into an unsigned long
2553 **/
2554static void
2555e1000_watchdog(unsigned long data)
2556{
2557 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2558 struct net_device *netdev = adapter->netdev;
545c67c0 2559 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2560 uint32_t link, tctl;
cd94dd0b
AK		 2561 int32_t ret_val;
2562
2563 ret_val = e1000_check_for_link(&adapter->hw);
2564 if ((ret_val == E1000_ERR_PHY) &&
2565 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2566 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2567 /* See e1000_kumeran_lock_loss_workaround() */
2568 DPRINTK(LINK, INFO,
2569 "Gigabit has been disabled, downgrading speed\n");
2570 }
90fb5135 2571
2d7edb92
MC		 2572 if (adapter->hw.mac_type == e1000_82573) {
2573 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2574 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2575 e1000_update_mng_vlan(adapter);
96838a40 2576 }
1da177e4 2577
96838a40 2578 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2579 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2580 link = !adapter->hw.serdes_link_down;
2581 else
2582 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2583
96838a40
JB		 2584 if (link) {
2585 if (!netif_carrier_ok(netdev)) {
9669f53b 2586 uint32_t ctrl;
fe7fe28e 2587 boolean_t txb2b = 1;
1da177e4
LT		 2588 e1000_get_speed_and_duplex(&adapter->hw,
2589 &adapter->link_speed,
2590 &adapter->link_duplex);
2591
9669f53b
AK		 2592 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2593 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, "
2594 "Flow Control: %s\n",
2595 adapter->link_speed,
2596 adapter->link_duplex == FULL_DUPLEX ?
2597 "Full Duplex" : "Half Duplex",
2598 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2599 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2600 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2601 E1000_CTRL_TFCE) ? "TX" : "None" )));
1da177e4 2602
7e6c9861
JK		 2603 /* tweak tx_queue_len according to speed/duplex
2604 * and adjust the timeout factor */
66a2b0a3
JK		 2605 netdev->tx_queue_len = adapter->tx_queue_len;
2606 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2607 switch (adapter->link_speed) {
2608 case SPEED_10:
fe7fe28e 2609 txb2b = 0;
7e6c9861
JK		 2610 netdev->tx_queue_len = 10;
2611 adapter->tx_timeout_factor = 8;
2612 break;
2613 case SPEED_100:
fe7fe28e 2614 txb2b = 0;
7e6c9861
JK		 2615 netdev->tx_queue_len = 100;
2616 /* maybe add some timeout factor ? */
2617 break;
2618 }
2619
fe7fe28e 2620 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2621 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2622 txb2b == 0) {
7e6c9861
JK		 2623 uint32_t tarc0;
2624 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2625 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2626 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2627 }
90fb5135 2628
7e6c9861
JK		 2629 /* disable TSO for pcie and 10/100 speeds, to avoid
2630 * some hardware issues */
2631 if (!adapter->tso_force &&
2632 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2633 switch (adapter->link_speed) {
2634 case SPEED_10:
66a2b0a3 2635 case SPEED_100:
7e6c9861
JK		 2636 DPRINTK(PROBE,INFO,
2637 "10/100 speed: disabling TSO\n");
2638 netdev->features &= ~NETIF_F_TSO;
87ca4e5b 2639 netdev->features &= ~NETIF_F_TSO6;
7e6c9861
JK		 2640 break;
2641 case SPEED_1000:
2642 netdev->features |= NETIF_F_TSO;
87ca4e5b 2643 netdev->features |= NETIF_F_TSO6;
7e6c9861
JK		 2644 break;
2645 default:
2646 /* oops */
66a2b0a3
JK		 2647 break;
2648 }
2649 }
7e6c9861
JK		 2650
2651 /* enable transmits in the hardware, need to do this
2652 * after setting TARC0 */
2653 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2654 tctl |= E1000_TCTL_EN;
2655 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2656
1da177e4
LT		 2657 netif_carrier_on(netdev);
2658 netif_wake_queue(netdev);
56e1393f 2659 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4 2660 adapter->smartspeed = 0;
bb8e3311
JG		 2661 } else {
2662 /* make sure the receive unit is started */
2663 if (adapter->hw.rx_needs_kicking) {
2664 struct e1000_hw *hw = &adapter->hw;
2665 uint32_t rctl = E1000_READ_REG(hw, RCTL);
2666 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2667 }
1da177e4
LT		 2668 }
2669 } else {
96838a40 2670 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2671 adapter->link_speed = 0;
2672 adapter->link_duplex = 0;
2673 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2674 netif_carrier_off(netdev);
2675 netif_stop_queue(netdev);
56e1393f 2676 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
87041639
JK		 2677
2678 /* 80003ES2LAN workaround--
2679 * For packet buffer work-around on link down event;
2680 * disable receives in the ISR and
2681 * reset device here in the watchdog
2682 */
8fc897b0 2683 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2684 /* reset device */
2685 schedule_work(&adapter->reset_task);
1da177e4
LT		 2686 }
2687
2688 e1000_smartspeed(adapter);
2689 }
2690
2691 e1000_update_stats(adapter);
2692
2693 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2694 adapter->tpt_old = adapter->stats.tpt;
2695 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2696 adapter->colc_old = adapter->stats.colc;
2697
2698 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2699 adapter->gorcl_old = adapter->stats.gorcl;
2700 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2701 adapter->gotcl_old = adapter->stats.gotcl;
2702
2703 e1000_update_adaptive(&adapter->hw);
2704
f56799ea 2705 if (!netif_carrier_ok(netdev)) {
581d708e 2706 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2707 /* We've lost link, so the controller stops DMA,
2708 * but we've got queued Tx work that's never going
2709 * to get done, so reset controller to flush Tx.
2710 * (Do the reset outside of interrupt context). */
87041639
JK		 2711 adapter->tx_timeout_count++;
2712 schedule_work(&adapter->reset_task);
1da177e4
LT		 2713 }
2714 }
2715
1da177e4
LT		 2716 /* Cause software interrupt to ensure rx ring is cleaned */
2717 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2718
2648345f 2719 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2720 adapter->detect_tx_hung = TRUE;
2721
96838a40 2722 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2723 * reset from the other port. Set the appropriate LAA in RAR[0] */
2724 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2725 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2726
1da177e4 2727 /* Reset the timer */
56e1393f 2728 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4
LT		 2729}
2730
835bb129
JB		 2731enum latency_range {
2732 lowest_latency = 0,
2733 low_latency = 1,
2734 bulk_latency = 2,
2735 latency_invalid = 255
2736};
2737
2738/**
2739 * e1000_update_itr - update the dynamic ITR value based on statistics
2740 * Stores a new ITR value based on packets and byte
2741 * counts during the last interrupt. The advantage of per interrupt
2742 * computation is faster updates and more accurate ITR for the current
2743 * traffic pattern. Constants in this function were computed
2744 * based on theoretical maximum wire speed and thresholds were set based
2745 * on testing data as well as attempting to minimize response time
2746 * while increasing bulk throughput.
2747 * this functionality is controlled by the InterruptThrottleRate module
2748 * parameter (see e1000_param.c)
2749 * @adapter: pointer to adapter
2750 * @itr_setting: current adapter->itr
2751 * @packets: the number of packets during this measurement interval
2752 * @bytes: the number of bytes during this measurement interval
2753 **/
2754static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2755 uint16_t itr_setting,
2756 int packets,
2757 int bytes)
2758{
2759 unsigned int retval = itr_setting;
2760 struct e1000_hw *hw = &adapter->hw;
2761
2762 if (unlikely(hw->mac_type < e1000_82540))
2763 goto update_itr_done;
2764
2765 if (packets == 0)
2766 goto update_itr_done;
2767
835bb129
JB		 2768 switch (itr_setting) {
2769 case lowest_latency:
2b65326e
JB		 2770 /* jumbo frames get bulk treatment*/
2771 if (bytes/packets > 8000)
2772 retval = bulk_latency;
2773 else if ((packets < 5) && (bytes > 512))
835bb129
JB		 2774 retval = low_latency;
2775 break;
2776 case low_latency: /* 50 usec aka 20000 ints/s */
2777 if (bytes > 10000) {
2b65326e
JB		 2778 /* jumbo frames need bulk latency setting */
2779 if (bytes/packets > 8000)
2780 retval = bulk_latency;
2781 else if ((packets < 10) || ((bytes/packets) > 1200))
835bb129
JB		 2782 retval = bulk_latency;
2783 else if ((packets > 35))
2784 retval = lowest_latency;
2b65326e
JB		 2785 } else if (bytes/packets > 2000)
2786 retval = bulk_latency;
2787 else if (packets <= 2 && bytes < 512)
835bb129
JB		 2788 retval = lowest_latency;
2789 break;
2790 case bulk_latency: /* 250 usec aka 4000 ints/s */
2791 if (bytes > 25000) {
2792 if (packets > 35)
2793 retval = low_latency;
2b65326e
JB		 2794 } else if (bytes < 6000) {
2795 retval = low_latency;
835bb129
JB		 2796 }
2797 break;
2798 }
2799
2800update_itr_done:
2801 return retval;
2802}
2803
2804static void e1000_set_itr(struct e1000_adapter *adapter)
2805{
2806 struct e1000_hw *hw = &adapter->hw;
2807 uint16_t current_itr;
2808 uint32_t new_itr = adapter->itr;
2809
2810 if (unlikely(hw->mac_type < e1000_82540))
2811 return;
2812
2813 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2814 if (unlikely(adapter->link_speed != SPEED_1000)) {
2815 current_itr = 0;
2816 new_itr = 4000;
2817 goto set_itr_now;
2818 }
2819
2820 adapter->tx_itr = e1000_update_itr(adapter,
2821 adapter->tx_itr,
2822 adapter->total_tx_packets,
2823 adapter->total_tx_bytes);
2b65326e
JB		 2824 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2825 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2826 adapter->tx_itr = low_latency;
2827
835bb129
JB		 2828 adapter->rx_itr = e1000_update_itr(adapter,
2829 adapter->rx_itr,
2830 adapter->total_rx_packets,
2831 adapter->total_rx_bytes);
2b65326e
JB		 2832 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2833 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2834 adapter->rx_itr = low_latency;
835bb129
JB		 2835
2836 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2837
835bb129
JB		 2838 switch (current_itr) {
2839 /* counts and packets in update_itr are dependent on these numbers */
2840 case lowest_latency:
2841 new_itr = 70000;
2842 break;
2843 case low_latency:
2844 new_itr = 20000; /* aka hwitr = ~200 */
2845 break;
2846 case bulk_latency:
2847 new_itr = 4000;
2848 break;
2849 default:
2850 break;
2851 }
2852
2853set_itr_now:
2854 if (new_itr != adapter->itr) {
2855 /* this attempts to bias the interrupt rate towards Bulk
2856 * by adding intermediate steps when interrupt rate is
2857 * increasing */
2858 new_itr = new_itr > adapter->itr ?
2859 min(adapter->itr + (new_itr >> 2), new_itr) :
2860 new_itr;
2861 adapter->itr = new_itr;
2862 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2863 }
2864
2865 return;
2866}
2867
1da177e4
LT		 2868#define E1000_TX_FLAGS_CSUM 0x00000001
2869#define E1000_TX_FLAGS_VLAN 0x00000002
2870#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2871#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2872#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2873#define E1000_TX_FLAGS_VLAN_SHIFT 16
2874
e619d523 2875static int
581d708e
MC		 2876e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2877 struct sk_buff *skb)
1da177e4 2878{
1da177e4 2879 struct e1000_context_desc *context_desc;
545c67c0 2880 struct e1000_buffer *buffer_info;
1da177e4
LT		 2881 unsigned int i;
2882 uint32_t cmd_length = 0;
2d7edb92 2883 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2884 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2885 int err;
2886
89114afd 2887 if (skb_is_gso(skb)) {
1da177e4
LT		 2888 if (skb_header_cloned(skb)) {
2889 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2890 if (err)
2891 return err;
2892 }
2893
ab6a5bb6 2894 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
7967168c 2895 mss = skb_shinfo(skb)->gso_size;
60828236 2896 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2897 struct iphdr *iph = ip_hdr(skb);
2898 iph->tot_len = 0;
2899 iph->check = 0;
aa8223c7
ACM		 2900 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2901 iph->daddr, 0,
2902 IPPROTO_TCP,
2903 0);
2d7edb92 2904 cmd_length = E1000_TXD_CMD_IP;
ea2ae17d 2905 ipcse = skb_transport_offset(skb) - 1;
e15fdd03 2906 } else if (skb->protocol == htons(ETH_P_IPV6)) {
0660e03f 2907 ipv6_hdr(skb)->payload_len = 0;
aa8223c7 2908 tcp_hdr(skb)->check =
0660e03f
ACM		 2909 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2910 &ipv6_hdr(skb)->daddr,
2911 0, IPPROTO_TCP, 0);
2d7edb92 2912 ipcse = 0;
2d7edb92 2913 }
bbe735e4 2914 ipcss = skb_network_offset(skb);
eddc9ec5 2915 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
ea2ae17d 2916 tucss = skb_transport_offset(skb);
aa8223c7 2917 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
1da177e4
LT		 2918 tucse = 0;
2919
2920 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2921 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2922
581d708e
MC		 2923 i = tx_ring->next_to_use;
2924 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2925 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2926
2927 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2928 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2929 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2930 context_desc->upper_setup.tcp_fields.tucss = tucss;
2931 context_desc->upper_setup.tcp_fields.tucso = tucso;
2932 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2933 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2934 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2935 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2936
545c67c0 2937 buffer_info->time_stamp = jiffies;
a9ebadd6 2938 buffer_info->next_to_watch = i;
545c67c0 2939
581d708e
MC		 2940 if (++i == tx_ring->count) i = 0;
2941 tx_ring->next_to_use = i;
1da177e4 2942
8241e35e 2943 return TRUE;
1da177e4 2944 }
8241e35e 2945 return FALSE;
1da177e4
LT		 2946}
2947
e619d523 2948static boolean_t
581d708e
MC		 2949e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2950 struct sk_buff *skb)
1da177e4
LT		 2951{
2952 struct e1000_context_desc *context_desc;
545c67c0 2953 struct e1000_buffer *buffer_info;
1da177e4
LT		 2954 unsigned int i;
2955 uint8_t css;
2956
84fa7933 2957 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2958 css = skb_transport_offset(skb);
1da177e4 2959
581d708e 2960 i = tx_ring->next_to_use;
545c67c0 2961 buffer_info = &tx_ring->buffer_info[i];
581d708e 2962 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4 2963
f6c57baf 2964 context_desc->lower_setup.ip_config = 0;
1da177e4 2965 context_desc->upper_setup.tcp_fields.tucss = css;
628592cc
HX		 2966 context_desc->upper_setup.tcp_fields.tucso =
2967 css + skb->csum_offset;
1da177e4
LT		 2968 context_desc->upper_setup.tcp_fields.tucse = 0;
2969 context_desc->tcp_seg_setup.data = 0;
2970 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2971
545c67c0 2972 buffer_info->time_stamp = jiffies;
a9ebadd6 2973 buffer_info->next_to_watch = i;
545c67c0 2974
581d708e
MC		 2975 if (unlikely(++i == tx_ring->count)) i = 0;
2976 tx_ring->next_to_use = i;
1da177e4
LT		 2977
2978 return TRUE;
2979 }
2980
2981 return FALSE;
2982}
2983
2984#define E1000_MAX_TXD_PWR 12
2985#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2986
e619d523 2987static int
581d708e
MC		 2988e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2989 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2990 unsigned int nr_frags, unsigned int mss)
1da177e4 2991{
1da177e4
LT		 2992 struct e1000_buffer *buffer_info;
2993 unsigned int len = skb->len;
2994 unsigned int offset = 0, size, count = 0, i;
2995 unsigned int f;
2996 len -= skb->data_len;
2997
2998 i = tx_ring->next_to_use;
2999
96838a40 3000 while (len) {
1da177e4
LT		 3001 buffer_info = &tx_ring->buffer_info[i];
3002 size = min(len, max_per_txd);
fd803241
JK		 3003 /* Workaround for Controller erratum --
3004 * descriptor for non-tso packet in a linear SKB that follows a
3005 * tso gets written back prematurely before the data is fully
0f15a8fa 3006 * DMA'd to the controller */
fd803241 3007 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 3008 !skb_is_gso(skb)) {
fd803241
JK		 3009 tx_ring->last_tx_tso = 0;
3010 size -= 4;
3011 }
3012
1da177e4
LT		 3013 /* Workaround for premature desc write-backs
3014 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3015 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4 3016 size -= 4;
97338bde
MC		 3017 /* work-around for errata 10 and it applies
3018 * to all controllers in PCI-X mode
3019 * The fix is to make sure that the first descriptor of a
3020 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
3021 */
96838a40 3022 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3023 (size > 2015) && count == 0))
3024 size = 2015;
96838a40 3025
1da177e4
LT		 3026 /* Workaround for potential 82544 hang in PCI-X. Avoid
3027 * terminating buffers within evenly-aligned dwords. */
96838a40 3028 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3029 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
3030 size > 4))
3031 size -= 4;
3032
3033 buffer_info->length = size;
3034 buffer_info->dma =
3035 pci_map_single(adapter->pdev,
3036 skb->data + offset,
3037 size,
3038 PCI_DMA_TODEVICE);
3039 buffer_info->time_stamp = jiffies;
a9ebadd6 3040 buffer_info->next_to_watch = i;
1da177e4
LT		 3041
3042 len -= size;
3043 offset += size;
3044 count++;
96838a40 3045 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3046 }
3047
96838a40 3048 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 3049 struct skb_frag_struct *frag;
3050
3051 frag = &skb_shinfo(skb)->frags[f];
3052 len = frag->size;
3053 offset = frag->page_offset;
3054
96838a40 3055 while (len) {
1da177e4
LT		 3056 buffer_info = &tx_ring->buffer_info[i];
3057 size = min(len, max_per_txd);
1da177e4
LT		 3058 /* Workaround for premature desc write-backs
3059 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3060 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4 3061 size -= 4;
1da177e4
LT		 3062 /* Workaround for potential 82544 hang in PCI-X.
3063 * Avoid terminating buffers within evenly-aligned
3064 * dwords. */
96838a40 3065 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3066 !((unsigned long)(frag->page+offset+size-1) & 4) &&
3067 size > 4))
3068 size -= 4;
3069
3070 buffer_info->length = size;
3071 buffer_info->dma =
3072 pci_map_page(adapter->pdev,
3073 frag->page,
3074 offset,
3075 size,
3076 PCI_DMA_TODEVICE);
3077 buffer_info->time_stamp = jiffies;
a9ebadd6 3078 buffer_info->next_to_watch = i;
1da177e4
LT		 3079
3080 len -= size;
3081 offset += size;
3082 count++;
96838a40 3083 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3084 }
3085 }
3086
3087 i = (i == 0) ? tx_ring->count - 1 : i - 1;
3088 tx_ring->buffer_info[i].skb = skb;
3089 tx_ring->buffer_info[first].next_to_watch = i;
3090
3091 return count;
3092}
3093
e619d523 3094static void
581d708e
MC		 3095e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3096 int tx_flags, int count)
1da177e4 3097{
1da177e4
LT		 3098 struct e1000_tx_desc *tx_desc = NULL;
3099 struct e1000_buffer *buffer_info;
3100 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
3101 unsigned int i;
3102
96838a40 3103 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 3104 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
3105 E1000_TXD_CMD_TSE;
2d7edb92
MC		 3106 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3107
96838a40 3108 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 3109 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 3110 }
3111
96838a40 3112 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 3113 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
3114 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3115 }
3116
96838a40 3117 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 3118 txd_lower |= E1000_TXD_CMD_VLE;
3119 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
3120 }
3121
3122 i = tx_ring->next_to_use;
3123
96838a40 3124 while (count--) {
1da177e4
LT		 3125 buffer_info = &tx_ring->buffer_info[i];
3126 tx_desc = E1000_TX_DESC(*tx_ring, i);
3127 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3128 tx_desc->lower.data =
3129 cpu_to_le32(txd_lower | buffer_info->length);
3130 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 3131 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3132 }
3133
3134 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3135
3136 /* Force memory writes to complete before letting h/w
3137 * know there are new descriptors to fetch. (Only
3138 * applicable for weak-ordered memory model archs,
3139 * such as IA-64). */
3140 wmb();
3141
3142 tx_ring->next_to_use = i;
581d708e 3143 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 3144 /* we need this if more than one processor can write to our tail
3145 * at a time, it syncronizes IO on IA64/Altix systems */
3146 mmiowb();
1da177e4
LT		 3147}
3148
3149/**
3150 * 82547 workaround to avoid controller hang in half-duplex environment.
3151 * The workaround is to avoid queuing a large packet that would span
3152 * the internal Tx FIFO ring boundary by notifying the stack to resend
3153 * the packet at a later time. This gives the Tx FIFO an opportunity to
3154 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3155 * to the beginning of the Tx FIFO.
3156 **/
3157
3158#define E1000_FIFO_HDR 0x10
3159#define E1000_82547_PAD_LEN 0x3E0
3160
e619d523 3161static int
1da177e4
LT		 3162e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3163{
3164 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3165 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
3166
9099cfb9 3167 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
1da177e4 3168
96838a40 3169 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 3170 goto no_fifo_stall_required;
3171
96838a40 3172 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 3173 return 1;
3174
96838a40 3175 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 3176 atomic_set(&adapter->tx_fifo_stall, 1);
3177 return 1;
3178 }
3179
3180no_fifo_stall_required:
3181 adapter->tx_fifo_head += skb_fifo_len;
96838a40 3182 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 3183 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3184 return 0;
3185}
3186
2d7edb92 3187#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 3188static int
2d7edb92
MC		 3189e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3190{
3191 struct e1000_hw *hw = &adapter->hw;
3192 uint16_t length, offset;
96838a40
JB		 3193 if (vlan_tx_tag_present(skb)) {
3194 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 3195 ( adapter->hw.mng_cookie.status &
3196 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
3197 return 0;
3198 }
20a44028 3199 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 3200 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 3201 if ((htons(ETH_P_IP) == eth->h_proto)) {
3202 const struct iphdr *ip =
2d7edb92 3203 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 3204 if (IPPROTO_UDP == ip->protocol) {
3205 struct udphdr *udp =
3206 (struct udphdr *)((uint8_t *)ip +
2d7edb92 3207 (ip->ihl << 2));
96838a40 3208 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 3209 offset = (uint8_t *)udp + 8 - skb->data;
3210 length = skb->len - offset;
3211
3212 return e1000_mng_write_dhcp_info(hw,
96838a40 3213 (uint8_t *)udp + 8,
2d7edb92
MC		 3214 length);
3215 }
3216 }
3217 }
3218 }
3219 return 0;
3220}
3221
65c7973f
JB		 3222static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3223{
3224 struct e1000_adapter *adapter = netdev_priv(netdev);
3225 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3226
3227 netif_stop_queue(netdev);
3228 /* Herbert's original patch had:
3229 * smp_mb__after_netif_stop_queue();
3230 * but since that doesn't exist yet, just open code it. */
3231 smp_mb();
3232
3233 /* We need to check again in a case another CPU has just
3234 * made room available. */
3235 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3236 return -EBUSY;
3237
3238 /* A reprieve! */
3239 netif_start_queue(netdev);
fcfb1224 3240 ++adapter->restart_queue;
65c7973f
JB		 3241 return 0;
3242}
3243
3244static int e1000_maybe_stop_tx(struct net_device *netdev,
3245 struct e1000_tx_ring *tx_ring, int size)
3246{
3247 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3248 return 0;
3249 return __e1000_maybe_stop_tx(netdev, size);
3250}
3251
1da177e4
LT		 3252#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3253static int
3254e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3255{
60490fe0 3256 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 3257 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 3258 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3259 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3260 unsigned int tx_flags = 0;
6d1e3aa7 3261 unsigned int len = skb->len - skb->data_len;
1da177e4 3262 unsigned long flags;
6d1e3aa7
KK		 3263 unsigned int nr_frags;
3264 unsigned int mss;
1da177e4 3265 int count = 0;
76c224bc 3266 int tso;
1da177e4 3267 unsigned int f;
1da177e4 3268
65c7973f
JB		 3269 /* This goes back to the question of how to logically map a tx queue
3270 * to a flow. Right now, performance is impacted slightly negatively
3271 * if using multiple tx queues. If the stack breaks away from a
3272 * single qdisc implementation, we can look at this again. */
581d708e 3273 tx_ring = adapter->tx_ring;
24025e4e 3274
581d708e 3275 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3276 dev_kfree_skb_any(skb);
3277 return NETDEV_TX_OK;
3278 }
3279
032fe6e9
JB		 3280 /* 82571 and newer doesn't need the workaround that limited descriptor
3281 * length to 4kB */
3282 if (adapter->hw.mac_type >= e1000_82571)
3283 max_per_txd = 8192;
3284
7967168c 3285 mss = skb_shinfo(skb)->gso_size;
76c224bc 3286 /* The controller does a simple calculation to
1da177e4
LT		 3287 * make sure there is enough room in the FIFO before
3288 * initiating the DMA for each buffer. The calc is:
3289 * 4 = ceil(buffer len/mss). To make sure we don't
3290 * overrun the FIFO, adjust the max buffer len if mss
3291 * drops. */
96838a40 3292 if (mss) {
9a3056da 3293 uint8_t hdr_len;
1da177e4
LT		 3294 max_per_txd = min(mss << 2, max_per_txd);
3295 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3296
90fb5135
AK		 3297 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3298 * points to just header, pull a few bytes of payload from
3299 * frags into skb->data */
ab6a5bb6 3300 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
6d1e3aa7 3301 if (skb->data_len && hdr_len == len) {
9f687888
JK		 3302 switch (adapter->hw.mac_type) {
3303 unsigned int pull_size;
683a2aa3
HX		 3304 case e1000_82544:
3305 /* Make sure we have room to chop off 4 bytes,
3306 * and that the end alignment will work out to
3307 * this hardware's requirements
3308 * NOTE: this is a TSO only workaround
3309 * if end byte alignment not correct move us
3310 * into the next dword */
27a884dc 3311 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
683a2aa3
HX		 3312 break;
3313 /* fall through */
9f687888
JK		 3314 case e1000_82571:
3315 case e1000_82572:
3316 case e1000_82573:
cd94dd0b 3317 case e1000_ich8lan:
9f687888
JK		 3318 pull_size = min((unsigned int)4, skb->data_len);
3319 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3320 DPRINTK(DRV, ERR,
9f687888
JK		 3321 "__pskb_pull_tail failed.\n");
3322 dev_kfree_skb_any(skb);
749dfc70 3323 return NETDEV_TX_OK;
9f687888
JK		 3324 }
3325 len = skb->len - skb->data_len;
3326 break;
3327 default:
3328 /* do nothing */
3329 break;
d74bbd3b 3330 }
9a3056da 3331 }
1da177e4
LT		 3332 }
3333
9a3056da 3334 /* reserve a descriptor for the offload context */
84fa7933 3335 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3336 count++;
2648345f 3337 count++;
fd803241 3338
fd803241 3339 /* Controller Erratum workaround */
89114afd 3340 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241 3341 count++;
fd803241 3342
1da177e4
LT		 3343 count += TXD_USE_COUNT(len, max_txd_pwr);
3344
96838a40 3345 if (adapter->pcix_82544)
1da177e4
LT		 3346 count++;
3347
96838a40 3348 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3349 * in PCI-X mode, so add one more descriptor to the count
3350 */
96838a40 3351 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3352 (len > 2015)))
3353 count++;
3354
1da177e4 3355 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3356 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3357 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3358 max_txd_pwr);
96838a40 3359 if (adapter->pcix_82544)
1da177e4
LT		 3360 count += nr_frags;
3361
0f15a8fa
JK		 3362
3363 if (adapter->hw.tx_pkt_filtering &&
3364 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3365 e1000_transfer_dhcp_info(adapter, skb);
3366
f50393fe 3367 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags))
581d708e 3368 /* Collision - tell upper layer to requeue */
581d708e 3369 return NETDEV_TX_LOCKED;
1da177e4
LT		 3370
3371 /* need: count + 2 desc gap to keep tail from touching
3372 * head, otherwise try next time */
65c7973f 3373 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3374 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3375 return NETDEV_TX_BUSY;
3376 }
3377
96838a40
JB		 3378 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3379 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3380 netif_stop_queue(netdev);
1314bbf3 3381 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3382 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3383 return NETDEV_TX_BUSY;
3384 }
3385 }
3386
96838a40 3387 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3388 tx_flags |= E1000_TX_FLAGS_VLAN;
3389 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3390 }
3391
581d708e 3392 first = tx_ring->next_to_use;
96838a40 3393
581d708e 3394 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3395 if (tso < 0) {
3396 dev_kfree_skb_any(skb);
581d708e 3397 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3398 return NETDEV_TX_OK;
3399 }
3400
fd803241
JK		 3401 if (likely(tso)) {
3402 tx_ring->last_tx_tso = 1;
1da177e4 3403 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3404 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3405 tx_flags |= E1000_TX_FLAGS_CSUM;
3406
2d7edb92 3407 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3408 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3409 * no longer assume, we must. */
60828236 3410 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3411 tx_flags |= E1000_TX_FLAGS_IPV4;
3412
581d708e
MC		 3413 e1000_tx_queue(adapter, tx_ring, tx_flags,
3414 e1000_tx_map(adapter, tx_ring, skb, first,
3415 max_per_txd, nr_frags, mss));
1da177e4
LT		 3416
3417 netdev->trans_start = jiffies;
3418
3419 /* Make sure there is space in the ring for the next send. */
65c7973f 3420 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3421
581d708e 3422 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3423 return NETDEV_TX_OK;
3424}
3425
3426/**
3427 * e1000_tx_timeout - Respond to a Tx Hang
3428 * @netdev: network interface device structure
3429 **/
3430
3431static void
3432e1000_tx_timeout(struct net_device *netdev)
3433{
60490fe0 3434 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3435
3436 /* Do the reset outside of interrupt context */
87041639
JK		 3437 adapter->tx_timeout_count++;
3438 schedule_work(&adapter->reset_task);
1da177e4
LT		 3439}
3440
3441static void
65f27f38 3442e1000_reset_task(struct work_struct *work)
1da177e4 3443{
65f27f38
DH		 3444 struct e1000_adapter *adapter =
3445 container_of(work, struct e1000_adapter, reset_task);
1da177e4 3446
2db10a08 3447 e1000_reinit_locked(adapter);
1da177e4
LT		 3448}
3449
3450/**
3451 * e1000_get_stats - Get System Network Statistics
3452 * @netdev: network interface device structure
3453 *
3454 * Returns the address of the device statistics structure.
3455 * The statistics are actually updated from the timer callback.
3456 **/
3457
3458static struct net_device_stats *
3459e1000_get_stats(struct net_device *netdev)
3460{
60490fe0 3461 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3462
6b7660cd 3463 /* only return the current stats */
1da177e4
LT		 3464 return &adapter->net_stats;
3465}
3466
3467/**
3468 * e1000_change_mtu - Change the Maximum Transfer Unit
3469 * @netdev: network interface device structure
3470 * @new_mtu: new value for maximum frame size
3471 *
3472 * Returns 0 on success, negative on failure
3473 **/
3474
3475static int
3476e1000_change_mtu(struct net_device *netdev, int new_mtu)
3477{
60490fe0 3478 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3479 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3480 uint16_t eeprom_data = 0;
1da177e4 3481
96838a40
JB		 3482 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3483 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3484 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3485 return -EINVAL;
2d7edb92 3486 }
1da177e4 3487
997f5cbd
JK		 3488 /* Adapter-specific max frame size limits. */
3489 switch (adapter->hw.mac_type) {
9e2feace 3490 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3491 case e1000_ich8lan:
997f5cbd
JK		 3492 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3493 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3494 return -EINVAL;
2d7edb92 3495 }
997f5cbd 3496 break;
85b22eb6 3497 case e1000_82573:
249d71d6
BA		 3498 /* Jumbo Frames not supported if:
3499 * - this is not an 82573L device
3500 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3501 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3502 &eeprom_data);
249d71d6
BA		 3503 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3504 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3505 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3506 DPRINTK(PROBE, ERR,
3507 "Jumbo Frames not supported.\n");
3508 return -EINVAL;
3509 }
3510 break;
3511 }
249d71d6
BA		 3512 /* ERT will be enabled later to enable wire speed receives */
3513
85b22eb6 3514 /* fall through to get support */
997f5cbd
JK		 3515 case e1000_82571:
3516 case e1000_82572:
87041639 3517 case e1000_80003es2lan:
997f5cbd
JK		 3518#define MAX_STD_JUMBO_FRAME_SIZE 9234
3519 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3520 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3521 return -EINVAL;
3522 }
3523 break;
3524 default:
3525 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3526 break;
1da177e4
LT		 3527 }
3528
87f5032e 3529 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3530 * means we reserve 2 more, this pushes us to allocate from the next
3531 * larger slab size
3532 * i.e. RXBUFFER_2048 --> size-4096 slab */
3533
3534 if (max_frame <= E1000_RXBUFFER_256)
3535 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3536 else if (max_frame <= E1000_RXBUFFER_512)
3537 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3538 else if (max_frame <= E1000_RXBUFFER_1024)
3539 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3540 else if (max_frame <= E1000_RXBUFFER_2048)
3541 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3542 else if (max_frame <= E1000_RXBUFFER_4096)
3543 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3544 else if (max_frame <= E1000_RXBUFFER_8192)
3545 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3546 else if (max_frame <= E1000_RXBUFFER_16384)
3547 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3548
3549 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3550 if (!adapter->hw.tbi_compatibility_on &&
3551 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3552 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3553 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3554
2d7edb92 3555 netdev->mtu = new_mtu;
83cd8279 3556 adapter->hw.max_frame_size = max_frame;
2d7edb92 3557
2db10a08
AK		 3558 if (netif_running(netdev))
3559 e1000_reinit_locked(adapter);
1da177e4 3560
1da177e4
LT		 3561 return 0;
3562}
3563
3564/**
3565 * e1000_update_stats - Update the board statistics counters
3566 * @adapter: board private structure
3567 **/
3568
3569void
3570e1000_update_stats(struct e1000_adapter *adapter)
3571{
3572 struct e1000_hw *hw = &adapter->hw;
282f33c9 3573 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3574 unsigned long flags;
3575 uint16_t phy_tmp;
3576
3577#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3578
282f33c9
LV		 3579 /*
3580 * Prevent stats update while adapter is being reset, or if the pci
3581 * connection is down.
3582 */
9026729b 3583 if (adapter->link_speed == 0)
282f33c9 3584 return;
81b1955e 3585 if (pci_channel_offline(pdev))
9026729b
AK		 3586 return;
3587
1da177e4
LT		 3588 spin_lock_irqsave(&adapter->stats_lock, flags);
3589
828d055f 3590 /* these counters are modified from e1000_tbi_adjust_stats,
1da177e4
LT		 3591 * called from the interrupt context, so they must only
3592 * be written while holding adapter->stats_lock
3593 */
3594
3595 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3596 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3597 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3598 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3599 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3600 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3601 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3602
3603 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3604 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3605 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3606 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3607 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3608 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3609 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3610 }
1da177e4
LT		 3611
3612 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3613 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3614 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3615 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3616 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3617 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3618 adapter->stats.dc += E1000_READ_REG(hw, DC);
3619 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3620 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3621 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3622 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3623 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3624 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3625 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3626 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3627 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3628 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3629 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3630 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3631 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3632 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3633 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3634 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3635 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3636 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3637 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3638
3639 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3640 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3641 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3642 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3643 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3644 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3645 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3646 }
3647
1da177e4
LT		 3648 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3649 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3650
3651 /* used for adaptive IFS */
3652
3653 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3654 adapter->stats.tpt += hw->tx_packet_delta;
3655 hw->collision_delta = E1000_READ_REG(hw, COLC);
3656 adapter->stats.colc += hw->collision_delta;
3657
96838a40 3658 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3659 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3660 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3661 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3662 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3663 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3664 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3665 }
96838a40 3666 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3667 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3668 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3669
3670 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3671 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3672 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3673 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3674 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3675 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3676 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3677 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3678 }
2d7edb92 3679 }
1da177e4
LT		 3680
3681 /* Fill out the OS statistics structure */
1da177e4
LT		 3682 adapter->net_stats.rx_packets = adapter->stats.gprc;
3683 adapter->net_stats.tx_packets = adapter->stats.gptc;
3684 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3685 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3686 adapter->net_stats.multicast = adapter->stats.mprc;
3687 adapter->net_stats.collisions = adapter->stats.colc;
3688
3689 /* Rx Errors */
3690
87041639
JK		 3691 /* RLEC on some newer hardware can be incorrect so build
3692 * our own version based on RUC and ROC */
1da177e4
LT		 3693 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3694 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3695 adapter->stats.ruc + adapter->stats.roc +
3696 adapter->stats.cexterr;
49559854
MW		 3697 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3698 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3699 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3700 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3701 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3702
3703 /* Tx Errors */
49559854
MW		 3704 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3705 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3706 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3707 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3708 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
167fb284
JG		 3709 if (adapter->hw.bad_tx_carr_stats_fd &&
3710 adapter->link_duplex == FULL_DUPLEX) {
3711 adapter->net_stats.tx_carrier_errors = 0;
3712 adapter->stats.tncrs = 0;
3713 }
1da177e4
LT		 3714
3715 /* Tx Dropped needs to be maintained elsewhere */
3716
3717 /* Phy Stats */
96838a40
JB		 3718 if (hw->media_type == e1000_media_type_copper) {
3719 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3720 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3721 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3722 adapter->phy_stats.idle_errors += phy_tmp;
3723 }
3724
96838a40 3725 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3726 (hw->phy_type == e1000_phy_m88) &&
3727 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3728 adapter->phy_stats.receive_errors += phy_tmp;
3729 }
3730
15e376b4
JG		 3731 /* Management Stats */
3732 if (adapter->hw.has_smbus) {
3733 adapter->stats.mgptc += E1000_READ_REG(hw, MGTPTC);
3734 adapter->stats.mgprc += E1000_READ_REG(hw, MGTPRC);
3735 adapter->stats.mgpdc += E1000_READ_REG(hw, MGTPDC);
3736 }
3737
1da177e4
LT		 3738 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3739}
9ac98284
JB		 3740
3741/**
3742 * e1000_intr_msi - Interrupt Handler
3743 * @irq: interrupt number
3744 * @data: pointer to a network interface device structure
3745 **/
3746
b5fc8f0c
JB		 3747static irqreturn_t
3748e1000_intr_msi(int irq, void *data)
9ac98284
JB		 3749{
3750 struct net_device *netdev = data;
3751 struct e1000_adapter *adapter = netdev_priv(netdev);
3752 struct e1000_hw *hw = &adapter->hw;
3753#ifndef CONFIG_E1000_NAPI
3754 int i;
3755#endif
b5fc8f0c 3756 uint32_t icr = E1000_READ_REG(hw, ICR);
9ac98284 3757
9ac98284 3758#ifdef CONFIG_E1000_NAPI
b5fc8f0c
JB		 3759 /* read ICR disables interrupts using IAM, so keep up with our
3760 * enable/disable accounting */
3761 atomic_inc(&adapter->irq_sem);
9ac98284 3762#endif
b5fc8f0c
JB		 3763 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3764 hw->get_link_status = 1;
3765 /* 80003ES2LAN workaround-- For packet buffer work-around on
3766 * link down event; disable receives here in the ISR and reset
3767 * adapter in watchdog */
3768 if (netif_carrier_ok(netdev) &&
3769 (adapter->hw.mac_type == e1000_80003es2lan)) {
3770 /* disable receives */
3771 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3772 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
9ac98284 3773 }
b5fc8f0c
JB		 3774 /* guard against interrupt when we're going down */
3775 if (!test_bit(__E1000_DOWN, &adapter->flags))
3776 mod_timer(&adapter->watchdog_timer, jiffies + 1);
9ac98284
JB		 3777 }
3778
3779#ifdef CONFIG_E1000_NAPI
bea3348e 3780 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3781 adapter->total_tx_bytes = 0;
3782 adapter->total_tx_packets = 0;
3783 adapter->total_rx_bytes = 0;
3784 adapter->total_rx_packets = 0;
bea3348e 3785 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3786 } else
9ac98284
JB		 3787 e1000_irq_enable(adapter);
3788#else
835bb129
JB		 3789 adapter->total_tx_bytes = 0;
3790 adapter->total_rx_bytes = 0;
3791 adapter->total_tx_packets = 0;
3792 adapter->total_rx_packets = 0;
3793
9ac98284
JB		 3794 for (i = 0; i < E1000_MAX_INTR; i++)
3795 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3796 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
9ac98284 3797 break;
835bb129
JB		 3798
3799 if (likely(adapter->itr_setting & 3))
3800 e1000_set_itr(adapter);
9ac98284
JB		 3801#endif
3802
3803 return IRQ_HANDLED;
3804}
1da177e4
LT		 3805
3806/**
3807 * e1000_intr - Interrupt Handler
3808 * @irq: interrupt number
3809 * @data: pointer to a network interface device structure
1da177e4
LT		 3810 **/
3811
3812static irqreturn_t
7d12e780 3813e1000_intr(int irq, void *data)
1da177e4
LT		 3814{
3815 struct net_device *netdev = data;
60490fe0 3816 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3817 struct e1000_hw *hw = &adapter->hw;
87041639 3818 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3819#ifndef CONFIG_E1000_NAPI
581d708e 3820 int i;
835bb129
JB		 3821#endif
3822 if (unlikely(!icr))
3823 return IRQ_NONE; /* Not our interrupt */
3824
3825#ifdef CONFIG_E1000_NAPI
3826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3827 * not set, then the adapter didn't send an interrupt */
3828 if (unlikely(hw->mac_type >= e1000_82571 &&
3829 !(icr & E1000_ICR_INT_ASSERTED)))
3830 return IRQ_NONE;
3831
1e613fd9
JK		 3832 /* Interrupt Auto-Mask...upon reading ICR,
3833 * interrupts are masked. No need for the
3834 * IMC write, but it does mean we should
3835 * account for it ASAP. */
3836 if (likely(hw->mac_type >= e1000_82571))
3837 atomic_inc(&adapter->irq_sem);
be2b28ed 3838#endif
1da177e4 3839
96838a40 3840 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3841 hw->get_link_status = 1;
87041639
JK		 3842 /* 80003ES2LAN workaround--
3843 * For packet buffer work-around on link down event;
3844 * disable receives here in the ISR and
3845 * reset adapter in watchdog
3846 */
3847 if (netif_carrier_ok(netdev) &&
3848 (adapter->hw.mac_type == e1000_80003es2lan)) {
3849 /* disable receives */
3850 rctl = E1000_READ_REG(hw, RCTL);
3851 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3852 }
1314bbf3
AK		 3853 /* guard against interrupt when we're going down */
3854 if (!test_bit(__E1000_DOWN, &adapter->flags))
3855 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3856 }
3857
3858#ifdef CONFIG_E1000_NAPI
1e613fd9 3859 if (unlikely(hw->mac_type < e1000_82571)) {
835bb129 3860 /* disable interrupts, without the synchronize_irq bit */
1e613fd9
JK		 3861 atomic_inc(&adapter->irq_sem);
3862 E1000_WRITE_REG(hw, IMC, ~0);
3863 E1000_WRITE_FLUSH(hw);
3864 }
bea3348e 3865 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3866 adapter->total_tx_bytes = 0;
3867 adapter->total_tx_packets = 0;
3868 adapter->total_rx_bytes = 0;
3869 adapter->total_rx_packets = 0;
bea3348e 3870 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3871 } else
90fb5135
AK		 3872 /* this really should not happen! if it does it is basically a
3873 * bug, but not a hard error, so enable ints and continue */
581d708e 3874 e1000_irq_enable(adapter);
c1605eb3 3875#else
1da177e4 3876 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3877 * Due to Hub Link bus being occupied, an interrupt
3878 * de-assertion message is not able to be sent.
3879 * When an interrupt assertion message is generated later,
3880 * two messages are re-ordered and sent out.
3881 * That causes APIC to think 82547 is in de-assertion
3882 * state, while 82547 is in assertion state, resulting
3883 * in dead lock. Writing IMC forces 82547 into
3884 * de-assertion state.
3885 */
3886 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3887 atomic_inc(&adapter->irq_sem);
2648345f 3888 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3889 }
3890
835bb129
JB		 3891 adapter->total_tx_bytes = 0;
3892 adapter->total_rx_bytes = 0;
3893 adapter->total_tx_packets = 0;
3894 adapter->total_rx_packets = 0;
3895
96838a40
JB		 3896 for (i = 0; i < E1000_MAX_INTR; i++)
3897 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3898 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3899 break;
3900
835bb129
JB		 3901 if (likely(adapter->itr_setting & 3))
3902 e1000_set_itr(adapter);
3903
96838a40 3904 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3905 e1000_irq_enable(adapter);
581d708e 3906
c1605eb3 3907#endif
1da177e4
LT		 3908 return IRQ_HANDLED;
3909}
3910
3911#ifdef CONFIG_E1000_NAPI
3912/**
3913 * e1000_clean - NAPI Rx polling callback
3914 * @adapter: board private structure
3915 **/
3916
3917static int
bea3348e 3918e1000_clean(struct napi_struct *napi, int budget)
1da177e4 3919{
bea3348e
SH		 3920 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
3921 struct net_device *poll_dev = adapter->netdev;
d3d9e484 3922 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3923
3924 /* Must NOT use netdev_priv macro here. */
3925 adapter = poll_dev->priv;
3926
d3d9e484
AK		 3927 /* e1000_clean is called per-cpu. This lock protects
3928 * tx_ring[0] from being cleaned by multiple cpus
3929 * simultaneously. A failure obtaining the lock means
3930 * tx_ring[0] is currently being cleaned anyway. */
3931 if (spin_trylock(&adapter->tx_queue_lock)) {
3932 tx_cleaned = e1000_clean_tx_irq(adapter,
3933 &adapter->tx_ring[0]);
3934 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3935 }
3936
d3d9e484 3937 adapter->clean_rx(adapter, &adapter->rx_ring[0],
bea3348e 3938 &work_done, budget);
96838a40 3939
2b02893e 3940 /* If no Tx and not enough Rx work done, exit the polling mode */
4ec24119 3941 if ((!tx_cleaned && (work_done == 0))) {
835bb129
JB		 3942 if (likely(adapter->itr_setting & 3))
3943 e1000_set_itr(adapter);
bea3348e 3944 netif_rx_complete(poll_dev, napi);
1da177e4 3945 e1000_irq_enable(adapter);
1da177e4
LT		 3946 }
3947
bea3348e 3948 return work_done;
1da177e4
LT		 3949}
3950
3951#endif
3952/**
3953 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3954 * @adapter: board private structure
3955 **/
3956
3957static boolean_t
581d708e
MC		 3958e1000_clean_tx_irq(struct e1000_adapter *adapter,
3959 struct e1000_tx_ring *tx_ring)
1da177e4 3960{
1da177e4
LT		 3961 struct net_device *netdev = adapter->netdev;
3962 struct e1000_tx_desc *tx_desc, *eop_desc;
3963 struct e1000_buffer *buffer_info;
3964 unsigned int i, eop;
2a1af5d7
JK		 3965#ifdef CONFIG_E1000_NAPI
3966 unsigned int count = 0;
3967#endif
46fcc86d 3968 boolean_t cleaned = FALSE;
835bb129 3969 unsigned int total_tx_bytes=0, total_tx_packets=0;
1da177e4
LT		 3970
3971 i = tx_ring->next_to_clean;
3972 eop = tx_ring->buffer_info[i].next_to_watch;
3973 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3974
581d708e 3975 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3976 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3977 tx_desc = E1000_TX_DESC(*tx_ring, i);
3978 buffer_info = &tx_ring->buffer_info[i];
3979 cleaned = (i == eop);
3980
835bb129 3981 if (cleaned) {
2b65326e 3982 struct sk_buff *skb = buffer_info->skb;
7753b171
JB		 3983 unsigned int segs, bytecount;
3984 segs = skb_shinfo(skb)->gso_segs ?: 1;
3985 /* multiply data chunks by size of headers */
3986 bytecount = ((segs - 1) * skb_headlen(skb)) +
3987 skb->len;
2b65326e 3988 total_tx_packets += segs;
7753b171 3989 total_tx_bytes += bytecount;
835bb129 3990 }
fd803241 3991 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 3992 tx_desc->upper.data = 0;
1da177e4 3993
96838a40 3994 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3995 }
581d708e 3996
1da177e4
LT		 3997 eop = tx_ring->buffer_info[i].next_to_watch;
3998 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3999#ifdef CONFIG_E1000_NAPI
4000#define E1000_TX_WEIGHT 64
4001 /* weight of a sort for tx, to avoid endless transmit cleanup */
46fcc86d 4002 if (count++ == E1000_TX_WEIGHT) break;
2a1af5d7 4003#endif
1da177e4
LT		 4004 }
4005
4006 tx_ring->next_to_clean = i;
4007
77b2aad5 4008#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 4009 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
4010 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
4011 /* Make sure that anybody stopping the queue after this
4012 * sees the new next_to_clean.
4013 */
4014 smp_mb();
fcfb1224 4015 if (netif_queue_stopped(netdev)) {
77b2aad5 4016 netif_wake_queue(netdev);
fcfb1224
JB		 4017 ++adapter->restart_queue;
4018 }
77b2aad5 4019 }
2648345f 4020
581d708e 4021 if (adapter->detect_tx_hung) {
2648345f 4022 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 4023 * check with the clearing of time_stamp and movement of i */
4024 adapter->detect_tx_hung = FALSE;
392137fa
JK		 4025 if (tx_ring->buffer_info[eop].dma &&
4026 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 4027 (adapter->tx_timeout_factor * HZ))
70b8f1e1 4028 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 4029 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 4030
4031 /* detected Tx unit hang */
c6963ef5 4032 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 4033 " Tx Queue <%lu>\n"
70b8f1e1
MC		 4034 " TDH <%x>\n"
4035 " TDT <%x>\n"
4036 " next_to_use <%x>\n"
4037 " next_to_clean <%x>\n"
4038 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 4039 " time_stamp <%lx>\n"
4040 " next_to_watch <%x>\n"
4041 " jiffies <%lx>\n"
4042 " next_to_watch.status <%x>\n",
7bfa4816
JK		 4043 (unsigned long)((tx_ring - adapter->tx_ring) /
4044 sizeof(struct e1000_tx_ring)),
581d708e
MC		 4045 readl(adapter->hw.hw_addr + tx_ring->tdh),
4046 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 4047 tx_ring->next_to_use,
392137fa
JK		 4048 tx_ring->next_to_clean,
4049 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 4050 eop,
4051 jiffies,
4052 eop_desc->upper.fields.status);
1da177e4 4053 netif_stop_queue(netdev);
70b8f1e1 4054 }
1da177e4 4055 }
835bb129
JB		 4056 adapter->total_tx_bytes += total_tx_bytes;
4057 adapter->total_tx_packets += total_tx_packets;
1da177e4
LT		 4058 return cleaned;
4059}
4060
4061/**
4062 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 4063 * @adapter: board private structure
4064 * @status_err: receive descriptor status and error fields
4065 * @csum: receive descriptor csum field
4066 * @sk_buff: socket buffer with received data
1da177e4
LT		 4067 **/
4068
e619d523 4069static void
1da177e4 4070e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 4071 uint32_t status_err, uint32_t csum,
4072 struct sk_buff *skb)
1da177e4 4073{
2d7edb92
MC		 4074 uint16_t status = (uint16_t)status_err;
4075 uint8_t errors = (uint8_t)(status_err >> 24);
4076 skb->ip_summed = CHECKSUM_NONE;
4077
1da177e4 4078 /* 82543 or newer only */
96838a40 4079 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 4080 /* Ignore Checksum bit is set */
96838a40 4081 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 4082 /* TCP/UDP checksum error bit is set */
96838a40 4083 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 4084 /* let the stack verify checksum errors */
1da177e4 4085 adapter->hw_csum_err++;
2d7edb92
MC		 4086 return;
4087 }
4088 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 4089 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
4090 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 4091 return;
1da177e4 4092 } else {
96838a40 4093 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 4094 return;
4095 }
4096 /* It must be a TCP or UDP packet with a valid checksum */
4097 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 4098 /* TCP checksum is good */
4099 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 4100 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
4101 /* IP fragment with UDP payload */
4102 /* Hardware complements the payload checksum, so we undo it
4103 * and then put the value in host order for further stack use.
4104 */
4105 csum = ntohl(csum ^ 0xFFFF);
4106 skb->csum = csum;
84fa7933 4107 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 4108 }
2d7edb92 4109 adapter->hw_csum_good++;
1da177e4
LT		 4110}
4111
4112/**
2d7edb92 4113 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 4114 * @adapter: board private structure
4115 **/
4116
4117static boolean_t
4118#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4119e1000_clean_rx_irq(struct e1000_adapter *adapter,
4120 struct e1000_rx_ring *rx_ring,
4121 int *work_done, int work_to_do)
1da177e4 4122#else
581d708e
MC		 4123e1000_clean_rx_irq(struct e1000_adapter *adapter,
4124 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 4125#endif
4126{
1da177e4
LT		 4127 struct net_device *netdev = adapter->netdev;
4128 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 4129 struct e1000_rx_desc *rx_desc, *next_rxd;
4130 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 4131 unsigned long flags;
4132 uint32_t length;
4133 uint8_t last_byte;
4134 unsigned int i;
72d64a43 4135 int cleaned_count = 0;
a1415ee6 4136 boolean_t cleaned = FALSE;
835bb129 4137 unsigned int total_rx_bytes=0, total_rx_packets=0;
1da177e4
LT		 4138
4139 i = rx_ring->next_to_clean;
4140 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 4141 buffer_info = &rx_ring->buffer_info[i];
1da177e4 4142
b92ff8ee 4143 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 4144 struct sk_buff *skb;
a292ca6e 4145 u8 status;
90fb5135 4146
1da177e4 4147#ifdef CONFIG_E1000_NAPI
96838a40 4148 if (*work_done >= work_to_do)
1da177e4
LT		 4149 break;
4150 (*work_done)++;
4151#endif
a292ca6e 4152 status = rx_desc->status;
b92ff8ee 4153 skb = buffer_info->skb;
86c3d59f
JB		 4154 buffer_info->skb = NULL;
4155
30320be8
JK		 4156 prefetch(skb->data - NET_IP_ALIGN);
4157
86c3d59f
JB		 4158 if (++i == rx_ring->count) i = 0;
4159 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 4160 prefetch(next_rxd);
4161
86c3d59f 4162 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4163
72d64a43
JK		 4164 cleaned = TRUE;
4165 cleaned_count++;
a292ca6e
JK		 4166 pci_unmap_single(pdev,
4167 buffer_info->dma,
4168 buffer_info->length,
1da177e4
LT		 4169 PCI_DMA_FROMDEVICE);
4170
1da177e4
LT		 4171 length = le16_to_cpu(rx_desc->length);
4172
a1415ee6
JK		 4173 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
4174 /* All receives must fit into a single buffer */
4175 E1000_DBG("%s: Receive packet consumed multiple"
4176 " buffers\n", netdev->name);
864c4e45 4177 /* recycle */
8fc897b0 4178 buffer_info->skb = skb;
1da177e4
LT		 4179 goto next_desc;
4180 }
4181
96838a40 4182 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 4183 last_byte = *(skb->data + length - 1);
b92ff8ee 4184 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 4185 rx_desc->errors, length, last_byte)) {
4186 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 4187 e1000_tbi_adjust_stats(&adapter->hw,
4188 &adapter->stats,
1da177e4
LT		 4189 length, skb->data);
4190 spin_unlock_irqrestore(&adapter->stats_lock,
4191 flags);
4192 length--;
4193 } else {
9e2feace
AK		 4194 /* recycle */
4195 buffer_info->skb = skb;
1da177e4
LT		 4196 goto next_desc;
4197 }
1cb5821f 4198 }
1da177e4 4199
d2a1e213
JB		 4200 /* adjust length to remove Ethernet CRC, this must be
4201 * done after the TBI_ACCEPT workaround above */
4202 length -= 4;
4203
835bb129
JB		 4204 /* probably a little skewed due to removing CRC */
4205 total_rx_bytes += length;
4206 total_rx_packets++;
4207
a292ca6e
JK		 4208 /* code added for copybreak, this should improve
4209 * performance for small packets with large amounts
4210 * of reassembly being done in the stack */
1f753861 4211 if (length < copybreak) {
a292ca6e 4212 struct sk_buff *new_skb =
87f5032e 4213 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 4214 if (new_skb) {
4215 skb_reserve(new_skb, NET_IP_ALIGN);
27d7ff46
ACM		 4216 skb_copy_to_linear_data_offset(new_skb,
4217 -NET_IP_ALIGN,
4218 (skb->data -
4219 NET_IP_ALIGN),
4220 (length +
4221 NET_IP_ALIGN));
a292ca6e
JK		 4222 /* save the skb in buffer_info as good */
4223 buffer_info->skb = skb;
4224 skb = new_skb;
a292ca6e 4225 }
996695de
AK		 4226 /* else just continue with the old one */
4227 }
a292ca6e 4228 /* end copybreak code */
996695de 4229 skb_put(skb, length);
1da177e4
LT		 4230
4231 /* Receive Checksum Offload */
a292ca6e
JK		 4232 e1000_rx_checksum(adapter,
4233 (uint32_t)(status) |
2d7edb92 4234 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 4235 le16_to_cpu(rx_desc->csum), skb);
96838a40 4236
1da177e4
LT		 4237 skb->protocol = eth_type_trans(skb, netdev);
4238#ifdef CONFIG_E1000_NAPI
96838a40 4239 if (unlikely(adapter->vlgrp &&
a292ca6e 4240 (status & E1000_RXD_STAT_VP))) {
1da177e4 4241 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 4242 le16_to_cpu(rx_desc->special) &
4243 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 4244 } else {
4245 netif_receive_skb(skb);
4246 }
4247#else /* CONFIG_E1000_NAPI */
96838a40 4248 if (unlikely(adapter->vlgrp &&
b92ff8ee 4249 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 4250 vlan_hwaccel_rx(skb, adapter->vlgrp,
4251 le16_to_cpu(rx_desc->special) &
4252 E1000_RXD_SPC_VLAN_MASK);
4253 } else {
4254 netif_rx(skb);
4255 }
4256#endif /* CONFIG_E1000_NAPI */
4257 netdev->last_rx = jiffies;
4258
4259next_desc:
4260 rx_desc->status = 0;
1da177e4 4261
72d64a43
JK		 4262 /* return some buffers to hardware, one at a time is too slow */
4263 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4264 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4265 cleaned_count = 0;
4266 }
4267
30320be8 4268 /* use prefetched values */
86c3d59f
JB		 4269 rx_desc = next_rxd;
4270 buffer_info = next_buffer;
1da177e4 4271 }
1da177e4 4272 rx_ring->next_to_clean = i;
72d64a43
JK		 4273
4274 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4275 if (cleaned_count)
4276 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92 4277
835bb129
JB		 4278 adapter->total_rx_packets += total_rx_packets;
4279 adapter->total_rx_bytes += total_rx_bytes;
2d7edb92
MC		 4280 return cleaned;
4281}
4282
4283/**
4284 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
4285 * @adapter: board private structure
4286 **/
4287
4288static boolean_t
4289#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4290e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4291 struct e1000_rx_ring *rx_ring,
4292 int *work_done, int work_to_do)
2d7edb92 4293#else
581d708e
MC		 4294e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4295 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 4296#endif
4297{
86c3d59f 4298 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 4299 struct net_device *netdev = adapter->netdev;
4300 struct pci_dev *pdev = adapter->pdev;
86c3d59f 4301 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 4302 struct e1000_ps_page *ps_page;
4303 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 4304 struct sk_buff *skb;
2d7edb92
MC		 4305 unsigned int i, j;
4306 uint32_t length, staterr;
72d64a43 4307 int cleaned_count = 0;
2d7edb92 4308 boolean_t cleaned = FALSE;
835bb129 4309 unsigned int total_rx_bytes=0, total_rx_packets=0;
2d7edb92
MC		 4310
4311 i = rx_ring->next_to_clean;
4312 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 4313 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 4314 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 4315
96838a40 4316 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 4317 ps_page = &rx_ring->ps_page[i];
4318 ps_page_dma = &rx_ring->ps_page_dma[i];
4319#ifdef CONFIG_E1000_NAPI
96838a40 4320 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 4321 break;
4322 (*work_done)++;
4323#endif
86c3d59f
JB		 4324 skb = buffer_info->skb;
4325
30320be8
JK		 4326 /* in the packet split case this is header only */
4327 prefetch(skb->data - NET_IP_ALIGN);
4328
86c3d59f
JB		 4329 if (++i == rx_ring->count) i = 0;
4330 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 4331 prefetch(next_rxd);
4332
86c3d59f 4333 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4334
2d7edb92 4335 cleaned = TRUE;
72d64a43 4336 cleaned_count++;
2d7edb92
MC		 4337 pci_unmap_single(pdev, buffer_info->dma,
4338 buffer_info->length,
4339 PCI_DMA_FROMDEVICE);
4340
96838a40 4341 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 4342 E1000_DBG("%s: Packet Split buffers didn't pick up"
4343 " the full packet\n", netdev->name);
4344 dev_kfree_skb_irq(skb);
4345 goto next_desc;
4346 }
1da177e4 4347
96838a40 4348 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 4349 dev_kfree_skb_irq(skb);
4350 goto next_desc;
4351 }
4352
4353 length = le16_to_cpu(rx_desc->wb.middle.length0);
4354
96838a40 4355 if (unlikely(!length)) {
2d7edb92
MC		 4356 E1000_DBG("%s: Last part of the packet spanning"
4357 " multiple descriptors\n", netdev->name);
4358 dev_kfree_skb_irq(skb);
4359 goto next_desc;
4360 }
4361
4362 /* Good Receive */
4363 skb_put(skb, length);
4364
dc7c6add
JK		 4365 {
4366 /* this looks ugly, but it seems compiler issues make it
4367 more efficient than reusing j */
4368 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4369
4370 /* page alloc/put takes too long and effects small packet
4371 * throughput, so unsplit small packets and save the alloc/put*/
1f753861 4372 if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4373 u8 *vaddr;
76c224bc 4374 /* there is no documentation about how to call
dc7c6add
JK		 4375 * kmap_atomic, so we can't hold the mapping
4376 * very long */
4377 pci_dma_sync_single_for_cpu(pdev,
4378 ps_page_dma->ps_page_dma[0],
4379 PAGE_SIZE,
4380 PCI_DMA_FROMDEVICE);
4381 vaddr = kmap_atomic(ps_page->ps_page[0],
4382 KM_SKB_DATA_SOFTIRQ);
27a884dc 4383 memcpy(skb_tail_pointer(skb), vaddr, l1);
dc7c6add
JK		 4384 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4385 pci_dma_sync_single_for_device(pdev,
4386 ps_page_dma->ps_page_dma[0],
4387 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4388 /* remove the CRC */
4389 l1 -= 4;
dc7c6add 4390 skb_put(skb, l1);
dc7c6add
JK		 4391 goto copydone;
4392 } /* if */
4393 }
90fb5135 4394
96838a40 4395 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4396 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4397 break;
2d7edb92
MC		 4398 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4399 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4400 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4401 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4402 length);
2d7edb92 4403 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4404 skb->len += length;
4405 skb->data_len += length;
5d51b80f 4406 skb->truesize += length;
2d7edb92
MC		 4407 }
4408
f235a2ab
AK		 4409 /* strip the ethernet crc, problem is we're using pages now so
4410 * this whole operation can get a little cpu intensive */
4411 pskb_trim(skb, skb->len - 4);
4412
dc7c6add 4413copydone:
835bb129
JB		 4414 total_rx_bytes += skb->len;
4415 total_rx_packets++;
4416
2d7edb92 4417 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4418 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4419 skb->protocol = eth_type_trans(skb, netdev);
4420
96838a40 4421 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4422 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4423 adapter->rx_hdr_split++;
2d7edb92 4424#ifdef CONFIG_E1000_NAPI
96838a40 4425 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4426 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 4427 le16_to_cpu(rx_desc->wb.middle.vlan) &
4428 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4429 } else {
4430 netif_receive_skb(skb);
4431 }
4432#else /* CONFIG_E1000_NAPI */
96838a40 4433 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4434 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 4435 le16_to_cpu(rx_desc->wb.middle.vlan) &
4436 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4437 } else {
4438 netif_rx(skb);
4439 }
4440#endif /* CONFIG_E1000_NAPI */
4441 netdev->last_rx = jiffies;
4442
4443next_desc:
c3d7a3a4 4444 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4445 buffer_info->skb = NULL;
2d7edb92 4446
72d64a43
JK		 4447 /* return some buffers to hardware, one at a time is too slow */
4448 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4449 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4450 cleaned_count = 0;
4451 }
4452
30320be8 4453 /* use prefetched values */
86c3d59f
JB		 4454 rx_desc = next_rxd;
4455 buffer_info = next_buffer;
4456
683a38f3 4457 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4458 }
4459 rx_ring->next_to_clean = i;
72d64a43
JK		 4460
4461 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4462 if (cleaned_count)
4463 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4 4464
835bb129
JB		 4465 adapter->total_rx_packets += total_rx_packets;
4466 adapter->total_rx_bytes += total_rx_bytes;
1da177e4
LT		 4467 return cleaned;
4468}
4469
4470/**
2d7edb92 4471 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4472 * @adapter: address of board private structure
4473 **/
4474
4475static void
581d708e 4476e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4477 struct e1000_rx_ring *rx_ring,
a292ca6e 4478 int cleaned_count)
1da177e4 4479{
1da177e4
LT		 4480 struct net_device *netdev = adapter->netdev;
4481 struct pci_dev *pdev = adapter->pdev;
4482 struct e1000_rx_desc *rx_desc;
4483 struct e1000_buffer *buffer_info;
4484 struct sk_buff *skb;
2648345f
MC		 4485 unsigned int i;
4486 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4487
4488 i = rx_ring->next_to_use;
4489 buffer_info = &rx_ring->buffer_info[i];
4490
a292ca6e 4491 while (cleaned_count--) {
ca6f7224
CH		 4492 skb = buffer_info->skb;
4493 if (skb) {
a292ca6e
JK		 4494 skb_trim(skb, 0);
4495 goto map_skb;
4496 }
4497
ca6f7224 4498 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4499 if (unlikely(!skb)) {
1da177e4 4500 /* Better luck next round */
72d64a43 4501 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4502 break;
4503 }
4504
2648345f 4505 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4506 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4507 struct sk_buff *oldskb = skb;
2648345f
MC		 4508 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4509 "at %p\n", bufsz, skb->data);
4510 /* Try again, without freeing the previous */
87f5032e 4511 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4512 /* Failed allocation, critical failure */
1da177e4
LT		 4513 if (!skb) {
4514 dev_kfree_skb(oldskb);
4515 break;
4516 }
2648345f 4517
1da177e4
LT		 4518 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4519 /* give up */
4520 dev_kfree_skb(skb);
4521 dev_kfree_skb(oldskb);
4522 break; /* while !buffer_info->skb */
1da177e4 4523 }
ca6f7224
CH		 4524
4525 /* Use new allocation */
4526 dev_kfree_skb(oldskb);
1da177e4 4527 }
1da177e4
LT		 4528 /* Make buffer alignment 2 beyond a 16 byte boundary
4529 * this will result in a 16 byte aligned IP header after
4530 * the 14 byte MAC header is removed
4531 */
4532 skb_reserve(skb, NET_IP_ALIGN);
4533
1da177e4
LT		 4534 buffer_info->skb = skb;
4535 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4536map_skb:
1da177e4
LT		 4537 buffer_info->dma = pci_map_single(pdev,
4538 skb->data,
4539 adapter->rx_buffer_len,
4540 PCI_DMA_FROMDEVICE);
4541
2648345f
MC		 4542 /* Fix for errata 23, can't cross 64kB boundary */
4543 if (!e1000_check_64k_bound(adapter,
4544 (void *)(unsigned long)buffer_info->dma,
4545 adapter->rx_buffer_len)) {
4546 DPRINTK(RX_ERR, ERR,
4547 "dma align check failed: %u bytes at %p\n",
4548 adapter->rx_buffer_len,
4549 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4550 dev_kfree_skb(skb);
4551 buffer_info->skb = NULL;
4552
2648345f 4553 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4554 adapter->rx_buffer_len,
4555 PCI_DMA_FROMDEVICE);
4556
4557 break; /* while !buffer_info->skb */
4558 }
1da177e4
LT		 4559 rx_desc = E1000_RX_DESC(*rx_ring, i);
4560 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4561
96838a40
JB		 4562 if (unlikely(++i == rx_ring->count))
4563 i = 0;
1da177e4
LT		 4564 buffer_info = &rx_ring->buffer_info[i];
4565 }
4566
b92ff8ee
JB		 4567 if (likely(rx_ring->next_to_use != i)) {
4568 rx_ring->next_to_use = i;
4569 if (unlikely(i-- == 0))
4570 i = (rx_ring->count - 1);
4571
4572 /* Force memory writes to complete before letting h/w
4573 * know there are new descriptors to fetch. (Only
4574 * applicable for weak-ordered memory model archs,
4575 * such as IA-64). */
4576 wmb();
4577 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4578 }
1da177e4
LT		 4579}
4580
2d7edb92
MC		 4581/**
4582 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4583 * @adapter: address of board private structure
4584 **/
4585
4586static void
581d708e 4587e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4588 struct e1000_rx_ring *rx_ring,
4589 int cleaned_count)
2d7edb92 4590{
2d7edb92
MC		 4591 struct net_device *netdev = adapter->netdev;
4592 struct pci_dev *pdev = adapter->pdev;
4593 union e1000_rx_desc_packet_split *rx_desc;
4594 struct e1000_buffer *buffer_info;
4595 struct e1000_ps_page *ps_page;
4596 struct e1000_ps_page_dma *ps_page_dma;
4597 struct sk_buff *skb;
4598 unsigned int i, j;
4599
4600 i = rx_ring->next_to_use;
4601 buffer_info = &rx_ring->buffer_info[i];
4602 ps_page = &rx_ring->ps_page[i];
4603 ps_page_dma = &rx_ring->ps_page_dma[i];
4604
72d64a43 4605 while (cleaned_count--) {
2d7edb92
MC		 4606 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4607
96838a40 4608 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4609 if (j < adapter->rx_ps_pages) {
4610 if (likely(!ps_page->ps_page[j])) {
4611 ps_page->ps_page[j] =
4612 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4613 if (unlikely(!ps_page->ps_page[j])) {
4614 adapter->alloc_rx_buff_failed++;
e4c811c9 4615 goto no_buffers;
b92ff8ee 4616 }
e4c811c9
MC		 4617 ps_page_dma->ps_page_dma[j] =
4618 pci_map_page(pdev,
4619 ps_page->ps_page[j],
4620 0, PAGE_SIZE,
4621 PCI_DMA_FROMDEVICE);
4622 }
4623 /* Refresh the desc even if buffer_addrs didn't
96838a40 4624 * change because each write-back erases
e4c811c9
MC		 4625 * this info.
4626 */
4627 rx_desc->read.buffer_addr[j+1] =
4628 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4629 } else
4630 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4631 }
4632
87f5032e 4633 skb = netdev_alloc_skb(netdev,
90fb5135 4634 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4635
b92ff8ee
JB		 4636 if (unlikely(!skb)) {
4637 adapter->alloc_rx_buff_failed++;
2d7edb92 4638 break;
b92ff8ee 4639 }
2d7edb92
MC		 4640
4641 /* Make buffer alignment 2 beyond a 16 byte boundary
4642 * this will result in a 16 byte aligned IP header after
4643 * the 14 byte MAC header is removed
4644 */
4645 skb_reserve(skb, NET_IP_ALIGN);
4646
2d7edb92
MC		 4647 buffer_info->skb = skb;
4648 buffer_info->length = adapter->rx_ps_bsize0;
4649 buffer_info->dma = pci_map_single(pdev, skb->data,
4650 adapter->rx_ps_bsize0,
4651 PCI_DMA_FROMDEVICE);
4652
4653 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4654
96838a40 4655 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4656 buffer_info = &rx_ring->buffer_info[i];
4657 ps_page = &rx_ring->ps_page[i];
4658 ps_page_dma = &rx_ring->ps_page_dma[i];
4659 }
4660
4661no_buffers:
b92ff8ee
JB		 4662 if (likely(rx_ring->next_to_use != i)) {
4663 rx_ring->next_to_use = i;
4664 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4665
4666 /* Force memory writes to complete before letting h/w
4667 * know there are new descriptors to fetch. (Only
4668 * applicable for weak-ordered memory model archs,
4669 * such as IA-64). */
4670 wmb();
4671 /* Hardware increments by 16 bytes, but packet split
4672 * descriptors are 32 bytes...so we increment tail
4673 * twice as much.
4674 */
4675 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4676 }
2d7edb92
MC		 4677}
4678
1da177e4
LT		 4679/**
4680 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4681 * @adapter:
4682 **/
4683
4684static void
4685e1000_smartspeed(struct e1000_adapter *adapter)
4686{
4687 uint16_t phy_status;
4688 uint16_t phy_ctrl;
4689
96838a40 4690 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4691 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4692 return;
4693
96838a40 4694 if (adapter->smartspeed == 0) {
1da177e4
LT		 4695 /* If Master/Slave config fault is asserted twice,
4696 * we assume back-to-back */
4697 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4698 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4699 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4700 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4701 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4702 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4703 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4704 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4705 phy_ctrl);
4706 adapter->smartspeed++;
96838a40 4707 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4708 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4709 &phy_ctrl)) {
4710 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4711 MII_CR_RESTART_AUTO_NEG);
4712 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4713 phy_ctrl);
4714 }
4715 }
4716 return;
96838a40 4717 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4718 /* If still no link, perhaps using 2/3 pair cable */
4719 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4720 phy_ctrl |= CR_1000T_MS_ENABLE;
4721 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4722 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4723 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4724 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4725 MII_CR_RESTART_AUTO_NEG);
4726 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4727 }
4728 }
4729 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4730 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4731 adapter->smartspeed = 0;
4732}
4733
4734/**
4735 * e1000_ioctl -
4736 * @netdev:
4737 * @ifreq:
4738 * @cmd:
4739 **/
4740
4741static int
4742e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4743{
4744 switch (cmd) {
4745 case SIOCGMIIPHY:
4746 case SIOCGMIIREG:
4747 case SIOCSMIIREG:
4748 return e1000_mii_ioctl(netdev, ifr, cmd);
4749 default:
4750 return -EOPNOTSUPP;
4751 }
4752}
4753
4754/**
4755 * e1000_mii_ioctl -
4756 * @netdev:
4757 * @ifreq:
4758 * @cmd:
4759 **/
4760
4761static int
4762e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4763{
60490fe0 4764 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4765 struct mii_ioctl_data *data = if_mii(ifr);
4766 int retval;
4767 uint16_t mii_reg;
4768 uint16_t spddplx;
97876fc6 4769 unsigned long flags;
1da177e4 4770
96838a40 4771 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4772 return -EOPNOTSUPP;
4773
4774 switch (cmd) {
4775 case SIOCGMIIPHY:
4776 data->phy_id = adapter->hw.phy_addr;
4777 break;
4778 case SIOCGMIIREG:
96838a40 4779 if (!capable(CAP_NET_ADMIN))
1da177e4 4780 return -EPERM;
97876fc6 4781 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4782 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4783 &data->val_out)) {
4784 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4785 return -EIO;
97876fc6
MC		 4786 }
4787 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4788 break;
4789 case SIOCSMIIREG:
96838a40 4790 if (!capable(CAP_NET_ADMIN))
1da177e4 4791 return -EPERM;
96838a40 4792 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4793 return -EFAULT;
4794 mii_reg = data->val_in;
97876fc6 4795 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4796 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4797 mii_reg)) {
4798 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4799 return -EIO;
97876fc6 4800 }
f0163ac4 4801 spin_unlock_irqrestore(&adapter->stats_lock, flags);
dc86d32a 4802 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4803 switch (data->reg_num) {
4804 case PHY_CTRL:
96838a40 4805 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4806 break;
96838a40 4807 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4808 adapter->hw.autoneg = 1;
4809 adapter->hw.autoneg_advertised = 0x2F;
4810 } else {
4811 if (mii_reg & 0x40)
4812 spddplx = SPEED_1000;
4813 else if (mii_reg & 0x2000)
4814 spddplx = SPEED_100;
4815 else
4816 spddplx = SPEED_10;
4817 spddplx += (mii_reg & 0x100)
cb764326
JK		 4818 ? DUPLEX_FULL :
4819 DUPLEX_HALF;
1da177e4
LT		 4820 retval = e1000_set_spd_dplx(adapter,
4821 spddplx);
f0163ac4 4822 if (retval)
1da177e4
LT		 4823 return retval;
4824 }
2db10a08
AK		 4825 if (netif_running(adapter->netdev))
4826 e1000_reinit_locked(adapter);
4827 else
1da177e4
LT		 4828 e1000_reset(adapter);
4829 break;
4830 case M88E1000_PHY_SPEC_CTRL:
4831 case M88E1000_EXT_PHY_SPEC_CTRL:
f0163ac4 4832 if (e1000_phy_reset(&adapter->hw))
1da177e4
LT		 4833 return -EIO;
4834 break;
4835 }
4836 } else {
4837 switch (data->reg_num) {
4838 case PHY_CTRL:
96838a40 4839 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4840 break;
2db10a08
AK		 4841 if (netif_running(adapter->netdev))
4842 e1000_reinit_locked(adapter);
4843 else
1da177e4
LT		 4844 e1000_reset(adapter);
4845 break;
4846 }
4847 }
4848 break;
4849 default:
4850 return -EOPNOTSUPP;
4851 }
4852 return E1000_SUCCESS;
4853}
4854
4855void
4856e1000_pci_set_mwi(struct e1000_hw *hw)
4857{
4858 struct e1000_adapter *adapter = hw->back;
2648345f 4859 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4860
96838a40 4861 if (ret_val)
2648345f 4862 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4863}
4864
4865void
4866e1000_pci_clear_mwi(struct e1000_hw *hw)
4867{
4868 struct e1000_adapter *adapter = hw->back;
4869
4870 pci_clear_mwi(adapter->pdev);
4871}
4872
4873void
4874e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4875{
4876 struct e1000_adapter *adapter = hw->back;
4877
4878 pci_read_config_word(adapter->pdev, reg, value);
4879}
4880
4881void
4882e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4883{
4884 struct e1000_adapter *adapter = hw->back;
4885
4886 pci_write_config_word(adapter->pdev, reg, *value);
4887}
4888
007755eb
PO		 4889int
4890e1000_pcix_get_mmrbc(struct e1000_hw *hw)
4891{
4892 struct e1000_adapter *adapter = hw->back;
4893 return pcix_get_mmrbc(adapter->pdev);
4894}
4895
4896void
4897e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
4898{
4899 struct e1000_adapter *adapter = hw->back;
4900 pcix_set_mmrbc(adapter->pdev, mmrbc);
4901}
4902
caeccb68
JK		 4903int32_t
4904e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4905{
4906 struct e1000_adapter *adapter = hw->back;
4907 uint16_t cap_offset;
4908
4909 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4910 if (!cap_offset)
4911 return -E1000_ERR_CONFIG;
4912
4913 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4914
4915 return E1000_SUCCESS;
4916}
4917
1da177e4
LT		 4918void
4919e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4920{
4921 outl(value, port);
4922}
4923
4924static void
4925e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4926{
60490fe0 4927 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4928 uint32_t ctrl, rctl;
4929
4930 e1000_irq_disable(adapter);
4931 adapter->vlgrp = grp;
4932
96838a40 4933 if (grp) {
1da177e4
LT		 4934 /* enable VLAN tag insert/strip */
4935 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4936 ctrl |= E1000_CTRL_VME;
4937 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4938
cd94dd0b 4939 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4940 /* enable VLAN receive filtering */
4941 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4942 rctl |= E1000_RCTL_VFE;
4943 rctl &= ~E1000_RCTL_CFIEN;
4944 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4945 e1000_update_mng_vlan(adapter);
cd94dd0b 4946 }
1da177e4
LT		 4947 } else {
4948 /* disable VLAN tag insert/strip */
4949 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4950 ctrl &= ~E1000_CTRL_VME;
4951 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4952
cd94dd0b 4953 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4954 /* disable VLAN filtering */
4955 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4956 rctl &= ~E1000_RCTL_VFE;
4957 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4958 if (adapter->mng_vlan_id !=
4959 (uint16_t)E1000_MNG_VLAN_NONE) {
4960 e1000_vlan_rx_kill_vid(netdev,
4961 adapter->mng_vlan_id);
4962 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4963 }
cd94dd0b 4964 }
1da177e4
LT		 4965 }
4966
4967 e1000_irq_enable(adapter);
4968}
4969
4970static void
4971e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4972{
60490fe0 4973 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4974 uint32_t vfta, index;
96838a40
JB		 4975
4976 if ((adapter->hw.mng_cookie.status &
4977 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4978 (vid == adapter->mng_vlan_id))
2d7edb92 4979 return;
1da177e4
LT		 4980 /* add VID to filter table */
4981 index = (vid >> 5) & 0x7F;
4982 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4983 vfta |= (1 << (vid & 0x1F));
4984 e1000_write_vfta(&adapter->hw, index, vfta);
4985}
4986
4987static void
4988e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4989{
60490fe0 4990 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4991 uint32_t vfta, index;
4992
4993 e1000_irq_disable(adapter);
5c15bdec 4994 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1da177e4
LT		 4995 e1000_irq_enable(adapter);
4996
96838a40
JB		 4997 if ((adapter->hw.mng_cookie.status &
4998 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4999 (vid == adapter->mng_vlan_id)) {
5000 /* release control to f/w */
5001 e1000_release_hw_control(adapter);
2d7edb92 5002 return;
ff147013
JK		 5003 }
5004
1da177e4
LT		 5005 /* remove VID from filter table */
5006 index = (vid >> 5) & 0x7F;
5007 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5008 vfta &= ~(1 << (vid & 0x1F));
5009 e1000_write_vfta(&adapter->hw, index, vfta);
5010}
5011
5012static void
5013e1000_restore_vlan(struct e1000_adapter *adapter)
5014{
5015 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5016
96838a40 5017 if (adapter->vlgrp) {
1da177e4 5018 uint16_t vid;
96838a40 5019 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5c15bdec 5020 if (!vlan_group_get_device(adapter->vlgrp, vid))
1da177e4
LT		 5021 continue;
5022 e1000_vlan_rx_add_vid(adapter->netdev, vid);
5023 }
5024 }
5025}
5026
5027int
5028e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
5029{
5030 adapter->hw.autoneg = 0;
5031
6921368f 5032 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 5033 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 5034 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5035 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
5036 return -EINVAL;
5037 }
5038
96838a40 5039 switch (spddplx) {
1da177e4
LT		 5040 case SPEED_10 + DUPLEX_HALF:
5041 adapter->hw.forced_speed_duplex = e1000_10_half;
5042 break;
5043 case SPEED_10 + DUPLEX_FULL:
5044 adapter->hw.forced_speed_duplex = e1000_10_full;
5045 break;
5046 case SPEED_100 + DUPLEX_HALF:
5047 adapter->hw.forced_speed_duplex = e1000_100_half;
5048 break;
5049 case SPEED_100 + DUPLEX_FULL:
5050 adapter->hw.forced_speed_duplex = e1000_100_full;
5051 break;
5052 case SPEED_1000 + DUPLEX_FULL:
5053 adapter->hw.autoneg = 1;
5054 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
5055 break;
5056 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5057 default:
2648345f 5058 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 5059 return -EINVAL;
5060 }
5061 return 0;
5062}
5063
1da177e4 5064static int
829ca9a3 5065e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 5066{
5067 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5068 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5069 uint32_t ctrl, ctrl_ext, rctl, status;
1da177e4 5070 uint32_t wufc = adapter->wol;
6fdfef16 5071#ifdef CONFIG_PM
240b1710 5072 int retval = 0;
6fdfef16 5073#endif
1da177e4
LT		 5074
5075 netif_device_detach(netdev);
5076
2db10a08
AK		 5077 if (netif_running(netdev)) {
5078 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 5079 e1000_down(adapter);
2db10a08 5080 }
1da177e4 5081
2f82665f 5082#ifdef CONFIG_PM
1d33e9c6 5083 retval = pci_save_state(pdev);
2f82665f
JB		 5084 if (retval)
5085 return retval;
5086#endif
5087
1da177e4 5088 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 5089 if (status & E1000_STATUS_LU)
1da177e4
LT		 5090 wufc &= ~E1000_WUFC_LNKC;
5091
96838a40 5092 if (wufc) {
1da177e4
LT		 5093 e1000_setup_rctl(adapter);
5094 e1000_set_multi(netdev);
5095
5096 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 5097 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 5098 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5099 rctl |= E1000_RCTL_MPE;
5100 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5101 }
5102
96838a40 5103 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 5104 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
5105 /* advertise wake from D3Cold */
5106 #define E1000_CTRL_ADVD3WUC 0x00100000
5107 /* phy power management enable */
5108 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5109 ctrl |= E1000_CTRL_ADVD3WUC |
5110 E1000_CTRL_EN_PHY_PWR_MGMT;
5111 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5112 }
5113
96838a40 5114 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 5115 adapter->hw.media_type == e1000_media_type_internal_serdes) {
5116 /* keep the laser running in D3 */
5117 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
5118 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
5119 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
5120 }
5121
2d7edb92
MC		 5122 /* Allow time for pending master requests to run */
5123 e1000_disable_pciex_master(&adapter->hw);
5124
1da177e4
LT		 5125 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
5126 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 5127 pci_enable_wake(pdev, PCI_D3hot, 1);
5128 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5129 } else {
5130 E1000_WRITE_REG(&adapter->hw, WUC, 0);
5131 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 5132 pci_enable_wake(pdev, PCI_D3hot, 0);
5133 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 5134 }
5135
0fccd0e9
JG		 5136 e1000_release_manageability(adapter);
5137
5138 /* make sure adapter isn't asleep if manageability is enabled */
5139 if (adapter->en_mng_pt) {
5140 pci_enable_wake(pdev, PCI_D3hot, 1);
5141 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5142 }
5143
cd94dd0b
AK		 5144 if (adapter->hw.phy_type == e1000_phy_igp_3)
5145 e1000_phy_powerdown_workaround(&adapter->hw);
5146
edd106fc
AK		 5147 if (netif_running(netdev))
5148 e1000_free_irq(adapter);
5149
b55ccb35
JK		 5150 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5151 * would have already happened in close and is redundant. */
5152 e1000_release_hw_control(adapter);
2d7edb92 5153
1da177e4 5154 pci_disable_device(pdev);
240b1710 5155
d0e027db 5156 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 5157
5158 return 0;
5159}
5160
2f82665f 5161#ifdef CONFIG_PM
1da177e4
LT		 5162static int
5163e1000_resume(struct pci_dev *pdev)
5164{
5165 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5166 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5167 uint32_t err;
1da177e4 5168
d0e027db 5169 pci_set_power_state(pdev, PCI_D0);
1d33e9c6 5170 pci_restore_state(pdev);
3d1dd8cb
AK		 5171 if ((err = pci_enable_device(pdev))) {
5172 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
5173 return err;
5174 }
a4cb847d 5175 pci_set_master(pdev);
1da177e4 5176
d0e027db
AK		 5177 pci_enable_wake(pdev, PCI_D3hot, 0);
5178 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 5179
edd106fc
AK		 5180 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
5181 return err;
5182
5183 e1000_power_up_phy(adapter);
1da177e4
LT		 5184 e1000_reset(adapter);
5185 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5186
0fccd0e9
JG		 5187 e1000_init_manageability(adapter);
5188
96838a40 5189 if (netif_running(netdev))
1da177e4
LT		 5190 e1000_up(adapter);
5191
5192 netif_device_attach(netdev);
5193
b55ccb35
JK		 5194 /* If the controller is 82573 and f/w is AMT, do not set
5195 * DRV_LOAD until the interface is up. For all other cases,
5196 * let the f/w know that the h/w is now under the control
5197 * of the driver. */
5198 if (adapter->hw.mac_type != e1000_82573 ||
5199 !e1000_check_mng_mode(&adapter->hw))
5200 e1000_get_hw_control(adapter);
2d7edb92 5201
1da177e4
LT		 5202 return 0;
5203}
5204#endif
c653e635
AK		 5205
5206static void e1000_shutdown(struct pci_dev *pdev)
5207{
5208 e1000_suspend(pdev, PMSG_SUSPEND);
5209}
5210
1da177e4
LT		 5211#ifdef CONFIG_NET_POLL_CONTROLLER
5212/*
5213 * Polling 'interrupt' - used by things like netconsole to send skbs
5214 * without having to re-enable interrupts. It's not called while
5215 * the interrupt routine is executing.
5216 */
5217static void
2648345f 5218e1000_netpoll(struct net_device *netdev)
1da177e4 5219{
60490fe0 5220 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 5221
1da177e4 5222 disable_irq(adapter->pdev->irq);
7d12e780 5223 e1000_intr(adapter->pdev->irq, netdev);
c4cfe567 5224 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 5225#ifndef CONFIG_E1000_NAPI
5226 adapter->clean_rx(adapter, adapter->rx_ring);
5227#endif
1da177e4
LT		 5228 enable_irq(adapter->pdev->irq);
5229}
5230#endif
5231
9026729b
AK		 5232/**
5233 * e1000_io_error_detected - called when PCI error is detected
5234 * @pdev: Pointer to PCI device
5235 * @state: The current pci conneection state
5236 *
5237 * This function is called after a PCI bus error affecting
5238 * this device has been detected.
5239 */
5240static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5241{
5242 struct net_device *netdev = pci_get_drvdata(pdev);
5243 struct e1000_adapter *adapter = netdev->priv;
5244
5245 netif_device_detach(netdev);
5246
5247 if (netif_running(netdev))
5248 e1000_down(adapter);
72e8d6bb 5249 pci_disable_device(pdev);
9026729b
AK		 5250
5251 /* Request a slot slot reset. */
5252 return PCI_ERS_RESULT_NEED_RESET;
5253}
5254
5255/**
5256 * e1000_io_slot_reset - called after the pci bus has been reset.
5257 * @pdev: Pointer to PCI device
5258 *
5259 * Restart the card from scratch, as if from a cold-boot. Implementation
5260 * resembles the first-half of the e1000_resume routine.
5261 */
5262static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5263{
5264 struct net_device *netdev = pci_get_drvdata(pdev);
5265 struct e1000_adapter *adapter = netdev->priv;
5266
5267 if (pci_enable_device(pdev)) {
5268 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
5269 return PCI_ERS_RESULT_DISCONNECT;
5270 }
5271 pci_set_master(pdev);
5272
dbf38c94
LV		 5273 pci_enable_wake(pdev, PCI_D3hot, 0);
5274 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 5275
9026729b
AK		 5276 e1000_reset(adapter);
5277 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5278
5279 return PCI_ERS_RESULT_RECOVERED;
5280}
5281
5282/**
5283 * e1000_io_resume - called when traffic can start flowing again.
5284 * @pdev: Pointer to PCI device
5285 *
5286 * This callback is called when the error recovery driver tells us that
5287 * its OK to resume normal operation. Implementation resembles the
5288 * second-half of the e1000_resume routine.
5289 */
5290static void e1000_io_resume(struct pci_dev *pdev)
5291{
5292 struct net_device *netdev = pci_get_drvdata(pdev);
5293 struct e1000_adapter *adapter = netdev->priv;
0fccd0e9
JG		 5294
5295 e1000_init_manageability(adapter);
9026729b
AK		 5296
5297 if (netif_running(netdev)) {
5298 if (e1000_up(adapter)) {
5299 printk("e1000: can't bring device back up after reset\n");
5300 return;
5301 }
5302 }
5303
5304 netif_device_attach(netdev);
5305
0fccd0e9
JG		 5306 /* If the controller is 82573 and f/w is AMT, do not set
5307 * DRV_LOAD until the interface is up. For all other cases,
5308 * let the f/w know that the h/w is now under the control
5309 * of the driver. */
5310 if (adapter->hw.mac_type != e1000_82573 ||
5311 !e1000_check_mng_mode(&adapter->hw))
5312 e1000_get_hw_control(adapter);
9026729b 5313
9026729b
AK		 5314}
5315
1da177e4 5316/* e1000_main.c */
Linux kernel - Deliverables
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