[deliverable/linux.git] / drivers / net / e1000 / e1000_osdep.h

/*******************************************************************************

  
  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
  
  This program is free software; you can redistribute it and/or modify it 
  under the terms of the GNU General Public License as published by the Free 
  Software Foundation; either version 2 of the License, or (at your option) 
  any later version.
  
  This program is distributed in the hope that it will be useful, but WITHOUT 
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
  more details.
  
  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc., 59 
  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  
  The full GNU General Public License is included in this distribution in the
  file called LICENSE.
  
  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* glue for the OS independent part of e1000
 * includes register access macros
 */

#ifndef _E1000_OSDEP_H_
#define _E1000_OSDEP_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/interrupt.h>
#include <linux/sched.h>

#ifndef msec_delay
#define msec_delay(x)	do { if(in_interrupt()) { \
				/* Don't mdelay in interrupt context! */ \
	                	BUG(); \
			} else { \
				msleep(x); \
			} } while (0)

/* Some workarounds require millisecond delays and are run during interrupt
 * context.  Most notably, when establishing link, the phy may need tweaking
 * but cannot process phy register reads/writes faster than millisecond
 * intervals...and we establish link due to a "link status change" interrupt.
 */
#define msec_delay_irq(x) mdelay(x)
#endif

#define PCI_COMMAND_REGISTER   PCI_COMMAND
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE

typedef enum {
#undef FALSE
    FALSE = 0,
#undef TRUE
    TRUE = 1
} boolean_t;

#define MSGOUT(S, A, B)	printk(KERN_DEBUG S "\n", A, B)

#ifdef DBG
#define DEBUGOUT(S)		printk(KERN_DEBUG S "\n")
#define DEBUGOUT1(S, A...)	printk(KERN_DEBUG S "\n", A)
#else
#define DEBUGOUT(S)
#define DEBUGOUT1(S, A...)
#endif

#define DEBUGFUNC(F) DEBUGOUT(F)
#define DEBUGOUT2 DEBUGOUT1
#define DEBUGOUT3 DEBUGOUT2
#define DEBUGOUT7 DEBUGOUT3


#define E1000_WRITE_REG(a, reg, value) ( \
    writel((value), ((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))

#define E1000_READ_REG(a, reg) ( \
    readl((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))

#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
    writel((value), ((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        ((offset) << 2))))

#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
    readl((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        ((offset) << 2)))

#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY

#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
    writew((value), ((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        ((offset) << 1))))

#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
    readw((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        ((offset) << 1)))

#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
    writeb((value), ((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        (offset))))

#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
    readb((a)->hw_addr + \
        (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
        (offset)))

#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)

#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
    writel((value), ((a)->flash_address + reg)))

#define E1000_READ_ICH8_REG(a, reg) ( \
    readl((a)->flash_address + reg))

#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
    writew((value), ((a)->flash_address + reg)))

#define E1000_READ_ICH8_REG16(a, reg) ( \
    readw((a)->flash_address + reg))


#endif /* _E1000_OSDEP_H_ */
Commit	Line	Data
1da177e4 LT	1	/*******************************************************************************
	2
	3
3d41e30a	4	Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4 LT	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms of the GNU General Public License as published by the Free
	8	Software Foundation; either version 2 of the License, or (at your option)
	9	any later version.
	10
	11	This program is distributed in the hope that it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc., 59
	18	Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19
	20	The full GNU General Public License is included in this distribution in the
	21	file called LICENSE.
	22
	23	Contact Information:
	24	Linux NICS <linux.nics@intel.com>
3d41e30a	25	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4 LT	26	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27
	28	*******************************************************************************/
	29
	30
	31	/* glue for the OS independent part of e1000
	32	* includes register access macros
	33	*/
	34
	35	#ifndef _E1000_OSDEP_H_
	36	#define _E1000_OSDEP_H_
	37
	38	#include <linux/types.h>
	39	#include <linux/pci.h>
	40	#include <linux/delay.h>
	41	#include <asm/io.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/sched.h>
	44
	45	#ifndef msec_delay
df25e164 MC	46	#define msec_delay(x) do { if(in_interrupt()) { \
	47	/* Don't mdelay in interrupt context! */ \
	48	BUG(); \
	49	} else { \
	50	msleep(x); \
96838a40	51	} } while (0)
1da177e4 LT	52
	53	/* Some workarounds require millisecond delays and are run during interrupt
	54	* context. Most notably, when establishing link, the phy may need tweaking
	55	* but cannot process phy register reads/writes faster than millisecond
	56	* intervals...and we establish link due to a "link status change" interrupt.
	57	*/
	58	#define msec_delay_irq(x) mdelay(x)
	59	#endif
	60
	61	#define PCI_COMMAND_REGISTER PCI_COMMAND
	62	#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
	63
	64	typedef enum {
	65	#undef FALSE
	66	FALSE = 0,
	67	#undef TRUE
	68	TRUE = 1
	69	} boolean_t;
	70
	71	#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
	72
	73	#ifdef DBG
	74	#define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
	75	#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
	76	#else
	77	#define DEBUGOUT(S)
	78	#define DEBUGOUT1(S, A...)
	79	#endif
	80
	81	#define DEBUGFUNC(F) DEBUGOUT(F)
	82	#define DEBUGOUT2 DEBUGOUT1
	83	#define DEBUGOUT3 DEBUGOUT2
	84	#define DEBUGOUT7 DEBUGOUT3
	85
	86
	87	#define E1000_WRITE_REG(a, reg, value) ( \
	88	writel((value), ((a)->hw_addr + \
	89	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
	90
	91	#define E1000_READ_REG(a, reg) ( \
	92	readl((a)->hw_addr + \
	93	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
	94
	95	#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
	96	writel((value), ((a)->hw_addr + \
	97	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	98	((offset) << 2))))
	99
	100	#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
	101	readl((a)->hw_addr + \
	102	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	103	((offset) << 2)))
	104
2d7edb92 MC	105	#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
	106	#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
	107
	108	#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
	109	writew((value), ((a)->hw_addr + \
	110	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	111	((offset) << 1))))
	112
	113	#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
	114	readw((a)->hw_addr + \
	115	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	116	((offset) << 1)))
	117
	118	#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
	119	writeb((value), ((a)->hw_addr + \
	120	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	121	(offset))))
	122
	123	#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
	124	readb((a)->hw_addr + \
	125	(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
	126	(offset)))
	127
1da177e4 LT	128	#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
1da177e4 LT	129
d37ea5d5 AK	130	#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
	131	writel((value), ((a)->flash_address + reg)))
	132
	133	#define E1000_READ_ICH8_REG(a, reg) ( \
	134	readl((a)->flash_address + reg))
	135
	136	#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
	137	writew((value), ((a)->flash_address + reg)))
	138
	139	#define E1000_READ_ICH8_REG16(a, reg) ( \
	140	readw((a)->flash_address + reg))
	141
	142
1da177e4	143	#endif /* _E1000_OSDEP_H_ */