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1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
4 | Copyright(c) 1999 - 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _E1000_DEFINES_H_ | |
30 | #define _E1000_DEFINES_H_ | |
31 | ||
32 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
33 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
34 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
35 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
36 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
37 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
38 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | |
39 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
40 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
41 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | |
42 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
43 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | |
44 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | |
45 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | |
46 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | |
47 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | |
48 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | |
49 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | |
50 | ||
51 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ | |
52 | #define REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
53 | #define REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
54 | ||
55 | /* Definitions for power management and wakeup registers */ | |
56 | /* Wake Up Control */ | |
57 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ | |
58 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ | |
59 | ||
60 | /* Wake Up Filter Control */ | |
61 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
62 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
63 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
64 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | |
65 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
efb90e43 | 66 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
bc7f75fa AK |
67 | |
68 | /* Extended Device Control */ | |
69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | |
70 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | |
71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | |
72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | |
73 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | |
74 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ | |
75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | |
76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | |
77 | ||
78 | /* Receive Decriptor bit definitions */ | |
79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | |
80 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | |
81 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | |
82 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | |
83 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | |
84 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | |
85 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | |
86 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | |
87 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | |
88 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | |
89 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | |
90 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | |
91 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
92 | ||
93 | #define E1000_RXDEXT_STATERR_CE 0x01000000 | |
94 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | |
95 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | |
96 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | |
97 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | |
98 | ||
99 | /* mask to determine if packets should be dropped due to frame errors */ | |
100 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ | |
101 | E1000_RXD_ERR_CE | \ | |
102 | E1000_RXD_ERR_SE | \ | |
103 | E1000_RXD_ERR_SEQ | \ | |
104 | E1000_RXD_ERR_CXE | \ | |
105 | E1000_RXD_ERR_RXE) | |
106 | ||
107 | /* Same mask, but for extended and packet split descriptors */ | |
108 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | |
109 | E1000_RXDEXT_STATERR_CE | \ | |
110 | E1000_RXDEXT_STATERR_SE | \ | |
111 | E1000_RXDEXT_STATERR_SEQ | \ | |
112 | E1000_RXDEXT_STATERR_CXE | \ | |
113 | E1000_RXDEXT_STATERR_RXE) | |
114 | ||
115 | #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 | |
116 | ||
117 | /* Management Control */ | |
118 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | |
119 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | |
120 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | |
121 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | |
122 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | |
123 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address | |
124 | * filtering */ | |
125 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host | |
126 | * memory */ | |
127 | ||
128 | /* Receive Control */ | |
129 | #define E1000_RCTL_EN 0x00000002 /* enable */ | |
130 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | |
131 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | |
132 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | |
133 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | |
134 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | |
135 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | |
136 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | |
137 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | |
138 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | |
139 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | |
140 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | |
141 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | |
142 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ | |
143 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ | |
144 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ | |
145 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | |
146 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ | |
147 | #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ | |
148 | #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ | |
149 | #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ | |
150 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | |
151 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | |
152 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | |
153 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | |
154 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | |
155 | ||
156 | /* Use byte values for the following shift parameters | |
157 | * Usage: | |
158 | * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & | |
159 | * E1000_PSRCTL_BSIZE0_MASK) | | |
160 | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & | |
161 | * E1000_PSRCTL_BSIZE1_MASK) | | |
162 | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & | |
163 | * E1000_PSRCTL_BSIZE2_MASK) | | |
164 | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; | |
165 | * E1000_PSRCTL_BSIZE3_MASK)) | |
166 | * where value0 = [128..16256], default=256 | |
167 | * value1 = [1024..64512], default=4096 | |
168 | * value2 = [0..64512], default=4096 | |
169 | * value3 = [0..64512], default=0 | |
170 | */ | |
171 | ||
172 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | |
173 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | |
174 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | |
175 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | |
176 | ||
177 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | |
178 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | |
179 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | |
180 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | |
181 | ||
182 | /* SWFW_SYNC Definitions */ | |
183 | #define E1000_SWFW_EEP_SM 0x1 | |
184 | #define E1000_SWFW_PHY0_SM 0x2 | |
185 | #define E1000_SWFW_PHY1_SM 0x4 | |
186 | ||
187 | /* Device Control */ | |
188 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | |
189 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | |
190 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | |
191 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | |
192 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | |
193 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | |
194 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | |
195 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | |
196 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | |
197 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | |
198 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | |
199 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | |
200 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | |
201 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | |
202 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | |
203 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ | |
204 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | |
205 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | |
206 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | |
207 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | |
208 | ||
209 | /* Bit definitions for the Management Data IO (MDIO) and Management Data | |
210 | * Clock (MDC) pins in the Device Control Register. | |
211 | */ | |
212 | ||
213 | /* Device Status */ | |
214 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | |
215 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | |
216 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | |
217 | #define E1000_STATUS_FUNC_SHIFT 2 | |
218 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | |
219 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | |
220 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ | |
221 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | |
222 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | |
223 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ | |
224 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | |
225 | ||
226 | /* Constants used to intrepret the masked PCI-X bus speed. */ | |
227 | ||
228 | #define HALF_DUPLEX 1 | |
229 | #define FULL_DUPLEX 2 | |
230 | ||
231 | ||
232 | #define ADVERTISE_10_HALF 0x0001 | |
233 | #define ADVERTISE_10_FULL 0x0002 | |
234 | #define ADVERTISE_100_HALF 0x0004 | |
235 | #define ADVERTISE_100_FULL 0x0008 | |
236 | #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | |
237 | #define ADVERTISE_1000_FULL 0x0020 | |
238 | ||
239 | /* 1000/H is not supported, nor spec-compliant. */ | |
240 | #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | |
241 | ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ | |
242 | ADVERTISE_1000_FULL) | |
243 | #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | |
244 | ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
245 | #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
246 | #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) | |
247 | #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) | |
248 | ||
249 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX | |
250 | ||
251 | /* LED Control */ | |
252 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F | |
253 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 | |
254 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | |
255 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | |
256 | ||
257 | #define E1000_LEDCTL_MODE_LED_ON 0xE | |
258 | #define E1000_LEDCTL_MODE_LED_OFF 0xF | |
259 | ||
260 | /* Transmit Descriptor bit definitions */ | |
261 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | |
262 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
263 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
264 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
265 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
266 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
267 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
268 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | |
269 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
270 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
271 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | |
272 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
273 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | |
274 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | |
275 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | |
276 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | |
277 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | |
278 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | |
279 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | |
280 | ||
281 | /* Transmit Control */ | |
282 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ | |
283 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | |
284 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | |
285 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | |
286 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | |
287 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | |
288 | ||
289 | /* Transmit Arbitration Count */ | |
290 | ||
291 | /* SerDes Control */ | |
292 | #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 | |
293 | ||
294 | /* Receive Checksum Control */ | |
295 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ | |
296 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | |
297 | ||
298 | /* Header split receive */ | |
299 | #define E1000_RFCTL_EXTEN 0x00008000 | |
300 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | |
301 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | |
302 | ||
303 | /* Collision related configuration parameters */ | |
304 | #define E1000_COLLISION_THRESHOLD 15 | |
305 | #define E1000_CT_SHIFT 4 | |
306 | #define E1000_COLLISION_DISTANCE 63 | |
307 | #define E1000_COLD_SHIFT 12 | |
308 | ||
309 | /* Default values for the transmit IPG register */ | |
310 | #define DEFAULT_82543_TIPG_IPGT_COPPER 8 | |
311 | ||
312 | #define E1000_TIPG_IPGT_MASK 0x000003FF | |
313 | ||
314 | #define DEFAULT_82543_TIPG_IPGR1 8 | |
315 | #define E1000_TIPG_IPGR1_SHIFT 10 | |
316 | ||
317 | #define DEFAULT_82543_TIPG_IPGR2 6 | |
318 | #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 | |
319 | #define E1000_TIPG_IPGR2_SHIFT 20 | |
320 | ||
321 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | |
322 | ||
323 | /* Extended Configuration Control and Size */ | |
324 | #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 | |
325 | #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 | |
326 | #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 | |
327 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 | |
328 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 | |
329 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 | |
330 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 | |
331 | ||
332 | #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 | |
333 | #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 | |
334 | #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 | |
335 | #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 | |
336 | ||
337 | #define E1000_KABGTXD_BGSQLBIAS 0x00050000 | |
338 | ||
339 | /* PBA constants */ | |
340 | #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ | |
341 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | |
342 | ||
343 | #define E1000_PBS_16K E1000_PBA_16K | |
344 | ||
345 | #define IFS_MAX 80 | |
346 | #define IFS_MIN 40 | |
347 | #define IFS_RATIO 4 | |
348 | #define IFS_STEP 10 | |
349 | #define MIN_NUM_XMITS 1000 | |
350 | ||
351 | /* SW Semaphore Register */ | |
352 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | |
353 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | |
354 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ | |
355 | ||
356 | /* Interrupt Cause Read */ | |
357 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | |
358 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | |
359 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | |
360 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | |
361 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | |
362 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | |
363 | ||
364 | /* This defines the bits that are set in the Interrupt Mask | |
365 | * Set/Read Register. Each bit is documented below: | |
366 | * o RXT0 = Receiver Timer Interrupt (ring 0) | |
367 | * o TXDW = Transmit Descriptor Written Back | |
368 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) | |
369 | * o RXSEQ = Receive Sequence Error | |
370 | * o LSC = Link Status Change | |
371 | */ | |
372 | #define IMS_ENABLE_MASK ( \ | |
373 | E1000_IMS_RXT0 | \ | |
374 | E1000_IMS_TXDW | \ | |
375 | E1000_IMS_RXDMT0 | \ | |
376 | E1000_IMS_RXSEQ | \ | |
377 | E1000_IMS_LSC) | |
378 | ||
379 | /* Interrupt Mask Set */ | |
380 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
381 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | |
382 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | |
383 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
384 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | |
385 | ||
386 | /* Interrupt Cause Set */ | |
387 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | |
388 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
389 | ||
390 | /* Transmit Descriptor Control */ | |
391 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ | |
392 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ | |
393 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ | |
394 | #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ | |
395 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. | |
396 | still to be processed. */ | |
397 | ||
398 | /* Flow Control Constants */ | |
399 | #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 | |
400 | #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 | |
401 | #define FLOW_CONTROL_TYPE 0x8808 | |
402 | ||
403 | /* 802.1q VLAN Packet Size */ | |
404 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
405 | ||
406 | /* Receive Address */ | |
407 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address | |
408 | * Registers) holds the directed and multicast addresses that we monitor. | |
409 | * Technically, we have 16 spots. However, we reserve one of these spots | |
410 | * (RAR[15]) for our directed address used by controllers with | |
411 | * manageability enabled, allowing us room for 15 multicast addresses. | |
412 | */ | |
413 | #define E1000_RAR_ENTRIES 15 | |
414 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | |
415 | ||
416 | /* Error Codes */ | |
417 | #define E1000_ERR_NVM 1 | |
418 | #define E1000_ERR_PHY 2 | |
419 | #define E1000_ERR_CONFIG 3 | |
420 | #define E1000_ERR_PARAM 4 | |
421 | #define E1000_ERR_MAC_INIT 5 | |
422 | #define E1000_ERR_PHY_TYPE 6 | |
423 | #define E1000_ERR_RESET 9 | |
424 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | |
425 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | |
426 | #define E1000_BLK_PHY_RESET 12 | |
427 | #define E1000_ERR_SWFW_SYNC 13 | |
428 | #define E1000_NOT_IMPLEMENTED 14 | |
429 | ||
430 | /* Loop limit on how long we wait for auto-negotiation to complete */ | |
431 | #define FIBER_LINK_UP_LIMIT 50 | |
432 | #define COPPER_LINK_UP_LIMIT 10 | |
433 | #define PHY_AUTO_NEG_LIMIT 45 | |
434 | #define PHY_FORCE_LIMIT 20 | |
435 | /* Number of 100 microseconds we wait for PCI Express master disable */ | |
436 | #define MASTER_DISABLE_TIMEOUT 800 | |
437 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | |
438 | #define PHY_CFG_TIMEOUT 100 | |
439 | /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ | |
440 | #define MDIO_OWNERSHIP_TIMEOUT 10 | |
441 | /* Number of milliseconds for NVM auto read done after MAC reset. */ | |
442 | #define AUTO_READ_DONE_TIMEOUT 10 | |
443 | ||
444 | /* Flow Control */ | |
445 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | |
446 | ||
447 | /* Transmit Configuration Word */ | |
448 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | |
449 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ | |
450 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ | |
451 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ | |
452 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ | |
453 | ||
454 | /* Receive Configuration Word */ | |
455 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ | |
456 | #define E1000_RXCW_C 0x20000000 /* Receive config */ | |
457 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | |
458 | ||
459 | /* PCI Express Control */ | |
460 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 | |
461 | #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 | |
462 | #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 | |
463 | #define E1000_GCR_TXD_NO_SNOOP 0x00000008 | |
464 | #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 | |
465 | #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 | |
466 | ||
467 | #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ | |
468 | E1000_GCR_RXDSCW_NO_SNOOP | \ | |
469 | E1000_GCR_RXDSCR_NO_SNOOP | \ | |
470 | E1000_GCR_TXD_NO_SNOOP | \ | |
471 | E1000_GCR_TXDSCW_NO_SNOOP | \ | |
472 | E1000_GCR_TXDSCR_NO_SNOOP) | |
473 | ||
474 | /* PHY Control Register */ | |
475 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | |
476 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | |
477 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | |
478 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | |
479 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | |
480 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | |
481 | #define MII_CR_SPEED_1000 0x0040 | |
482 | #define MII_CR_SPEED_100 0x2000 | |
483 | #define MII_CR_SPEED_10 0x0000 | |
484 | ||
485 | /* PHY Status Register */ | |
486 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | |
487 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | |
488 | ||
489 | /* Autoneg Advertisement Register */ | |
490 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | |
491 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | |
492 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | |
493 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | |
494 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ | |
495 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | |
496 | ||
497 | /* Link Partner Ability Register (Base Page) */ | |
498 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ | |
499 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ | |
500 | ||
501 | /* Autoneg Expansion Register */ | |
502 | ||
503 | /* 1000BASE-T Control Register */ | |
504 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | |
505 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | |
506 | /* 0=DTE device */ | |
507 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ | |
508 | /* 0=Configure PHY as Slave */ | |
509 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | |
510 | /* 0=Automatic Master/Slave config */ | |
511 | ||
512 | /* 1000BASE-T Status Register */ | |
513 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | |
514 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | |
515 | ||
516 | ||
517 | /* PHY 1000 MII Register/Bit Definitions */ | |
518 | /* PHY Registers defined by IEEE */ | |
519 | #define PHY_CONTROL 0x00 /* Control Register */ | |
520 | #define PHY_STATUS 0x01 /* Status Regiser */ | |
521 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | |
522 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | |
523 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | |
524 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | |
525 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | |
526 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | |
527 | ||
528 | /* NVM Control */ | |
529 | #define E1000_EECD_SK 0x00000001 /* NVM Clock */ | |
530 | #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ | |
531 | #define E1000_EECD_DI 0x00000004 /* NVM Data In */ | |
532 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | |
533 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | |
534 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | |
535 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | |
536 | #define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type | |
537 | * (0-small, 1-large) */ | |
538 | #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | |
539 | #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | |
540 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | |
541 | #define E1000_EECD_SIZE_EX_SHIFT 11 | |
542 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | |
543 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | |
544 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | |
545 | ||
546 | #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ | |
547 | #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | |
548 | #define E1000_NVM_RW_REG_START 1 /* Start operation */ | |
549 | #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | |
550 | #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ | |
551 | #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ | |
552 | #define E1000_FLASH_UPDATES 2000 | |
553 | ||
554 | /* NVM Word Offsets */ | |
555 | #define NVM_ID_LED_SETTINGS 0x0004 | |
556 | #define NVM_INIT_CONTROL2_REG 0x000F | |
557 | #define NVM_INIT_CONTROL3_PORT_B 0x0014 | |
558 | #define NVM_INIT_3GIO_3 0x001A | |
559 | #define NVM_INIT_CONTROL3_PORT_A 0x0024 | |
560 | #define NVM_CFG 0x0012 | |
93ca1610 | 561 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 |
bc7f75fa AK |
562 | #define NVM_CHECKSUM_REG 0x003F |
563 | ||
564 | #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ | |
565 | #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ | |
566 | ||
567 | /* Mask bits for fields in Word 0x0f of the NVM */ | |
568 | #define NVM_WORD0F_PAUSE_MASK 0x3000 | |
569 | #define NVM_WORD0F_PAUSE 0x1000 | |
570 | #define NVM_WORD0F_ASM_DIR 0x2000 | |
571 | ||
572 | /* Mask bits for fields in Word 0x1a of the NVM */ | |
573 | #define NVM_WORD1A_ASPM_MASK 0x000C | |
574 | ||
575 | /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ | |
576 | #define NVM_SUM 0xBABA | |
577 | ||
578 | /* PBA (printed board assembly) number words */ | |
579 | #define NVM_PBA_OFFSET_0 8 | |
580 | #define NVM_PBA_OFFSET_1 9 | |
581 | ||
582 | #define NVM_WORD_SIZE_BASE_SHIFT 6 | |
583 | ||
584 | /* NVM Commands - SPI */ | |
585 | #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | |
586 | #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ | |
587 | #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ | |
588 | #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ | |
589 | #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ | |
590 | #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ | |
591 | ||
592 | /* SPI NVM Status Register */ | |
593 | #define NVM_STATUS_RDY_SPI 0x01 | |
594 | ||
595 | /* Word definitions for ID LED Settings */ | |
596 | #define ID_LED_RESERVED_0000 0x0000 | |
597 | #define ID_LED_RESERVED_FFFF 0xFFFF | |
598 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ | |
599 | (ID_LED_OFF1_OFF2 << 8) | \ | |
600 | (ID_LED_DEF1_DEF2 << 4) | \ | |
601 | (ID_LED_DEF1_DEF2)) | |
602 | #define ID_LED_DEF1_DEF2 0x1 | |
603 | #define ID_LED_DEF1_ON2 0x2 | |
604 | #define ID_LED_DEF1_OFF2 0x3 | |
605 | #define ID_LED_ON1_DEF2 0x4 | |
606 | #define ID_LED_ON1_ON2 0x5 | |
607 | #define ID_LED_ON1_OFF2 0x6 | |
608 | #define ID_LED_OFF1_DEF2 0x7 | |
609 | #define ID_LED_OFF1_ON2 0x8 | |
610 | #define ID_LED_OFF1_OFF2 0x9 | |
611 | ||
612 | #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF | |
613 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 | |
614 | #define IGP_LED3_MODE 0x07000000 | |
615 | ||
616 | /* PCI/PCI-X/PCI-EX Config space */ | |
617 | #define PCI_HEADER_TYPE_REGISTER 0x0E | |
618 | #define PCIE_LINK_STATUS 0x12 | |
619 | ||
620 | #define PCI_HEADER_TYPE_MULTIFUNC 0x80 | |
621 | #define PCIE_LINK_WIDTH_MASK 0x3F0 | |
622 | #define PCIE_LINK_WIDTH_SHIFT 4 | |
623 | ||
624 | #define PHY_REVISION_MASK 0xFFFFFFF0 | |
625 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | |
626 | #define MAX_PHY_MULTI_PAGE_REG 0xF | |
627 | ||
628 | /* Bit definitions for valid PHY IDs. */ | |
629 | /* I = Integrated | |
630 | * E = External | |
631 | */ | |
632 | #define M88E1000_E_PHY_ID 0x01410C50 | |
633 | #define M88E1000_I_PHY_ID 0x01410C30 | |
634 | #define M88E1011_I_PHY_ID 0x01410C20 | |
635 | #define IGP01E1000_I_PHY_ID 0x02A80380 | |
636 | #define M88E1111_I_PHY_ID 0x01410CC0 | |
637 | #define GG82563_E_PHY_ID 0x01410CA0 | |
638 | #define IGP03E1000_E_PHY_ID 0x02A80390 | |
639 | #define IFE_E_PHY_ID 0x02A80330 | |
640 | #define IFE_PLUS_E_PHY_ID 0x02A80320 | |
641 | #define IFE_C_E_PHY_ID 0x02A80310 | |
642 | ||
643 | /* M88E1000 Specific Registers */ | |
644 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | |
645 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | |
646 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | |
647 | ||
648 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | |
649 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | |
650 | ||
651 | /* M88E1000 PHY Specific Control Register */ | |
652 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | |
653 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ | |
654 | /* Manual MDI configuration */ | |
655 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | |
656 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, | |
657 | * 100BASE-TX/10BASE-T: | |
658 | * MDI Mode | |
659 | */ | |
660 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled | |
661 | * all speeds. | |
662 | */ | |
663 | /* 1=Enable Extended 10BASE-T distance | |
664 | * (Lower 10BASE-T RX Threshold) | |
665 | * 0=Normal 10BASE-T RX Threshold */ | |
666 | /* 1=5-Bit interface in 100BASE-TX | |
667 | * 0=MII interface in 100BASE-TX */ | |
668 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | |
669 | ||
670 | /* M88E1000 PHY Specific Status Register */ | |
671 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ | |
672 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ | |
673 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ | |
674 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; | |
675 | * 3=110-140M;4=>140M */ | |
676 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | |
677 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | |
678 | ||
679 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 | |
680 | ||
681 | /* Number of times we will attempt to autonegotiate before downshifting if we | |
682 | * are the master */ | |
683 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 | |
684 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 | |
685 | /* Number of times we will attempt to autonegotiate before downshifting if we | |
686 | * are the slave */ | |
687 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 | |
688 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 | |
689 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ | |
690 | ||
691 | /* M88EC018 Rev 2 specific DownShift settings */ | |
692 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 | |
693 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 | |
694 | ||
695 | /* Bits... | |
696 | * 15-5: page | |
697 | * 4-0: register offset | |
698 | */ | |
699 | #define GG82563_PAGE_SHIFT 5 | |
700 | #define GG82563_REG(page, reg) \ | |
701 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) | |
702 | #define GG82563_MIN_ALT_REG 30 | |
703 | ||
704 | /* GG82563 Specific Registers */ | |
705 | #define GG82563_PHY_SPEC_CTRL \ | |
706 | GG82563_REG(0, 16) /* PHY Specific Control */ | |
707 | #define GG82563_PHY_PAGE_SELECT \ | |
708 | GG82563_REG(0, 22) /* Page Select */ | |
709 | #define GG82563_PHY_SPEC_CTRL_2 \ | |
710 | GG82563_REG(0, 26) /* PHY Specific Control 2 */ | |
711 | #define GG82563_PHY_PAGE_SELECT_ALT \ | |
712 | GG82563_REG(0, 29) /* Alternate Page Select */ | |
713 | ||
714 | #define GG82563_PHY_MAC_SPEC_CTRL \ | |
715 | GG82563_REG(2, 21) /* MAC Specific Control Register */ | |
716 | ||
717 | #define GG82563_PHY_DSP_DISTANCE \ | |
718 | GG82563_REG(5, 26) /* DSP Distance */ | |
719 | ||
720 | /* Page 193 - Port Control Registers */ | |
721 | #define GG82563_PHY_KMRN_MODE_CTRL \ | |
722 | GG82563_REG(193, 16) /* Kumeran Mode Control */ | |
723 | #define GG82563_PHY_PWR_MGMT_CTRL \ | |
724 | GG82563_REG(193, 20) /* Power Management Control */ | |
725 | ||
726 | /* Page 194 - KMRN Registers */ | |
727 | #define GG82563_PHY_INBAND_CTRL \ | |
728 | GG82563_REG(194, 18) /* Inband Control */ | |
729 | ||
730 | /* MDI Control */ | |
731 | #define E1000_MDIC_REG_SHIFT 16 | |
732 | #define E1000_MDIC_PHY_SHIFT 21 | |
733 | #define E1000_MDIC_OP_WRITE 0x04000000 | |
734 | #define E1000_MDIC_OP_READ 0x08000000 | |
735 | #define E1000_MDIC_READY 0x10000000 | |
736 | #define E1000_MDIC_ERROR 0x40000000 | |
737 | ||
738 | /* SerDes Control */ | |
739 | #define E1000_GEN_POLL_TIMEOUT 640 | |
740 | ||
741 | #endif /* _E1000_DEFINES_H_ */ |