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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Copper) | |
31 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) | |
32 | */ | |
33 | ||
34 | #include <linux/netdevice.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/pci.h> | |
38 | ||
39 | #include "e1000.h" | |
40 | ||
41 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
42 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
43 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
2d9498f3 | 44 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
bc7f75fa AK |
45 | |
46 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
47 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
48 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
49 | ||
50 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
51 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
2d9498f3 | 52 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
bc7f75fa AK |
53 | |
54 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | |
55 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
56 | ||
57 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
58 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
59 | ||
60 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
61 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ | |
62 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
63 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
64 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
65 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
66 | ||
67 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
68 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 | |
69 | /* 1=Reverse Auto-Negotiation */ | |
70 | ||
71 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
72 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
73 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
74 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
75 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
76 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
77 | ||
78 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
79 | ||
80 | /* DSP Distance Register (Page 5, Register 26) */ | |
81 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M | |
82 | 1 = 50-80M | |
83 | 2 = 80-110M | |
84 | 3 = 110-140M | |
85 | 4 = >140M */ | |
86 | ||
87 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
88 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
89 | ||
2d9498f3 DG |
90 | /* Max number of times Kumeran read/write should be validated */ |
91 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
92 | ||
bc7f75fa AK |
93 | /* Power Management Control Register (Page 193, Register 20) */ |
94 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
95 | /* 1=Enable SERDES Electrical Idle */ | |
96 | ||
97 | /* In-Band Control Register (Page 194, Register 18) */ | |
98 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
99 | ||
ad68076e BA |
100 | /* |
101 | * A table for the GG82563 cable length where the range is defined | |
bc7f75fa AK |
102 | * with a lower bound at "index" and the upper bound at |
103 | * "index + 5". | |
104 | */ | |
105 | static const u16 e1000_gg82563_cable_length_table[] = | |
106 | { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
107 | ||
108 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
109 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
110 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
111 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
112 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
113 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
114 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
115 | ||
116 | /** | |
117 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
118 | * @hw: pointer to the HW structure | |
119 | * | |
120 | * This is a function pointer entry point called by the api module. | |
121 | **/ | |
122 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
123 | { | |
124 | struct e1000_phy_info *phy = &hw->phy; | |
125 | s32 ret_val; | |
126 | ||
318a94d6 | 127 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
128 | phy->type = e1000_phy_none; |
129 | return 0; | |
130 | } | |
131 | ||
132 | phy->addr = 1; | |
133 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
134 | phy->reset_delay_us = 100; | |
135 | phy->type = e1000_phy_gg82563; | |
136 | ||
137 | /* This can only be done after all function pointers are setup. */ | |
138 | ret_val = e1000e_get_phy_id(hw); | |
139 | ||
140 | /* Verify phy id */ | |
141 | if (phy->id != GG82563_E_PHY_ID) | |
142 | return -E1000_ERR_PHY; | |
143 | ||
144 | return ret_val; | |
145 | } | |
146 | ||
147 | /** | |
148 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
149 | * @hw: pointer to the HW structure | |
150 | * | |
151 | * This is a function pointer entry point called by the api module. | |
152 | **/ | |
153 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
154 | { | |
155 | struct e1000_nvm_info *nvm = &hw->nvm; | |
156 | u32 eecd = er32(EECD); | |
157 | u16 size; | |
158 | ||
159 | nvm->opcode_bits = 8; | |
160 | nvm->delay_usec = 1; | |
161 | switch (nvm->override) { | |
162 | case e1000_nvm_override_spi_large: | |
163 | nvm->page_size = 32; | |
164 | nvm->address_bits = 16; | |
165 | break; | |
166 | case e1000_nvm_override_spi_small: | |
167 | nvm->page_size = 8; | |
168 | nvm->address_bits = 8; | |
169 | break; | |
170 | default: | |
171 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
172 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
173 | break; | |
174 | } | |
175 | ||
ad68076e | 176 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
177 | |
178 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
179 | E1000_EECD_SIZE_EX_SHIFT); | |
180 | ||
ad68076e BA |
181 | /* |
182 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
183 | * for setting word_size. |
184 | */ | |
185 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
186 | |
187 | /* EEPROM access above 16k is unsupported */ | |
188 | if (size > 14) | |
189 | size = 14; | |
bc7f75fa AK |
190 | nvm->word_size = 1 << size; |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | /** | |
196 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
197 | * @hw: pointer to the HW structure | |
198 | * | |
199 | * This is a function pointer entry point called by the api module. | |
200 | **/ | |
201 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) | |
202 | { | |
203 | struct e1000_hw *hw = &adapter->hw; | |
204 | struct e1000_mac_info *mac = &hw->mac; | |
205 | struct e1000_mac_operations *func = &mac->ops; | |
206 | ||
207 | /* Set media type */ | |
208 | switch (adapter->pdev->device) { | |
209 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
318a94d6 | 210 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
211 | break; |
212 | default: | |
318a94d6 | 213 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
214 | break; |
215 | } | |
216 | ||
217 | /* Set mta register count */ | |
218 | mac->mta_reg_count = 128; | |
219 | /* Set rar entry count */ | |
220 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
221 | /* Set if manageability features are enabled. */ | |
ad68076e | 222 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
bc7f75fa AK |
223 | |
224 | /* check for link */ | |
318a94d6 | 225 | switch (hw->phy.media_type) { |
bc7f75fa AK |
226 | case e1000_media_type_copper: |
227 | func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; | |
228 | func->check_for_link = e1000e_check_for_copper_link; | |
229 | break; | |
230 | case e1000_media_type_fiber: | |
231 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
232 | func->check_for_link = e1000e_check_for_fiber_link; | |
233 | break; | |
234 | case e1000_media_type_internal_serdes: | |
235 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
236 | func->check_for_link = e1000e_check_for_serdes_link; | |
237 | break; | |
238 | default: | |
239 | return -E1000_ERR_CONFIG; | |
240 | break; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
69e3fd8c | 246 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
247 | { |
248 | struct e1000_hw *hw = &adapter->hw; | |
249 | s32 rc; | |
250 | ||
251 | rc = e1000_init_mac_params_80003es2lan(adapter); | |
252 | if (rc) | |
253 | return rc; | |
254 | ||
255 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
256 | if (rc) | |
257 | return rc; | |
258 | ||
259 | rc = e1000_init_phy_params_80003es2lan(hw); | |
260 | if (rc) | |
261 | return rc; | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | /** | |
267 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
268 | * @hw: pointer to the HW structure | |
269 | * | |
270 | * A wrapper to acquire access rights to the correct PHY. This is a | |
271 | * function pointer entry point called by the api module. | |
272 | **/ | |
273 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
274 | { | |
275 | u16 mask; | |
276 | ||
277 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
2d9498f3 | 278 | mask |= E1000_SWFW_CSR_SM; |
bc7f75fa AK |
279 | |
280 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
281 | } | |
282 | ||
283 | /** | |
284 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
285 | * @hw: pointer to the HW structure | |
286 | * | |
287 | * A wrapper to release access rights to the correct PHY. This is a | |
288 | * function pointer entry point called by the api module. | |
289 | **/ | |
290 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
291 | { | |
292 | u16 mask; | |
293 | ||
294 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
2d9498f3 DG |
295 | mask |= E1000_SWFW_CSR_SM; |
296 | ||
bc7f75fa AK |
297 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
298 | } | |
299 | ||
300 | /** | |
301 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
302 | * @hw: pointer to the HW structure | |
303 | * | |
304 | * Acquire the semaphore to access the EEPROM. This is a function | |
305 | * pointer entry point called by the api module. | |
306 | **/ | |
307 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
308 | { | |
309 | s32 ret_val; | |
310 | ||
311 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
312 | if (ret_val) | |
313 | return ret_val; | |
314 | ||
315 | ret_val = e1000e_acquire_nvm(hw); | |
316 | ||
317 | if (ret_val) | |
318 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
319 | ||
320 | return ret_val; | |
321 | } | |
322 | ||
323 | /** | |
324 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
325 | * @hw: pointer to the HW structure | |
326 | * | |
327 | * Release the semaphore used to access the EEPROM. This is a | |
328 | * function pointer entry point called by the api module. | |
329 | **/ | |
330 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
331 | { | |
332 | e1000e_release_nvm(hw); | |
333 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
334 | } | |
335 | ||
336 | /** | |
337 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
338 | * @hw: pointer to the HW structure | |
339 | * @mask: specifies which semaphore to acquire | |
340 | * | |
341 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
342 | * will also specify which port we're acquiring the lock for. | |
343 | **/ | |
344 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
345 | { | |
346 | u32 swfw_sync; | |
347 | u32 swmask = mask; | |
348 | u32 fwmask = mask << 16; | |
349 | s32 i = 0; | |
350 | s32 timeout = 200; | |
351 | ||
352 | while (i < timeout) { | |
353 | if (e1000e_get_hw_semaphore(hw)) | |
354 | return -E1000_ERR_SWFW_SYNC; | |
355 | ||
356 | swfw_sync = er32(SW_FW_SYNC); | |
357 | if (!(swfw_sync & (fwmask | swmask))) | |
358 | break; | |
359 | ||
ad68076e BA |
360 | /* |
361 | * Firmware currently using resource (fwmask) | |
362 | * or other software thread using resource (swmask) | |
363 | */ | |
bc7f75fa AK |
364 | e1000e_put_hw_semaphore(hw); |
365 | mdelay(5); | |
366 | i++; | |
367 | } | |
368 | ||
369 | if (i == timeout) { | |
370 | hw_dbg(hw, | |
371 | "Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
372 | return -E1000_ERR_SWFW_SYNC; | |
373 | } | |
374 | ||
375 | swfw_sync |= swmask; | |
376 | ew32(SW_FW_SYNC, swfw_sync); | |
377 | ||
378 | e1000e_put_hw_semaphore(hw); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | /** | |
384 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
385 | * @hw: pointer to the HW structure | |
386 | * @mask: specifies which semaphore to acquire | |
387 | * | |
388 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
389 | * will also specify which port we're releasing the lock for. | |
390 | **/ | |
391 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
392 | { | |
393 | u32 swfw_sync; | |
394 | ||
395 | while (e1000e_get_hw_semaphore(hw) != 0); | |
396 | /* Empty */ | |
397 | ||
398 | swfw_sync = er32(SW_FW_SYNC); | |
399 | swfw_sync &= ~mask; | |
400 | ew32(SW_FW_SYNC, swfw_sync); | |
401 | ||
402 | e1000e_put_hw_semaphore(hw); | |
403 | } | |
404 | ||
405 | /** | |
406 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
407 | * @hw: pointer to the HW structure | |
408 | * @offset: offset of the register to read | |
409 | * @data: pointer to the data returned from the operation | |
410 | * | |
411 | * Read the GG82563 PHY register. This is a function pointer entry | |
412 | * point called by the api module. | |
413 | **/ | |
414 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
415 | u32 offset, u16 *data) | |
416 | { | |
417 | s32 ret_val; | |
418 | u32 page_select; | |
419 | u16 temp; | |
420 | ||
2d9498f3 DG |
421 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
422 | if (ret_val) | |
423 | return ret_val; | |
424 | ||
bc7f75fa | 425 | /* Select Configuration Page */ |
2d9498f3 | 426 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 427 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 428 | } else { |
ad68076e BA |
429 | /* |
430 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
431 | * registers 30 and 31 |
432 | */ | |
433 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 434 | } |
bc7f75fa AK |
435 | |
436 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
437 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
438 | if (ret_val) { | |
439 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 440 | return ret_val; |
2d9498f3 | 441 | } |
bc7f75fa | 442 | |
ad68076e BA |
443 | /* |
444 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
445 | * before the device has completed the "Page Select" MDI |
446 | * transaction. So we wait 200us after each MDI command... | |
447 | */ | |
448 | udelay(200); | |
449 | ||
450 | /* ...and verify the command was successful. */ | |
2d9498f3 | 451 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa AK |
452 | |
453 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | |
454 | ret_val = -E1000_ERR_PHY; | |
2d9498f3 | 455 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
456 | return ret_val; |
457 | } | |
458 | ||
459 | udelay(200); | |
460 | ||
2d9498f3 DG |
461 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
462 | data); | |
bc7f75fa AK |
463 | |
464 | udelay(200); | |
2d9498f3 | 465 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
466 | |
467 | return ret_val; | |
468 | } | |
469 | ||
470 | /** | |
471 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
472 | * @hw: pointer to the HW structure | |
473 | * @offset: offset of the register to read | |
474 | * @data: value to write to the register | |
475 | * | |
476 | * Write to the GG82563 PHY register. This is a function pointer entry | |
477 | * point called by the api module. | |
478 | **/ | |
479 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
480 | u32 offset, u16 data) | |
481 | { | |
482 | s32 ret_val; | |
483 | u32 page_select; | |
484 | u16 temp; | |
485 | ||
2d9498f3 DG |
486 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
487 | if (ret_val) | |
488 | return ret_val; | |
489 | ||
bc7f75fa | 490 | /* Select Configuration Page */ |
2d9498f3 | 491 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 492 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 493 | } else { |
ad68076e BA |
494 | /* |
495 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
496 | * registers 30 and 31 |
497 | */ | |
498 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 499 | } |
bc7f75fa AK |
500 | |
501 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
502 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
503 | if (ret_val) { | |
504 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 505 | return ret_val; |
2d9498f3 | 506 | } |
bc7f75fa AK |
507 | |
508 | ||
ad68076e BA |
509 | /* |
510 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
511 | * before the device has completed the "Page Select" MDI |
512 | * transaction. So we wait 200us after each MDI command... | |
513 | */ | |
514 | udelay(200); | |
515 | ||
516 | /* ...and verify the command was successful. */ | |
2d9498f3 | 517 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa | 518 | |
2d9498f3 DG |
519 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
520 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 521 | return -E1000_ERR_PHY; |
2d9498f3 | 522 | } |
bc7f75fa AK |
523 | |
524 | udelay(200); | |
525 | ||
2d9498f3 DG |
526 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
527 | data); | |
bc7f75fa AK |
528 | |
529 | udelay(200); | |
2d9498f3 | 530 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
531 | |
532 | return ret_val; | |
533 | } | |
534 | ||
535 | /** | |
536 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
537 | * @hw: pointer to the HW structure | |
538 | * @offset: offset of the register to read | |
539 | * @words: number of words to write | |
540 | * @data: buffer of data to write to the NVM | |
541 | * | |
542 | * Write "words" of data to the ESB2 NVM. This is a function | |
543 | * pointer entry point called by the api module. | |
544 | **/ | |
545 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
546 | u16 words, u16 *data) | |
547 | { | |
548 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
549 | } | |
550 | ||
551 | /** | |
552 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
553 | * @hw: pointer to the HW structure | |
554 | * | |
555 | * Wait a specific amount of time for manageability processes to complete. | |
556 | * This is a function pointer entry point called by the phy module. | |
557 | **/ | |
558 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
559 | { | |
560 | s32 timeout = PHY_CFG_TIMEOUT; | |
561 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
562 | ||
563 | if (hw->bus.func == 1) | |
564 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
565 | ||
566 | while (timeout) { | |
567 | if (er32(EEMNGCTL) & mask) | |
568 | break; | |
569 | msleep(1); | |
570 | timeout--; | |
571 | } | |
572 | if (!timeout) { | |
573 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
574 | return -E1000_ERR_RESET; | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | /** | |
581 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
582 | * @hw: pointer to the HW structure | |
583 | * | |
584 | * Force the speed and duplex settings onto the PHY. This is a | |
585 | * function pointer entry point called by the phy module. | |
586 | **/ | |
587 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
588 | { | |
589 | s32 ret_val; | |
590 | u16 phy_data; | |
591 | bool link; | |
592 | ||
ad68076e BA |
593 | /* |
594 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
595 | * forced whenever speed and duplex are forced. |
596 | */ | |
597 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
598 | if (ret_val) | |
599 | return ret_val; | |
600 | ||
601 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
602 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
603 | if (ret_val) | |
604 | return ret_val; | |
605 | ||
606 | hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); | |
607 | ||
608 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
609 | if (ret_val) | |
610 | return ret_val; | |
611 | ||
612 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
613 | ||
614 | /* Reset the phy to commit changes. */ | |
615 | phy_data |= MII_CR_RESET; | |
616 | ||
617 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
618 | if (ret_val) | |
619 | return ret_val; | |
620 | ||
621 | udelay(1); | |
622 | ||
318a94d6 | 623 | if (hw->phy.autoneg_wait_to_complete) { |
bc7f75fa AK |
624 | hw_dbg(hw, "Waiting for forced speed/duplex link " |
625 | "on GG82563 phy.\n"); | |
626 | ||
627 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
628 | 100000, &link); | |
629 | if (ret_val) | |
630 | return ret_val; | |
631 | ||
632 | if (!link) { | |
ad68076e BA |
633 | /* |
634 | * We didn't get link. | |
bc7f75fa AK |
635 | * Reset the DSP and cross our fingers. |
636 | */ | |
637 | ret_val = e1000e_phy_reset_dsp(hw); | |
638 | if (ret_val) | |
639 | return ret_val; | |
640 | } | |
641 | ||
642 | /* Try once more */ | |
643 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
644 | 100000, &link); | |
645 | if (ret_val) | |
646 | return ret_val; | |
647 | } | |
648 | ||
649 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
650 | if (ret_val) | |
651 | return ret_val; | |
652 | ||
ad68076e BA |
653 | /* |
654 | * Resetting the phy means we need to verify the TX_CLK corresponds | |
bc7f75fa AK |
655 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
656 | */ | |
657 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
658 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
659 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
660 | else | |
661 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
662 | ||
ad68076e BA |
663 | /* |
664 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
665 | * duplex. |
666 | */ | |
667 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
668 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
669 | ||
670 | return ret_val; | |
671 | } | |
672 | ||
673 | /** | |
674 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
675 | * @hw: pointer to the HW structure | |
676 | * | |
677 | * Find the approximate cable length as measured by the GG82563 PHY. | |
678 | * This is a function pointer entry point called by the phy module. | |
679 | **/ | |
680 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
681 | { | |
682 | struct e1000_phy_info *phy = &hw->phy; | |
683 | s32 ret_val; | |
684 | u16 phy_data; | |
685 | u16 index; | |
686 | ||
687 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
688 | if (ret_val) | |
689 | return ret_val; | |
690 | ||
691 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
692 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; | |
693 | phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; | |
694 | ||
695 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | /** | |
701 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
702 | * @hw: pointer to the HW structure | |
703 | * @speed: pointer to speed buffer | |
704 | * @duplex: pointer to duplex buffer | |
705 | * | |
706 | * Retrieve the current speed and duplex configuration. | |
707 | * This is a function pointer entry point called by the api module. | |
708 | **/ | |
709 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
710 | u16 *duplex) | |
711 | { | |
712 | s32 ret_val; | |
713 | ||
318a94d6 | 714 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
715 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
716 | speed, | |
717 | duplex); | |
718 | if (ret_val) | |
719 | return ret_val; | |
720 | if (*speed == SPEED_1000) | |
721 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
722 | else | |
723 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, | |
724 | *duplex); | |
725 | } else { | |
726 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
727 | speed, | |
728 | duplex); | |
729 | } | |
730 | ||
731 | return ret_val; | |
732 | } | |
733 | ||
734 | /** | |
735 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
736 | * @hw: pointer to the HW structure | |
737 | * | |
738 | * Perform a global reset to the ESB2 controller. | |
739 | * This is a function pointer entry point called by the api module. | |
740 | **/ | |
741 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
742 | { | |
743 | u32 ctrl; | |
744 | u32 icr; | |
745 | s32 ret_val; | |
746 | ||
ad68076e BA |
747 | /* |
748 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
749 | * on the last TLP read/write transaction when MAC is reset. |
750 | */ | |
751 | ret_val = e1000e_disable_pcie_master(hw); | |
752 | if (ret_val) | |
753 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
754 | ||
755 | hw_dbg(hw, "Masking off all interrupts\n"); | |
756 | ew32(IMC, 0xffffffff); | |
757 | ||
758 | ew32(RCTL, 0); | |
759 | ew32(TCTL, E1000_TCTL_PSP); | |
760 | e1e_flush(); | |
761 | ||
762 | msleep(10); | |
763 | ||
764 | ctrl = er32(CTRL); | |
765 | ||
766 | hw_dbg(hw, "Issuing a global reset to MAC\n"); | |
767 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
768 | ||
769 | ret_val = e1000e_get_auto_rd_done(hw); | |
770 | if (ret_val) | |
771 | /* We don't want to continue accessing MAC registers. */ | |
772 | return ret_val; | |
773 | ||
774 | /* Clear any pending interrupt events. */ | |
775 | ew32(IMC, 0xffffffff); | |
776 | icr = er32(ICR); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | /** | |
782 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
783 | * @hw: pointer to the HW structure | |
784 | * | |
785 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
786 | * This is a function pointer entry point called by the api module. | |
787 | **/ | |
788 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
789 | { | |
790 | struct e1000_mac_info *mac = &hw->mac; | |
791 | u32 reg_data; | |
792 | s32 ret_val; | |
793 | u16 i; | |
794 | ||
795 | e1000_initialize_hw_bits_80003es2lan(hw); | |
796 | ||
797 | /* Initialize identification LED */ | |
798 | ret_val = e1000e_id_led_init(hw); | |
799 | if (ret_val) { | |
800 | hw_dbg(hw, "Error initializing identification LED\n"); | |
801 | return ret_val; | |
802 | } | |
803 | ||
804 | /* Disabling VLAN filtering */ | |
805 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
806 | e1000e_clear_vfta(hw); | |
807 | ||
808 | /* Setup the receive address. */ | |
809 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
810 | ||
811 | /* Zero out the Multicast HASH table */ | |
812 | hw_dbg(hw, "Zeroing the MTA\n"); | |
813 | for (i = 0; i < mac->mta_reg_count; i++) | |
814 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
815 | ||
816 | /* Setup link and flow control */ | |
817 | ret_val = e1000e_setup_link(hw); | |
818 | ||
819 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 820 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
821 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
822 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 823 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
824 | |
825 | /* ...for both queues. */ | |
e9ec2c0f | 826 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
827 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
828 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 829 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
830 | |
831 | /* Enable retransmit on late collisions */ | |
832 | reg_data = er32(TCTL); | |
833 | reg_data |= E1000_TCTL_RTLC; | |
834 | ew32(TCTL, reg_data); | |
835 | ||
836 | /* Configure Gigabit Carry Extend Padding */ | |
837 | reg_data = er32(TCTL_EXT); | |
838 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
839 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
840 | ew32(TCTL_EXT, reg_data); | |
841 | ||
842 | /* Configure Transmit Inter-Packet Gap */ | |
843 | reg_data = er32(TIPG); | |
844 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
845 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
846 | ew32(TIPG, reg_data); | |
847 | ||
848 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
849 | reg_data &= ~0x00100000; | |
850 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
851 | ||
ad68076e BA |
852 | /* |
853 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
854 | * important that we do this after we have tried to establish link |
855 | * because the symbol error count will increment wildly if there | |
856 | * is no link. | |
857 | */ | |
858 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
859 | ||
860 | return ret_val; | |
861 | } | |
862 | ||
863 | /** | |
864 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
865 | * @hw: pointer to the HW structure | |
866 | * | |
867 | * Initializes required hardware-dependent bits needed for normal operation. | |
868 | **/ | |
869 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
870 | { | |
871 | u32 reg; | |
872 | ||
873 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 874 | reg = er32(TXDCTL(0)); |
bc7f75fa | 875 | reg |= (1 << 22); |
e9ec2c0f | 876 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
877 | |
878 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 879 | reg = er32(TXDCTL(1)); |
bc7f75fa | 880 | reg |= (1 << 22); |
e9ec2c0f | 881 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
882 | |
883 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 884 | reg = er32(TARC(0)); |
bc7f75fa | 885 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 886 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 887 | reg &= ~(1 << 20); |
e9ec2c0f | 888 | ew32(TARC(0), reg); |
bc7f75fa AK |
889 | |
890 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 891 | reg = er32(TARC(1)); |
bc7f75fa AK |
892 | if (er32(TCTL) & E1000_TCTL_MULR) |
893 | reg &= ~(1 << 28); | |
894 | else | |
895 | reg |= (1 << 28); | |
e9ec2c0f | 896 | ew32(TARC(1), reg); |
bc7f75fa AK |
897 | } |
898 | ||
899 | /** | |
900 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
901 | * @hw: pointer to the HW structure | |
902 | * | |
903 | * Setup some GG82563 PHY registers for obtaining link | |
904 | **/ | |
905 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
906 | { | |
907 | struct e1000_phy_info *phy = &hw->phy; | |
908 | s32 ret_val; | |
909 | u32 ctrl_ext; | |
2d9498f3 DG |
910 | u32 i = 0; |
911 | u16 data, data2; | |
bc7f75fa | 912 | |
2d9498f3 | 913 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
914 | if (ret_val) |
915 | return ret_val; | |
916 | ||
917 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
918 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
919 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
920 | ||
2d9498f3 | 921 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
922 | if (ret_val) |
923 | return ret_val; | |
924 | ||
ad68076e BA |
925 | /* |
926 | * Options: | |
bc7f75fa AK |
927 | * MDI/MDI-X = 0 (default) |
928 | * 0 - Auto for all speeds | |
929 | * 1 - MDI mode | |
930 | * 2 - MDI-X mode | |
931 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
932 | */ | |
933 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
934 | if (ret_val) | |
935 | return ret_val; | |
936 | ||
937 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
938 | ||
939 | switch (phy->mdix) { | |
940 | case 1: | |
941 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
942 | break; | |
943 | case 2: | |
944 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
945 | break; | |
946 | case 0: | |
947 | default: | |
948 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
949 | break; | |
950 | } | |
951 | ||
ad68076e BA |
952 | /* |
953 | * Options: | |
bc7f75fa AK |
954 | * disable_polarity_correction = 0 (default) |
955 | * Automatic Correction for Reversed Cable Polarity | |
956 | * 0 - Disabled | |
957 | * 1 - Enabled | |
958 | */ | |
959 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
960 | if (phy->disable_polarity_correction) | |
961 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
962 | ||
963 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
964 | if (ret_val) | |
965 | return ret_val; | |
966 | ||
967 | /* SW Reset the PHY so all changes take effect */ | |
968 | ret_val = e1000e_commit_phy(hw); | |
969 | if (ret_val) { | |
970 | hw_dbg(hw, "Error Resetting the PHY\n"); | |
971 | return ret_val; | |
972 | } | |
973 | ||
ad68076e BA |
974 | /* Bypass Rx and Tx FIFO's */ |
975 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
976 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | | |
bc7f75fa AK |
977 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
978 | if (ret_val) | |
979 | return ret_val; | |
980 | ||
2d9498f3 DG |
981 | ret_val = e1000e_read_kmrn_reg(hw, |
982 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, | |
983 | &data); | |
984 | if (ret_val) | |
985 | return ret_val; | |
986 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
987 | ret_val = e1000e_write_kmrn_reg(hw, | |
988 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, | |
989 | data); | |
990 | if (ret_val) | |
991 | return ret_val; | |
992 | ||
bc7f75fa AK |
993 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
994 | if (ret_val) | |
995 | return ret_val; | |
996 | ||
997 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
998 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
999 | if (ret_val) | |
1000 | return ret_val; | |
1001 | ||
1002 | ctrl_ext = er32(CTRL_EXT); | |
1003 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1004 | ew32(CTRL_EXT, ctrl_ext); | |
1005 | ||
1006 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
1007 | if (ret_val) | |
1008 | return ret_val; | |
1009 | ||
ad68076e BA |
1010 | /* |
1011 | * Do not init these registers when the HW is in IAMT mode, since the | |
bc7f75fa AK |
1012 | * firmware will have already initialized them. We only initialize |
1013 | * them if the HW is not in IAMT mode. | |
1014 | */ | |
1015 | if (!e1000e_check_mng_mode(hw)) { | |
1016 | /* Enable Electrical Idle on the PHY */ | |
1017 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1018 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1019 | if (ret_val) | |
1020 | return ret_val; | |
1021 | ||
2d9498f3 DG |
1022 | do { |
1023 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1024 | &data); | |
1025 | if (ret_val) | |
1026 | return ret_val; | |
1027 | ||
1028 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1029 | &data2); | |
1030 | if (ret_val) | |
1031 | return ret_val; | |
1032 | i++; | |
1033 | } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1034 | |
1035 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1036 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1037 | if (ret_val) | |
1038 | return ret_val; | |
1039 | } | |
1040 | ||
ad68076e BA |
1041 | /* |
1042 | * Workaround: Disable padding in Kumeran interface in the MAC | |
bc7f75fa AK |
1043 | * and in the PHY to avoid CRC errors. |
1044 | */ | |
1045 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1046 | if (ret_val) | |
1047 | return ret_val; | |
1048 | ||
1049 | data |= GG82563_ICR_DIS_PADDING; | |
1050 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1051 | if (ret_val) | |
1052 | return ret_val; | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | /** | |
1058 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1059 | * @hw: pointer to the HW structure | |
1060 | * | |
1061 | * Essentially a wrapper for setting up all things "copper" related. | |
1062 | * This is a function pointer entry point called by the mac module. | |
1063 | **/ | |
1064 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1065 | { | |
1066 | u32 ctrl; | |
1067 | s32 ret_val; | |
1068 | u16 reg_data; | |
1069 | ||
1070 | ctrl = er32(CTRL); | |
1071 | ctrl |= E1000_CTRL_SLU; | |
1072 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1073 | ew32(CTRL, ctrl); | |
1074 | ||
ad68076e BA |
1075 | /* |
1076 | * Set the mac to wait the maximum time between each | |
bc7f75fa | 1077 | * iteration and increase the max iterations when |
ad68076e BA |
1078 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1079 | */ | |
bc7f75fa AK |
1080 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
1081 | if (ret_val) | |
1082 | return ret_val; | |
1083 | ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
1084 | if (ret_val) | |
1085 | return ret_val; | |
1086 | reg_data |= 0x3F; | |
1087 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
1088 | if (ret_val) | |
1089 | return ret_val; | |
1090 | ret_val = e1000e_read_kmrn_reg(hw, | |
1091 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
1092 | ®_data); | |
1093 | if (ret_val) | |
1094 | return ret_val; | |
1095 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
ad68076e BA |
1096 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
1097 | reg_data); | |
bc7f75fa AK |
1098 | if (ret_val) |
1099 | return ret_val; | |
1100 | ||
1101 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1102 | if (ret_val) | |
1103 | return ret_val; | |
1104 | ||
1105 | ret_val = e1000e_setup_copper_link(hw); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | /** | |
1111 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1112 | * @hw: pointer to the HW structure | |
1113 | * @duplex: current duplex setting | |
1114 | * | |
1115 | * Configure the KMRN interface by applying last minute quirks for | |
1116 | * 10/100 operation. | |
1117 | **/ | |
1118 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1119 | { | |
1120 | s32 ret_val; | |
1121 | u32 tipg; | |
2d9498f3 DG |
1122 | u32 i = 0; |
1123 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1124 | |
1125 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
ad68076e BA |
1126 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
1127 | reg_data); | |
bc7f75fa AK |
1128 | if (ret_val) |
1129 | return ret_val; | |
1130 | ||
1131 | /* Configure Transmit Inter-Packet Gap */ | |
1132 | tipg = er32(TIPG); | |
1133 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1134 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1135 | ew32(TIPG, tipg); | |
1136 | ||
2d9498f3 DG |
1137 | do { |
1138 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1139 | if (ret_val) | |
1140 | return ret_val; | |
1141 | ||
1142 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1143 | if (ret_val) | |
1144 | return ret_val; | |
1145 | i++; | |
1146 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1147 | |
1148 | if (duplex == HALF_DUPLEX) | |
1149 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1150 | else | |
1151 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1152 | ||
1153 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /** | |
1159 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1160 | * @hw: pointer to the HW structure | |
1161 | * | |
1162 | * Configure the KMRN interface by applying last minute quirks for | |
1163 | * gigabit operation. | |
1164 | **/ | |
1165 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1166 | { | |
1167 | s32 ret_val; | |
2d9498f3 | 1168 | u16 reg_data, reg_data2; |
bc7f75fa | 1169 | u32 tipg; |
2d9498f3 | 1170 | u32 i = 0; |
bc7f75fa AK |
1171 | |
1172 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
ad68076e BA |
1173 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
1174 | reg_data); | |
bc7f75fa AK |
1175 | if (ret_val) |
1176 | return ret_val; | |
1177 | ||
1178 | /* Configure Transmit Inter-Packet Gap */ | |
1179 | tipg = er32(TIPG); | |
1180 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1181 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1182 | ew32(TIPG, tipg); | |
1183 | ||
2d9498f3 DG |
1184 | do { |
1185 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1186 | if (ret_val) | |
1187 | return ret_val; | |
1188 | ||
1189 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1190 | if (ret_val) | |
1191 | return ret_val; | |
1192 | i++; | |
1193 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1194 | |
1195 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1196 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1197 | ||
1198 | return ret_val; | |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1203 | * @hw: pointer to the HW structure | |
1204 | * | |
1205 | * Clears the hardware counters by reading the counter registers. | |
1206 | **/ | |
1207 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1208 | { | |
1209 | u32 temp; | |
1210 | ||
1211 | e1000e_clear_hw_cntrs_base(hw); | |
1212 | ||
1213 | temp = er32(PRC64); | |
1214 | temp = er32(PRC127); | |
1215 | temp = er32(PRC255); | |
1216 | temp = er32(PRC511); | |
1217 | temp = er32(PRC1023); | |
1218 | temp = er32(PRC1522); | |
1219 | temp = er32(PTC64); | |
1220 | temp = er32(PTC127); | |
1221 | temp = er32(PTC255); | |
1222 | temp = er32(PTC511); | |
1223 | temp = er32(PTC1023); | |
1224 | temp = er32(PTC1522); | |
1225 | ||
1226 | temp = er32(ALGNERRC); | |
1227 | temp = er32(RXERRC); | |
1228 | temp = er32(TNCRS); | |
1229 | temp = er32(CEXTERR); | |
1230 | temp = er32(TSCTC); | |
1231 | temp = er32(TSCTFC); | |
1232 | ||
1233 | temp = er32(MGTPRC); | |
1234 | temp = er32(MGTPDC); | |
1235 | temp = er32(MGTPTC); | |
1236 | ||
1237 | temp = er32(IAC); | |
1238 | temp = er32(ICRXOC); | |
1239 | ||
1240 | temp = er32(ICRXPTC); | |
1241 | temp = er32(ICRXATC); | |
1242 | temp = er32(ICTXPTC); | |
1243 | temp = er32(ICTXATC); | |
1244 | temp = er32(ICTXQEC); | |
1245 | temp = er32(ICTXQMTC); | |
1246 | temp = er32(ICRXDMTC); | |
1247 | } | |
1248 | ||
1249 | static struct e1000_mac_operations es2_mac_ops = { | |
4662e82b | 1250 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1251 | /* check_for_link dependent on media type */ |
1252 | .cleanup_led = e1000e_cleanup_led_generic, | |
1253 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1254 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1255 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, | |
1256 | .led_on = e1000e_led_on_generic, | |
1257 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1258 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
1259 | .reset_hw = e1000_reset_hw_80003es2lan, |
1260 | .init_hw = e1000_init_hw_80003es2lan, | |
1261 | .setup_link = e1000e_setup_link, | |
1262 | /* setup_physical_interface dependent on media type */ | |
1263 | }; | |
1264 | ||
1265 | static struct e1000_phy_operations es2_phy_ops = { | |
1266 | .acquire_phy = e1000_acquire_phy_80003es2lan, | |
1267 | .check_reset_block = e1000e_check_reset_block_generic, | |
1268 | .commit_phy = e1000e_phy_sw_reset, | |
1269 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, | |
1270 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1271 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
1272 | .get_phy_info = e1000e_get_phy_info_m88, | |
1273 | .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
1274 | .release_phy = e1000_release_phy_80003es2lan, | |
1275 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1276 | .set_d0_lplu_state = NULL, | |
1277 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1278 | .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, | |
1279 | }; | |
1280 | ||
1281 | static struct e1000_nvm_operations es2_nvm_ops = { | |
1282 | .acquire_nvm = e1000_acquire_nvm_80003es2lan, | |
1283 | .read_nvm = e1000e_read_nvm_eerd, | |
1284 | .release_nvm = e1000_release_nvm_80003es2lan, | |
1285 | .update_nvm = e1000e_update_nvm_checksum_generic, | |
1286 | .valid_led_default = e1000e_valid_led_default, | |
1287 | .validate_nvm = e1000e_validate_nvm_checksum_generic, | |
1288 | .write_nvm = e1000_write_nvm_80003es2lan, | |
1289 | }; | |
1290 | ||
1291 | struct e1000_info e1000_es2_info = { | |
1292 | .mac = e1000_80003es2lan, | |
1293 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1294 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1295 | | FLAG_HAS_WOL |
1296 | | FLAG_APME_IN_CTRL3 | |
1297 | | FLAG_RX_CSUM_ENABLED | |
1298 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1299 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1300 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1301 | | FLAG_APME_CHECK_PORT_B | |
1302 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
1303 | | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, | |
1304 | .pba = 38, | |
69e3fd8c | 1305 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1306 | .mac_ops = &es2_mac_ops, |
1307 | .phy_ops = &es2_phy_ops, | |
1308 | .nvm_ops = &es2_nvm_ops, | |
1309 | }; | |
1310 |