Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82562G-2 10/100 Network Connection | |
31 | * 82562GT 10/100 Network Connection | |
32 | * 82562GT-2 10/100 Network Connection | |
33 | * 82562V 10/100 Network Connection | |
34 | * 82562V-2 10/100 Network Connection | |
35 | * 82566DC-2 Gigabit Network Connection | |
36 | * 82566DC Gigabit Network Connection | |
37 | * 82566DM-2 Gigabit Network Connection | |
38 | * 82566DM Gigabit Network Connection | |
39 | * 82566MC Gigabit Network Connection | |
40 | * 82566MM Gigabit Network Connection | |
97ac8cae BA |
41 | * 82567LM Gigabit Network Connection |
42 | * 82567LF Gigabit Network Connection | |
43 | * 82567LM-2 Gigabit Network Connection | |
44 | * 82567LF-2 Gigabit Network Connection | |
45 | * 82567V-2 Gigabit Network Connection | |
46 | * 82562GT-3 10/100 Network Connection | |
bc7f75fa AK |
47 | */ |
48 | ||
49 | #include <linux/netdevice.h> | |
50 | #include <linux/ethtool.h> | |
51 | #include <linux/delay.h> | |
52 | #include <linux/pci.h> | |
53 | ||
54 | #include "e1000.h" | |
55 | ||
56 | #define ICH_FLASH_GFPREG 0x0000 | |
57 | #define ICH_FLASH_HSFSTS 0x0004 | |
58 | #define ICH_FLASH_HSFCTL 0x0006 | |
59 | #define ICH_FLASH_FADDR 0x0008 | |
60 | #define ICH_FLASH_FDATA0 0x0010 | |
4a770358 | 61 | #define ICH_FLASH_PR0 0x0074 |
bc7f75fa AK |
62 | |
63 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 | |
64 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 | |
65 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 | |
66 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
67 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
68 | ||
69 | #define ICH_CYCLE_READ 0 | |
70 | #define ICH_CYCLE_WRITE 2 | |
71 | #define ICH_CYCLE_ERASE 3 | |
72 | ||
73 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
74 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
75 | ||
76 | #define ICH_FLASH_SEG_SIZE_256 256 | |
77 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
78 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
79 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
80 | ||
81 | ||
82 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
83 | ||
84 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
85 | ||
86 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | |
87 | (ID_LED_DEF1_OFF2 << 8) | \ | |
88 | (ID_LED_DEF1_ON2 << 4) | \ | |
89 | (ID_LED_DEF1_DEF2)) | |
90 | ||
91 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
92 | #define E1000_ICH_NVM_SIG_MASK 0xC000 | |
93 | ||
94 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
95 | ||
96 | #define E1000_FEXTNVM_SW_CONFIG 1 | |
97 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ | |
98 | ||
99 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL | |
100 | ||
101 | #define E1000_ICH_RAR_ENTRIES 7 | |
102 | ||
103 | #define PHY_PAGE_SHIFT 5 | |
104 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
105 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
106 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
107 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
108 | ||
109 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
110 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
111 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
112 | ||
113 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ | |
114 | /* Offset 04h HSFSTS */ | |
115 | union ich8_hws_flash_status { | |
116 | struct ich8_hsfsts { | |
117 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | |
118 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | |
119 | u16 dael :1; /* bit 2 Direct Access error Log */ | |
120 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ | |
121 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ | |
122 | u16 reserved1 :2; /* bit 13:6 Reserved */ | |
123 | u16 reserved2 :6; /* bit 13:6 Reserved */ | |
124 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | |
125 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ | |
126 | } hsf_status; | |
127 | u16 regval; | |
128 | }; | |
129 | ||
130 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
131 | /* Offset 06h FLCTL */ | |
132 | union ich8_hws_flash_ctrl { | |
133 | struct ich8_hsflctl { | |
134 | u16 flcgo :1; /* 0 Flash Cycle Go */ | |
135 | u16 flcycle :2; /* 2:1 Flash Cycle */ | |
136 | u16 reserved :5; /* 7:3 Reserved */ | |
137 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | |
138 | u16 flockdn :6; /* 15:10 Reserved */ | |
139 | } hsf_ctrl; | |
140 | u16 regval; | |
141 | }; | |
142 | ||
143 | /* ICH Flash Region Access Permissions */ | |
144 | union ich8_hws_flash_regacc { | |
145 | struct ich8_flracc { | |
146 | u32 grra :8; /* 0:7 GbE region Read Access */ | |
147 | u32 grwa :8; /* 8:15 GbE region Write Access */ | |
148 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | |
149 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | |
150 | } hsf_flregacc; | |
151 | u16 regval; | |
152 | }; | |
153 | ||
4a770358 BA |
154 | /* ICH Flash Protected Region */ |
155 | union ich8_flash_protected_range { | |
156 | struct ich8_pr { | |
157 | u32 base:13; /* 0:12 Protected Range Base */ | |
158 | u32 reserved1:2; /* 13:14 Reserved */ | |
159 | u32 rpe:1; /* 15 Read Protection Enable */ | |
160 | u32 limit:13; /* 16:28 Protected Range Limit */ | |
161 | u32 reserved2:2; /* 29:30 Reserved */ | |
162 | u32 wpe:1; /* 31 Write Protection Enable */ | |
163 | } range; | |
164 | u32 regval; | |
165 | }; | |
166 | ||
bc7f75fa AK |
167 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
168 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
169 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
170 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); | |
171 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | |
172 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
173 | u32 offset, u8 byte); | |
174 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
175 | u16 *data); | |
176 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
177 | u8 size, u16 *data); | |
178 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | |
179 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
180 | ||
181 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
182 | { | |
183 | return readw(hw->flash_address + reg); | |
184 | } | |
185 | ||
186 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
187 | { | |
188 | return readl(hw->flash_address + reg); | |
189 | } | |
190 | ||
191 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
192 | { | |
193 | writew(val, hw->flash_address + reg); | |
194 | } | |
195 | ||
196 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
197 | { | |
198 | writel(val, hw->flash_address + reg); | |
199 | } | |
200 | ||
201 | #define er16flash(reg) __er16flash(hw, (reg)) | |
202 | #define er32flash(reg) __er32flash(hw, (reg)) | |
203 | #define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) | |
204 | #define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) | |
205 | ||
206 | /** | |
207 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
208 | * @hw: pointer to the HW structure | |
209 | * | |
210 | * Initialize family-specific PHY parameters and function pointers. | |
211 | **/ | |
212 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
213 | { | |
214 | struct e1000_phy_info *phy = &hw->phy; | |
215 | s32 ret_val; | |
216 | u16 i = 0; | |
217 | ||
218 | phy->addr = 1; | |
219 | phy->reset_delay_us = 100; | |
220 | ||
97ac8cae BA |
221 | /* |
222 | * We may need to do this twice - once for IGP and if that fails, | |
223 | * we'll set BM func pointers and try again | |
224 | */ | |
225 | ret_val = e1000e_determine_phy_address(hw); | |
226 | if (ret_val) { | |
227 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
228 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
229 | ret_val = e1000e_determine_phy_address(hw); | |
230 | if (ret_val) | |
231 | return ret_val; | |
232 | } | |
233 | ||
bc7f75fa AK |
234 | phy->id = 0; |
235 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
236 | (i++ < 100)) { | |
237 | msleep(1); | |
238 | ret_val = e1000e_get_phy_id(hw); | |
239 | if (ret_val) | |
240 | return ret_val; | |
241 | } | |
242 | ||
243 | /* Verify phy id */ | |
244 | switch (phy->id) { | |
245 | case IGP03E1000_E_PHY_ID: | |
246 | phy->type = e1000_phy_igp_3; | |
247 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
248 | break; | |
249 | case IFE_E_PHY_ID: | |
250 | case IFE_PLUS_E_PHY_ID: | |
251 | case IFE_C_E_PHY_ID: | |
252 | phy->type = e1000_phy_ife; | |
253 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
254 | break; | |
97ac8cae BA |
255 | case BME1000_E_PHY_ID: |
256 | phy->type = e1000_phy_bm; | |
257 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
258 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
259 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
260 | hw->phy.ops.commit_phy = e1000e_phy_sw_reset; | |
261 | break; | |
bc7f75fa AK |
262 | default: |
263 | return -E1000_ERR_PHY; | |
264 | break; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | /** | |
271 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
272 | * @hw: pointer to the HW structure | |
273 | * | |
274 | * Initialize family-specific NVM parameters and function | |
275 | * pointers. | |
276 | **/ | |
277 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
278 | { | |
279 | struct e1000_nvm_info *nvm = &hw->nvm; | |
280 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
281 | u32 gfpreg; | |
282 | u32 sector_base_addr; | |
283 | u32 sector_end_addr; | |
284 | u16 i; | |
285 | ||
ad68076e | 286 | /* Can't read flash registers if the register set isn't mapped. */ |
bc7f75fa AK |
287 | if (!hw->flash_address) { |
288 | hw_dbg(hw, "ERROR: Flash registers not mapped\n"); | |
289 | return -E1000_ERR_CONFIG; | |
290 | } | |
291 | ||
292 | nvm->type = e1000_nvm_flash_sw; | |
293 | ||
294 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
295 | ||
ad68076e BA |
296 | /* |
297 | * sector_X_addr is a "sector"-aligned address (4096 bytes) | |
bc7f75fa | 298 | * Add 1 to sector_end_addr since this sector is included in |
ad68076e BA |
299 | * the overall size. |
300 | */ | |
bc7f75fa AK |
301 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
302 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
303 | ||
304 | /* flash_base_addr is byte-aligned */ | |
305 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
306 | ||
ad68076e BA |
307 | /* |
308 | * find total size of the NVM, then cut in half since the total | |
309 | * size represents two separate NVM banks. | |
310 | */ | |
bc7f75fa AK |
311 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
312 | << FLASH_SECTOR_ADDR_SHIFT; | |
313 | nvm->flash_bank_size /= 2; | |
314 | /* Adjust to word count */ | |
315 | nvm->flash_bank_size /= sizeof(u16); | |
316 | ||
317 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
318 | ||
319 | /* Clear shadow ram */ | |
320 | for (i = 0; i < nvm->word_size; i++) { | |
321 | dev_spec->shadow_ram[i].modified = 0; | |
322 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | /** | |
329 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
330 | * @hw: pointer to the HW structure | |
331 | * | |
332 | * Initialize family-specific MAC parameters and function | |
333 | * pointers. | |
334 | **/ | |
335 | static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) | |
336 | { | |
337 | struct e1000_hw *hw = &adapter->hw; | |
338 | struct e1000_mac_info *mac = &hw->mac; | |
339 | ||
340 | /* Set media type function pointer */ | |
318a94d6 | 341 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
342 | |
343 | /* Set mta register count */ | |
344 | mac->mta_reg_count = 32; | |
345 | /* Set rar entry count */ | |
346 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
347 | if (mac->type == e1000_ich8lan) | |
348 | mac->rar_entry_count--; | |
349 | /* Set if manageability features are enabled. */ | |
350 | mac->arc_subsystem_valid = 1; | |
351 | ||
352 | /* Enable PCS Lock-loss workaround for ICH8 */ | |
353 | if (mac->type == e1000_ich8lan) | |
354 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
69e3fd8c | 359 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
360 | { |
361 | struct e1000_hw *hw = &adapter->hw; | |
362 | s32 rc; | |
363 | ||
364 | rc = e1000_init_mac_params_ich8lan(adapter); | |
365 | if (rc) | |
366 | return rc; | |
367 | ||
368 | rc = e1000_init_nvm_params_ich8lan(hw); | |
369 | if (rc) | |
370 | return rc; | |
371 | ||
372 | rc = e1000_init_phy_params_ich8lan(hw); | |
373 | if (rc) | |
374 | return rc; | |
375 | ||
376 | if ((adapter->hw.mac.type == e1000_ich8lan) && | |
377 | (adapter->hw.phy.type == e1000_phy_igp_3)) | |
378 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | /** | |
384 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
385 | * @hw: pointer to the HW structure | |
386 | * | |
387 | * Acquires the software control flag for performing NVM and PHY | |
388 | * operations. This is a function pointer entry point only called by | |
389 | * read/write routines for the PHY and NVM parts. | |
390 | **/ | |
391 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
392 | { | |
393 | u32 extcnf_ctrl; | |
394 | u32 timeout = PHY_CFG_TIMEOUT; | |
395 | ||
396 | while (timeout) { | |
397 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
398 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
399 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
400 | ||
401 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
402 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
403 | break; | |
404 | mdelay(1); | |
405 | timeout--; | |
406 | } | |
407 | ||
408 | if (!timeout) { | |
409 | hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); | |
410 | return -E1000_ERR_CONFIG; | |
411 | } | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | /** | |
417 | * e1000_release_swflag_ich8lan - Release software control flag | |
418 | * @hw: pointer to the HW structure | |
419 | * | |
420 | * Releases the software control flag for performing NVM and PHY operations. | |
421 | * This is a function pointer entry point only called by read/write | |
422 | * routines for the PHY and NVM parts. | |
423 | **/ | |
424 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
425 | { | |
426 | u32 extcnf_ctrl; | |
427 | ||
428 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
429 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
430 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
431 | } | |
432 | ||
433 | /** | |
434 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
435 | * @hw: pointer to the HW structure | |
436 | * | |
437 | * Checks if firmware is blocking the reset of the PHY. | |
438 | * This is a function pointer entry point only called by | |
439 | * reset routines. | |
440 | **/ | |
441 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
442 | { | |
443 | u32 fwsm; | |
444 | ||
445 | fwsm = er32(FWSM); | |
446 | ||
447 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; | |
448 | } | |
449 | ||
450 | /** | |
451 | * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex | |
452 | * @hw: pointer to the HW structure | |
453 | * | |
454 | * Forces the speed and duplex settings of the PHY. | |
455 | * This is a function pointer entry point only called by | |
456 | * PHY setup routines. | |
457 | **/ | |
458 | static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |
459 | { | |
460 | struct e1000_phy_info *phy = &hw->phy; | |
461 | s32 ret_val; | |
462 | u16 data; | |
463 | bool link; | |
464 | ||
465 | if (phy->type != e1000_phy_ife) { | |
466 | ret_val = e1000e_phy_force_speed_duplex_igp(hw); | |
467 | return ret_val; | |
468 | } | |
469 | ||
470 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
471 | if (ret_val) | |
472 | return ret_val; | |
473 | ||
474 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
475 | ||
476 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
477 | if (ret_val) | |
478 | return ret_val; | |
479 | ||
480 | /* Disable MDI-X support for 10/100 */ | |
481 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
482 | if (ret_val) | |
483 | return ret_val; | |
484 | ||
485 | data &= ~IFE_PMC_AUTO_MDIX; | |
486 | data &= ~IFE_PMC_FORCE_MDIX; | |
487 | ||
488 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
489 | if (ret_val) | |
490 | return ret_val; | |
491 | ||
492 | hw_dbg(hw, "IFE PMC: %X\n", data); | |
493 | ||
494 | udelay(1); | |
495 | ||
318a94d6 | 496 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
497 | hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); |
498 | ||
499 | ret_val = e1000e_phy_has_link_generic(hw, | |
500 | PHY_FORCE_LIMIT, | |
501 | 100000, | |
502 | &link); | |
503 | if (ret_val) | |
504 | return ret_val; | |
505 | ||
506 | if (!link) | |
507 | hw_dbg(hw, "Link taking longer than expected.\n"); | |
508 | ||
509 | /* Try once more */ | |
510 | ret_val = e1000e_phy_has_link_generic(hw, | |
511 | PHY_FORCE_LIMIT, | |
512 | 100000, | |
513 | &link); | |
514 | if (ret_val) | |
515 | return ret_val; | |
516 | } | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | /** | |
522 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
523 | * @hw: pointer to the HW structure | |
524 | * | |
525 | * Resets the PHY | |
526 | * This is a function pointer entry point called by drivers | |
527 | * or other shared routines. | |
528 | **/ | |
529 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
530 | { | |
531 | struct e1000_phy_info *phy = &hw->phy; | |
532 | u32 i; | |
533 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
534 | s32 ret_val; | |
535 | u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
536 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | |
537 | ||
538 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
539 | if (ret_val) | |
540 | return ret_val; | |
541 | ||
ad68076e BA |
542 | /* |
543 | * Initialize the PHY from the NVM on ICH platforms. This | |
bc7f75fa AK |
544 | * is needed due to an issue where the NVM configuration is |
545 | * not properly autoloaded after power transitions. | |
546 | * Therefore, after each PHY reset, we will load the | |
547 | * configuration data out of the NVM manually. | |
548 | */ | |
549 | if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { | |
550 | struct e1000_adapter *adapter = hw->adapter; | |
551 | ||
552 | /* Check if SW needs configure the PHY */ | |
553 | if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || | |
554 | (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M)) | |
555 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; | |
556 | else | |
557 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; | |
558 | ||
559 | data = er32(FEXTNVM); | |
560 | if (!(data & sw_cfg_mask)) | |
561 | return 0; | |
562 | ||
563 | /* Wait for basic configuration completes before proceeding*/ | |
564 | do { | |
565 | data = er32(STATUS); | |
566 | data &= E1000_STATUS_LAN_INIT_DONE; | |
567 | udelay(100); | |
568 | } while ((!data) && --loop); | |
569 | ||
ad68076e BA |
570 | /* |
571 | * If basic configuration is incomplete before the above loop | |
bc7f75fa AK |
572 | * count reaches 0, loading the configuration from NVM will |
573 | * leave the PHY in a bad state possibly resulting in no link. | |
574 | */ | |
575 | if (loop == 0) { | |
576 | hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); | |
577 | } | |
578 | ||
579 | /* Clear the Init Done bit for the next init event */ | |
580 | data = er32(STATUS); | |
581 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
582 | ew32(STATUS, data); | |
583 | ||
ad68076e BA |
584 | /* |
585 | * Make sure HW does not configure LCD from PHY | |
586 | * extended configuration before SW configuration | |
587 | */ | |
bc7f75fa AK |
588 | data = er32(EXTCNF_CTRL); |
589 | if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) | |
590 | return 0; | |
591 | ||
592 | cnf_size = er32(EXTCNF_SIZE); | |
593 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
594 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
595 | if (!cnf_size) | |
596 | return 0; | |
597 | ||
598 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
599 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
600 | ||
ad68076e | 601 | /* Configure LCD from extended configuration region. */ |
bc7f75fa AK |
602 | |
603 | /* cnf_base_addr is in DWORD */ | |
604 | word_addr = (u16)(cnf_base_addr << 1); | |
605 | ||
606 | for (i = 0; i < cnf_size; i++) { | |
607 | ret_val = e1000_read_nvm(hw, | |
608 | (word_addr + i * 2), | |
609 | 1, | |
610 | ®_data); | |
611 | if (ret_val) | |
612 | return ret_val; | |
613 | ||
614 | ret_val = e1000_read_nvm(hw, | |
615 | (word_addr + i * 2 + 1), | |
616 | 1, | |
617 | ®_addr); | |
618 | if (ret_val) | |
619 | return ret_val; | |
620 | ||
621 | /* Save off the PHY page for future writes. */ | |
622 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
623 | phy_page = reg_data; | |
624 | continue; | |
625 | } | |
626 | ||
627 | reg_addr |= phy_page; | |
628 | ||
629 | ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); | |
630 | if (ret_val) | |
631 | return ret_val; | |
632 | } | |
633 | } | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | /** | |
639 | * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states | |
640 | * @hw: pointer to the HW structure | |
641 | * | |
642 | * Populates "phy" structure with various feature states. | |
643 | * This function is only called by other family-specific | |
644 | * routines. | |
645 | **/ | |
646 | static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) | |
647 | { | |
648 | struct e1000_phy_info *phy = &hw->phy; | |
649 | s32 ret_val; | |
650 | u16 data; | |
651 | bool link; | |
652 | ||
653 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
654 | if (ret_val) | |
655 | return ret_val; | |
656 | ||
657 | if (!link) { | |
658 | hw_dbg(hw, "Phy info is only valid if link is up\n"); | |
659 | return -E1000_ERR_CONFIG; | |
660 | } | |
661 | ||
662 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
663 | if (ret_val) | |
664 | return ret_val; | |
665 | phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); | |
666 | ||
667 | if (phy->polarity_correction) { | |
668 | ret_val = e1000_check_polarity_ife_ich8lan(hw); | |
669 | if (ret_val) | |
670 | return ret_val; | |
671 | } else { | |
672 | /* Polarity is forced */ | |
673 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
674 | ? e1000_rev_polarity_reversed | |
675 | : e1000_rev_polarity_normal; | |
676 | } | |
677 | ||
678 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
679 | if (ret_val) | |
680 | return ret_val; | |
681 | ||
682 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); | |
683 | ||
684 | /* The following parameters are undefined for 10/100 operation. */ | |
685 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
686 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
687 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | /** | |
693 | * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info | |
694 | * @hw: pointer to the HW structure | |
695 | * | |
696 | * Wrapper for calling the get_phy_info routines for the appropriate phy type. | |
697 | * This is a function pointer entry point called by drivers | |
698 | * or other shared routines. | |
699 | **/ | |
700 | static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) | |
701 | { | |
702 | switch (hw->phy.type) { | |
703 | case e1000_phy_ife: | |
704 | return e1000_get_phy_info_ife_ich8lan(hw); | |
705 | break; | |
706 | case e1000_phy_igp_3: | |
97ac8cae | 707 | case e1000_phy_bm: |
bc7f75fa AK |
708 | return e1000e_get_phy_info_igp(hw); |
709 | break; | |
710 | default: | |
711 | break; | |
712 | } | |
713 | ||
714 | return -E1000_ERR_PHY_TYPE; | |
715 | } | |
716 | ||
717 | /** | |
718 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY | |
719 | * @hw: pointer to the HW structure | |
720 | * | |
489815ce | 721 | * Polarity is determined on the polarity reversal feature being enabled. |
bc7f75fa AK |
722 | * This function is only called by other family-specific |
723 | * routines. | |
724 | **/ | |
725 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) | |
726 | { | |
727 | struct e1000_phy_info *phy = &hw->phy; | |
728 | s32 ret_val; | |
729 | u16 phy_data, offset, mask; | |
730 | ||
ad68076e BA |
731 | /* |
732 | * Polarity is determined based on the reversal feature being enabled. | |
bc7f75fa AK |
733 | */ |
734 | if (phy->polarity_correction) { | |
735 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
736 | mask = IFE_PESC_POLARITY_REVERSED; | |
737 | } else { | |
738 | offset = IFE_PHY_SPECIAL_CONTROL; | |
739 | mask = IFE_PSC_FORCE_POLARITY; | |
740 | } | |
741 | ||
742 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
743 | ||
744 | if (!ret_val) | |
745 | phy->cable_polarity = (phy_data & mask) | |
746 | ? e1000_rev_polarity_reversed | |
747 | : e1000_rev_polarity_normal; | |
748 | ||
749 | return ret_val; | |
750 | } | |
751 | ||
752 | /** | |
753 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
754 | * @hw: pointer to the HW structure | |
755 | * @active: TRUE to enable LPLU, FALSE to disable | |
756 | * | |
757 | * Sets the LPLU D0 state according to the active flag. When | |
758 | * activating LPLU this function also disables smart speed | |
759 | * and vice versa. LPLU will not be activated unless the | |
760 | * device autonegotiation advertisement meets standards of | |
761 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
762 | * This is a function pointer entry point only called by | |
763 | * PHY setup routines. | |
764 | **/ | |
765 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
766 | { | |
767 | struct e1000_phy_info *phy = &hw->phy; | |
768 | u32 phy_ctrl; | |
769 | s32 ret_val = 0; | |
770 | u16 data; | |
771 | ||
97ac8cae | 772 | if (phy->type == e1000_phy_ife) |
bc7f75fa AK |
773 | return ret_val; |
774 | ||
775 | phy_ctrl = er32(PHY_CTRL); | |
776 | ||
777 | if (active) { | |
778 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
779 | ew32(PHY_CTRL, phy_ctrl); | |
780 | ||
ad68076e BA |
781 | /* |
782 | * Call gig speed drop workaround on LPLU before accessing | |
783 | * any PHY registers | |
784 | */ | |
bc7f75fa AK |
785 | if ((hw->mac.type == e1000_ich8lan) && |
786 | (hw->phy.type == e1000_phy_igp_3)) | |
787 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
788 | ||
789 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
790 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
791 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
792 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
793 | if (ret_val) | |
794 | return ret_val; | |
795 | } else { | |
796 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
797 | ew32(PHY_CTRL, phy_ctrl); | |
798 | ||
ad68076e BA |
799 | /* |
800 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
801 | * during Dx states where the power conservation is most |
802 | * important. During driver activity we should enable | |
ad68076e BA |
803 | * SmartSpeed, so performance is maintained. |
804 | */ | |
bc7f75fa AK |
805 | if (phy->smart_speed == e1000_smart_speed_on) { |
806 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 807 | &data); |
bc7f75fa AK |
808 | if (ret_val) |
809 | return ret_val; | |
810 | ||
811 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
812 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 813 | data); |
bc7f75fa AK |
814 | if (ret_val) |
815 | return ret_val; | |
816 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
817 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 818 | &data); |
bc7f75fa AK |
819 | if (ret_val) |
820 | return ret_val; | |
821 | ||
822 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
823 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 824 | data); |
bc7f75fa AK |
825 | if (ret_val) |
826 | return ret_val; | |
827 | } | |
828 | } | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
833 | /** | |
834 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
835 | * @hw: pointer to the HW structure | |
836 | * @active: TRUE to enable LPLU, FALSE to disable | |
837 | * | |
838 | * Sets the LPLU D3 state according to the active flag. When | |
839 | * activating LPLU this function also disables smart speed | |
840 | * and vice versa. LPLU will not be activated unless the | |
841 | * device autonegotiation advertisement meets standards of | |
842 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
843 | * This is a function pointer entry point only called by | |
844 | * PHY setup routines. | |
845 | **/ | |
846 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
847 | { | |
848 | struct e1000_phy_info *phy = &hw->phy; | |
849 | u32 phy_ctrl; | |
850 | s32 ret_val; | |
851 | u16 data; | |
852 | ||
853 | phy_ctrl = er32(PHY_CTRL); | |
854 | ||
855 | if (!active) { | |
856 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
857 | ew32(PHY_CTRL, phy_ctrl); | |
ad68076e BA |
858 | /* |
859 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
860 | * during Dx states where the power conservation is most |
861 | * important. During driver activity we should enable | |
ad68076e BA |
862 | * SmartSpeed, so performance is maintained. |
863 | */ | |
bc7f75fa | 864 | if (phy->smart_speed == e1000_smart_speed_on) { |
ad68076e BA |
865 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
866 | &data); | |
bc7f75fa AK |
867 | if (ret_val) |
868 | return ret_val; | |
869 | ||
870 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
871 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
872 | data); | |
bc7f75fa AK |
873 | if (ret_val) |
874 | return ret_val; | |
875 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
ad68076e BA |
876 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
877 | &data); | |
bc7f75fa AK |
878 | if (ret_val) |
879 | return ret_val; | |
880 | ||
881 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
882 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
883 | data); | |
bc7f75fa AK |
884 | if (ret_val) |
885 | return ret_val; | |
886 | } | |
887 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
888 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
889 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
890 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
891 | ew32(PHY_CTRL, phy_ctrl); | |
892 | ||
ad68076e BA |
893 | /* |
894 | * Call gig speed drop workaround on LPLU before accessing | |
895 | * any PHY registers | |
896 | */ | |
bc7f75fa AK |
897 | if ((hw->mac.type == e1000_ich8lan) && |
898 | (hw->phy.type == e1000_phy_igp_3)) | |
899 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
900 | ||
901 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
ad68076e | 902 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
bc7f75fa AK |
903 | if (ret_val) |
904 | return ret_val; | |
905 | ||
906 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e | 907 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
bc7f75fa AK |
908 | } |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | /** | |
914 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
915 | * @hw: pointer to the HW structure | |
916 | * @offset: The offset (in bytes) of the word(s) to read. | |
917 | * @words: Size of data to read in words | |
918 | * @data: Pointer to the word(s) to read at offset. | |
919 | * | |
920 | * Reads a word(s) from the NVM using the flash access registers. | |
921 | **/ | |
922 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
923 | u16 *data) | |
924 | { | |
925 | struct e1000_nvm_info *nvm = &hw->nvm; | |
926 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
927 | u32 act_offset; | |
928 | s32 ret_val; | |
929 | u16 i, word; | |
930 | ||
931 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
932 | (words == 0)) { | |
933 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
934 | return -E1000_ERR_NVM; | |
935 | } | |
936 | ||
937 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
938 | if (ret_val) | |
939 | return ret_val; | |
940 | ||
941 | /* Start with the bank offset, then add the relative offset. */ | |
942 | act_offset = (er32(EECD) & E1000_EECD_SEC1VAL) | |
943 | ? nvm->flash_bank_size | |
944 | : 0; | |
945 | act_offset += offset; | |
946 | ||
947 | for (i = 0; i < words; i++) { | |
948 | if ((dev_spec->shadow_ram) && | |
949 | (dev_spec->shadow_ram[offset+i].modified)) { | |
950 | data[i] = dev_spec->shadow_ram[offset+i].value; | |
951 | } else { | |
952 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
953 | act_offset + i, | |
954 | &word); | |
955 | if (ret_val) | |
956 | break; | |
957 | data[i] = word; | |
958 | } | |
959 | } | |
960 | ||
961 | e1000_release_swflag_ich8lan(hw); | |
962 | ||
963 | return ret_val; | |
964 | } | |
965 | ||
966 | /** | |
967 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
968 | * @hw: pointer to the HW structure | |
969 | * | |
970 | * This function does initial flash setup so that a new read/write/erase cycle | |
971 | * can be started. | |
972 | **/ | |
973 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
974 | { | |
975 | union ich8_hws_flash_status hsfsts; | |
976 | s32 ret_val = -E1000_ERR_NVM; | |
977 | s32 i = 0; | |
978 | ||
979 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
980 | ||
981 | /* Check if the flash descriptor is valid */ | |
982 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
983 | hw_dbg(hw, "Flash descriptor invalid. " | |
984 | "SW Sequencing must be used."); | |
985 | return -E1000_ERR_NVM; | |
986 | } | |
987 | ||
988 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
989 | hsfsts.hsf_status.flcerr = 1; | |
990 | hsfsts.hsf_status.dael = 1; | |
991 | ||
992 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
993 | ||
ad68076e BA |
994 | /* |
995 | * Either we should have a hardware SPI cycle in progress | |
bc7f75fa AK |
996 | * bit to check against, in order to start a new cycle or |
997 | * FDONE bit should be changed in the hardware so that it | |
489815ce | 998 | * is 1 after hardware reset, which can then be used as an |
bc7f75fa AK |
999 | * indication whether a cycle is in progress or has been |
1000 | * completed. | |
1001 | */ | |
1002 | ||
1003 | if (hsfsts.hsf_status.flcinprog == 0) { | |
ad68076e BA |
1004 | /* |
1005 | * There is no cycle running at present, | |
1006 | * so we can start a cycle | |
1007 | * Begin by setting Flash Cycle Done. | |
1008 | */ | |
bc7f75fa AK |
1009 | hsfsts.hsf_status.flcdone = 1; |
1010 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1011 | ret_val = 0; | |
1012 | } else { | |
ad68076e BA |
1013 | /* |
1014 | * otherwise poll for sometime so the current | |
1015 | * cycle has a chance to end before giving up. | |
1016 | */ | |
bc7f75fa AK |
1017 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
1018 | hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); | |
1019 | if (hsfsts.hsf_status.flcinprog == 0) { | |
1020 | ret_val = 0; | |
1021 | break; | |
1022 | } | |
1023 | udelay(1); | |
1024 | } | |
1025 | if (ret_val == 0) { | |
ad68076e BA |
1026 | /* |
1027 | * Successful in waiting for previous cycle to timeout, | |
1028 | * now set the Flash Cycle Done. | |
1029 | */ | |
bc7f75fa AK |
1030 | hsfsts.hsf_status.flcdone = 1; |
1031 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1032 | } else { | |
1033 | hw_dbg(hw, "Flash controller busy, cannot get access"); | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | return ret_val; | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
1042 | * @hw: pointer to the HW structure | |
1043 | * @timeout: maximum time to wait for completion | |
1044 | * | |
1045 | * This function starts a flash cycle and waits for its completion. | |
1046 | **/ | |
1047 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
1048 | { | |
1049 | union ich8_hws_flash_ctrl hsflctl; | |
1050 | union ich8_hws_flash_status hsfsts; | |
1051 | s32 ret_val = -E1000_ERR_NVM; | |
1052 | u32 i = 0; | |
1053 | ||
1054 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
1055 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1056 | hsflctl.hsf_ctrl.flcgo = 1; | |
1057 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1058 | ||
1059 | /* wait till FDONE bit is set to 1 */ | |
1060 | do { | |
1061 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1062 | if (hsfsts.hsf_status.flcdone == 1) | |
1063 | break; | |
1064 | udelay(1); | |
1065 | } while (i++ < timeout); | |
1066 | ||
1067 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) | |
1068 | return 0; | |
1069 | ||
1070 | return ret_val; | |
1071 | } | |
1072 | ||
1073 | /** | |
1074 | * e1000_read_flash_word_ich8lan - Read word from flash | |
1075 | * @hw: pointer to the HW structure | |
1076 | * @offset: offset to data location | |
1077 | * @data: pointer to the location for storing the data | |
1078 | * | |
1079 | * Reads the flash word at offset into data. Offset is converted | |
1080 | * to bytes before read. | |
1081 | **/ | |
1082 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
1083 | u16 *data) | |
1084 | { | |
1085 | /* Must convert offset into bytes. */ | |
1086 | offset <<= 1; | |
1087 | ||
1088 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
1089 | } | |
1090 | ||
1091 | /** | |
1092 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
1093 | * @hw: pointer to the HW structure | |
1094 | * @offset: The offset (in bytes) of the byte or word to read. | |
1095 | * @size: Size of data to read, 1=byte 2=word | |
1096 | * @data: Pointer to the word to store the value read. | |
1097 | * | |
1098 | * Reads a byte or word from the NVM using the flash access registers. | |
1099 | **/ | |
1100 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1101 | u8 size, u16 *data) | |
1102 | { | |
1103 | union ich8_hws_flash_status hsfsts; | |
1104 | union ich8_hws_flash_ctrl hsflctl; | |
1105 | u32 flash_linear_addr; | |
1106 | u32 flash_data = 0; | |
1107 | s32 ret_val = -E1000_ERR_NVM; | |
1108 | u8 count = 0; | |
1109 | ||
1110 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1111 | return -E1000_ERR_NVM; | |
1112 | ||
1113 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1114 | hw->nvm.flash_base_addr; | |
1115 | ||
1116 | do { | |
1117 | udelay(1); | |
1118 | /* Steps */ | |
1119 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1120 | if (ret_val != 0) | |
1121 | break; | |
1122 | ||
1123 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1124 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1125 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
1126 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
1127 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1128 | ||
1129 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1130 | ||
1131 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1132 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
1133 | ||
ad68076e BA |
1134 | /* |
1135 | * Check if FCERR is set to 1, if set to 1, clear it | |
bc7f75fa AK |
1136 | * and try the whole sequence a few more times, else |
1137 | * read in (shift in) the Flash Data0, the order is | |
ad68076e BA |
1138 | * least significant byte first msb to lsb |
1139 | */ | |
bc7f75fa AK |
1140 | if (ret_val == 0) { |
1141 | flash_data = er32flash(ICH_FLASH_FDATA0); | |
1142 | if (size == 1) { | |
1143 | *data = (u8)(flash_data & 0x000000FF); | |
1144 | } else if (size == 2) { | |
1145 | *data = (u16)(flash_data & 0x0000FFFF); | |
1146 | } | |
1147 | break; | |
1148 | } else { | |
ad68076e BA |
1149 | /* |
1150 | * If we've gotten here, then things are probably | |
bc7f75fa AK |
1151 | * completely hosed, but if the error condition is |
1152 | * detected, it won't hurt to give it another try... | |
1153 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1154 | */ | |
1155 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1156 | if (hsfsts.hsf_status.flcerr == 1) { | |
1157 | /* Repeat for some time before giving up. */ | |
1158 | continue; | |
1159 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
1160 | hw_dbg(hw, "Timeout error - flash cycle " | |
1161 | "did not complete."); | |
1162 | break; | |
1163 | } | |
1164 | } | |
1165 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1166 | ||
1167 | return ret_val; | |
1168 | } | |
1169 | ||
1170 | /** | |
1171 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
1172 | * @hw: pointer to the HW structure | |
1173 | * @offset: The offset (in bytes) of the word(s) to write. | |
1174 | * @words: Size of data to write in words | |
1175 | * @data: Pointer to the word(s) to write at offset. | |
1176 | * | |
1177 | * Writes a byte or word to the NVM using the flash access registers. | |
1178 | **/ | |
1179 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1180 | u16 *data) | |
1181 | { | |
1182 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1183 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1184 | s32 ret_val; | |
1185 | u16 i; | |
1186 | ||
1187 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1188 | (words == 0)) { | |
1189 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1190 | return -E1000_ERR_NVM; | |
1191 | } | |
1192 | ||
1193 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1194 | if (ret_val) | |
1195 | return ret_val; | |
1196 | ||
1197 | for (i = 0; i < words; i++) { | |
1198 | dev_spec->shadow_ram[offset+i].modified = 1; | |
1199 | dev_spec->shadow_ram[offset+i].value = data[i]; | |
1200 | } | |
1201 | ||
1202 | e1000_release_swflag_ich8lan(hw); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | /** | |
1208 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
1209 | * @hw: pointer to the HW structure | |
1210 | * | |
1211 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
1212 | * which writes the checksum to the shadow ram. The changes in the shadow | |
1213 | * ram are then committed to the EEPROM by processing each bank at a time | |
1214 | * checking for the modified bit and writing only the pending changes. | |
489815ce | 1215 | * After a successful commit, the shadow ram is cleared and is ready for |
bc7f75fa AK |
1216 | * future writes. |
1217 | **/ | |
1218 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1219 | { | |
1220 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1221 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1222 | u32 i, act_offset, new_bank_offset, old_bank_offset; | |
1223 | s32 ret_val; | |
1224 | u16 data; | |
1225 | ||
1226 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
1227 | if (ret_val) | |
ad68076e | 1228 | return ret_val; |
bc7f75fa AK |
1229 | |
1230 | if (nvm->type != e1000_nvm_flash_sw) | |
ad68076e | 1231 | return ret_val; |
bc7f75fa AK |
1232 | |
1233 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1234 | if (ret_val) | |
ad68076e | 1235 | return ret_val; |
bc7f75fa | 1236 | |
ad68076e BA |
1237 | /* |
1238 | * We're writing to the opposite bank so if we're on bank 1, | |
bc7f75fa | 1239 | * write to bank 0 etc. We also need to erase the segment that |
ad68076e BA |
1240 | * is going to be written |
1241 | */ | |
bc7f75fa AK |
1242 | if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { |
1243 | new_bank_offset = nvm->flash_bank_size; | |
1244 | old_bank_offset = 0; | |
1245 | e1000_erase_flash_bank_ich8lan(hw, 1); | |
1246 | } else { | |
1247 | old_bank_offset = nvm->flash_bank_size; | |
1248 | new_bank_offset = 0; | |
1249 | e1000_erase_flash_bank_ich8lan(hw, 0); | |
1250 | } | |
1251 | ||
1252 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
ad68076e BA |
1253 | /* |
1254 | * Determine whether to write the value stored | |
bc7f75fa | 1255 | * in the other NVM bank or a modified value stored |
ad68076e BA |
1256 | * in the shadow RAM |
1257 | */ | |
bc7f75fa AK |
1258 | if (dev_spec->shadow_ram[i].modified) { |
1259 | data = dev_spec->shadow_ram[i].value; | |
1260 | } else { | |
1261 | e1000_read_flash_word_ich8lan(hw, | |
1262 | i + old_bank_offset, | |
1263 | &data); | |
1264 | } | |
1265 | ||
ad68076e BA |
1266 | /* |
1267 | * If the word is 0x13, then make sure the signature bits | |
bc7f75fa AK |
1268 | * (15:14) are 11b until the commit has completed. |
1269 | * This will allow us to write 10b which indicates the | |
1270 | * signature is valid. We want to do this after the write | |
1271 | * has completed so that we don't mark the segment valid | |
ad68076e BA |
1272 | * while the write is still in progress |
1273 | */ | |
bc7f75fa AK |
1274 | if (i == E1000_ICH_NVM_SIG_WORD) |
1275 | data |= E1000_ICH_NVM_SIG_MASK; | |
1276 | ||
1277 | /* Convert offset to bytes. */ | |
1278 | act_offset = (i + new_bank_offset) << 1; | |
1279 | ||
1280 | udelay(100); | |
1281 | /* Write the bytes to the new bank. */ | |
1282 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1283 | act_offset, | |
1284 | (u8)data); | |
1285 | if (ret_val) | |
1286 | break; | |
1287 | ||
1288 | udelay(100); | |
1289 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1290 | act_offset + 1, | |
1291 | (u8)(data >> 8)); | |
1292 | if (ret_val) | |
1293 | break; | |
1294 | } | |
1295 | ||
ad68076e BA |
1296 | /* |
1297 | * Don't bother writing the segment valid bits if sector | |
1298 | * programming failed. | |
1299 | */ | |
bc7f75fa | 1300 | if (ret_val) { |
4a770358 | 1301 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
bc7f75fa AK |
1302 | hw_dbg(hw, "Flash commit failed.\n"); |
1303 | e1000_release_swflag_ich8lan(hw); | |
1304 | return ret_val; | |
1305 | } | |
1306 | ||
ad68076e BA |
1307 | /* |
1308 | * Finally validate the new segment by setting bit 15:14 | |
bc7f75fa AK |
1309 | * to 10b in word 0x13 , this can be done without an |
1310 | * erase as well since these bits are 11 to start with | |
ad68076e BA |
1311 | * and we need to change bit 14 to 0b |
1312 | */ | |
bc7f75fa AK |
1313 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
1314 | e1000_read_flash_word_ich8lan(hw, act_offset, &data); | |
1315 | data &= 0xBFFF; | |
1316 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1317 | act_offset * 2 + 1, | |
1318 | (u8)(data >> 8)); | |
1319 | if (ret_val) { | |
1320 | e1000_release_swflag_ich8lan(hw); | |
1321 | return ret_val; | |
1322 | } | |
1323 | ||
ad68076e BA |
1324 | /* |
1325 | * And invalidate the previously valid segment by setting | |
bc7f75fa AK |
1326 | * its signature word (0x13) high_byte to 0b. This can be |
1327 | * done without an erase because flash erase sets all bits | |
ad68076e BA |
1328 | * to 1's. We can write 1's to 0's without an erase |
1329 | */ | |
bc7f75fa AK |
1330 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
1331 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
1332 | if (ret_val) { | |
1333 | e1000_release_swflag_ich8lan(hw); | |
1334 | return ret_val; | |
1335 | } | |
1336 | ||
1337 | /* Great! Everything worked, we can now clear the cached entries. */ | |
1338 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
1339 | dev_spec->shadow_ram[i].modified = 0; | |
1340 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
1341 | } | |
1342 | ||
1343 | e1000_release_swflag_ich8lan(hw); | |
1344 | ||
ad68076e BA |
1345 | /* |
1346 | * Reload the EEPROM, or else modifications will not appear | |
bc7f75fa AK |
1347 | * until after the next adapter reset. |
1348 | */ | |
1349 | e1000e_reload_nvm(hw); | |
1350 | msleep(10); | |
1351 | ||
1352 | return ret_val; | |
1353 | } | |
1354 | ||
1355 | /** | |
1356 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
1357 | * @hw: pointer to the HW structure | |
1358 | * | |
1359 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
1360 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
1361 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
1362 | **/ | |
1363 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1364 | { | |
1365 | s32 ret_val; | |
1366 | u16 data; | |
1367 | ||
ad68076e BA |
1368 | /* |
1369 | * Read 0x19 and check bit 6. If this bit is 0, the checksum | |
bc7f75fa AK |
1370 | * needs to be fixed. This bit is an indication that the NVM |
1371 | * was prepared by OEM software and did not calculate the | |
1372 | * checksum...a likely scenario. | |
1373 | */ | |
1374 | ret_val = e1000_read_nvm(hw, 0x19, 1, &data); | |
1375 | if (ret_val) | |
1376 | return ret_val; | |
1377 | ||
1378 | if ((data & 0x40) == 0) { | |
1379 | data |= 0x40; | |
1380 | ret_val = e1000_write_nvm(hw, 0x19, 1, &data); | |
1381 | if (ret_val) | |
1382 | return ret_val; | |
1383 | ret_val = e1000e_update_nvm_checksum(hw); | |
1384 | if (ret_val) | |
1385 | return ret_val; | |
1386 | } | |
1387 | ||
1388 | return e1000e_validate_nvm_checksum_generic(hw); | |
1389 | } | |
1390 | ||
4a770358 BA |
1391 | /** |
1392 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only | |
1393 | * @hw: pointer to the HW structure | |
1394 | * | |
1395 | * To prevent malicious write/erase of the NVM, set it to be read-only | |
1396 | * so that the hardware ignores all write/erase cycles of the NVM via | |
1397 | * the flash control registers. The shadow-ram copy of the NVM will | |
1398 | * still be updated, however any updates to this copy will not stick | |
1399 | * across driver reloads. | |
1400 | **/ | |
1401 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |
1402 | { | |
1403 | union ich8_flash_protected_range pr0; | |
1404 | union ich8_hws_flash_status hsfsts; | |
1405 | u32 gfpreg; | |
1406 | s32 ret_val; | |
1407 | ||
1408 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1409 | if (ret_val) | |
1410 | return; | |
1411 | ||
1412 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
1413 | ||
1414 | /* Write-protect GbE Sector of NVM */ | |
1415 | pr0.regval = er32flash(ICH_FLASH_PR0); | |
1416 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; | |
1417 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); | |
1418 | pr0.range.wpe = true; | |
1419 | ew32flash(ICH_FLASH_PR0, pr0.regval); | |
1420 | ||
1421 | /* | |
1422 | * Lock down a subset of GbE Flash Control Registers, e.g. | |
1423 | * PR0 to prevent the write-protection from being lifted. | |
1424 | * Once FLOCKDN is set, the registers protected by it cannot | |
1425 | * be written until FLOCKDN is cleared by a hardware reset. | |
1426 | */ | |
1427 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1428 | hsfsts.hsf_status.flockdn = true; | |
1429 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1430 | ||
1431 | e1000_release_swflag_ich8lan(hw); | |
1432 | } | |
1433 | ||
bc7f75fa AK |
1434 | /** |
1435 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
1436 | * @hw: pointer to the HW structure | |
1437 | * @offset: The offset (in bytes) of the byte/word to read. | |
1438 | * @size: Size of data to read, 1=byte 2=word | |
1439 | * @data: The byte(s) to write to the NVM. | |
1440 | * | |
1441 | * Writes one/two bytes to the NVM using the flash access registers. | |
1442 | **/ | |
1443 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1444 | u8 size, u16 data) | |
1445 | { | |
1446 | union ich8_hws_flash_status hsfsts; | |
1447 | union ich8_hws_flash_ctrl hsflctl; | |
1448 | u32 flash_linear_addr; | |
1449 | u32 flash_data = 0; | |
1450 | s32 ret_val; | |
1451 | u8 count = 0; | |
1452 | ||
1453 | if (size < 1 || size > 2 || data > size * 0xff || | |
1454 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1455 | return -E1000_ERR_NVM; | |
1456 | ||
1457 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1458 | hw->nvm.flash_base_addr; | |
1459 | ||
1460 | do { | |
1461 | udelay(1); | |
1462 | /* Steps */ | |
1463 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1464 | if (ret_val) | |
1465 | break; | |
1466 | ||
1467 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1468 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1469 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
1470 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
1471 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1472 | ||
1473 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1474 | ||
1475 | if (size == 1) | |
1476 | flash_data = (u32)data & 0x00FF; | |
1477 | else | |
1478 | flash_data = (u32)data; | |
1479 | ||
1480 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
1481 | ||
ad68076e BA |
1482 | /* |
1483 | * check if FCERR is set to 1 , if set to 1, clear it | |
1484 | * and try the whole sequence a few more times else done | |
1485 | */ | |
bc7f75fa AK |
1486 | ret_val = e1000_flash_cycle_ich8lan(hw, |
1487 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
1488 | if (!ret_val) | |
1489 | break; | |
1490 | ||
ad68076e BA |
1491 | /* |
1492 | * If we're here, then things are most likely | |
bc7f75fa AK |
1493 | * completely hosed, but if the error condition |
1494 | * is detected, it won't hurt to give it another | |
1495 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1496 | */ | |
1497 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1498 | if (hsfsts.hsf_status.flcerr == 1) | |
1499 | /* Repeat for some time before giving up. */ | |
1500 | continue; | |
1501 | if (hsfsts.hsf_status.flcdone == 0) { | |
1502 | hw_dbg(hw, "Timeout error - flash cycle " | |
1503 | "did not complete."); | |
1504 | break; | |
1505 | } | |
1506 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1507 | ||
1508 | return ret_val; | |
1509 | } | |
1510 | ||
1511 | /** | |
1512 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
1513 | * @hw: pointer to the HW structure | |
1514 | * @offset: The index of the byte to read. | |
1515 | * @data: The byte to write to the NVM. | |
1516 | * | |
1517 | * Writes a single byte to the NVM using the flash access registers. | |
1518 | **/ | |
1519 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1520 | u8 data) | |
1521 | { | |
1522 | u16 word = (u16)data; | |
1523 | ||
1524 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
1525 | } | |
1526 | ||
1527 | /** | |
1528 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
1529 | * @hw: pointer to the HW structure | |
1530 | * @offset: The offset of the byte to write. | |
1531 | * @byte: The byte to write to the NVM. | |
1532 | * | |
1533 | * Writes a single byte to the NVM using the flash access registers. | |
1534 | * Goes through a retry algorithm before giving up. | |
1535 | **/ | |
1536 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
1537 | u32 offset, u8 byte) | |
1538 | { | |
1539 | s32 ret_val; | |
1540 | u16 program_retries; | |
1541 | ||
1542 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1543 | if (!ret_val) | |
1544 | return ret_val; | |
1545 | ||
1546 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
1547 | hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); | |
1548 | udelay(100); | |
1549 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1550 | if (!ret_val) | |
1551 | break; | |
1552 | } | |
1553 | if (program_retries == 100) | |
1554 | return -E1000_ERR_NVM; | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
1561 | * @hw: pointer to the HW structure | |
1562 | * @bank: 0 for first bank, 1 for second bank, etc. | |
1563 | * | |
1564 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
1565 | * bank N is 4096 * N + flash_reg_addr. | |
1566 | **/ | |
1567 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
1568 | { | |
1569 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1570 | union ich8_hws_flash_status hsfsts; | |
1571 | union ich8_hws_flash_ctrl hsflctl; | |
1572 | u32 flash_linear_addr; | |
1573 | /* bank size is in 16bit words - adjust to bytes */ | |
1574 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
1575 | s32 ret_val; | |
1576 | s32 count = 0; | |
1577 | s32 iteration; | |
1578 | s32 sector_size; | |
1579 | s32 j; | |
1580 | ||
1581 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1582 | ||
ad68076e BA |
1583 | /* |
1584 | * Determine HW Sector size: Read BERASE bits of hw flash status | |
1585 | * register | |
1586 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
bc7f75fa AK |
1587 | * consecutive sectors. The start index for the nth Hw sector |
1588 | * can be calculated as = bank * 4096 + n * 256 | |
1589 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
1590 | * The start index for the nth Hw sector can be calculated | |
1591 | * as = bank * 4096 | |
1592 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
1593 | * (ich9 only, otherwise error condition) | |
1594 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
1595 | */ | |
1596 | switch (hsfsts.hsf_status.berasesz) { | |
1597 | case 0: | |
1598 | /* Hw sector size 256 */ | |
1599 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
1600 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
1601 | break; | |
1602 | case 1: | |
1603 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
1604 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; | |
1605 | break; | |
1606 | case 2: | |
1607 | if (hw->mac.type == e1000_ich9lan) { | |
1608 | sector_size = ICH_FLASH_SEG_SIZE_8K; | |
1609 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; | |
1610 | } else { | |
1611 | return -E1000_ERR_NVM; | |
1612 | } | |
1613 | break; | |
1614 | case 3: | |
1615 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
1616 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; | |
1617 | break; | |
1618 | default: | |
1619 | return -E1000_ERR_NVM; | |
1620 | } | |
1621 | ||
1622 | /* Start with the base address, then add the sector offset. */ | |
1623 | flash_linear_addr = hw->nvm.flash_base_addr; | |
1624 | flash_linear_addr += (bank) ? (sector_size * iteration) : 0; | |
1625 | ||
1626 | for (j = 0; j < iteration ; j++) { | |
1627 | do { | |
1628 | /* Steps */ | |
1629 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1630 | if (ret_val) | |
1631 | return ret_val; | |
1632 | ||
ad68076e BA |
1633 | /* |
1634 | * Write a value 11 (block Erase) in Flash | |
1635 | * Cycle field in hw flash control | |
1636 | */ | |
bc7f75fa AK |
1637 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
1638 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
1639 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1640 | ||
ad68076e BA |
1641 | /* |
1642 | * Write the last 24 bits of an index within the | |
bc7f75fa AK |
1643 | * block into Flash Linear address field in Flash |
1644 | * Address. | |
1645 | */ | |
1646 | flash_linear_addr += (j * sector_size); | |
1647 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1648 | ||
1649 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1650 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); | |
1651 | if (ret_val == 0) | |
1652 | break; | |
1653 | ||
ad68076e BA |
1654 | /* |
1655 | * Check if FCERR is set to 1. If 1, | |
bc7f75fa | 1656 | * clear it and try the whole sequence |
ad68076e BA |
1657 | * a few more times else Done |
1658 | */ | |
bc7f75fa AK |
1659 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
1660 | if (hsfsts.hsf_status.flcerr == 1) | |
ad68076e | 1661 | /* repeat for some time before giving up */ |
bc7f75fa AK |
1662 | continue; |
1663 | else if (hsfsts.hsf_status.flcdone == 0) | |
1664 | return ret_val; | |
1665 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1666 | } | |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
1673 | * @hw: pointer to the HW structure | |
1674 | * @data: Pointer to the LED settings | |
1675 | * | |
1676 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
1677 | * settings is all 0's or F's, set the LED default to a valid LED default | |
1678 | * setting. | |
1679 | **/ | |
1680 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
1681 | { | |
1682 | s32 ret_val; | |
1683 | ||
1684 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1685 | if (ret_val) { | |
1686 | hw_dbg(hw, "NVM Read Error\n"); | |
1687 | return ret_val; | |
1688 | } | |
1689 | ||
1690 | if (*data == ID_LED_RESERVED_0000 || | |
1691 | *data == ID_LED_RESERVED_FFFF) | |
1692 | *data = ID_LED_DEFAULT_ICH8LAN; | |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | /** | |
1698 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
1699 | * @hw: pointer to the HW structure | |
1700 | * | |
1701 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
1702 | * register, so the the bus width is hard coded. | |
1703 | **/ | |
1704 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
1705 | { | |
1706 | struct e1000_bus_info *bus = &hw->bus; | |
1707 | s32 ret_val; | |
1708 | ||
1709 | ret_val = e1000e_get_bus_info_pcie(hw); | |
1710 | ||
ad68076e BA |
1711 | /* |
1712 | * ICH devices are "PCI Express"-ish. They have | |
bc7f75fa AK |
1713 | * a configuration space, but do not contain |
1714 | * PCI Express Capability registers, so bus width | |
1715 | * must be hardcoded. | |
1716 | */ | |
1717 | if (bus->width == e1000_bus_width_unknown) | |
1718 | bus->width = e1000_bus_width_pcie_x1; | |
1719 | ||
1720 | return ret_val; | |
1721 | } | |
1722 | ||
1723 | /** | |
1724 | * e1000_reset_hw_ich8lan - Reset the hardware | |
1725 | * @hw: pointer to the HW structure | |
1726 | * | |
1727 | * Does a full reset of the hardware which includes a reset of the PHY and | |
1728 | * MAC. | |
1729 | **/ | |
1730 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
1731 | { | |
1732 | u32 ctrl, icr, kab; | |
1733 | s32 ret_val; | |
1734 | ||
ad68076e BA |
1735 | /* |
1736 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
1737 | * on the last TLP read/write transaction when MAC is reset. |
1738 | */ | |
1739 | ret_val = e1000e_disable_pcie_master(hw); | |
1740 | if (ret_val) { | |
1741 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
1742 | } | |
1743 | ||
1744 | hw_dbg(hw, "Masking off all interrupts\n"); | |
1745 | ew32(IMC, 0xffffffff); | |
1746 | ||
ad68076e BA |
1747 | /* |
1748 | * Disable the Transmit and Receive units. Then delay to allow | |
bc7f75fa AK |
1749 | * any pending transactions to complete before we hit the MAC |
1750 | * with the global reset. | |
1751 | */ | |
1752 | ew32(RCTL, 0); | |
1753 | ew32(TCTL, E1000_TCTL_PSP); | |
1754 | e1e_flush(); | |
1755 | ||
1756 | msleep(10); | |
1757 | ||
1758 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
1759 | if (hw->mac.type == e1000_ich8lan) { | |
1760 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
1761 | ew32(PBA, E1000_PBA_8K); | |
1762 | /* Set Packet Buffer Size to 16k. */ | |
1763 | ew32(PBS, E1000_PBS_16K); | |
1764 | } | |
1765 | ||
1766 | ctrl = er32(CTRL); | |
1767 | ||
1768 | if (!e1000_check_reset_block(hw)) { | |
ad68076e BA |
1769 | /* |
1770 | * PHY HW reset requires MAC CORE reset at the same | |
bc7f75fa AK |
1771 | * time to make sure the interface between MAC and the |
1772 | * external PHY is reset. | |
1773 | */ | |
1774 | ctrl |= E1000_CTRL_PHY_RST; | |
1775 | } | |
1776 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1777 | hw_dbg(hw, "Issuing a global reset to ich8lan"); | |
1778 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | |
1779 | msleep(20); | |
1780 | ||
1781 | ret_val = e1000e_get_auto_rd_done(hw); | |
1782 | if (ret_val) { | |
1783 | /* | |
1784 | * When auto config read does not complete, do not | |
1785 | * return with an error. This can happen in situations | |
1786 | * where there is no eeprom and prevents getting link. | |
1787 | */ | |
1788 | hw_dbg(hw, "Auto Read Done did not complete\n"); | |
1789 | } | |
1790 | ||
1791 | ew32(IMC, 0xffffffff); | |
1792 | icr = er32(ICR); | |
1793 | ||
1794 | kab = er32(KABGTXD); | |
1795 | kab |= E1000_KABGTXD_BGSQLBIAS; | |
1796 | ew32(KABGTXD, kab); | |
1797 | ||
1798 | return ret_val; | |
1799 | } | |
1800 | ||
1801 | /** | |
1802 | * e1000_init_hw_ich8lan - Initialize the hardware | |
1803 | * @hw: pointer to the HW structure | |
1804 | * | |
1805 | * Prepares the hardware for transmit and receive by doing the following: | |
1806 | * - initialize hardware bits | |
1807 | * - initialize LED identification | |
1808 | * - setup receive address registers | |
1809 | * - setup flow control | |
489815ce | 1810 | * - setup transmit descriptors |
bc7f75fa AK |
1811 | * - clear statistics |
1812 | **/ | |
1813 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
1814 | { | |
1815 | struct e1000_mac_info *mac = &hw->mac; | |
1816 | u32 ctrl_ext, txdctl, snoop; | |
1817 | s32 ret_val; | |
1818 | u16 i; | |
1819 | ||
1820 | e1000_initialize_hw_bits_ich8lan(hw); | |
1821 | ||
1822 | /* Initialize identification LED */ | |
1823 | ret_val = e1000e_id_led_init(hw); | |
1824 | if (ret_val) { | |
1825 | hw_dbg(hw, "Error initializing identification LED\n"); | |
1826 | return ret_val; | |
1827 | } | |
1828 | ||
1829 | /* Setup the receive address. */ | |
1830 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
1831 | ||
1832 | /* Zero out the Multicast HASH table */ | |
1833 | hw_dbg(hw, "Zeroing the MTA\n"); | |
1834 | for (i = 0; i < mac->mta_reg_count; i++) | |
1835 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1836 | ||
1837 | /* Setup link and flow control */ | |
1838 | ret_val = e1000_setup_link_ich8lan(hw); | |
1839 | ||
1840 | /* Set the transmit descriptor write-back policy for both queues */ | |
e9ec2c0f | 1841 | txdctl = er32(TXDCTL(0)); |
bc7f75fa AK |
1842 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1843 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1844 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
1845 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f JK |
1846 | ew32(TXDCTL(0), txdctl); |
1847 | txdctl = er32(TXDCTL(1)); | |
bc7f75fa AK |
1848 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1849 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1850 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
1851 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f | 1852 | ew32(TXDCTL(1), txdctl); |
bc7f75fa | 1853 | |
ad68076e BA |
1854 | /* |
1855 | * ICH8 has opposite polarity of no_snoop bits. | |
1856 | * By default, we should use snoop behavior. | |
1857 | */ | |
bc7f75fa AK |
1858 | if (mac->type == e1000_ich8lan) |
1859 | snoop = PCIE_ICH8_SNOOP_ALL; | |
1860 | else | |
1861 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); | |
1862 | e1000e_set_pcie_no_snoop(hw, snoop); | |
1863 | ||
1864 | ctrl_ext = er32(CTRL_EXT); | |
1865 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
1866 | ew32(CTRL_EXT, ctrl_ext); | |
1867 | ||
ad68076e BA |
1868 | /* |
1869 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1870 | * important that we do this after we have tried to establish link |
1871 | * because the symbol error count will increment wildly if there | |
1872 | * is no link. | |
1873 | */ | |
1874 | e1000_clear_hw_cntrs_ich8lan(hw); | |
1875 | ||
1876 | return 0; | |
1877 | } | |
1878 | /** | |
1879 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
1880 | * @hw: pointer to the HW structure | |
1881 | * | |
1882 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
1883 | * hardware for transmit and receive. | |
1884 | **/ | |
1885 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
1886 | { | |
1887 | u32 reg; | |
1888 | ||
1889 | /* Extended Device Control */ | |
1890 | reg = er32(CTRL_EXT); | |
1891 | reg |= (1 << 22); | |
1892 | ew32(CTRL_EXT, reg); | |
1893 | ||
1894 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1895 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1896 | reg |= (1 << 22); |
e9ec2c0f | 1897 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1898 | |
1899 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1900 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1901 | reg |= (1 << 22); |
e9ec2c0f | 1902 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1903 | |
1904 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1905 | reg = er32(TARC(0)); |
bc7f75fa AK |
1906 | if (hw->mac.type == e1000_ich8lan) |
1907 | reg |= (1 << 28) | (1 << 29); | |
1908 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
e9ec2c0f | 1909 | ew32(TARC(0), reg); |
bc7f75fa AK |
1910 | |
1911 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1912 | reg = er32(TARC(1)); |
bc7f75fa AK |
1913 | if (er32(TCTL) & E1000_TCTL_MULR) |
1914 | reg &= ~(1 << 28); | |
1915 | else | |
1916 | reg |= (1 << 28); | |
1917 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
e9ec2c0f | 1918 | ew32(TARC(1), reg); |
bc7f75fa AK |
1919 | |
1920 | /* Device Status */ | |
1921 | if (hw->mac.type == e1000_ich8lan) { | |
1922 | reg = er32(STATUS); | |
1923 | reg &= ~(1 << 31); | |
1924 | ew32(STATUS, reg); | |
1925 | } | |
1926 | } | |
1927 | ||
1928 | /** | |
1929 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
1930 | * @hw: pointer to the HW structure | |
1931 | * | |
1932 | * Determines which flow control settings to use, then configures flow | |
1933 | * control. Calls the appropriate media-specific link configuration | |
1934 | * function. Assuming the adapter has a valid link partner, a valid link | |
1935 | * should be established. Assumes the hardware has previously been reset | |
1936 | * and the transmitter and receiver are not enabled. | |
1937 | **/ | |
1938 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
1939 | { | |
bc7f75fa AK |
1940 | s32 ret_val; |
1941 | ||
1942 | if (e1000_check_reset_block(hw)) | |
1943 | return 0; | |
1944 | ||
ad68076e BA |
1945 | /* |
1946 | * ICH parts do not have a word in the NVM to determine | |
bc7f75fa AK |
1947 | * the default flow control setting, so we explicitly |
1948 | * set it to full. | |
1949 | */ | |
318a94d6 JK |
1950 | if (hw->fc.type == e1000_fc_default) |
1951 | hw->fc.type = e1000_fc_full; | |
bc7f75fa | 1952 | |
318a94d6 | 1953 | hw->fc.original_type = hw->fc.type; |
bc7f75fa | 1954 | |
318a94d6 | 1955 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type); |
bc7f75fa AK |
1956 | |
1957 | /* Continue to configure the copper link. */ | |
1958 | ret_val = e1000_setup_copper_link_ich8lan(hw); | |
1959 | if (ret_val) | |
1960 | return ret_val; | |
1961 | ||
318a94d6 | 1962 | ew32(FCTTV, hw->fc.pause_time); |
bc7f75fa AK |
1963 | |
1964 | return e1000e_set_fc_watermarks(hw); | |
1965 | } | |
1966 | ||
1967 | /** | |
1968 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
1969 | * @hw: pointer to the HW structure | |
1970 | * | |
1971 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
1972 | * when polling the PHY, then call the generic setup_copper_link to finish | |
1973 | * configuring the copper link. | |
1974 | **/ | |
1975 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
1976 | { | |
1977 | u32 ctrl; | |
1978 | s32 ret_val; | |
1979 | u16 reg_data; | |
1980 | ||
1981 | ctrl = er32(CTRL); | |
1982 | ctrl |= E1000_CTRL_SLU; | |
1983 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1984 | ew32(CTRL, ctrl); | |
1985 | ||
ad68076e BA |
1986 | /* |
1987 | * Set the mac to wait the maximum time between each iteration | |
bc7f75fa | 1988 | * and increase the max iterations when polling the phy; |
ad68076e BA |
1989 | * this fixes erroneous timeouts at 10Mbps. |
1990 | */ | |
bc7f75fa AK |
1991 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
1992 | if (ret_val) | |
1993 | return ret_val; | |
1994 | ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
1995 | if (ret_val) | |
1996 | return ret_val; | |
1997 | reg_data |= 0x3F; | |
1998 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
1999 | if (ret_val) | |
2000 | return ret_val; | |
2001 | ||
2002 | if (hw->phy.type == e1000_phy_igp_3) { | |
2003 | ret_val = e1000e_copper_link_setup_igp(hw); | |
2004 | if (ret_val) | |
2005 | return ret_val; | |
97ac8cae BA |
2006 | } else if (hw->phy.type == e1000_phy_bm) { |
2007 | ret_val = e1000e_copper_link_setup_m88(hw); | |
2008 | if (ret_val) | |
2009 | return ret_val; | |
bc7f75fa AK |
2010 | } |
2011 | ||
97ac8cae BA |
2012 | if (hw->phy.type == e1000_phy_ife) { |
2013 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); | |
2014 | if (ret_val) | |
2015 | return ret_val; | |
2016 | ||
2017 | reg_data &= ~IFE_PMC_AUTO_MDIX; | |
2018 | ||
2019 | switch (hw->phy.mdix) { | |
2020 | case 1: | |
2021 | reg_data &= ~IFE_PMC_FORCE_MDIX; | |
2022 | break; | |
2023 | case 2: | |
2024 | reg_data |= IFE_PMC_FORCE_MDIX; | |
2025 | break; | |
2026 | case 0: | |
2027 | default: | |
2028 | reg_data |= IFE_PMC_AUTO_MDIX; | |
2029 | break; | |
2030 | } | |
2031 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); | |
2032 | if (ret_val) | |
2033 | return ret_val; | |
2034 | } | |
bc7f75fa AK |
2035 | return e1000e_setup_copper_link(hw); |
2036 | } | |
2037 | ||
2038 | /** | |
2039 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
2040 | * @hw: pointer to the HW structure | |
2041 | * @speed: pointer to store current link speed | |
2042 | * @duplex: pointer to store the current link duplex | |
2043 | * | |
ad68076e | 2044 | * Calls the generic get_speed_and_duplex to retrieve the current link |
bc7f75fa AK |
2045 | * information and then calls the Kumeran lock loss workaround for links at |
2046 | * gigabit speeds. | |
2047 | **/ | |
2048 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
2049 | u16 *duplex) | |
2050 | { | |
2051 | s32 ret_val; | |
2052 | ||
2053 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
2054 | if (ret_val) | |
2055 | return ret_val; | |
2056 | ||
2057 | if ((hw->mac.type == e1000_ich8lan) && | |
2058 | (hw->phy.type == e1000_phy_igp_3) && | |
2059 | (*speed == SPEED_1000)) { | |
2060 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
2061 | } | |
2062 | ||
2063 | return ret_val; | |
2064 | } | |
2065 | ||
2066 | /** | |
2067 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
2068 | * @hw: pointer to the HW structure | |
2069 | * | |
2070 | * Work-around for 82566 Kumeran PCS lock loss: | |
2071 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
2072 | * speed is gigabit- | |
2073 | * 0) if workaround is optionally disabled do nothing | |
2074 | * 1) wait 1ms for Kumeran link to come up | |
2075 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
2076 | * 3) if not set the link is locked (all is good), otherwise... | |
2077 | * 4) reset the PHY | |
2078 | * 5) repeat up to 10 times | |
2079 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
2080 | **/ | |
2081 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
2082 | { | |
2083 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2084 | u32 phy_ctrl; | |
2085 | s32 ret_val; | |
2086 | u16 i, data; | |
2087 | bool link; | |
2088 | ||
2089 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
2090 | return 0; | |
2091 | ||
ad68076e BA |
2092 | /* |
2093 | * Make sure link is up before proceeding. If not just return. | |
bc7f75fa | 2094 | * Attempting this while link is negotiating fouled up link |
ad68076e BA |
2095 | * stability |
2096 | */ | |
bc7f75fa AK |
2097 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
2098 | if (!link) | |
2099 | return 0; | |
2100 | ||
2101 | for (i = 0; i < 10; i++) { | |
2102 | /* read once to clear */ | |
2103 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2104 | if (ret_val) | |
2105 | return ret_val; | |
2106 | /* and again to get new status */ | |
2107 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2108 | if (ret_val) | |
2109 | return ret_val; | |
2110 | ||
2111 | /* check for PCS lock */ | |
2112 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
2113 | return 0; | |
2114 | ||
2115 | /* Issue PHY reset */ | |
2116 | e1000_phy_hw_reset(hw); | |
2117 | mdelay(5); | |
2118 | } | |
2119 | /* Disable GigE link negotiation */ | |
2120 | phy_ctrl = er32(PHY_CTRL); | |
2121 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2122 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2123 | ew32(PHY_CTRL, phy_ctrl); | |
2124 | ||
ad68076e BA |
2125 | /* |
2126 | * Call gig speed drop workaround on Gig disable before accessing | |
2127 | * any PHY registers | |
2128 | */ | |
bc7f75fa AK |
2129 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2130 | ||
2131 | /* unable to acquire PCS lock */ | |
2132 | return -E1000_ERR_PHY; | |
2133 | } | |
2134 | ||
2135 | /** | |
ad68076e | 2136 | * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
bc7f75fa | 2137 | * @hw: pointer to the HW structure |
489815ce | 2138 | * @state: boolean value used to set the current Kumeran workaround state |
bc7f75fa AK |
2139 | * |
2140 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE | |
2141 | * /disabled - FALSE). | |
2142 | **/ | |
2143 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
2144 | bool state) | |
2145 | { | |
2146 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2147 | ||
2148 | if (hw->mac.type != e1000_ich8lan) { | |
2149 | hw_dbg(hw, "Workaround applies to ICH8 only.\n"); | |
2150 | return; | |
2151 | } | |
2152 | ||
2153 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
2154 | } | |
2155 | ||
2156 | /** | |
2157 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
2158 | * @hw: pointer to the HW structure | |
2159 | * | |
2160 | * Workaround for 82566 power-down on D3 entry: | |
2161 | * 1) disable gigabit link | |
2162 | * 2) write VR power-down enable | |
2163 | * 3) read it back | |
2164 | * Continue if successful, else issue LCD reset and repeat | |
2165 | **/ | |
2166 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
2167 | { | |
2168 | u32 reg; | |
2169 | u16 data; | |
2170 | u8 retry = 0; | |
2171 | ||
2172 | if (hw->phy.type != e1000_phy_igp_3) | |
2173 | return; | |
2174 | ||
2175 | /* Try the workaround twice (if needed) */ | |
2176 | do { | |
2177 | /* Disable link */ | |
2178 | reg = er32(PHY_CTRL); | |
2179 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2180 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2181 | ew32(PHY_CTRL, reg); | |
2182 | ||
ad68076e BA |
2183 | /* |
2184 | * Call gig speed drop workaround on Gig disable before | |
2185 | * accessing any PHY registers | |
2186 | */ | |
bc7f75fa AK |
2187 | if (hw->mac.type == e1000_ich8lan) |
2188 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2189 | ||
2190 | /* Write VR power-down enable */ | |
2191 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2192 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2193 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
2194 | ||
2195 | /* Read it back and test */ | |
2196 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2197 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2198 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
2199 | break; | |
2200 | ||
2201 | /* Issue PHY reset and repeat at most one more time */ | |
2202 | reg = er32(CTRL); | |
2203 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
2204 | retry++; | |
2205 | } while (retry); | |
2206 | } | |
2207 | ||
2208 | /** | |
2209 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
2210 | * @hw: pointer to the HW structure | |
2211 | * | |
2212 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
489815ce | 2213 | * LPLU, Gig disable, MDIC PHY reset): |
bc7f75fa AK |
2214 | * 1) Set Kumeran Near-end loopback |
2215 | * 2) Clear Kumeran Near-end loopback | |
2216 | * Should only be called for ICH8[m] devices with IGP_3 Phy. | |
2217 | **/ | |
2218 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
2219 | { | |
2220 | s32 ret_val; | |
2221 | u16 reg_data; | |
2222 | ||
2223 | if ((hw->mac.type != e1000_ich8lan) || | |
2224 | (hw->phy.type != e1000_phy_igp_3)) | |
2225 | return; | |
2226 | ||
2227 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2228 | ®_data); | |
2229 | if (ret_val) | |
2230 | return; | |
2231 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2232 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2233 | reg_data); | |
2234 | if (ret_val) | |
2235 | return; | |
2236 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2237 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2238 | reg_data); | |
2239 | } | |
2240 | ||
97ac8cae BA |
2241 | /** |
2242 | * e1000e_disable_gig_wol_ich8lan - disable gig during WoL | |
2243 | * @hw: pointer to the HW structure | |
2244 | * | |
2245 | * During S0 to Sx transition, it is possible the link remains at gig | |
2246 | * instead of negotiating to a lower speed. Before going to Sx, set | |
2247 | * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation | |
2248 | * to a lower speed. | |
2249 | * | |
2250 | * Should only be called for ICH9 devices. | |
2251 | **/ | |
2252 | void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) | |
2253 | { | |
2254 | u32 phy_ctrl; | |
2255 | ||
2256 | if (hw->mac.type == e1000_ich9lan) { | |
2257 | phy_ctrl = er32(PHY_CTRL); | |
2258 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | | |
2259 | E1000_PHY_CTRL_GBE_DISABLE; | |
2260 | ew32(PHY_CTRL, phy_ctrl); | |
2261 | } | |
2262 | ||
2263 | return; | |
2264 | } | |
2265 | ||
bc7f75fa AK |
2266 | /** |
2267 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
2268 | * @hw: pointer to the HW structure | |
2269 | * | |
2270 | * Return the LED back to the default configuration. | |
2271 | **/ | |
2272 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
2273 | { | |
2274 | if (hw->phy.type == e1000_phy_ife) | |
2275 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
2276 | ||
2277 | ew32(LEDCTL, hw->mac.ledctl_default); | |
2278 | return 0; | |
2279 | } | |
2280 | ||
2281 | /** | |
489815ce | 2282 | * e1000_led_on_ich8lan - Turn LEDs on |
bc7f75fa AK |
2283 | * @hw: pointer to the HW structure |
2284 | * | |
489815ce | 2285 | * Turn on the LEDs. |
bc7f75fa AK |
2286 | **/ |
2287 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
2288 | { | |
2289 | if (hw->phy.type == e1000_phy_ife) | |
2290 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2291 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
2292 | ||
2293 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
2294 | return 0; | |
2295 | } | |
2296 | ||
2297 | /** | |
489815ce | 2298 | * e1000_led_off_ich8lan - Turn LEDs off |
bc7f75fa AK |
2299 | * @hw: pointer to the HW structure |
2300 | * | |
489815ce | 2301 | * Turn off the LEDs. |
bc7f75fa AK |
2302 | **/ |
2303 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
2304 | { | |
2305 | if (hw->phy.type == e1000_phy_ife) | |
2306 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2307 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
2308 | ||
2309 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
2310 | return 0; | |
2311 | } | |
2312 | ||
2313 | /** | |
2314 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
2315 | * @hw: pointer to the HW structure | |
2316 | * | |
2317 | * Clears hardware counters specific to the silicon family and calls | |
2318 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
2319 | **/ | |
2320 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
2321 | { | |
2322 | u32 temp; | |
2323 | ||
2324 | e1000e_clear_hw_cntrs_base(hw); | |
2325 | ||
2326 | temp = er32(ALGNERRC); | |
2327 | temp = er32(RXERRC); | |
2328 | temp = er32(TNCRS); | |
2329 | temp = er32(CEXTERR); | |
2330 | temp = er32(TSCTC); | |
2331 | temp = er32(TSCTFC); | |
2332 | ||
2333 | temp = er32(MGTPRC); | |
2334 | temp = er32(MGTPDC); | |
2335 | temp = er32(MGTPTC); | |
2336 | ||
2337 | temp = er32(IAC); | |
2338 | temp = er32(ICRXOC); | |
2339 | ||
2340 | } | |
2341 | ||
2342 | static struct e1000_mac_operations ich8_mac_ops = { | |
2343 | .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, | |
2344 | .check_for_link = e1000e_check_for_copper_link, | |
2345 | .cleanup_led = e1000_cleanup_led_ich8lan, | |
2346 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, | |
2347 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
2348 | .get_link_up_info = e1000_get_link_up_info_ich8lan, | |
2349 | .led_on = e1000_led_on_ich8lan, | |
2350 | .led_off = e1000_led_off_ich8lan, | |
e2de3eb6 | 2351 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
2352 | .reset_hw = e1000_reset_hw_ich8lan, |
2353 | .init_hw = e1000_init_hw_ich8lan, | |
2354 | .setup_link = e1000_setup_link_ich8lan, | |
2355 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, | |
2356 | }; | |
2357 | ||
2358 | static struct e1000_phy_operations ich8_phy_ops = { | |
2359 | .acquire_phy = e1000_acquire_swflag_ich8lan, | |
2360 | .check_reset_block = e1000_check_reset_block_ich8lan, | |
2361 | .commit_phy = NULL, | |
2362 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, | |
2363 | .get_cfg_done = e1000e_get_cfg_done, | |
2364 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
2365 | .get_phy_info = e1000_get_phy_info_ich8lan, | |
2366 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
2367 | .release_phy = e1000_release_swflag_ich8lan, | |
2368 | .reset_phy = e1000_phy_hw_reset_ich8lan, | |
2369 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, | |
2370 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
2371 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
2372 | }; | |
2373 | ||
2374 | static struct e1000_nvm_operations ich8_nvm_ops = { | |
2375 | .acquire_nvm = e1000_acquire_swflag_ich8lan, | |
2376 | .read_nvm = e1000_read_nvm_ich8lan, | |
2377 | .release_nvm = e1000_release_swflag_ich8lan, | |
2378 | .update_nvm = e1000_update_nvm_checksum_ich8lan, | |
2379 | .valid_led_default = e1000_valid_led_default_ich8lan, | |
2380 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, | |
2381 | .write_nvm = e1000_write_nvm_ich8lan, | |
2382 | }; | |
2383 | ||
2384 | struct e1000_info e1000_ich8_info = { | |
2385 | .mac = e1000_ich8lan, | |
2386 | .flags = FLAG_HAS_WOL | |
97ac8cae | 2387 | | FLAG_IS_ICH |
bc7f75fa AK |
2388 | | FLAG_RX_CSUM_ENABLED |
2389 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2390 | | FLAG_HAS_AMT | |
2391 | | FLAG_HAS_FLASH | |
2392 | | FLAG_APME_IN_WUC, | |
2393 | .pba = 8, | |
69e3fd8c | 2394 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
2395 | .mac_ops = &ich8_mac_ops, |
2396 | .phy_ops = &ich8_phy_ops, | |
2397 | .nvm_ops = &ich8_nvm_ops, | |
2398 | }; | |
2399 | ||
2400 | struct e1000_info e1000_ich9_info = { | |
2401 | .mac = e1000_ich9lan, | |
2402 | .flags = FLAG_HAS_JUMBO_FRAMES | |
97ac8cae | 2403 | | FLAG_IS_ICH |
bc7f75fa AK |
2404 | | FLAG_HAS_WOL |
2405 | | FLAG_RX_CSUM_ENABLED | |
2406 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2407 | | FLAG_HAS_AMT | |
2408 | | FLAG_HAS_ERT | |
2409 | | FLAG_HAS_FLASH | |
2410 | | FLAG_APME_IN_WUC, | |
2411 | .pba = 10, | |
69e3fd8c | 2412 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
2413 | .mac_ops = &ich8_mac_ops, |
2414 | .phy_ops = &ich8_phy_ops, | |
2415 | .nvm_ops = &ich8_nvm_ops, | |
2416 | }; | |
2417 |