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e1000e: do not error out on identification LED init failure
[deliverable/linux.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
bc7f75fa
AK		 55 */
56
bc7f75fa
AK		 57#include "e1000.h"
58
59#define ICH_FLASH_GFPREG 0x0000
60#define ICH_FLASH_HSFSTS 0x0004
61#define ICH_FLASH_HSFCTL 0x0006
62#define ICH_FLASH_FADDR 0x0008
63#define ICH_FLASH_FDATA0 0x0010
4a770358 64#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 65
66#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72#define ICH_CYCLE_READ 0
73#define ICH_CYCLE_WRITE 2
74#define ICH_CYCLE_ERASE 3
75
76#define FLASH_GFPREG_BASE_MASK 0x1FFF
77#define FLASH_SECTOR_ADDR_SHIFT 12
78
79#define ICH_FLASH_SEG_SIZE_256 256
80#define ICH_FLASH_SEG_SIZE_4K 4096
81#define ICH_FLASH_SEG_SIZE_8K 8192
82#define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86
87#define E1000_ICH_MNG_IAMT_MODE 0x2
88
89#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
92 (ID_LED_DEF1_DEF2))
93
94#define E1000_ICH_NVM_SIG_WORD 0x13
95#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 96#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 98
99#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
100
101#define E1000_FEXTNVM_SW_CONFIG 1
102#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
103
104#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
105
106#define E1000_ICH_RAR_ENTRIES 7
107
108#define PHY_PAGE_SHIFT 5
109#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
113
114#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
117
a4f58f54
BA		 118#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
119
53ac5a88
BA		 120#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
121
f523d211
BA		 122/* SMBus Address Phy Register */
123#define HV_SMB_ADDR PHY_REG(768, 26)
124#define HV_SMB_ADDR_PEC_EN 0x0200
125#define HV_SMB_ADDR_VALID 0x0080
126
127/* Strapping Option Register - RO */
128#define E1000_STRAP 0x0000C
129#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
131
fa2ce13c
BA		 132/* OEM Bits Phy Register */
133#define HV_OEM_BITS PHY_REG(768, 25)
134#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 135#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 136#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
137
1d5846b9
BA		 138#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
140
bc7f75fa
AK		 141/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
142/* Offset 04h HSFSTS */
143union ich8_hws_flash_status {
144 struct ich8_hsfsts {
145 u16 flcdone :1; /* bit 0 Flash Cycle Done */
146 u16 flcerr :1; /* bit 1 Flash Cycle Error */
147 u16 dael :1; /* bit 2 Direct Access error Log */
148 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
149 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
150 u16 reserved1 :2; /* bit 13:6 Reserved */
151 u16 reserved2 :6; /* bit 13:6 Reserved */
152 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
153 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
154 } hsf_status;
155 u16 regval;
156};
157
158/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
159/* Offset 06h FLCTL */
160union ich8_hws_flash_ctrl {
161 struct ich8_hsflctl {
162 u16 flcgo :1; /* 0 Flash Cycle Go */
163 u16 flcycle :2; /* 2:1 Flash Cycle */
164 u16 reserved :5; /* 7:3 Reserved */
165 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
166 u16 flockdn :6; /* 15:10 Reserved */
167 } hsf_ctrl;
168 u16 regval;
169};
170
171/* ICH Flash Region Access Permissions */
172union ich8_hws_flash_regacc {
173 struct ich8_flracc {
174 u32 grra :8; /* 0:7 GbE region Read Access */
175 u32 grwa :8; /* 8:15 GbE region Write Access */
176 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
177 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
178 } hsf_flregacc;
179 u16 regval;
180};
181
4a770358
BA		 182/* ICH Flash Protected Region */
183union ich8_flash_protected_range {
184 struct ich8_pr {
185 u32 base:13; /* 0:12 Protected Range Base */
186 u32 reserved1:2; /* 13:14 Reserved */
187 u32 rpe:1; /* 15 Read Protection Enable */
188 u32 limit:13; /* 16:28 Protected Range Limit */
189 u32 reserved2:2; /* 29:30 Reserved */
190 u32 wpe:1; /* 31 Write Protection Enable */
191 } range;
192 u32 regval;
193};
194
bc7f75fa
AK		 195static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
196static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
197static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
198static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
199static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
200static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
201 u32 offset, u8 byte);
f4187b56
BA		 202static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
203 u8 *data);
bc7f75fa
AK		 204static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
205 u16 *data);
206static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
207 u8 size, u16 *data);
208static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
209static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 210static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 211static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
212static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
213static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
214static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
215static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
216static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
217static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
218static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 219static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
f523d211 220static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 221static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
bc7f75fa
AK		 222
223static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
224{
225 return readw(hw->flash_address + reg);
226}
227
228static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
229{
230 return readl(hw->flash_address + reg);
231}
232
233static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
234{
235 writew(val, hw->flash_address + reg);
236}
237
238static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
239{
240 writel(val, hw->flash_address + reg);
241}
242
243#define er16flash(reg) __er16flash(hw, (reg))
244#define er32flash(reg) __er32flash(hw, (reg))
245#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
246#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
247
a4f58f54
BA		 248/**
249 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
250 * @hw: pointer to the HW structure
251 *
252 * Initialize family-specific PHY parameters and function pointers.
253 **/
254static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
255{
256 struct e1000_phy_info *phy = &hw->phy;
257 s32 ret_val = 0;
258
259 phy->addr = 1;
260 phy->reset_delay_us = 100;
261
262 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
94d8186a
BA		 263 phy->ops.read_reg = e1000_read_phy_reg_hv;
264 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 265 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
266 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 267 phy->ops.write_reg = e1000_write_phy_reg_hv;
268 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
a4f58f54
BA		 269 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
270
271 phy->id = e1000_phy_unknown;
272 e1000e_get_phy_id(hw);
273 phy->type = e1000e_get_phy_type_from_id(phy->id);
274
275 if (phy->type == e1000_phy_82577) {
276 phy->ops.check_polarity = e1000_check_polarity_82577;
277 phy->ops.force_speed_duplex =
278 e1000_phy_force_speed_duplex_82577;
279 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 280 phy->ops.get_info = e1000_get_phy_info_82577;
281 phy->ops.commit = e1000e_phy_sw_reset;
a4f58f54
BA		 282 }
283
284 return ret_val;
285}
286
bc7f75fa
AK		 287/**
288 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
289 * @hw: pointer to the HW structure
290 *
291 * Initialize family-specific PHY parameters and function pointers.
292 **/
293static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
294{
295 struct e1000_phy_info *phy = &hw->phy;
296 s32 ret_val;
297 u16 i = 0;
298
299 phy->addr = 1;
300 phy->reset_delay_us = 100;
301
97ac8cae
BA		 302 /*
303 * We may need to do this twice - once for IGP and if that fails,
304 * we'll set BM func pointers and try again
305 */
306 ret_val = e1000e_determine_phy_address(hw);
307 if (ret_val) {
94d8186a
BA		 308 phy->ops.write_reg = e1000e_write_phy_reg_bm;
309 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae
BA		 310 ret_val = e1000e_determine_phy_address(hw);
311 if (ret_val)
312 return ret_val;
313 }
314
bc7f75fa
AK		 315 phy->id = 0;
316 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
317 (i++ < 100)) {
318 msleep(1);
319 ret_val = e1000e_get_phy_id(hw);
320 if (ret_val)
321 return ret_val;
322 }
323
324 /* Verify phy id */
325 switch (phy->id) {
326 case IGP03E1000_E_PHY_ID:
327 phy->type = e1000_phy_igp_3;
328 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 329 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
330 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
bc7f75fa
AK		 331 break;
332 case IFE_E_PHY_ID:
333 case IFE_PLUS_E_PHY_ID:
334 case IFE_C_E_PHY_ID:
335 phy->type = e1000_phy_ife;
336 phy->autoneg_mask = E1000_ALL_NOT_GIG;
337 break;
97ac8cae
BA		 338 case BME1000_E_PHY_ID:
339 phy->type = e1000_phy_bm;
340 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 341 phy->ops.read_reg = e1000e_read_phy_reg_bm;
342 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343 phy->ops.commit = e1000e_phy_sw_reset;
97ac8cae 344 break;
bc7f75fa
AK		 345 default:
346 return -E1000_ERR_PHY;
347 break;
348 }
349
a4f58f54
BA		 350 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
351
bc7f75fa
AK		 352 return 0;
353}
354
355/**
356 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
357 * @hw: pointer to the HW structure
358 *
359 * Initialize family-specific NVM parameters and function
360 * pointers.
361 **/
362static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
363{
364 struct e1000_nvm_info *nvm = &hw->nvm;
365 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 366 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 367 u16 i;
368
ad68076e 369 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 370 if (!hw->flash_address) {
3bb99fe2 371 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 372 return -E1000_ERR_CONFIG;
373 }
374
375 nvm->type = e1000_nvm_flash_sw;
376
377 gfpreg = er32flash(ICH_FLASH_GFPREG);
378
ad68076e
BA		 379 /*
380 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 381 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 382 * the overall size.
383 */
bc7f75fa
AK		 384 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
385 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
386
387 /* flash_base_addr is byte-aligned */
388 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
389
ad68076e
BA		 390 /*
391 * find total size of the NVM, then cut in half since the total
392 * size represents two separate NVM banks.
393 */
bc7f75fa
AK		 394 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
395 << FLASH_SECTOR_ADDR_SHIFT;
396 nvm->flash_bank_size /= 2;
397 /* Adjust to word count */
398 nvm->flash_bank_size /= sizeof(u16);
399
400 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
401
402 /* Clear shadow ram */
403 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 404 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 405 dev_spec->shadow_ram[i].value = 0xFFFF;
406 }
407
408 return 0;
409}
410
411/**
412 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
413 * @hw: pointer to the HW structure
414 *
415 * Initialize family-specific MAC parameters and function
416 * pointers.
417 **/
418static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
419{
420 struct e1000_hw *hw = &adapter->hw;
421 struct e1000_mac_info *mac = &hw->mac;
422
423 /* Set media type function pointer */
318a94d6 424 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 425
426 /* Set mta register count */
427 mac->mta_reg_count = 32;
428 /* Set rar entry count */
429 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
430 if (mac->type == e1000_ich8lan)
431 mac->rar_entry_count--;
432 /* Set if manageability features are enabled. */
564ea9bb 433 mac->arc_subsystem_valid = true;
bc7f75fa 434
a4f58f54
BA		 435 /* LED operations */
436 switch (mac->type) {
437 case e1000_ich8lan:
438 case e1000_ich9lan:
439 case e1000_ich10lan:
440 /* ID LED init */
441 mac->ops.id_led_init = e1000e_id_led_init;
442 /* setup LED */
443 mac->ops.setup_led = e1000e_setup_led_generic;
444 /* cleanup LED */
445 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
446 /* turn on/off LED */
447 mac->ops.led_on = e1000_led_on_ich8lan;
448 mac->ops.led_off = e1000_led_off_ich8lan;
449 break;
450 case e1000_pchlan:
451 /* ID LED init */
452 mac->ops.id_led_init = e1000_id_led_init_pchlan;
453 /* setup LED */
454 mac->ops.setup_led = e1000_setup_led_pchlan;
455 /* cleanup LED */
456 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
457 /* turn on/off LED */
458 mac->ops.led_on = e1000_led_on_pchlan;
459 mac->ops.led_off = e1000_led_off_pchlan;
460 break;
461 default:
462 break;
463 }
464
bc7f75fa
AK		 465 /* Enable PCS Lock-loss workaround for ICH8 */
466 if (mac->type == e1000_ich8lan)
564ea9bb 467 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 468
469 return 0;
470}
471
7d3cabbc
BA		 472/**
473 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
474 * @hw: pointer to the HW structure
475 *
476 * Checks to see of the link status of the hardware has changed. If a
477 * change in link status has been detected, then we read the PHY registers
478 * to get the current speed/duplex if link exists.
479 **/
480static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
481{
482 struct e1000_mac_info *mac = &hw->mac;
483 s32 ret_val;
484 bool link;
485
486 /*
487 * We only want to go out to the PHY registers to see if Auto-Neg
488 * has completed and/or if our link status has changed. The
489 * get_link_status flag is set upon receiving a Link Status
490 * Change or Rx Sequence Error interrupt.
491 */
492 if (!mac->get_link_status) {
493 ret_val = 0;
494 goto out;
495 }
496
7d3cabbc
BA		 497 /*
498 * First we want to see if the MII Status Register reports
499 * link. If so, then we want to get the current speed/duplex
500 * of the PHY.
501 */
502 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
503 if (ret_val)
504 goto out;
505
1d5846b9
BA		 506 if (hw->mac.type == e1000_pchlan) {
507 ret_val = e1000_k1_gig_workaround_hv(hw, link);
508 if (ret_val)
509 goto out;
510 }
511
7d3cabbc
BA		 512 if (!link)
513 goto out; /* No link detected */
514
515 mac->get_link_status = false;
516
517 if (hw->phy.type == e1000_phy_82578) {
518 ret_val = e1000_link_stall_workaround_hv(hw);
519 if (ret_val)
520 goto out;
521 }
522
523 /*
524 * Check if there was DownShift, must be checked
525 * immediately after link-up
526 */
527 e1000e_check_downshift(hw);
528
529 /*
530 * If we are forcing speed/duplex, then we simply return since
531 * we have already determined whether we have link or not.
532 */
533 if (!mac->autoneg) {
534 ret_val = -E1000_ERR_CONFIG;
535 goto out;
536 }
537
538 /*
539 * Auto-Neg is enabled. Auto Speed Detection takes care
540 * of MAC speed/duplex configuration. So we only need to
541 * configure Collision Distance in the MAC.
542 */
543 e1000e_config_collision_dist(hw);
544
545 /*
546 * Configure Flow Control now that Auto-Neg has completed.
547 * First, we need to restore the desired flow control
548 * settings because we may have had to re-autoneg with a
549 * different link partner.
550 */
551 ret_val = e1000e_config_fc_after_link_up(hw);
552 if (ret_val)
3bb99fe2 553 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 554
555out:
556 return ret_val;
557}
558
69e3fd8c 559static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 560{
561 struct e1000_hw *hw = &adapter->hw;
562 s32 rc;
563
564 rc = e1000_init_mac_params_ich8lan(adapter);
565 if (rc)
566 return rc;
567
568 rc = e1000_init_nvm_params_ich8lan(hw);
569 if (rc)
570 return rc;
571
a4f58f54
BA		 572 if (hw->mac.type == e1000_pchlan)
573 rc = e1000_init_phy_params_pchlan(hw);
574 else
575 rc = e1000_init_phy_params_ich8lan(hw);
bc7f75fa
AK		 576 if (rc)
577 return rc;
578
2adc55c9
BA		 579 if (adapter->hw.phy.type == e1000_phy_ife) {
580 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
581 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
582 }
583
bc7f75fa
AK		 584 if ((adapter->hw.mac.type == e1000_ich8lan) &&
585 (adapter->hw.phy.type == e1000_phy_igp_3))
586 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
587
588 return 0;
589}
590
717d438d 591static DEFINE_MUTEX(nvm_mutex);
717d438d 592
ca15df58
BA		 593/**
594 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
595 * @hw: pointer to the HW structure
596 *
597 * Acquires the mutex for performing NVM operations.
598 **/
599static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
600{
601 mutex_lock(&nvm_mutex);
602
603 return 0;
604}
605
606/**
607 * e1000_release_nvm_ich8lan - Release NVM mutex
608 * @hw: pointer to the HW structure
609 *
610 * Releases the mutex used while performing NVM operations.
611 **/
612static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
613{
614 mutex_unlock(&nvm_mutex);
615
616 return;
617}
618
619static DEFINE_MUTEX(swflag_mutex);
620
bc7f75fa
AK		 621/**
622 * e1000_acquire_swflag_ich8lan - Acquire software control flag
623 * @hw: pointer to the HW structure
624 *
ca15df58
BA		 625 * Acquires the software control flag for performing PHY and select
626 * MAC CSR accesses.
bc7f75fa
AK		 627 **/
628static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
629{
373a88d7
BA		 630 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
631 s32 ret_val = 0;
bc7f75fa 632
95b866d5 633 might_sleep();
717d438d 634
ca15df58 635 mutex_lock(&swflag_mutex);
717d438d 636
bc7f75fa
AK		 637 while (timeout) {
638 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 639 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
640 break;
bc7f75fa 641
373a88d7
BA		 642 mdelay(1);
643 timeout--;
644 }
645
646 if (!timeout) {
3bb99fe2 647 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 648 ret_val = -E1000_ERR_CONFIG;
649 goto out;
650 }
651
53ac5a88 652 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 653
654 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
655 ew32(EXTCNF_CTRL, extcnf_ctrl);
656
657 while (timeout) {
658 extcnf_ctrl = er32(EXTCNF_CTRL);
659 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
660 break;
a4f58f54 661
bc7f75fa
AK		 662 mdelay(1);
663 timeout--;
664 }
665
666 if (!timeout) {
3bb99fe2 667 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 668 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
669 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 670 ret_val = -E1000_ERR_CONFIG;
671 goto out;
bc7f75fa
AK		 672 }
673
373a88d7
BA		 674out:
675 if (ret_val)
ca15df58 676 mutex_unlock(&swflag_mutex);
373a88d7
BA		 677
678 return ret_val;
bc7f75fa
AK		 679}
680
681/**
682 * e1000_release_swflag_ich8lan - Release software control flag
683 * @hw: pointer to the HW structure
684 *
ca15df58
BA		 685 * Releases the software control flag for performing PHY and select
686 * MAC CSR accesses.
bc7f75fa
AK		 687 **/
688static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
689{
690 u32 extcnf_ctrl;
691
692 extcnf_ctrl = er32(EXTCNF_CTRL);
693 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
694 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 695
ca15df58
BA		 696 mutex_unlock(&swflag_mutex);
697
698 return;
bc7f75fa
AK		 699}
700
4662e82b
BA		 701/**
702 * e1000_check_mng_mode_ich8lan - Checks management mode
703 * @hw: pointer to the HW structure
704 *
705 * This checks if the adapter has manageability enabled.
706 * This is a function pointer entry point only called by read/write
707 * routines for the PHY and NVM parts.
708 **/
709static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
710{
711 u32 fwsm = er32(FWSM);
712
713 return (fwsm & E1000_FWSM_MODE_MASK) ==
714 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
715}
716
bc7f75fa
AK		 717/**
718 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
719 * @hw: pointer to the HW structure
720 *
721 * Checks if firmware is blocking the reset of the PHY.
722 * This is a function pointer entry point only called by
723 * reset routines.
724 **/
725static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
726{
727 u32 fwsm;
728
729 fwsm = er32(FWSM);
730
731 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
732}
733
734/**
735 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
736 * @hw: pointer to the HW structure
737 *
738 * Forces the speed and duplex settings of the PHY.
739 * This is a function pointer entry point only called by
740 * PHY setup routines.
741 **/
742static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
743{
744 struct e1000_phy_info *phy = &hw->phy;
745 s32 ret_val;
746 u16 data;
747 bool link;
748
749 if (phy->type != e1000_phy_ife) {
750 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
751 return ret_val;
752 }
753
754 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
755 if (ret_val)
756 return ret_val;
757
758 e1000e_phy_force_speed_duplex_setup(hw, &data);
759
760 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
761 if (ret_val)
762 return ret_val;
763
764 /* Disable MDI-X support for 10/100 */
765 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
766 if (ret_val)
767 return ret_val;
768
769 data &= ~IFE_PMC_AUTO_MDIX;
770 data &= ~IFE_PMC_FORCE_MDIX;
771
772 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
773 if (ret_val)
774 return ret_val;
775
3bb99fe2 776 e_dbg("IFE PMC: %X\n", data);
bc7f75fa
AK		 777
778 udelay(1);
779
318a94d6 780 if (phy->autoneg_wait_to_complete) {
3bb99fe2 781 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
bc7f75fa
AK		 782
783 ret_val = e1000e_phy_has_link_generic(hw,
784 PHY_FORCE_LIMIT,
785 100000,
786 &link);
787 if (ret_val)
788 return ret_val;
789
790 if (!link)
3bb99fe2 791 e_dbg("Link taking longer than expected.\n");
bc7f75fa
AK		 792
793 /* Try once more */
794 ret_val = e1000e_phy_has_link_generic(hw,
795 PHY_FORCE_LIMIT,
796 100000,
797 &link);
798 if (ret_val)
799 return ret_val;
800 }
801
802 return 0;
803}
804
f523d211
BA		 805/**
806 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
807 * @hw: pointer to the HW structure
808 *
809 * SW should configure the LCD from the NVM extended configuration region
810 * as a workaround for certain parts.
811 **/
812static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
813{
814 struct e1000_phy_info *phy = &hw->phy;
815 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
816 s32 ret_val;
817 u16 word_addr, reg_data, reg_addr, phy_page = 0;
818
94d8186a 819 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 820 if (ret_val)
821 return ret_val;
822
823 /*
824 * Initialize the PHY from the NVM on ICH platforms. This
825 * is needed due to an issue where the NVM configuration is
826 * not properly autoloaded after power transitions.
827 * Therefore, after each PHY reset, we will load the
828 * configuration data out of the NVM manually.
829 */
830 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
831 (hw->mac.type == e1000_pchlan)) {
832 struct e1000_adapter *adapter = hw->adapter;
833
834 /* Check if SW needs to configure the PHY */
835 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
836 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
837 (hw->mac.type == e1000_pchlan))
838 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
839 else
840 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
841
842 data = er32(FEXTNVM);
843 if (!(data & sw_cfg_mask))
844 goto out;
845
846 /* Wait for basic configuration completes before proceeding */
847 e1000_lan_init_done_ich8lan(hw);
848
849 /*
850 * Make sure HW does not configure LCD from PHY
851 * extended configuration before SW configuration
852 */
853 data = er32(EXTCNF_CTRL);
854 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
855 goto out;
856
857 cnf_size = er32(EXTCNF_SIZE);
858 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
859 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
860 if (!cnf_size)
861 goto out;
862
863 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
864 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
865
866 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
867 (hw->mac.type == e1000_pchlan)) {
868 /*
869 * HW configures the SMBus address and LEDs when the
870 * OEM and LCD Write Enable bits are set in the NVM.
871 * When both NVM bits are cleared, SW will configure
872 * them instead.
873 */
874 data = er32(STRAP);
875 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
876 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
877 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
878 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
879 reg_data);
880 if (ret_val)
881 goto out;
882
883 data = er32(LEDCTL);
884 ret_val = e1000_write_phy_reg_hv_locked(hw,
885 HV_LED_CONFIG,
886 (u16)data);
887 if (ret_val)
888 goto out;
889 }
890 /* Configure LCD from extended configuration region. */
891
892 /* cnf_base_addr is in DWORD */
893 word_addr = (u16)(cnf_base_addr << 1);
894
895 for (i = 0; i < cnf_size; i++) {
896 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
897 &reg_data);
898 if (ret_val)
899 goto out;
900
901 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
902 1, &reg_addr);
903 if (ret_val)
904 goto out;
905
906 /* Save off the PHY page for future writes. */
907 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
908 phy_page = reg_data;
909 continue;
910 }
911
912 reg_addr &= PHY_REG_MASK;
913 reg_addr |= phy_page;
914
94d8186a 915 ret_val = phy->ops.write_reg_locked(hw,
f523d211
BA		 916 (u32)reg_addr,
917 reg_data);
918 if (ret_val)
919 goto out;
920 }
921 }
922
923out:
94d8186a 924 hw->phy.ops.release(hw);
f523d211
BA		 925 return ret_val;
926}
927
1d5846b9
BA		 928/**
929 * e1000_k1_gig_workaround_hv - K1 Si workaround
930 * @hw: pointer to the HW structure
931 * @link: link up bool flag
932 *
933 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
934 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
935 * If link is down, the function will restore the default K1 setting located
936 * in the NVM.
937 **/
938static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
939{
940 s32 ret_val = 0;
941 u16 status_reg = 0;
942 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
943
944 if (hw->mac.type != e1000_pchlan)
945 goto out;
946
947 /* Wrap the whole flow with the sw flag */
94d8186a 948 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 949 if (ret_val)
950 goto out;
951
952 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
953 if (link) {
954 if (hw->phy.type == e1000_phy_82578) {
94d8186a 955 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 956 &status_reg);
957 if (ret_val)
958 goto release;
959
960 status_reg &= BM_CS_STATUS_LINK_UP |
961 BM_CS_STATUS_RESOLVED |
962 BM_CS_STATUS_SPEED_MASK;
963
964 if (status_reg == (BM_CS_STATUS_LINK_UP |
965 BM_CS_STATUS_RESOLVED |
966 BM_CS_STATUS_SPEED_1000))
967 k1_enable = false;
968 }
969
970 if (hw->phy.type == e1000_phy_82577) {
94d8186a 971 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 972 &status_reg);
973 if (ret_val)
974 goto release;
975
976 status_reg &= HV_M_STATUS_LINK_UP |
977 HV_M_STATUS_AUTONEG_COMPLETE |
978 HV_M_STATUS_SPEED_MASK;
979
980 if (status_reg == (HV_M_STATUS_LINK_UP |
981 HV_M_STATUS_AUTONEG_COMPLETE |
982 HV_M_STATUS_SPEED_1000))
983 k1_enable = false;
984 }
985
986 /* Link stall fix for link up */
94d8186a 987 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 988 0x0100);
989 if (ret_val)
990 goto release;
991
992 } else {
993 /* Link stall fix for link down */
94d8186a 994 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 995 0x4100);
996 if (ret_val)
997 goto release;
998 }
999
1000 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1001
1002release:
94d8186a 1003 hw->phy.ops.release(hw);
1d5846b9
BA		 1004out:
1005 return ret_val;
1006}
1007
1008/**
1009 * e1000_configure_k1_ich8lan - Configure K1 power state
1010 * @hw: pointer to the HW structure
1011 * @enable: K1 state to configure
1012 *
1013 * Configure the K1 power state based on the provided parameter.
1014 * Assumes semaphore already acquired.
1015 *
1016 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1017 **/
bb436b20 1018s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1019{
1020 s32 ret_val = 0;
1021 u32 ctrl_reg = 0;
1022 u32 ctrl_ext = 0;
1023 u32 reg = 0;
1024 u16 kmrn_reg = 0;
1025
1026 ret_val = e1000e_read_kmrn_reg_locked(hw,
1027 E1000_KMRNCTRLSTA_K1_CONFIG,
1028 &kmrn_reg);
1029 if (ret_val)
1030 goto out;
1031
1032 if (k1_enable)
1033 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1034 else
1035 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1036
1037 ret_val = e1000e_write_kmrn_reg_locked(hw,
1038 E1000_KMRNCTRLSTA_K1_CONFIG,
1039 kmrn_reg);
1040 if (ret_val)
1041 goto out;
1042
1043 udelay(20);
1044 ctrl_ext = er32(CTRL_EXT);
1045 ctrl_reg = er32(CTRL);
1046
1047 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1048 reg |= E1000_CTRL_FRCSPD;
1049 ew32(CTRL, reg);
1050
1051 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1052 udelay(20);
1053 ew32(CTRL, ctrl_reg);
1054 ew32(CTRL_EXT, ctrl_ext);
1055 udelay(20);
1056
1057out:
1058 return ret_val;
1059}
1060
f523d211
BA		 1061/**
1062 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1063 * @hw: pointer to the HW structure
1064 * @d0_state: boolean if entering d0 or d3 device state
1065 *
1066 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1067 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1068 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1069 **/
1070static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1071{
1072 s32 ret_val = 0;
1073 u32 mac_reg;
1074 u16 oem_reg;
1075
1076 if (hw->mac.type != e1000_pchlan)
1077 return ret_val;
1078
94d8186a 1079 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1080 if (ret_val)
1081 return ret_val;
1082
1083 mac_reg = er32(EXTCNF_CTRL);
1084 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1085 goto out;
1086
1087 mac_reg = er32(FEXTNVM);
1088 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1089 goto out;
1090
1091 mac_reg = er32(PHY_CTRL);
1092
94d8186a 1093 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1094 if (ret_val)
1095 goto out;
1096
1097 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1098
1099 if (d0_state) {
1100 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1101 oem_reg |= HV_OEM_BITS_GBE_DIS;
1102
1103 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1104 oem_reg |= HV_OEM_BITS_LPLU;
1105 } else {
1106 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1107 oem_reg |= HV_OEM_BITS_GBE_DIS;
1108
1109 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1110 oem_reg |= HV_OEM_BITS_LPLU;
1111 }
1112 /* Restart auto-neg to activate the bits */
1113 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1114 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1115
1116out:
94d8186a 1117 hw->phy.ops.release(hw);
f523d211
BA		 1118
1119 return ret_val;
1120}
1121
1122
a4f58f54
BA		 1123/**
1124 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1125 * done after every PHY reset.
1126 **/
1127static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1128{
1129 s32 ret_val = 0;
1130
1131 if (hw->mac.type != e1000_pchlan)
1132 return ret_val;
1133
1134 if (((hw->phy.type == e1000_phy_82577) &&
1135 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1136 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1137 /* Disable generation of early preamble */
1138 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1139 if (ret_val)
1140 return ret_val;
1141
1142 /* Preamble tuning for SSC */
1143 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1144 if (ret_val)
1145 return ret_val;
1146 }
1147
1148 if (hw->phy.type == e1000_phy_82578) {
1149 /*
1150 * Return registers to default by doing a soft reset then
1151 * writing 0x3140 to the control register.
1152 */
1153 if (hw->phy.revision < 2) {
1154 e1000e_phy_sw_reset(hw);
1155 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1156 }
1157 }
1158
1159 /* Select page 0 */
94d8186a 1160 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1161 if (ret_val)
1162 return ret_val;
1d5846b9 1163
a4f58f54 1164 hw->phy.addr = 1;
1d5846b9
BA		 1165 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1166 if (ret_val)
1167 goto out;
94d8186a 1168 hw->phy.ops.release(hw);
a4f58f54 1169
1d5846b9
BA		 1170 /*
1171 * Configure the K1 Si workaround during phy reset assuming there is
1172 * link so that it disables K1 if link is in 1Gbps.
1173 */
1174 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1175
1176out:
a4f58f54
BA		 1177 return ret_val;
1178}
1179
fc0c7760
BA		 1180/**
1181 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1182 * @hw: pointer to the HW structure
1183 *
1184 * Check the appropriate indication the MAC has finished configuring the
1185 * PHY after a software reset.
1186 **/
1187static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1188{
1189 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1190
1191 /* Wait for basic configuration completes before proceeding */
1192 do {
1193 data = er32(STATUS);
1194 data &= E1000_STATUS_LAN_INIT_DONE;
1195 udelay(100);
1196 } while ((!data) && --loop);
1197
1198 /*
1199 * If basic configuration is incomplete before the above loop
1200 * count reaches 0, loading the configuration from NVM will
1201 * leave the PHY in a bad state possibly resulting in no link.
1202 */
1203 if (loop == 0)
3bb99fe2 1204 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1205
1206 /* Clear the Init Done bit for the next init event */
1207 data = er32(STATUS);
1208 data &= ~E1000_STATUS_LAN_INIT_DONE;
1209 ew32(STATUS, data);
1210}
1211
bc7f75fa
AK		 1212/**
1213 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1214 * @hw: pointer to the HW structure
1215 *
1216 * Resets the PHY
1217 * This is a function pointer entry point called by drivers
1218 * or other shared routines.
1219 **/
1220static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1221{
f523d211
BA		 1222 s32 ret_val = 0;
1223 u16 reg;
bc7f75fa
AK		 1224
1225 ret_val = e1000e_phy_hw_reset_generic(hw);
1226 if (ret_val)
1227 return ret_val;
1228
fc0c7760
BA		 1229 /* Allow time for h/w to get to a quiescent state after reset */
1230 mdelay(10);
1231
a4f58f54
BA		 1232 if (hw->mac.type == e1000_pchlan) {
1233 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1234 if (ret_val)
1235 return ret_val;
1236 }
1237
db2932ec
BA		 1238 /* Dummy read to clear the phy wakeup bit after lcd reset */
1239 if (hw->mac.type == e1000_pchlan)
1240 e1e_rphy(hw, BM_WUC, &reg);
1241
f523d211
BA		 1242 /* Configure the LCD with the extended configuration region in NVM */
1243 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1244 if (ret_val)
1245 goto out;
bc7f75fa 1246
f523d211
BA		 1247 /* Configure the LCD with the OEM bits in NVM */
1248 if (hw->mac.type == e1000_pchlan)
1249 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1250
f523d211 1251out:
bc7f75fa
AK		 1252 return 0;
1253}
1254
1255/**
1256 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1257 * @hw: pointer to the HW structure
1258 *
1259 * Populates "phy" structure with various feature states.
1260 * This function is only called by other family-specific
1261 * routines.
1262 **/
1263static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1264{
1265 struct e1000_phy_info *phy = &hw->phy;
1266 s32 ret_val;
1267 u16 data;
1268 bool link;
1269
1270 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1271 if (ret_val)
1272 return ret_val;
1273
1274 if (!link) {
3bb99fe2 1275 e_dbg("Phy info is only valid if link is up\n");
bc7f75fa
AK		 1276 return -E1000_ERR_CONFIG;
1277 }
1278
1279 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1280 if (ret_val)
1281 return ret_val;
1282 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1283
1284 if (phy->polarity_correction) {
a4f58f54 1285 ret_val = phy->ops.check_polarity(hw);
bc7f75fa
AK		 1286 if (ret_val)
1287 return ret_val;
1288 } else {
1289 /* Polarity is forced */
1290 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1291 ? e1000_rev_polarity_reversed
1292 : e1000_rev_polarity_normal;
1293 }
1294
1295 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1296 if (ret_val)
1297 return ret_val;
1298
1299 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1300
1301 /* The following parameters are undefined for 10/100 operation. */
1302 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1303 phy->local_rx = e1000_1000t_rx_status_undefined;
1304 phy->remote_rx = e1000_1000t_rx_status_undefined;
1305
1306 return 0;
1307}
1308
1309/**
1310 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1311 * @hw: pointer to the HW structure
1312 *
1313 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1314 * This is a function pointer entry point called by drivers
1315 * or other shared routines.
1316 **/
1317static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1318{
1319 switch (hw->phy.type) {
1320 case e1000_phy_ife:
1321 return e1000_get_phy_info_ife_ich8lan(hw);
1322 break;
1323 case e1000_phy_igp_3:
97ac8cae 1324 case e1000_phy_bm:
a4f58f54
BA		 1325 case e1000_phy_82578:
1326 case e1000_phy_82577:
bc7f75fa
AK		 1327 return e1000e_get_phy_info_igp(hw);
1328 break;
1329 default:
1330 break;
1331 }
1332
1333 return -E1000_ERR_PHY_TYPE;
1334}
1335
1336/**
1337 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1338 * @hw: pointer to the HW structure
1339 *
489815ce 1340 * Polarity is determined on the polarity reversal feature being enabled.
bc7f75fa
AK		 1341 * This function is only called by other family-specific
1342 * routines.
1343 **/
1344static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1345{
1346 struct e1000_phy_info *phy = &hw->phy;
1347 s32 ret_val;
1348 u16 phy_data, offset, mask;
1349
ad68076e
BA		 1350 /*
1351 * Polarity is determined based on the reversal feature being enabled.
bc7f75fa
AK		 1352 */
1353 if (phy->polarity_correction) {
1354 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1355 mask = IFE_PESC_POLARITY_REVERSED;
1356 } else {
1357 offset = IFE_PHY_SPECIAL_CONTROL;
1358 mask = IFE_PSC_FORCE_POLARITY;
1359 }
1360
1361 ret_val = e1e_rphy(hw, offset, &phy_data);
1362
1363 if (!ret_val)
1364 phy->cable_polarity = (phy_data & mask)
1365 ? e1000_rev_polarity_reversed
1366 : e1000_rev_polarity_normal;
1367
1368 return ret_val;
1369}
1370
fa2ce13c
BA		 1371/**
1372 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1373 * @hw: pointer to the HW structure
1374 * @active: true to enable LPLU, false to disable
1375 *
1376 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1377 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1378 * the phy speed. This function will manually set the LPLU bit and restart
1379 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1380 * since it configures the same bit.
1381 **/
1382static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1383{
1384 s32 ret_val = 0;
1385 u16 oem_reg;
1386
1387 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1388 if (ret_val)
1389 goto out;
1390
1391 if (active)
1392 oem_reg |= HV_OEM_BITS_LPLU;
1393 else
1394 oem_reg &= ~HV_OEM_BITS_LPLU;
1395
1396 oem_reg |= HV_OEM_BITS_RESTART_AN;
1397 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1398
1399out:
1400 return ret_val;
1401}
1402
bc7f75fa
AK		 1403/**
1404 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1405 * @hw: pointer to the HW structure
564ea9bb 1406 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1407 *
1408 * Sets the LPLU D0 state according to the active flag. When
1409 * activating LPLU this function also disables smart speed
1410 * and vice versa. LPLU will not be activated unless the
1411 * device autonegotiation advertisement meets standards of
1412 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1413 * This is a function pointer entry point only called by
1414 * PHY setup routines.
1415 **/
1416static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1417{
1418 struct e1000_phy_info *phy = &hw->phy;
1419 u32 phy_ctrl;
1420 s32 ret_val = 0;
1421 u16 data;
1422
97ac8cae 1423 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1424 return ret_val;
1425
1426 phy_ctrl = er32(PHY_CTRL);
1427
1428 if (active) {
1429 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1430 ew32(PHY_CTRL, phy_ctrl);
1431
60f1292f
BA		 1432 if (phy->type != e1000_phy_igp_3)
1433 return 0;
1434
ad68076e
BA		 1435 /*
1436 * Call gig speed drop workaround on LPLU before accessing
1437 * any PHY registers
1438 */
60f1292f 1439 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1440 e1000e_gig_downshift_workaround_ich8lan(hw);
1441
1442 /* When LPLU is enabled, we should disable SmartSpeed */
1443 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1444 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1445 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1446 if (ret_val)
1447 return ret_val;
1448 } else {
1449 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1450 ew32(PHY_CTRL, phy_ctrl);
1451
60f1292f
BA		 1452 if (phy->type != e1000_phy_igp_3)
1453 return 0;
1454
ad68076e
BA		 1455 /*
1456 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1457 * during Dx states where the power conservation is most
1458 * important. During driver activity we should enable
ad68076e
BA		 1459 * SmartSpeed, so performance is maintained.
1460 */
bc7f75fa
AK		 1461 if (phy->smart_speed == e1000_smart_speed_on) {
1462 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1463 &data);
bc7f75fa
AK		 1464 if (ret_val)
1465 return ret_val;
1466
1467 data |= IGP01E1000_PSCFR_SMART_SPEED;
1468 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1469 data);
bc7f75fa
AK		 1470 if (ret_val)
1471 return ret_val;
1472 } else if (phy->smart_speed == e1000_smart_speed_off) {
1473 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1474 &data);
bc7f75fa
AK		 1475 if (ret_val)
1476 return ret_val;
1477
1478 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1479 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1480 data);
bc7f75fa
AK		 1481 if (ret_val)
1482 return ret_val;
1483 }
1484 }
1485
1486 return 0;
1487}
1488
1489/**
1490 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1491 * @hw: pointer to the HW structure
564ea9bb 1492 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1493 *
1494 * Sets the LPLU D3 state according to the active flag. When
1495 * activating LPLU this function also disables smart speed
1496 * and vice versa. LPLU will not be activated unless the
1497 * device autonegotiation advertisement meets standards of
1498 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1499 * This is a function pointer entry point only called by
1500 * PHY setup routines.
1501 **/
1502static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1503{
1504 struct e1000_phy_info *phy = &hw->phy;
1505 u32 phy_ctrl;
1506 s32 ret_val;
1507 u16 data;
1508
1509 phy_ctrl = er32(PHY_CTRL);
1510
1511 if (!active) {
1512 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1513 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1514
1515 if (phy->type != e1000_phy_igp_3)
1516 return 0;
1517
ad68076e
BA		 1518 /*
1519 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1520 * during Dx states where the power conservation is most
1521 * important. During driver activity we should enable
ad68076e
BA		 1522 * SmartSpeed, so performance is maintained.
1523 */
bc7f75fa 1524 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1525 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1526 &data);
bc7f75fa
AK		 1527 if (ret_val)
1528 return ret_val;
1529
1530 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1531 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1532 data);
bc7f75fa
AK		 1533 if (ret_val)
1534 return ret_val;
1535 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1536 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 &data);
bc7f75fa
AK		 1538 if (ret_val)
1539 return ret_val;
1540
1541 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1542 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1543 data);
bc7f75fa
AK		 1544 if (ret_val)
1545 return ret_val;
1546 }
1547 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1548 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1549 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1550 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1551 ew32(PHY_CTRL, phy_ctrl);
1552
60f1292f
BA		 1553 if (phy->type != e1000_phy_igp_3)
1554 return 0;
1555
ad68076e
BA		 1556 /*
1557 * Call gig speed drop workaround on LPLU before accessing
1558 * any PHY registers
1559 */
60f1292f 1560 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1561 e1000e_gig_downshift_workaround_ich8lan(hw);
1562
1563 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1564 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1565 if (ret_val)
1566 return ret_val;
1567
1568 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1569 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1570 }
1571
1572 return 0;
1573}
1574
f4187b56
BA		 1575/**
1576 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1577 * @hw: pointer to the HW structure
1578 * @bank: pointer to the variable that returns the active bank
1579 *
1580 * Reads signature byte from the NVM using the flash access registers.
e243455d 1581 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1582 **/
1583static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1584{
e243455d 1585 u32 eecd;
f4187b56 1586 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1587 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1588 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1589 u8 sig_byte = 0;
1590 s32 ret_val = 0;
f4187b56 1591
e243455d
BA		 1592 switch (hw->mac.type) {
1593 case e1000_ich8lan:
1594 case e1000_ich9lan:
1595 eecd = er32(EECD);
1596 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1597 E1000_EECD_SEC1VAL_VALID_MASK) {
1598 if (eecd & E1000_EECD_SEC1VAL)
1599 *bank = 1;
1600 else
1601 *bank = 0;
1602
1603 return 0;
1604 }
3bb99fe2 1605 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 1606 "reading flash signature\n");
1607 /* fall-thru */
1608 default:
1609 /* set bank to 0 in case flash read fails */
1610 *bank = 0;
1611
1612 /* Check bank 0 */
1613 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1614 &sig_byte);
1615 if (ret_val)
1616 return ret_val;
1617 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1618 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 1619 *bank = 0;
e243455d
BA		 1620 return 0;
1621 }
f4187b56 1622
e243455d
BA		 1623 /* Check bank 1 */
1624 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1625 bank1_offset,
1626 &sig_byte);
1627 if (ret_val)
1628 return ret_val;
1629 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1630 E1000_ICH_NVM_SIG_VALUE) {
1631 *bank = 1;
1632 return 0;
f4187b56 1633 }
e243455d 1634
3bb99fe2 1635 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 1636 return -E1000_ERR_NVM;
f4187b56
BA		 1637 }
1638
1639 return 0;
1640}
1641
bc7f75fa
AK		 1642/**
1643 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1644 * @hw: pointer to the HW structure
1645 * @offset: The offset (in bytes) of the word(s) to read.
1646 * @words: Size of data to read in words
1647 * @data: Pointer to the word(s) to read at offset.
1648 *
1649 * Reads a word(s) from the NVM using the flash access registers.
1650 **/
1651static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1652 u16 *data)
1653{
1654 struct e1000_nvm_info *nvm = &hw->nvm;
1655 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1656 u32 act_offset;
148675a7 1657 s32 ret_val = 0;
f4187b56 1658 u32 bank = 0;
bc7f75fa
AK		 1659 u16 i, word;
1660
1661 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1662 (words == 0)) {
3bb99fe2 1663 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 1664 ret_val = -E1000_ERR_NVM;
1665 goto out;
bc7f75fa
AK		 1666 }
1667
94d8186a 1668 nvm->ops.acquire(hw);
bc7f75fa 1669
f4187b56 1670 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 1671 if (ret_val) {
3bb99fe2 1672 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 1673 bank = 0;
1674 }
f4187b56
BA		 1675
1676 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 1677 act_offset += offset;
1678
148675a7 1679 ret_val = 0;
bc7f75fa
AK		 1680 for (i = 0; i < words; i++) {
1681 if ((dev_spec->shadow_ram) &&
1682 (dev_spec->shadow_ram[offset+i].modified)) {
1683 data[i] = dev_spec->shadow_ram[offset+i].value;
1684 } else {
1685 ret_val = e1000_read_flash_word_ich8lan(hw,
1686 act_offset + i,
1687 &word);
1688 if (ret_val)
1689 break;
1690 data[i] = word;
1691 }
1692 }
1693
94d8186a 1694 nvm->ops.release(hw);
bc7f75fa 1695
e243455d
BA		 1696out:
1697 if (ret_val)
3bb99fe2 1698 e_dbg("NVM read error: %d\n", ret_val);
e243455d 1699
bc7f75fa
AK		 1700 return ret_val;
1701}
1702
1703/**
1704 * e1000_flash_cycle_init_ich8lan - Initialize flash
1705 * @hw: pointer to the HW structure
1706 *
1707 * This function does initial flash setup so that a new read/write/erase cycle
1708 * can be started.
1709 **/
1710static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1711{
1712 union ich8_hws_flash_status hsfsts;
1713 s32 ret_val = -E1000_ERR_NVM;
1714 s32 i = 0;
1715
1716 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1717
1718 /* Check if the flash descriptor is valid */
1719 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 1720 e_dbg("Flash descriptor invalid. "
bc7f75fa
AK		 1721 "SW Sequencing must be used.");
1722 return -E1000_ERR_NVM;
1723 }
1724
1725 /* Clear FCERR and DAEL in hw status by writing 1 */
1726 hsfsts.hsf_status.flcerr = 1;
1727 hsfsts.hsf_status.dael = 1;
1728
1729 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1730
ad68076e
BA		 1731 /*
1732 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 1733 * bit to check against, in order to start a new cycle or
1734 * FDONE bit should be changed in the hardware so that it
489815ce 1735 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 1736 * indication whether a cycle is in progress or has been
1737 * completed.
1738 */
1739
1740 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 1741 /*
1742 * There is no cycle running at present,
1743 * so we can start a cycle
1744 * Begin by setting Flash Cycle Done.
1745 */
bc7f75fa
AK		 1746 hsfsts.hsf_status.flcdone = 1;
1747 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1748 ret_val = 0;
1749 } else {
ad68076e
BA		 1750 /*
1751 * otherwise poll for sometime so the current
1752 * cycle has a chance to end before giving up.
1753 */
bc7f75fa
AK		 1754 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1755 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1756 if (hsfsts.hsf_status.flcinprog == 0) {
1757 ret_val = 0;
1758 break;
1759 }
1760 udelay(1);
1761 }
1762 if (ret_val == 0) {
ad68076e
BA		 1763 /*
1764 * Successful in waiting for previous cycle to timeout,
1765 * now set the Flash Cycle Done.
1766 */
bc7f75fa
AK		 1767 hsfsts.hsf_status.flcdone = 1;
1768 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1769 } else {
3bb99fe2 1770 e_dbg("Flash controller busy, cannot get access");
bc7f75fa
AK		 1771 }
1772 }
1773
1774 return ret_val;
1775}
1776
1777/**
1778 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1779 * @hw: pointer to the HW structure
1780 * @timeout: maximum time to wait for completion
1781 *
1782 * This function starts a flash cycle and waits for its completion.
1783 **/
1784static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1785{
1786 union ich8_hws_flash_ctrl hsflctl;
1787 union ich8_hws_flash_status hsfsts;
1788 s32 ret_val = -E1000_ERR_NVM;
1789 u32 i = 0;
1790
1791 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1792 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1793 hsflctl.hsf_ctrl.flcgo = 1;
1794 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1795
1796 /* wait till FDONE bit is set to 1 */
1797 do {
1798 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1799 if (hsfsts.hsf_status.flcdone == 1)
1800 break;
1801 udelay(1);
1802 } while (i++ < timeout);
1803
1804 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1805 return 0;
1806
1807 return ret_val;
1808}
1809
1810/**
1811 * e1000_read_flash_word_ich8lan - Read word from flash
1812 * @hw: pointer to the HW structure
1813 * @offset: offset to data location
1814 * @data: pointer to the location for storing the data
1815 *
1816 * Reads the flash word at offset into data. Offset is converted
1817 * to bytes before read.
1818 **/
1819static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1820 u16 *data)
1821{
1822 /* Must convert offset into bytes. */
1823 offset <<= 1;
1824
1825 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1826}
1827
f4187b56
BA		 1828/**
1829 * e1000_read_flash_byte_ich8lan - Read byte from flash
1830 * @hw: pointer to the HW structure
1831 * @offset: The offset of the byte to read.
1832 * @data: Pointer to a byte to store the value read.
1833 *
1834 * Reads a single byte from the NVM using the flash access registers.
1835 **/
1836static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1837 u8 *data)
1838{
1839 s32 ret_val;
1840 u16 word = 0;
1841
1842 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1843 if (ret_val)
1844 return ret_val;
1845
1846 *data = (u8)word;
1847
1848 return 0;
1849}
1850
bc7f75fa
AK		 1851/**
1852 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1853 * @hw: pointer to the HW structure
1854 * @offset: The offset (in bytes) of the byte or word to read.
1855 * @size: Size of data to read, 1=byte 2=word
1856 * @data: Pointer to the word to store the value read.
1857 *
1858 * Reads a byte or word from the NVM using the flash access registers.
1859 **/
1860static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1861 u8 size, u16 *data)
1862{
1863 union ich8_hws_flash_status hsfsts;
1864 union ich8_hws_flash_ctrl hsflctl;
1865 u32 flash_linear_addr;
1866 u32 flash_data = 0;
1867 s32 ret_val = -E1000_ERR_NVM;
1868 u8 count = 0;
1869
1870 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1871 return -E1000_ERR_NVM;
1872
1873 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1874 hw->nvm.flash_base_addr;
1875
1876 do {
1877 udelay(1);
1878 /* Steps */
1879 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1880 if (ret_val != 0)
1881 break;
1882
1883 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1884 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1885 hsflctl.hsf_ctrl.fldbcount = size - 1;
1886 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1887 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1888
1889 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1890
1891 ret_val = e1000_flash_cycle_ich8lan(hw,
1892 ICH_FLASH_READ_COMMAND_TIMEOUT);
1893
ad68076e
BA		 1894 /*
1895 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 1896 * and try the whole sequence a few more times, else
1897 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 1898 * least significant byte first msb to lsb
1899 */
bc7f75fa
AK		 1900 if (ret_val == 0) {
1901 flash_data = er32flash(ICH_FLASH_FDATA0);
1902 if (size == 1) {
1903 *data = (u8)(flash_data & 0x000000FF);
1904 } else if (size == 2) {
1905 *data = (u16)(flash_data & 0x0000FFFF);
1906 }
1907 break;
1908 } else {
ad68076e
BA		 1909 /*
1910 * If we've gotten here, then things are probably
bc7f75fa
AK		 1911 * completely hosed, but if the error condition is
1912 * detected, it won't hurt to give it another try...
1913 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1914 */
1915 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1916 if (hsfsts.hsf_status.flcerr == 1) {
1917 /* Repeat for some time before giving up. */
1918 continue;
1919 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 1920 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 1921 "did not complete.");
1922 break;
1923 }
1924 }
1925 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1926
1927 return ret_val;
1928}
1929
1930/**
1931 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1932 * @hw: pointer to the HW structure
1933 * @offset: The offset (in bytes) of the word(s) to write.
1934 * @words: Size of data to write in words
1935 * @data: Pointer to the word(s) to write at offset.
1936 *
1937 * Writes a byte or word to the NVM using the flash access registers.
1938 **/
1939static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1940 u16 *data)
1941{
1942 struct e1000_nvm_info *nvm = &hw->nvm;
1943 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 1944 u16 i;
1945
1946 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1947 (words == 0)) {
3bb99fe2 1948 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 1949 return -E1000_ERR_NVM;
1950 }
1951
94d8186a 1952 nvm->ops.acquire(hw);
ca15df58 1953
bc7f75fa 1954 for (i = 0; i < words; i++) {
564ea9bb 1955 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 1956 dev_spec->shadow_ram[offset+i].value = data[i];
1957 }
1958
94d8186a 1959 nvm->ops.release(hw);
ca15df58 1960
bc7f75fa
AK		 1961 return 0;
1962}
1963
1964/**
1965 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1966 * @hw: pointer to the HW structure
1967 *
1968 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1969 * which writes the checksum to the shadow ram. The changes in the shadow
1970 * ram are then committed to the EEPROM by processing each bank at a time
1971 * checking for the modified bit and writing only the pending changes.
489815ce 1972 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 1973 * future writes.
1974 **/
1975static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1976{
1977 struct e1000_nvm_info *nvm = &hw->nvm;
1978 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 1979 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 1980 s32 ret_val;
1981 u16 data;
1982
1983 ret_val = e1000e_update_nvm_checksum_generic(hw);
1984 if (ret_val)
e243455d 1985 goto out;
bc7f75fa
AK		 1986
1987 if (nvm->type != e1000_nvm_flash_sw)
e243455d 1988 goto out;
bc7f75fa 1989
94d8186a 1990 nvm->ops.acquire(hw);
bc7f75fa 1991
ad68076e
BA		 1992 /*
1993 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 1994 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 1995 * is going to be written
1996 */
f4187b56 1997 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 1998 if (ret_val) {
3bb99fe2 1999 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2000 bank = 0;
e243455d 2001 }
f4187b56
BA		 2002
2003 if (bank == 0) {
bc7f75fa
AK		 2004 new_bank_offset = nvm->flash_bank_size;
2005 old_bank_offset = 0;
e243455d
BA		 2006 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2007 if (ret_val) {
94d8186a 2008 nvm->ops.release(hw);
e243455d
BA		 2009 goto out;
2010 }
bc7f75fa
AK		 2011 } else {
2012 old_bank_offset = nvm->flash_bank_size;
2013 new_bank_offset = 0;
e243455d
BA		 2014 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2015 if (ret_val) {
94d8186a 2016 nvm->ops.release(hw);
e243455d
BA		 2017 goto out;
2018 }
bc7f75fa
AK		 2019 }
2020
2021 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 2022 /*
2023 * Determine whether to write the value stored
bc7f75fa 2024 * in the other NVM bank or a modified value stored
ad68076e
BA		 2025 * in the shadow RAM
2026 */
bc7f75fa
AK		 2027 if (dev_spec->shadow_ram[i].modified) {
2028 data = dev_spec->shadow_ram[i].value;
2029 } else {
e243455d
BA		 2030 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2031 old_bank_offset,
2032 &data);
2033 if (ret_val)
2034 break;
bc7f75fa
AK		 2035 }
2036
ad68076e
BA		 2037 /*
2038 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2039 * (15:14) are 11b until the commit has completed.
2040 * This will allow us to write 10b which indicates the
2041 * signature is valid. We want to do this after the write
2042 * has completed so that we don't mark the segment valid
ad68076e
BA		 2043 * while the write is still in progress
2044 */
bc7f75fa
AK		 2045 if (i == E1000_ICH_NVM_SIG_WORD)
2046 data |= E1000_ICH_NVM_SIG_MASK;
2047
2048 /* Convert offset to bytes. */
2049 act_offset = (i + new_bank_offset) << 1;
2050
2051 udelay(100);
2052 /* Write the bytes to the new bank. */
2053 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2054 act_offset,
2055 (u8)data);
2056 if (ret_val)
2057 break;
2058
2059 udelay(100);
2060 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2061 act_offset + 1,
2062 (u8)(data >> 8));
2063 if (ret_val)
2064 break;
2065 }
2066
ad68076e
BA		 2067 /*
2068 * Don't bother writing the segment valid bits if sector
2069 * programming failed.
2070 */
bc7f75fa 2071 if (ret_val) {
4a770358 2072 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2073 e_dbg("Flash commit failed.\n");
94d8186a 2074 nvm->ops.release(hw);
e243455d 2075 goto out;
bc7f75fa
AK		 2076 }
2077
ad68076e
BA		 2078 /*
2079 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2080 * to 10b in word 0x13 , this can be done without an
2081 * erase as well since these bits are 11 to start with
ad68076e
BA		 2082 * and we need to change bit 14 to 0b
2083 */
bc7f75fa 2084 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d
BA		 2085 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2086 if (ret_val) {
94d8186a 2087 nvm->ops.release(hw);
e243455d
BA		 2088 goto out;
2089 }
bc7f75fa
AK		 2090 data &= 0xBFFF;
2091 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2092 act_offset * 2 + 1,
2093 (u8)(data >> 8));
2094 if (ret_val) {
94d8186a 2095 nvm->ops.release(hw);
e243455d 2096 goto out;
bc7f75fa
AK		 2097 }
2098
ad68076e
BA		 2099 /*
2100 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2101 * its signature word (0x13) high_byte to 0b. This can be
2102 * done without an erase because flash erase sets all bits
ad68076e
BA		 2103 * to 1's. We can write 1's to 0's without an erase
2104 */
bc7f75fa
AK		 2105 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2106 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2107 if (ret_val) {
94d8186a 2108 nvm->ops.release(hw);
e243455d 2109 goto out;
bc7f75fa
AK		 2110 }
2111
2112 /* Great! Everything worked, we can now clear the cached entries. */
2113 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2114 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2115 dev_spec->shadow_ram[i].value = 0xFFFF;
2116 }
2117
94d8186a 2118 nvm->ops.release(hw);
bc7f75fa 2119
ad68076e
BA		 2120 /*
2121 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2122 * until after the next adapter reset.
2123 */
2124 e1000e_reload_nvm(hw);
2125 msleep(10);
2126
e243455d
BA		 2127out:
2128 if (ret_val)
3bb99fe2 2129 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2130
bc7f75fa
AK		 2131 return ret_val;
2132}
2133
2134/**
2135 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2136 * @hw: pointer to the HW structure
2137 *
2138 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2139 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2140 * calculated, in which case we need to calculate the checksum and set bit 6.
2141 **/
2142static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2143{
2144 s32 ret_val;
2145 u16 data;
2146
ad68076e
BA		 2147 /*
2148 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2149 * needs to be fixed. This bit is an indication that the NVM
2150 * was prepared by OEM software and did not calculate the
2151 * checksum...a likely scenario.
2152 */
2153 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2154 if (ret_val)
2155 return ret_val;
2156
2157 if ((data & 0x40) == 0) {
2158 data |= 0x40;
2159 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2160 if (ret_val)
2161 return ret_val;
2162 ret_val = e1000e_update_nvm_checksum(hw);
2163 if (ret_val)
2164 return ret_val;
2165 }
2166
2167 return e1000e_validate_nvm_checksum_generic(hw);
2168}
2169
4a770358
BA		 2170/**
2171 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2172 * @hw: pointer to the HW structure
2173 *
2174 * To prevent malicious write/erase of the NVM, set it to be read-only
2175 * so that the hardware ignores all write/erase cycles of the NVM via
2176 * the flash control registers. The shadow-ram copy of the NVM will
2177 * still be updated, however any updates to this copy will not stick
2178 * across driver reloads.
2179 **/
2180void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2181{
ca15df58 2182 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2183 union ich8_flash_protected_range pr0;
2184 union ich8_hws_flash_status hsfsts;
2185 u32 gfpreg;
4a770358 2186
94d8186a 2187 nvm->ops.acquire(hw);
4a770358
BA		 2188
2189 gfpreg = er32flash(ICH_FLASH_GFPREG);
2190
2191 /* Write-protect GbE Sector of NVM */
2192 pr0.regval = er32flash(ICH_FLASH_PR0);
2193 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2194 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2195 pr0.range.wpe = true;
2196 ew32flash(ICH_FLASH_PR0, pr0.regval);
2197
2198 /*
2199 * Lock down a subset of GbE Flash Control Registers, e.g.
2200 * PR0 to prevent the write-protection from being lifted.
2201 * Once FLOCKDN is set, the registers protected by it cannot
2202 * be written until FLOCKDN is cleared by a hardware reset.
2203 */
2204 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2205 hsfsts.hsf_status.flockdn = true;
2206 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2207
94d8186a 2208 nvm->ops.release(hw);
4a770358
BA		 2209}
2210
bc7f75fa
AK		 2211/**
2212 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2213 * @hw: pointer to the HW structure
2214 * @offset: The offset (in bytes) of the byte/word to read.
2215 * @size: Size of data to read, 1=byte 2=word
2216 * @data: The byte(s) to write to the NVM.
2217 *
2218 * Writes one/two bytes to the NVM using the flash access registers.
2219 **/
2220static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2221 u8 size, u16 data)
2222{
2223 union ich8_hws_flash_status hsfsts;
2224 union ich8_hws_flash_ctrl hsflctl;
2225 u32 flash_linear_addr;
2226 u32 flash_data = 0;
2227 s32 ret_val;
2228 u8 count = 0;
2229
2230 if (size < 1 || size > 2 || data > size * 0xff ||
2231 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2232 return -E1000_ERR_NVM;
2233
2234 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2235 hw->nvm.flash_base_addr;
2236
2237 do {
2238 udelay(1);
2239 /* Steps */
2240 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2241 if (ret_val)
2242 break;
2243
2244 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2245 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2246 hsflctl.hsf_ctrl.fldbcount = size -1;
2247 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2248 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2249
2250 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2251
2252 if (size == 1)
2253 flash_data = (u32)data & 0x00FF;
2254 else
2255 flash_data = (u32)data;
2256
2257 ew32flash(ICH_FLASH_FDATA0, flash_data);
2258
ad68076e
BA		 2259 /*
2260 * check if FCERR is set to 1 , if set to 1, clear it
2261 * and try the whole sequence a few more times else done
2262 */
bc7f75fa
AK		 2263 ret_val = e1000_flash_cycle_ich8lan(hw,
2264 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2265 if (!ret_val)
2266 break;
2267
ad68076e
BA		 2268 /*
2269 * If we're here, then things are most likely
bc7f75fa
AK		 2270 * completely hosed, but if the error condition
2271 * is detected, it won't hurt to give it another
2272 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2273 */
2274 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2275 if (hsfsts.hsf_status.flcerr == 1)
2276 /* Repeat for some time before giving up. */
2277 continue;
2278 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2279 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2280 "did not complete.");
2281 break;
2282 }
2283 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2284
2285 return ret_val;
2286}
2287
2288/**
2289 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2290 * @hw: pointer to the HW structure
2291 * @offset: The index of the byte to read.
2292 * @data: The byte to write to the NVM.
2293 *
2294 * Writes a single byte to the NVM using the flash access registers.
2295 **/
2296static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2297 u8 data)
2298{
2299 u16 word = (u16)data;
2300
2301 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2302}
2303
2304/**
2305 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2306 * @hw: pointer to the HW structure
2307 * @offset: The offset of the byte to write.
2308 * @byte: The byte to write to the NVM.
2309 *
2310 * Writes a single byte to the NVM using the flash access registers.
2311 * Goes through a retry algorithm before giving up.
2312 **/
2313static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2314 u32 offset, u8 byte)
2315{
2316 s32 ret_val;
2317 u16 program_retries;
2318
2319 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2320 if (!ret_val)
2321 return ret_val;
2322
2323 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2324 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2325 udelay(100);
2326 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2327 if (!ret_val)
2328 break;
2329 }
2330 if (program_retries == 100)
2331 return -E1000_ERR_NVM;
2332
2333 return 0;
2334}
2335
2336/**
2337 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2338 * @hw: pointer to the HW structure
2339 * @bank: 0 for first bank, 1 for second bank, etc.
2340 *
2341 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2342 * bank N is 4096 * N + flash_reg_addr.
2343 **/
2344static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2345{
2346 struct e1000_nvm_info *nvm = &hw->nvm;
2347 union ich8_hws_flash_status hsfsts;
2348 union ich8_hws_flash_ctrl hsflctl;
2349 u32 flash_linear_addr;
2350 /* bank size is in 16bit words - adjust to bytes */
2351 u32 flash_bank_size = nvm->flash_bank_size * 2;
2352 s32 ret_val;
2353 s32 count = 0;
2354 s32 iteration;
2355 s32 sector_size;
2356 s32 j;
2357
2358 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2359
ad68076e
BA		 2360 /*
2361 * Determine HW Sector size: Read BERASE bits of hw flash status
2362 * register
2363 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2364 * consecutive sectors. The start index for the nth Hw sector
2365 * can be calculated as = bank * 4096 + n * 256
2366 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2367 * The start index for the nth Hw sector can be calculated
2368 * as = bank * 4096
2369 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2370 * (ich9 only, otherwise error condition)
2371 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2372 */
2373 switch (hsfsts.hsf_status.berasesz) {
2374 case 0:
2375 /* Hw sector size 256 */
2376 sector_size = ICH_FLASH_SEG_SIZE_256;
2377 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2378 break;
2379 case 1:
2380 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2381 iteration = 1;
bc7f75fa
AK		 2382 break;
2383 case 2:
148675a7
BA		 2384 sector_size = ICH_FLASH_SEG_SIZE_8K;
2385 iteration = 1;
bc7f75fa
AK		 2386 break;
2387 case 3:
2388 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2389 iteration = 1;
bc7f75fa
AK		 2390 break;
2391 default:
2392 return -E1000_ERR_NVM;
2393 }
2394
2395 /* Start with the base address, then add the sector offset. */
2396 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2397 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2398
2399 for (j = 0; j < iteration ; j++) {
2400 do {
2401 /* Steps */
2402 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2403 if (ret_val)
2404 return ret_val;
2405
ad68076e
BA		 2406 /*
2407 * Write a value 11 (block Erase) in Flash
2408 * Cycle field in hw flash control
2409 */
bc7f75fa
AK		 2410 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2411 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2412 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2413
ad68076e
BA		 2414 /*
2415 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2416 * block into Flash Linear address field in Flash
2417 * Address.
2418 */
2419 flash_linear_addr += (j * sector_size);
2420 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2421
2422 ret_val = e1000_flash_cycle_ich8lan(hw,
2423 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2424 if (ret_val == 0)
2425 break;
2426
ad68076e
BA		 2427 /*
2428 * Check if FCERR is set to 1. If 1,
bc7f75fa 2429 * clear it and try the whole sequence
ad68076e
BA		 2430 * a few more times else Done
2431 */
bc7f75fa
AK		 2432 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2433 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2434 /* repeat for some time before giving up */
bc7f75fa
AK		 2435 continue;
2436 else if (hsfsts.hsf_status.flcdone == 0)
2437 return ret_val;
2438 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2439 }
2440
2441 return 0;
2442}
2443
2444/**
2445 * e1000_valid_led_default_ich8lan - Set the default LED settings
2446 * @hw: pointer to the HW structure
2447 * @data: Pointer to the LED settings
2448 *
2449 * Reads the LED default settings from the NVM to data. If the NVM LED
2450 * settings is all 0's or F's, set the LED default to a valid LED default
2451 * setting.
2452 **/
2453static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2454{
2455 s32 ret_val;
2456
2457 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2458 if (ret_val) {
3bb99fe2 2459 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2460 return ret_val;
2461 }
2462
2463 if (*data == ID_LED_RESERVED_0000 ||
2464 *data == ID_LED_RESERVED_FFFF)
2465 *data = ID_LED_DEFAULT_ICH8LAN;
2466
2467 return 0;
2468}
2469
a4f58f54
BA		 2470/**
2471 * e1000_id_led_init_pchlan - store LED configurations
2472 * @hw: pointer to the HW structure
2473 *
2474 * PCH does not control LEDs via the LEDCTL register, rather it uses
2475 * the PHY LED configuration register.
2476 *
2477 * PCH also does not have an "always on" or "always off" mode which
2478 * complicates the ID feature. Instead of using the "on" mode to indicate
2479 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2480 * use "link_up" mode. The LEDs will still ID on request if there is no
2481 * link based on logic in e1000_led_[on|off]_pchlan().
2482 **/
2483static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2484{
2485 struct e1000_mac_info *mac = &hw->mac;
2486 s32 ret_val;
2487 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2488 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2489 u16 data, i, temp, shift;
2490
2491 /* Get default ID LED modes */
2492 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2493 if (ret_val)
2494 goto out;
2495
2496 mac->ledctl_default = er32(LEDCTL);
2497 mac->ledctl_mode1 = mac->ledctl_default;
2498 mac->ledctl_mode2 = mac->ledctl_default;
2499
2500 for (i = 0; i < 4; i++) {
2501 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2502 shift = (i * 5);
2503 switch (temp) {
2504 case ID_LED_ON1_DEF2:
2505 case ID_LED_ON1_ON2:
2506 case ID_LED_ON1_OFF2:
2507 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2508 mac->ledctl_mode1 |= (ledctl_on << shift);
2509 break;
2510 case ID_LED_OFF1_DEF2:
2511 case ID_LED_OFF1_ON2:
2512 case ID_LED_OFF1_OFF2:
2513 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2514 mac->ledctl_mode1 |= (ledctl_off << shift);
2515 break;
2516 default:
2517 /* Do nothing */
2518 break;
2519 }
2520 switch (temp) {
2521 case ID_LED_DEF1_ON2:
2522 case ID_LED_ON1_ON2:
2523 case ID_LED_OFF1_ON2:
2524 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2525 mac->ledctl_mode2 |= (ledctl_on << shift);
2526 break;
2527 case ID_LED_DEF1_OFF2:
2528 case ID_LED_ON1_OFF2:
2529 case ID_LED_OFF1_OFF2:
2530 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2531 mac->ledctl_mode2 |= (ledctl_off << shift);
2532 break;
2533 default:
2534 /* Do nothing */
2535 break;
2536 }
2537 }
2538
2539out:
2540 return ret_val;
2541}
2542
bc7f75fa
AK		 2543/**
2544 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2545 * @hw: pointer to the HW structure
2546 *
2547 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2548 * register, so the the bus width is hard coded.
2549 **/
2550static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2551{
2552 struct e1000_bus_info *bus = &hw->bus;
2553 s32 ret_val;
2554
2555 ret_val = e1000e_get_bus_info_pcie(hw);
2556
ad68076e
BA		 2557 /*
2558 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2559 * a configuration space, but do not contain
2560 * PCI Express Capability registers, so bus width
2561 * must be hardcoded.
2562 */
2563 if (bus->width == e1000_bus_width_unknown)
2564 bus->width = e1000_bus_width_pcie_x1;
2565
2566 return ret_val;
2567}
2568
2569/**
2570 * e1000_reset_hw_ich8lan - Reset the hardware
2571 * @hw: pointer to the HW structure
2572 *
2573 * Does a full reset of the hardware which includes a reset of the PHY and
2574 * MAC.
2575 **/
2576static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2577{
1d5846b9 2578 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2579 u16 reg;
bc7f75fa
AK		 2580 u32 ctrl, icr, kab;
2581 s32 ret_val;
2582
ad68076e
BA		 2583 /*
2584 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2585 * on the last TLP read/write transaction when MAC is reset.
2586 */
2587 ret_val = e1000e_disable_pcie_master(hw);
2588 if (ret_val) {
3bb99fe2 2589 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa
AK		 2590 }
2591
3bb99fe2 2592 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2593 ew32(IMC, 0xffffffff);
2594
ad68076e
BA		 2595 /*
2596 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2597 * any pending transactions to complete before we hit the MAC
2598 * with the global reset.
2599 */
2600 ew32(RCTL, 0);
2601 ew32(TCTL, E1000_TCTL_PSP);
2602 e1e_flush();
2603
2604 msleep(10);
2605
2606 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2607 if (hw->mac.type == e1000_ich8lan) {
2608 /* Set Tx and Rx buffer allocation to 8k apiece. */
2609 ew32(PBA, E1000_PBA_8K);
2610 /* Set Packet Buffer Size to 16k. */
2611 ew32(PBS, E1000_PBS_16K);
2612 }
2613
1d5846b9
BA		 2614 if (hw->mac.type == e1000_pchlan) {
2615 /* Save the NVM K1 bit setting*/
2616 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2617 if (ret_val)
2618 return ret_val;
2619
2620 if (reg & E1000_NVM_K1_ENABLE)
2621 dev_spec->nvm_k1_enabled = true;
2622 else
2623 dev_spec->nvm_k1_enabled = false;
2624 }
2625
bc7f75fa
AK		 2626 ctrl = er32(CTRL);
2627
2628 if (!e1000_check_reset_block(hw)) {
fc0c7760
BA		 2629 /* Clear PHY Reset Asserted bit */
2630 if (hw->mac.type >= e1000_pchlan) {
2631 u32 status = er32(STATUS);
2632 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2633 }
2634
ad68076e
BA		 2635 /*
2636 * PHY HW reset requires MAC CORE reset at the same
bc7f75fa
AK		 2637 * time to make sure the interface between MAC and the
2638 * external PHY is reset.
2639 */
2640 ctrl |= E1000_CTRL_PHY_RST;
2641 }
2642 ret_val = e1000_acquire_swflag_ich8lan(hw);
30bb0e0d 2643 /* Whether or not the swflag was acquired, we need to reset the part */
3bb99fe2 2644 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 2645 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2646 msleep(20);
2647
fc0c7760 2648 if (!ret_val)
30bb0e0d 2649 e1000_release_swflag_ich8lan(hw);
37f40239 2650
fc0c7760
BA		 2651 if (ctrl & E1000_CTRL_PHY_RST)
2652 ret_val = hw->phy.ops.get_cfg_done(hw);
2653
2654 if (hw->mac.type >= e1000_ich10lan) {
2655 e1000_lan_init_done_ich8lan(hw);
2656 } else {
2657 ret_val = e1000e_get_auto_rd_done(hw);
2658 if (ret_val) {
2659 /*
2660 * When auto config read does not complete, do not
2661 * return with an error. This can happen in situations
2662 * where there is no eeprom and prevents getting link.
2663 */
3bb99fe2 2664 e_dbg("Auto Read Done did not complete\n");
fc0c7760 2665 }
bc7f75fa 2666 }
db2932ec
BA		 2667 /* Dummy read to clear the phy wakeup bit after lcd reset */
2668 if (hw->mac.type == e1000_pchlan)
2669 e1e_rphy(hw, BM_WUC, &reg);
bc7f75fa 2670
f523d211
BA		 2671 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2672 if (ret_val)
2673 goto out;
2674
2675 if (hw->mac.type == e1000_pchlan) {
2676 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2677 if (ret_val)
2678 goto out;
2679 }
7d3cabbc
BA		 2680 /*
2681 * For PCH, this write will make sure that any noise
2682 * will be detected as a CRC error and be dropped rather than show up
2683 * as a bad packet to the DMA engine.
2684 */
2685 if (hw->mac.type == e1000_pchlan)
2686 ew32(CRC_OFFSET, 0x65656565);
2687
bc7f75fa
AK		 2688 ew32(IMC, 0xffffffff);
2689 icr = er32(ICR);
2690
2691 kab = er32(KABGTXD);
2692 kab |= E1000_KABGTXD_BGSQLBIAS;
2693 ew32(KABGTXD, kab);
2694
a4f58f54
BA		 2695 if (hw->mac.type == e1000_pchlan)
2696 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2697
f523d211 2698out:
bc7f75fa
AK		 2699 return ret_val;
2700}
2701
2702/**
2703 * e1000_init_hw_ich8lan - Initialize the hardware
2704 * @hw: pointer to the HW structure
2705 *
2706 * Prepares the hardware for transmit and receive by doing the following:
2707 * - initialize hardware bits
2708 * - initialize LED identification
2709 * - setup receive address registers
2710 * - setup flow control
489815ce 2711 * - setup transmit descriptors
bc7f75fa
AK		 2712 * - clear statistics
2713 **/
2714static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2715{
2716 struct e1000_mac_info *mac = &hw->mac;
2717 u32 ctrl_ext, txdctl, snoop;
2718 s32 ret_val;
2719 u16 i;
2720
2721 e1000_initialize_hw_bits_ich8lan(hw);
2722
2723 /* Initialize identification LED */
a4f58f54 2724 ret_val = mac->ops.id_led_init(hw);
de39b752 2725 if (ret_val)
3bb99fe2 2726 e_dbg("Error initializing identification LED\n");
de39b752 2727 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 2728
2729 /* Setup the receive address. */
2730 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2731
2732 /* Zero out the Multicast HASH table */
3bb99fe2 2733 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 2734 for (i = 0; i < mac->mta_reg_count; i++)
2735 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2736
fc0c7760
BA		 2737 /*
2738 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2739 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2740 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2741 */
2742 if (hw->phy.type == e1000_phy_82578) {
94d8186a 2743 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 2744 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2745 if (ret_val)
2746 return ret_val;
2747 }
2748
bc7f75fa
AK		 2749 /* Setup link and flow control */
2750 ret_val = e1000_setup_link_ich8lan(hw);
2751
2752 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 2753 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 2754 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2755 E1000_TXDCTL_FULL_TX_DESC_WB;
2756 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2757 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 2758 ew32(TXDCTL(0), txdctl);
2759 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 2760 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2761 E1000_TXDCTL_FULL_TX_DESC_WB;
2762 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2763 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 2764 ew32(TXDCTL(1), txdctl);
bc7f75fa 2765
ad68076e
BA		 2766 /*
2767 * ICH8 has opposite polarity of no_snoop bits.
2768 * By default, we should use snoop behavior.
2769 */
bc7f75fa
AK		 2770 if (mac->type == e1000_ich8lan)
2771 snoop = PCIE_ICH8_SNOOP_ALL;
2772 else
2773 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2774 e1000e_set_pcie_no_snoop(hw, snoop);
2775
2776 ctrl_ext = er32(CTRL_EXT);
2777 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2778 ew32(CTRL_EXT, ctrl_ext);
2779
ad68076e
BA		 2780 /*
2781 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 2782 * important that we do this after we have tried to establish link
2783 * because the symbol error count will increment wildly if there
2784 * is no link.
2785 */
2786 e1000_clear_hw_cntrs_ich8lan(hw);
2787
2788 return 0;
2789}
2790/**
2791 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2792 * @hw: pointer to the HW structure
2793 *
2794 * Sets/Clears required hardware bits necessary for correctly setting up the
2795 * hardware for transmit and receive.
2796 **/
2797static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2798{
2799 u32 reg;
2800
2801 /* Extended Device Control */
2802 reg = er32(CTRL_EXT);
2803 reg |= (1 << 22);
a4f58f54
BA		 2804 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2805 if (hw->mac.type >= e1000_pchlan)
2806 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 2807 ew32(CTRL_EXT, reg);
2808
2809 /* Transmit Descriptor Control 0 */
e9ec2c0f 2810 reg = er32(TXDCTL(0));
bc7f75fa 2811 reg |= (1 << 22);
e9ec2c0f 2812 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 2813
2814 /* Transmit Descriptor Control 1 */
e9ec2c0f 2815 reg = er32(TXDCTL(1));
bc7f75fa 2816 reg |= (1 << 22);
e9ec2c0f 2817 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 2818
2819 /* Transmit Arbitration Control 0 */
e9ec2c0f 2820 reg = er32(TARC(0));
bc7f75fa
AK		 2821 if (hw->mac.type == e1000_ich8lan)
2822 reg |= (1 << 28) | (1 << 29);
2823 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 2824 ew32(TARC(0), reg);
bc7f75fa
AK		 2825
2826 /* Transmit Arbitration Control 1 */
e9ec2c0f 2827 reg = er32(TARC(1));
bc7f75fa
AK		 2828 if (er32(TCTL) & E1000_TCTL_MULR)
2829 reg &= ~(1 << 28);
2830 else
2831 reg |= (1 << 28);
2832 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 2833 ew32(TARC(1), reg);
bc7f75fa
AK		 2834
2835 /* Device Status */
2836 if (hw->mac.type == e1000_ich8lan) {
2837 reg = er32(STATUS);
2838 reg &= ~(1 << 31);
2839 ew32(STATUS, reg);
2840 }
2841}
2842
2843/**
2844 * e1000_setup_link_ich8lan - Setup flow control and link settings
2845 * @hw: pointer to the HW structure
2846 *
2847 * Determines which flow control settings to use, then configures flow
2848 * control. Calls the appropriate media-specific link configuration
2849 * function. Assuming the adapter has a valid link partner, a valid link
2850 * should be established. Assumes the hardware has previously been reset
2851 * and the transmitter and receiver are not enabled.
2852 **/
2853static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2854{
bc7f75fa
AK		 2855 s32 ret_val;
2856
2857 if (e1000_check_reset_block(hw))
2858 return 0;
2859
ad68076e
BA		 2860 /*
2861 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 2862 * the default flow control setting, so we explicitly
2863 * set it to full.
2864 */
37289d9c
BA		 2865 if (hw->fc.requested_mode == e1000_fc_default) {
2866 /* Workaround h/w hang when Tx flow control enabled */
2867 if (hw->mac.type == e1000_pchlan)
2868 hw->fc.requested_mode = e1000_fc_rx_pause;
2869 else
2870 hw->fc.requested_mode = e1000_fc_full;
2871 }
bc7f75fa 2872
5c48ef3e
BA		 2873 /*
2874 * Save off the requested flow control mode for use later. Depending
2875 * on the link partner's capabilities, we may or may not use this mode.
2876 */
2877 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 2878
3bb99fe2 2879 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 2880 hw->fc.current_mode);
bc7f75fa
AK		 2881
2882 /* Continue to configure the copper link. */
2883 ret_val = e1000_setup_copper_link_ich8lan(hw);
2884 if (ret_val)
2885 return ret_val;
2886
318a94d6 2887 ew32(FCTTV, hw->fc.pause_time);
a4f58f54
BA		 2888 if ((hw->phy.type == e1000_phy_82578) ||
2889 (hw->phy.type == e1000_phy_82577)) {
94d8186a 2890 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 2891 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2892 hw->fc.pause_time);
2893 if (ret_val)
2894 return ret_val;
2895 }
bc7f75fa
AK		 2896
2897 return e1000e_set_fc_watermarks(hw);
2898}
2899
2900/**
2901 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2902 * @hw: pointer to the HW structure
2903 *
2904 * Configures the kumeran interface to the PHY to wait the appropriate time
2905 * when polling the PHY, then call the generic setup_copper_link to finish
2906 * configuring the copper link.
2907 **/
2908static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2909{
2910 u32 ctrl;
2911 s32 ret_val;
2912 u16 reg_data;
2913
2914 ctrl = er32(CTRL);
2915 ctrl |= E1000_CTRL_SLU;
2916 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2917 ew32(CTRL, ctrl);
2918
ad68076e
BA		 2919 /*
2920 * Set the mac to wait the maximum time between each iteration
bc7f75fa 2921 * and increase the max iterations when polling the phy;
ad68076e
BA		 2922 * this fixes erroneous timeouts at 10Mbps.
2923 */
bc7f75fa
AK		 2924 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2925 if (ret_val)
2926 return ret_val;
2927 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2928 if (ret_val)
2929 return ret_val;
2930 reg_data |= 0x3F;
2931 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2932 if (ret_val)
2933 return ret_val;
2934
a4f58f54
BA		 2935 switch (hw->phy.type) {
2936 case e1000_phy_igp_3:
bc7f75fa
AK		 2937 ret_val = e1000e_copper_link_setup_igp(hw);
2938 if (ret_val)
2939 return ret_val;
a4f58f54
BA		 2940 break;
2941 case e1000_phy_bm:
2942 case e1000_phy_82578:
97ac8cae
BA		 2943 ret_val = e1000e_copper_link_setup_m88(hw);
2944 if (ret_val)
2945 return ret_val;
a4f58f54
BA		 2946 break;
2947 case e1000_phy_82577:
2948 ret_val = e1000_copper_link_setup_82577(hw);
2949 if (ret_val)
2950 return ret_val;
2951 break;
2952 case e1000_phy_ife:
94d8186a 2953 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2954 &reg_data);
97ac8cae
BA		 2955 if (ret_val)
2956 return ret_val;
2957
2958 reg_data &= ~IFE_PMC_AUTO_MDIX;
2959
2960 switch (hw->phy.mdix) {
2961 case 1:
2962 reg_data &= ~IFE_PMC_FORCE_MDIX;
2963 break;
2964 case 2:
2965 reg_data |= IFE_PMC_FORCE_MDIX;
2966 break;
2967 case 0:
2968 default:
2969 reg_data |= IFE_PMC_AUTO_MDIX;
2970 break;
2971 }
94d8186a 2972 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2973 reg_data);
97ac8cae
BA		 2974 if (ret_val)
2975 return ret_val;
a4f58f54
BA		 2976 break;
2977 default:
2978 break;
97ac8cae 2979 }
bc7f75fa
AK		 2980 return e1000e_setup_copper_link(hw);
2981}
2982
2983/**
2984 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2985 * @hw: pointer to the HW structure
2986 * @speed: pointer to store current link speed
2987 * @duplex: pointer to store the current link duplex
2988 *
ad68076e 2989 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 2990 * information and then calls the Kumeran lock loss workaround for links at
2991 * gigabit speeds.
2992 **/
2993static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2994 u16 *duplex)
2995{
2996 s32 ret_val;
2997
2998 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2999 if (ret_val)
3000 return ret_val;
3001
3002 if ((hw->mac.type == e1000_ich8lan) &&
3003 (hw->phy.type == e1000_phy_igp_3) &&
3004 (*speed == SPEED_1000)) {
3005 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3006 }
3007
3008 return ret_val;
3009}
3010
3011/**
3012 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3013 * @hw: pointer to the HW structure
3014 *
3015 * Work-around for 82566 Kumeran PCS lock loss:
3016 * On link status change (i.e. PCI reset, speed change) and link is up and
3017 * speed is gigabit-
3018 * 0) if workaround is optionally disabled do nothing
3019 * 1) wait 1ms for Kumeran link to come up
3020 * 2) check Kumeran Diagnostic register PCS lock loss bit
3021 * 3) if not set the link is locked (all is good), otherwise...
3022 * 4) reset the PHY
3023 * 5) repeat up to 10 times
3024 * Note: this is only called for IGP3 copper when speed is 1gb.
3025 **/
3026static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3027{
3028 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3029 u32 phy_ctrl;
3030 s32 ret_val;
3031 u16 i, data;
3032 bool link;
3033
3034 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3035 return 0;
3036
ad68076e
BA		 3037 /*
3038 * Make sure link is up before proceeding. If not just return.
bc7f75fa 3039 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3040 * stability
3041 */
bc7f75fa
AK		 3042 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3043 if (!link)
3044 return 0;
3045
3046 for (i = 0; i < 10; i++) {
3047 /* read once to clear */
3048 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3049 if (ret_val)
3050 return ret_val;
3051 /* and again to get new status */
3052 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3053 if (ret_val)
3054 return ret_val;
3055
3056 /* check for PCS lock */
3057 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3058 return 0;
3059
3060 /* Issue PHY reset */
3061 e1000_phy_hw_reset(hw);
3062 mdelay(5);
3063 }
3064 /* Disable GigE link negotiation */
3065 phy_ctrl = er32(PHY_CTRL);
3066 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3067 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3068 ew32(PHY_CTRL, phy_ctrl);
3069
ad68076e
BA		 3070 /*
3071 * Call gig speed drop workaround on Gig disable before accessing
3072 * any PHY registers
3073 */
bc7f75fa
AK		 3074 e1000e_gig_downshift_workaround_ich8lan(hw);
3075
3076 /* unable to acquire PCS lock */
3077 return -E1000_ERR_PHY;
3078}
3079
3080/**
ad68076e 3081 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3082 * @hw: pointer to the HW structure
489815ce 3083 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3084 *
564ea9bb
BA		 3085 * If ICH8, set the current Kumeran workaround state (enabled - true
3086 * /disabled - false).
bc7f75fa
AK		 3087 **/
3088void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3089 bool state)
3090{
3091 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3092
3093 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3094 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3095 return;
3096 }
3097
3098 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3099}
3100
3101/**
3102 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3103 * @hw: pointer to the HW structure
3104 *
3105 * Workaround for 82566 power-down on D3 entry:
3106 * 1) disable gigabit link
3107 * 2) write VR power-down enable
3108 * 3) read it back
3109 * Continue if successful, else issue LCD reset and repeat
3110 **/
3111void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3112{
3113 u32 reg;
3114 u16 data;
3115 u8 retry = 0;
3116
3117 if (hw->phy.type != e1000_phy_igp_3)
3118 return;
3119
3120 /* Try the workaround twice (if needed) */
3121 do {
3122 /* Disable link */
3123 reg = er32(PHY_CTRL);
3124 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3125 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3126 ew32(PHY_CTRL, reg);
3127
ad68076e
BA		 3128 /*
3129 * Call gig speed drop workaround on Gig disable before
3130 * accessing any PHY registers
3131 */
bc7f75fa
AK		 3132 if (hw->mac.type == e1000_ich8lan)
3133 e1000e_gig_downshift_workaround_ich8lan(hw);
3134
3135 /* Write VR power-down enable */
3136 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3137 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3138 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3139
3140 /* Read it back and test */
3141 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3142 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3143 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3144 break;
3145
3146 /* Issue PHY reset and repeat at most one more time */
3147 reg = er32(CTRL);
3148 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3149 retry++;
3150 } while (retry);
3151}
3152
3153/**
3154 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3155 * @hw: pointer to the HW structure
3156 *
3157 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3158 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3159 * 1) Set Kumeran Near-end loopback
3160 * 2) Clear Kumeran Near-end loopback
3161 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3162 **/
3163void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3164{
3165 s32 ret_val;
3166 u16 reg_data;
3167
3168 if ((hw->mac.type != e1000_ich8lan) ||
3169 (hw->phy.type != e1000_phy_igp_3))
3170 return;
3171
3172 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3173 &reg_data);
3174 if (ret_val)
3175 return;
3176 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3177 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3178 reg_data);
3179 if (ret_val)
3180 return;
3181 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3182 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3183 reg_data);
3184}
3185
97ac8cae
BA		 3186/**
3187 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3188 * @hw: pointer to the HW structure
3189 *
3190 * During S0 to Sx transition, it is possible the link remains at gig
3191 * instead of negotiating to a lower speed. Before going to Sx, set
3192 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3193 * to a lower speed.
3194 *
a4f58f54 3195 * Should only be called for applicable parts.
97ac8cae
BA		 3196 **/
3197void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3198{
3199 u32 phy_ctrl;
3200
a4f58f54
BA		 3201 switch (hw->mac.type) {
3202 case e1000_ich9lan:
3203 case e1000_ich10lan:
3204 case e1000_pchlan:
97ac8cae
BA		 3205 phy_ctrl = er32(PHY_CTRL);
3206 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3207 E1000_PHY_CTRL_GBE_DISABLE;
3208 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3209
a4f58f54 3210 if (hw->mac.type == e1000_pchlan)
74eee2e8 3211 e1000_phy_hw_reset_ich8lan(hw);
a4f58f54
BA		 3212 default:
3213 break;
97ac8cae
BA		 3214 }
3215
3216 return;
3217}
3218
bc7f75fa
AK		 3219/**
3220 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3221 * @hw: pointer to the HW structure
3222 *
3223 * Return the LED back to the default configuration.
3224 **/
3225static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3226{
3227 if (hw->phy.type == e1000_phy_ife)
3228 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3229
3230 ew32(LEDCTL, hw->mac.ledctl_default);
3231 return 0;
3232}
3233
3234/**
489815ce 3235 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3236 * @hw: pointer to the HW structure
3237 *
489815ce 3238 * Turn on the LEDs.
bc7f75fa
AK		 3239 **/
3240static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3241{
3242 if (hw->phy.type == e1000_phy_ife)
3243 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3244 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3245
3246 ew32(LEDCTL, hw->mac.ledctl_mode2);
3247 return 0;
3248}
3249
3250/**
489815ce 3251 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3252 * @hw: pointer to the HW structure
3253 *
489815ce 3254 * Turn off the LEDs.
bc7f75fa
AK		 3255 **/
3256static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3257{
3258 if (hw->phy.type == e1000_phy_ife)
3259 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3260 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3261
3262 ew32(LEDCTL, hw->mac.ledctl_mode1);
3263 return 0;
3264}
3265
a4f58f54
BA		 3266/**
3267 * e1000_setup_led_pchlan - Configures SW controllable LED
3268 * @hw: pointer to the HW structure
3269 *
3270 * This prepares the SW controllable LED for use.
3271 **/
3272static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3273{
94d8186a 3274 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3275 (u16)hw->mac.ledctl_mode1);
3276}
3277
3278/**
3279 * e1000_cleanup_led_pchlan - Restore the default LED operation
3280 * @hw: pointer to the HW structure
3281 *
3282 * Return the LED back to the default configuration.
3283 **/
3284static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3285{
94d8186a 3286 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3287 (u16)hw->mac.ledctl_default);
3288}
3289
3290/**
3291 * e1000_led_on_pchlan - Turn LEDs on
3292 * @hw: pointer to the HW structure
3293 *
3294 * Turn on the LEDs.
3295 **/
3296static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3297{
3298 u16 data = (u16)hw->mac.ledctl_mode2;
3299 u32 i, led;
3300
3301 /*
3302 * If no link, then turn LED on by setting the invert bit
3303 * for each LED that's mode is "link_up" in ledctl_mode2.
3304 */
3305 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3306 for (i = 0; i < 3; i++) {
3307 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3308 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3309 E1000_LEDCTL_MODE_LINK_UP)
3310 continue;
3311 if (led & E1000_PHY_LED0_IVRT)
3312 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3313 else
3314 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3315 }
3316 }
3317
94d8186a 3318 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3319}
3320
3321/**
3322 * e1000_led_off_pchlan - Turn LEDs off
3323 * @hw: pointer to the HW structure
3324 *
3325 * Turn off the LEDs.
3326 **/
3327static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3328{
3329 u16 data = (u16)hw->mac.ledctl_mode1;
3330 u32 i, led;
3331
3332 /*
3333 * If no link, then turn LED off by clearing the invert bit
3334 * for each LED that's mode is "link_up" in ledctl_mode1.
3335 */
3336 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3337 for (i = 0; i < 3; i++) {
3338 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3339 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3340 E1000_LEDCTL_MODE_LINK_UP)
3341 continue;
3342 if (led & E1000_PHY_LED0_IVRT)
3343 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3344 else
3345 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3346 }
3347 }
3348
94d8186a 3349 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3350}
3351
f4187b56
BA		 3352/**
3353 * e1000_get_cfg_done_ich8lan - Read config done bit
3354 * @hw: pointer to the HW structure
3355 *
3356 * Read the management control register for the config done bit for
3357 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3358 * to read the config done bit, so an error is *ONLY* logged and returns
a4f58f54 3359 * 0. If we were to return with error, EEPROM-less silicon
f4187b56
BA		 3360 * would not be able to be reset or change link.
3361 **/
3362static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3363{
3364 u32 bank = 0;
3365
fc0c7760
BA		 3366 if (hw->mac.type >= e1000_pchlan) {
3367 u32 status = er32(STATUS);
3368
3369 if (status & E1000_STATUS_PHYRA)
3370 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3371 else
3bb99fe2 3372 e_dbg("PHY Reset Asserted not set - needs delay\n");
fc0c7760
BA		 3373 }
3374
f4187b56
BA		 3375 e1000e_get_cfg_done(hw);
3376
3377 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
a4f58f54
BA		 3378 if ((hw->mac.type != e1000_ich10lan) &&
3379 (hw->mac.type != e1000_pchlan)) {
f4187b56
BA		 3380 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3381 (hw->phy.type == e1000_phy_igp_3)) {
3382 e1000e_phy_init_script_igp3(hw);
3383 }
3384 } else {
3385 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3386 /* Maybe we should do a basic PHY config */
3bb99fe2 3387 e_dbg("EEPROM not present\n");
f4187b56
BA		 3388 return -E1000_ERR_CONFIG;
3389 }
3390 }
3391
3392 return 0;
3393}
3394
bc7f75fa
AK		 3395/**
3396 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3397 * @hw: pointer to the HW structure
3398 *
3399 * Clears hardware counters specific to the silicon family and calls
3400 * clear_hw_cntrs_generic to clear all general purpose counters.
3401 **/
3402static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3403{
a4f58f54 3404 u16 phy_data;
bc7f75fa
AK		 3405
3406 e1000e_clear_hw_cntrs_base(hw);
3407
99673d9b
BA		 3408 er32(ALGNERRC);
3409 er32(RXERRC);
3410 er32(TNCRS);
3411 er32(CEXTERR);
3412 er32(TSCTC);
3413 er32(TSCTFC);
bc7f75fa 3414
99673d9b
BA		 3415 er32(MGTPRC);
3416 er32(MGTPDC);
3417 er32(MGTPTC);
bc7f75fa 3418
99673d9b
BA		 3419 er32(IAC);
3420 er32(ICRXOC);
bc7f75fa 3421
a4f58f54
BA		 3422 /* Clear PHY statistics registers */
3423 if ((hw->phy.type == e1000_phy_82578) ||
3424 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3425 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3426 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3427 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3428 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3429 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3430 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3431 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3432 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3433 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3434 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3435 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3436 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3437 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3438 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3439 }
bc7f75fa
AK		 3440}
3441
3442static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3443 .id_led_init = e1000e_id_led_init,
4662e82b 3444 .check_mng_mode = e1000_check_mng_mode_ich8lan,
7d3cabbc 3445 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3446 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3447 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3448 .get_bus_info = e1000_get_bus_info_ich8lan,
3449 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3450 /* led_on dependent on mac type */
3451 /* led_off dependent on mac type */
e2de3eb6 3452 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3453 .reset_hw = e1000_reset_hw_ich8lan,
3454 .init_hw = e1000_init_hw_ich8lan,
3455 .setup_link = e1000_setup_link_ich8lan,
3456 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3457 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3458};
3459
3460static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3461 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3462 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3463 .commit = NULL,
bc7f75fa 3464 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
f4187b56 3465 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3466 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3467 .get_info = e1000_get_phy_info_ich8lan,
3468 .read_reg = e1000e_read_phy_reg_igp,
3469 .release = e1000_release_swflag_ich8lan,
3470 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3471 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3472 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3473 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3474};
3475
3476static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3477 .acquire = e1000_acquire_nvm_ich8lan,
3478 .read = e1000_read_nvm_ich8lan,
3479 .release = e1000_release_nvm_ich8lan,
3480 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3481 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3482 .validate = e1000_validate_nvm_checksum_ich8lan,
3483 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3484};
3485
3486struct e1000_info e1000_ich8_info = {
3487 .mac = e1000_ich8lan,
3488 .flags = FLAG_HAS_WOL
97ac8cae 3489 | FLAG_IS_ICH
bc7f75fa
AK		 3490 | FLAG_RX_CSUM_ENABLED
3491 | FLAG_HAS_CTRLEXT_ON_LOAD
3492 | FLAG_HAS_AMT
3493 | FLAG_HAS_FLASH
3494 | FLAG_APME_IN_WUC,
3495 .pba = 8,
2adc55c9 3496 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3497 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3498 .mac_ops = &ich8_mac_ops,
3499 .phy_ops = &ich8_phy_ops,
3500 .nvm_ops = &ich8_nvm_ops,
3501};
3502
3503struct e1000_info e1000_ich9_info = {
3504 .mac = e1000_ich9lan,
3505 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3506 | FLAG_IS_ICH
bc7f75fa
AK		 3507 | FLAG_HAS_WOL
3508 | FLAG_RX_CSUM_ENABLED
3509 | FLAG_HAS_CTRLEXT_ON_LOAD
3510 | FLAG_HAS_AMT
3511 | FLAG_HAS_ERT
3512 | FLAG_HAS_FLASH
3513 | FLAG_APME_IN_WUC,
3514 .pba = 10,
2adc55c9 3515 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3516 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3517 .mac_ops = &ich8_mac_ops,
3518 .phy_ops = &ich8_phy_ops,
3519 .nvm_ops = &ich8_nvm_ops,
3520};
3521
f4187b56
BA		 3522struct e1000_info e1000_ich10_info = {
3523 .mac = e1000_ich10lan,
3524 .flags = FLAG_HAS_JUMBO_FRAMES
3525 | FLAG_IS_ICH
3526 | FLAG_HAS_WOL
3527 | FLAG_RX_CSUM_ENABLED
3528 | FLAG_HAS_CTRLEXT_ON_LOAD
3529 | FLAG_HAS_AMT
3530 | FLAG_HAS_ERT
3531 | FLAG_HAS_FLASH
3532 | FLAG_APME_IN_WUC,
3533 .pba = 10,
2adc55c9 3534 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3535 .get_variants = e1000_get_variants_ich8lan,
3536 .mac_ops = &ich8_mac_ops,
3537 .phy_ops = &ich8_phy_ops,
3538 .nvm_ops = &ich8_nvm_ops,
3539};
a4f58f54
BA		 3540
3541struct e1000_info e1000_pch_info = {
3542 .mac = e1000_pchlan,
3543 .flags = FLAG_IS_ICH
3544 | FLAG_HAS_WOL
3545 | FLAG_RX_CSUM_ENABLED
3546 | FLAG_HAS_CTRLEXT_ON_LOAD
3547 | FLAG_HAS_AMT
3548 | FLAG_HAS_FLASH
3549 | FLAG_HAS_JUMBO_FRAMES
3550 | FLAG_APME_IN_WUC,
3551 .pba = 26,
3552 .max_hw_frame_size = 4096,
3553 .get_variants = e1000_get_variants_ich8lan,
3554 .mac_ops = &ich8_mac_ops,
3555 .phy_ops = &ich8_phy_ops,
3556 .nvm_ops = &ich8_nvm_ops,
3557};
Linux kernel - Deliverables
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