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1da177e4 LT |
1 | /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */ |
2 | /* | |
3 | Written/copyright 1997-2001 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | This driver is for the SMC83c170/175 "EPIC" series, as used on the | |
13 | SMC EtherPower II 9432 PCI adapter, and several CardBus cards. | |
14 | ||
15 | The author may be reached as becker@scyld.com, or C/O | |
16 | Scyld Computing Corporation | |
17 | 410 Severn Ave., Suite 210 | |
18 | Annapolis MD 21403 | |
19 | ||
20 | Information and updates available at | |
21 | http://www.scyld.com/network/epic100.html | |
36e1e847 | 22 | [this link no longer provides anything useful -jgarzik] |
1da177e4 LT |
23 | |
24 | --------------------------------------------------------------------- | |
f3b197ac | 25 | |
1da177e4 LT |
26 | */ |
27 | ||
28 | #define DRV_NAME "epic100" | |
d5b20697 AG |
29 | #define DRV_VERSION "2.1" |
30 | #define DRV_RELDATE "Sept 11, 2006" | |
1da177e4 LT |
31 | |
32 | /* The user-configurable values. | |
33 | These may be modified when a driver module is loaded.*/ | |
34 | ||
35 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
36 | ||
37 | /* Used to pass the full-duplex flag, etc. */ | |
38 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
39 | static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
40 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
41 | ||
42 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
43 | Setting to > 1518 effectively disables this feature. */ | |
44 | static int rx_copybreak; | |
45 | ||
46 | /* Operational parameters that are set at compile time. */ | |
47 | ||
48 | /* Keep the ring sizes a power of two for operational efficiency. | |
49 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
50 | Making the Tx ring too large decreases the effectiveness of channel | |
51 | bonding and packet priority. | |
52 | There are no ill effects from too-large receive rings. */ | |
53 | #define TX_RING_SIZE 256 | |
54 | #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */ | |
55 | #define RX_RING_SIZE 256 | |
56 | #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc) | |
57 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc) | |
58 | ||
59 | /* Operational parameters that usually are not changed. */ | |
60 | /* Time in jiffies before concluding the transmitter is hung. */ | |
61 | #define TX_TIMEOUT (2*HZ) | |
62 | ||
63 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
64 | ||
65 | /* Bytes transferred to chip before transmission starts. */ | |
66 | /* Initial threshold, increased on underflow, rounded down to 4 byte units. */ | |
67 | #define TX_FIFO_THRESH 256 | |
68 | #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */ | |
69 | ||
1da177e4 LT |
70 | #include <linux/module.h> |
71 | #include <linux/kernel.h> | |
72 | #include <linux/string.h> | |
73 | #include <linux/timer.h> | |
74 | #include <linux/errno.h> | |
75 | #include <linux/ioport.h> | |
76 | #include <linux/slab.h> | |
77 | #include <linux/interrupt.h> | |
78 | #include <linux/pci.h> | |
79 | #include <linux/delay.h> | |
80 | #include <linux/netdevice.h> | |
81 | #include <linux/etherdevice.h> | |
82 | #include <linux/skbuff.h> | |
83 | #include <linux/init.h> | |
84 | #include <linux/spinlock.h> | |
85 | #include <linux/ethtool.h> | |
86 | #include <linux/mii.h> | |
87 | #include <linux/crc32.h> | |
88 | #include <linux/bitops.h> | |
89 | #include <asm/io.h> | |
90 | #include <asm/uaccess.h> | |
91 | ||
92 | /* These identify the driver base version and may not be removed. */ | |
93 | static char version[] __devinitdata = | |
94 | DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n"; | |
95 | static char version2[] __devinitdata = | |
1da177e4 LT |
96 | " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; |
97 | ||
98 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
99 | MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver"); | |
100 | MODULE_LICENSE("GPL"); | |
101 | ||
102 | module_param(debug, int, 0); | |
103 | module_param(rx_copybreak, int, 0); | |
104 | module_param_array(options, int, NULL, 0); | |
105 | module_param_array(full_duplex, int, NULL, 0); | |
106 | MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)"); | |
107 | MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex"); | |
108 | MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames"); | |
109 | MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)"); | |
110 | ||
111 | /* | |
112 | Theory of Operation | |
113 | ||
114 | I. Board Compatibility | |
115 | ||
116 | This device driver is designed for the SMC "EPIC/100", the SMC | |
117 | single-chip Ethernet controllers for PCI. This chip is used on | |
118 | the SMC EtherPower II boards. | |
119 | ||
120 | II. Board-specific settings | |
121 | ||
122 | PCI bus devices are configured by the system at boot time, so no jumpers | |
123 | need to be set on the board. The system BIOS will assign the | |
124 | PCI INTA signal to a (preferably otherwise unused) system IRQ line. | |
125 | Note: Kernel versions earlier than 1.3.73 do not support shared PCI | |
126 | interrupt lines. | |
127 | ||
128 | III. Driver operation | |
129 | ||
130 | IIIa. Ring buffers | |
131 | ||
132 | IVb. References | |
133 | ||
9ebfd492 AV |
134 | http://www.smsc.com/main/tools/discontinued/83c171.pdf |
135 | http://www.smsc.com/main/tools/discontinued/83c175.pdf | |
1da177e4 LT |
136 | http://scyld.com/expert/NWay.html |
137 | http://www.national.com/pf/DP/DP83840A.html | |
138 | ||
139 | IVc. Errata | |
140 | ||
141 | */ | |
142 | ||
143 | ||
1da177e4 LT |
144 | enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 }; |
145 | ||
146 | #define EPIC_TOTAL_SIZE 0x100 | |
147 | #define USE_IO_OPS 1 | |
1da177e4 LT |
148 | |
149 | typedef enum { | |
150 | SMSC_83C170_0, | |
151 | SMSC_83C170, | |
152 | SMSC_83C175, | |
153 | } chip_t; | |
154 | ||
155 | ||
156 | struct epic_chip_info { | |
157 | const char *name; | |
1da177e4 LT |
158 | int drv_flags; /* Driver use, intended as capability flags. */ |
159 | }; | |
160 | ||
161 | ||
162 | /* indexed by chip_t */ | |
f71e1309 | 163 | static const struct epic_chip_info pci_id_tbl[] = { |
36e1e847 JG |
164 | { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN }, |
165 | { "SMSC EPIC/100 83c170", TYPE2_INTR }, | |
166 | { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN }, | |
1da177e4 LT |
167 | }; |
168 | ||
169 | ||
170 | static struct pci_device_id epic_pci_tbl[] = { | |
171 | { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 }, | |
172 | { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 }, | |
173 | { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID, | |
174 | PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 }, | |
175 | { 0,} | |
176 | }; | |
177 | MODULE_DEVICE_TABLE (pci, epic_pci_tbl); | |
178 | ||
f3b197ac | 179 | |
1da177e4 LT |
180 | #ifndef USE_IO_OPS |
181 | #undef inb | |
182 | #undef inw | |
183 | #undef inl | |
184 | #undef outb | |
185 | #undef outw | |
186 | #undef outl | |
187 | #define inb readb | |
188 | #define inw readw | |
189 | #define inl readl | |
190 | #define outb writeb | |
191 | #define outw writew | |
192 | #define outl writel | |
193 | #endif | |
194 | ||
195 | /* Offsets to registers, using the (ugh) SMC names. */ | |
196 | enum epic_registers { | |
197 | COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14, | |
198 | PCIBurstCnt=0x18, | |
199 | TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */ | |
200 | MIICtrl=0x30, MIIData=0x34, MIICfg=0x38, | |
201 | LAN0=64, /* MAC address. */ | |
202 | MC0=80, /* Multicast filter table. */ | |
203 | RxCtrl=96, TxCtrl=112, TxSTAT=0x74, | |
204 | PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC, | |
205 | }; | |
206 | ||
207 | /* Interrupt register bits, using my own meaningful names. */ | |
208 | enum IntrStatus { | |
209 | TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000, | |
210 | PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000, | |
211 | RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100, | |
212 | TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010, | |
213 | RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001, | |
214 | }; | |
215 | enum CommandBits { | |
216 | StopRx=1, StartRx=2, TxQueued=4, RxQueued=8, | |
217 | StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80, | |
218 | }; | |
219 | ||
220 | #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */ | |
221 | ||
222 | #define EpicNapiEvent (TxEmpty | TxDone | \ | |
223 | RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull) | |
224 | #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent) | |
225 | ||
f71e1309 | 226 | static const u16 media2miictl[16] = { |
1da177e4 LT |
227 | 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0, |
228 | 0, 0, 0, 0, 0, 0, 0, 0 }; | |
229 | ||
9ebfd492 AV |
230 | /* |
231 | * The EPIC100 Rx and Tx buffer descriptors. Note that these | |
232 | * really ARE host-endian; it's not a misannotation. We tell | |
233 | * the card to byteswap them internally on big-endian hosts - | |
234 | * look for #ifdef CONFIG_BIG_ENDIAN in epic_open(). | |
235 | */ | |
1da177e4 LT |
236 | |
237 | struct epic_tx_desc { | |
238 | u32 txstatus; | |
239 | u32 bufaddr; | |
240 | u32 buflength; | |
241 | u32 next; | |
242 | }; | |
243 | ||
244 | struct epic_rx_desc { | |
245 | u32 rxstatus; | |
246 | u32 bufaddr; | |
247 | u32 buflength; | |
248 | u32 next; | |
249 | }; | |
250 | ||
251 | enum desc_status_bits { | |
252 | DescOwn=0x8000, | |
253 | }; | |
254 | ||
255 | #define PRIV_ALIGN 15 /* Required alignment mask */ | |
256 | struct epic_private { | |
257 | struct epic_rx_desc *rx_ring; | |
258 | struct epic_tx_desc *tx_ring; | |
259 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | |
260 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
261 | /* The addresses of receive-in-place skbuffs. */ | |
262 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
263 | ||
264 | dma_addr_t tx_ring_dma; | |
265 | dma_addr_t rx_ring_dma; | |
266 | ||
267 | /* Ring pointers. */ | |
268 | spinlock_t lock; /* Group with Tx control cache line. */ | |
269 | spinlock_t napi_lock; | |
bea3348e | 270 | struct napi_struct napi; |
1da177e4 LT |
271 | unsigned int reschedule_in_poll; |
272 | unsigned int cur_tx, dirty_tx; | |
273 | ||
274 | unsigned int cur_rx, dirty_rx; | |
275 | u32 irq_mask; | |
276 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
277 | ||
278 | struct pci_dev *pci_dev; /* PCI bus location. */ | |
279 | int chip_id, chip_flags; | |
280 | ||
281 | struct net_device_stats stats; | |
282 | struct timer_list timer; /* Media selection timer. */ | |
283 | int tx_threshold; | |
284 | unsigned char mc_filter[8]; | |
285 | signed char phys[4]; /* MII device addresses. */ | |
286 | u16 advertising; /* NWay media advertisement */ | |
287 | int mii_phy_cnt; | |
288 | struct mii_if_info mii; | |
289 | unsigned int tx_full:1; /* The Tx queue is full. */ | |
290 | unsigned int default_port:4; /* Last dev->if_port value. */ | |
291 | }; | |
292 | ||
293 | static int epic_open(struct net_device *dev); | |
294 | static int read_eeprom(long ioaddr, int location); | |
295 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
296 | static void mdio_write(struct net_device *dev, int phy_id, int loc, int val); | |
297 | static void epic_restart(struct net_device *dev); | |
298 | static void epic_timer(unsigned long data); | |
299 | static void epic_tx_timeout(struct net_device *dev); | |
300 | static void epic_init_ring(struct net_device *dev); | |
301 | static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
302 | static int epic_rx(struct net_device *dev, int budget); | |
bea3348e | 303 | static int epic_poll(struct napi_struct *napi, int budget); |
7d12e780 | 304 | static irqreturn_t epic_interrupt(int irq, void *dev_instance); |
1da177e4 | 305 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
7282d491 | 306 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 LT |
307 | static int epic_close(struct net_device *dev); |
308 | static struct net_device_stats *epic_get_stats(struct net_device *dev); | |
309 | static void set_rx_mode(struct net_device *dev); | |
310 | ||
f3b197ac | 311 | |
1da177e4 LT |
312 | |
313 | static int __devinit epic_init_one (struct pci_dev *pdev, | |
314 | const struct pci_device_id *ent) | |
315 | { | |
316 | static int card_idx = -1; | |
317 | long ioaddr; | |
318 | int chip_idx = (int) ent->driver_data; | |
319 | int irq; | |
320 | struct net_device *dev; | |
321 | struct epic_private *ep; | |
322 | int i, ret, option = 0, duplex = 0; | |
323 | void *ring_space; | |
324 | dma_addr_t ring_dma; | |
325 | ||
326 | /* when built into the kernel, we only print version if device is found */ | |
327 | #ifndef MODULE | |
328 | static int printed_version; | |
329 | if (!printed_version++) | |
2c2a8c53 MD |
330 | printk (KERN_INFO "%s" KERN_INFO "%s", |
331 | version, version2); | |
1da177e4 | 332 | #endif |
f3b197ac | 333 | |
1da177e4 | 334 | card_idx++; |
f3b197ac | 335 | |
1da177e4 LT |
336 | ret = pci_enable_device(pdev); |
337 | if (ret) | |
338 | goto out; | |
339 | irq = pdev->irq; | |
340 | ||
36e1e847 | 341 | if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) { |
9b91cf9d | 342 | dev_err(&pdev->dev, "no PCI region space\n"); |
1da177e4 LT |
343 | ret = -ENODEV; |
344 | goto err_out_disable; | |
345 | } | |
f3b197ac | 346 | |
1da177e4 LT |
347 | pci_set_master(pdev); |
348 | ||
349 | ret = pci_request_regions(pdev, DRV_NAME); | |
350 | if (ret < 0) | |
351 | goto err_out_disable; | |
352 | ||
353 | ret = -ENOMEM; | |
354 | ||
355 | dev = alloc_etherdev(sizeof (*ep)); | |
356 | if (!dev) { | |
9b91cf9d | 357 | dev_err(&pdev->dev, "no memory for eth device\n"); |
1da177e4 LT |
358 | goto err_out_free_res; |
359 | } | |
1da177e4 LT |
360 | SET_NETDEV_DEV(dev, &pdev->dev); |
361 | ||
362 | #ifdef USE_IO_OPS | |
363 | ioaddr = pci_resource_start (pdev, 0); | |
364 | #else | |
365 | ioaddr = pci_resource_start (pdev, 1); | |
275f165f | 366 | ioaddr = (long) pci_ioremap_bar(pdev, 1); |
1da177e4 | 367 | if (!ioaddr) { |
9b91cf9d | 368 | dev_err(&pdev->dev, "ioremap failed\n"); |
1da177e4 LT |
369 | goto err_out_free_netdev; |
370 | } | |
371 | #endif | |
372 | ||
373 | pci_set_drvdata(pdev, dev); | |
4cf1653a | 374 | ep = netdev_priv(dev); |
1da177e4 LT |
375 | ep->mii.dev = dev; |
376 | ep->mii.mdio_read = mdio_read; | |
377 | ep->mii.mdio_write = mdio_write; | |
378 | ep->mii.phy_id_mask = 0x1f; | |
379 | ep->mii.reg_num_mask = 0x1f; | |
380 | ||
381 | ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma); | |
382 | if (!ring_space) | |
383 | goto err_out_iounmap; | |
384 | ep->tx_ring = (struct epic_tx_desc *)ring_space; | |
385 | ep->tx_ring_dma = ring_dma; | |
386 | ||
387 | ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma); | |
388 | if (!ring_space) | |
389 | goto err_out_unmap_tx; | |
390 | ep->rx_ring = (struct epic_rx_desc *)ring_space; | |
391 | ep->rx_ring_dma = ring_dma; | |
392 | ||
393 | if (dev->mem_start) { | |
394 | option = dev->mem_start; | |
395 | duplex = (dev->mem_start & 16) ? 1 : 0; | |
396 | } else if (card_idx >= 0 && card_idx < MAX_UNITS) { | |
397 | if (options[card_idx] >= 0) | |
398 | option = options[card_idx]; | |
399 | if (full_duplex[card_idx] >= 0) | |
400 | duplex = full_duplex[card_idx]; | |
401 | } | |
402 | ||
403 | dev->base_addr = ioaddr; | |
404 | dev->irq = irq; | |
405 | ||
406 | spin_lock_init(&ep->lock); | |
407 | spin_lock_init(&ep->napi_lock); | |
408 | ep->reschedule_in_poll = 0; | |
409 | ||
410 | /* Bring the chip out of low-power mode. */ | |
411 | outl(0x4200, ioaddr + GENCTL); | |
412 | /* Magic?! If we don't set this bit the MII interface won't work. */ | |
413 | /* This magic is documented in SMSC app note 7.15 */ | |
414 | for (i = 16; i > 0; i--) | |
415 | outl(0x0008, ioaddr + TEST1); | |
416 | ||
417 | /* Turn on the MII transceiver. */ | |
418 | outl(0x12, ioaddr + MIICfg); | |
419 | if (chip_idx == 1) | |
420 | outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL); | |
421 | outl(0x0200, ioaddr + GENCTL); | |
422 | ||
423 | /* Note: the '175 does not have a serial EEPROM. */ | |
424 | for (i = 0; i < 3; i++) | |
9ebfd492 | 425 | ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4)); |
1da177e4 LT |
426 | |
427 | if (debug > 2) { | |
2e8a538d | 428 | dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n"); |
1da177e4 LT |
429 | for (i = 0; i < 64; i++) |
430 | printk(" %4.4x%s", read_eeprom(ioaddr, i), | |
431 | i % 16 == 15 ? "\n" : ""); | |
432 | } | |
433 | ||
434 | ep->pci_dev = pdev; | |
435 | ep->chip_id = chip_idx; | |
436 | ep->chip_flags = pci_id_tbl[chip_idx].drv_flags; | |
f3b197ac | 437 | ep->irq_mask = |
1da177e4 LT |
438 | (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170) |
439 | | CntFull | TxUnderrun | EpicNapiEvent; | |
440 | ||
441 | /* Find the connected MII xcvrs. | |
442 | Doing this in open() would allow detecting external xcvrs later, but | |
443 | takes much time and no cards have external MII. */ | |
444 | { | |
445 | int phy, phy_idx = 0; | |
446 | for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) { | |
447 | int mii_status = mdio_read(dev, phy, MII_BMSR); | |
448 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
449 | ep->phys[phy_idx++] = phy; | |
9b91cf9d | 450 | dev_info(&pdev->dev, |
2e8a538d JG |
451 | "MII transceiver #%d control " |
452 | "%4.4x status %4.4x.\n", | |
453 | phy, mdio_read(dev, phy, 0), mii_status); | |
1da177e4 LT |
454 | } |
455 | } | |
456 | ep->mii_phy_cnt = phy_idx; | |
457 | if (phy_idx != 0) { | |
458 | phy = ep->phys[0]; | |
459 | ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
9b91cf9d | 460 | dev_info(&pdev->dev, |
2e8a538d | 461 | "Autonegotiation advertising %4.4x link " |
1da177e4 | 462 | "partner %4.4x.\n", |
2e8a538d | 463 | ep->mii.advertising, mdio_read(dev, phy, 5)); |
1da177e4 | 464 | } else if ( ! (ep->chip_flags & NO_MII)) { |
9b91cf9d | 465 | dev_warn(&pdev->dev, |
2e8a538d | 466 | "***WARNING***: No MII transceiver found!\n"); |
1da177e4 LT |
467 | /* Use the known PHY address of the EPII. */ |
468 | ep->phys[0] = 3; | |
469 | } | |
470 | ep->mii.phy_id = ep->phys[0]; | |
471 | } | |
472 | ||
473 | /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */ | |
474 | if (ep->chip_flags & MII_PWRDWN) | |
475 | outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL); | |
476 | outl(0x0008, ioaddr + GENCTL); | |
477 | ||
478 | /* The lower four bits are the media type. */ | |
479 | if (duplex) { | |
480 | ep->mii.force_media = ep->mii.full_duplex = 1; | |
9b91cf9d | 481 | dev_info(&pdev->dev, "Forced full duplex requested.\n"); |
1da177e4 LT |
482 | } |
483 | dev->if_port = ep->default_port = option; | |
484 | ||
485 | /* The Epic-specific entries in the device structure. */ | |
486 | dev->open = &epic_open; | |
487 | dev->hard_start_xmit = &epic_start_xmit; | |
488 | dev->stop = &epic_close; | |
489 | dev->get_stats = &epic_get_stats; | |
490 | dev->set_multicast_list = &set_rx_mode; | |
491 | dev->do_ioctl = &netdev_ioctl; | |
492 | dev->ethtool_ops = &netdev_ethtool_ops; | |
493 | dev->watchdog_timeo = TX_TIMEOUT; | |
494 | dev->tx_timeout = &epic_tx_timeout; | |
bea3348e | 495 | netif_napi_add(dev, &ep->napi, epic_poll, 64); |
1da177e4 LT |
496 | |
497 | ret = register_netdev(dev); | |
498 | if (ret < 0) | |
499 | goto err_out_unmap_rx; | |
500 | ||
e174961c | 501 | printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n", |
0795af57 | 502 | dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq, |
e174961c | 503 | dev->dev_addr); |
1da177e4 LT |
504 | |
505 | out: | |
506 | return ret; | |
507 | ||
508 | err_out_unmap_rx: | |
509 | pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma); | |
510 | err_out_unmap_tx: | |
511 | pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma); | |
512 | err_out_iounmap: | |
513 | #ifndef USE_IO_OPS | |
514 | iounmap(ioaddr); | |
515 | err_out_free_netdev: | |
516 | #endif | |
517 | free_netdev(dev); | |
518 | err_out_free_res: | |
519 | pci_release_regions(pdev); | |
520 | err_out_disable: | |
521 | pci_disable_device(pdev); | |
522 | goto out; | |
523 | } | |
f3b197ac | 524 | |
1da177e4 LT |
525 | /* Serial EEPROM section. */ |
526 | ||
527 | /* EEPROM_Ctrl bits. */ | |
528 | #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ | |
529 | #define EE_CS 0x02 /* EEPROM chip select. */ | |
530 | #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */ | |
531 | #define EE_WRITE_0 0x01 | |
532 | #define EE_WRITE_1 0x09 | |
533 | #define EE_DATA_READ 0x10 /* EEPROM chip data out. */ | |
534 | #define EE_ENB (0x0001 | EE_CS) | |
535 | ||
536 | /* Delay between EEPROM clock transitions. | |
537 | This serves to flush the operation to the PCI bus. | |
538 | */ | |
539 | ||
540 | #define eeprom_delay() inl(ee_addr) | |
541 | ||
542 | /* The EEPROM commands include the alway-set leading bit. */ | |
543 | #define EE_WRITE_CMD (5 << 6) | |
544 | #define EE_READ64_CMD (6 << 6) | |
545 | #define EE_READ256_CMD (6 << 8) | |
546 | #define EE_ERASE_CMD (7 << 6) | |
547 | ||
548 | static void epic_disable_int(struct net_device *dev, struct epic_private *ep) | |
549 | { | |
550 | long ioaddr = dev->base_addr; | |
551 | ||
552 | outl(0x00000000, ioaddr + INTMASK); | |
553 | } | |
554 | ||
555 | static inline void __epic_pci_commit(long ioaddr) | |
556 | { | |
557 | #ifndef USE_IO_OPS | |
558 | inl(ioaddr + INTMASK); | |
559 | #endif | |
560 | } | |
561 | ||
562 | static inline void epic_napi_irq_off(struct net_device *dev, | |
563 | struct epic_private *ep) | |
564 | { | |
565 | long ioaddr = dev->base_addr; | |
566 | ||
567 | outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK); | |
568 | __epic_pci_commit(ioaddr); | |
569 | } | |
570 | ||
571 | static inline void epic_napi_irq_on(struct net_device *dev, | |
572 | struct epic_private *ep) | |
573 | { | |
574 | long ioaddr = dev->base_addr; | |
575 | ||
576 | /* No need to commit possible posted write */ | |
577 | outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK); | |
578 | } | |
579 | ||
580 | static int __devinit read_eeprom(long ioaddr, int location) | |
581 | { | |
582 | int i; | |
583 | int retval = 0; | |
584 | long ee_addr = ioaddr + EECTL; | |
585 | int read_cmd = location | | |
586 | (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD); | |
587 | ||
588 | outl(EE_ENB & ~EE_CS, ee_addr); | |
589 | outl(EE_ENB, ee_addr); | |
590 | ||
591 | /* Shift the read command bits out. */ | |
592 | for (i = 12; i >= 0; i--) { | |
593 | short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0; | |
594 | outl(EE_ENB | dataval, ee_addr); | |
595 | eeprom_delay(); | |
596 | outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); | |
597 | eeprom_delay(); | |
598 | } | |
599 | outl(EE_ENB, ee_addr); | |
600 | ||
601 | for (i = 16; i > 0; i--) { | |
602 | outl(EE_ENB | EE_SHIFT_CLK, ee_addr); | |
603 | eeprom_delay(); | |
604 | retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); | |
605 | outl(EE_ENB, ee_addr); | |
606 | eeprom_delay(); | |
607 | } | |
608 | ||
609 | /* Terminate the EEPROM access. */ | |
610 | outl(EE_ENB & ~EE_CS, ee_addr); | |
611 | return retval; | |
612 | } | |
613 | ||
614 | #define MII_READOP 1 | |
615 | #define MII_WRITEOP 2 | |
616 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
617 | { | |
618 | long ioaddr = dev->base_addr; | |
619 | int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP; | |
620 | int i; | |
621 | ||
622 | outl(read_cmd, ioaddr + MIICtrl); | |
623 | /* Typical operation takes 25 loops. */ | |
624 | for (i = 400; i > 0; i--) { | |
625 | barrier(); | |
626 | if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) { | |
627 | /* Work around read failure bug. */ | |
628 | if (phy_id == 1 && location < 6 | |
629 | && inw(ioaddr + MIIData) == 0xffff) { | |
630 | outl(read_cmd, ioaddr + MIICtrl); | |
631 | continue; | |
632 | } | |
633 | return inw(ioaddr + MIIData); | |
634 | } | |
635 | } | |
636 | return 0xffff; | |
637 | } | |
638 | ||
639 | static void mdio_write(struct net_device *dev, int phy_id, int loc, int value) | |
640 | { | |
641 | long ioaddr = dev->base_addr; | |
642 | int i; | |
643 | ||
644 | outw(value, ioaddr + MIIData); | |
645 | outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl); | |
f3b197ac | 646 | for (i = 10000; i > 0; i--) { |
1da177e4 LT |
647 | barrier(); |
648 | if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0) | |
649 | break; | |
650 | } | |
651 | return; | |
652 | } | |
653 | ||
f3b197ac | 654 | |
1da177e4 LT |
655 | static int epic_open(struct net_device *dev) |
656 | { | |
4cf1653a | 657 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
658 | long ioaddr = dev->base_addr; |
659 | int i; | |
660 | int retval; | |
661 | ||
662 | /* Soft reset the chip. */ | |
663 | outl(0x4001, ioaddr + GENCTL); | |
664 | ||
bea3348e SH |
665 | napi_enable(&ep->napi); |
666 | if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev))) { | |
667 | napi_disable(&ep->napi); | |
1da177e4 | 668 | return retval; |
bea3348e | 669 | } |
1da177e4 LT |
670 | |
671 | epic_init_ring(dev); | |
672 | ||
673 | outl(0x4000, ioaddr + GENCTL); | |
674 | /* This magic is documented in SMSC app note 7.15 */ | |
675 | for (i = 16; i > 0; i--) | |
676 | outl(0x0008, ioaddr + TEST1); | |
677 | ||
678 | /* Pull the chip out of low-power mode, enable interrupts, and set for | |
679 | PCI read multiple. The MIIcfg setting and strange write order are | |
680 | required by the details of which bits are reset and the transceiver | |
681 | wiring on the Ositech CardBus card. | |
682 | */ | |
683 | #if 0 | |
684 | outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg); | |
685 | #endif | |
686 | if (ep->chip_flags & MII_PWRDWN) | |
687 | outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL); | |
688 | ||
9ebfd492 AV |
689 | /* Tell the chip to byteswap descriptors on big-endian hosts */ |
690 | #ifdef CONFIG_BIG_ENDIAN | |
1da177e4 LT |
691 | outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); |
692 | inl(ioaddr + GENCTL); | |
693 | outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); | |
694 | #else | |
695 | outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); | |
696 | inl(ioaddr + GENCTL); | |
697 | outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); | |
698 | #endif | |
699 | ||
700 | udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */ | |
f3b197ac | 701 | |
1da177e4 | 702 | for (i = 0; i < 3; i++) |
9ebfd492 | 703 | outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4); |
1da177e4 LT |
704 | |
705 | ep->tx_threshold = TX_FIFO_THRESH; | |
706 | outl(ep->tx_threshold, ioaddr + TxThresh); | |
707 | ||
708 | if (media2miictl[dev->if_port & 15]) { | |
709 | if (ep->mii_phy_cnt) | |
710 | mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]); | |
711 | if (dev->if_port == 1) { | |
712 | if (debug > 1) | |
713 | printk(KERN_INFO "%s: Using the 10base2 transceiver, MII " | |
714 | "status %4.4x.\n", | |
715 | dev->name, mdio_read(dev, ep->phys[0], MII_BMSR)); | |
716 | } | |
717 | } else { | |
718 | int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA); | |
719 | if (mii_lpa != 0xffff) { | |
720 | if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL) | |
721 | ep->mii.full_duplex = 1; | |
722 | else if (! (mii_lpa & LPA_LPACK)) | |
723 | mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART); | |
724 | if (debug > 1) | |
725 | printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d" | |
726 | " register read of %4.4x.\n", dev->name, | |
727 | ep->mii.full_duplex ? "full" : "half", | |
728 | ep->phys[0], mii_lpa); | |
729 | } | |
730 | } | |
731 | ||
732 | outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl); | |
733 | outl(ep->rx_ring_dma, ioaddr + PRxCDAR); | |
734 | outl(ep->tx_ring_dma, ioaddr + PTxCDAR); | |
735 | ||
736 | /* Start the chip's Rx process. */ | |
737 | set_rx_mode(dev); | |
738 | outl(StartRx | RxQueued, ioaddr + COMMAND); | |
739 | ||
740 | netif_start_queue(dev); | |
741 | ||
742 | /* Enable interrupts by setting the interrupt mask. */ | |
743 | outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170) | |
f3b197ac | 744 | | CntFull | TxUnderrun |
1da177e4 LT |
745 | | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK); |
746 | ||
747 | if (debug > 1) | |
748 | printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x " | |
749 | "%s-duplex.\n", | |
750 | dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL), | |
751 | ep->mii.full_duplex ? "full" : "half"); | |
752 | ||
753 | /* Set the timer to switch to check for link beat and perhaps switch | |
754 | to an alternate media type. */ | |
755 | init_timer(&ep->timer); | |
756 | ep->timer.expires = jiffies + 3*HZ; | |
757 | ep->timer.data = (unsigned long)dev; | |
758 | ep->timer.function = &epic_timer; /* timer handler */ | |
759 | add_timer(&ep->timer); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | /* Reset the chip to recover from a PCI transaction error. | |
765 | This may occur at interrupt time. */ | |
766 | static void epic_pause(struct net_device *dev) | |
767 | { | |
768 | long ioaddr = dev->base_addr; | |
4cf1653a | 769 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
770 | |
771 | netif_stop_queue (dev); | |
f3b197ac | 772 | |
1da177e4 LT |
773 | /* Disable interrupts by clearing the interrupt mask. */ |
774 | outl(0x00000000, ioaddr + INTMASK); | |
775 | /* Stop the chip's Tx and Rx DMA processes. */ | |
776 | outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND); | |
777 | ||
778 | /* Update the error counts. */ | |
779 | if (inw(ioaddr + COMMAND) != 0xffff) { | |
780 | ep->stats.rx_missed_errors += inb(ioaddr + MPCNT); | |
781 | ep->stats.rx_frame_errors += inb(ioaddr + ALICNT); | |
782 | ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT); | |
783 | } | |
784 | ||
785 | /* Remove the packets on the Rx queue. */ | |
786 | epic_rx(dev, RX_RING_SIZE); | |
787 | } | |
788 | ||
789 | static void epic_restart(struct net_device *dev) | |
790 | { | |
791 | long ioaddr = dev->base_addr; | |
4cf1653a | 792 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
793 | int i; |
794 | ||
795 | /* Soft reset the chip. */ | |
796 | outl(0x4001, ioaddr + GENCTL); | |
797 | ||
798 | printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n", | |
799 | dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx); | |
800 | udelay(1); | |
801 | ||
802 | /* This magic is documented in SMSC app note 7.15 */ | |
803 | for (i = 16; i > 0; i--) | |
804 | outl(0x0008, ioaddr + TEST1); | |
805 | ||
9ebfd492 | 806 | #ifdef CONFIG_BIG_ENDIAN |
1da177e4 LT |
807 | outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); |
808 | #else | |
809 | outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL); | |
810 | #endif | |
811 | outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg); | |
812 | if (ep->chip_flags & MII_PWRDWN) | |
813 | outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL); | |
814 | ||
815 | for (i = 0; i < 3; i++) | |
9ebfd492 | 816 | outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4); |
1da177e4 LT |
817 | |
818 | ep->tx_threshold = TX_FIFO_THRESH; | |
819 | outl(ep->tx_threshold, ioaddr + TxThresh); | |
820 | outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl); | |
821 | outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)* | |
822 | sizeof(struct epic_rx_desc), ioaddr + PRxCDAR); | |
823 | outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)* | |
824 | sizeof(struct epic_tx_desc), ioaddr + PTxCDAR); | |
825 | ||
826 | /* Start the chip's Rx process. */ | |
827 | set_rx_mode(dev); | |
828 | outl(StartRx | RxQueued, ioaddr + COMMAND); | |
829 | ||
830 | /* Enable interrupts by setting the interrupt mask. */ | |
831 | outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170) | |
832 | | CntFull | TxUnderrun | |
833 | | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK); | |
834 | ||
835 | printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x" | |
836 | " interrupt %4.4x.\n", | |
837 | dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL), | |
838 | (int)inl(ioaddr + INTSTAT)); | |
839 | return; | |
840 | } | |
841 | ||
842 | static void check_media(struct net_device *dev) | |
843 | { | |
4cf1653a | 844 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
845 | long ioaddr = dev->base_addr; |
846 | int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0; | |
847 | int negotiated = mii_lpa & ep->mii.advertising; | |
848 | int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; | |
849 | ||
850 | if (ep->mii.force_media) | |
851 | return; | |
852 | if (mii_lpa == 0xffff) /* Bogus read */ | |
853 | return; | |
854 | if (ep->mii.full_duplex != duplex) { | |
855 | ep->mii.full_duplex = duplex; | |
856 | printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link" | |
857 | " partner capability of %4.4x.\n", dev->name, | |
858 | ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa); | |
859 | outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl); | |
860 | } | |
861 | } | |
862 | ||
863 | static void epic_timer(unsigned long data) | |
864 | { | |
865 | struct net_device *dev = (struct net_device *)data; | |
4cf1653a | 866 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
867 | long ioaddr = dev->base_addr; |
868 | int next_tick = 5*HZ; | |
869 | ||
870 | if (debug > 3) { | |
871 | printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n", | |
872 | dev->name, (int)inl(ioaddr + TxSTAT)); | |
873 | printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x " | |
874 | "IntStatus %4.4x RxStatus %4.4x.\n", | |
875 | dev->name, (int)inl(ioaddr + INTMASK), | |
876 | (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT)); | |
877 | } | |
878 | ||
879 | check_media(dev); | |
880 | ||
881 | ep->timer.expires = jiffies + next_tick; | |
882 | add_timer(&ep->timer); | |
883 | } | |
884 | ||
885 | static void epic_tx_timeout(struct net_device *dev) | |
886 | { | |
4cf1653a | 887 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
888 | long ioaddr = dev->base_addr; |
889 | ||
890 | if (debug > 0) { | |
891 | printk(KERN_WARNING "%s: Transmit timeout using MII device, " | |
892 | "Tx status %4.4x.\n", | |
893 | dev->name, (int)inw(ioaddr + TxSTAT)); | |
894 | if (debug > 1) { | |
895 | printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n", | |
896 | dev->name, ep->dirty_tx, ep->cur_tx); | |
897 | } | |
898 | } | |
899 | if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */ | |
900 | ep->stats.tx_fifo_errors++; | |
901 | outl(RestartTx, ioaddr + COMMAND); | |
902 | } else { | |
903 | epic_restart(dev); | |
904 | outl(TxQueued, dev->base_addr + COMMAND); | |
905 | } | |
906 | ||
907 | dev->trans_start = jiffies; | |
908 | ep->stats.tx_errors++; | |
909 | if (!ep->tx_full) | |
910 | netif_wake_queue(dev); | |
911 | } | |
912 | ||
913 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
914 | static void epic_init_ring(struct net_device *dev) | |
915 | { | |
4cf1653a | 916 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
917 | int i; |
918 | ||
919 | ep->tx_full = 0; | |
920 | ep->dirty_tx = ep->cur_tx = 0; | |
921 | ep->cur_rx = ep->dirty_rx = 0; | |
922 | ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
923 | ||
924 | /* Initialize all Rx descriptors. */ | |
925 | for (i = 0; i < RX_RING_SIZE; i++) { | |
926 | ep->rx_ring[i].rxstatus = 0; | |
9ebfd492 | 927 | ep->rx_ring[i].buflength = ep->rx_buf_sz; |
f3b197ac | 928 | ep->rx_ring[i].next = ep->rx_ring_dma + |
1da177e4 LT |
929 | (i+1)*sizeof(struct epic_rx_desc); |
930 | ep->rx_skbuff[i] = NULL; | |
931 | } | |
932 | /* Mark the last entry as wrapping the ring. */ | |
933 | ep->rx_ring[i-1].next = ep->rx_ring_dma; | |
934 | ||
935 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
936 | for (i = 0; i < RX_RING_SIZE; i++) { | |
937 | struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz); | |
938 | ep->rx_skbuff[i] = skb; | |
939 | if (skb == NULL) | |
940 | break; | |
1da177e4 | 941 | skb_reserve(skb, 2); /* 16 byte align the IP header. */ |
f3b197ac | 942 | ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev, |
689be439 | 943 | skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE); |
9ebfd492 | 944 | ep->rx_ring[i].rxstatus = DescOwn; |
1da177e4 LT |
945 | } |
946 | ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
947 | ||
948 | /* The Tx buffer descriptor is filled in as needed, but we | |
949 | do need to clear the ownership bit. */ | |
950 | for (i = 0; i < TX_RING_SIZE; i++) { | |
951 | ep->tx_skbuff[i] = NULL; | |
952 | ep->tx_ring[i].txstatus = 0x0000; | |
f3b197ac | 953 | ep->tx_ring[i].next = ep->tx_ring_dma + |
1da177e4 LT |
954 | (i+1)*sizeof(struct epic_tx_desc); |
955 | } | |
956 | ep->tx_ring[i-1].next = ep->tx_ring_dma; | |
957 | return; | |
958 | } | |
959 | ||
960 | static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
961 | { | |
4cf1653a | 962 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
963 | int entry, free_count; |
964 | u32 ctrl_word; | |
965 | unsigned long flags; | |
f3b197ac | 966 | |
5b057c6b HX |
967 | if (skb_padto(skb, ETH_ZLEN)) |
968 | return 0; | |
1da177e4 LT |
969 | |
970 | /* Caution: the write order is important here, set the field with the | |
971 | "ownership" bit last. */ | |
972 | ||
973 | /* Calculate the next Tx descriptor entry. */ | |
974 | spin_lock_irqsave(&ep->lock, flags); | |
975 | free_count = ep->cur_tx - ep->dirty_tx; | |
976 | entry = ep->cur_tx % TX_RING_SIZE; | |
977 | ||
978 | ep->tx_skbuff[entry] = skb; | |
f3b197ac | 979 | ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data, |
1da177e4 LT |
980 | skb->len, PCI_DMA_TODEVICE); |
981 | if (free_count < TX_QUEUE_LEN/2) {/* Typical path */ | |
9ebfd492 | 982 | ctrl_word = 0x100000; /* No interrupt */ |
1da177e4 | 983 | } else if (free_count == TX_QUEUE_LEN/2) { |
9ebfd492 | 984 | ctrl_word = 0x140000; /* Tx-done intr. */ |
1da177e4 | 985 | } else if (free_count < TX_QUEUE_LEN - 1) { |
9ebfd492 | 986 | ctrl_word = 0x100000; /* No Tx-done intr. */ |
1da177e4 LT |
987 | } else { |
988 | /* Leave room for an additional entry. */ | |
9ebfd492 | 989 | ctrl_word = 0x140000; /* Tx-done intr. */ |
1da177e4 LT |
990 | ep->tx_full = 1; |
991 | } | |
9ebfd492 | 992 | ep->tx_ring[entry].buflength = ctrl_word | skb->len; |
1da177e4 LT |
993 | ep->tx_ring[entry].txstatus = |
994 | ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16) | |
9ebfd492 | 995 | | DescOwn; |
1da177e4 LT |
996 | |
997 | ep->cur_tx++; | |
998 | if (ep->tx_full) | |
999 | netif_stop_queue(dev); | |
1000 | ||
1001 | spin_unlock_irqrestore(&ep->lock, flags); | |
1002 | /* Trigger an immediate transmit demand. */ | |
1003 | outl(TxQueued, dev->base_addr + COMMAND); | |
1004 | ||
1005 | dev->trans_start = jiffies; | |
1006 | if (debug > 4) | |
1007 | printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, " | |
1008 | "flag %2.2x Tx status %8.8x.\n", | |
1009 | dev->name, (int)skb->len, entry, ctrl_word, | |
1010 | (int)inl(dev->base_addr + TxSTAT)); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
1015 | static void epic_tx_error(struct net_device *dev, struct epic_private *ep, | |
1016 | int status) | |
1017 | { | |
1018 | struct net_device_stats *stats = &ep->stats; | |
1019 | ||
1020 | #ifndef final_version | |
1021 | /* There was an major error, log it. */ | |
1022 | if (debug > 1) | |
1023 | printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n", | |
1024 | dev->name, status); | |
1025 | #endif | |
1026 | stats->tx_errors++; | |
1027 | if (status & 0x1050) | |
1028 | stats->tx_aborted_errors++; | |
1029 | if (status & 0x0008) | |
1030 | stats->tx_carrier_errors++; | |
1031 | if (status & 0x0040) | |
1032 | stats->tx_window_errors++; | |
1033 | if (status & 0x0010) | |
1034 | stats->tx_fifo_errors++; | |
1035 | } | |
1036 | ||
1037 | static void epic_tx(struct net_device *dev, struct epic_private *ep) | |
1038 | { | |
1039 | unsigned int dirty_tx, cur_tx; | |
1040 | ||
1041 | /* | |
1042 | * Note: if this lock becomes a problem we can narrow the locked | |
1043 | * region at the cost of occasionally grabbing the lock more times. | |
1044 | */ | |
1045 | cur_tx = ep->cur_tx; | |
1046 | for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) { | |
1047 | struct sk_buff *skb; | |
1048 | int entry = dirty_tx % TX_RING_SIZE; | |
9ebfd492 | 1049 | int txstatus = ep->tx_ring[entry].txstatus; |
1da177e4 LT |
1050 | |
1051 | if (txstatus & DescOwn) | |
1052 | break; /* It still hasn't been Txed */ | |
1053 | ||
1054 | if (likely(txstatus & 0x0001)) { | |
1055 | ep->stats.collisions += (txstatus >> 8) & 15; | |
1056 | ep->stats.tx_packets++; | |
1057 | ep->stats.tx_bytes += ep->tx_skbuff[entry]->len; | |
1058 | } else | |
1059 | epic_tx_error(dev, ep, txstatus); | |
1060 | ||
1061 | /* Free the original skb. */ | |
1062 | skb = ep->tx_skbuff[entry]; | |
f3b197ac | 1063 | pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr, |
1da177e4 LT |
1064 | skb->len, PCI_DMA_TODEVICE); |
1065 | dev_kfree_skb_irq(skb); | |
1066 | ep->tx_skbuff[entry] = NULL; | |
1067 | } | |
1068 | ||
1069 | #ifndef final_version | |
1070 | if (cur_tx - dirty_tx > TX_RING_SIZE) { | |
1071 | printk(KERN_WARNING | |
1072 | "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
1073 | dev->name, dirty_tx, cur_tx, ep->tx_full); | |
1074 | dirty_tx += TX_RING_SIZE; | |
1075 | } | |
1076 | #endif | |
1077 | ep->dirty_tx = dirty_tx; | |
1078 | if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) { | |
1079 | /* The ring is no longer full, allow new TX entries. */ | |
1080 | ep->tx_full = 0; | |
1081 | netif_wake_queue(dev); | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1086 | after the Tx thread. */ | |
7d12e780 | 1087 | static irqreturn_t epic_interrupt(int irq, void *dev_instance) |
1da177e4 LT |
1088 | { |
1089 | struct net_device *dev = dev_instance; | |
4cf1653a | 1090 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1091 | long ioaddr = dev->base_addr; |
1092 | unsigned int handled = 0; | |
1093 | int status; | |
1094 | ||
1095 | status = inl(ioaddr + INTSTAT); | |
1096 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1097 | outl(status & EpicNormalEvent, ioaddr + INTSTAT); | |
1098 | ||
1099 | if (debug > 4) { | |
1100 | printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new " | |
1101 | "intstat=%#8.8x.\n", dev->name, status, | |
1102 | (int)inl(ioaddr + INTSTAT)); | |
1103 | } | |
1104 | ||
1105 | if ((status & IntrSummary) == 0) | |
1106 | goto out; | |
1107 | ||
1108 | handled = 1; | |
1109 | ||
1110 | if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) { | |
1111 | spin_lock(&ep->napi_lock); | |
bea3348e | 1112 | if (netif_rx_schedule_prep(dev, &ep->napi)) { |
1da177e4 | 1113 | epic_napi_irq_off(dev, ep); |
bea3348e | 1114 | __netif_rx_schedule(dev, &ep->napi); |
1da177e4 LT |
1115 | } else |
1116 | ep->reschedule_in_poll++; | |
1117 | spin_unlock(&ep->napi_lock); | |
1118 | } | |
1119 | status &= ~EpicNapiEvent; | |
1120 | ||
1121 | /* Check uncommon events all at once. */ | |
1122 | if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) { | |
1123 | if (status == EpicRemoved) | |
1124 | goto out; | |
1125 | ||
1126 | /* Always update the error counts to avoid overhead later. */ | |
1127 | ep->stats.rx_missed_errors += inb(ioaddr + MPCNT); | |
1128 | ep->stats.rx_frame_errors += inb(ioaddr + ALICNT); | |
1129 | ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT); | |
1130 | ||
1131 | if (status & TxUnderrun) { /* Tx FIFO underflow. */ | |
1132 | ep->stats.tx_fifo_errors++; | |
1133 | outl(ep->tx_threshold += 128, ioaddr + TxThresh); | |
1134 | /* Restart the transmit process. */ | |
1135 | outl(RestartTx, ioaddr + COMMAND); | |
1136 | } | |
1137 | if (status & PCIBusErr170) { | |
1138 | printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n", | |
1139 | dev->name, status); | |
1140 | epic_pause(dev); | |
1141 | epic_restart(dev); | |
1142 | } | |
1143 | /* Clear all error sources. */ | |
1144 | outl(status & 0x7f18, ioaddr + INTSTAT); | |
1145 | } | |
1146 | ||
1147 | out: | |
1148 | if (debug > 3) { | |
1149 | printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n", | |
1150 | dev->name, status); | |
1151 | } | |
1152 | ||
1153 | return IRQ_RETVAL(handled); | |
1154 | } | |
1155 | ||
1156 | static int epic_rx(struct net_device *dev, int budget) | |
1157 | { | |
4cf1653a | 1158 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1159 | int entry = ep->cur_rx % RX_RING_SIZE; |
1160 | int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx; | |
1161 | int work_done = 0; | |
1162 | ||
1163 | if (debug > 4) | |
1164 | printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry, | |
1165 | ep->rx_ring[entry].rxstatus); | |
1166 | ||
1167 | if (rx_work_limit > budget) | |
1168 | rx_work_limit = budget; | |
1169 | ||
1170 | /* If we own the next entry, it's a new packet. Send it up. */ | |
9ebfd492 AV |
1171 | while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) { |
1172 | int status = ep->rx_ring[entry].rxstatus; | |
1da177e4 LT |
1173 | |
1174 | if (debug > 4) | |
1175 | printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status); | |
1176 | if (--rx_work_limit < 0) | |
1177 | break; | |
1178 | if (status & 0x2006) { | |
1179 | if (debug > 2) | |
1180 | printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n", | |
1181 | dev->name, status); | |
1182 | if (status & 0x2000) { | |
1183 | printk(KERN_WARNING "%s: Oversized Ethernet frame spanned " | |
1184 | "multiple buffers, status %4.4x!\n", dev->name, status); | |
1185 | ep->stats.rx_length_errors++; | |
1186 | } else if (status & 0x0006) | |
1187 | /* Rx Frame errors are counted in hardware. */ | |
1188 | ep->stats.rx_errors++; | |
1189 | } else { | |
1190 | /* Malloc up new buffer, compatible with net-2e. */ | |
1191 | /* Omit the four octet CRC from the length. */ | |
1192 | short pkt_len = (status >> 16) - 4; | |
1193 | struct sk_buff *skb; | |
1194 | ||
1195 | if (pkt_len > PKT_BUF_SZ - 4) { | |
1196 | printk(KERN_ERR "%s: Oversized Ethernet frame, status %x " | |
1197 | "%d bytes.\n", | |
1198 | dev->name, status, pkt_len); | |
1199 | pkt_len = 1514; | |
1200 | } | |
1201 | /* Check if the packet is long enough to accept without copying | |
1202 | to a minimally-sized skbuff. */ | |
1203 | if (pkt_len < rx_copybreak | |
1204 | && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1205 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1206 | pci_dma_sync_single_for_cpu(ep->pci_dev, | |
1207 | ep->rx_ring[entry].bufaddr, | |
1208 | ep->rx_buf_sz, | |
1209 | PCI_DMA_FROMDEVICE); | |
8c7b7faa | 1210 | skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len); |
1da177e4 LT |
1211 | skb_put(skb, pkt_len); |
1212 | pci_dma_sync_single_for_device(ep->pci_dev, | |
1213 | ep->rx_ring[entry].bufaddr, | |
1214 | ep->rx_buf_sz, | |
1215 | PCI_DMA_FROMDEVICE); | |
1216 | } else { | |
f3b197ac JG |
1217 | pci_unmap_single(ep->pci_dev, |
1218 | ep->rx_ring[entry].bufaddr, | |
1da177e4 LT |
1219 | ep->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1220 | skb_put(skb = ep->rx_skbuff[entry], pkt_len); | |
1221 | ep->rx_skbuff[entry] = NULL; | |
1222 | } | |
1223 | skb->protocol = eth_type_trans(skb, dev); | |
1224 | netif_receive_skb(skb); | |
1da177e4 LT |
1225 | ep->stats.rx_packets++; |
1226 | ep->stats.rx_bytes += pkt_len; | |
1227 | } | |
1228 | work_done++; | |
1229 | entry = (++ep->cur_rx) % RX_RING_SIZE; | |
1230 | } | |
1231 | ||
1232 | /* Refill the Rx ring buffers. */ | |
1233 | for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) { | |
1234 | entry = ep->dirty_rx % RX_RING_SIZE; | |
1235 | if (ep->rx_skbuff[entry] == NULL) { | |
1236 | struct sk_buff *skb; | |
1237 | skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz); | |
1238 | if (skb == NULL) | |
1239 | break; | |
1da177e4 | 1240 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
f3b197ac | 1241 | ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, |
689be439 | 1242 | skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1243 | work_done++; |
1244 | } | |
9ebfd492 AV |
1245 | /* AV: shouldn't we add a barrier here? */ |
1246 | ep->rx_ring[entry].rxstatus = DescOwn; | |
1da177e4 LT |
1247 | } |
1248 | return work_done; | |
1249 | } | |
1250 | ||
1251 | static void epic_rx_err(struct net_device *dev, struct epic_private *ep) | |
1252 | { | |
1253 | long ioaddr = dev->base_addr; | |
1254 | int status; | |
1255 | ||
1256 | status = inl(ioaddr + INTSTAT); | |
1257 | ||
1258 | if (status == EpicRemoved) | |
1259 | return; | |
1260 | if (status & RxOverflow) /* Missed a Rx frame. */ | |
1261 | ep->stats.rx_errors++; | |
1262 | if (status & (RxOverflow | RxFull)) | |
1263 | outw(RxQueued, ioaddr + COMMAND); | |
1264 | } | |
1265 | ||
bea3348e | 1266 | static int epic_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1267 | { |
bea3348e SH |
1268 | struct epic_private *ep = container_of(napi, struct epic_private, napi); |
1269 | struct net_device *dev = ep->mii.dev; | |
1270 | int work_done = 0; | |
1da177e4 LT |
1271 | long ioaddr = dev->base_addr; |
1272 | ||
1da177e4 LT |
1273 | rx_action: |
1274 | ||
1275 | epic_tx(dev, ep); | |
1276 | ||
bea3348e | 1277 | work_done += epic_rx(dev, budget); |
1da177e4 LT |
1278 | |
1279 | epic_rx_err(dev, ep); | |
1280 | ||
4ec24119 | 1281 | if (work_done < budget) { |
1da177e4 LT |
1282 | unsigned long flags; |
1283 | int more; | |
1284 | ||
1285 | /* A bit baroque but it avoids a (space hungry) spin_unlock */ | |
1286 | ||
1287 | spin_lock_irqsave(&ep->napi_lock, flags); | |
1288 | ||
1289 | more = ep->reschedule_in_poll; | |
1290 | if (!more) { | |
bea3348e | 1291 | __netif_rx_complete(dev, napi); |
1da177e4 LT |
1292 | outl(EpicNapiEvent, ioaddr + INTSTAT); |
1293 | epic_napi_irq_on(dev, ep); | |
1294 | } else | |
1295 | ep->reschedule_in_poll--; | |
1296 | ||
1297 | spin_unlock_irqrestore(&ep->napi_lock, flags); | |
1298 | ||
1299 | if (more) | |
1300 | goto rx_action; | |
1301 | } | |
1302 | ||
bea3348e | 1303 | return work_done; |
1da177e4 LT |
1304 | } |
1305 | ||
1306 | static int epic_close(struct net_device *dev) | |
1307 | { | |
1308 | long ioaddr = dev->base_addr; | |
4cf1653a | 1309 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1310 | struct sk_buff *skb; |
1311 | int i; | |
1312 | ||
1313 | netif_stop_queue(dev); | |
bea3348e | 1314 | napi_disable(&ep->napi); |
1da177e4 LT |
1315 | |
1316 | if (debug > 1) | |
1317 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | |
1318 | dev->name, (int)inl(ioaddr + INTSTAT)); | |
1319 | ||
1320 | del_timer_sync(&ep->timer); | |
1321 | ||
1322 | epic_disable_int(dev, ep); | |
1323 | ||
1324 | free_irq(dev->irq, dev); | |
1325 | ||
1326 | epic_pause(dev); | |
1327 | ||
1328 | /* Free all the skbuffs in the Rx queue. */ | |
1329 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1330 | skb = ep->rx_skbuff[i]; | |
1331 | ep->rx_skbuff[i] = NULL; | |
1332 | ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */ | |
1333 | ep->rx_ring[i].buflength = 0; | |
1334 | if (skb) { | |
f3b197ac | 1335 | pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr, |
1da177e4 LT |
1336 | ep->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1337 | dev_kfree_skb(skb); | |
1338 | } | |
1339 | ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */ | |
1340 | } | |
1341 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1342 | skb = ep->tx_skbuff[i]; | |
1343 | ep->tx_skbuff[i] = NULL; | |
1344 | if (!skb) | |
1345 | continue; | |
f3b197ac | 1346 | pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr, |
1da177e4 LT |
1347 | skb->len, PCI_DMA_TODEVICE); |
1348 | dev_kfree_skb(skb); | |
1349 | } | |
1350 | ||
1351 | /* Green! Leave the chip in low-power mode. */ | |
1352 | outl(0x0008, ioaddr + GENCTL); | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | static struct net_device_stats *epic_get_stats(struct net_device *dev) | |
1358 | { | |
4cf1653a | 1359 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1360 | long ioaddr = dev->base_addr; |
1361 | ||
1362 | if (netif_running(dev)) { | |
1363 | /* Update the error counts. */ | |
1364 | ep->stats.rx_missed_errors += inb(ioaddr + MPCNT); | |
1365 | ep->stats.rx_frame_errors += inb(ioaddr + ALICNT); | |
1366 | ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT); | |
1367 | } | |
1368 | ||
1369 | return &ep->stats; | |
1370 | } | |
1371 | ||
1372 | /* Set or clear the multicast filter for this adaptor. | |
1373 | Note that we only use exclusion around actually queueing the | |
1374 | new frame, not around filling ep->setup_frame. This is non-deterministic | |
1375 | when re-entered but still correct. */ | |
1376 | ||
1377 | static void set_rx_mode(struct net_device *dev) | |
1378 | { | |
1379 | long ioaddr = dev->base_addr; | |
4cf1653a | 1380 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1381 | unsigned char mc_filter[8]; /* Multicast hash filter */ |
1382 | int i; | |
1383 | ||
1384 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1385 | outl(0x002C, ioaddr + RxCtrl); | |
1386 | /* Unconditionally log net taps. */ | |
1da177e4 LT |
1387 | memset(mc_filter, 0xff, sizeof(mc_filter)); |
1388 | } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) { | |
1389 | /* There is apparently a chip bug, so the multicast filter | |
1390 | is never enabled. */ | |
1391 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1392 | memset(mc_filter, 0xff, sizeof(mc_filter)); | |
1393 | outl(0x000C, ioaddr + RxCtrl); | |
1394 | } else if (dev->mc_count == 0) { | |
1395 | outl(0x0004, ioaddr + RxCtrl); | |
1396 | return; | |
1397 | } else { /* Never executed, for now. */ | |
1398 | struct dev_mc_list *mclist; | |
1399 | ||
1400 | memset(mc_filter, 0, sizeof(mc_filter)); | |
1401 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1402 | i++, mclist = mclist->next) { | |
1403 | unsigned int bit_nr = | |
1404 | ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f; | |
1405 | mc_filter[bit_nr >> 3] |= (1 << bit_nr); | |
1406 | } | |
1407 | } | |
1408 | /* ToDo: perhaps we need to stop the Tx and Rx process here? */ | |
1409 | if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) { | |
1410 | for (i = 0; i < 4; i++) | |
1411 | outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4); | |
1412 | memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter)); | |
1413 | } | |
1414 | return; | |
1415 | } | |
1416 | ||
1417 | static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) | |
1418 | { | |
4cf1653a | 1419 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1420 | |
1421 | strcpy (info->driver, DRV_NAME); | |
1422 | strcpy (info->version, DRV_VERSION); | |
1423 | strcpy (info->bus_info, pci_name(np->pci_dev)); | |
1424 | } | |
1425 | ||
1426 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1427 | { | |
4cf1653a | 1428 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1429 | int rc; |
1430 | ||
1431 | spin_lock_irq(&np->lock); | |
1432 | rc = mii_ethtool_gset(&np->mii, cmd); | |
1433 | spin_unlock_irq(&np->lock); | |
1434 | ||
1435 | return rc; | |
1436 | } | |
1437 | ||
1438 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1439 | { | |
4cf1653a | 1440 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1441 | int rc; |
1442 | ||
1443 | spin_lock_irq(&np->lock); | |
1444 | rc = mii_ethtool_sset(&np->mii, cmd); | |
1445 | spin_unlock_irq(&np->lock); | |
1446 | ||
1447 | return rc; | |
1448 | } | |
1449 | ||
1450 | static int netdev_nway_reset(struct net_device *dev) | |
1451 | { | |
4cf1653a | 1452 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1453 | return mii_nway_restart(&np->mii); |
1454 | } | |
1455 | ||
1456 | static u32 netdev_get_link(struct net_device *dev) | |
1457 | { | |
4cf1653a | 1458 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1459 | return mii_link_ok(&np->mii); |
1460 | } | |
1461 | ||
1462 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1463 | { | |
1464 | return debug; | |
1465 | } | |
1466 | ||
1467 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1468 | { | |
1469 | debug = value; | |
1470 | } | |
1471 | ||
1472 | static int ethtool_begin(struct net_device *dev) | |
1473 | { | |
1474 | unsigned long ioaddr = dev->base_addr; | |
1475 | /* power-up, if interface is down */ | |
1476 | if (! netif_running(dev)) { | |
1477 | outl(0x0200, ioaddr + GENCTL); | |
1478 | outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL); | |
1479 | } | |
1480 | return 0; | |
1481 | } | |
1482 | ||
1483 | static void ethtool_complete(struct net_device *dev) | |
1484 | { | |
1485 | unsigned long ioaddr = dev->base_addr; | |
1486 | /* power-down, if interface is down */ | |
1487 | if (! netif_running(dev)) { | |
1488 | outl(0x0008, ioaddr + GENCTL); | |
1489 | outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL); | |
1490 | } | |
1491 | } | |
1492 | ||
7282d491 | 1493 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
1494 | .get_drvinfo = netdev_get_drvinfo, |
1495 | .get_settings = netdev_get_settings, | |
1496 | .set_settings = netdev_set_settings, | |
1497 | .nway_reset = netdev_nway_reset, | |
1498 | .get_link = netdev_get_link, | |
1499 | .get_msglevel = netdev_get_msglevel, | |
1500 | .set_msglevel = netdev_set_msglevel, | |
1da177e4 LT |
1501 | .begin = ethtool_begin, |
1502 | .complete = ethtool_complete | |
1503 | }; | |
1504 | ||
1505 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1506 | { | |
4cf1653a | 1507 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1508 | long ioaddr = dev->base_addr; |
1509 | struct mii_ioctl_data *data = if_mii(rq); | |
1510 | int rc; | |
1511 | ||
1512 | /* power-up, if interface is down */ | |
1513 | if (! netif_running(dev)) { | |
1514 | outl(0x0200, ioaddr + GENCTL); | |
1515 | outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL); | |
1516 | } | |
1517 | ||
1518 | /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */ | |
1519 | spin_lock_irq(&np->lock); | |
1520 | rc = generic_mii_ioctl(&np->mii, data, cmd, NULL); | |
1521 | spin_unlock_irq(&np->lock); | |
1522 | ||
1523 | /* power-down, if interface is down */ | |
1524 | if (! netif_running(dev)) { | |
1525 | outl(0x0008, ioaddr + GENCTL); | |
1526 | outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL); | |
1527 | } | |
1528 | return rc; | |
1529 | } | |
1530 | ||
1531 | ||
1532 | static void __devexit epic_remove_one (struct pci_dev *pdev) | |
1533 | { | |
1534 | struct net_device *dev = pci_get_drvdata(pdev); | |
4cf1653a | 1535 | struct epic_private *ep = netdev_priv(dev); |
f3b197ac | 1536 | |
1da177e4 LT |
1537 | pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma); |
1538 | pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma); | |
1539 | unregister_netdev(dev); | |
1540 | #ifndef USE_IO_OPS | |
1541 | iounmap((void*) dev->base_addr); | |
1542 | #endif | |
1543 | pci_release_regions(pdev); | |
1544 | free_netdev(dev); | |
1545 | pci_disable_device(pdev); | |
1546 | pci_set_drvdata(pdev, NULL); | |
1547 | /* pci_power_off(pdev, -1); */ | |
1548 | } | |
1549 | ||
1550 | ||
1551 | #ifdef CONFIG_PM | |
1552 | ||
1553 | static int epic_suspend (struct pci_dev *pdev, pm_message_t state) | |
1554 | { | |
1555 | struct net_device *dev = pci_get_drvdata(pdev); | |
1556 | long ioaddr = dev->base_addr; | |
1557 | ||
1558 | if (!netif_running(dev)) | |
1559 | return 0; | |
1560 | epic_pause(dev); | |
1561 | /* Put the chip into low-power mode. */ | |
1562 | outl(0x0008, ioaddr + GENCTL); | |
1563 | /* pci_power_off(pdev, -1); */ | |
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | ||
1568 | static int epic_resume (struct pci_dev *pdev) | |
1569 | { | |
1570 | struct net_device *dev = pci_get_drvdata(pdev); | |
1571 | ||
1572 | if (!netif_running(dev)) | |
1573 | return 0; | |
1574 | epic_restart(dev); | |
1575 | /* pci_power_on(pdev); */ | |
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | #endif /* CONFIG_PM */ | |
1580 | ||
1581 | ||
1582 | static struct pci_driver epic_driver = { | |
1583 | .name = DRV_NAME, | |
1584 | .id_table = epic_pci_tbl, | |
1585 | .probe = epic_init_one, | |
1586 | .remove = __devexit_p(epic_remove_one), | |
1587 | #ifdef CONFIG_PM | |
1588 | .suspend = epic_suspend, | |
1589 | .resume = epic_resume, | |
1590 | #endif /* CONFIG_PM */ | |
1591 | }; | |
1592 | ||
1593 | ||
1594 | static int __init epic_init (void) | |
1595 | { | |
1596 | /* when a module, this is printed whether or not devices are found in probe */ | |
1597 | #ifdef MODULE | |
2c2a8c53 MD |
1598 | printk (KERN_INFO "%s" KERN_INFO "%s", |
1599 | version, version2); | |
1da177e4 LT |
1600 | #endif |
1601 | ||
29917620 | 1602 | return pci_register_driver(&epic_driver); |
1da177e4 LT |
1603 | } |
1604 | ||
1605 | ||
1606 | static void __exit epic_cleanup (void) | |
1607 | { | |
1608 | pci_unregister_driver (&epic_driver); | |
1609 | } | |
1610 | ||
1611 | ||
1612 | module_init(epic_init); | |
1613 | module_exit(epic_cleanup); |