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ThunderLAN: remove is_eisa flag
[deliverable/linux.git] / drivers / net / ethernet / 3com / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
3f6db0f3 105static const char version[] =
86de79b6 106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
3f6db0f3 280} vortex_info_tbl[] = {
1da177e4 281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
1da177e4
LT		 438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
cc2d6596
AV		 544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
cc2d6596
AV		 564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 566#if DO_ZEROCOPY
567 struct {
cc2d6596
AV		 568 __le32 addr;
569 __le32 length;
1da177e4
LT		 570 } frag[1+MAX_SKB_FRAGS];
571#else
cc2d6596
AV		 572 __le32 addr;
573 __le32 length;
1da177e4
LT		 574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
8d1d0340
SK		 588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
1da177e4
LT		 593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
62afe595
JL		 612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 625 full_duplex:1, autoselect:1,
1da177e4
LT		 626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
aa25ab7d
NH		 635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
84176b7b
DK		 637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
639 */
1da177e4
LT		 640 int drv_flags;
641 u16 status_enable;
642 u16 intr_enable;
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
de847272
BH		 650
651 /* Serialises access to hardware other than MII and variables below.
24cd804d 652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
de847272
BH		 653 spinlock_t lock;
654
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
1da177e4
LT		 659};
660
a095cfc4
BH		 661static void window_set(struct vortex_private *vp, int window)
662{
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
665 vp->window = window;
666 }
667}
668
669#define DEFINE_WINDOW_IO(size) \
670static u ## size \
671window_read ## size(struct vortex_private *vp, int window, int addr) \
672{ \
de847272
BH		 673 unsigned long flags; \
674 u ## size ret; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4 676 window_set(vp, window); \
de847272
BH		 677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
679 return ret; \
a095cfc4
BH		 680} \
681static void \
682window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
684{ \
de847272
BH		 685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4
BH		 687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
de847272 689 spin_unlock_irqrestore(&vp->window_lock, flags); \
a095cfc4
BH		 690}
691DEFINE_WINDOW_IO(8)
692DEFINE_WINDOW_IO(16)
693DEFINE_WINDOW_IO(32)
694
1da177e4
LT		 695#ifdef CONFIG_PCI
696#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
697#else
698#define DEVICE_PCI(dev) NULL
699#endif
700
d530db0d
NK		 701#define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
1da177e4
LT		 703
704#ifdef CONFIG_EISA
705#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
706#else
707#define DEVICE_EISA(dev) NULL
708#endif
709
d530db0d
NK		 710#define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
1da177e4
LT		 712
713/* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
715 */
716enum xcvr_types {
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
719};
720
f71e1309 721static const struct media_table {
1da177e4
LT		 722 char *name;
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
727} media_tbl[] = {
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
739};
740
741static struct {
742 const char str[ETH_GSTRING_LEN];
743} ethtool_stats_keys[] = {
744 { "tx_deferred" },
8d1d0340 745 { "tx_max_collisions" },
1da177e4 746 { "tx_multiple_collisions" },
8d1d0340 747 { "tx_single_collisions" },
1da177e4
LT		 748 { "rx_bad_ssd" },
749};
750
751/* number of ETHTOOL_GSTATS u64's */
8d1d0340 752#define VORTEX_NUM_STATS 5
1da177e4 753
62afe595 754static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 755 int chip_idx, int card_idx);
c8303d10 756static int vortex_up(struct net_device *dev);
1da177e4
LT		 757static void vortex_down(struct net_device *dev, int final);
758static int vortex_open(struct net_device *dev);
a095cfc4 759static void mdio_sync(struct vortex_private *vp, int bits);
1da177e4
LT		 760static int mdio_read(struct net_device *dev, int phy_id, int location);
761static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762static void vortex_timer(unsigned long arg);
763static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 764static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
1da177e4
LT		 768static int vortex_rx(struct net_device *dev);
769static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 770static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 772static int vortex_close(struct net_device *dev);
773static void dump_tx_ring(struct net_device *dev);
62afe595 774static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 775static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776static void set_rx_mode(struct net_device *dev);
777#ifdef CONFIG_PCI
778static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
779#endif
780static void vortex_tx_timeout(struct net_device *dev);
781static void acpi_set_WOL(struct net_device *dev);
7282d491 782static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 783static void set_8021q_mode(struct net_device *dev, int enable);
784
1da177e4
LT		 785/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786/* Option count limit only -- unlimited interfaces are supported. */
787#define MAX_UNITS 8
9954ab7f
JL		 788static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 793static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 794static int global_options = -1;
795static int global_full_duplex = -1;
796static int global_enable_wol = -1;
900fd17d 797static int global_use_mmio = -1;
1da177e4 798
1da177e4
LT		 799/* Variables to work-around the Compaq PCI BIOS32 problem. */
800static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801static struct net_device *compaq_net_device;
802
803static int vortex_cards_found;
804
805module_param(debug, int, 0);
806module_param(global_options, int, 0);
807module_param_array(options, int, NULL, 0);
808module_param(global_full_duplex, int, 0);
809module_param_array(full_duplex, int, NULL, 0);
810module_param_array(hw_checksums, int, NULL, 0);
811module_param_array(flow_ctrl, int, NULL, 0);
812module_param(global_enable_wol, int, 0);
813module_param_array(enable_wol, int, NULL, 0);
814module_param(rx_copybreak, int, 0);
815module_param(max_interrupt_work, int, 0);
816module_param(compaq_ioaddr, int, 0);
817module_param(compaq_irq, int, 0);
818module_param(compaq_device_id, int, 0);
819module_param(watchdog, int, 0);
900fd17d
JL		 820module_param(global_use_mmio, int, 0);
821module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 822MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 826MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 827MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 830MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 831MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 837MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 839
840#ifdef CONFIG_NET_POLL_CONTROLLER
841static void poll_vortex(struct net_device *dev)
842{
843 struct vortex_private *vp = netdev_priv(dev);
844 unsigned long flags;
0d38ff1d 845 local_irq_save(flags);
7d12e780 846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 847 local_irq_restore(flags);
6aa20a22 848}
1da177e4
LT		 849#endif
850
851#ifdef CONFIG_PM
852
7bfc4ab5 853static int vortex_suspend(struct device *dev)
1da177e4 854{
7bfc4ab5
AV		 855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
857
858 if (!ndev || !netif_running(ndev))
859 return 0;
860
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
1da177e4 863
1da177e4
LT		 864 return 0;
865}
866
7bfc4ab5 867static int vortex_resume(struct device *dev)
1da177e4 868{
7bfc4ab5
AV		 869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 871 int err;
1da177e4 872
7bfc4ab5
AV		 873 if (!ndev || !netif_running(ndev))
874 return 0;
875
876 err = vortex_up(ndev);
877 if (err)
878 return err;
879
880 netif_device_attach(ndev);
881
1da177e4
LT		 882 return 0;
883}
884
47145210 885static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
892};
893
894#define VORTEX_PM_OPS (&vortex_pm_ops)
895
896#else /* !CONFIG_PM */
897
898#define VORTEX_PM_OPS NULL
899
900#endif /* !CONFIG_PM */
1da177e4
LT		 901
902#ifdef CONFIG_EISA
948252cb 903static struct eisa_device_id vortex_eisa_ids[] = {
1da177e4
LT		 904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
906 { "" }
907};
07563c71 908MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 909
948252cb 910static int __init vortex_eisa_probe(struct device *device)
1da177e4 911{
62afe595 912 void __iomem *ioaddr;
1da177e4
LT		 913 struct eisa_device *edev;
914
a880c4cd 915 edev = to_eisa_device(device);
1da177e4 916
62afe595 917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 918 return -EBUSY;
919
62afe595
JL		 920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
921
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 923 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 925 return -ENODEV;
926 }
927
928 vortex_cards_found++;
929
930 return 0;
931}
932
3f6db0f3 933static int vortex_eisa_remove(struct device *device)
1da177e4
LT		 934{
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
62afe595 938 void __iomem *ioaddr;
1da177e4 939
a880c4cd
SK		 940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
1da177e4
LT		 942
943 if (!dev) {
39738e16 944 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 945 BUG();
946 }
947
948 vp = netdev_priv(dev);
62afe595 949 ioaddr = vp->ioaddr;
6aa20a22 950
a880c4cd
SK		 951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
c81400be 953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 954
a880c4cd 955 free_netdev(dev);
1da177e4
LT		 956 return 0;
957}
95c408a9
RB		 958
959static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
961 .driver = {
962 .name = "3c59x",
963 .probe = vortex_eisa_probe,
3f6db0f3 964 .remove = vortex_eisa_remove
95c408a9
RB		 965 }
966};
967
968#endif /* CONFIG_EISA */
1da177e4
LT		 969
970/* returns count found (>= 0), or negative on error */
a880c4cd 971static int __init vortex_eisa_init(void)
1da177e4
LT		 972{
973 int eisa_found = 0;
974 int orig_cards_found = vortex_cards_found;
975
976#ifdef CONFIG_EISA
c2f6fabb
BH		 977 int err;
978
979 err = eisa_driver_register (&vortex_eisa_driver);
980 if (!err) {
981 /*
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
25985edc 986 * found, and let the sysfs magic happened...
c2f6fabb
BH		 987 */
988 eisa_found = 1;
1da177e4
LT		 989 }
990#endif
6aa20a22 991
1da177e4
LT		 992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
993 if (compaq_ioaddr) {
62afe595
JL		 994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 996 }
997
998 return vortex_cards_found - orig_cards_found + eisa_found;
999}
1000
1001/* returns count (>= 0), or negative on error */
3f6db0f3 1002static int vortex_init_one(struct pci_dev *pdev,
1dd06ae8 1003 const struct pci_device_id *ent)
1da177e4 1004{
900fd17d
JL		 1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1da177e4 1008
6aa20a22 1009 /* wake up and enable device */
a880c4cd 1010 rc = pci_enable_device(pdev);
1da177e4
LT		 1011 if (rc < 0)
1012 goto out;
1013
4b264a16
SS		 1014 rc = pci_request_regions(pdev, DRV_NAME);
1015 if (rc < 0) {
1016 pci_disable_device(pdev);
1017 goto out;
1018 }
1019
900fd17d
JL		 1020 unit = vortex_cards_found;
1021
1022 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1023 /* Determine the default if the user didn't override us */
1024 vci = &vortex_info_tbl[ent->driver_data];
1025 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1026 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1027 pci_bar = use_mmio[unit] ? 1 : 0;
1028 else
1029 pci_bar = global_use_mmio ? 1 : 0;
1030
1031 ioaddr = pci_iomap(pdev, pci_bar, 0);
1032 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1033 ioaddr = pci_iomap(pdev, 0, 0);
8cd47ea1 1034 if (!ioaddr) {
4b264a16 1035 pci_release_regions(pdev);
8cd47ea1
KV		 1036 pci_disable_device(pdev);
1037 rc = -ENOMEM;
1038 goto out;
1039 }
900fd17d
JL		 1040
1041 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1042 ent->driver_data, unit);
1da177e4 1043 if (rc < 0) {
f89f5d0e 1044 pci_iounmap(pdev, ioaddr);
4b264a16 1045 pci_release_regions(pdev);
a880c4cd 1046 pci_disable_device(pdev);
1da177e4
LT		 1047 goto out;
1048 }
1049
1050 vortex_cards_found++;
1051
1052out:
1053 return rc;
1054}
1055
48b47a5e
SH		 1056static const struct net_device_ops boomrang_netdev_ops = {
1057 .ndo_open = vortex_open,
1058 .ndo_stop = vortex_close,
1059 .ndo_start_xmit = boomerang_start_xmit,
1060 .ndo_tx_timeout = vortex_tx_timeout,
1061 .ndo_get_stats = vortex_get_stats,
1062#ifdef CONFIG_PCI
1063 .ndo_do_ioctl = vortex_ioctl,
1064#endif
afc4b13d 1065 .ndo_set_rx_mode = set_rx_mode,
48b47a5e
SH		 1066 .ndo_change_mtu = eth_change_mtu,
1067 .ndo_set_mac_address = eth_mac_addr,
1068 .ndo_validate_addr = eth_validate_addr,
1069#ifdef CONFIG_NET_POLL_CONTROLLER
1070 .ndo_poll_controller = poll_vortex,
1071#endif
1072};
1073
1074static const struct net_device_ops vortex_netdev_ops = {
1075 .ndo_open = vortex_open,
1076 .ndo_stop = vortex_close,
1077 .ndo_start_xmit = vortex_start_xmit,
1078 .ndo_tx_timeout = vortex_tx_timeout,
1079 .ndo_get_stats = vortex_get_stats,
1080#ifdef CONFIG_PCI
1081 .ndo_do_ioctl = vortex_ioctl,
1082#endif
afc4b13d 1083 .ndo_set_rx_mode = set_rx_mode,
48b47a5e
SH		 1084 .ndo_change_mtu = eth_change_mtu,
1085 .ndo_set_mac_address = eth_mac_addr,
1086 .ndo_validate_addr = eth_validate_addr,
1087#ifdef CONFIG_NET_POLL_CONTROLLER
1088 .ndo_poll_controller = poll_vortex,
1089#endif
1090};
1091
1da177e4
LT		 1092/*
1093 * Start up the PCI/EISA device which is described by *gendev.
1094 * Return 0 on success.
1095 *
1096 * NOTE: pdev can be NULL, for the case of a Compaq device
1097 */
1dd06ae8
GKH		 1098static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1099 int chip_idx, int card_idx)
1da177e4
LT		 1100{
1101 struct vortex_private *vp;
1102 int option;
1103 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1104 int i, step;
1105 struct net_device *dev;
1106 static int printed_version;
1107 int retval, print_info;
1108 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1109 const char *print_name = "3c59x";
1da177e4
LT		 1110 struct pci_dev *pdev = NULL;
1111 struct eisa_device *edev = NULL;
1112
1113 if (!printed_version) {
39738e16 1114 pr_info("%s", version);
1da177e4
LT		 1115 printed_version = 1;
1116 }
1117
1118 if (gendev) {
1119 if ((pdev = DEVICE_PCI(gendev))) {
1120 print_name = pci_name(pdev);
1121 }
1122
1123 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1124 print_name = dev_name(&edev->dev);
1da177e4
LT		 1125 }
1126 }
1127
1128 dev = alloc_etherdev(sizeof(*vp));
1129 retval = -ENOMEM;
41de8d4c 1130 if (!dev)
1da177e4 1131 goto out;
41de8d4c 1132
1da177e4
LT		 1133 SET_NETDEV_DEV(dev, gendev);
1134 vp = netdev_priv(dev);
1135
1136 option = global_options;
1137
1138 /* The lower four bits are the media type. */
1139 if (dev->mem_start) {
1140 /*
1141 * The 'options' param is passed in as the third arg to the
1142 * LILO 'ether=' argument for non-modular use
1143 */
1144 option = dev->mem_start;
1145 }
1146 else if (card_idx < MAX_UNITS) {
1147 if (options[card_idx] >= 0)
1148 option = options[card_idx];
1149 }
1150
1151 if (option > 0) {
1152 if (option & 0x8000)
1153 vortex_debug = 7;
1154 if (option & 0x4000)
1155 vortex_debug = 2;
1156 if (option & 0x0400)
1157 vp->enable_wol = 1;
1158 }
1159
1160 print_info = (vortex_debug > 1);
1161 if (print_info)
39738e16 1162 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1163
39738e16 1164 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1165 print_name,
1166 pdev ? "PCI" : "EISA",
1167 vci->name,
1168 ioaddr);
1169
62afe595 1170 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1171 dev->irq = irq;
1172 dev->mtu = mtu;
62afe595 1173 vp->ioaddr = ioaddr;
1da177e4
LT		 1174 vp->large_frames = mtu > 1500;
1175 vp->drv_flags = vci->drv_flags;
1176 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1177 vp->io_size = vci->io_size;
1178 vp->card_idx = card_idx;
a095cfc4 1179 vp->window = -1;
1da177e4
LT		 1180
1181 /* module list only for Compaq device */
1182 if (gendev == NULL) {
1183 compaq_net_device = dev;
1184 }
1185
1186 /* PCI-only startup logic */
1187 if (pdev) {
6aa20a22 1188 /* enable bus-mastering if necessary */
1da177e4 1189 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1190 pci_set_master(pdev);
1da177e4
LT		 1191
1192 if (vci->drv_flags & IS_VORTEX) {
1193 u8 pci_latency;
1194 u8 new_latency = 248;
1195
1196 /* Check the PCI latency value. On the 3c590 series the latency timer
1197 must be set to the maximum value to avoid data corruption that occurs
1198 when the timer expires during a transfer. This bug exists the Vortex
1199 chip only. */
1200 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1201 if (pci_latency < new_latency) {
39738e16 1202 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1203 print_name, pci_latency, new_latency);
39738e16 1204 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1205 }
1206 }
1207 }
1208
1209 spin_lock_init(&vp->lock);
de847272
BH		 1210 spin_lock_init(&vp->mii_lock);
1211 spin_lock_init(&vp->window_lock);
1da177e4
LT		 1212 vp->gendev = gendev;
1213 vp->mii.dev = dev;
1214 vp->mii.mdio_read = mdio_read;
1215 vp->mii.mdio_write = mdio_write;
1216 vp->mii.phy_id_mask = 0x1f;
1217 vp->mii.reg_num_mask = 0x1f;
1218
1219 /* Makes sure rings are at least 16 byte aligned. */
1220 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1221 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1222 &vp->rx_ring_dma);
1223 retval = -ENOMEM;
cc2d6596 1224 if (!vp->rx_ring)
4b264a16 1225 goto free_device;
1da177e4
LT		 1226
1227 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1228 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1229
1230 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1231 * instead of a module list */
1da177e4
LT		 1232 if (pdev)
1233 pci_set_drvdata(pdev, dev);
1234 if (edev)
a880c4cd 1235 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1236
1237 vp->media_override = 7;
1238 if (option >= 0) {
1239 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1240 if (vp->media_override != 7)
1241 vp->medialock = 1;
1242 vp->full_duplex = (option & 0x200) ? 1 : 0;
1243 vp->bus_master = (option & 16) ? 1 : 0;
1244 }
1245
1246 if (global_full_duplex > 0)
1247 vp->full_duplex = 1;
1248 if (global_enable_wol > 0)
1249 vp->enable_wol = 1;
1250
1251 if (card_idx < MAX_UNITS) {
1252 if (full_duplex[card_idx] > 0)
1253 vp->full_duplex = 1;
1254 if (flow_ctrl[card_idx] > 0)
1255 vp->flow_ctrl = 1;
1256 if (enable_wol[card_idx] > 0)
1257 vp->enable_wol = 1;
1258 }
1259
125d5ce8 1260 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1261 vp->options = option;
1262 /* Read the station address from the EEPROM. */
1da177e4
LT		 1263 {
1264 int base;
1265
1266 if (vci->drv_flags & EEPROM_8BIT)
1267 base = 0x230;
1268 else if (vci->drv_flags & EEPROM_OFFSET)
1269 base = EEPROM_Read + 0x30;
1270 else
1271 base = EEPROM_Read;
1272
1273 for (i = 0; i < 0x40; i++) {
1274 int timer;
a095cfc4 1275 window_write16(vp, base + i, 0, Wn0EepromCmd);
1da177e4
LT		 1276 /* Pause for at least 162 us. for the read to take place. */
1277 for (timer = 10; timer >= 0; timer--) {
1278 udelay(162);
a095cfc4
BH		 1279 if ((window_read16(vp, 0, Wn0EepromCmd) &
1280 0x8000) == 0)
1da177e4
LT		 1281 break;
1282 }
a095cfc4 1283 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1da177e4
LT		 1284 }
1285 }
1286 for (i = 0; i < 0x18; i++)
1287 checksum ^= eeprom[i];
1288 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1289 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1290 while (i < 0x21)
1291 checksum ^= eeprom[i++];
1292 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1293 }
1294 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1295 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1296 for (i = 0; i < 3; i++)
cc2d6596 1297 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
0795af57 1298 if (print_info)
39738e16 1299 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1300 /* Unfortunately an all zero eeprom passes the checksum and this
1301 gets found in the wild in failure cases. Crypto is hard 8) */
1302 if (!is_valid_ether_addr(dev->dev_addr)) {
1303 retval = -EINVAL;
39738e16 1304 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1305 goto free_ring; /* With every pack */
1306 }
1da177e4 1307 for (i = 0; i < 6; i++)
a095cfc4 1308 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1309
1da177e4 1310 if (print_info)
39738e16 1311 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1312 /* Tell them about an invalid IRQ. */
60e4ad7a 1313 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1314 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1315 dev->irq);
1da177e4 1316
a095cfc4 1317 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1318 if (print_info) {
39738e16
AB		 1319 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1320 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1321 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1322 }
1323
1324
1325 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1326 unsigned short n;
1327
62afe595
JL		 1328 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1329 if (!vp->cb_fn_base) {
1da177e4 1330 retval = -ENOMEM;
62afe595 1331 goto free_ring;
1da177e4 1332 }
62afe595 1333
1da177e4 1334 if (print_info) {
39738e16 1335 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1336 print_name,
1337 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1338 vp->cb_fn_base);
1da177e4 1339 }
1da177e4 1340
a095cfc4 1341 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1342 if (vp->drv_flags & INVERT_LED_PWR)
1343 n |= 0x10;
1344 if (vp->drv_flags & INVERT_MII_PWR)
1345 n |= 0x4000;
a095cfc4 1346 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4 1347 if (vp->drv_flags & WNO_XCVR_PWR) {
a095cfc4 1348 window_write16(vp, 0x0800, 0, 0);
1da177e4
LT		 1349 }
1350 }
1351
1352 /* Extract our information from the EEPROM data. */
1353 vp->info1 = eeprom[13];
1354 vp->info2 = eeprom[15];
1355 vp->capabilities = eeprom[16];
1356
1357 if (vp->info1 & 0x8000) {
1358 vp->full_duplex = 1;
1359 if (print_info)
39738e16 1360 pr_info("Full duplex capable\n");
1da177e4
LT		 1361 }
1362
1363 {
f71e1309 1364 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4 1365 unsigned int config;
a095cfc4 1366 vp->available_media = window_read16(vp, 3, Wn3_Options);
1da177e4
LT		 1367 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1368 vp->available_media = 0x40;
a095cfc4 1369 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1370 if (print_info) {
39738e16 1371 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
a095cfc4 1372 config, window_read16(vp, 3, Wn3_Options));
39738e16 1373 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1374 8 << RAM_SIZE(config),
1375 RAM_WIDTH(config) ? "word" : "byte",
1376 ram_split[RAM_SPLIT(config)],
1377 AUTOSELECT(config) ? "autoselect/" : "",
1378 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1379 media_tbl[XCVR(config)].name);
1380 }
1381 vp->default_media = XCVR(config);
1382 if (vp->default_media == XCVR_NWAY)
1383 vp->has_nway = 1;
1384 vp->autoselect = AUTOSELECT(config);
1385 }
1386
1387 if (vp->media_override != 7) {
39738e16 1388 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1389 print_name, vp->media_override,
1390 media_tbl[vp->media_override].name);
1391 dev->if_port = vp->media_override;
1392 } else
1393 dev->if_port = vp->default_media;
1394
1395 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1396 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1397 int phy, phy_idx = 0;
1da177e4
LT		 1398 mii_preamble_required++;
1399 if (vp->drv_flags & EXTRA_PREAMBLE)
1400 mii_preamble_required++;
344e0f62 1401 mdio_sync(vp, 32);
106427e6 1402 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1403 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1404 int mii_status, phyx;
1405
1406 /*
1407 * For the 3c905CX we look at index 24 first, because it bogusly
1408 * reports an external PHY at all indices
1409 */
1410 if (phy == 0)
1411 phyx = 24;
1412 else if (phy <= 24)
1413 phyx = phy - 1;
1414 else
1415 phyx = phy;
106427e6 1416 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1417 if (mii_status && mii_status != 0xffff) {
1418 vp->phys[phy_idx++] = phyx;
1419 if (print_info) {
39738e16
AB		 1420 pr_info(" MII transceiver found at address %d, status %4x.\n",
1421 phyx, mii_status);
1da177e4
LT		 1422 }
1423 if ((mii_status & 0x0040) == 0)
1424 mii_preamble_required++;
1425 }
1426 }
1427 mii_preamble_required--;
1428 if (phy_idx == 0) {
39738e16 1429 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1430 vp->phys[0] = 24;
1431 } else {
106427e6 1432 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1433 if (vp->full_duplex) {
1434 /* Only advertise the FD media types. */
1435 vp->advertising &= ~0x02A0;
1436 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1437 }
1438 }
1439 vp->mii.phy_id = vp->phys[0];
1440 }
1441
1442 if (vp->capabilities & CapBusMaster) {
1443 vp->full_bus_master_tx = 1;
1444 if (print_info) {
39738e16 1445 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1446 (vp->info2 & 1) ? "early" : "whole-frame" );
1447 }
1448 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1449 vp->bus_master = 0; /* AKPM: vortex only */
1450 }
1451
1452 /* The 3c59x-specific entries in the device structure. */
1da177e4 1453 if (vp->full_bus_master_tx) {
48b47a5e 1454 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1455 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1456 if (card_idx < MAX_UNITS &&
1457 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1458 hw_checksums[card_idx] == 1)) {
d311b0d3 1459 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1460 }
48b47a5e
SH		 1461 } else
1462 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1463
1464 if (print_info) {
39738e16 1465 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1466 print_name,
1467 (dev->features & NETIF_F_SG) ? "en":"dis",
1468 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1469 }
1470
1da177e4 1471 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1472 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1473
1da177e4
LT		 1474 if (pdev) {
1475 vp->pm_state_valid = 1;
1476 pci_save_state(VORTEX_PCI(vp));
1477 acpi_set_WOL(dev);
1478 }
1479 retval = register_netdev(dev);
1480 if (retval == 0)
1481 return 0;
1482
1483free_ring:
1484 pci_free_consistent(pdev,
1485 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1486 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1487 vp->rx_ring,
1488 vp->rx_ring_dma);
4b264a16 1489free_device:
1da177e4 1490 free_netdev(dev);
39738e16 1491 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1492out:
1493 return retval;
1494}
1495
1496static void
1497issue_and_wait(struct net_device *dev, int cmd)
1498{
62afe595
JL		 1499 struct vortex_private *vp = netdev_priv(dev);
1500 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1501 int i;
1502
62afe595 1503 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1504 for (i = 0; i < 2000; i++) {
62afe595 1505 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1506 return;
1507 }
1508
1509 /* OK, that didn't work. Do it the slow way. One second */
1510 for (i = 0; i < 100000; i++) {
62afe595 1511 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1512 if (vortex_debug > 1)
39738e16 1513 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1514 dev->name, cmd, i * 10);
1515 return;
1516 }
1517 udelay(10);
1518 }
39738e16 1519 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1520 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1521}
1522
125d5ce8
SK		 1523static void
1524vortex_set_duplex(struct net_device *dev)
1525{
1526 struct vortex_private *vp = netdev_priv(dev);
125d5ce8 1527
39738e16 1528 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1529 dev->name, (vp->full_duplex) ? "full" : "half");
1530
125d5ce8 1531 /* Set the full-duplex bit. */
a095cfc4
BH		 1532 window_write16(vp,
1533 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1534 (vp->large_frames ? 0x40 : 0) |
1535 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1536 0x100 : 0),
1537 3, Wn3_MAC_Ctrl);
125d5ce8
SK		 1538}
1539
1540static void vortex_check_media(struct net_device *dev, unsigned int init)
1541{
1542 struct vortex_private *vp = netdev_priv(dev);
1543 unsigned int ok_to_print = 0;
1544
1545 if (vortex_debug > 3)
1546 ok_to_print = 1;
1547
1548 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1549 vp->full_duplex = vp->mii.full_duplex;
1550 vortex_set_duplex(dev);
1551 } else if (init) {
1552 vortex_set_duplex(dev);
1553 }
1554}
1555
c8303d10 1556static int
1da177e4
LT		 1557vortex_up(struct net_device *dev)
1558{
1da177e4 1559 struct vortex_private *vp = netdev_priv(dev);
62afe595 1560 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1561 unsigned int config;
0280f9f9 1562 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1563
1564 if (VORTEX_PCI(vp)) {
1565 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1566 if (vp->pm_state_valid)
1567 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1568 err = pci_enable_device(VORTEX_PCI(vp));
1569 if (err) {
39738e16 1570 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1571 dev->name);
1572 goto err_out;
1573 }
1da177e4
LT		 1574 }
1575
1576 /* Before initializing select the active media port. */
a095cfc4 1577 config = window_read32(vp, 3, Wn3_Config);
1da177e4
LT		 1578
1579 if (vp->media_override != 7) {
39738e16 1580 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1581 dev->name, vp->media_override,
1582 media_tbl[vp->media_override].name);
1583 dev->if_port = vp->media_override;
1584 } else if (vp->autoselect) {
1585 if (vp->has_nway) {
1586 if (vortex_debug > 1)
39738e16 1587 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1588 dev->name, dev->if_port);
1589 dev->if_port = XCVR_NWAY;
1590 } else {
1591 /* Find first available media type, starting with 100baseTx. */
1592 dev->if_port = XCVR_100baseTx;
1593 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1594 dev->if_port = media_tbl[dev->if_port].next;
1595 if (vortex_debug > 1)
39738e16 1596 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1597 dev->name, media_tbl[dev->if_port].name);
1598 }
1599 } else {
1600 dev->if_port = vp->default_media;
1601 if (vortex_debug > 1)
39738e16 1602 pr_info("%s: using default media %s\n",
1da177e4
LT		 1603 dev->name, media_tbl[dev->if_port].name);
1604 }
1605
1606 init_timer(&vp->timer);
1607 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1608 vp->timer.data = (unsigned long)dev;
1609 vp->timer.function = vortex_timer; /* timer handler */
1610 add_timer(&vp->timer);
1611
1612 init_timer(&vp->rx_oom_timer);
1613 vp->rx_oom_timer.data = (unsigned long)dev;
1614 vp->rx_oom_timer.function = rx_oom_timer;
1615
1616 if (vortex_debug > 1)
39738e16 1617 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1618 dev->name, media_tbl[dev->if_port].name);
1619
125d5ce8 1620 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1621 config = BFINS(config, dev->if_port, 20, 4);
1622 if (vortex_debug > 6)
39738e16 1623 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
a095cfc4 1624 window_write32(vp, config, 3, Wn3_Config);
1da177e4
LT		 1625
1626 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
09ce3512
SK		 1627 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1628 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1629 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1630 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1631
125d5ce8 1632 vortex_check_media(dev, 1);
1da177e4 1633 }
125d5ce8
SK		 1634 else
1635 vortex_set_duplex(dev);
1da177e4 1636
09ce3512
SK		 1637 issue_and_wait(dev, TxReset);
1638 /*
1639 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1640 */
1641 issue_and_wait(dev, RxReset|0x04);
1642
1da177e4 1643
62afe595 1644 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1645
1646 if (vortex_debug > 1) {
39738e16 1647 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
a095cfc4 1648 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1da177e4
LT		 1649 }
1650
1651 /* Set the station address and mask in window 2 each time opened. */
1da177e4 1652 for (i = 0; i < 6; i++)
a095cfc4 1653 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1654 for (; i < 12; i+=2)
a095cfc4 1655 window_write16(vp, 0, 2, i);
1da177e4
LT		 1656
1657 if (vp->cb_fn_base) {
a095cfc4 1658 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1659 if (vp->drv_flags & INVERT_LED_PWR)
1660 n |= 0x10;
1661 if (vp->drv_flags & INVERT_MII_PWR)
1662 n |= 0x4000;
a095cfc4 1663 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4
LT		 1664 }
1665
1666 if (dev->if_port == XCVR_10base2)
1667 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1668 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4 1669 if (dev->if_port != XCVR_NWAY) {
a095cfc4
BH		 1670 window_write16(vp,
1671 (window_read16(vp, 4, Wn4_Media) &
1672 ~(Media_10TP|Media_SQE)) |
1673 media_tbl[dev->if_port].media_bits,
1674 4, Wn4_Media);
1da177e4
LT		 1675 }
1676
1677 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1678 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4 1679 for (i = 0; i < 10; i++)
a095cfc4
BH		 1680 window_read8(vp, 6, i);
1681 window_read16(vp, 6, 10);
1682 window_read16(vp, 6, 12);
1da177e4 1683 /* New: On the Vortex we must also clear the BadSSD counter. */
a095cfc4 1684 window_read8(vp, 4, 12);
1da177e4 1685 /* ..and on the Boomerang we enable the extra statistics bits. */
a095cfc4 1686 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1da177e4
LT		 1687
1688 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1689 vp->cur_rx = vp->dirty_rx = 0;
1690 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1691 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1692 iowrite32(0x0020, ioaddr + PktStatus);
1693 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1694 }
1695 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1696 vp->cur_tx = vp->dirty_tx = 0;
1697 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1698 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1699 /* Clear the Rx, Tx rings. */
1700 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1701 vp->rx_ring[i].status = 0;
1702 for (i = 0; i < TX_RING_SIZE; i++)
1703 vp->tx_skbuff[i] = NULL;
62afe595 1704 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1705 }
1706 /* Set receiver mode: presumably accept b-case and phys addr only. */
1707 set_rx_mode(dev);
1708 /* enable 802.1q tagged frames */
1709 set_8021q_mode(dev, 1);
62afe595 1710 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1711
62afe595
JL		 1712 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1713 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1714 /* Allow status bits to be seen. */
1715 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1716 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1717 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1718 (vp->bus_master ? DMADone : 0);
1719 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1720 (vp->full_bus_master_rx ? 0 : RxComplete) |
1721 StatsFull | HostError | TxComplete | IntReq
1722 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1723 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1724 /* Ack all pending events, and set active indicator mask. */
62afe595 1725 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1726 ioaddr + EL3_CMD);
62afe595 1727 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1728 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1729 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1730 netif_start_queue (dev);
c8303d10
MH		 1731err_out:
1732 return err;
1da177e4
LT		 1733}
1734
1735static int
1736vortex_open(struct net_device *dev)
1737{
1738 struct vortex_private *vp = netdev_priv(dev);
1739 int i;
1740 int retval;
1741
1742 /* Use the now-standard shared IRQ implementation. */
1743 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
c061b18d 1744 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1745 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1746 goto err;
1da177e4
LT		 1747 }
1748
1749 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1750 if (vortex_debug > 2)
39738e16 1751 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1752 for (i = 0; i < RX_RING_SIZE; i++) {
1753 struct sk_buff *skb;
1754 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1755 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1756 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1757
1758 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1759 GFP_KERNEL);
1da177e4
LT		 1760 vp->rx_skbuff[i] = skb;
1761 if (skb == NULL)
1762 break; /* Bad news! */
9a5d3414
SH		 1763
1764 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1765 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1766 }
1767 if (i != RX_RING_SIZE) {
1768 int j;
39738e16 1769 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1770 for (j = 0; j < i; j++) {
1771 if (vp->rx_skbuff[j]) {
1772 dev_kfree_skb(vp->rx_skbuff[j]);
1773 vp->rx_skbuff[j] = NULL;
1774 }
1775 }
1776 retval = -ENOMEM;
c8303d10 1777 goto err_free_irq;
1da177e4
LT		 1778 }
1779 /* Wrap the ring. */
1780 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1781 }
1782
c8303d10
MH		 1783 retval = vortex_up(dev);
1784 if (!retval)
1785 goto out;
1da177e4 1786
c8303d10 1787err_free_irq:
1da177e4 1788 free_irq(dev->irq, dev);
c8303d10 1789err:
1da177e4 1790 if (vortex_debug > 1)
39738e16 1791 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1792out:
1da177e4
LT		 1793 return retval;
1794}
1795
1796static void
1797vortex_timer(unsigned long data)
1798{
1799 struct net_device *dev = (struct net_device *)data;
1800 struct vortex_private *vp = netdev_priv(dev);
62afe595 1801 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1802 int next_tick = 60*HZ;
1803 int ok = 0;
a095cfc4 1804 int media_status;
1da177e4
LT		 1805
1806 if (vortex_debug > 2) {
39738e16 1807 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1808 dev->name, media_tbl[dev->if_port].name);
39738e16 1809 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1810 }
1811
a095cfc4 1812 media_status = window_read16(vp, 4, Wn4_Media);
1da177e4
LT		 1813 switch (dev->if_port) {
1814 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1815 if (media_status & Media_LnkBeat) {
1816 netif_carrier_on(dev);
1817 ok = 1;
1818 if (vortex_debug > 1)
39738e16 1819 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1820 dev->name, media_tbl[dev->if_port].name, media_status);
1821 } else {
1822 netif_carrier_off(dev);
1823 if (vortex_debug > 1) {
39738e16 1824 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1825 dev->name, media_tbl[dev->if_port].name, media_status);
1826 }
1827 }
1828 break;
1829 case XCVR_MII: case XCVR_NWAY:
1830 {
1da177e4 1831 ok = 1;
125d5ce8 1832 vortex_check_media(dev, 0);
1da177e4
LT		 1833 }
1834 break;
1835 default: /* Other media types handled by Tx timeouts. */
1836 if (vortex_debug > 1)
39738e16 1837 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1838 dev->name, media_tbl[dev->if_port].name, media_status);
1839 ok = 1;
1840 }
b4ff6450 1841
3013dc0c 1842 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
b4ff6450
SK		 1843 next_tick = 5*HZ;
1844
e94d10eb
SK		 1845 if (vp->medialock)
1846 goto leave_media_alone;
1847
a880c4cd 1848 if (!ok) {
1da177e4
LT		 1849 unsigned int config;
1850
de847272
BH		 1851 spin_lock_irq(&vp->lock);
1852
1da177e4
LT		 1853 do {
1854 dev->if_port = media_tbl[dev->if_port].next;
1855 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1856 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1857 dev->if_port = vp->default_media;
1858 if (vortex_debug > 1)
39738e16 1859 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1860 dev->name, media_tbl[dev->if_port].name);
1861 } else {
1862 if (vortex_debug > 1)
39738e16 1863 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1864 dev->name, media_tbl[dev->if_port].name);
1865 next_tick = media_tbl[dev->if_port].wait;
1866 }
a095cfc4
BH		 1867 window_write16(vp,
1868 (media_status & ~(Media_10TP|Media_SQE)) |
1869 media_tbl[dev->if_port].media_bits,
1870 4, Wn4_Media);
1da177e4 1871
a095cfc4 1872 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1873 config = BFINS(config, dev->if_port, 20, 4);
a095cfc4 1874 window_write32(vp, config, 3, Wn3_Config);
1da177e4 1875
62afe595 1876 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1877 ioaddr + EL3_CMD);
1878 if (vortex_debug > 1)
39738e16 1879 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4 1880 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
de847272
BH		 1881
1882 spin_unlock_irq(&vp->lock);
1da177e4 1883 }
1da177e4
LT		 1884
1885leave_media_alone:
1886 if (vortex_debug > 2)
39738e16 1887 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1888 dev->name, media_tbl[dev->if_port].name);
1889
1890 mod_timer(&vp->timer, RUN_AT(next_tick));
1891 if (vp->deferred)
62afe595 1892 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1893}
1894
1895static void vortex_tx_timeout(struct net_device *dev)
1896{
1897 struct vortex_private *vp = netdev_priv(dev);
62afe595 1898 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1899
39738e16 1900 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1901 dev->name, ioread8(ioaddr + TxStatus),
1902 ioread16(ioaddr + EL3_STATUS));
39738e16 1903 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
a095cfc4
BH		 1904 window_read16(vp, 4, Wn4_NetDiag),
1905 window_read16(vp, 4, Wn4_Media),
62afe595 1906 ioread32(ioaddr + PktStatus),
a095cfc4 1907 window_read16(vp, 4, Wn4_FIFODiag));
1da177e4 1908 /* Slight code bloat to be user friendly. */
62afe595 1909 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1910 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1911 " network cable problem?\n", dev->name);
62afe595 1912 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1913 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1914 " IRQ blocked by another device?\n", dev->name);
1915 /* Bad idea here.. but we might as well handle a few events. */
1916 {
1917 /*
1918 * Block interrupts because vortex_interrupt does a bare spin_lock()
1919 */
1920 unsigned long flags;
1921 local_irq_save(flags);
1922 if (vp->full_bus_master_tx)
7d12e780 1923 boomerang_interrupt(dev->irq, dev);
1da177e4 1924 else
7d12e780 1925 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1926 local_irq_restore(flags);
1927 }
1928 }
1929
1930 if (vortex_debug > 0)
1931 dump_tx_ring(dev);
1932
1933 issue_and_wait(dev, TxReset);
1934
1daad055 1935 dev->stats.tx_errors++;
1da177e4 1936 if (vp->full_bus_master_tx) {
39738e16 1937 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1938 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1939 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1940 ioaddr + DownListPtr);
1941 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1942 netif_wake_queue (dev);
1943 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1944 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1945 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1946 } else {
1daad055 1947 dev->stats.tx_dropped++;
1da177e4
LT		 1948 netif_wake_queue(dev);
1949 }
6aa20a22 1950
1da177e4 1951 /* Issue Tx Enable */
62afe595 1952 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1953 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1954}
1955
1956/*
1957 * Handle uncommon interrupt sources. This is a separate routine to minimize
1958 * the cache impact.
1959 */
1960static void
1961vortex_error(struct net_device *dev, int status)
1962{
1963 struct vortex_private *vp = netdev_priv(dev);
62afe595 1964 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1965 int do_tx_reset = 0, reset_mask = 0;
1966 unsigned char tx_status = 0;
1967
1968 if (vortex_debug > 2) {
39738e16 1969 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1970 }
1971
1972 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1973 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1974 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1975 if (vortex_debug > 2 ||
1976 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1977 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1978 dev->name, tx_status);
1979 if (tx_status == 0x82) {
39738e16 1980 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1981 "Documentation/networking/vortex.txt\n");
1982 }
1983 dump_tx_ring(dev);
1984 }
1daad055
PZ		 1985 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1986 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1987 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1988 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1989 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1990 do_tx_reset = 1;
0000754c
AM		 1991 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1992 do_tx_reset = 1;
1993 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1994 } else { /* Merely re-enable the transmitter. */
62afe595 1995 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1996 }
1997 }
1998
89b12fab 1999 if (status & RxEarly) /* Rx early is unused. */
62afe595 2000 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
89b12fab 2001
1da177e4
LT		 2002 if (status & StatsFull) { /* Empty statistics. */
2003 static int DoneDidThat;
2004 if (vortex_debug > 4)
39738e16 2005 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 2006 update_stats(ioaddr, dev);
2007 /* HACK: Disable statistics as an interrupt source. */
2008 /* This occurs when we have the wrong media type! */
2009 if (DoneDidThat == 0 &&
62afe595 2010 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 2011 pr_warning("%s: Updating statistics failed, disabling "
1da177e4 2012 "stats as an interrupt source.\n", dev->name);
a095cfc4
BH		 2013 iowrite16(SetIntrEnb |
2014 (window_read16(vp, 5, 10) & ~StatsFull),
2015 ioaddr + EL3_CMD);
1da177e4 2016 vp->intr_enable &= ~StatsFull;
1da177e4
LT		 2017 DoneDidThat++;
2018 }
2019 }
2020 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2021 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2022 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2023 }
2024 if (status & HostError) {
2025 u16 fifo_diag;
a095cfc4 2026 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
39738e16 2027 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2028 dev->name, fifo_diag);
2029 /* Adapter failure requires Tx/Rx reset and reinit. */
2030 if (vp->full_bus_master_tx) {
62afe595 2031 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2032 /* 0x80000000 PCI master abort. */
2033 /* 0x40000000 PCI target abort. */
2034 if (vortex_debug)
39738e16 2035 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2036
2037 /* In this case, blow the card away */
2038 /* Must not enter D3 or we can't legally issue the reset! */
2039 vortex_down(dev, 0);
2040 issue_and_wait(dev, TotalReset | 0xff);
2041 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2042 } else if (fifo_diag & 0x0400)
2043 do_tx_reset = 1;
2044 if (fifo_diag & 0x3000) {
2045 /* Reset Rx fifo and upload logic */
2046 issue_and_wait(dev, RxReset|0x07);
2047 /* Set the Rx filter to the current state. */
2048 set_rx_mode(dev);
2049 /* enable 802.1q VLAN tagged frames */
2050 set_8021q_mode(dev, 1);
62afe595
JL		 2051 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2052 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2053 }
2054 }
2055
2056 if (do_tx_reset) {
2057 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2058 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2059 if (!vp->full_bus_master_tx)
2060 netif_wake_queue(dev);
2061 }
2062}
2063
27a1de95 2064static netdev_tx_t
1da177e4
LT		 2065vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2066{
2067 struct vortex_private *vp = netdev_priv(dev);
62afe595 2068 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2069
2070 /* Put out the doubleword header... */
62afe595 2071 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2072 if (vp->bus_master) {
2073 /* Set the bus-master controller to transfer the packet. */
2074 int len = (skb->len + 3) & ~3;
a095cfc4
BH		 2075 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2076 PCI_DMA_TODEVICE);
de847272 2077 spin_lock_irq(&vp->window_lock);
a095cfc4
BH		 2078 window_set(vp, 7);
2079 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
62afe595 2080 iowrite16(len, ioaddr + Wn7_MasterLen);
de847272 2081 spin_unlock_irq(&vp->window_lock);
1da177e4 2082 vp->tx_skb = skb;
62afe595 2083 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2084 /* netif_wake_queue() will be called at the DMADone interrupt. */
2085 } else {
2086 /* ... and the packet rounded to a doubleword. */
62afe595 2087 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2088 dev_kfree_skb (skb);
62afe595 2089 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2090 netif_start_queue (dev); /* AKPM: redundant? */
2091 } else {
2092 /* Interrupt us when the FIFO has room for max-sized packet. */
2093 netif_stop_queue(dev);
62afe595 2094 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2095 }
2096 }
2097
1da177e4
LT		 2098
2099 /* Clear the Tx status stack. */
2100 {
2101 int tx_status;
2102 int i = 32;
2103
62afe595 2104 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2105 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2106 if (vortex_debug > 2)
39738e16 2107 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2108 dev->name, tx_status);
1daad055
PZ		 2109 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2110 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2111 if (tx_status & 0x30) {
2112 issue_and_wait(dev, TxReset);
2113 }
62afe595 2114 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2115 }
62afe595 2116 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2117 }
2118 }
6ed10654 2119 return NETDEV_TX_OK;
1da177e4
LT		 2120}
2121
27a1de95 2122static netdev_tx_t
1da177e4
LT		 2123boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2124{
2125 struct vortex_private *vp = netdev_priv(dev);
62afe595 2126 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2127 /* Calculate the next Tx descriptor entry. */
2128 int entry = vp->cur_tx % TX_RING_SIZE;
2129 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2130 unsigned long flags;
2131
2132 if (vortex_debug > 6) {
39738e16
AB		 2133 pr_debug("boomerang_start_xmit()\n");
2134 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2135 dev->name, vp->cur_tx);
1da177e4
LT		 2136 }
2137
aa25ab7d
NH		 2138 /*
2139 * We can't allow a recursion from our interrupt handler back into the
2140 * tx routine, as they take the same spin lock, and that causes
2141 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2142 * a bit
2143 */
2144 if (vp->handling_irq)
2145 return NETDEV_TX_BUSY;
2146
1da177e4
LT		 2147 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2148 if (vortex_debug > 0)
39738e16 2149 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2150 dev->name);
2151 netif_stop_queue(dev);
5b548140 2152 return NETDEV_TX_BUSY;
1da177e4
LT		 2153 }
2154
2155 vp->tx_skbuff[entry] = skb;
2156
2157 vp->tx_ring[entry].next = 0;
2158#if DO_ZEROCOPY
84fa7933 2159 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2160 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2161 else
2162 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2163
2164 if (!skb_shinfo(skb)->nr_frags) {
2165 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2166 skb->len, PCI_DMA_TODEVICE));
2167 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2168 } else {
2169 int i;
2170
2171 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2172 skb_headlen(skb), PCI_DMA_TODEVICE));
2173 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2174
2175 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2176 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2177
2178 vp->tx_ring[entry].frag[i+1].addr =
7b63e3a8
IC		 2179 cpu_to_le32(pci_map_single(
2180 VORTEX_PCI(vp),
2181 (void *)skb_frag_address(frag),
9e903e08 2182 skb_frag_size(frag), PCI_DMA_TODEVICE));
1da177e4
LT		 2183
2184 if (i == skb_shinfo(skb)->nr_frags-1)
9e903e08 2185 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
1da177e4 2186 else
9e903e08 2187 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
1da177e4
LT		 2188 }
2189 }
2190#else
2191 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2192 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2193 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2194#endif
2195
2196 spin_lock_irqsave(&vp->lock, flags);
2197 /* Wait for the stall to complete. */
2198 issue_and_wait(dev, DownStall);
2199 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2200 if (ioread32(ioaddr + DownListPtr) == 0) {
2201 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2202 vp->queued_packet++;
2203 }
2204
2205 vp->cur_tx++;
2206 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2207 netif_stop_queue (dev);
2208 } else { /* Clear previous interrupt enable. */
2209#if defined(tx_interrupt_mitigation)
2210 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2211 * were selected, this would corrupt DN_COMPLETE. No?
2212 */
2213 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2214#endif
2215 }
62afe595 2216 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2217 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2218 return NETDEV_TX_OK;
1da177e4
LT		 2219}
2220
2221/* The interrupt handler does all of the Rx thread work and cleans up
2222 after the Tx thread. */
2223
2224/*
2225 * This is the ISR for the vortex series chips.
2226 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2227 */
2228
2229static irqreturn_t
7d12e780 2230vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2231{
2232 struct net_device *dev = dev_id;
2233 struct vortex_private *vp = netdev_priv(dev);
62afe595 2234 void __iomem *ioaddr;
1da177e4
LT		 2235 int status;
2236 int work_done = max_interrupt_work;
2237 int handled = 0;
2238
62afe595 2239 ioaddr = vp->ioaddr;
1da177e4
LT		 2240 spin_lock(&vp->lock);
2241
62afe595 2242 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2243
2244 if (vortex_debug > 6)
39738e16 2245 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2246
2247 if ((status & IntLatch) == 0)
2248 goto handler_exit; /* No interrupt: shared IRQs cause this */
2249 handled = 1;
2250
2251 if (status & IntReq) {
2252 status |= vp->deferred;
2253 vp->deferred = 0;
2254 }
2255
2256 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2257 goto handler_exit;
2258
2259 if (vortex_debug > 4)
39738e16 2260 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2261 dev->name, status, ioread8(ioaddr + Timer));
1da177e4 2262
de847272 2263 spin_lock(&vp->window_lock);
a095cfc4
BH		 2264 window_set(vp, 7);
2265
1da177e4
LT		 2266 do {
2267 if (vortex_debug > 5)
39738e16 2268 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2269 dev->name, status);
2270 if (status & RxComplete)
2271 vortex_rx(dev);
2272
2273 if (status & TxAvailable) {
2274 if (vortex_debug > 5)
39738e16 2275 pr_debug(" TX room bit was handled.\n");
1da177e4 2276 /* There's room in the FIFO for a full-sized packet. */
62afe595 2277 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2278 netif_wake_queue (dev);
2279 }
2280
2281 if (status & DMADone) {
62afe595
JL		 2282 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2283 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2284 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2285 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2286 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2287 /*
2288 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2289 * insufficient FIFO room, the TxAvailable test will succeed and call
2290 * netif_wake_queue()
2291 */
2292 netif_wake_queue(dev);
2293 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2294 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2295 netif_stop_queue(dev);
2296 }
2297 }
2298 }
2299 /* Check for all uncommon interrupts at once. */
2300 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2301 if (status == 0xffff)
2302 break;
89b12fab
BH		 2303 if (status & RxEarly)
2304 vortex_rx(dev);
2305 spin_unlock(&vp->window_lock);
1da177e4 2306 vortex_error(dev, status);
89b12fab
BH		 2307 spin_lock(&vp->window_lock);
2308 window_set(vp, 7);
1da177e4
LT		 2309 }
2310
2311 if (--work_done < 0) {
39738e16
AB		 2312 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2313 dev->name, status);
1da177e4
LT		 2314 /* Disable all pending interrupts. */
2315 do {
2316 vp->deferred |= status;
62afe595 2317 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2318 ioaddr + EL3_CMD);
62afe595
JL		 2319 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2320 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2321 /* The timer will reenable interrupts. */
2322 mod_timer(&vp->timer, jiffies + 1*HZ);
2323 break;
2324 }
2325 /* Acknowledge the IRQ. */
62afe595
JL		 2326 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2327 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4 2328
de847272
BH		 2329 spin_unlock(&vp->window_lock);
2330
1da177e4 2331 if (vortex_debug > 4)
39738e16 2332 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2333 dev->name, status);
2334handler_exit:
2335 spin_unlock(&vp->lock);
2336 return IRQ_RETVAL(handled);
2337}
2338
2339/*
2340 * This is the ISR for the boomerang series chips.
2341 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2342 */
2343
2344static irqreturn_t
7d12e780 2345boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2346{
2347 struct net_device *dev = dev_id;
2348 struct vortex_private *vp = netdev_priv(dev);
62afe595 2349 void __iomem *ioaddr;
1da177e4
LT		 2350 int status;
2351 int work_done = max_interrupt_work;
2352
62afe595 2353 ioaddr = vp->ioaddr;
1da177e4 2354
aa25ab7d 2355
1da177e4
LT		 2356 /*
2357 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2358 * and boomerang_start_xmit
2359 */
2360 spin_lock(&vp->lock);
aa25ab7d 2361 vp->handling_irq = 1;
1da177e4 2362
62afe595 2363 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2364
2365 if (vortex_debug > 6)
39738e16 2366 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2367
2368 if ((status & IntLatch) == 0)
2369 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2370
2371 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2372 if (vortex_debug > 1)
39738e16 2373 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2374 goto handler_exit;
2375 }
2376
2377 if (status & IntReq) {
2378 status |= vp->deferred;
2379 vp->deferred = 0;
2380 }
2381
2382 if (vortex_debug > 4)
39738e16 2383 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2384 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2385 do {
2386 if (vortex_debug > 5)
39738e16 2387 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2388 dev->name, status);
2389 if (status & UpComplete) {
62afe595 2390 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2391 if (vortex_debug > 5)
39738e16 2392 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2393 boomerang_rx(dev);
2394 }
2395
2396 if (status & DownComplete) {
2397 unsigned int dirty_tx = vp->dirty_tx;
2398
62afe595 2399 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2400 while (vp->cur_tx - dirty_tx > 0) {
2401 int entry = dirty_tx % TX_RING_SIZE;
2402#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2403 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2404 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2405 break; /* It still hasn't been processed. */
2406#else
2407 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2408 break; /* It still hasn't been processed. */
2409#endif
6aa20a22 2410
1da177e4
LT		 2411 if (vp->tx_skbuff[entry]) {
2412 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2413#if DO_ZEROCOPY
1da177e4
LT		 2414 int i;
2415 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2416 pci_unmap_single(VORTEX_PCI(vp),
2417 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2418 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2419 PCI_DMA_TODEVICE);
2420#else
2421 pci_unmap_single(VORTEX_PCI(vp),
2422 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2423#endif
2424 dev_kfree_skb_irq(skb);
2425 vp->tx_skbuff[entry] = NULL;
2426 } else {
39738e16 2427 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2428 }
1daad055 2429 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2430 dirty_tx++;
2431 }
2432 vp->dirty_tx = dirty_tx;
2433 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2434 if (vortex_debug > 6)
39738e16 2435 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2436 netif_wake_queue (dev);
2437 }
2438 }
2439
2440 /* Check for all uncommon interrupts at once. */
2441 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2442 vortex_error(dev, status);
2443
2444 if (--work_done < 0) {
39738e16
AB		 2445 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2446 dev->name, status);
1da177e4
LT		 2447 /* Disable all pending interrupts. */
2448 do {
2449 vp->deferred |= status;
62afe595 2450 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2451 ioaddr + EL3_CMD);
62afe595
JL		 2452 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2453 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2454 /* The timer will reenable interrupts. */
2455 mod_timer(&vp->timer, jiffies + 1*HZ);
2456 break;
2457 }
2458 /* Acknowledge the IRQ. */
62afe595 2459 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2460 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2461 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2462
62afe595 2463 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2464
2465 if (vortex_debug > 4)
39738e16 2466 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2467 dev->name, status);
2468handler_exit:
aa25ab7d 2469 vp->handling_irq = 0;
1da177e4
LT		 2470 spin_unlock(&vp->lock);
2471 return IRQ_HANDLED;
2472}
2473
2474static int vortex_rx(struct net_device *dev)
2475{
2476 struct vortex_private *vp = netdev_priv(dev);
62afe595 2477 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2478 int i;
2479 short rx_status;
2480
2481 if (vortex_debug > 5)
39738e16 2482 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2483 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2484 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2485 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2486 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2487 if (vortex_debug > 2)
39738e16 2488 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2489 dev->stats.rx_errors++;
2490 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2491 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2492 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2493 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2494 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2495 } else {
2496 /* The packet length: up to 4.5K!. */
2497 int pkt_len = rx_status & 0x1fff;
2498 struct sk_buff *skb;
2499
1d266430 2500 skb = netdev_alloc_skb(dev, pkt_len + 5);
1da177e4 2501 if (vortex_debug > 4)
39738e16 2502 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2503 pkt_len, rx_status);
2504 if (skb != NULL) {
1da177e4
LT		 2505 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2506 /* 'skb_put()' points to the start of sk_buff data area. */
2507 if (vp->bus_master &&
62afe595 2508 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2509 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2510 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2511 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2512 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2513 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2514 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2515 ;
2516 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2517 } else {
62afe595
JL		 2518 ioread32_rep(ioaddr + RX_FIFO,
2519 skb_put(skb, pkt_len),
2520 (pkt_len + 3) >> 2);
1da177e4 2521 }
62afe595 2522 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2523 skb->protocol = eth_type_trans(skb, dev);
2524 netif_rx(skb);
1daad055 2525 dev->stats.rx_packets++;
1da177e4
LT		 2526 /* Wait a limited time to go to next packet. */
2527 for (i = 200; i >= 0; i--)
62afe595 2528 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2529 break;
2530 continue;
2531 } else if (vortex_debug > 0)
39738e16
AB		 2532 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2533 dev->name, pkt_len);
1daad055 2534 dev->stats.rx_dropped++;
1da177e4 2535 }
1da177e4
LT		 2536 issue_and_wait(dev, RxDiscard);
2537 }
2538
2539 return 0;
2540}
2541
2542static int
2543boomerang_rx(struct net_device *dev)
2544{
2545 struct vortex_private *vp = netdev_priv(dev);
2546 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2547 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2548 int rx_status;
2549 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2550
2551 if (vortex_debug > 5)
39738e16 2552 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2553
2554 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2555 if (--rx_work_limit < 0)
2556 break;
2557 if (rx_status & RxDError) { /* Error, update stats. */
2558 unsigned char rx_error = rx_status >> 16;
2559 if (vortex_debug > 2)
39738e16 2560 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2561 dev->stats.rx_errors++;
2562 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2563 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2564 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2565 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2566 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2567 } else {
2568 /* The packet length: up to 4.5K!. */
2569 int pkt_len = rx_status & 0x1fff;
2570 struct sk_buff *skb;
2571 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2572
2573 if (vortex_debug > 4)
39738e16 2574 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2575 pkt_len, rx_status);
2576
2577 /* Check if the packet is long enough to just accept without
2578 copying to a properly sized skbuff. */
1d266430
PD		 2579 if (pkt_len < rx_copybreak &&
2580 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1da177e4
LT		 2581 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2582 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2583 /* 'skb_put()' points to the start of sk_buff data area. */
2584 memcpy(skb_put(skb, pkt_len),
689be439 2585 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2586 pkt_len);
2587 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2588 vp->rx_copy++;
2589 } else {
2590 /* Pass up the skbuff already on the Rx ring. */
2591 skb = vp->rx_skbuff[entry];
2592 vp->rx_skbuff[entry] = NULL;
2593 skb_put(skb, pkt_len);
2594 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2595 vp->rx_nocopy++;
2596 }
2597 skb->protocol = eth_type_trans(skb, dev);
2598 { /* Use hardware checksum info. */
2599 int csum_bits = rx_status & 0xee000000;
2600 if (csum_bits &&
2601 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2602 csum_bits == (IPChksumValid | UDPChksumValid))) {
2603 skb->ip_summed = CHECKSUM_UNNECESSARY;
2604 vp->rx_csumhits++;
2605 }
2606 }
2607 netif_rx(skb);
1daad055 2608 dev->stats.rx_packets++;
1da177e4
LT		 2609 }
2610 entry = (++vp->cur_rx) % RX_RING_SIZE;
2611 }
2612 /* Refill the Rx ring buffers. */
2613 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2614 struct sk_buff *skb;
2615 entry = vp->dirty_rx % RX_RING_SIZE;
2616 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2617 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2618 if (skb == NULL) {
2619 static unsigned long last_jif;
ff5688ae 2620 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2621 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2622 last_jif = jiffies;
2623 }
2624 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2625 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2626 break; /* Bad news! */
2627 }
9a5d3414 2628
689be439 2629 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2630 vp->rx_skbuff[entry] = skb;
2631 }
2632 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2633 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2634 }
2635 return 0;
2636}
2637
2638/*
2639 * If we've hit a total OOM refilling the Rx ring we poll once a second
2640 * for some memory. Otherwise there is no way to restart the rx process.
2641 */
2642static void
2643rx_oom_timer(unsigned long arg)
2644{
2645 struct net_device *dev = (struct net_device *)arg;
2646 struct vortex_private *vp = netdev_priv(dev);
2647
2648 spin_lock_irq(&vp->lock);
2649 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2650 boomerang_rx(dev);
2651 if (vortex_debug > 1) {
39738e16 2652 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2653 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2654 }
2655 spin_unlock_irq(&vp->lock);
2656}
2657
2658static void
2659vortex_down(struct net_device *dev, int final_down)
2660{
2661 struct vortex_private *vp = netdev_priv(dev);
62afe595 2662 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2663
2664 netif_stop_queue (dev);
2665
2666 del_timer_sync(&vp->rx_oom_timer);
2667 del_timer_sync(&vp->timer);
2668
1daad055 2669 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2670 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2671
2672 /* Disable the receiver and transmitter. */
62afe595
JL		 2673 iowrite16(RxDisable, ioaddr + EL3_CMD);
2674 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2675
2676 /* Disable receiving 802.1q tagged frames */
2677 set_8021q_mode(dev, 0);
2678
2679 if (dev->if_port == XCVR_10base2)
2680 /* Turn off thinnet power. Green! */
62afe595 2681 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2682
62afe595 2683 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2684
2685 update_stats(ioaddr, dev);
2686 if (vp->full_bus_master_rx)
62afe595 2687 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2688 if (vp->full_bus_master_tx)
62afe595 2689 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2690
2691 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2692 vp->pm_state_valid = 1;
1da177e4
LT		 2693 pci_save_state(VORTEX_PCI(vp));
2694 acpi_set_WOL(dev);
2695 }
2696}
2697
2698static int
2699vortex_close(struct net_device *dev)
2700{
2701 struct vortex_private *vp = netdev_priv(dev);
62afe595 2702 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2703 int i;
2704
2705 if (netif_device_present(dev))
2706 vortex_down(dev, 1);
2707
2708 if (vortex_debug > 1) {
39738e16 2709 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2710 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2711 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2712 " tx_queued %d Rx pre-checksummed %d.\n",
2713 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2714 }
2715
2716#if DO_ZEROCOPY
32fb5f06
JL		 2717 if (vp->rx_csumhits &&
2718 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2719 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2720 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2721 }
2722#endif
6aa20a22 2723
1da177e4
LT		 2724 free_irq(dev->irq, dev);
2725
2726 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2727 for (i = 0; i < RX_RING_SIZE; i++)
2728 if (vp->rx_skbuff[i]) {
2729 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2730 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2731 dev_kfree_skb(vp->rx_skbuff[i]);
2732 vp->rx_skbuff[i] = NULL;
2733 }
2734 }
2735 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2736 for (i = 0; i < TX_RING_SIZE; i++) {
2737 if (vp->tx_skbuff[i]) {
2738 struct sk_buff *skb = vp->tx_skbuff[i];
2739#if DO_ZEROCOPY
2740 int k;
2741
2742 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2743 pci_unmap_single(VORTEX_PCI(vp),
2744 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2745 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2746 PCI_DMA_TODEVICE);
2747#else
2748 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2749#endif
2750 dev_kfree_skb(skb);
2751 vp->tx_skbuff[i] = NULL;
2752 }
2753 }
2754 }
2755
2756 return 0;
2757}
2758
2759static void
2760dump_tx_ring(struct net_device *dev)
2761{
2762 if (vortex_debug > 0) {
2763 struct vortex_private *vp = netdev_priv(dev);
62afe595 2764 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2765
1da177e4
LT		 2766 if (vp->full_bus_master_tx) {
2767 int i;
62afe595 2768 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2769
39738e16 2770 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2771 vp->full_bus_master_tx,
2772 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2773 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2774 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2775 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2776 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2777 issue_and_wait(dev, DownStall);
2778 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2779 unsigned int length;
2780
1da177e4 2781#if DO_ZEROCOPY
0cb13536 2782 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2783#else
0cb13536 2784 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2785#endif
0cb13536
JD		 2786 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2787 i, &vp->tx_ring[i], length,
1da177e4
LT		 2788 le32_to_cpu(vp->tx_ring[i].status));
2789 }
2790 if (!stalled)
62afe595 2791 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2792 }
2793 }
2794}
2795
2796static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2797{
2798 struct vortex_private *vp = netdev_priv(dev);
62afe595 2799 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2800 unsigned long flags;
2801
2802 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2803 spin_lock_irqsave (&vp->lock, flags);
62afe595 2804 update_stats(ioaddr, dev);
1da177e4
LT		 2805 spin_unlock_irqrestore (&vp->lock, flags);
2806 }
1daad055 2807 return &dev->stats;
1da177e4
LT		 2808}
2809
2810/* Update statistics.
2811 Unlike with the EL3 we need not worry about interrupts changing
2812 the window setting from underneath us, but we must still guard
2813 against a race condition with a StatsUpdate interrupt updating the
2814 table. This is done by checking that the ASM (!) code generated uses
2815 atomic updates with '+='.
2816 */
62afe595 2817static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2818{
2819 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2820
1da177e4
LT		 2821 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2822 /* Switch to the stats window, and read everything. */
a095cfc4
BH		 2823 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2824 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2825 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2826 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2827 dev->stats.tx_packets += window_read8(vp, 6, 6);
2828 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2829 0x30) << 4;
2830 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
1da177e4
LT		 2831 /* Don't bother with register 9, an extension of registers 6&7.
2832 If we do use the 6&7 values the atomic update assumption above
2833 is invalid. */
a095cfc4
BH		 2834 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2835 dev->stats.tx_bytes += window_read16(vp, 6, 12);
1da177e4 2836 /* Extra stats for get_ethtool_stats() */
a095cfc4
BH		 2837 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2838 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2839 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2840 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
1da177e4 2841
1daad055 2842 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2843 + vp->xstats.tx_single_collisions
2844 + vp->xstats.tx_max_collisions;
2845
1da177e4 2846 {
a095cfc4 2847 u8 up = window_read8(vp, 4, 13);
1daad055
PZ		 2848 dev->stats.rx_bytes += (up & 0x0f) << 16;
2849 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4 2850 }
1da177e4
LT		 2851}
2852
2853static int vortex_nway_reset(struct net_device *dev)
2854{
2855 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2856
de847272 2857 return mii_nway_restart(&vp->mii);
1da177e4
LT		 2858}
2859
1da177e4
LT		 2860static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2861{
2862 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2863
de847272 2864 return mii_ethtool_gset(&vp->mii, cmd);
1da177e4
LT		 2865}
2866
2867static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2868{
2869 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2870
de847272 2871 return mii_ethtool_sset(&vp->mii, cmd);
1da177e4
LT		 2872}
2873
2874static u32 vortex_get_msglevel(struct net_device *dev)
2875{
2876 return vortex_debug;
2877}
2878
2879static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2880{
2881 vortex_debug = dbg;
2882}
2883
b9f2c044 2884static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2885{
b9f2c044
JG		 2886 switch (sset) {
2887 case ETH_SS_STATS:
2888 return VORTEX_NUM_STATS;
2889 default:
2890 return -EOPNOTSUPP;
2891 }
1da177e4
LT		 2892}
2893
2894static void vortex_get_ethtool_stats(struct net_device *dev,
2895 struct ethtool_stats *stats, u64 *data)
2896{
2897 struct vortex_private *vp = netdev_priv(dev);
62afe595 2898 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2899 unsigned long flags;
2900
2901 spin_lock_irqsave(&vp->lock, flags);
62afe595 2902 update_stats(ioaddr, dev);
1da177e4
LT		 2903 spin_unlock_irqrestore(&vp->lock, flags);
2904
2905 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2906 data[1] = vp->xstats.tx_max_collisions;
2907 data[2] = vp->xstats.tx_multiple_collisions;
2908 data[3] = vp->xstats.tx_single_collisions;
2909 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2910}
2911
2912
2913static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2914{
2915 switch (stringset) {
2916 case ETH_SS_STATS:
2917 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2918 break;
2919 default:
2920 WARN_ON(1);
2921 break;
2922 }
2923}
2924
2925static void vortex_get_drvinfo(struct net_device *dev,
2926 struct ethtool_drvinfo *info)
2927{
2928 struct vortex_private *vp = netdev_priv(dev);
2929
68aad78c 2930 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1da177e4 2931 if (VORTEX_PCI(vp)) {
68aad78c
RJ		 2932 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2933 sizeof(info->bus_info));
1da177e4
LT		 2934 } else {
2935 if (VORTEX_EISA(vp))
68aad78c
RJ		 2936 strlcpy(info->bus_info, dev_name(vp->gendev),
2937 sizeof(info->bus_info));
1da177e4 2938 else
68aad78c
RJ		 2939 snprintf(info->bus_info, sizeof(info->bus_info),
2940 "EISA 0x%lx %d", dev->base_addr, dev->irq);
1da177e4
LT		 2941 }
2942}
2943
690a1f20
AS		 2944static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2945{
2946 struct vortex_private *vp = netdev_priv(dev);
2947
3fd6c88e
JB		 2948 if (!VORTEX_PCI(vp))
2949 return;
2950
690a1f20
AS		 2951 wol->supported = WAKE_MAGIC;
2952
2953 wol->wolopts = 0;
2954 if (vp->enable_wol)
2955 wol->wolopts |= WAKE_MAGIC;
690a1f20
AS		 2956}
2957
2958static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2959{
2960 struct vortex_private *vp = netdev_priv(dev);
3fd6c88e
JB		 2961
2962 if (!VORTEX_PCI(vp))
2963 return -EOPNOTSUPP;
2964
690a1f20
AS		 2965 if (wol->wolopts & ~WAKE_MAGIC)
2966 return -EINVAL;
2967
690a1f20
AS		 2968 if (wol->wolopts & WAKE_MAGIC)
2969 vp->enable_wol = 1;
2970 else
2971 vp->enable_wol = 0;
2972 acpi_set_WOL(dev);
690a1f20
AS		 2973
2974 return 0;
2975}
2976
7282d491 2977static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2978 .get_drvinfo = vortex_get_drvinfo,
2979 .get_strings = vortex_get_strings,
2980 .get_msglevel = vortex_get_msglevel,
2981 .set_msglevel = vortex_set_msglevel,
2982 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2983 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2984 .get_settings = vortex_get_settings,
2985 .set_settings = vortex_set_settings,
373a6887 2986 .get_link = ethtool_op_get_link,
1da177e4 2987 .nway_reset = vortex_nway_reset,
690a1f20
AS		 2988 .get_wol = vortex_get_wol,
2989 .set_wol = vortex_set_wol,
1da177e4
LT		 2990};
2991
2992#ifdef CONFIG_PCI
2993/*
2994 * Must power the device up to do MDIO operations
2995 */
2996static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2997{
2998 int err;
2999 struct vortex_private *vp = netdev_priv(dev);
cc2d6596 3000 pci_power_t state = 0;
1da177e4
LT		 3001
3002 if(VORTEX_PCI(vp))
3003 state = VORTEX_PCI(vp)->current_state;
3004
3005 /* The kernel core really should have pci_get_power_state() */
3006
3007 if(state != 0)
3008 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
1da177e4 3009 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
1da177e4
LT		 3010 if(state != 0)
3011 pci_set_power_state(VORTEX_PCI(vp), state);
3012
3013 return err;
3014}
3015#endif
3016
3017
3018/* Pre-Cyclone chips have no documented multicast filter, so the only
3019 multicast setting is to receive all multicast frames. At least
3020 the chip has a very clean way to set the mode, unlike many others. */
3021static void set_rx_mode(struct net_device *dev)
3022{
62afe595
JL		 3023 struct vortex_private *vp = netdev_priv(dev);
3024 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3025 int new_mode;
3026
3027 if (dev->flags & IFF_PROMISC) {
d5b20697 3028 if (vortex_debug > 3)
39738e16 3029 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 3030 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 3031 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 3032 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3033 } else
3034 new_mode = SetRxFilter | RxStation | RxBroadcast;
3035
62afe595 3036 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3037}
3038
3039#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3040/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3041 Note that this must be done after each RxReset due to some backwards
3042 compatibility logic in the Cyclone and Tornado ASICs */
3043
3044/* The Ethernet Type used for 802.1q tagged frames */
3045#define VLAN_ETHER_TYPE 0x8100
3046
3047static void set_8021q_mode(struct net_device *dev, int enable)
3048{
3049 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3050 int mac_ctrl;
3051
3052 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3053 /* cyclone and tornado chipsets can recognize 802.1q
3054 * tagged frames and treat them correctly */
3055
3056 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3057 if (enable)
3058 max_pkt_size += 4; /* 802.1Q VLAN tag */
3059
a095cfc4 3060 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
1da177e4
LT		 3061
3062 /* set VlanEtherType to let the hardware checksumming
3063 treat tagged frames correctly */
a095cfc4 3064 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
1da177e4
LT		 3065 } else {
3066 /* on older cards we have to enable large frames */
3067
3068 vp->large_frames = dev->mtu > 1500 || enable;
3069
a095cfc4 3070 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
1da177e4
LT		 3071 if (vp->large_frames)
3072 mac_ctrl |= 0x40;
3073 else
3074 mac_ctrl &= ~0x40;
a095cfc4 3075 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
1da177e4 3076 }
1da177e4
LT		 3077}
3078#else
3079
3080static void set_8021q_mode(struct net_device *dev, int enable)
3081{
3082}
3083
3084
3085#endif
3086
3087/* MII transceiver control section.
3088 Read and write the MII registers using software-generated serial
3089 MDIO protocol. See the MII specifications or DP83840A data sheet
3090 for details. */
3091
3092/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3093 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3094 "overclocking" issues. */
a095cfc4
BH		 3095static void mdio_delay(struct vortex_private *vp)
3096{
3097 window_read32(vp, 4, Wn4_PhysicalMgmt);
3098}
1da177e4
LT		 3099
3100#define MDIO_SHIFT_CLK 0x01
3101#define MDIO_DIR_WRITE 0x04
3102#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3103#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3104#define MDIO_DATA_READ 0x02
3105#define MDIO_ENB_IN 0x00
3106
3107/* Generate the preamble required for initial synchronization and
3108 a few older transceivers. */
a095cfc4 3109static void mdio_sync(struct vortex_private *vp, int bits)
1da177e4 3110{
1da177e4
LT		 3111 /* Establish sync by sending at least 32 logic ones. */
3112 while (-- bits >= 0) {
a095cfc4
BH		 3113 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3114 mdio_delay(vp);
3115 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3116 4, Wn4_PhysicalMgmt);
3117 mdio_delay(vp);
1da177e4
LT		 3118 }
3119}
3120
3121static int mdio_read(struct net_device *dev, int phy_id, int location)
3122{
3123 int i;
62afe595 3124 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3125 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3126 unsigned int retval = 0;
1da177e4 3127
de847272
BH		 3128 spin_lock_bh(&vp->mii_lock);
3129
1da177e4 3130 if (mii_preamble_required)
a095cfc4 3131 mdio_sync(vp, 32);
1da177e4
LT		 3132
3133 /* Shift the read command bits out. */
3134 for (i = 14; i >= 0; i--) {
3135 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3136 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3137 mdio_delay(vp);
3138 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3139 4, Wn4_PhysicalMgmt);
3140 mdio_delay(vp);
1da177e4
LT		 3141 }
3142 /* Read the two transition, 16 data, and wire-idle bits. */
3143 for (i = 19; i > 0; i--) {
a095cfc4
BH		 3144 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3145 mdio_delay(vp);
3146 retval = (retval << 1) |
3147 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3148 MDIO_DATA_READ) ? 1 : 0);
3149 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3150 4, Wn4_PhysicalMgmt);
3151 mdio_delay(vp);
1da177e4 3152 }
de847272
BH		 3153
3154 spin_unlock_bh(&vp->mii_lock);
3155
1da177e4
LT		 3156 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3157}
3158
3159static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3160{
62afe595 3161 struct vortex_private *vp = netdev_priv(dev);
1da177e4 3162 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
1da177e4
LT		 3163 int i;
3164
de847272
BH		 3165 spin_lock_bh(&vp->mii_lock);
3166
1da177e4 3167 if (mii_preamble_required)
a095cfc4 3168 mdio_sync(vp, 32);
1da177e4
LT		 3169
3170 /* Shift the command bits out. */
3171 for (i = 31; i >= 0; i--) {
3172 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3173 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3174 mdio_delay(vp);
3175 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3176 4, Wn4_PhysicalMgmt);
3177 mdio_delay(vp);
1da177e4
LT		 3178 }
3179 /* Leave the interface idle. */
3180 for (i = 1; i >= 0; i--) {
a095cfc4
BH		 3181 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3182 mdio_delay(vp);
3183 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3184 4, Wn4_PhysicalMgmt);
3185 mdio_delay(vp);
1da177e4 3186 }
de847272
BH		 3187
3188 spin_unlock_bh(&vp->mii_lock);
1da177e4 3189}
a880c4cd 3190
1da177e4
LT		 3191/* ACPI: Advanced Configuration and Power Interface. */
3192/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3193static void acpi_set_WOL(struct net_device *dev)
3194{
3195 struct vortex_private *vp = netdev_priv(dev);
62afe595 3196 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3197
c17931c5
SK		 3198 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3199
1da177e4
LT		 3200 if (vp->enable_wol) {
3201 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
a095cfc4 3202 window_write16(vp, 2, 7, 0x0c);
1da177e4 3203 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3204 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3205 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3206
1a1769f3 3207 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3208 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3209
3210 vp->enable_wol = 0;
3211 return;
3212 }
3c8fad18 3213
3fd6c88e
JB		 3214 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3215 return;
3216
3c8fad18
DR		 3217 /* Change the power state to D3; RxEnable doesn't take effect. */
3218 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3219 }
1da177e4
LT		 3220}
3221
3222
3f6db0f3 3223static void vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3224{
3225 struct net_device *dev = pci_get_drvdata(pdev);
3226 struct vortex_private *vp;
3227
3228 if (!dev) {
39738e16 3229 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3230 BUG();
3231 }
3232
3233 vp = netdev_priv(dev);
3234
62afe595
JL		 3235 if (vp->cb_fn_base)
3236 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3237
1da177e4
LT		 3238 unregister_netdev(dev);
3239
3240 if (VORTEX_PCI(vp)) {
3241 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3242 if (vp->pm_state_valid)
3243 pci_restore_state(VORTEX_PCI(vp));
3244 pci_disable_device(VORTEX_PCI(vp));
3245 }
3246 /* Should really use issue_and_wait() here */
62afe595
JL		 3247 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3248 vp->ioaddr + EL3_CMD);
3249
3250 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3251
3252 pci_free_consistent(pdev,
3253 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3254 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3255 vp->rx_ring,
3256 vp->rx_ring_dma);
4b264a16
SS		 3257
3258 pci_release_regions(pdev);
3259
1da177e4
LT		 3260 free_netdev(dev);
3261}
3262
3263
3264static struct pci_driver vortex_driver = {
3265 .name = "3c59x",
3266 .probe = vortex_init_one,
3f6db0f3 3267 .remove = vortex_remove_one,
1da177e4 3268 .id_table = vortex_pci_tbl,
7bfc4ab5 3269 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3270};
3271
3272
3273static int vortex_have_pci;
3274static int vortex_have_eisa;
3275
3276
a880c4cd 3277static int __init vortex_init(void)
1da177e4
LT		 3278{
3279 int pci_rc, eisa_rc;
3280
29917620 3281 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3282 eisa_rc = vortex_eisa_init();
3283
3284 if (pci_rc == 0)
3285 vortex_have_pci = 1;
3286 if (eisa_rc > 0)
3287 vortex_have_eisa = 1;
3288
3289 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3290}
3291
3292
a880c4cd 3293static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3294{
3295 struct vortex_private *vp;
62afe595 3296 void __iomem *ioaddr;
1da177e4
LT		 3297
3298#ifdef CONFIG_EISA
3299 /* Take care of the EISA devices */
a880c4cd 3300 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3301#endif
6aa20a22 3302
1da177e4 3303 if (compaq_net_device) {
454d7c9b 3304 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3305 ioaddr = ioport_map(compaq_net_device->base_addr,
3306 VORTEX_TOTAL_SIZE);
1da177e4 3307
a880c4cd
SK		 3308 unregister_netdev(compaq_net_device);
3309 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3310 release_region(compaq_net_device->base_addr,
3311 VORTEX_TOTAL_SIZE);
1da177e4 3312
a880c4cd 3313 free_netdev(compaq_net_device);
1da177e4
LT		 3314 }
3315}
3316
3317
a880c4cd 3318static void __exit vortex_cleanup(void)
1da177e4
LT		 3319{
3320 if (vortex_have_pci)
a880c4cd 3321 pci_unregister_driver(&vortex_driver);
1da177e4 3322 if (vortex_have_eisa)
a880c4cd 3323 vortex_eisa_cleanup();
1da177e4
LT		 3324}
3325
3326
3327module_init(vortex_init);
3328module_exit(vortex_cleanup);
Linux kernel - Deliverables
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