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[deliverable/linux.git] / drivers / net / ethernet / 3com / 3c59x.c
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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
1da177e4
LT		 438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
cc2d6596
AV		 544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
cc2d6596
AV		 564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 566#if DO_ZEROCOPY
567 struct {
cc2d6596
AV		 568 __le32 addr;
569 __le32 length;
1da177e4
LT		 570 } frag[1+MAX_SKB_FRAGS];
571#else
cc2d6596
AV		 572 __le32 addr;
573 __le32 length;
1da177e4
LT		 574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
8d1d0340
SK		 588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
1da177e4
LT		 593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
62afe595
JL		 612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 625 full_duplex:1, autoselect:1,
1da177e4
LT		 626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
aa25ab7d
NH		 636 large_frames:1, /* accept large frames */
637 handling_irq:1; /* private in_irq indicator */
84176b7b
DK		 638 /* {get|set}_wol operations are already serialized by rtnl.
639 * no additional locking is required for the enable_wol and acpi_set_WOL()
640 */
1da177e4
LT		 641 int drv_flags;
642 u16 status_enable;
643 u16 intr_enable;
644 u16 available_media; /* From Wn3_Options. */
645 u16 capabilities, info1, info2; /* Various, from EEPROM. */
646 u16 advertising; /* NWay media advertisement */
647 unsigned char phys[2]; /* MII device addresses. */
648 u16 deferred; /* Resend these interrupts when we
649 * bale from the ISR */
650 u16 io_size; /* Size of PCI region (for release_region) */
de847272
BH		 651
652 /* Serialises access to hardware other than MII and variables below.
24cd804d 653 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
de847272
BH		 654 spinlock_t lock;
655
656 spinlock_t mii_lock; /* Serialises access to MII */
657 struct mii_if_info mii; /* MII lib hooks/info */
658 spinlock_t window_lock; /* Serialises access to windowed regs */
659 int window; /* Register window */
1da177e4
LT		 660};
661
a095cfc4
BH		 662static void window_set(struct vortex_private *vp, int window)
663{
664 if (window != vp->window) {
665 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
666 vp->window = window;
667 }
668}
669
670#define DEFINE_WINDOW_IO(size) \
671static u ## size \
672window_read ## size(struct vortex_private *vp, int window, int addr) \
673{ \
de847272
BH		 674 unsigned long flags; \
675 u ## size ret; \
676 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4 677 window_set(vp, window); \
de847272
BH		 678 ret = ioread ## size(vp->ioaddr + addr); \
679 spin_unlock_irqrestore(&vp->window_lock, flags); \
680 return ret; \
a095cfc4
BH		 681} \
682static void \
683window_write ## size(struct vortex_private *vp, u ## size value, \
684 int window, int addr) \
685{ \
de847272
BH		 686 unsigned long flags; \
687 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4
BH		 688 window_set(vp, window); \
689 iowrite ## size(value, vp->ioaddr + addr); \
de847272 690 spin_unlock_irqrestore(&vp->window_lock, flags); \
a095cfc4
BH		 691}
692DEFINE_WINDOW_IO(8)
693DEFINE_WINDOW_IO(16)
694DEFINE_WINDOW_IO(32)
695
1da177e4
LT		 696#ifdef CONFIG_PCI
697#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
698#else
699#define DEVICE_PCI(dev) NULL
700#endif
701
d530db0d
NK		 702#define VORTEX_PCI(vp) \
703 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
1da177e4
LT		 704
705#ifdef CONFIG_EISA
706#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
707#else
708#define DEVICE_EISA(dev) NULL
709#endif
710
d530db0d
NK		 711#define VORTEX_EISA(vp) \
712 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
1da177e4
LT		 713
714/* The action to take with a media selection timer tick.
715 Note that we deviate from the 3Com order by checking 10base2 before AUI.
716 */
717enum xcvr_types {
718 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
719 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
720};
721
f71e1309 722static const struct media_table {
1da177e4
LT		 723 char *name;
724 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
725 mask:8, /* The transceiver-present bit in Wn3_Config.*/
726 next:8; /* The media type to try next. */
727 int wait; /* Time before we check media status. */
728} media_tbl[] = {
729 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
730 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
731 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
732 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
733 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
734 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
735 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
736 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
737 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
738 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
739 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
740};
741
742static struct {
743 const char str[ETH_GSTRING_LEN];
744} ethtool_stats_keys[] = {
745 { "tx_deferred" },
8d1d0340 746 { "tx_max_collisions" },
1da177e4 747 { "tx_multiple_collisions" },
8d1d0340 748 { "tx_single_collisions" },
1da177e4
LT		 749 { "rx_bad_ssd" },
750};
751
752/* number of ETHTOOL_GSTATS u64's */
8d1d0340 753#define VORTEX_NUM_STATS 5
1da177e4 754
62afe595 755static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 756 int chip_idx, int card_idx);
c8303d10 757static int vortex_up(struct net_device *dev);
1da177e4
LT		 758static void vortex_down(struct net_device *dev, int final);
759static int vortex_open(struct net_device *dev);
a095cfc4 760static void mdio_sync(struct vortex_private *vp, int bits);
1da177e4
LT		 761static int mdio_read(struct net_device *dev, int phy_id, int location);
762static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
763static void vortex_timer(unsigned long arg);
764static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 765static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
766 struct net_device *dev);
767static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
768 struct net_device *dev);
1da177e4
LT		 769static int vortex_rx(struct net_device *dev);
770static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 771static irqreturn_t vortex_interrupt(int irq, void *dev_id);
772static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 773static int vortex_close(struct net_device *dev);
774static void dump_tx_ring(struct net_device *dev);
62afe595 775static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 776static struct net_device_stats *vortex_get_stats(struct net_device *dev);
777static void set_rx_mode(struct net_device *dev);
778#ifdef CONFIG_PCI
779static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
780#endif
781static void vortex_tx_timeout(struct net_device *dev);
782static void acpi_set_WOL(struct net_device *dev);
7282d491 783static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 784static void set_8021q_mode(struct net_device *dev, int enable);
785
1da177e4
LT		 786/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
787/* Option count limit only -- unlimited interfaces are supported. */
788#define MAX_UNITS 8
9954ab7f
JL		 789static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
790static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 794static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 795static int global_options = -1;
796static int global_full_duplex = -1;
797static int global_enable_wol = -1;
900fd17d 798static int global_use_mmio = -1;
1da177e4 799
1da177e4
LT		 800/* Variables to work-around the Compaq PCI BIOS32 problem. */
801static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
802static struct net_device *compaq_net_device;
803
804static int vortex_cards_found;
805
806module_param(debug, int, 0);
807module_param(global_options, int, 0);
808module_param_array(options, int, NULL, 0);
809module_param(global_full_duplex, int, 0);
810module_param_array(full_duplex, int, NULL, 0);
811module_param_array(hw_checksums, int, NULL, 0);
812module_param_array(flow_ctrl, int, NULL, 0);
813module_param(global_enable_wol, int, 0);
814module_param_array(enable_wol, int, NULL, 0);
815module_param(rx_copybreak, int, 0);
816module_param(max_interrupt_work, int, 0);
817module_param(compaq_ioaddr, int, 0);
818module_param(compaq_irq, int, 0);
819module_param(compaq_device_id, int, 0);
820module_param(watchdog, int, 0);
900fd17d
JL		 821module_param(global_use_mmio, int, 0);
822module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 823MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
824MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
825MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
826MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 827MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 828MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
829MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
830MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 831MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 832MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
833MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
834MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
835MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
836MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
837MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 838MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
839MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 840
841#ifdef CONFIG_NET_POLL_CONTROLLER
842static void poll_vortex(struct net_device *dev)
843{
844 struct vortex_private *vp = netdev_priv(dev);
845 unsigned long flags;
0d38ff1d 846 local_irq_save(flags);
7d12e780 847 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 848 local_irq_restore(flags);
6aa20a22 849}
1da177e4
LT		 850#endif
851
852#ifdef CONFIG_PM
853
7bfc4ab5 854static int vortex_suspend(struct device *dev)
1da177e4 855{
7bfc4ab5
AV		 856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct net_device *ndev = pci_get_drvdata(pdev);
858
859 if (!ndev || !netif_running(ndev))
860 return 0;
861
862 netif_device_detach(ndev);
863 vortex_down(ndev, 1);
1da177e4 864
1da177e4
LT		 865 return 0;
866}
867
7bfc4ab5 868static int vortex_resume(struct device *dev)
1da177e4 869{
7bfc4ab5
AV		 870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 872 int err;
1da177e4 873
7bfc4ab5
AV		 874 if (!ndev || !netif_running(ndev))
875 return 0;
876
877 err = vortex_up(ndev);
878 if (err)
879 return err;
880
881 netif_device_attach(ndev);
882
1da177e4
LT		 883 return 0;
884}
885
47145210 886static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 887 .suspend = vortex_suspend,
888 .resume = vortex_resume,
889 .freeze = vortex_suspend,
890 .thaw = vortex_resume,
891 .poweroff = vortex_suspend,
892 .restore = vortex_resume,
893};
894
895#define VORTEX_PM_OPS (&vortex_pm_ops)
896
897#else /* !CONFIG_PM */
898
899#define VORTEX_PM_OPS NULL
900
901#endif /* !CONFIG_PM */
1da177e4
LT		 902
903#ifdef CONFIG_EISA
948252cb 904static struct eisa_device_id vortex_eisa_ids[] = {
1da177e4
LT		 905 { "TCM5920", CH_3C592 },
906 { "TCM5970", CH_3C597 },
907 { "" }
908};
07563c71 909MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 910
948252cb 911static int __init vortex_eisa_probe(struct device *device)
1da177e4 912{
62afe595 913 void __iomem *ioaddr;
1da177e4
LT		 914 struct eisa_device *edev;
915
a880c4cd 916 edev = to_eisa_device(device);
1da177e4 917
62afe595 918 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 919 return -EBUSY;
920
62afe595
JL		 921 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
922
923 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 924 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 925 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 926 return -ENODEV;
927 }
928
929 vortex_cards_found++;
930
931 return 0;
932}
933
95c408a9 934static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 935{
936 struct eisa_device *edev;
937 struct net_device *dev;
938 struct vortex_private *vp;
62afe595 939 void __iomem *ioaddr;
1da177e4 940
a880c4cd
SK		 941 edev = to_eisa_device(device);
942 dev = eisa_get_drvdata(edev);
1da177e4
LT		 943
944 if (!dev) {
39738e16 945 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 946 BUG();
947 }
948
949 vp = netdev_priv(dev);
62afe595 950 ioaddr = vp->ioaddr;
6aa20a22 951
a880c4cd
SK		 952 unregister_netdev(dev);
953 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
954 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 955
a880c4cd 956 free_netdev(dev);
1da177e4
LT		 957 return 0;
958}
95c408a9
RB		 959
960static struct eisa_driver vortex_eisa_driver = {
961 .id_table = vortex_eisa_ids,
962 .driver = {
963 .name = "3c59x",
964 .probe = vortex_eisa_probe,
965 .remove = __devexit_p(vortex_eisa_remove)
966 }
967};
968
969#endif /* CONFIG_EISA */
1da177e4
LT		 970
971/* returns count found (>= 0), or negative on error */
a880c4cd 972static int __init vortex_eisa_init(void)
1da177e4
LT		 973{
974 int eisa_found = 0;
975 int orig_cards_found = vortex_cards_found;
976
977#ifdef CONFIG_EISA
c2f6fabb
BH		 978 int err;
979
980 err = eisa_driver_register (&vortex_eisa_driver);
981 if (!err) {
982 /*
983 * Because of the way EISA bus is probed, we cannot assume
984 * any device have been found when we exit from
985 * eisa_driver_register (the bus root driver may not be
986 * initialized yet). So we blindly assume something was
25985edc 987 * found, and let the sysfs magic happened...
c2f6fabb
BH		 988 */
989 eisa_found = 1;
1da177e4
LT		 990 }
991#endif
6aa20a22 992
1da177e4
LT		 993 /* Special code to work-around the Compaq PCI BIOS32 problem. */
994 if (compaq_ioaddr) {
62afe595
JL		 995 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
996 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 997 }
998
999 return vortex_cards_found - orig_cards_found + eisa_found;
1000}
1001
1002/* returns count (>= 0), or negative on error */
a880c4cd 1003static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 1004 const struct pci_device_id *ent)
1005{
900fd17d
JL		 1006 int rc, unit, pci_bar;
1007 struct vortex_chip_info *vci;
1008 void __iomem *ioaddr;
1da177e4 1009
6aa20a22 1010 /* wake up and enable device */
a880c4cd 1011 rc = pci_enable_device(pdev);
1da177e4
LT		 1012 if (rc < 0)
1013 goto out;
1014
900fd17d
JL		 1015 unit = vortex_cards_found;
1016
1017 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1018 /* Determine the default if the user didn't override us */
1019 vci = &vortex_info_tbl[ent->driver_data];
1020 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1021 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1022 pci_bar = use_mmio[unit] ? 1 : 0;
1023 else
1024 pci_bar = global_use_mmio ? 1 : 0;
1025
1026 ioaddr = pci_iomap(pdev, pci_bar, 0);
1027 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1028 ioaddr = pci_iomap(pdev, 0, 0);
8cd47ea1
KV		 1029 if (!ioaddr) {
1030 pci_disable_device(pdev);
1031 rc = -ENOMEM;
1032 goto out;
1033 }
900fd17d
JL		 1034
1035 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1036 ent->driver_data, unit);
1da177e4 1037 if (rc < 0) {
f89f5d0e 1038 pci_iounmap(pdev, ioaddr);
a880c4cd 1039 pci_disable_device(pdev);
1da177e4
LT		 1040 goto out;
1041 }
1042
1043 vortex_cards_found++;
1044
1045out:
1046 return rc;
1047}
1048
48b47a5e
SH		 1049static const struct net_device_ops boomrang_netdev_ops = {
1050 .ndo_open = vortex_open,
1051 .ndo_stop = vortex_close,
1052 .ndo_start_xmit = boomerang_start_xmit,
1053 .ndo_tx_timeout = vortex_tx_timeout,
1054 .ndo_get_stats = vortex_get_stats,
1055#ifdef CONFIG_PCI
1056 .ndo_do_ioctl = vortex_ioctl,
1057#endif
afc4b13d 1058 .ndo_set_rx_mode = set_rx_mode,
48b47a5e
SH		 1059 .ndo_change_mtu = eth_change_mtu,
1060 .ndo_set_mac_address = eth_mac_addr,
1061 .ndo_validate_addr = eth_validate_addr,
1062#ifdef CONFIG_NET_POLL_CONTROLLER
1063 .ndo_poll_controller = poll_vortex,
1064#endif
1065};
1066
1067static const struct net_device_ops vortex_netdev_ops = {
1068 .ndo_open = vortex_open,
1069 .ndo_stop = vortex_close,
1070 .ndo_start_xmit = vortex_start_xmit,
1071 .ndo_tx_timeout = vortex_tx_timeout,
1072 .ndo_get_stats = vortex_get_stats,
1073#ifdef CONFIG_PCI
1074 .ndo_do_ioctl = vortex_ioctl,
1075#endif
afc4b13d 1076 .ndo_set_rx_mode = set_rx_mode,
48b47a5e
SH		 1077 .ndo_change_mtu = eth_change_mtu,
1078 .ndo_set_mac_address = eth_mac_addr,
1079 .ndo_validate_addr = eth_validate_addr,
1080#ifdef CONFIG_NET_POLL_CONTROLLER
1081 .ndo_poll_controller = poll_vortex,
1082#endif
1083};
1084
1da177e4
LT		 1085/*
1086 * Start up the PCI/EISA device which is described by *gendev.
1087 * Return 0 on success.
1088 *
1089 * NOTE: pdev can be NULL, for the case of a Compaq device
1090 */
1091static int __devinit vortex_probe1(struct device *gendev,
62afe595 1092 void __iomem *ioaddr, int irq,
1da177e4
LT		 1093 int chip_idx, int card_idx)
1094{
1095 struct vortex_private *vp;
1096 int option;
1097 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1098 int i, step;
1099 struct net_device *dev;
1100 static int printed_version;
1101 int retval, print_info;
1102 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1103 const char *print_name = "3c59x";
1da177e4
LT		 1104 struct pci_dev *pdev = NULL;
1105 struct eisa_device *edev = NULL;
1106
1107 if (!printed_version) {
39738e16 1108 pr_info("%s", version);
1da177e4
LT		 1109 printed_version = 1;
1110 }
1111
1112 if (gendev) {
1113 if ((pdev = DEVICE_PCI(gendev))) {
1114 print_name = pci_name(pdev);
1115 }
1116
1117 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1118 print_name = dev_name(&edev->dev);
1da177e4
LT		 1119 }
1120 }
1121
1122 dev = alloc_etherdev(sizeof(*vp));
1123 retval = -ENOMEM;
1124 if (!dev) {
39738e16 1125 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1126 goto out;
1127 }
1da177e4
LT		 1128 SET_NETDEV_DEV(dev, gendev);
1129 vp = netdev_priv(dev);
1130
1131 option = global_options;
1132
1133 /* The lower four bits are the media type. */
1134 if (dev->mem_start) {
1135 /*
1136 * The 'options' param is passed in as the third arg to the
1137 * LILO 'ether=' argument for non-modular use
1138 */
1139 option = dev->mem_start;
1140 }
1141 else if (card_idx < MAX_UNITS) {
1142 if (options[card_idx] >= 0)
1143 option = options[card_idx];
1144 }
1145
1146 if (option > 0) {
1147 if (option & 0x8000)
1148 vortex_debug = 7;
1149 if (option & 0x4000)
1150 vortex_debug = 2;
1151 if (option & 0x0400)
1152 vp->enable_wol = 1;
1153 }
1154
1155 print_info = (vortex_debug > 1);
1156 if (print_info)
39738e16 1157 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1158
39738e16 1159 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1160 print_name,
1161 pdev ? "PCI" : "EISA",
1162 vci->name,
1163 ioaddr);
1164
62afe595 1165 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1166 dev->irq = irq;
1167 dev->mtu = mtu;
62afe595 1168 vp->ioaddr = ioaddr;
1da177e4
LT		 1169 vp->large_frames = mtu > 1500;
1170 vp->drv_flags = vci->drv_flags;
1171 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1172 vp->io_size = vci->io_size;
1173 vp->card_idx = card_idx;
a095cfc4 1174 vp->window = -1;
1da177e4
LT		 1175
1176 /* module list only for Compaq device */
1177 if (gendev == NULL) {
1178 compaq_net_device = dev;
1179 }
1180
1181 /* PCI-only startup logic */
1182 if (pdev) {
1183 /* EISA resources already marked, so only PCI needs to do this here */
1184 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1185 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1186 vp->must_free_region = 1;
1187
6aa20a22 1188 /* enable bus-mastering if necessary */
1da177e4 1189 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1190 pci_set_master(pdev);
1da177e4
LT		 1191
1192 if (vci->drv_flags & IS_VORTEX) {
1193 u8 pci_latency;
1194 u8 new_latency = 248;
1195
1196 /* Check the PCI latency value. On the 3c590 series the latency timer
1197 must be set to the maximum value to avoid data corruption that occurs
1198 when the timer expires during a transfer. This bug exists the Vortex
1199 chip only. */
1200 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1201 if (pci_latency < new_latency) {
39738e16 1202 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1203 print_name, pci_latency, new_latency);
39738e16 1204 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1205 }
1206 }
1207 }
1208
1209 spin_lock_init(&vp->lock);
de847272
BH		 1210 spin_lock_init(&vp->mii_lock);
1211 spin_lock_init(&vp->window_lock);
1da177e4
LT		 1212 vp->gendev = gendev;
1213 vp->mii.dev = dev;
1214 vp->mii.mdio_read = mdio_read;
1215 vp->mii.mdio_write = mdio_write;
1216 vp->mii.phy_id_mask = 0x1f;
1217 vp->mii.reg_num_mask = 0x1f;
1218
1219 /* Makes sure rings are at least 16 byte aligned. */
1220 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1221 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1222 &vp->rx_ring_dma);
1223 retval = -ENOMEM;
cc2d6596 1224 if (!vp->rx_ring)
1da177e4
LT		 1225 goto free_region;
1226
1227 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1228 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1229
1230 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1231 * instead of a module list */
1da177e4
LT		 1232 if (pdev)
1233 pci_set_drvdata(pdev, dev);
1234 if (edev)
a880c4cd 1235 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1236
1237 vp->media_override = 7;
1238 if (option >= 0) {
1239 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1240 if (vp->media_override != 7)
1241 vp->medialock = 1;
1242 vp->full_duplex = (option & 0x200) ? 1 : 0;
1243 vp->bus_master = (option & 16) ? 1 : 0;
1244 }
1245
1246 if (global_full_duplex > 0)
1247 vp->full_duplex = 1;
1248 if (global_enable_wol > 0)
1249 vp->enable_wol = 1;
1250
1251 if (card_idx < MAX_UNITS) {
1252 if (full_duplex[card_idx] > 0)
1253 vp->full_duplex = 1;
1254 if (flow_ctrl[card_idx] > 0)
1255 vp->flow_ctrl = 1;
1256 if (enable_wol[card_idx] > 0)
1257 vp->enable_wol = 1;
1258 }
1259
125d5ce8 1260 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1261 vp->options = option;
1262 /* Read the station address from the EEPROM. */
1da177e4
LT		 1263 {
1264 int base;
1265
1266 if (vci->drv_flags & EEPROM_8BIT)
1267 base = 0x230;
1268 else if (vci->drv_flags & EEPROM_OFFSET)
1269 base = EEPROM_Read + 0x30;
1270 else
1271 base = EEPROM_Read;
1272
1273 for (i = 0; i < 0x40; i++) {
1274 int timer;
a095cfc4 1275 window_write16(vp, base + i, 0, Wn0EepromCmd);
1da177e4
LT		 1276 /* Pause for at least 162 us. for the read to take place. */
1277 for (timer = 10; timer >= 0; timer--) {
1278 udelay(162);
a095cfc4
BH		 1279 if ((window_read16(vp, 0, Wn0EepromCmd) &
1280 0x8000) == 0)
1da177e4
LT		 1281 break;
1282 }
a095cfc4 1283 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1da177e4
LT		 1284 }
1285 }
1286 for (i = 0; i < 0x18; i++)
1287 checksum ^= eeprom[i];
1288 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1289 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1290 while (i < 0x21)
1291 checksum ^= eeprom[i++];
1292 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1293 }
1294 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1295 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1296 for (i = 0; i < 3; i++)
cc2d6596 1297 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1298 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1299 if (print_info)
39738e16 1300 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1301 /* Unfortunately an all zero eeprom passes the checksum and this
1302 gets found in the wild in failure cases. Crypto is hard 8) */
1303 if (!is_valid_ether_addr(dev->dev_addr)) {
1304 retval = -EINVAL;
39738e16 1305 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1306 goto free_ring; /* With every pack */
1307 }
1da177e4 1308 for (i = 0; i < 6; i++)
a095cfc4 1309 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1310
1da177e4 1311 if (print_info)
39738e16 1312 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1313 /* Tell them about an invalid IRQ. */
60e4ad7a 1314 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1315 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1316 dev->irq);
1da177e4 1317
a095cfc4 1318 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1319 if (print_info) {
39738e16
AB		 1320 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1321 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1322 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1323 }
1324
1325
1326 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1327 unsigned short n;
1328
62afe595
JL		 1329 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1330 if (!vp->cb_fn_base) {
1da177e4 1331 retval = -ENOMEM;
62afe595 1332 goto free_ring;
1da177e4 1333 }
62afe595 1334
1da177e4 1335 if (print_info) {
39738e16 1336 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1337 print_name,
1338 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1339 vp->cb_fn_base);
1da177e4 1340 }
1da177e4 1341
a095cfc4 1342 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1343 if (vp->drv_flags & INVERT_LED_PWR)
1344 n |= 0x10;
1345 if (vp->drv_flags & INVERT_MII_PWR)
1346 n |= 0x4000;
a095cfc4 1347 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4 1348 if (vp->drv_flags & WNO_XCVR_PWR) {
a095cfc4 1349 window_write16(vp, 0x0800, 0, 0);
1da177e4
LT		 1350 }
1351 }
1352
1353 /* Extract our information from the EEPROM data. */
1354 vp->info1 = eeprom[13];
1355 vp->info2 = eeprom[15];
1356 vp->capabilities = eeprom[16];
1357
1358 if (vp->info1 & 0x8000) {
1359 vp->full_duplex = 1;
1360 if (print_info)
39738e16 1361 pr_info("Full duplex capable\n");
1da177e4
LT		 1362 }
1363
1364 {
f71e1309 1365 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4 1366 unsigned int config;
a095cfc4 1367 vp->available_media = window_read16(vp, 3, Wn3_Options);
1da177e4
LT		 1368 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1369 vp->available_media = 0x40;
a095cfc4 1370 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1371 if (print_info) {
39738e16 1372 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
a095cfc4 1373 config, window_read16(vp, 3, Wn3_Options));
39738e16 1374 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1375 8 << RAM_SIZE(config),
1376 RAM_WIDTH(config) ? "word" : "byte",
1377 ram_split[RAM_SPLIT(config)],
1378 AUTOSELECT(config) ? "autoselect/" : "",
1379 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1380 media_tbl[XCVR(config)].name);
1381 }
1382 vp->default_media = XCVR(config);
1383 if (vp->default_media == XCVR_NWAY)
1384 vp->has_nway = 1;
1385 vp->autoselect = AUTOSELECT(config);
1386 }
1387
1388 if (vp->media_override != 7) {
39738e16 1389 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1390 print_name, vp->media_override,
1391 media_tbl[vp->media_override].name);
1392 dev->if_port = vp->media_override;
1393 } else
1394 dev->if_port = vp->default_media;
1395
1396 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1397 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1398 int phy, phy_idx = 0;
1da177e4
LT		 1399 mii_preamble_required++;
1400 if (vp->drv_flags & EXTRA_PREAMBLE)
1401 mii_preamble_required++;
344e0f62 1402 mdio_sync(vp, 32);
106427e6 1403 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1404 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1405 int mii_status, phyx;
1406
1407 /*
1408 * For the 3c905CX we look at index 24 first, because it bogusly
1409 * reports an external PHY at all indices
1410 */
1411 if (phy == 0)
1412 phyx = 24;
1413 else if (phy <= 24)
1414 phyx = phy - 1;
1415 else
1416 phyx = phy;
106427e6 1417 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1418 if (mii_status && mii_status != 0xffff) {
1419 vp->phys[phy_idx++] = phyx;
1420 if (print_info) {
39738e16
AB		 1421 pr_info(" MII transceiver found at address %d, status %4x.\n",
1422 phyx, mii_status);
1da177e4
LT		 1423 }
1424 if ((mii_status & 0x0040) == 0)
1425 mii_preamble_required++;
1426 }
1427 }
1428 mii_preamble_required--;
1429 if (phy_idx == 0) {
39738e16 1430 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1431 vp->phys[0] = 24;
1432 } else {
106427e6 1433 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1434 if (vp->full_duplex) {
1435 /* Only advertise the FD media types. */
1436 vp->advertising &= ~0x02A0;
1437 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 }
1439 }
1440 vp->mii.phy_id = vp->phys[0];
1441 }
1442
1443 if (vp->capabilities & CapBusMaster) {
1444 vp->full_bus_master_tx = 1;
1445 if (print_info) {
39738e16 1446 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1447 (vp->info2 & 1) ? "early" : "whole-frame" );
1448 }
1449 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1450 vp->bus_master = 0; /* AKPM: vortex only */
1451 }
1452
1453 /* The 3c59x-specific entries in the device structure. */
1da177e4 1454 if (vp->full_bus_master_tx) {
48b47a5e 1455 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1456 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1457 if (card_idx < MAX_UNITS &&
1458 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1459 hw_checksums[card_idx] == 1)) {
d311b0d3 1460 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1461 }
48b47a5e
SH		 1462 } else
1463 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1464
1465 if (print_info) {
39738e16 1466 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1467 print_name,
1468 (dev->features & NETIF_F_SG) ? "en":"dis",
1469 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1470 }
1471
1da177e4 1472 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1473 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1474
1da177e4
LT		 1475 if (pdev) {
1476 vp->pm_state_valid = 1;
1477 pci_save_state(VORTEX_PCI(vp));
1478 acpi_set_WOL(dev);
1479 }
1480 retval = register_netdev(dev);
1481 if (retval == 0)
1482 return 0;
1483
1484free_ring:
1485 pci_free_consistent(pdev,
1486 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1487 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1488 vp->rx_ring,
1489 vp->rx_ring_dma);
1490free_region:
1491 if (vp->must_free_region)
62afe595 1492 release_region(dev->base_addr, vci->io_size);
1da177e4 1493 free_netdev(dev);
39738e16 1494 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1495out:
1496 return retval;
1497}
1498
1499static void
1500issue_and_wait(struct net_device *dev, int cmd)
1501{
62afe595
JL		 1502 struct vortex_private *vp = netdev_priv(dev);
1503 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1504 int i;
1505
62afe595 1506 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1507 for (i = 0; i < 2000; i++) {
62afe595 1508 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1509 return;
1510 }
1511
1512 /* OK, that didn't work. Do it the slow way. One second */
1513 for (i = 0; i < 100000; i++) {
62afe595 1514 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1515 if (vortex_debug > 1)
39738e16 1516 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1517 dev->name, cmd, i * 10);
1518 return;
1519 }
1520 udelay(10);
1521 }
39738e16 1522 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1523 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1524}
1525
125d5ce8
SK		 1526static void
1527vortex_set_duplex(struct net_device *dev)
1528{
1529 struct vortex_private *vp = netdev_priv(dev);
125d5ce8 1530
39738e16 1531 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1532 dev->name, (vp->full_duplex) ? "full" : "half");
1533
125d5ce8 1534 /* Set the full-duplex bit. */
a095cfc4
BH		 1535 window_write16(vp,
1536 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1537 (vp->large_frames ? 0x40 : 0) |
1538 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1539 0x100 : 0),
1540 3, Wn3_MAC_Ctrl);
125d5ce8
SK		 1541}
1542
1543static void vortex_check_media(struct net_device *dev, unsigned int init)
1544{
1545 struct vortex_private *vp = netdev_priv(dev);
1546 unsigned int ok_to_print = 0;
1547
1548 if (vortex_debug > 3)
1549 ok_to_print = 1;
1550
1551 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1552 vp->full_duplex = vp->mii.full_duplex;
1553 vortex_set_duplex(dev);
1554 } else if (init) {
1555 vortex_set_duplex(dev);
1556 }
1557}
1558
c8303d10 1559static int
1da177e4
LT		 1560vortex_up(struct net_device *dev)
1561{
1da177e4 1562 struct vortex_private *vp = netdev_priv(dev);
62afe595 1563 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1564 unsigned int config;
0280f9f9 1565 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1566
1567 if (VORTEX_PCI(vp)) {
1568 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1569 if (vp->pm_state_valid)
1570 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1571 err = pci_enable_device(VORTEX_PCI(vp));
1572 if (err) {
39738e16 1573 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1574 dev->name);
1575 goto err_out;
1576 }
1da177e4
LT		 1577 }
1578
1579 /* Before initializing select the active media port. */
a095cfc4 1580 config = window_read32(vp, 3, Wn3_Config);
1da177e4
LT		 1581
1582 if (vp->media_override != 7) {
39738e16 1583 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1584 dev->name, vp->media_override,
1585 media_tbl[vp->media_override].name);
1586 dev->if_port = vp->media_override;
1587 } else if (vp->autoselect) {
1588 if (vp->has_nway) {
1589 if (vortex_debug > 1)
39738e16 1590 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1591 dev->name, dev->if_port);
1592 dev->if_port = XCVR_NWAY;
1593 } else {
1594 /* Find first available media type, starting with 100baseTx. */
1595 dev->if_port = XCVR_100baseTx;
1596 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1597 dev->if_port = media_tbl[dev->if_port].next;
1598 if (vortex_debug > 1)
39738e16 1599 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1600 dev->name, media_tbl[dev->if_port].name);
1601 }
1602 } else {
1603 dev->if_port = vp->default_media;
1604 if (vortex_debug > 1)
39738e16 1605 pr_info("%s: using default media %s\n",
1da177e4
LT		 1606 dev->name, media_tbl[dev->if_port].name);
1607 }
1608
1609 init_timer(&vp->timer);
1610 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1611 vp->timer.data = (unsigned long)dev;
1612 vp->timer.function = vortex_timer; /* timer handler */
1613 add_timer(&vp->timer);
1614
1615 init_timer(&vp->rx_oom_timer);
1616 vp->rx_oom_timer.data = (unsigned long)dev;
1617 vp->rx_oom_timer.function = rx_oom_timer;
1618
1619 if (vortex_debug > 1)
39738e16 1620 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1621 dev->name, media_tbl[dev->if_port].name);
1622
125d5ce8 1623 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1624 config = BFINS(config, dev->if_port, 20, 4);
1625 if (vortex_debug > 6)
39738e16 1626 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
a095cfc4 1627 window_write32(vp, config, 3, Wn3_Config);
1da177e4
LT		 1628
1629 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
09ce3512
SK		 1630 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1631 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1632 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1633 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1634
125d5ce8 1635 vortex_check_media(dev, 1);
1da177e4 1636 }
125d5ce8
SK		 1637 else
1638 vortex_set_duplex(dev);
1da177e4 1639
09ce3512
SK		 1640 issue_and_wait(dev, TxReset);
1641 /*
1642 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1643 */
1644 issue_and_wait(dev, RxReset|0x04);
1645
1da177e4 1646
62afe595 1647 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1648
1649 if (vortex_debug > 1) {
39738e16 1650 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
a095cfc4 1651 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1da177e4
LT		 1652 }
1653
1654 /* Set the station address and mask in window 2 each time opened. */
1da177e4 1655 for (i = 0; i < 6; i++)
a095cfc4 1656 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1657 for (; i < 12; i+=2)
a095cfc4 1658 window_write16(vp, 0, 2, i);
1da177e4
LT		 1659
1660 if (vp->cb_fn_base) {
a095cfc4 1661 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1662 if (vp->drv_flags & INVERT_LED_PWR)
1663 n |= 0x10;
1664 if (vp->drv_flags & INVERT_MII_PWR)
1665 n |= 0x4000;
a095cfc4 1666 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4
LT		 1667 }
1668
1669 if (dev->if_port == XCVR_10base2)
1670 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1671 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4 1672 if (dev->if_port != XCVR_NWAY) {
a095cfc4
BH		 1673 window_write16(vp,
1674 (window_read16(vp, 4, Wn4_Media) &
1675 ~(Media_10TP|Media_SQE)) |
1676 media_tbl[dev->if_port].media_bits,
1677 4, Wn4_Media);
1da177e4
LT		 1678 }
1679
1680 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1681 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4 1682 for (i = 0; i < 10; i++)
a095cfc4
BH		 1683 window_read8(vp, 6, i);
1684 window_read16(vp, 6, 10);
1685 window_read16(vp, 6, 12);
1da177e4 1686 /* New: On the Vortex we must also clear the BadSSD counter. */
a095cfc4 1687 window_read8(vp, 4, 12);
1da177e4 1688 /* ..and on the Boomerang we enable the extra statistics bits. */
a095cfc4 1689 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1da177e4
LT		 1690
1691 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1692 vp->cur_rx = vp->dirty_rx = 0;
1693 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1694 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1695 iowrite32(0x0020, ioaddr + PktStatus);
1696 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1697 }
1698 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1699 vp->cur_tx = vp->dirty_tx = 0;
1700 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1701 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1702 /* Clear the Rx, Tx rings. */
1703 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1704 vp->rx_ring[i].status = 0;
1705 for (i = 0; i < TX_RING_SIZE; i++)
1706 vp->tx_skbuff[i] = NULL;
62afe595 1707 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1708 }
1709 /* Set receiver mode: presumably accept b-case and phys addr only. */
1710 set_rx_mode(dev);
1711 /* enable 802.1q tagged frames */
1712 set_8021q_mode(dev, 1);
62afe595 1713 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1714
62afe595
JL		 1715 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1716 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1717 /* Allow status bits to be seen. */
1718 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1719 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1720 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1721 (vp->bus_master ? DMADone : 0);
1722 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1723 (vp->full_bus_master_rx ? 0 : RxComplete) |
1724 StatsFull | HostError | TxComplete | IntReq
1725 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1726 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1727 /* Ack all pending events, and set active indicator mask. */
62afe595 1728 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1729 ioaddr + EL3_CMD);
62afe595 1730 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1731 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1732 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1733 netif_start_queue (dev);
c8303d10
MH		 1734err_out:
1735 return err;
1da177e4
LT		 1736}
1737
1738static int
1739vortex_open(struct net_device *dev)
1740{
1741 struct vortex_private *vp = netdev_priv(dev);
1742 int i;
1743 int retval;
1744
1745 /* Use the now-standard shared IRQ implementation. */
1746 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
c061b18d 1747 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1748 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1749 goto err;
1da177e4
LT		 1750 }
1751
1752 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1753 if (vortex_debug > 2)
39738e16 1754 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1755 for (i = 0; i < RX_RING_SIZE; i++) {
1756 struct sk_buff *skb;
1757 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1758 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1759 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1760
1761 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1762 GFP_KERNEL);
1da177e4
LT		 1763 vp->rx_skbuff[i] = skb;
1764 if (skb == NULL)
1765 break; /* Bad news! */
9a5d3414
SH		 1766
1767 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1768 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1769 }
1770 if (i != RX_RING_SIZE) {
1771 int j;
39738e16 1772 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1773 for (j = 0; j < i; j++) {
1774 if (vp->rx_skbuff[j]) {
1775 dev_kfree_skb(vp->rx_skbuff[j]);
1776 vp->rx_skbuff[j] = NULL;
1777 }
1778 }
1779 retval = -ENOMEM;
c8303d10 1780 goto err_free_irq;
1da177e4
LT		 1781 }
1782 /* Wrap the ring. */
1783 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1784 }
1785
c8303d10
MH		 1786 retval = vortex_up(dev);
1787 if (!retval)
1788 goto out;
1da177e4 1789
c8303d10 1790err_free_irq:
1da177e4 1791 free_irq(dev->irq, dev);
c8303d10 1792err:
1da177e4 1793 if (vortex_debug > 1)
39738e16 1794 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1795out:
1da177e4
LT		 1796 return retval;
1797}
1798
1799static void
1800vortex_timer(unsigned long data)
1801{
1802 struct net_device *dev = (struct net_device *)data;
1803 struct vortex_private *vp = netdev_priv(dev);
62afe595 1804 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1805 int next_tick = 60*HZ;
1806 int ok = 0;
a095cfc4 1807 int media_status;
1da177e4
LT		 1808
1809 if (vortex_debug > 2) {
39738e16 1810 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1811 dev->name, media_tbl[dev->if_port].name);
39738e16 1812 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1813 }
1814
a095cfc4 1815 media_status = window_read16(vp, 4, Wn4_Media);
1da177e4
LT		 1816 switch (dev->if_port) {
1817 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1818 if (media_status & Media_LnkBeat) {
1819 netif_carrier_on(dev);
1820 ok = 1;
1821 if (vortex_debug > 1)
39738e16 1822 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1823 dev->name, media_tbl[dev->if_port].name, media_status);
1824 } else {
1825 netif_carrier_off(dev);
1826 if (vortex_debug > 1) {
39738e16 1827 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1828 dev->name, media_tbl[dev->if_port].name, media_status);
1829 }
1830 }
1831 break;
1832 case XCVR_MII: case XCVR_NWAY:
1833 {
1da177e4 1834 ok = 1;
125d5ce8 1835 vortex_check_media(dev, 0);
1da177e4
LT		 1836 }
1837 break;
1838 default: /* Other media types handled by Tx timeouts. */
1839 if (vortex_debug > 1)
39738e16 1840 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1841 dev->name, media_tbl[dev->if_port].name, media_status);
1842 ok = 1;
1843 }
b4ff6450
SK		 1844
1845 if (!netif_carrier_ok(dev))
1846 next_tick = 5*HZ;
1847
e94d10eb
SK		 1848 if (vp->medialock)
1849 goto leave_media_alone;
1850
a880c4cd 1851 if (!ok) {
1da177e4
LT		 1852 unsigned int config;
1853
de847272
BH		 1854 spin_lock_irq(&vp->lock);
1855
1da177e4
LT		 1856 do {
1857 dev->if_port = media_tbl[dev->if_port].next;
1858 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1859 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1860 dev->if_port = vp->default_media;
1861 if (vortex_debug > 1)
39738e16 1862 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1863 dev->name, media_tbl[dev->if_port].name);
1864 } else {
1865 if (vortex_debug > 1)
39738e16 1866 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1867 dev->name, media_tbl[dev->if_port].name);
1868 next_tick = media_tbl[dev->if_port].wait;
1869 }
a095cfc4
BH		 1870 window_write16(vp,
1871 (media_status & ~(Media_10TP|Media_SQE)) |
1872 media_tbl[dev->if_port].media_bits,
1873 4, Wn4_Media);
1da177e4 1874
a095cfc4 1875 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1876 config = BFINS(config, dev->if_port, 20, 4);
a095cfc4 1877 window_write32(vp, config, 3, Wn3_Config);
1da177e4 1878
62afe595 1879 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1880 ioaddr + EL3_CMD);
1881 if (vortex_debug > 1)
39738e16 1882 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4 1883 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
de847272
BH		 1884
1885 spin_unlock_irq(&vp->lock);
1da177e4 1886 }
1da177e4
LT		 1887
1888leave_media_alone:
1889 if (vortex_debug > 2)
39738e16 1890 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1891 dev->name, media_tbl[dev->if_port].name);
1892
1893 mod_timer(&vp->timer, RUN_AT(next_tick));
1894 if (vp->deferred)
62afe595 1895 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1896}
1897
1898static void vortex_tx_timeout(struct net_device *dev)
1899{
1900 struct vortex_private *vp = netdev_priv(dev);
62afe595 1901 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1902
39738e16 1903 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1904 dev->name, ioread8(ioaddr + TxStatus),
1905 ioread16(ioaddr + EL3_STATUS));
39738e16 1906 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
a095cfc4
BH		 1907 window_read16(vp, 4, Wn4_NetDiag),
1908 window_read16(vp, 4, Wn4_Media),
62afe595 1909 ioread32(ioaddr + PktStatus),
a095cfc4 1910 window_read16(vp, 4, Wn4_FIFODiag));
1da177e4 1911 /* Slight code bloat to be user friendly. */
62afe595 1912 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1913 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1914 " network cable problem?\n", dev->name);
62afe595 1915 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1916 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1917 " IRQ blocked by another device?\n", dev->name);
1918 /* Bad idea here.. but we might as well handle a few events. */
1919 {
1920 /*
1921 * Block interrupts because vortex_interrupt does a bare spin_lock()
1922 */
1923 unsigned long flags;
1924 local_irq_save(flags);
1925 if (vp->full_bus_master_tx)
7d12e780 1926 boomerang_interrupt(dev->irq, dev);
1da177e4 1927 else
7d12e780 1928 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1929 local_irq_restore(flags);
1930 }
1931 }
1932
1933 if (vortex_debug > 0)
1934 dump_tx_ring(dev);
1935
1936 issue_and_wait(dev, TxReset);
1937
1daad055 1938 dev->stats.tx_errors++;
1da177e4 1939 if (vp->full_bus_master_tx) {
39738e16 1940 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1941 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1942 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1943 ioaddr + DownListPtr);
1944 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1945 netif_wake_queue (dev);
1946 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1947 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1948 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1949 } else {
1daad055 1950 dev->stats.tx_dropped++;
1da177e4
LT		 1951 netif_wake_queue(dev);
1952 }
6aa20a22 1953
1da177e4 1954 /* Issue Tx Enable */
62afe595 1955 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1956 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1957}
1958
1959/*
1960 * Handle uncommon interrupt sources. This is a separate routine to minimize
1961 * the cache impact.
1962 */
1963static void
1964vortex_error(struct net_device *dev, int status)
1965{
1966 struct vortex_private *vp = netdev_priv(dev);
62afe595 1967 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1968 int do_tx_reset = 0, reset_mask = 0;
1969 unsigned char tx_status = 0;
1970
1971 if (vortex_debug > 2) {
39738e16 1972 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1973 }
1974
1975 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1976 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1977 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1978 if (vortex_debug > 2 ||
1979 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1980 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1981 dev->name, tx_status);
1982 if (tx_status == 0x82) {
39738e16 1983 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1984 "Documentation/networking/vortex.txt\n");
1985 }
1986 dump_tx_ring(dev);
1987 }
1daad055
PZ		 1988 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1989 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1990 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1991 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1992 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1993 do_tx_reset = 1;
0000754c
AM		 1994 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1995 do_tx_reset = 1;
1996 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1997 } else { /* Merely re-enable the transmitter. */
62afe595 1998 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1999 }
2000 }
2001
89b12fab 2002 if (status & RxEarly) /* Rx early is unused. */
62afe595 2003 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
89b12fab 2004
1da177e4
LT		 2005 if (status & StatsFull) { /* Empty statistics. */
2006 static int DoneDidThat;
2007 if (vortex_debug > 4)
39738e16 2008 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 2009 update_stats(ioaddr, dev);
2010 /* HACK: Disable statistics as an interrupt source. */
2011 /* This occurs when we have the wrong media type! */
2012 if (DoneDidThat == 0 &&
62afe595 2013 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 2014 pr_warning("%s: Updating statistics failed, disabling "
1da177e4 2015 "stats as an interrupt source.\n", dev->name);
a095cfc4
BH		 2016 iowrite16(SetIntrEnb |
2017 (window_read16(vp, 5, 10) & ~StatsFull),
2018 ioaddr + EL3_CMD);
1da177e4 2019 vp->intr_enable &= ~StatsFull;
1da177e4
LT		 2020 DoneDidThat++;
2021 }
2022 }
2023 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2024 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2025 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2026 }
2027 if (status & HostError) {
2028 u16 fifo_diag;
a095cfc4 2029 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
39738e16 2030 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2031 dev->name, fifo_diag);
2032 /* Adapter failure requires Tx/Rx reset and reinit. */
2033 if (vp->full_bus_master_tx) {
62afe595 2034 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2035 /* 0x80000000 PCI master abort. */
2036 /* 0x40000000 PCI target abort. */
2037 if (vortex_debug)
39738e16 2038 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2039
2040 /* In this case, blow the card away */
2041 /* Must not enter D3 or we can't legally issue the reset! */
2042 vortex_down(dev, 0);
2043 issue_and_wait(dev, TotalReset | 0xff);
2044 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2045 } else if (fifo_diag & 0x0400)
2046 do_tx_reset = 1;
2047 if (fifo_diag & 0x3000) {
2048 /* Reset Rx fifo and upload logic */
2049 issue_and_wait(dev, RxReset|0x07);
2050 /* Set the Rx filter to the current state. */
2051 set_rx_mode(dev);
2052 /* enable 802.1q VLAN tagged frames */
2053 set_8021q_mode(dev, 1);
62afe595
JL		 2054 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2055 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2056 }
2057 }
2058
2059 if (do_tx_reset) {
2060 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2061 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2062 if (!vp->full_bus_master_tx)
2063 netif_wake_queue(dev);
2064 }
2065}
2066
27a1de95 2067static netdev_tx_t
1da177e4
LT		 2068vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2069{
2070 struct vortex_private *vp = netdev_priv(dev);
62afe595 2071 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2072
2073 /* Put out the doubleword header... */
62afe595 2074 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2075 if (vp->bus_master) {
2076 /* Set the bus-master controller to transfer the packet. */
2077 int len = (skb->len + 3) & ~3;
a095cfc4
BH		 2078 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2079 PCI_DMA_TODEVICE);
de847272 2080 spin_lock_irq(&vp->window_lock);
a095cfc4
BH		 2081 window_set(vp, 7);
2082 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
62afe595 2083 iowrite16(len, ioaddr + Wn7_MasterLen);
de847272 2084 spin_unlock_irq(&vp->window_lock);
1da177e4 2085 vp->tx_skb = skb;
62afe595 2086 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2087 /* netif_wake_queue() will be called at the DMADone interrupt. */
2088 } else {
2089 /* ... and the packet rounded to a doubleword. */
62afe595 2090 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2091 dev_kfree_skb (skb);
62afe595 2092 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2093 netif_start_queue (dev); /* AKPM: redundant? */
2094 } else {
2095 /* Interrupt us when the FIFO has room for max-sized packet. */
2096 netif_stop_queue(dev);
62afe595 2097 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2098 }
2099 }
2100
1da177e4
LT		 2101
2102 /* Clear the Tx status stack. */
2103 {
2104 int tx_status;
2105 int i = 32;
2106
62afe595 2107 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2108 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2109 if (vortex_debug > 2)
39738e16 2110 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2111 dev->name, tx_status);
1daad055
PZ		 2112 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2113 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2114 if (tx_status & 0x30) {
2115 issue_and_wait(dev, TxReset);
2116 }
62afe595 2117 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2118 }
62afe595 2119 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2120 }
2121 }
6ed10654 2122 return NETDEV_TX_OK;
1da177e4
LT		 2123}
2124
27a1de95 2125static netdev_tx_t
1da177e4
LT		 2126boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2127{
2128 struct vortex_private *vp = netdev_priv(dev);
62afe595 2129 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2130 /* Calculate the next Tx descriptor entry. */
2131 int entry = vp->cur_tx % TX_RING_SIZE;
2132 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2133 unsigned long flags;
2134
2135 if (vortex_debug > 6) {
39738e16
AB		 2136 pr_debug("boomerang_start_xmit()\n");
2137 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2138 dev->name, vp->cur_tx);
1da177e4
LT		 2139 }
2140
aa25ab7d
NH		 2141 /*
2142 * We can't allow a recursion from our interrupt handler back into the
2143 * tx routine, as they take the same spin lock, and that causes
2144 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2145 * a bit
2146 */
2147 if (vp->handling_irq)
2148 return NETDEV_TX_BUSY;
2149
1da177e4
LT		 2150 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2151 if (vortex_debug > 0)
39738e16 2152 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2153 dev->name);
2154 netif_stop_queue(dev);
5b548140 2155 return NETDEV_TX_BUSY;
1da177e4
LT		 2156 }
2157
2158 vp->tx_skbuff[entry] = skb;
2159
2160 vp->tx_ring[entry].next = 0;
2161#if DO_ZEROCOPY
84fa7933 2162 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2163 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2164 else
2165 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2166
2167 if (!skb_shinfo(skb)->nr_frags) {
2168 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2169 skb->len, PCI_DMA_TODEVICE));
2170 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2171 } else {
2172 int i;
2173
2174 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2175 skb_headlen(skb), PCI_DMA_TODEVICE));
2176 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2177
2178 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2179 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2180
2181 vp->tx_ring[entry].frag[i+1].addr =
7b63e3a8
IC		 2182 cpu_to_le32(pci_map_single(
2183 VORTEX_PCI(vp),
2184 (void *)skb_frag_address(frag),
2185 frag->size, PCI_DMA_TODEVICE));
1da177e4
LT		 2186
2187 if (i == skb_shinfo(skb)->nr_frags-1)
2188 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2189 else
2190 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2191 }
2192 }
2193#else
2194 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2195 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2196 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2197#endif
2198
2199 spin_lock_irqsave(&vp->lock, flags);
2200 /* Wait for the stall to complete. */
2201 issue_and_wait(dev, DownStall);
2202 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2203 if (ioread32(ioaddr + DownListPtr) == 0) {
2204 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2205 vp->queued_packet++;
2206 }
2207
2208 vp->cur_tx++;
2209 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2210 netif_stop_queue (dev);
2211 } else { /* Clear previous interrupt enable. */
2212#if defined(tx_interrupt_mitigation)
2213 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2214 * were selected, this would corrupt DN_COMPLETE. No?
2215 */
2216 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2217#endif
2218 }
62afe595 2219 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2220 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2221 return NETDEV_TX_OK;
1da177e4
LT		 2222}
2223
2224/* The interrupt handler does all of the Rx thread work and cleans up
2225 after the Tx thread. */
2226
2227/*
2228 * This is the ISR for the vortex series chips.
2229 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2230 */
2231
2232static irqreturn_t
7d12e780 2233vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2234{
2235 struct net_device *dev = dev_id;
2236 struct vortex_private *vp = netdev_priv(dev);
62afe595 2237 void __iomem *ioaddr;
1da177e4
LT		 2238 int status;
2239 int work_done = max_interrupt_work;
2240 int handled = 0;
2241
62afe595 2242 ioaddr = vp->ioaddr;
1da177e4
LT		 2243 spin_lock(&vp->lock);
2244
62afe595 2245 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2246
2247 if (vortex_debug > 6)
39738e16 2248 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2249
2250 if ((status & IntLatch) == 0)
2251 goto handler_exit; /* No interrupt: shared IRQs cause this */
2252 handled = 1;
2253
2254 if (status & IntReq) {
2255 status |= vp->deferred;
2256 vp->deferred = 0;
2257 }
2258
2259 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2260 goto handler_exit;
2261
2262 if (vortex_debug > 4)
39738e16 2263 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2264 dev->name, status, ioread8(ioaddr + Timer));
1da177e4 2265
de847272 2266 spin_lock(&vp->window_lock);
a095cfc4
BH		 2267 window_set(vp, 7);
2268
1da177e4
LT		 2269 do {
2270 if (vortex_debug > 5)
39738e16 2271 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2272 dev->name, status);
2273 if (status & RxComplete)
2274 vortex_rx(dev);
2275
2276 if (status & TxAvailable) {
2277 if (vortex_debug > 5)
39738e16 2278 pr_debug(" TX room bit was handled.\n");
1da177e4 2279 /* There's room in the FIFO for a full-sized packet. */
62afe595 2280 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2281 netif_wake_queue (dev);
2282 }
2283
2284 if (status & DMADone) {
62afe595
JL		 2285 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2286 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2287 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2288 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2289 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2290 /*
2291 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2292 * insufficient FIFO room, the TxAvailable test will succeed and call
2293 * netif_wake_queue()
2294 */
2295 netif_wake_queue(dev);
2296 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2297 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2298 netif_stop_queue(dev);
2299 }
2300 }
2301 }
2302 /* Check for all uncommon interrupts at once. */
2303 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2304 if (status == 0xffff)
2305 break;
89b12fab
BH		 2306 if (status & RxEarly)
2307 vortex_rx(dev);
2308 spin_unlock(&vp->window_lock);
1da177e4 2309 vortex_error(dev, status);
89b12fab
BH		 2310 spin_lock(&vp->window_lock);
2311 window_set(vp, 7);
1da177e4
LT		 2312 }
2313
2314 if (--work_done < 0) {
39738e16
AB		 2315 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2316 dev->name, status);
1da177e4
LT		 2317 /* Disable all pending interrupts. */
2318 do {
2319 vp->deferred |= status;
62afe595 2320 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2321 ioaddr + EL3_CMD);
62afe595
JL		 2322 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2323 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2324 /* The timer will reenable interrupts. */
2325 mod_timer(&vp->timer, jiffies + 1*HZ);
2326 break;
2327 }
2328 /* Acknowledge the IRQ. */
62afe595
JL		 2329 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2330 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4 2331
de847272
BH		 2332 spin_unlock(&vp->window_lock);
2333
1da177e4 2334 if (vortex_debug > 4)
39738e16 2335 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2336 dev->name, status);
2337handler_exit:
2338 spin_unlock(&vp->lock);
2339 return IRQ_RETVAL(handled);
2340}
2341
2342/*
2343 * This is the ISR for the boomerang series chips.
2344 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2345 */
2346
2347static irqreturn_t
7d12e780 2348boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2349{
2350 struct net_device *dev = dev_id;
2351 struct vortex_private *vp = netdev_priv(dev);
62afe595 2352 void __iomem *ioaddr;
1da177e4
LT		 2353 int status;
2354 int work_done = max_interrupt_work;
2355
62afe595 2356 ioaddr = vp->ioaddr;
1da177e4 2357
aa25ab7d 2358
1da177e4
LT		 2359 /*
2360 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2361 * and boomerang_start_xmit
2362 */
2363 spin_lock(&vp->lock);
aa25ab7d 2364 vp->handling_irq = 1;
1da177e4 2365
62afe595 2366 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2367
2368 if (vortex_debug > 6)
39738e16 2369 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2370
2371 if ((status & IntLatch) == 0)
2372 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2373
2374 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2375 if (vortex_debug > 1)
39738e16 2376 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2377 goto handler_exit;
2378 }
2379
2380 if (status & IntReq) {
2381 status |= vp->deferred;
2382 vp->deferred = 0;
2383 }
2384
2385 if (vortex_debug > 4)
39738e16 2386 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2387 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2388 do {
2389 if (vortex_debug > 5)
39738e16 2390 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2391 dev->name, status);
2392 if (status & UpComplete) {
62afe595 2393 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2394 if (vortex_debug > 5)
39738e16 2395 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2396 boomerang_rx(dev);
2397 }
2398
2399 if (status & DownComplete) {
2400 unsigned int dirty_tx = vp->dirty_tx;
2401
62afe595 2402 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2403 while (vp->cur_tx - dirty_tx > 0) {
2404 int entry = dirty_tx % TX_RING_SIZE;
2405#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2406 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2407 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2408 break; /* It still hasn't been processed. */
2409#else
2410 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2411 break; /* It still hasn't been processed. */
2412#endif
6aa20a22 2413
1da177e4
LT		 2414 if (vp->tx_skbuff[entry]) {
2415 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2416#if DO_ZEROCOPY
1da177e4
LT		 2417 int i;
2418 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2419 pci_unmap_single(VORTEX_PCI(vp),
2420 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2421 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2422 PCI_DMA_TODEVICE);
2423#else
2424 pci_unmap_single(VORTEX_PCI(vp),
2425 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2426#endif
2427 dev_kfree_skb_irq(skb);
2428 vp->tx_skbuff[entry] = NULL;
2429 } else {
39738e16 2430 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2431 }
1daad055 2432 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2433 dirty_tx++;
2434 }
2435 vp->dirty_tx = dirty_tx;
2436 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2437 if (vortex_debug > 6)
39738e16 2438 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2439 netif_wake_queue (dev);
2440 }
2441 }
2442
2443 /* Check for all uncommon interrupts at once. */
2444 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2445 vortex_error(dev, status);
2446
2447 if (--work_done < 0) {
39738e16
AB		 2448 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2449 dev->name, status);
1da177e4
LT		 2450 /* Disable all pending interrupts. */
2451 do {
2452 vp->deferred |= status;
62afe595 2453 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2454 ioaddr + EL3_CMD);
62afe595
JL		 2455 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2456 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2457 /* The timer will reenable interrupts. */
2458 mod_timer(&vp->timer, jiffies + 1*HZ);
2459 break;
2460 }
2461 /* Acknowledge the IRQ. */
62afe595 2462 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2463 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2464 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2465
62afe595 2466 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2467
2468 if (vortex_debug > 4)
39738e16 2469 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2470 dev->name, status);
2471handler_exit:
aa25ab7d 2472 vp->handling_irq = 0;
1da177e4
LT		 2473 spin_unlock(&vp->lock);
2474 return IRQ_HANDLED;
2475}
2476
2477static int vortex_rx(struct net_device *dev)
2478{
2479 struct vortex_private *vp = netdev_priv(dev);
62afe595 2480 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2481 int i;
2482 short rx_status;
2483
2484 if (vortex_debug > 5)
39738e16 2485 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2486 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2487 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2488 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2489 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2490 if (vortex_debug > 2)
39738e16 2491 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2492 dev->stats.rx_errors++;
2493 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2494 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2495 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2496 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2497 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2498 } else {
2499 /* The packet length: up to 4.5K!. */
2500 int pkt_len = rx_status & 0x1fff;
2501 struct sk_buff *skb;
2502
2503 skb = dev_alloc_skb(pkt_len + 5);
2504 if (vortex_debug > 4)
39738e16 2505 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2506 pkt_len, rx_status);
2507 if (skb != NULL) {
1da177e4
LT		 2508 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2509 /* 'skb_put()' points to the start of sk_buff data area. */
2510 if (vp->bus_master &&
62afe595 2511 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2512 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2513 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2514 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2515 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2516 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2517 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2518 ;
2519 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2520 } else {
62afe595
JL		 2521 ioread32_rep(ioaddr + RX_FIFO,
2522 skb_put(skb, pkt_len),
2523 (pkt_len + 3) >> 2);
1da177e4 2524 }
62afe595 2525 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2526 skb->protocol = eth_type_trans(skb, dev);
2527 netif_rx(skb);
1daad055 2528 dev->stats.rx_packets++;
1da177e4
LT		 2529 /* Wait a limited time to go to next packet. */
2530 for (i = 200; i >= 0; i--)
62afe595 2531 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2532 break;
2533 continue;
2534 } else if (vortex_debug > 0)
39738e16
AB		 2535 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2536 dev->name, pkt_len);
1daad055 2537 dev->stats.rx_dropped++;
1da177e4 2538 }
1da177e4
LT		 2539 issue_and_wait(dev, RxDiscard);
2540 }
2541
2542 return 0;
2543}
2544
2545static int
2546boomerang_rx(struct net_device *dev)
2547{
2548 struct vortex_private *vp = netdev_priv(dev);
2549 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2550 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2551 int rx_status;
2552 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2553
2554 if (vortex_debug > 5)
39738e16 2555 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2556
2557 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2558 if (--rx_work_limit < 0)
2559 break;
2560 if (rx_status & RxDError) { /* Error, update stats. */
2561 unsigned char rx_error = rx_status >> 16;
2562 if (vortex_debug > 2)
39738e16 2563 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2564 dev->stats.rx_errors++;
2565 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2566 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2567 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2568 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2569 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2570 } else {
2571 /* The packet length: up to 4.5K!. */
2572 int pkt_len = rx_status & 0x1fff;
2573 struct sk_buff *skb;
2574 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2575
2576 if (vortex_debug > 4)
39738e16 2577 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2578 pkt_len, rx_status);
2579
2580 /* Check if the packet is long enough to just accept without
2581 copying to a properly sized skbuff. */
cc2d6596 2582 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2583 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2584 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2585 /* 'skb_put()' points to the start of sk_buff data area. */
2586 memcpy(skb_put(skb, pkt_len),
689be439 2587 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2588 pkt_len);
2589 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2590 vp->rx_copy++;
2591 } else {
2592 /* Pass up the skbuff already on the Rx ring. */
2593 skb = vp->rx_skbuff[entry];
2594 vp->rx_skbuff[entry] = NULL;
2595 skb_put(skb, pkt_len);
2596 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2597 vp->rx_nocopy++;
2598 }
2599 skb->protocol = eth_type_trans(skb, dev);
2600 { /* Use hardware checksum info. */
2601 int csum_bits = rx_status & 0xee000000;
2602 if (csum_bits &&
2603 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2604 csum_bits == (IPChksumValid | UDPChksumValid))) {
2605 skb->ip_summed = CHECKSUM_UNNECESSARY;
2606 vp->rx_csumhits++;
2607 }
2608 }
2609 netif_rx(skb);
1daad055 2610 dev->stats.rx_packets++;
1da177e4
LT		 2611 }
2612 entry = (++vp->cur_rx) % RX_RING_SIZE;
2613 }
2614 /* Refill the Rx ring buffers. */
2615 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2616 struct sk_buff *skb;
2617 entry = vp->dirty_rx % RX_RING_SIZE;
2618 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2619 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2620 if (skb == NULL) {
2621 static unsigned long last_jif;
ff5688ae 2622 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2623 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2624 last_jif = jiffies;
2625 }
2626 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2627 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2628 break; /* Bad news! */
2629 }
9a5d3414 2630
689be439 2631 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2632 vp->rx_skbuff[entry] = skb;
2633 }
2634 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2635 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2636 }
2637 return 0;
2638}
2639
2640/*
2641 * If we've hit a total OOM refilling the Rx ring we poll once a second
2642 * for some memory. Otherwise there is no way to restart the rx process.
2643 */
2644static void
2645rx_oom_timer(unsigned long arg)
2646{
2647 struct net_device *dev = (struct net_device *)arg;
2648 struct vortex_private *vp = netdev_priv(dev);
2649
2650 spin_lock_irq(&vp->lock);
2651 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2652 boomerang_rx(dev);
2653 if (vortex_debug > 1) {
39738e16 2654 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2655 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2656 }
2657 spin_unlock_irq(&vp->lock);
2658}
2659
2660static void
2661vortex_down(struct net_device *dev, int final_down)
2662{
2663 struct vortex_private *vp = netdev_priv(dev);
62afe595 2664 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2665
2666 netif_stop_queue (dev);
2667
2668 del_timer_sync(&vp->rx_oom_timer);
2669 del_timer_sync(&vp->timer);
2670
1daad055 2671 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2672 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2673
2674 /* Disable the receiver and transmitter. */
62afe595
JL		 2675 iowrite16(RxDisable, ioaddr + EL3_CMD);
2676 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2677
2678 /* Disable receiving 802.1q tagged frames */
2679 set_8021q_mode(dev, 0);
2680
2681 if (dev->if_port == XCVR_10base2)
2682 /* Turn off thinnet power. Green! */
62afe595 2683 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2684
62afe595 2685 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2686
2687 update_stats(ioaddr, dev);
2688 if (vp->full_bus_master_rx)
62afe595 2689 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2690 if (vp->full_bus_master_tx)
62afe595 2691 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2692
2693 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2694 vp->pm_state_valid = 1;
1da177e4
LT		 2695 pci_save_state(VORTEX_PCI(vp));
2696 acpi_set_WOL(dev);
2697 }
2698}
2699
2700static int
2701vortex_close(struct net_device *dev)
2702{
2703 struct vortex_private *vp = netdev_priv(dev);
62afe595 2704 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2705 int i;
2706
2707 if (netif_device_present(dev))
2708 vortex_down(dev, 1);
2709
2710 if (vortex_debug > 1) {
39738e16 2711 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2712 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2713 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2714 " tx_queued %d Rx pre-checksummed %d.\n",
2715 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2716 }
2717
2718#if DO_ZEROCOPY
32fb5f06
JL		 2719 if (vp->rx_csumhits &&
2720 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2721 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2722 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2723 }
2724#endif
6aa20a22 2725
1da177e4
LT		 2726 free_irq(dev->irq, dev);
2727
2728 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2729 for (i = 0; i < RX_RING_SIZE; i++)
2730 if (vp->rx_skbuff[i]) {
2731 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2732 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2733 dev_kfree_skb(vp->rx_skbuff[i]);
2734 vp->rx_skbuff[i] = NULL;
2735 }
2736 }
2737 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2738 for (i = 0; i < TX_RING_SIZE; i++) {
2739 if (vp->tx_skbuff[i]) {
2740 struct sk_buff *skb = vp->tx_skbuff[i];
2741#if DO_ZEROCOPY
2742 int k;
2743
2744 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2745 pci_unmap_single(VORTEX_PCI(vp),
2746 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2747 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2748 PCI_DMA_TODEVICE);
2749#else
2750 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2751#endif
2752 dev_kfree_skb(skb);
2753 vp->tx_skbuff[i] = NULL;
2754 }
2755 }
2756 }
2757
2758 return 0;
2759}
2760
2761static void
2762dump_tx_ring(struct net_device *dev)
2763{
2764 if (vortex_debug > 0) {
2765 struct vortex_private *vp = netdev_priv(dev);
62afe595 2766 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2767
1da177e4
LT		 2768 if (vp->full_bus_master_tx) {
2769 int i;
62afe595 2770 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2771
39738e16 2772 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2773 vp->full_bus_master_tx,
2774 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2775 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2776 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2777 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2778 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2779 issue_and_wait(dev, DownStall);
2780 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2781 unsigned int length;
2782
1da177e4 2783#if DO_ZEROCOPY
0cb13536 2784 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2785#else
0cb13536 2786 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2787#endif
0cb13536
JD		 2788 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2789 i, &vp->tx_ring[i], length,
1da177e4
LT		 2790 le32_to_cpu(vp->tx_ring[i].status));
2791 }
2792 if (!stalled)
62afe595 2793 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2794 }
2795 }
2796}
2797
2798static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2799{
2800 struct vortex_private *vp = netdev_priv(dev);
62afe595 2801 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2802 unsigned long flags;
2803
2804 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2805 spin_lock_irqsave (&vp->lock, flags);
62afe595 2806 update_stats(ioaddr, dev);
1da177e4
LT		 2807 spin_unlock_irqrestore (&vp->lock, flags);
2808 }
1daad055 2809 return &dev->stats;
1da177e4
LT		 2810}
2811
2812/* Update statistics.
2813 Unlike with the EL3 we need not worry about interrupts changing
2814 the window setting from underneath us, but we must still guard
2815 against a race condition with a StatsUpdate interrupt updating the
2816 table. This is done by checking that the ASM (!) code generated uses
2817 atomic updates with '+='.
2818 */
62afe595 2819static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2820{
2821 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2822
1da177e4
LT		 2823 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2824 /* Switch to the stats window, and read everything. */
a095cfc4
BH		 2825 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2826 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2827 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2828 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2829 dev->stats.tx_packets += window_read8(vp, 6, 6);
2830 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2831 0x30) << 4;
2832 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
1da177e4
LT		 2833 /* Don't bother with register 9, an extension of registers 6&7.
2834 If we do use the 6&7 values the atomic update assumption above
2835 is invalid. */
a095cfc4
BH		 2836 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2837 dev->stats.tx_bytes += window_read16(vp, 6, 12);
1da177e4 2838 /* Extra stats for get_ethtool_stats() */
a095cfc4
BH		 2839 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2840 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2841 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2842 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
1da177e4 2843
1daad055 2844 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2845 + vp->xstats.tx_single_collisions
2846 + vp->xstats.tx_max_collisions;
2847
1da177e4 2848 {
a095cfc4 2849 u8 up = window_read8(vp, 4, 13);
1daad055
PZ		 2850 dev->stats.rx_bytes += (up & 0x0f) << 16;
2851 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4 2852 }
1da177e4
LT		 2853}
2854
2855static int vortex_nway_reset(struct net_device *dev)
2856{
2857 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2858
de847272 2859 return mii_nway_restart(&vp->mii);
1da177e4
LT		 2860}
2861
1da177e4
LT		 2862static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2863{
2864 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2865
de847272 2866 return mii_ethtool_gset(&vp->mii, cmd);
1da177e4
LT		 2867}
2868
2869static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2870{
2871 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2872
de847272 2873 return mii_ethtool_sset(&vp->mii, cmd);
1da177e4
LT		 2874}
2875
2876static u32 vortex_get_msglevel(struct net_device *dev)
2877{
2878 return vortex_debug;
2879}
2880
2881static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2882{
2883 vortex_debug = dbg;
2884}
2885
b9f2c044 2886static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2887{
b9f2c044
JG		 2888 switch (sset) {
2889 case ETH_SS_STATS:
2890 return VORTEX_NUM_STATS;
2891 default:
2892 return -EOPNOTSUPP;
2893 }
1da177e4
LT		 2894}
2895
2896static void vortex_get_ethtool_stats(struct net_device *dev,
2897 struct ethtool_stats *stats, u64 *data)
2898{
2899 struct vortex_private *vp = netdev_priv(dev);
62afe595 2900 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2901 unsigned long flags;
2902
2903 spin_lock_irqsave(&vp->lock, flags);
62afe595 2904 update_stats(ioaddr, dev);
1da177e4
LT		 2905 spin_unlock_irqrestore(&vp->lock, flags);
2906
2907 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2908 data[1] = vp->xstats.tx_max_collisions;
2909 data[2] = vp->xstats.tx_multiple_collisions;
2910 data[3] = vp->xstats.tx_single_collisions;
2911 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2912}
2913
2914
2915static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2916{
2917 switch (stringset) {
2918 case ETH_SS_STATS:
2919 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2920 break;
2921 default:
2922 WARN_ON(1);
2923 break;
2924 }
2925}
2926
2927static void vortex_get_drvinfo(struct net_device *dev,
2928 struct ethtool_drvinfo *info)
2929{
2930 struct vortex_private *vp = netdev_priv(dev);
2931
2932 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2933 if (VORTEX_PCI(vp)) {
2934 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2935 } else {
2936 if (VORTEX_EISA(vp))
86de79b6 2937 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2938 else
2939 sprintf(info->bus_info, "EISA 0x%lx %d",
2940 dev->base_addr, dev->irq);
2941 }
2942}
2943
690a1f20
AS		 2944static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2945{
2946 struct vortex_private *vp = netdev_priv(dev);
2947
3fd6c88e
JB		 2948 if (!VORTEX_PCI(vp))
2949 return;
2950
690a1f20
AS		 2951 wol->supported = WAKE_MAGIC;
2952
2953 wol->wolopts = 0;
2954 if (vp->enable_wol)
2955 wol->wolopts |= WAKE_MAGIC;
690a1f20
AS		 2956}
2957
2958static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2959{
2960 struct vortex_private *vp = netdev_priv(dev);
3fd6c88e
JB		 2961
2962 if (!VORTEX_PCI(vp))
2963 return -EOPNOTSUPP;
2964
690a1f20
AS		 2965 if (wol->wolopts & ~WAKE_MAGIC)
2966 return -EINVAL;
2967
690a1f20
AS		 2968 if (wol->wolopts & WAKE_MAGIC)
2969 vp->enable_wol = 1;
2970 else
2971 vp->enable_wol = 0;
2972 acpi_set_WOL(dev);
690a1f20
AS		 2973
2974 return 0;
2975}
2976
7282d491 2977static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2978 .get_drvinfo = vortex_get_drvinfo,
2979 .get_strings = vortex_get_strings,
2980 .get_msglevel = vortex_get_msglevel,
2981 .set_msglevel = vortex_set_msglevel,
2982 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2983 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2984 .get_settings = vortex_get_settings,
2985 .set_settings = vortex_set_settings,
373a6887 2986 .get_link = ethtool_op_get_link,
1da177e4 2987 .nway_reset = vortex_nway_reset,
690a1f20
AS		 2988 .get_wol = vortex_get_wol,
2989 .set_wol = vortex_set_wol,
1da177e4
LT		 2990};
2991
2992#ifdef CONFIG_PCI
2993/*
2994 * Must power the device up to do MDIO operations
2995 */
2996static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2997{
2998 int err;
2999 struct vortex_private *vp = netdev_priv(dev);
cc2d6596 3000 pci_power_t state = 0;
1da177e4
LT		 3001
3002 if(VORTEX_PCI(vp))
3003 state = VORTEX_PCI(vp)->current_state;
3004
3005 /* The kernel core really should have pci_get_power_state() */
3006
3007 if(state != 0)
3008 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
1da177e4 3009 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
1da177e4
LT		 3010 if(state != 0)
3011 pci_set_power_state(VORTEX_PCI(vp), state);
3012
3013 return err;
3014}
3015#endif
3016
3017
3018/* Pre-Cyclone chips have no documented multicast filter, so the only
3019 multicast setting is to receive all multicast frames. At least
3020 the chip has a very clean way to set the mode, unlike many others. */
3021static void set_rx_mode(struct net_device *dev)
3022{
62afe595
JL		 3023 struct vortex_private *vp = netdev_priv(dev);
3024 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3025 int new_mode;
3026
3027 if (dev->flags & IFF_PROMISC) {
d5b20697 3028 if (vortex_debug > 3)
39738e16 3029 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 3030 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 3031 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 3032 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3033 } else
3034 new_mode = SetRxFilter | RxStation | RxBroadcast;
3035
62afe595 3036 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3037}
3038
3039#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3040/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3041 Note that this must be done after each RxReset due to some backwards
3042 compatibility logic in the Cyclone and Tornado ASICs */
3043
3044/* The Ethernet Type used for 802.1q tagged frames */
3045#define VLAN_ETHER_TYPE 0x8100
3046
3047static void set_8021q_mode(struct net_device *dev, int enable)
3048{
3049 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3050 int mac_ctrl;
3051
3052 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3053 /* cyclone and tornado chipsets can recognize 802.1q
3054 * tagged frames and treat them correctly */
3055
3056 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3057 if (enable)
3058 max_pkt_size += 4; /* 802.1Q VLAN tag */
3059
a095cfc4 3060 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
1da177e4
LT		 3061
3062 /* set VlanEtherType to let the hardware checksumming
3063 treat tagged frames correctly */
a095cfc4 3064 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
1da177e4
LT		 3065 } else {
3066 /* on older cards we have to enable large frames */
3067
3068 vp->large_frames = dev->mtu > 1500 || enable;
3069
a095cfc4 3070 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
1da177e4
LT		 3071 if (vp->large_frames)
3072 mac_ctrl |= 0x40;
3073 else
3074 mac_ctrl &= ~0x40;
a095cfc4 3075 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
1da177e4 3076 }
1da177e4
LT		 3077}
3078#else
3079
3080static void set_8021q_mode(struct net_device *dev, int enable)
3081{
3082}
3083
3084
3085#endif
3086
3087/* MII transceiver control section.
3088 Read and write the MII registers using software-generated serial
3089 MDIO protocol. See the MII specifications or DP83840A data sheet
3090 for details. */
3091
3092/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3093 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3094 "overclocking" issues. */
a095cfc4
BH		 3095static void mdio_delay(struct vortex_private *vp)
3096{
3097 window_read32(vp, 4, Wn4_PhysicalMgmt);
3098}
1da177e4
LT		 3099
3100#define MDIO_SHIFT_CLK 0x01
3101#define MDIO_DIR_WRITE 0x04
3102#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3103#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3104#define MDIO_DATA_READ 0x02
3105#define MDIO_ENB_IN 0x00
3106
3107/* Generate the preamble required for initial synchronization and
3108 a few older transceivers. */
a095cfc4 3109static void mdio_sync(struct vortex_private *vp, int bits)
1da177e4 3110{
1da177e4
LT		 3111 /* Establish sync by sending at least 32 logic ones. */
3112 while (-- bits >= 0) {
a095cfc4
BH		 3113 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3114 mdio_delay(vp);
3115 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3116 4, Wn4_PhysicalMgmt);
3117 mdio_delay(vp);
1da177e4
LT		 3118 }
3119}
3120
3121static int mdio_read(struct net_device *dev, int phy_id, int location)
3122{
3123 int i;
62afe595 3124 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3125 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3126 unsigned int retval = 0;
1da177e4 3127
de847272
BH		 3128 spin_lock_bh(&vp->mii_lock);
3129
1da177e4 3130 if (mii_preamble_required)
a095cfc4 3131 mdio_sync(vp, 32);
1da177e4
LT		 3132
3133 /* Shift the read command bits out. */
3134 for (i = 14; i >= 0; i--) {
3135 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3136 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3137 mdio_delay(vp);
3138 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3139 4, Wn4_PhysicalMgmt);
3140 mdio_delay(vp);
1da177e4
LT		 3141 }
3142 /* Read the two transition, 16 data, and wire-idle bits. */
3143 for (i = 19; i > 0; i--) {
a095cfc4
BH		 3144 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3145 mdio_delay(vp);
3146 retval = (retval << 1) |
3147 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3148 MDIO_DATA_READ) ? 1 : 0);
3149 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3150 4, Wn4_PhysicalMgmt);
3151 mdio_delay(vp);
1da177e4 3152 }
de847272
BH		 3153
3154 spin_unlock_bh(&vp->mii_lock);
3155
1da177e4
LT		 3156 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3157}
3158
3159static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3160{
62afe595 3161 struct vortex_private *vp = netdev_priv(dev);
1da177e4 3162 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
1da177e4
LT		 3163 int i;
3164
de847272
BH		 3165 spin_lock_bh(&vp->mii_lock);
3166
1da177e4 3167 if (mii_preamble_required)
a095cfc4 3168 mdio_sync(vp, 32);
1da177e4
LT		 3169
3170 /* Shift the command bits out. */
3171 for (i = 31; i >= 0; i--) {
3172 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3173 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3174 mdio_delay(vp);
3175 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3176 4, Wn4_PhysicalMgmt);
3177 mdio_delay(vp);
1da177e4
LT		 3178 }
3179 /* Leave the interface idle. */
3180 for (i = 1; i >= 0; i--) {
a095cfc4
BH		 3181 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3182 mdio_delay(vp);
3183 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3184 4, Wn4_PhysicalMgmt);
3185 mdio_delay(vp);
1da177e4 3186 }
de847272
BH		 3187
3188 spin_unlock_bh(&vp->mii_lock);
1da177e4 3189}
a880c4cd 3190
1da177e4
LT		 3191/* ACPI: Advanced Configuration and Power Interface. */
3192/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3193static void acpi_set_WOL(struct net_device *dev)
3194{
3195 struct vortex_private *vp = netdev_priv(dev);
62afe595 3196 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3197
c17931c5
SK		 3198 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3199
1da177e4
LT		 3200 if (vp->enable_wol) {
3201 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
a095cfc4 3202 window_write16(vp, 2, 7, 0x0c);
1da177e4 3203 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3204 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3205 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3206
1a1769f3 3207 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3208 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3209
3210 vp->enable_wol = 0;
3211 return;
3212 }
3c8fad18 3213
3fd6c88e
JB		 3214 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3215 return;
3216
3c8fad18
DR		 3217 /* Change the power state to D3; RxEnable doesn't take effect. */
3218 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3219 }
1da177e4
LT		 3220}
3221
3222
a880c4cd 3223static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3224{
3225 struct net_device *dev = pci_get_drvdata(pdev);
3226 struct vortex_private *vp;
3227
3228 if (!dev) {
39738e16 3229 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3230 BUG();
3231 }
3232
3233 vp = netdev_priv(dev);
3234
62afe595
JL		 3235 if (vp->cb_fn_base)
3236 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3237
1da177e4
LT		 3238 unregister_netdev(dev);
3239
3240 if (VORTEX_PCI(vp)) {
3241 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3242 if (vp->pm_state_valid)
3243 pci_restore_state(VORTEX_PCI(vp));
3244 pci_disable_device(VORTEX_PCI(vp));
3245 }
3246 /* Should really use issue_and_wait() here */
62afe595
JL		 3247 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3248 vp->ioaddr + EL3_CMD);
3249
3250 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3251
3252 pci_free_consistent(pdev,
3253 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3254 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3255 vp->rx_ring,
3256 vp->rx_ring_dma);
3257 if (vp->must_free_region)
3258 release_region(dev->base_addr, vp->io_size);
3259 free_netdev(dev);
3260}
3261
3262
3263static struct pci_driver vortex_driver = {
3264 .name = "3c59x",
3265 .probe = vortex_init_one,
3266 .remove = __devexit_p(vortex_remove_one),
3267 .id_table = vortex_pci_tbl,
7bfc4ab5 3268 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3269};
3270
3271
3272static int vortex_have_pci;
3273static int vortex_have_eisa;
3274
3275
a880c4cd 3276static int __init vortex_init(void)
1da177e4
LT		 3277{
3278 int pci_rc, eisa_rc;
3279
29917620 3280 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3281 eisa_rc = vortex_eisa_init();
3282
3283 if (pci_rc == 0)
3284 vortex_have_pci = 1;
3285 if (eisa_rc > 0)
3286 vortex_have_eisa = 1;
3287
3288 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3289}
3290
3291
a880c4cd 3292static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3293{
3294 struct vortex_private *vp;
62afe595 3295 void __iomem *ioaddr;
1da177e4
LT		 3296
3297#ifdef CONFIG_EISA
3298 /* Take care of the EISA devices */
a880c4cd 3299 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3300#endif
6aa20a22 3301
1da177e4 3302 if (compaq_net_device) {
454d7c9b 3303 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3304 ioaddr = ioport_map(compaq_net_device->base_addr,
3305 VORTEX_TOTAL_SIZE);
1da177e4 3306
a880c4cd
SK		 3307 unregister_netdev(compaq_net_device);
3308 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3309 release_region(compaq_net_device->base_addr,
3310 VORTEX_TOTAL_SIZE);
1da177e4 3311
a880c4cd 3312 free_netdev(compaq_net_device);
1da177e4
LT		 3313 }
3314}
3315
3316
a880c4cd 3317static void __exit vortex_cleanup(void)
1da177e4
LT		 3318{
3319 if (vortex_have_pci)
a880c4cd 3320 pci_unregister_driver(&vortex_driver);
1da177e4 3321 if (vortex_have_eisa)
a880c4cd 3322 vortex_eisa_cleanup();
1da177e4
LT		 3323}
3324
3325
3326module_init(vortex_init);
3327module_exit(vortex_cleanup);
Linux kernel - Deliverables
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