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1da177e4 LT |
1 | /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */ |
2 | /* | |
3 | Written 1998-2000 by Donald Becker. | |
4 | ||
fdecea66 | 5 | Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please |
1da177e4 LT |
6 | send all bug reports to me, and not to Donald Becker, as this code |
7 | has been heavily modified from Donald's original version. | |
8 | ||
9 | This software may be used and distributed according to the terms of | |
10 | the GNU General Public License (GPL), incorporated herein by reference. | |
11 | Drivers based on or derived from this code fall under the GPL and must | |
12 | retain the authorship, copyright and license notice. This file is not | |
13 | a complete program and may only be used when the entire operating | |
14 | system is licensed under the GPL. | |
15 | ||
16 | The information below comes from Donald Becker's original driver: | |
17 | ||
18 | The author may be reached as becker@scyld.com, or C/O | |
19 | Scyld Computing Corporation | |
20 | 410 Severn Ave., Suite 210 | |
21 | Annapolis MD 21403 | |
22 | ||
23 | Support and updates available at | |
24 | http://www.scyld.com/network/starfire.html | |
03a8c661 | 25 | [link no longer provides useful info -jgarzik] |
1da177e4 | 26 | |
1da177e4 LT |
27 | */ |
28 | ||
29 | #define DRV_NAME "starfire" | |
a6676019 FR |
30 | #define DRV_VERSION "2.1" |
31 | #define DRV_RELDATE "July 6, 2008" | |
1da177e4 | 32 | |
a6b7a407 | 33 | #include <linux/interrupt.h> |
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
fdecea66 JG |
41 | #include <linux/crc32.h> |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/if_vlan.h> | |
d7fe0f24 | 45 | #include <linux/mm.h> |
cfc3a44c | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
48 | #include <asm/uaccess.h> | |
49 | #include <asm/io.h> | |
50 | ||
1da177e4 LT |
51 | /* |
52 | * The current frame processor firmware fails to checksum a fragment | |
53 | * of length 1. If and when this is fixed, the #define below can be removed. | |
54 | */ | |
55 | #define HAS_BROKEN_FIRMWARE | |
67974231 IB |
56 | |
57 | /* | |
58 | * If using the broken firmware, data must be padded to the next 32-bit boundary. | |
59 | */ | |
60 | #ifdef HAS_BROKEN_FIRMWARE | |
61 | #define PADDING_MASK 3 | |
62 | #endif | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Define this if using the driver with the zero-copy patch | |
66 | */ | |
1da177e4 | 67 | #define ZEROCOPY |
1da177e4 LT |
68 | |
69 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
70 | #define VLAN_SUPPORT | |
71 | #endif | |
72 | ||
1da177e4 LT |
73 | /* The user-configurable values. |
74 | These may be modified when a driver module is loaded.*/ | |
75 | ||
76 | /* Used for tuning interrupt latency vs. overhead. */ | |
77 | static int intr_latency; | |
78 | static int small_frames; | |
79 | ||
80 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
81 | static int max_interrupt_work = 20; | |
82 | static int mtu; | |
83 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
84 | The Starfire has a 512 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 512; |
1da177e4 | 86 | /* Whether to do TCP/UDP checksums in hardware */ |
1da177e4 | 87 | static int enable_hw_cksum = 1; |
1da177e4 LT |
88 | |
89 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
90 | /* | |
91 | * Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
92 | * Setting to > 1518 effectively disables this feature. | |
93 | * | |
94 | * NOTE: | |
95 | * The ia64 doesn't allow for unaligned loads even of integers being | |
96 | * misaligned on a 2 byte boundary. Thus always force copying of | |
97 | * packets as the starfire doesn't allow for misaligned DMAs ;-( | |
98 | * 23/10/2000 - Jes | |
99 | * | |
100 | * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64, | |
101 | * at least, having unaligned frames leads to a rather serious performance | |
102 | * penalty. -Ion | |
103 | */ | |
104 | #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) | |
105 | static int rx_copybreak = PKT_BUF_SZ; | |
106 | #else | |
107 | static int rx_copybreak /* = 0 */; | |
108 | #endif | |
109 | ||
110 | /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */ | |
111 | #ifdef __sparc__ | |
112 | #define DMA_BURST_SIZE 64 | |
113 | #else | |
114 | #define DMA_BURST_SIZE 128 | |
115 | #endif | |
116 | ||
1da177e4 LT |
117 | /* Operational parameters that are set at compile time. */ |
118 | ||
119 | /* The "native" ring sizes are either 256 or 2048. | |
120 | However in some modes a descriptor may be marked to wrap the ring earlier. | |
121 | */ | |
122 | #define RX_RING_SIZE 256 | |
123 | #define TX_RING_SIZE 32 | |
124 | /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */ | |
125 | #define DONE_Q_SIZE 1024 | |
126 | /* All queues must be aligned on a 256-byte boundary */ | |
127 | #define QUEUE_ALIGN 256 | |
128 | ||
129 | #if RX_RING_SIZE > 256 | |
130 | #define RX_Q_ENTRIES Rx2048QEntries | |
131 | #else | |
132 | #define RX_Q_ENTRIES Rx256QEntries | |
133 | #endif | |
134 | ||
135 | /* Operational parameters that usually are not changed. */ | |
136 | /* Time in jiffies before concluding the transmitter is hung. */ | |
137 | #define TX_TIMEOUT (2 * HZ) | |
138 | ||
1591cb60 | 139 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
1da177e4 LT |
140 | /* 64-bit dma_addr_t */ |
141 | #define ADDR_64BITS /* This chip uses 64 bit addresses. */ | |
88b1943b | 142 | #define netdrv_addr_t __le64 |
1da177e4 LT |
143 | #define cpu_to_dma(x) cpu_to_le64(x) |
144 | #define dma_to_cpu(x) le64_to_cpu(x) | |
145 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit | |
146 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit | |
147 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit | |
148 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit | |
149 | #define RX_DESC_ADDR_SIZE RxDescAddr64bit | |
150 | #else /* 32-bit dma_addr_t */ | |
88b1943b | 151 | #define netdrv_addr_t __le32 |
1da177e4 LT |
152 | #define cpu_to_dma(x) cpu_to_le32(x) |
153 | #define dma_to_cpu(x) le32_to_cpu(x) | |
154 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit | |
155 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit | |
156 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit | |
157 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit | |
158 | #define RX_DESC_ADDR_SIZE RxDescAddr32bit | |
159 | #endif | |
160 | ||
1da177e4 LT |
161 | #define skb_first_frag_len(skb) skb_headlen(skb) |
162 | #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) | |
1da177e4 | 163 | |
cfc3a44c JSR |
164 | /* Firmware names */ |
165 | #define FIRMWARE_RX "adaptec/starfire_rx.bin" | |
166 | #define FIRMWARE_TX "adaptec/starfire_tx.bin" | |
167 | ||
1da177e4 | 168 | /* These identify the driver base version and may not be removed. */ |
d3ace588 | 169 | static const char version[] = |
1da177e4 | 170 | KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" |
ad361c98 | 171 | " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; |
1da177e4 LT |
172 | |
173 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
174 | MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver"); | |
175 | MODULE_LICENSE("GPL"); | |
fdecea66 | 176 | MODULE_VERSION(DRV_VERSION); |
cfc3a44c JSR |
177 | MODULE_FIRMWARE(FIRMWARE_RX); |
178 | MODULE_FIRMWARE(FIRMWARE_TX); | |
1da177e4 LT |
179 | |
180 | module_param(max_interrupt_work, int, 0); | |
181 | module_param(mtu, int, 0); | |
182 | module_param(debug, int, 0); | |
183 | module_param(rx_copybreak, int, 0); | |
184 | module_param(intr_latency, int, 0); | |
185 | module_param(small_frames, int, 0); | |
1da177e4 LT |
186 | module_param(enable_hw_cksum, int, 0); |
187 | MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt"); | |
188 | MODULE_PARM_DESC(mtu, "MTU (all boards)"); | |
189 | MODULE_PARM_DESC(debug, "Debug level (0-6)"); | |
190 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); | |
191 | MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds"); | |
192 | MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)"); | |
1da177e4 LT |
193 | MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)"); |
194 | ||
195 | /* | |
196 | Theory of Operation | |
197 | ||
198 | I. Board Compatibility | |
199 | ||
200 | This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter. | |
201 | ||
202 | II. Board-specific settings | |
203 | ||
204 | III. Driver operation | |
205 | ||
206 | IIIa. Ring buffers | |
207 | ||
208 | The Starfire hardware uses multiple fixed-size descriptor queues/rings. The | |
209 | ring sizes are set fixed by the hardware, but may optionally be wrapped | |
210 | earlier by the END bit in the descriptor. | |
211 | This driver uses that hardware queue size for the Rx ring, where a large | |
212 | number of entries has no ill effect beyond increases the potential backlog. | |
213 | The Tx ring is wrapped with the END bit, since a large hardware Tx queue | |
214 | disables the queue layer priority ordering and we have no mechanism to | |
215 | utilize the hardware two-level priority queue. When modifying the | |
216 | RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning | |
217 | levels. | |
218 | ||
219 | IIIb/c. Transmit/Receive Structure | |
220 | ||
221 | See the Adaptec manual for the many possible structures, and options for | |
222 | each structure. There are far too many to document all of them here. | |
223 | ||
224 | For transmit this driver uses type 0/1 transmit descriptors (depending | |
225 | on the 32/64 bitness of the architecture), and relies on automatic | |
226 | minimum-length padding. It does not use the completion queue | |
227 | consumer index, but instead checks for non-zero status entries. | |
228 | ||
fdecea66 | 229 | For receive this driver uses type 2/3 receive descriptors. The driver |
1da177e4 LT |
230 | allocates full frame size skbuffs for the Rx ring buffers, so all frames |
231 | should fit in a single descriptor. The driver does not use the completion | |
232 | queue consumer index, but instead checks for non-zero status entries. | |
233 | ||
234 | When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff | |
235 | is allocated and the frame is copied to the new skbuff. When the incoming | |
236 | frame is larger, the skbuff is passed directly up the protocol stack. | |
237 | Buffers consumed this way are replaced by newly allocated skbuffs in a later | |
238 | phase of receive. | |
239 | ||
240 | A notable aspect of operation is that unaligned buffers are not permitted by | |
241 | the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame | |
242 | isn't longword aligned, which may cause problems on some machine | |
243 | e.g. Alphas and IA64. For these architectures, the driver is forced to copy | |
244 | the frame into a new skbuff unconditionally. Copied frames are put into the | |
245 | skbuff at an offset of "+2", thus 16-byte aligning the IP header. | |
246 | ||
247 | IIId. Synchronization | |
248 | ||
249 | The driver runs as two independent, single-threaded flows of control. One | |
250 | is the send-packet routine, which enforces single-threaded use by the | |
251 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
252 | threaded by the hardware and interrupt handling software. | |
253 | ||
254 | The send packet thread has partial control over the Tx ring and the netif_queue | |
255 | status. If the number of free Tx slots in the ring falls below a certain number | |
256 | (currently hardcoded to 4), it signals the upper layer to stop the queue. | |
257 | ||
258 | The interrupt handler has exclusive control over the Rx ring and records stats | |
259 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
260 | empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the | |
261 | number of free Tx slow is above the threshold, it signals the upper layer to | |
262 | restart the queue. | |
263 | ||
264 | IV. Notes | |
265 | ||
266 | IVb. References | |
267 | ||
268 | The Adaptec Starfire manuals, available only from Adaptec. | |
269 | http://www.scyld.com/expert/100mbps.html | |
270 | http://www.scyld.com/expert/NWay.html | |
271 | ||
272 | IVc. Errata | |
273 | ||
274 | - StopOnPerr is broken, don't enable | |
275 | - Hardware ethernet padding exposes random data, perform software padding | |
276 | instead (unverified -- works correctly for all the hardware I have) | |
277 | ||
278 | */ | |
279 | ||
fdecea66 | 280 | |
1da177e4 LT |
281 | |
282 | enum chip_capability_flags {CanHaveMII=1, }; | |
283 | ||
284 | enum chipset { | |
285 | CH_6915 = 0, | |
286 | }; | |
287 | ||
9baa3c34 | 288 | static const struct pci_device_id starfire_pci_tbl[] = { |
d08336e9 | 289 | { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 }, |
1da177e4 LT |
290 | { 0, } |
291 | }; | |
292 | MODULE_DEVICE_TABLE(pci, starfire_pci_tbl); | |
293 | ||
294 | /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */ | |
f71e1309 | 295 | static const struct chip_info { |
1da177e4 LT |
296 | const char *name; |
297 | int drv_flags; | |
d3ace588 | 298 | } netdrv_tbl[] = { |
1da177e4 LT |
299 | { "Adaptec Starfire 6915", CanHaveMII }, |
300 | }; | |
301 | ||
302 | ||
303 | /* Offsets to the device registers. | |
304 | Unlike software-only systems, device drivers interact with complex hardware. | |
305 | It's not useful to define symbolic names for every register bit in the | |
306 | device. The name can only partially document the semantics and make | |
307 | the driver longer and more difficult to read. | |
308 | In general, only the important configuration values or bits changed | |
309 | multiple times should be defined symbolically. | |
310 | */ | |
311 | enum register_offsets { | |
312 | PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074, | |
313 | IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088, | |
314 | MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000, | |
315 | GPIOCtrl=0x5008C, TxDescCtrl=0x50090, | |
316 | TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */ | |
317 | TxRingHiAddr=0x5009C, /* 64 bit address extension. */ | |
318 | TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4, | |
319 | TxThreshold=0x500B0, | |
320 | CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8, | |
321 | RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0, | |
322 | CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0, | |
323 | RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0, | |
324 | RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4, | |
325 | TxMode=0x55000, VlanType=0x55064, | |
326 | PerfFilterTable=0x56000, HashTable=0x56100, | |
327 | TxGfpMem=0x58000, RxGfpMem=0x5a000, | |
328 | }; | |
329 | ||
330 | /* | |
331 | * Bits in the interrupt status/mask registers. | |
332 | * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register | |
333 | * enables all the interrupt sources that are or'ed into those status bits. | |
334 | */ | |
335 | enum intr_status_bits { | |
336 | IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000, | |
337 | IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000, | |
338 | IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000, | |
339 | IntrTxComplQLow=0x200000, IntrPCI=0x100000, | |
340 | IntrDMAErr=0x080000, IntrTxDataLow=0x040000, | |
341 | IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000, | |
342 | IntrNormalSummary=0x8000, IntrTxDone=0x4000, | |
343 | IntrTxDMADone=0x2000, IntrTxEmpty=0x1000, | |
344 | IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400, | |
345 | IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100, | |
346 | IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40, | |
347 | IntrNoTxCsum=0x20, IntrTxBadID=0x10, | |
348 | IntrHiPriTxBadID=0x08, IntrRxGfp=0x04, | |
349 | IntrTxGfp=0x02, IntrPCIPad=0x01, | |
350 | /* not quite bits */ | |
351 | IntrRxDone=IntrRxQ2Done | IntrRxQ1Done, | |
352 | IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low, | |
353 | IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe, | |
354 | }; | |
355 | ||
356 | /* Bits in the RxFilterMode register. */ | |
357 | enum rx_mode_bits { | |
358 | AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01, | |
359 | AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30, | |
360 | PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200, | |
361 | WakeupOnGFP=0x0800, | |
362 | }; | |
363 | ||
364 | /* Bits in the TxMode register */ | |
365 | enum tx_mode_bits { | |
366 | MiiSoftReset=0x8000, MIILoopback=0x4000, | |
367 | TxFlowEnable=0x0800, RxFlowEnable=0x0400, | |
368 | PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01, | |
369 | }; | |
370 | ||
371 | /* Bits in the TxDescCtrl register. */ | |
372 | enum tx_ctrl_bits { | |
373 | TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20, | |
374 | TxDescSpace128=0x30, TxDescSpace256=0x40, | |
375 | TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02, | |
376 | TxDescType3=0x03, TxDescType4=0x04, | |
377 | TxNoDMACompletion=0x08, | |
378 | TxDescQAddr64bit=0x80, TxDescQAddr32bit=0, | |
379 | TxHiPriFIFOThreshShift=24, TxPadLenShift=16, | |
380 | TxDMABurstSizeShift=8, | |
381 | }; | |
382 | ||
383 | /* Bits in the RxDescQCtrl register. */ | |
384 | enum rx_ctrl_bits { | |
385 | RxBufferLenShift=16, RxMinDescrThreshShift=0, | |
386 | RxPrefetchMode=0x8000, RxVariableQ=0x2000, | |
387 | Rx2048QEntries=0x4000, Rx256QEntries=0, | |
388 | RxDescAddr64bit=0x1000, RxDescAddr32bit=0, | |
389 | RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0, | |
390 | RxDescSpace4=0x000, RxDescSpace8=0x100, | |
391 | RxDescSpace16=0x200, RxDescSpace32=0x300, | |
392 | RxDescSpace64=0x400, RxDescSpace128=0x500, | |
393 | RxConsumerWrEn=0x80, | |
394 | }; | |
395 | ||
396 | /* Bits in the RxDMACtrl register. */ | |
397 | enum rx_dmactrl_bits { | |
398 | RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000, | |
399 | RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000, | |
400 | RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000, | |
401 | RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000, | |
402 | RxChecksumRejectTCPOnly=0x01000000, | |
403 | RxCompletionQ2Enable=0x800000, | |
404 | RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000, | |
405 | RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000, | |
406 | RxDMAQ2NonIP=0x400000, | |
407 | RxUseBackupQueue=0x080000, RxDMACRC=0x040000, | |
408 | RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8, | |
409 | RxBurstSizeShift=0, | |
410 | }; | |
411 | ||
412 | /* Bits in the RxCompletionAddr register */ | |
413 | enum rx_compl_bits { | |
414 | RxComplQAddr64bit=0x80, RxComplQAddr32bit=0, | |
415 | RxComplProducerWrEn=0x40, | |
416 | RxComplType0=0x00, RxComplType1=0x10, | |
417 | RxComplType2=0x20, RxComplType3=0x30, | |
418 | RxComplThreshShift=0, | |
419 | }; | |
420 | ||
421 | /* Bits in the TxCompletionAddr register */ | |
422 | enum tx_compl_bits { | |
423 | TxComplQAddr64bit=0x80, TxComplQAddr32bit=0, | |
424 | TxComplProducerWrEn=0x40, | |
425 | TxComplIntrStatus=0x20, | |
426 | CommonQueueMode=0x10, | |
427 | TxComplThreshShift=0, | |
428 | }; | |
429 | ||
430 | /* Bits in the GenCtrl register */ | |
431 | enum gen_ctrl_bits { | |
432 | RxEnable=0x05, TxEnable=0x0a, | |
433 | RxGFPEnable=0x10, TxGFPEnable=0x20, | |
434 | }; | |
435 | ||
436 | /* Bits in the IntrTimerCtrl register */ | |
437 | enum intr_ctrl_bits { | |
438 | Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100, | |
439 | SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600, | |
440 | IntrLatencyMask=0x1f, | |
441 | }; | |
442 | ||
443 | /* The Rx and Tx buffer descriptors. */ | |
444 | struct starfire_rx_desc { | |
88b1943b | 445 | netdrv_addr_t rxaddr; |
1da177e4 LT |
446 | }; |
447 | enum rx_desc_bits { | |
448 | RxDescValid=1, RxDescEndRing=2, | |
449 | }; | |
450 | ||
451 | /* Completion queue entry. */ | |
452 | struct short_rx_done_desc { | |
88b1943b | 453 | __le32 status; /* Low 16 bits is length. */ |
1da177e4 LT |
454 | }; |
455 | struct basic_rx_done_desc { | |
88b1943b AV |
456 | __le32 status; /* Low 16 bits is length. */ |
457 | __le16 vlanid; | |
458 | __le16 status2; | |
1da177e4 LT |
459 | }; |
460 | struct csum_rx_done_desc { | |
88b1943b AV |
461 | __le32 status; /* Low 16 bits is length. */ |
462 | __le16 csum; /* Partial checksum */ | |
463 | __le16 status2; | |
1da177e4 LT |
464 | }; |
465 | struct full_rx_done_desc { | |
88b1943b AV |
466 | __le32 status; /* Low 16 bits is length. */ |
467 | __le16 status3; | |
468 | __le16 status2; | |
469 | __le16 vlanid; | |
470 | __le16 csum; /* partial checksum */ | |
471 | __le32 timestamp; | |
1da177e4 LT |
472 | }; |
473 | /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ | |
1da177e4 LT |
474 | #ifdef VLAN_SUPPORT |
475 | typedef struct full_rx_done_desc rx_done_desc; | |
476 | #define RxComplType RxComplType3 | |
477 | #else /* not VLAN_SUPPORT */ | |
478 | typedef struct csum_rx_done_desc rx_done_desc; | |
479 | #define RxComplType RxComplType2 | |
480 | #endif /* not VLAN_SUPPORT */ | |
1da177e4 LT |
481 | |
482 | enum rx_done_bits { | |
483 | RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000, | |
484 | }; | |
485 | ||
486 | /* Type 1 Tx descriptor. */ | |
487 | struct starfire_tx_desc_1 { | |
88b1943b AV |
488 | __le32 status; /* Upper bits are status, lower 16 length. */ |
489 | __le32 addr; | |
1da177e4 LT |
490 | }; |
491 | ||
492 | /* Type 2 Tx descriptor. */ | |
493 | struct starfire_tx_desc_2 { | |
88b1943b AV |
494 | __le32 status; /* Upper bits are status, lower 16 length. */ |
495 | __le32 reserved; | |
496 | __le64 addr; | |
1da177e4 LT |
497 | }; |
498 | ||
499 | #ifdef ADDR_64BITS | |
500 | typedef struct starfire_tx_desc_2 starfire_tx_desc; | |
501 | #define TX_DESC_TYPE TxDescType2 | |
502 | #else /* not ADDR_64BITS */ | |
503 | typedef struct starfire_tx_desc_1 starfire_tx_desc; | |
504 | #define TX_DESC_TYPE TxDescType1 | |
505 | #endif /* not ADDR_64BITS */ | |
506 | #define TX_DESC_SPACING TxDescSpaceUnlim | |
507 | ||
508 | enum tx_desc_bits { | |
509 | TxDescID=0xB0000000, | |
510 | TxCRCEn=0x01000000, TxDescIntr=0x08000000, | |
511 | TxRingWrap=0x04000000, TxCalTCP=0x02000000, | |
512 | }; | |
513 | struct tx_done_desc { | |
88b1943b | 514 | __le32 status; /* timestamp, index. */ |
1da177e4 | 515 | #if 0 |
88b1943b | 516 | __le32 intrstatus; /* interrupt status */ |
1da177e4 LT |
517 | #endif |
518 | }; | |
519 | ||
520 | struct rx_ring_info { | |
521 | struct sk_buff *skb; | |
522 | dma_addr_t mapping; | |
523 | }; | |
524 | struct tx_ring_info { | |
525 | struct sk_buff *skb; | |
526 | dma_addr_t mapping; | |
527 | unsigned int used_slots; | |
528 | }; | |
529 | ||
530 | #define PHY_CNT 2 | |
531 | struct netdev_private { | |
532 | /* Descriptor rings first for alignment. */ | |
533 | struct starfire_rx_desc *rx_ring; | |
534 | starfire_tx_desc *tx_ring; | |
535 | dma_addr_t rx_ring_dma; | |
536 | dma_addr_t tx_ring_dma; | |
537 | /* The addresses of rx/tx-in-place skbuffs. */ | |
538 | struct rx_ring_info rx_info[RX_RING_SIZE]; | |
539 | struct tx_ring_info tx_info[TX_RING_SIZE]; | |
540 | /* Pointers to completion queues (full pages). */ | |
541 | rx_done_desc *rx_done_q; | |
542 | dma_addr_t rx_done_q_dma; | |
543 | unsigned int rx_done; | |
544 | struct tx_done_desc *tx_done_q; | |
545 | dma_addr_t tx_done_q_dma; | |
546 | unsigned int tx_done; | |
bea3348e SH |
547 | struct napi_struct napi; |
548 | struct net_device *dev; | |
1da177e4 LT |
549 | struct pci_dev *pci_dev; |
550 | #ifdef VLAN_SUPPORT | |
5da96be5 | 551 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
1da177e4 LT |
552 | #endif |
553 | void *queue_mem; | |
554 | dma_addr_t queue_mem_dma; | |
555 | size_t queue_mem_size; | |
556 | ||
557 | /* Frequently used values: keep some adjacent for cache effect. */ | |
558 | spinlock_t lock; | |
559 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
560 | unsigned int cur_tx, dirty_tx, reap_tx; | |
561 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
562 | /* These values keep track of the transceiver/media in use. */ | |
563 | int speed100; /* Set if speed == 100MBit. */ | |
564 | u32 tx_mode; | |
565 | u32 intr_timer_ctrl; | |
566 | u8 tx_threshold; | |
567 | /* MII transceiver section. */ | |
568 | struct mii_if_info mii_if; /* MII lib hooks/info */ | |
569 | int phy_cnt; /* MII device addresses. */ | |
570 | unsigned char phys[PHY_CNT]; /* MII device addresses. */ | |
571 | void __iomem *base; | |
572 | }; | |
573 | ||
574 | ||
575 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
576 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
577 | static int netdev_open(struct net_device *dev); | |
578 | static void check_duplex(struct net_device *dev); | |
579 | static void tx_timeout(struct net_device *dev); | |
580 | static void init_ring(struct net_device *dev); | |
61357325 | 581 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); |
7d12e780 | 582 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 LT |
583 | static void netdev_error(struct net_device *dev, int intr_status); |
584 | static int __netdev_rx(struct net_device *dev, int *quota); | |
a6676019 | 585 | static int netdev_poll(struct napi_struct *napi, int budget); |
1da177e4 LT |
586 | static void refill_rx_ring(struct net_device *dev); |
587 | static void netdev_error(struct net_device *dev, int intr_status); | |
588 | static void set_rx_mode(struct net_device *dev); | |
589 | static struct net_device_stats *get_stats(struct net_device *dev); | |
590 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
591 | static int netdev_close(struct net_device *dev); | |
592 | static void netdev_media_change(struct net_device *dev); | |
7282d491 | 593 | static const struct ethtool_ops ethtool_ops; |
1da177e4 LT |
594 | |
595 | ||
596 | #ifdef VLAN_SUPPORT | |
80d5c368 PM |
597 | static int netdev_vlan_rx_add_vid(struct net_device *dev, |
598 | __be16 proto, u16 vid) | |
1da177e4 LT |
599 | { |
600 | struct netdev_private *np = netdev_priv(dev); | |
601 | ||
602 | spin_lock(&np->lock); | |
603 | if (debug > 1) | |
604 | printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid); | |
5da96be5 | 605 | set_bit(vid, np->active_vlans); |
1da177e4 LT |
606 | set_rx_mode(dev); |
607 | spin_unlock(&np->lock); | |
8e586137 JP |
608 | |
609 | return 0; | |
1da177e4 LT |
610 | } |
611 | ||
80d5c368 PM |
612 | static int netdev_vlan_rx_kill_vid(struct net_device *dev, |
613 | __be16 proto, u16 vid) | |
1da177e4 LT |
614 | { |
615 | struct netdev_private *np = netdev_priv(dev); | |
616 | ||
617 | spin_lock(&np->lock); | |
618 | if (debug > 1) | |
619 | printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid); | |
5da96be5 | 620 | clear_bit(vid, np->active_vlans); |
1da177e4 LT |
621 | set_rx_mode(dev); |
622 | spin_unlock(&np->lock); | |
8e586137 JP |
623 | |
624 | return 0; | |
1da177e4 LT |
625 | } |
626 | #endif /* VLAN_SUPPORT */ | |
627 | ||
628 | ||
4fc8006e SH |
629 | static const struct net_device_ops netdev_ops = { |
630 | .ndo_open = netdev_open, | |
631 | .ndo_stop = netdev_close, | |
632 | .ndo_start_xmit = start_tx, | |
5da96be5 JP |
633 | .ndo_tx_timeout = tx_timeout, |
634 | .ndo_get_stats = get_stats, | |
afc4b13d | 635 | .ndo_set_rx_mode = set_rx_mode, |
5da96be5 | 636 | .ndo_do_ioctl = netdev_ioctl, |
4fc8006e | 637 | .ndo_change_mtu = eth_change_mtu, |
5da96be5 | 638 | .ndo_set_mac_address = eth_mac_addr, |
4fc8006e SH |
639 | .ndo_validate_addr = eth_validate_addr, |
640 | #ifdef VLAN_SUPPORT | |
4fc8006e SH |
641 | .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid, |
642 | .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid, | |
643 | #endif | |
644 | }; | |
645 | ||
d3ace588 | 646 | static int starfire_init_one(struct pci_dev *pdev, |
1dd06ae8 | 647 | const struct pci_device_id *ent) |
1da177e4 | 648 | { |
2d5fb628 | 649 | struct device *d = &pdev->dev; |
1da177e4 | 650 | struct netdev_private *np; |
2d5fb628 | 651 | int i, irq, chip_idx = ent->driver_data; |
1da177e4 | 652 | struct net_device *dev; |
1da177e4 LT |
653 | long ioaddr; |
654 | void __iomem *base; | |
655 | int drv_flags, io_size; | |
656 | int boguscnt; | |
657 | ||
658 | /* when built into the kernel, we only print version if device is found */ | |
659 | #ifndef MODULE | |
660 | static int printed_version; | |
661 | if (!printed_version++) | |
662 | printk(version); | |
663 | #endif | |
664 | ||
1da177e4 LT |
665 | if (pci_enable_device (pdev)) |
666 | return -EIO; | |
667 | ||
668 | ioaddr = pci_resource_start(pdev, 0); | |
669 | io_size = pci_resource_len(pdev, 0); | |
670 | if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) { | |
2d5fb628 | 671 | dev_err(d, "no PCI MEM resources, aborting\n"); |
1da177e4 LT |
672 | return -ENODEV; |
673 | } | |
674 | ||
675 | dev = alloc_etherdev(sizeof(*np)); | |
41de8d4c | 676 | if (!dev) |
1da177e4 | 677 | return -ENOMEM; |
41de8d4c | 678 | |
1da177e4 LT |
679 | SET_NETDEV_DEV(dev, &pdev->dev); |
680 | ||
681 | irq = pdev->irq; | |
682 | ||
683 | if (pci_request_regions (pdev, DRV_NAME)) { | |
2d5fb628 | 684 | dev_err(d, "cannot reserve PCI resources, aborting\n"); |
1da177e4 LT |
685 | goto err_out_free_netdev; |
686 | } | |
687 | ||
1da177e4 LT |
688 | base = ioremap(ioaddr, io_size); |
689 | if (!base) { | |
2d5fb628 FR |
690 | dev_err(d, "cannot remap %#x @ %#lx, aborting\n", |
691 | io_size, ioaddr); | |
1da177e4 LT |
692 | goto err_out_free_res; |
693 | } | |
694 | ||
695 | pci_set_master(pdev); | |
696 | ||
697 | /* enable MWI -- it vastly improves Rx performance on sparc64 */ | |
694625c0 | 698 | pci_try_set_mwi(pdev); |
1da177e4 | 699 | |
1da177e4 LT |
700 | #ifdef ZEROCOPY |
701 | /* Starfire can do TCP/UDP checksumming */ | |
702 | if (enable_hw_cksum) | |
fdecea66 | 703 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
1da177e4 | 704 | #endif /* ZEROCOPY */ |
4fc8006e | 705 | |
1da177e4 | 706 | #ifdef VLAN_SUPPORT |
f646968f | 707 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER; |
1da177e4 LT |
708 | #endif /* VLAN_RX_KILL_VID */ |
709 | #ifdef ADDR_64BITS | |
710 | dev->features |= NETIF_F_HIGHDMA; | |
711 | #endif /* ADDR_64BITS */ | |
712 | ||
713 | /* Serial EEPROM reads are hidden by the hardware. */ | |
714 | for (i = 0; i < 6; i++) | |
715 | dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i); | |
716 | ||
717 | #if ! defined(final_version) /* Dump the EEPROM contents during development. */ | |
718 | if (debug > 4) | |
719 | for (i = 0; i < 0x20; i++) | |
720 | printk("%2.2x%s", | |
721 | (unsigned int)readb(base + EEPROMCtrl + i), | |
722 | i % 16 != 15 ? " " : "\n"); | |
723 | #endif | |
724 | ||
725 | /* Issue soft reset */ | |
726 | writel(MiiSoftReset, base + TxMode); | |
727 | udelay(1000); | |
728 | writel(0, base + TxMode); | |
729 | ||
730 | /* Reset the chip to erase previous misconfiguration. */ | |
731 | writel(1, base + PCIDeviceConfig); | |
732 | boguscnt = 1000; | |
733 | while (--boguscnt > 0) { | |
734 | udelay(10); | |
735 | if ((readl(base + PCIDeviceConfig) & 1) == 0) | |
736 | break; | |
737 | } | |
738 | if (boguscnt == 0) | |
739 | printk("%s: chipset reset never completed!\n", dev->name); | |
740 | /* wait a little longer */ | |
741 | udelay(1000); | |
742 | ||
1da177e4 | 743 | np = netdev_priv(dev); |
bea3348e | 744 | np->dev = dev; |
1da177e4 LT |
745 | np->base = base; |
746 | spin_lock_init(&np->lock); | |
747 | pci_set_drvdata(pdev, dev); | |
748 | ||
749 | np->pci_dev = pdev; | |
750 | ||
751 | np->mii_if.dev = dev; | |
752 | np->mii_if.mdio_read = mdio_read; | |
753 | np->mii_if.mdio_write = mdio_write; | |
754 | np->mii_if.phy_id_mask = 0x1f; | |
755 | np->mii_if.reg_num_mask = 0x1f; | |
756 | ||
757 | drv_flags = netdrv_tbl[chip_idx].drv_flags; | |
758 | ||
1da177e4 LT |
759 | np->speed100 = 1; |
760 | ||
761 | /* timer resolution is 128 * 0.8us */ | |
762 | np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) | | |
763 | Timer10X | EnableIntrMasking; | |
764 | ||
765 | if (small_frames > 0) { | |
766 | np->intr_timer_ctrl |= SmallFrameBypass; | |
767 | switch (small_frames) { | |
768 | case 1 ... 64: | |
769 | np->intr_timer_ctrl |= SmallFrame64; | |
770 | break; | |
771 | case 65 ... 128: | |
772 | np->intr_timer_ctrl |= SmallFrame128; | |
773 | break; | |
774 | case 129 ... 256: | |
775 | np->intr_timer_ctrl |= SmallFrame256; | |
776 | break; | |
777 | default: | |
778 | np->intr_timer_ctrl |= SmallFrame512; | |
779 | if (small_frames > 512) | |
780 | printk("Adjusting small_frames down to 512\n"); | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
4fc8006e | 785 | dev->netdev_ops = &netdev_ops; |
fdecea66 | 786 | dev->watchdog_timeo = TX_TIMEOUT; |
7ad24ea4 | 787 | dev->ethtool_ops = ðtool_ops; |
1da177e4 | 788 | |
4fc8006e SH |
789 | netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work); |
790 | ||
1da177e4 LT |
791 | if (mtu) |
792 | dev->mtu = mtu; | |
793 | ||
794 | if (register_netdev(dev)) | |
795 | goto err_out_cleardev; | |
796 | ||
e174961c | 797 | printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", |
0795af57 | 798 | dev->name, netdrv_tbl[chip_idx].name, base, |
e174961c | 799 | dev->dev_addr, irq); |
1da177e4 LT |
800 | |
801 | if (drv_flags & CanHaveMII) { | |
802 | int phy, phy_idx = 0; | |
803 | int mii_status; | |
804 | for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) { | |
805 | mdio_write(dev, phy, MII_BMCR, BMCR_RESET); | |
806 | mdelay(100); | |
807 | boguscnt = 1000; | |
808 | while (--boguscnt > 0) | |
809 | if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) | |
810 | break; | |
811 | if (boguscnt == 0) { | |
fdecea66 | 812 | printk("%s: PHY#%d reset never completed!\n", dev->name, phy); |
1da177e4 LT |
813 | continue; |
814 | } | |
815 | mii_status = mdio_read(dev, phy, MII_BMSR); | |
816 | if (mii_status != 0) { | |
817 | np->phys[phy_idx++] = phy; | |
818 | np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
819 | printk(KERN_INFO "%s: MII PHY found at address %d, status " | |
820 | "%#4.4x advertising %#4.4x.\n", | |
821 | dev->name, phy, mii_status, np->mii_if.advertising); | |
822 | /* there can be only one PHY on-board */ | |
823 | break; | |
824 | } | |
825 | } | |
826 | np->phy_cnt = phy_idx; | |
827 | if (np->phy_cnt > 0) | |
828 | np->mii_if.phy_id = np->phys[0]; | |
829 | else | |
830 | memset(&np->mii_if, 0, sizeof(np->mii_if)); | |
831 | } | |
832 | ||
833 | printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n", | |
834 | dev->name, enable_hw_cksum ? "enabled" : "disabled"); | |
835 | return 0; | |
836 | ||
837 | err_out_cleardev: | |
1da177e4 LT |
838 | iounmap(base); |
839 | err_out_free_res: | |
840 | pci_release_regions (pdev); | |
841 | err_out_free_netdev: | |
842 | free_netdev(dev); | |
843 | return -ENODEV; | |
844 | } | |
845 | ||
846 | ||
847 | /* Read the MII Management Data I/O (MDIO) interfaces. */ | |
848 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
849 | { | |
850 | struct netdev_private *np = netdev_priv(dev); | |
851 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
852 | int result, boguscnt=1000; | |
853 | /* ??? Should we add a busy-wait here? */ | |
e4c3c13c | 854 | do { |
1da177e4 | 855 | result = readl(mdio_addr); |
e4c3c13c | 856 | } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0); |
1da177e4 LT |
857 | if (boguscnt == 0) |
858 | return 0; | |
859 | if ((result & 0xffff) == 0xffff) | |
860 | return 0; | |
861 | return result & 0xffff; | |
862 | } | |
863 | ||
864 | ||
865 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
866 | { | |
867 | struct netdev_private *np = netdev_priv(dev); | |
868 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
869 | writel(value, mdio_addr); | |
870 | /* The busy-wait will occur before a read. */ | |
871 | } | |
872 | ||
873 | ||
874 | static int netdev_open(struct net_device *dev) | |
875 | { | |
cfc3a44c JSR |
876 | const struct firmware *fw_rx, *fw_tx; |
877 | const __be32 *fw_rx_data, *fw_tx_data; | |
1da177e4 LT |
878 | struct netdev_private *np = netdev_priv(dev); |
879 | void __iomem *ioaddr = np->base; | |
ea8f2ed0 | 880 | const int irq = np->pci_dev->irq; |
1da177e4 | 881 | int i, retval; |
cfc3a44c | 882 | size_t tx_size, rx_size; |
1da177e4 LT |
883 | size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size; |
884 | ||
885 | /* Do we ever need to reset the chip??? */ | |
fdecea66 | 886 | |
ea8f2ed0 | 887 | retval = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
888 | if (retval) |
889 | return retval; | |
890 | ||
891 | /* Disable the Rx and Tx, and reset the chip. */ | |
892 | writel(0, ioaddr + GenCtrl); | |
893 | writel(1, ioaddr + PCIDeviceConfig); | |
894 | if (debug > 1) | |
895 | printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", | |
ea8f2ed0 | 896 | dev->name, irq); |
1da177e4 LT |
897 | |
898 | /* Allocate the various queues. */ | |
88b1943b | 899 | if (!np->queue_mem) { |
1da177e4 LT |
900 | tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; |
901 | rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
902 | tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
903 | rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE; | |
904 | np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size; | |
905 | np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma); | |
d8840ac9 | 906 | if (np->queue_mem == NULL) { |
ea8f2ed0 | 907 | free_irq(irq, dev); |
1da177e4 | 908 | return -ENOMEM; |
d8840ac9 | 909 | } |
1da177e4 LT |
910 | |
911 | np->tx_done_q = np->queue_mem; | |
912 | np->tx_done_q_dma = np->queue_mem_dma; | |
913 | np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size; | |
914 | np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size; | |
915 | np->tx_ring = (void *) np->rx_done_q + rx_done_q_size; | |
916 | np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size; | |
917 | np->rx_ring = (void *) np->tx_ring + tx_ring_size; | |
918 | np->rx_ring_dma = np->tx_ring_dma + tx_ring_size; | |
919 | } | |
920 | ||
921 | /* Start with no carrier, it gets adjusted later */ | |
922 | netif_carrier_off(dev); | |
923 | init_ring(dev); | |
924 | /* Set the size of the Rx buffers. */ | |
925 | writel((np->rx_buf_sz << RxBufferLenShift) | | |
926 | (0 << RxMinDescrThreshShift) | | |
927 | RxPrefetchMode | RxVariableQ | | |
928 | RX_Q_ENTRIES | | |
929 | RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE | | |
930 | RxDescSpace4, | |
931 | ioaddr + RxDescQCtrl); | |
932 | ||
933 | /* Set up the Rx DMA controller. */ | |
934 | writel(RxChecksumIgnore | | |
935 | (0 << RxEarlyIntThreshShift) | | |
936 | (6 << RxHighPrioThreshShift) | | |
937 | ((DMA_BURST_SIZE / 32) << RxBurstSizeShift), | |
938 | ioaddr + RxDMACtrl); | |
939 | ||
940 | /* Set Tx descriptor */ | |
941 | writel((2 << TxHiPriFIFOThreshShift) | | |
942 | (0 << TxPadLenShift) | | |
943 | ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) | | |
944 | TX_DESC_Q_ADDR_SIZE | | |
945 | TX_DESC_SPACING | TX_DESC_TYPE, | |
946 | ioaddr + TxDescCtrl); | |
947 | ||
948 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr); | |
949 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr); | |
950 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr); | |
951 | writel(np->rx_ring_dma, ioaddr + RxDescQAddr); | |
952 | writel(np->tx_ring_dma, ioaddr + TxRingPtr); | |
953 | ||
954 | writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr); | |
955 | writel(np->rx_done_q_dma | | |
956 | RxComplType | | |
957 | (0 << RxComplThreshShift), | |
958 | ioaddr + RxCompletionAddr); | |
959 | ||
960 | if (debug > 1) | |
961 | printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name); | |
962 | ||
963 | /* Fill both the Tx SA register and the Rx perfect filter. */ | |
964 | for (i = 0; i < 6; i++) | |
965 | writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i); | |
966 | /* The first entry is special because it bypasses the VLAN filter. | |
967 | Don't use it. */ | |
968 | writew(0, ioaddr + PerfFilterTable); | |
969 | writew(0, ioaddr + PerfFilterTable + 4); | |
970 | writew(0, ioaddr + PerfFilterTable + 8); | |
971 | for (i = 1; i < 16; i++) { | |
88b1943b | 972 | __be16 *eaddrs = (__be16 *)dev->dev_addr; |
1da177e4 | 973 | void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; |
88b1943b AV |
974 | writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4; |
975 | writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4; | |
976 | writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8; | |
1da177e4 LT |
977 | } |
978 | ||
979 | /* Initialize other registers. */ | |
980 | /* Configure the PCI bus bursts and FIFO thresholds. */ | |
981 | np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */ | |
982 | writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode); | |
983 | udelay(1000); | |
984 | writel(np->tx_mode, ioaddr + TxMode); | |
985 | np->tx_threshold = 4; | |
986 | writel(np->tx_threshold, ioaddr + TxThreshold); | |
987 | ||
988 | writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
989 | ||
bea3348e | 990 | napi_enable(&np->napi); |
a6676019 | 991 | |
1da177e4 LT |
992 | netif_start_queue(dev); |
993 | ||
994 | if (debug > 1) | |
995 | printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name); | |
996 | set_rx_mode(dev); | |
997 | ||
998 | np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
999 | check_duplex(dev); | |
1000 | ||
1001 | /* Enable GPIO interrupts on link change */ | |
1002 | writel(0x0f00ff00, ioaddr + GPIOCtrl); | |
1003 | ||
1004 | /* Set the interrupt mask */ | |
1005 | writel(IntrRxDone | IntrRxEmpty | IntrDMAErr | | |
1006 | IntrTxDMADone | IntrStatsMax | IntrLinkChange | | |
1007 | IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID, | |
1008 | ioaddr + IntrEnable); | |
1009 | /* Enable PCI interrupts. */ | |
1010 | writel(0x00800000 | readl(ioaddr + PCIDeviceConfig), | |
1011 | ioaddr + PCIDeviceConfig); | |
1012 | ||
1013 | #ifdef VLAN_SUPPORT | |
1014 | /* Set VLAN type to 802.1q */ | |
1015 | writel(ETH_P_8021Q, ioaddr + VlanType); | |
1016 | #endif /* VLAN_SUPPORT */ | |
1017 | ||
cfc3a44c JSR |
1018 | retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev); |
1019 | if (retval) { | |
1020 | printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n", | |
1021 | FIRMWARE_RX); | |
c928febf | 1022 | goto out_init; |
cfc3a44c JSR |
1023 | } |
1024 | if (fw_rx->size % 4) { | |
1025 | printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", | |
1026 | fw_rx->size, FIRMWARE_RX); | |
1027 | retval = -EINVAL; | |
1028 | goto out_rx; | |
1029 | } | |
1030 | retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev); | |
1031 | if (retval) { | |
1032 | printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n", | |
1033 | FIRMWARE_TX); | |
1034 | goto out_rx; | |
1035 | } | |
1036 | if (fw_tx->size % 4) { | |
1037 | printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", | |
1038 | fw_tx->size, FIRMWARE_TX); | |
1039 | retval = -EINVAL; | |
1040 | goto out_tx; | |
1041 | } | |
1042 | fw_rx_data = (const __be32 *)&fw_rx->data[0]; | |
1043 | fw_tx_data = (const __be32 *)&fw_tx->data[0]; | |
1044 | rx_size = fw_rx->size / 4; | |
1045 | tx_size = fw_tx->size / 4; | |
1046 | ||
1da177e4 | 1047 | /* Load Rx/Tx firmware into the frame processors */ |
cfc3a44c JSR |
1048 | for (i = 0; i < rx_size; i++) |
1049 | writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4); | |
1050 | for (i = 0; i < tx_size; i++) | |
1051 | writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4); | |
1da177e4 LT |
1052 | if (enable_hw_cksum) |
1053 | /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */ | |
1054 | writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl); | |
1055 | else | |
1056 | /* Enable the Rx and Tx units only. */ | |
1057 | writel(TxEnable|RxEnable, ioaddr + GenCtrl); | |
1058 | ||
1059 | if (debug > 1) | |
1060 | printk(KERN_DEBUG "%s: Done netdev_open().\n", | |
1061 | dev->name); | |
1062 | ||
cfc3a44c JSR |
1063 | out_tx: |
1064 | release_firmware(fw_tx); | |
1065 | out_rx: | |
1066 | release_firmware(fw_rx); | |
c928febf BH |
1067 | out_init: |
1068 | if (retval) | |
1069 | netdev_close(dev); | |
cfc3a44c | 1070 | return retval; |
1da177e4 LT |
1071 | } |
1072 | ||
1073 | ||
1074 | static void check_duplex(struct net_device *dev) | |
1075 | { | |
1076 | struct netdev_private *np = netdev_priv(dev); | |
1077 | u16 reg0; | |
1078 | int silly_count = 1000; | |
1079 | ||
1080 | mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising); | |
1081 | mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET); | |
1082 | udelay(500); | |
1083 | while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET) | |
1084 | /* do nothing */; | |
1085 | if (!silly_count) { | |
1086 | printk("%s: MII reset failed!\n", dev->name); | |
1087 | return; | |
1088 | } | |
1089 | ||
1090 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1091 | ||
1092 | if (!np->mii_if.force_media) { | |
1093 | reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; | |
1094 | } else { | |
1095 | reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); | |
1096 | if (np->speed100) | |
1097 | reg0 |= BMCR_SPEED100; | |
1098 | if (np->mii_if.full_duplex) | |
1099 | reg0 |= BMCR_FULLDPLX; | |
1100 | printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n", | |
1101 | dev->name, | |
1102 | np->speed100 ? "100" : "10", | |
1103 | np->mii_if.full_duplex ? "full" : "half"); | |
1104 | } | |
1105 | mdio_write(dev, np->phys[0], MII_BMCR, reg0); | |
1106 | } | |
1107 | ||
1108 | ||
1109 | static void tx_timeout(struct net_device *dev) | |
1110 | { | |
1111 | struct netdev_private *np = netdev_priv(dev); | |
1112 | void __iomem *ioaddr = np->base; | |
1113 | int old_debug; | |
1114 | ||
1115 | printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, " | |
1116 | "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus)); | |
1117 | ||
1118 | /* Perhaps we should reinitialize the hardware here. */ | |
1119 | ||
1120 | /* | |
1121 | * Stop and restart the interface. | |
1122 | * Cheat and increase the debug level temporarily. | |
1123 | */ | |
1124 | old_debug = debug; | |
1125 | debug = 2; | |
1126 | netdev_close(dev); | |
1127 | netdev_open(dev); | |
1128 | debug = old_debug; | |
1129 | ||
1130 | /* Trigger an immediate transmit demand. */ | |
1131 | ||
860e9538 | 1132 | netif_trans_update(dev); /* prevent tx timeout */ |
86678a20 | 1133 | dev->stats.tx_errors++; |
1da177e4 LT |
1134 | netif_wake_queue(dev); |
1135 | } | |
1136 | ||
1137 | ||
1138 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
1139 | static void init_ring(struct net_device *dev) | |
1140 | { | |
1141 | struct netdev_private *np = netdev_priv(dev); | |
1142 | int i; | |
1143 | ||
1144 | np->cur_rx = np->cur_tx = np->reap_tx = 0; | |
1145 | np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0; | |
1146 | ||
1147 | np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
1148 | ||
1149 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
1150 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1d266430 | 1151 | struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz); |
1da177e4 LT |
1152 | np->rx_info[i].skb = skb; |
1153 | if (skb == NULL) | |
1154 | break; | |
689be439 | 1155 | np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1156 | /* Grrr, we cannot offset to correctly align the IP header. */ |
1157 | np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid); | |
1158 | } | |
1159 | writew(i - 1, np->base + RxDescQIdx); | |
1160 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
1161 | ||
1162 | /* Clear the remainder of the Rx buffer ring. */ | |
1163 | for ( ; i < RX_RING_SIZE; i++) { | |
1164 | np->rx_ring[i].rxaddr = 0; | |
1165 | np->rx_info[i].skb = NULL; | |
1166 | np->rx_info[i].mapping = 0; | |
1167 | } | |
1168 | /* Mark the last entry as wrapping the ring. */ | |
1169 | np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1170 | ||
1171 | /* Clear the completion rings. */ | |
1172 | for (i = 0; i < DONE_Q_SIZE; i++) { | |
1173 | np->rx_done_q[i].status = 0; | |
1174 | np->tx_done_q[i].status = 0; | |
1175 | } | |
1176 | ||
1177 | for (i = 0; i < TX_RING_SIZE; i++) | |
1178 | memset(&np->tx_info[i], 0, sizeof(np->tx_info[i])); | |
1da177e4 LT |
1179 | } |
1180 | ||
1181 | ||
61357325 | 1182 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
1183 | { |
1184 | struct netdev_private *np = netdev_priv(dev); | |
1185 | unsigned int entry; | |
1186 | u32 status; | |
1187 | int i; | |
1188 | ||
1da177e4 LT |
1189 | /* |
1190 | * be cautious here, wrapping the queue has weird semantics | |
1191 | * and we may not have enough slots even when it seems we do. | |
1192 | */ | |
1193 | if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) { | |
1194 | netif_stop_queue(dev); | |
5b548140 | 1195 | return NETDEV_TX_BUSY; |
1da177e4 LT |
1196 | } |
1197 | ||
1198 | #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE) | |
84fa7933 | 1199 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5b057c6b | 1200 | if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK)) |
67974231 | 1201 | return NETDEV_TX_OK; |
1da177e4 LT |
1202 | } |
1203 | #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */ | |
1204 | ||
1205 | entry = np->cur_tx % TX_RING_SIZE; | |
1206 | for (i = 0; i < skb_num_frags(skb); i++) { | |
1207 | int wrap_ring = 0; | |
1208 | status = TxDescID; | |
1209 | ||
1210 | if (i == 0) { | |
1211 | np->tx_info[entry].skb = skb; | |
1212 | status |= TxCRCEn; | |
1213 | if (entry >= TX_RING_SIZE - skb_num_frags(skb)) { | |
1214 | status |= TxRingWrap; | |
1215 | wrap_ring = 1; | |
1216 | } | |
1217 | if (np->reap_tx) { | |
1218 | status |= TxDescIntr; | |
1219 | np->reap_tx = 0; | |
1220 | } | |
84fa7933 | 1221 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1da177e4 | 1222 | status |= TxCalTCP; |
86678a20 | 1223 | dev->stats.tx_compressed++; |
1da177e4 LT |
1224 | } |
1225 | status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16); | |
1226 | ||
1227 | np->tx_info[entry].mapping = | |
1228 | pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1229 | } else { | |
9e903e08 ED |
1230 | const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1]; |
1231 | status |= skb_frag_size(this_frag); | |
1da177e4 | 1232 | np->tx_info[entry].mapping = |
0cd83cc0 IC |
1233 | pci_map_single(np->pci_dev, |
1234 | skb_frag_address(this_frag), | |
9e903e08 | 1235 | skb_frag_size(this_frag), |
0cd83cc0 | 1236 | PCI_DMA_TODEVICE); |
1da177e4 LT |
1237 | } |
1238 | ||
1239 | np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping); | |
1240 | np->tx_ring[entry].status = cpu_to_le32(status); | |
1241 | if (debug > 3) | |
1242 | printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n", | |
1243 | dev->name, np->cur_tx, np->dirty_tx, | |
1244 | entry, status); | |
1245 | if (wrap_ring) { | |
1246 | np->tx_info[entry].used_slots = TX_RING_SIZE - entry; | |
1247 | np->cur_tx += np->tx_info[entry].used_slots; | |
1248 | entry = 0; | |
1249 | } else { | |
1250 | np->tx_info[entry].used_slots = 1; | |
1251 | np->cur_tx += np->tx_info[entry].used_slots; | |
1252 | entry++; | |
1253 | } | |
1254 | /* scavenge the tx descriptors twice per TX_RING_SIZE */ | |
1255 | if (np->cur_tx % (TX_RING_SIZE / 2) == 0) | |
1256 | np->reap_tx = 1; | |
1257 | } | |
1258 | ||
1259 | /* Non-x86: explicitly flush descriptor cache lines here. */ | |
1260 | /* Ensure all descriptors are written back before the transmit is | |
1261 | initiated. - Jes */ | |
1262 | wmb(); | |
1263 | ||
1264 | /* Update the producer index. */ | |
1265 | writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx); | |
1266 | ||
1267 | /* 4 is arbitrary, but should be ok */ | |
1268 | if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE) | |
1269 | netif_stop_queue(dev); | |
1270 | ||
6ed10654 | 1271 | return NETDEV_TX_OK; |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | ||
1275 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1276 | after the Tx thread. */ | |
7d12e780 | 1277 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
1278 | { |
1279 | struct net_device *dev = dev_instance; | |
1280 | struct netdev_private *np = netdev_priv(dev); | |
1281 | void __iomem *ioaddr = np->base; | |
1282 | int boguscnt = max_interrupt_work; | |
1283 | int consumer; | |
1284 | int tx_status; | |
1285 | int handled = 0; | |
1286 | ||
1287 | do { | |
1288 | u32 intr_status = readl(ioaddr + IntrClear); | |
1289 | ||
1290 | if (debug > 4) | |
1291 | printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n", | |
1292 | dev->name, intr_status); | |
1293 | ||
1294 | if (intr_status == 0 || intr_status == (u32) -1) | |
1295 | break; | |
1296 | ||
1297 | handled = 1; | |
1298 | ||
a6676019 FR |
1299 | if (intr_status & (IntrRxDone | IntrRxEmpty)) { |
1300 | u32 enable; | |
1301 | ||
288379f0 BH |
1302 | if (likely(napi_schedule_prep(&np->napi))) { |
1303 | __napi_schedule(&np->napi); | |
a6676019 FR |
1304 | enable = readl(ioaddr + IntrEnable); |
1305 | enable &= ~(IntrRxDone | IntrRxEmpty); | |
1306 | writel(enable, ioaddr + IntrEnable); | |
1307 | /* flush PCI posting buffers */ | |
1308 | readl(ioaddr + IntrEnable); | |
1309 | } else { | |
1310 | /* Paranoia check */ | |
1311 | enable = readl(ioaddr + IntrEnable); | |
1312 | if (enable & (IntrRxDone | IntrRxEmpty)) { | |
1313 | printk(KERN_INFO | |
1314 | "%s: interrupt while in poll!\n", | |
1315 | dev->name); | |
1316 | enable &= ~(IntrRxDone | IntrRxEmpty); | |
1317 | writel(enable, ioaddr + IntrEnable); | |
1318 | } | |
1319 | } | |
1320 | } | |
1da177e4 LT |
1321 | |
1322 | /* Scavenge the skbuff list based on the Tx-done queue. | |
1323 | There are redundant checks here that may be cleaned up | |
1324 | after the driver has proven to be reliable. */ | |
1325 | consumer = readl(ioaddr + TxConsumerIdx); | |
1326 | if (debug > 3) | |
1327 | printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n", | |
1328 | dev->name, consumer); | |
1329 | ||
1330 | while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) { | |
1331 | if (debug > 3) | |
1332 | printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n", | |
1333 | dev->name, np->dirty_tx, np->tx_done, tx_status); | |
1334 | if ((tx_status & 0xe0000000) == 0xa0000000) { | |
86678a20 | 1335 | dev->stats.tx_packets++; |
1da177e4 LT |
1336 | } else if ((tx_status & 0xe0000000) == 0x80000000) { |
1337 | u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc); | |
1338 | struct sk_buff *skb = np->tx_info[entry].skb; | |
1339 | np->tx_info[entry].skb = NULL; | |
1340 | pci_unmap_single(np->pci_dev, | |
1341 | np->tx_info[entry].mapping, | |
1342 | skb_first_frag_len(skb), | |
1343 | PCI_DMA_TODEVICE); | |
1344 | np->tx_info[entry].mapping = 0; | |
1345 | np->dirty_tx += np->tx_info[entry].used_slots; | |
1346 | entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE; | |
1da177e4 LT |
1347 | { |
1348 | int i; | |
1349 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1350 | pci_unmap_single(np->pci_dev, | |
1351 | np->tx_info[entry].mapping, | |
9e903e08 | 1352 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
1da177e4 LT |
1353 | PCI_DMA_TODEVICE); |
1354 | np->dirty_tx++; | |
1355 | entry++; | |
1356 | } | |
1357 | } | |
fdecea66 | 1358 | |
1da177e4 LT |
1359 | dev_kfree_skb_irq(skb); |
1360 | } | |
1361 | np->tx_done_q[np->tx_done].status = 0; | |
1362 | np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE; | |
1363 | } | |
1364 | writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2); | |
1365 | ||
1366 | if (netif_queue_stopped(dev) && | |
1367 | (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) { | |
1368 | /* The ring is no longer full, wake the queue. */ | |
1369 | netif_wake_queue(dev); | |
1370 | } | |
1371 | ||
1372 | /* Stats overflow */ | |
1373 | if (intr_status & IntrStatsMax) | |
1374 | get_stats(dev); | |
1375 | ||
1376 | /* Media change interrupt. */ | |
1377 | if (intr_status & IntrLinkChange) | |
1378 | netdev_media_change(dev); | |
1379 | ||
1380 | /* Abnormal error summary/uncommon events handlers. */ | |
1381 | if (intr_status & IntrAbnormalSummary) | |
1382 | netdev_error(dev, intr_status); | |
1383 | ||
1384 | if (--boguscnt < 0) { | |
1385 | if (debug > 1) | |
1386 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1387 | "status=%#8.8x.\n", | |
1388 | dev->name, intr_status); | |
1389 | break; | |
1390 | } | |
1391 | } while (1); | |
1392 | ||
1393 | if (debug > 4) | |
1394 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n", | |
1395 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1396 | return IRQ_RETVAL(handled); | |
1397 | } | |
1398 | ||
1399 | ||
a6676019 FR |
1400 | /* |
1401 | * This routine is logically part of the interrupt/poll handler, but separated | |
1402 | * for clarity and better register allocation. | |
1403 | */ | |
1da177e4 LT |
1404 | static int __netdev_rx(struct net_device *dev, int *quota) |
1405 | { | |
1406 | struct netdev_private *np = netdev_priv(dev); | |
1407 | u32 desc_status; | |
1408 | int retcode = 0; | |
1409 | ||
1410 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1411 | while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) { | |
1412 | struct sk_buff *skb; | |
1413 | u16 pkt_len; | |
1414 | int entry; | |
1415 | rx_done_desc *desc = &np->rx_done_q[np->rx_done]; | |
1416 | ||
1417 | if (debug > 4) | |
1418 | printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status); | |
1419 | if (!(desc_status & RxOK)) { | |
fdecea66 | 1420 | /* There was an error. */ |
1da177e4 LT |
1421 | if (debug > 2) |
1422 | printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status); | |
86678a20 | 1423 | dev->stats.rx_errors++; |
1da177e4 | 1424 | if (desc_status & RxFIFOErr) |
86678a20 | 1425 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
1426 | goto next_rx; |
1427 | } | |
1428 | ||
1429 | if (*quota <= 0) { /* out of rx quota */ | |
1430 | retcode = 1; | |
1431 | goto out; | |
1432 | } | |
1433 | (*quota)--; | |
1434 | ||
1435 | pkt_len = desc_status; /* Implicitly Truncate */ | |
1436 | entry = (desc_status >> 16) & 0x7ff; | |
1437 | ||
1438 | if (debug > 4) | |
1439 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota); | |
1440 | /* Check if the packet is long enough to accept without copying | |
1441 | to a minimally-sized skbuff. */ | |
8e95a202 | 1442 | if (pkt_len < rx_copybreak && |
1d266430 | 1443 | (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { |
1da177e4 LT |
1444 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1445 | pci_dma_sync_single_for_cpu(np->pci_dev, | |
1446 | np->rx_info[entry].mapping, | |
1447 | pkt_len, PCI_DMA_FROMDEVICE); | |
8c7b7faa | 1448 | skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len); |
1da177e4 LT |
1449 | pci_dma_sync_single_for_device(np->pci_dev, |
1450 | np->rx_info[entry].mapping, | |
1451 | pkt_len, PCI_DMA_FROMDEVICE); | |
1452 | skb_put(skb, pkt_len); | |
1453 | } else { | |
1454 | pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1455 | skb = np->rx_info[entry].skb; | |
1456 | skb_put(skb, pkt_len); | |
1457 | np->rx_info[entry].skb = NULL; | |
1458 | np->rx_info[entry].mapping = 0; | |
1459 | } | |
1460 | #ifndef final_version /* Remove after testing. */ | |
1461 | /* You will want this info for the initial debug. */ | |
0795af57 | 1462 | if (debug > 5) { |
e174961c JB |
1463 | printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n", |
1464 | skb->data, skb->data + 6, | |
0795af57 JP |
1465 | skb->data[12], skb->data[13]); |
1466 | } | |
1da177e4 LT |
1467 | #endif |
1468 | ||
1469 | skb->protocol = eth_type_trans(skb, dev); | |
fdecea66 | 1470 | #ifdef VLAN_SUPPORT |
1da177e4 LT |
1471 | if (debug > 4) |
1472 | printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2)); | |
1473 | #endif | |
1da177e4 LT |
1474 | if (le16_to_cpu(desc->status2) & 0x0100) { |
1475 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
86678a20 | 1476 | dev->stats.rx_compressed++; |
1da177e4 LT |
1477 | } |
1478 | /* | |
1479 | * This feature doesn't seem to be working, at least | |
1480 | * with the two firmware versions I have. If the GFP sees | |
1481 | * an IP fragment, it either ignores it completely, or reports | |
1482 | * "bad checksum" on it. | |
1483 | * | |
1484 | * Maybe I missed something -- corrections are welcome. | |
1485 | * Until then, the printk stays. :-) -Ion | |
1486 | */ | |
1487 | else if (le16_to_cpu(desc->status2) & 0x0040) { | |
84fa7933 | 1488 | skb->ip_summed = CHECKSUM_COMPLETE; |
1da177e4 LT |
1489 | skb->csum = le16_to_cpu(desc->csum); |
1490 | printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2)); | |
1491 | } | |
1da177e4 | 1492 | #ifdef VLAN_SUPPORT |
5da96be5 | 1493 | if (le16_to_cpu(desc->status2) & 0x0200) { |
a6676019 FR |
1494 | u16 vlid = le16_to_cpu(desc->vlanid); |
1495 | ||
1496 | if (debug > 4) { | |
1497 | printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", | |
1498 | vlid); | |
1499 | } | |
86a9bad3 | 1500 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlid); |
5da96be5 | 1501 | } |
1da177e4 | 1502 | #endif /* VLAN_SUPPORT */ |
5da96be5 | 1503 | netif_receive_skb(skb); |
86678a20 | 1504 | dev->stats.rx_packets++; |
1da177e4 LT |
1505 | |
1506 | next_rx: | |
1507 | np->cur_rx++; | |
1508 | desc->status = 0; | |
1509 | np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE; | |
1510 | } | |
9a3de255 JP |
1511 | |
1512 | if (*quota == 0) { /* out of rx quota */ | |
1513 | retcode = 1; | |
1514 | goto out; | |
1515 | } | |
1da177e4 LT |
1516 | writew(np->rx_done, np->base + CompletionQConsumerIdx); |
1517 | ||
1518 | out: | |
1519 | refill_rx_ring(dev); | |
1520 | if (debug > 5) | |
1521 | printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n", | |
1522 | retcode, np->rx_done, desc_status); | |
1523 | return retcode; | |
1524 | } | |
1525 | ||
bea3348e | 1526 | static int netdev_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1527 | { |
bea3348e SH |
1528 | struct netdev_private *np = container_of(napi, struct netdev_private, napi); |
1529 | struct net_device *dev = np->dev; | |
1da177e4 | 1530 | u32 intr_status; |
1da177e4 | 1531 | void __iomem *ioaddr = np->base; |
bea3348e | 1532 | int quota = budget; |
1da177e4 LT |
1533 | |
1534 | do { | |
1535 | writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear); | |
1536 | ||
bea3348e | 1537 | if (__netdev_rx(dev, "a)) |
1da177e4 LT |
1538 | goto out; |
1539 | ||
1540 | intr_status = readl(ioaddr + IntrStatus); | |
1541 | } while (intr_status & (IntrRxDone | IntrRxEmpty)); | |
1542 | ||
288379f0 | 1543 | napi_complete(napi); |
1da177e4 LT |
1544 | intr_status = readl(ioaddr + IntrEnable); |
1545 | intr_status |= IntrRxDone | IntrRxEmpty; | |
1546 | writel(intr_status, ioaddr + IntrEnable); | |
1547 | ||
1548 | out: | |
1549 | if (debug > 5) | |
bea3348e SH |
1550 | printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", |
1551 | budget - quota); | |
1da177e4 LT |
1552 | |
1553 | /* Restart Rx engine if stopped. */ | |
bea3348e | 1554 | return budget - quota; |
1da177e4 | 1555 | } |
1da177e4 LT |
1556 | |
1557 | static void refill_rx_ring(struct net_device *dev) | |
1558 | { | |
1559 | struct netdev_private *np = netdev_priv(dev); | |
1560 | struct sk_buff *skb; | |
1561 | int entry = -1; | |
1562 | ||
1563 | /* Refill the Rx ring buffers. */ | |
1564 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1565 | entry = np->dirty_rx % RX_RING_SIZE; | |
1566 | if (np->rx_info[entry].skb == NULL) { | |
1d266430 | 1567 | skb = netdev_alloc_skb(dev, np->rx_buf_sz); |
1da177e4 LT |
1568 | np->rx_info[entry].skb = skb; |
1569 | if (skb == NULL) | |
1570 | break; /* Better luck next round. */ | |
1571 | np->rx_info[entry].mapping = | |
689be439 | 1572 | pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1573 | np->rx_ring[entry].rxaddr = |
1574 | cpu_to_dma(np->rx_info[entry].mapping | RxDescValid); | |
1575 | } | |
1576 | if (entry == RX_RING_SIZE - 1) | |
1577 | np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1578 | } | |
1579 | if (entry >= 0) | |
1580 | writew(entry, np->base + RxDescQIdx); | |
1581 | } | |
1582 | ||
1583 | ||
1584 | static void netdev_media_change(struct net_device *dev) | |
1585 | { | |
1586 | struct netdev_private *np = netdev_priv(dev); | |
1587 | void __iomem *ioaddr = np->base; | |
1588 | u16 reg0, reg1, reg4, reg5; | |
1589 | u32 new_tx_mode; | |
1590 | u32 new_intr_timer_ctrl; | |
1591 | ||
1592 | /* reset status first */ | |
1593 | mdio_read(dev, np->phys[0], MII_BMCR); | |
1594 | mdio_read(dev, np->phys[0], MII_BMSR); | |
1595 | ||
1596 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1597 | reg1 = mdio_read(dev, np->phys[0], MII_BMSR); | |
1598 | ||
1599 | if (reg1 & BMSR_LSTATUS) { | |
1600 | /* link is up */ | |
1601 | if (reg0 & BMCR_ANENABLE) { | |
1602 | /* autonegotiation is enabled */ | |
1603 | reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
1604 | reg5 = mdio_read(dev, np->phys[0], MII_LPA); | |
1605 | if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) { | |
1606 | np->speed100 = 1; | |
1607 | np->mii_if.full_duplex = 1; | |
1608 | } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) { | |
1609 | np->speed100 = 1; | |
1610 | np->mii_if.full_duplex = 0; | |
1611 | } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) { | |
1612 | np->speed100 = 0; | |
1613 | np->mii_if.full_duplex = 1; | |
1614 | } else { | |
1615 | np->speed100 = 0; | |
1616 | np->mii_if.full_duplex = 0; | |
1617 | } | |
1618 | } else { | |
1619 | /* autonegotiation is disabled */ | |
1620 | if (reg0 & BMCR_SPEED100) | |
1621 | np->speed100 = 1; | |
1622 | else | |
1623 | np->speed100 = 0; | |
1624 | if (reg0 & BMCR_FULLDPLX) | |
1625 | np->mii_if.full_duplex = 1; | |
1626 | else | |
1627 | np->mii_if.full_duplex = 0; | |
1628 | } | |
1629 | netif_carrier_on(dev); | |
1630 | printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n", | |
1631 | dev->name, | |
1632 | np->speed100 ? "100" : "10", | |
1633 | np->mii_if.full_duplex ? "full" : "half"); | |
1634 | ||
1635 | new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */ | |
1636 | if (np->mii_if.full_duplex) | |
1637 | new_tx_mode |= FullDuplex; | |
1638 | if (np->tx_mode != new_tx_mode) { | |
1639 | np->tx_mode = new_tx_mode; | |
1640 | writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode); | |
1641 | udelay(1000); | |
1642 | writel(np->tx_mode, ioaddr + TxMode); | |
1643 | } | |
1644 | ||
1645 | new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X; | |
1646 | if (np->speed100) | |
1647 | new_intr_timer_ctrl |= Timer10X; | |
1648 | if (np->intr_timer_ctrl != new_intr_timer_ctrl) { | |
1649 | np->intr_timer_ctrl = new_intr_timer_ctrl; | |
1650 | writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
1651 | } | |
1652 | } else { | |
1653 | netif_carrier_off(dev); | |
1654 | printk(KERN_DEBUG "%s: Link is down\n", dev->name); | |
1655 | } | |
1656 | } | |
1657 | ||
1658 | ||
1659 | static void netdev_error(struct net_device *dev, int intr_status) | |
1660 | { | |
1661 | struct netdev_private *np = netdev_priv(dev); | |
1662 | ||
1663 | /* Came close to underrunning the Tx FIFO, increase threshold. */ | |
1664 | if (intr_status & IntrTxDataLow) { | |
1665 | if (np->tx_threshold <= PKT_BUF_SZ / 16) { | |
1666 | writel(++np->tx_threshold, np->base + TxThreshold); | |
1667 | printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n", | |
1668 | dev->name, np->tx_threshold * 16); | |
1669 | } else | |
1670 | printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name); | |
1671 | } | |
1672 | if (intr_status & IntrRxGFPDead) { | |
86678a20 KV |
1673 | dev->stats.rx_fifo_errors++; |
1674 | dev->stats.rx_errors++; | |
1da177e4 LT |
1675 | } |
1676 | if (intr_status & (IntrNoTxCsum | IntrDMAErr)) { | |
86678a20 KV |
1677 | dev->stats.tx_fifo_errors++; |
1678 | dev->stats.tx_errors++; | |
1da177e4 LT |
1679 | } |
1680 | if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug) | |
1681 | printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n", | |
1682 | dev->name, intr_status); | |
1683 | } | |
1684 | ||
1685 | ||
1686 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1687 | { | |
1688 | struct netdev_private *np = netdev_priv(dev); | |
1689 | void __iomem *ioaddr = np->base; | |
1690 | ||
1691 | /* This adapter architecture needs no SMP locks. */ | |
86678a20 KV |
1692 | dev->stats.tx_bytes = readl(ioaddr + 0x57010); |
1693 | dev->stats.rx_bytes = readl(ioaddr + 0x57044); | |
1694 | dev->stats.tx_packets = readl(ioaddr + 0x57000); | |
1695 | dev->stats.tx_aborted_errors = | |
1da177e4 | 1696 | readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028); |
86678a20 KV |
1697 | dev->stats.tx_window_errors = readl(ioaddr + 0x57018); |
1698 | dev->stats.collisions = | |
1da177e4 LT |
1699 | readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008); |
1700 | ||
1701 | /* The chip only need report frame silently dropped. */ | |
86678a20 | 1702 | dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus); |
1da177e4 | 1703 | writew(0, ioaddr + RxDMAStatus); |
86678a20 KV |
1704 | dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C); |
1705 | dev->stats.rx_frame_errors = readl(ioaddr + 0x57040); | |
1706 | dev->stats.rx_length_errors = readl(ioaddr + 0x57058); | |
1707 | dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C); | |
1da177e4 | 1708 | |
86678a20 | 1709 | return &dev->stats; |
1da177e4 LT |
1710 | } |
1711 | ||
5da96be5 JP |
1712 | #ifdef VLAN_SUPPORT |
1713 | static u32 set_vlan_mode(struct netdev_private *np) | |
1714 | { | |
1715 | u32 ret = VlanMode; | |
1716 | u16 vid; | |
1717 | void __iomem *filter_addr = np->base + HashTable + 8; | |
1718 | int vlan_count = 0; | |
1719 | ||
1720 | for_each_set_bit(vid, np->active_vlans, VLAN_N_VID) { | |
1721 | if (vlan_count == 32) | |
1722 | break; | |
1723 | writew(vid, filter_addr); | |
1724 | filter_addr += 16; | |
1725 | vlan_count++; | |
1726 | } | |
1727 | if (vlan_count == 32) { | |
1728 | ret |= PerfectFilterVlan; | |
1729 | while (vlan_count < 32) { | |
1730 | writew(0, filter_addr); | |
1731 | filter_addr += 16; | |
1732 | vlan_count++; | |
1733 | } | |
1734 | } | |
1735 | return ret; | |
1736 | } | |
1737 | #endif /* VLAN_SUPPORT */ | |
1da177e4 | 1738 | |
1da177e4 LT |
1739 | static void set_rx_mode(struct net_device *dev) |
1740 | { | |
1741 | struct netdev_private *np = netdev_priv(dev); | |
1742 | void __iomem *ioaddr = np->base; | |
1743 | u32 rx_mode = MinVLANPrio; | |
22bedad3 | 1744 | struct netdev_hw_addr *ha; |
1da177e4 | 1745 | int i; |
1da177e4 | 1746 | |
5da96be5 JP |
1747 | #ifdef VLAN_SUPPORT |
1748 | rx_mode |= set_vlan_mode(np); | |
1da177e4 LT |
1749 | #endif /* VLAN_SUPPORT */ |
1750 | ||
1751 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1752 | rx_mode |= AcceptAll; | |
4cd24eaf | 1753 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 1754 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
1755 | /* Too many to match, or accept all multicasts. */ |
1756 | rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter; | |
4cd24eaf | 1757 | } else if (netdev_mc_count(dev) <= 14) { |
1da177e4 LT |
1758 | /* Use the 16 element perfect filter, skip first two entries. */ |
1759 | void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
88b1943b | 1760 | __be16 *eaddrs; |
22bedad3 JP |
1761 | netdev_for_each_mc_addr(ha, dev) { |
1762 | eaddrs = (__be16 *) ha->addr; | |
88b1943b AV |
1763 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4; |
1764 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1765 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8; | |
1da177e4 | 1766 | } |
88b1943b | 1767 | eaddrs = (__be16 *)dev->dev_addr; |
5508590c | 1768 | i = netdev_mc_count(dev) + 2; |
1da177e4 | 1769 | while (i++ < 16) { |
88b1943b AV |
1770 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; |
1771 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1772 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8; | |
1da177e4 LT |
1773 | } |
1774 | rx_mode |= AcceptBroadcast|PerfectFilter; | |
1775 | } else { | |
1776 | /* Must use a multicast hash table. */ | |
1777 | void __iomem *filter_addr; | |
88b1943b AV |
1778 | __be16 *eaddrs; |
1779 | __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ | |
1da177e4 LT |
1780 | |
1781 | memset(mc_filter, 0, sizeof(mc_filter)); | |
22bedad3 | 1782 | netdev_for_each_mc_addr(ha, dev) { |
fdecea66 JG |
1783 | /* The chip uses the upper 9 CRC bits |
1784 | as index into the hash table */ | |
22bedad3 | 1785 | int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23; |
88b1943b | 1786 | __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1]; |
1da177e4 LT |
1787 | |
1788 | *fptr |= cpu_to_le32(1 << (bit_nr & 31)); | |
1789 | } | |
1790 | /* Clear the perfect filter list, skip first two entries. */ | |
1791 | filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
88b1943b | 1792 | eaddrs = (__be16 *)dev->dev_addr; |
1da177e4 | 1793 | for (i = 2; i < 16; i++) { |
88b1943b AV |
1794 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; |
1795 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1796 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8; | |
1da177e4 LT |
1797 | } |
1798 | for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) | |
1799 | writew(mc_filter[i], filter_addr); | |
1800 | rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter; | |
1801 | } | |
1802 | writel(rx_mode, ioaddr + RxFilterMode); | |
1803 | } | |
1804 | ||
1805 | static int check_if_running(struct net_device *dev) | |
1806 | { | |
1807 | if (!netif_running(dev)) | |
1808 | return -EINVAL; | |
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1813 | { | |
1814 | struct netdev_private *np = netdev_priv(dev); | |
68aad78c RJ |
1815 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
1816 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1817 | strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1818 | } |
1819 | ||
1820 | static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1821 | { | |
1822 | struct netdev_private *np = netdev_priv(dev); | |
1823 | spin_lock_irq(&np->lock); | |
1824 | mii_ethtool_gset(&np->mii_if, ecmd); | |
1825 | spin_unlock_irq(&np->lock); | |
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1830 | { | |
1831 | struct netdev_private *np = netdev_priv(dev); | |
1832 | int res; | |
1833 | spin_lock_irq(&np->lock); | |
1834 | res = mii_ethtool_sset(&np->mii_if, ecmd); | |
1835 | spin_unlock_irq(&np->lock); | |
1836 | check_duplex(dev); | |
1837 | return res; | |
1838 | } | |
1839 | ||
1840 | static int nway_reset(struct net_device *dev) | |
1841 | { | |
1842 | struct netdev_private *np = netdev_priv(dev); | |
1843 | return mii_nway_restart(&np->mii_if); | |
1844 | } | |
1845 | ||
1846 | static u32 get_link(struct net_device *dev) | |
1847 | { | |
1848 | struct netdev_private *np = netdev_priv(dev); | |
1849 | return mii_link_ok(&np->mii_if); | |
1850 | } | |
1851 | ||
1852 | static u32 get_msglevel(struct net_device *dev) | |
1853 | { | |
1854 | return debug; | |
1855 | } | |
1856 | ||
1857 | static void set_msglevel(struct net_device *dev, u32 val) | |
1858 | { | |
1859 | debug = val; | |
1860 | } | |
1861 | ||
7282d491 | 1862 | static const struct ethtool_ops ethtool_ops = { |
1da177e4 LT |
1863 | .begin = check_if_running, |
1864 | .get_drvinfo = get_drvinfo, | |
1865 | .get_settings = get_settings, | |
1866 | .set_settings = set_settings, | |
1867 | .nway_reset = nway_reset, | |
1868 | .get_link = get_link, | |
1869 | .get_msglevel = get_msglevel, | |
1870 | .set_msglevel = set_msglevel, | |
1871 | }; | |
1872 | ||
1873 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1874 | { | |
1875 | struct netdev_private *np = netdev_priv(dev); | |
1876 | struct mii_ioctl_data *data = if_mii(rq); | |
1877 | int rc; | |
1878 | ||
1879 | if (!netif_running(dev)) | |
1880 | return -EINVAL; | |
1881 | ||
1882 | spin_lock_irq(&np->lock); | |
1883 | rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL); | |
1884 | spin_unlock_irq(&np->lock); | |
1885 | ||
1886 | if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0])) | |
1887 | check_duplex(dev); | |
1888 | ||
1889 | return rc; | |
1890 | } | |
1891 | ||
1892 | static int netdev_close(struct net_device *dev) | |
1893 | { | |
1894 | struct netdev_private *np = netdev_priv(dev); | |
1895 | void __iomem *ioaddr = np->base; | |
1896 | int i; | |
1897 | ||
1898 | netif_stop_queue(dev); | |
a6676019 | 1899 | |
bea3348e | 1900 | napi_disable(&np->napi); |
1da177e4 LT |
1901 | |
1902 | if (debug > 1) { | |
1903 | printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", | |
1904 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1905 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1906 | dev->name, np->cur_tx, np->dirty_tx, | |
1907 | np->cur_rx, np->dirty_rx); | |
1908 | } | |
1909 | ||
1910 | /* Disable interrupts by clearing the interrupt mask. */ | |
1911 | writel(0, ioaddr + IntrEnable); | |
1912 | ||
1913 | /* Stop the chip's Tx and Rx processes. */ | |
1914 | writel(0, ioaddr + GenCtrl); | |
1915 | readl(ioaddr + GenCtrl); | |
1916 | ||
1917 | if (debug > 5) { | |
1918 | printk(KERN_DEBUG" Tx ring at %#llx:\n", | |
1919 | (long long) np->tx_ring_dma); | |
1920 | for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++) | |
1921 | printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n", | |
1922 | i, le32_to_cpu(np->tx_ring[i].status), | |
1923 | (long long) dma_to_cpu(np->tx_ring[i].addr), | |
1924 | le32_to_cpu(np->tx_done_q[i].status)); | |
1925 | printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n", | |
1926 | (long long) np->rx_ring_dma, np->rx_done_q); | |
1927 | if (np->rx_done_q) | |
1928 | for (i = 0; i < 8 /* RX_RING_SIZE */; i++) { | |
1929 | printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n", | |
1930 | i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status)); | |
1931 | } | |
1932 | } | |
1933 | ||
ea8f2ed0 | 1934 | free_irq(np->pci_dev->irq, dev); |
1da177e4 LT |
1935 | |
1936 | /* Free all the skbuffs in the Rx queue. */ | |
1937 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1938 | np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */ | |
1939 | if (np->rx_info[i].skb != NULL) { | |
1940 | pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1941 | dev_kfree_skb(np->rx_info[i].skb); | |
1942 | } | |
1943 | np->rx_info[i].skb = NULL; | |
1944 | np->rx_info[i].mapping = 0; | |
1945 | } | |
1946 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1947 | struct sk_buff *skb = np->tx_info[i].skb; | |
1948 | if (skb == NULL) | |
1949 | continue; | |
1950 | pci_unmap_single(np->pci_dev, | |
1951 | np->tx_info[i].mapping, | |
1952 | skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1953 | np->tx_info[i].mapping = 0; | |
1954 | dev_kfree_skb(skb); | |
1955 | np->tx_info[i].skb = NULL; | |
1956 | } | |
1957 | ||
1958 | return 0; | |
1959 | } | |
1960 | ||
d4fbeabb SR |
1961 | #ifdef CONFIG_PM |
1962 | static int starfire_suspend(struct pci_dev *pdev, pm_message_t state) | |
1963 | { | |
1964 | struct net_device *dev = pci_get_drvdata(pdev); | |
1965 | ||
1966 | if (netif_running(dev)) { | |
1967 | netif_device_detach(dev); | |
1968 | netdev_close(dev); | |
1969 | } | |
1970 | ||
1971 | pci_save_state(pdev); | |
1972 | pci_set_power_state(pdev, pci_choose_state(pdev,state)); | |
1973 | ||
1974 | return 0; | |
1975 | } | |
1976 | ||
1977 | static int starfire_resume(struct pci_dev *pdev) | |
1978 | { | |
1979 | struct net_device *dev = pci_get_drvdata(pdev); | |
6aa20a22 | 1980 | |
d4fbeabb SR |
1981 | pci_set_power_state(pdev, PCI_D0); |
1982 | pci_restore_state(pdev); | |
1983 | ||
1984 | if (netif_running(dev)) { | |
1985 | netdev_open(dev); | |
1986 | netif_device_attach(dev); | |
1987 | } | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | #endif /* CONFIG_PM */ | |
1992 | ||
1da177e4 | 1993 | |
d3ace588 | 1994 | static void starfire_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1995 | { |
1996 | struct net_device *dev = pci_get_drvdata(pdev); | |
1997 | struct netdev_private *np = netdev_priv(dev); | |
1998 | ||
5d9428de | 1999 | BUG_ON(!dev); |
1da177e4 LT |
2000 | |
2001 | unregister_netdev(dev); | |
2002 | ||
2003 | if (np->queue_mem) | |
2004 | pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma); | |
2005 | ||
2006 | ||
2007 | /* XXX: add wakeup code -- requires firmware for MagicPacket */ | |
2008 | pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */ | |
2009 | pci_disable_device(pdev); | |
2010 | ||
2011 | iounmap(np->base); | |
2012 | pci_release_regions(pdev); | |
2013 | ||
1da177e4 LT |
2014 | free_netdev(dev); /* Will also free np!! */ |
2015 | } | |
2016 | ||
2017 | ||
2018 | static struct pci_driver starfire_driver = { | |
2019 | .name = DRV_NAME, | |
2020 | .probe = starfire_init_one, | |
d3ace588 | 2021 | .remove = starfire_remove_one, |
d4fbeabb SR |
2022 | #ifdef CONFIG_PM |
2023 | .suspend = starfire_suspend, | |
2024 | .resume = starfire_resume, | |
2025 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
2026 | .id_table = starfire_pci_tbl, |
2027 | }; | |
2028 | ||
2029 | ||
2030 | static int __init starfire_init (void) | |
2031 | { | |
2032 | /* when a module, this is printed whether or not devices are found in probe */ | |
2033 | #ifdef MODULE | |
2034 | printk(version); | |
a6676019 | 2035 | |
fdecea66 | 2036 | printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n"); |
fdecea66 JG |
2037 | #endif |
2038 | ||
56543af9 | 2039 | BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t)); |
67974231 | 2040 | |
29917620 | 2041 | return pci_register_driver(&starfire_driver); |
1da177e4 LT |
2042 | } |
2043 | ||
2044 | ||
2045 | static void __exit starfire_cleanup (void) | |
2046 | { | |
2047 | pci_unregister_driver (&starfire_driver); | |
2048 | } | |
2049 | ||
2050 | ||
2051 | module_init(starfire_init); | |
2052 | module_exit(starfire_cleanup); | |
2053 | ||
2054 | ||
2055 | /* | |
2056 | * Local variables: | |
2057 | * c-basic-offset: 8 | |
2058 | * tab-width: 8 | |
2059 | * End: | |
2060 | */ |