Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
02460d08 | 4 | * Copyright 2004-2010 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
c6dd5098 MF |
11 | #define DRV_VERSION "1.1" |
12 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" | |
13 | ||
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
15 | ||
e190d6b1 BW |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/crc32.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/spinlock.h> | |
e190d6b1 | 30 | #include <linux/mii.h> |
e190d6b1 BW |
31 | #include <linux/netdevice.h> |
32 | #include <linux/etherdevice.h> | |
679dce39 | 33 | #include <linux/ethtool.h> |
e190d6b1 | 34 | #include <linux/skbuff.h> |
e190d6b1 | 35 | #include <linux/platform_device.h> |
e190d6b1 BW |
36 | |
37 | #include <asm/dma.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | ||
fe92afed | 40 | #include <asm/div64.h> |
98f672ca | 41 | #include <asm/dpmc.h> |
e190d6b1 BW |
42 | #include <asm/blackfin.h> |
43 | #include <asm/cacheflush.h> | |
44 | #include <asm/portmux.h> | |
3dcc1e7f | 45 | #include <mach/pll.h> |
e190d6b1 BW |
46 | |
47 | #include "bfin_mac.h" | |
48 | ||
c6dd5098 | 49 | MODULE_AUTHOR("Bryan Wu, Luke Yang"); |
e190d6b1 BW |
50 | MODULE_LICENSE("GPL"); |
51 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 52 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
53 | |
54 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
118133e6 SZ |
55 | # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num) |
56 | # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr) | |
e190d6b1 | 57 | #else |
118133e6 SZ |
58 | # define bfin_mac_alloc(dma_handle, size, num) \ |
59 | dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL) | |
60 | # define bfin_mac_free(dma_handle, ptr, num) \ | |
61 | dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle) | |
e190d6b1 BW |
62 | #endif |
63 | ||
64 | #define PKT_BUF_SZ 1580 | |
65 | ||
66 | #define MAX_TIMEOUT_CNT 500 | |
67 | ||
68 | /* pointers to maintain transmit list */ | |
69 | static struct net_dma_desc_tx *tx_list_head; | |
70 | static struct net_dma_desc_tx *tx_list_tail; | |
71 | static struct net_dma_desc_rx *rx_list_head; | |
72 | static struct net_dma_desc_rx *rx_list_tail; | |
73 | static struct net_dma_desc_rx *current_rx_ptr; | |
74 | static struct net_dma_desc_tx *current_tx_ptr; | |
75 | static struct net_dma_desc_tx *tx_desc; | |
76 | static struct net_dma_desc_rx *rx_desc; | |
77 | ||
78 | static void desc_list_free(void) | |
79 | { | |
80 | struct net_dma_desc_rx *r; | |
81 | struct net_dma_desc_tx *t; | |
82 | int i; | |
83 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
84 | dma_addr_t dma_handle = 0; | |
85 | #endif | |
86 | ||
87 | if (tx_desc) { | |
88 | t = tx_list_head; | |
89 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
90 | if (t) { | |
91 | if (t->skb) { | |
92 | dev_kfree_skb(t->skb); | |
93 | t->skb = NULL; | |
94 | } | |
95 | t = t->next; | |
96 | } | |
97 | } | |
118133e6 | 98 | bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM); |
e190d6b1 BW |
99 | } |
100 | ||
101 | if (rx_desc) { | |
102 | r = rx_list_head; | |
103 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
104 | if (r) { | |
105 | if (r->skb) { | |
106 | dev_kfree_skb(r->skb); | |
107 | r->skb = NULL; | |
108 | } | |
109 | r = r->next; | |
110 | } | |
111 | } | |
118133e6 | 112 | bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM); |
e190d6b1 BW |
113 | } |
114 | } | |
115 | ||
1ab0d2ec | 116 | static int desc_list_init(struct net_device *dev) |
e190d6b1 BW |
117 | { |
118 | int i; | |
119 | struct sk_buff *new_skb; | |
120 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
121 | /* | |
122 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
123 | * The real dma handler is the return value of dma_alloc_coherent(). | |
124 | */ | |
125 | dma_addr_t dma_handle; | |
126 | #endif | |
127 | ||
128 | tx_desc = bfin_mac_alloc(&dma_handle, | |
118133e6 | 129 | sizeof(struct net_dma_desc_tx), |
e190d6b1 BW |
130 | CONFIG_BFIN_TX_DESC_NUM); |
131 | if (tx_desc == NULL) | |
132 | goto init_error; | |
133 | ||
134 | rx_desc = bfin_mac_alloc(&dma_handle, | |
118133e6 | 135 | sizeof(struct net_dma_desc_rx), |
e190d6b1 BW |
136 | CONFIG_BFIN_RX_DESC_NUM); |
137 | if (rx_desc == NULL) | |
138 | goto init_error; | |
139 | ||
140 | /* init tx_list */ | |
141 | tx_list_head = tx_list_tail = tx_desc; | |
142 | ||
143 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
144 | struct net_dma_desc_tx *t = tx_desc + i; | |
145 | struct dma_descriptor *a = &(t->desc_a); | |
146 | struct dma_descriptor *b = &(t->desc_b); | |
147 | ||
148 | /* | |
149 | * disable DMA | |
150 | * read from memory WNR = 0 | |
151 | * wordsize is 32 bits | |
152 | * 6 half words is desc size | |
153 | * large desc flow | |
154 | */ | |
155 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
156 | a->start_addr = (unsigned long)t->packet; | |
157 | a->x_count = 0; | |
158 | a->next_dma_desc = b; | |
159 | ||
160 | /* | |
161 | * enabled DMA | |
162 | * write to memory WNR = 1 | |
163 | * wordsize is 32 bits | |
164 | * disable interrupt | |
165 | * 6 half words is desc size | |
166 | * large desc flow | |
167 | */ | |
168 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
169 | b->start_addr = (unsigned long)(&(t->status)); | |
170 | b->x_count = 0; | |
171 | ||
172 | t->skb = NULL; | |
173 | tx_list_tail->desc_b.next_dma_desc = a; | |
174 | tx_list_tail->next = t; | |
175 | tx_list_tail = t; | |
176 | } | |
177 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
178 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
179 | current_tx_ptr = tx_list_head; | |
180 | ||
181 | /* init rx_list */ | |
182 | rx_list_head = rx_list_tail = rx_desc; | |
183 | ||
184 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
185 | struct net_dma_desc_rx *r = rx_desc + i; | |
186 | struct dma_descriptor *a = &(r->desc_a); | |
187 | struct dma_descriptor *b = &(r->desc_b); | |
188 | ||
189 | /* allocate a new skb for next time receive */ | |
1ab0d2ec | 190 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
720a43ef | 191 | if (!new_skb) |
e190d6b1 | 192 | goto init_error; |
720a43ef | 193 | |
015dac88 | 194 | skb_reserve(new_skb, NET_IP_ALIGN); |
f6e1e4f3 SZ |
195 | /* Invidate the data cache of skb->data range when it is write back |
196 | * cache. It will prevent overwritting the new data from DMA | |
197 | */ | |
198 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
199 | (unsigned long)new_skb->end); | |
e190d6b1 BW |
200 | r->skb = new_skb; |
201 | ||
202 | /* | |
203 | * enabled DMA | |
204 | * write to memory WNR = 1 | |
205 | * wordsize is 32 bits | |
206 | * disable interrupt | |
207 | * 6 half words is desc size | |
208 | * large desc flow | |
209 | */ | |
210 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
211 | /* since RXDWA is enabled */ | |
212 | a->start_addr = (unsigned long)new_skb->data - 2; | |
213 | a->x_count = 0; | |
214 | a->next_dma_desc = b; | |
215 | ||
216 | /* | |
217 | * enabled DMA | |
218 | * write to memory WNR = 1 | |
219 | * wordsize is 32 bits | |
220 | * enable interrupt | |
221 | * 6 half words is desc size | |
222 | * large desc flow | |
223 | */ | |
224 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
225 | NDSIZE_6 | DMAFLOW_LARGE; | |
226 | b->start_addr = (unsigned long)(&(r->status)); | |
227 | b->x_count = 0; | |
228 | ||
229 | rx_list_tail->desc_b.next_dma_desc = a; | |
230 | rx_list_tail->next = r; | |
231 | rx_list_tail = r; | |
232 | } | |
233 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
234 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
235 | current_rx_ptr = rx_list_head; | |
236 | ||
237 | return 0; | |
238 | ||
239 | init_error: | |
240 | desc_list_free(); | |
c6dd5098 | 241 | pr_err("kmalloc failed\n"); |
e190d6b1 BW |
242 | return -ENOMEM; |
243 | } | |
244 | ||
245 | ||
246 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
247 | ||
4ae5a3ad BW |
248 | /* |
249 | * MII operations | |
250 | */ | |
e190d6b1 | 251 | /* Wait until the previous MDC/MDIO transaction has completed */ |
2bfa0f0c | 252 | static int bfin_mdio_poll(void) |
e190d6b1 BW |
253 | { |
254 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
255 | ||
256 | /* poll the STABUSY bit */ | |
257 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 258 | udelay(1); |
e190d6b1 | 259 | if (timeout_cnt-- < 0) { |
c6dd5098 | 260 | pr_err("wait MDC/MDIO transaction to complete timeout\n"); |
2bfa0f0c | 261 | return -ETIMEDOUT; |
e190d6b1 BW |
262 | } |
263 | } | |
2bfa0f0c MF |
264 | |
265 | return 0; | |
e190d6b1 BW |
266 | } |
267 | ||
268 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e | 269 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 270 | { |
2bfa0f0c MF |
271 | int ret; |
272 | ||
273 | ret = bfin_mdio_poll(); | |
274 | if (ret) | |
275 | return ret; | |
4ae5a3ad | 276 | |
e190d6b1 | 277 | /* read mode */ |
4ae5a3ad BW |
278 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
279 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 280 | STABUSY); |
e190d6b1 | 281 | |
2bfa0f0c MF |
282 | ret = bfin_mdio_poll(); |
283 | if (ret) | |
284 | return ret; | |
4ae5a3ad BW |
285 | |
286 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
287 | } |
288 | ||
289 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e AB |
290 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
291 | u16 value) | |
e190d6b1 | 292 | { |
2bfa0f0c MF |
293 | int ret; |
294 | ||
295 | ret = bfin_mdio_poll(); | |
296 | if (ret) | |
297 | return ret; | |
4ae5a3ad BW |
298 | |
299 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
300 | |
301 | /* write mode */ | |
4ae5a3ad BW |
302 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
303 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
304 | STAOP | |
305 | STABUSY); | |
306 | ||
2bfa0f0c | 307 | return bfin_mdio_poll(); |
e190d6b1 BW |
308 | } |
309 | ||
0ed0563e | 310 | static int bfin_mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 311 | { |
4ae5a3ad | 312 | return 0; |
e190d6b1 BW |
313 | } |
314 | ||
7ef0a7ee | 315 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 316 | { |
7ef0a7ee | 317 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
318 | struct phy_device *phydev = lp->phydev; |
319 | unsigned long flags; | |
320 | int new_state = 0; | |
321 | ||
322 | spin_lock_irqsave(&lp->lock, flags); | |
323 | if (phydev->link) { | |
324 | /* Now we make sure that we can be in full duplex mode. | |
325 | * If not, we operate in half-duplex mode. */ | |
326 | if (phydev->duplex != lp->old_duplex) { | |
327 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
328 | new_state = 1; | |
329 | ||
330 | if (phydev->duplex) | |
331 | opmode |= FDMODE; | |
332 | else | |
333 | opmode &= ~(FDMODE); | |
334 | ||
335 | bfin_write_EMAC_OPMODE(opmode); | |
336 | lp->old_duplex = phydev->duplex; | |
337 | } | |
e190d6b1 | 338 | |
4ae5a3ad | 339 | if (phydev->speed != lp->old_speed) { |
02460d08 SZ |
340 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
341 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
342 | switch (phydev->speed) { | |
343 | case 10: | |
344 | opmode |= RMII_10; | |
345 | break; | |
346 | case 100: | |
347 | opmode &= ~RMII_10; | |
348 | break; | |
349 | default: | |
c6dd5098 MF |
350 | netdev_warn(dev, |
351 | "Ack! Speed (%d) is not 10/100!\n", | |
352 | phydev->speed); | |
02460d08 SZ |
353 | break; |
354 | } | |
355 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 356 | } |
e190d6b1 | 357 | |
4ae5a3ad BW |
358 | new_state = 1; |
359 | lp->old_speed = phydev->speed; | |
360 | } | |
e190d6b1 | 361 | |
4ae5a3ad BW |
362 | if (!lp->old_link) { |
363 | new_state = 1; | |
364 | lp->old_link = 1; | |
4ae5a3ad BW |
365 | } |
366 | } else if (lp->old_link) { | |
367 | new_state = 1; | |
368 | lp->old_link = 0; | |
369 | lp->old_speed = 0; | |
370 | lp->old_duplex = -1; | |
e190d6b1 BW |
371 | } |
372 | ||
4ae5a3ad BW |
373 | if (new_state) { |
374 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
375 | phy_print_status(phydev); | |
376 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 377 | } |
4ae5a3ad BW |
378 | |
379 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
380 | } |
381 | ||
7cc8f381 BW |
382 | /* MDC = 2.5 MHz */ |
383 | #define MDC_CLK 2500000 | |
384 | ||
02460d08 | 385 | static int mii_probe(struct net_device *dev, int phy_mode) |
e190d6b1 | 386 | { |
7ef0a7ee | 387 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
388 | struct phy_device *phydev = NULL; |
389 | unsigned short sysctl; | |
390 | int i; | |
7cc8f381 | 391 | u32 sclk, mdc_div; |
e190d6b1 | 392 | |
4ae5a3ad | 393 | /* Enable PHY output early */ |
98f672ca MF |
394 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
395 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); | |
e190d6b1 | 396 | |
7cc8f381 BW |
397 | sclk = get_sclk(); |
398 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
399 | ||
4ae5a3ad | 400 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 401 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 402 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 403 | |
02460d08 SZ |
404 | /* search for connected PHY device */ |
405 | for (i = 0; i < PHY_MAX_ADDR; ++i) { | |
298cf9be | 406 | struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; |
e190d6b1 | 407 | |
4ae5a3ad BW |
408 | if (!tmp_phydev) |
409 | continue; /* no PHY here... */ | |
e190d6b1 | 410 | |
4ae5a3ad BW |
411 | phydev = tmp_phydev; |
412 | break; /* found it */ | |
413 | } | |
414 | ||
415 | /* now we are supposed to have a proper phydev, to attach to... */ | |
416 | if (!phydev) { | |
c6dd5098 | 417 | netdev_err(dev, "no phy device found\n"); |
4ae5a3ad | 418 | return -ENODEV; |
e190d6b1 BW |
419 | } |
420 | ||
02460d08 SZ |
421 | if (phy_mode != PHY_INTERFACE_MODE_RMII && |
422 | phy_mode != PHY_INTERFACE_MODE_MII) { | |
c6dd5098 | 423 | netdev_err(dev, "invalid phy interface mode\n"); |
02460d08 SZ |
424 | return -EINVAL; |
425 | } | |
426 | ||
f9a8f83b FF |
427 | phydev = phy_connect(dev, dev_name(&phydev->dev), |
428 | &bfin_mac_adjust_link, phy_mode); | |
e190d6b1 | 429 | |
4ae5a3ad | 430 | if (IS_ERR(phydev)) { |
c6dd5098 | 431 | netdev_err(dev, "could not attach PHY\n"); |
4ae5a3ad BW |
432 | return PTR_ERR(phydev); |
433 | } | |
434 | ||
435 | /* mask with MAC supported features */ | |
436 | phydev->supported &= (SUPPORTED_10baseT_Half | |
437 | | SUPPORTED_10baseT_Full | |
438 | | SUPPORTED_100baseT_Half | |
439 | | SUPPORTED_100baseT_Full | |
440 | | SUPPORTED_Autoneg | |
441 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
442 | | SUPPORTED_MII | |
443 | | SUPPORTED_TP); | |
444 | ||
445 | phydev->advertising = phydev->supported; | |
446 | ||
447 | lp->old_link = 0; | |
448 | lp->old_speed = 0; | |
449 | lp->old_duplex = -1; | |
450 | lp->phydev = phydev; | |
451 | ||
c6dd5098 MF |
452 | pr_info("attached PHY driver [%s] " |
453 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", | |
454 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq, | |
455 | MDC_CLK, mdc_div, sclk/1000000); | |
4ae5a3ad BW |
456 | |
457 | return 0; | |
458 | } | |
459 | ||
679dce39 BW |
460 | /* |
461 | * Ethtool support | |
462 | */ | |
463 | ||
53fd3f28 MH |
464 | /* |
465 | * interrupt routine for magic packet wakeup | |
466 | */ | |
467 | static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) | |
468 | { | |
469 | return IRQ_HANDLED; | |
470 | } | |
471 | ||
679dce39 BW |
472 | static int |
473 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
474 | { | |
475 | struct bfin_mac_local *lp = netdev_priv(dev); | |
476 | ||
477 | if (lp->phydev) | |
478 | return phy_ethtool_gset(lp->phydev, cmd); | |
479 | ||
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | static int | |
484 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
485 | { | |
486 | struct bfin_mac_local *lp = netdev_priv(dev); | |
487 | ||
488 | if (!capable(CAP_NET_ADMIN)) | |
489 | return -EPERM; | |
490 | ||
491 | if (lp->phydev) | |
492 | return phy_ethtool_sset(lp->phydev, cmd); | |
493 | ||
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
498 | struct ethtool_drvinfo *info) | |
499 | { | |
7826d43f JP |
500 | strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); |
501 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
502 | strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); | |
503 | strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); | |
679dce39 BW |
504 | } |
505 | ||
53fd3f28 MH |
506 | static void bfin_mac_ethtool_getwol(struct net_device *dev, |
507 | struct ethtool_wolinfo *wolinfo) | |
508 | { | |
509 | struct bfin_mac_local *lp = netdev_priv(dev); | |
510 | ||
511 | wolinfo->supported = WAKE_MAGIC; | |
512 | wolinfo->wolopts = lp->wol; | |
513 | } | |
514 | ||
515 | static int bfin_mac_ethtool_setwol(struct net_device *dev, | |
516 | struct ethtool_wolinfo *wolinfo) | |
517 | { | |
518 | struct bfin_mac_local *lp = netdev_priv(dev); | |
519 | int rc; | |
520 | ||
521 | if (wolinfo->wolopts & (WAKE_MAGICSECURE | | |
522 | WAKE_UCAST | | |
523 | WAKE_MCAST | | |
524 | WAKE_BCAST | | |
525 | WAKE_ARP)) | |
526 | return -EOPNOTSUPP; | |
527 | ||
528 | lp->wol = wolinfo->wolopts; | |
529 | ||
530 | if (lp->wol && !lp->irq_wake_requested) { | |
531 | /* register wake irq handler */ | |
532 | rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, | |
63aca0f7 | 533 | 0, "EMAC_WAKE", dev); |
53fd3f28 MH |
534 | if (rc) |
535 | return rc; | |
536 | lp->irq_wake_requested = true; | |
537 | } | |
538 | ||
539 | if (!lp->wol && lp->irq_wake_requested) { | |
540 | free_irq(IRQ_MAC_WAKEDET, dev); | |
541 | lp->irq_wake_requested = false; | |
542 | } | |
543 | ||
544 | /* Make sure the PHY driver doesn't suspend */ | |
545 | device_init_wakeup(&dev->dev, lp->wol); | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
85c153d2 | 550 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
a85bbddd | 551 | static int bfin_mac_ethtool_get_ts_info(struct net_device *dev, |
3ffa4290 | 552 | struct ethtool_ts_info *info) |
a85bbddd | 553 | { |
dd87b22f RC |
554 | struct bfin_mac_local *lp = netdev_priv(dev); |
555 | ||
a85bbddd RC |
556 | info->so_timestamping = |
557 | SOF_TIMESTAMPING_TX_HARDWARE | | |
558 | SOF_TIMESTAMPING_RX_HARDWARE | | |
bc3c5f63 | 559 | SOF_TIMESTAMPING_RAW_HARDWARE; |
dd87b22f | 560 | info->phc_index = lp->phc_index; |
a85bbddd RC |
561 | info->tx_types = |
562 | (1 << HWTSTAMP_TX_OFF) | | |
563 | (1 << HWTSTAMP_TX_ON); | |
564 | info->rx_filters = | |
565 | (1 << HWTSTAMP_FILTER_NONE) | | |
566 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | | |
567 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | | |
568 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); | |
569 | return 0; | |
570 | } | |
85c153d2 | 571 | #endif |
a85bbddd | 572 | |
0fc0b732 | 573 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
679dce39 BW |
574 | .get_settings = bfin_mac_ethtool_getsettings, |
575 | .set_settings = bfin_mac_ethtool_setsettings, | |
576 | .get_link = ethtool_op_get_link, | |
577 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
53fd3f28 MH |
578 | .get_wol = bfin_mac_ethtool_getwol, |
579 | .set_wol = bfin_mac_ethtool_setwol, | |
85c153d2 | 580 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
a85bbddd | 581 | .get_ts_info = bfin_mac_ethtool_get_ts_info, |
85c153d2 | 582 | #endif |
679dce39 BW |
583 | }; |
584 | ||
4ae5a3ad | 585 | /**************************************************************************/ |
5ca1bb5a | 586 | static void setup_system_regs(struct net_device *dev) |
4ae5a3ad | 587 | { |
02460d08 SZ |
588 | struct bfin_mac_local *lp = netdev_priv(dev); |
589 | int i; | |
4ae5a3ad BW |
590 | unsigned short sysctl; |
591 | ||
592 | /* | |
593 | * Odd word alignment for Receive Frame DMA word | |
594 | * Configure checksum support and rcve frame word alignment | |
595 | */ | |
596 | sysctl = bfin_read_EMAC_SYSCTL(); | |
02460d08 SZ |
597 | /* |
598 | * check if interrupt is requested for any PHY, | |
599 | * enable PHY interrupt only if needed | |
600 | */ | |
601 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
602 | if (lp->mii_bus->irq[i] != PHY_POLL) | |
603 | break; | |
604 | if (i < PHY_MAX_ADDR) | |
605 | sysctl |= PHYIE; | |
812a9de7 | 606 | sysctl |= RXDWA; |
4ae5a3ad | 607 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
812a9de7 | 608 | sysctl |= RXCKS; |
4ae5a3ad | 609 | #else |
812a9de7 | 610 | sysctl &= ~RXCKS; |
4ae5a3ad BW |
611 | #endif |
612 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
613 | |
614 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
615 | ||
c599bd6b MF |
616 | /* Set vlan regs to let 1522 bytes long packets pass through */ |
617 | bfin_write_EMAC_VLAN1(lp->vlan1_mask); | |
618 | bfin_write_EMAC_VLAN2(lp->vlan2_mask); | |
619 | ||
e190d6b1 BW |
620 | /* Initialize the TX DMA channel registers */ |
621 | bfin_write_DMA2_X_COUNT(0); | |
622 | bfin_write_DMA2_X_MODIFY(4); | |
623 | bfin_write_DMA2_Y_COUNT(0); | |
624 | bfin_write_DMA2_Y_MODIFY(0); | |
625 | ||
626 | /* Initialize the RX DMA channel registers */ | |
627 | bfin_write_DMA1_X_COUNT(0); | |
628 | bfin_write_DMA1_X_MODIFY(4); | |
629 | bfin_write_DMA1_Y_COUNT(0); | |
630 | bfin_write_DMA1_Y_MODIFY(0); | |
631 | } | |
632 | ||
73f83182 | 633 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
634 | { |
635 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
636 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
637 | ||
638 | /* this depends on a little-endian machine */ | |
639 | bfin_write_EMAC_ADDRLO(addr_low); | |
640 | bfin_write_EMAC_ADDRHI(addr_hi); | |
641 | } | |
642 | ||
7ef0a7ee | 643 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
644 | { |
645 | struct sockaddr *addr = p; | |
646 | if (netif_running(dev)) | |
647 | return -EBUSY; | |
648 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
649 | setup_mac_addr(dev->dev_addr); | |
650 | return 0; | |
651 | } | |
652 | ||
fe92afed BS |
653 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
654 | #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) | |
655 | ||
bc3c5f63 RC |
656 | static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result) |
657 | { | |
658 | u32 ipn = 1000000000UL / input_clk; | |
659 | u32 ppn = 1; | |
660 | unsigned int shift = 0; | |
661 | ||
662 | while (ppn <= ipn) { | |
663 | ppn <<= 1; | |
664 | shift++; | |
665 | } | |
666 | *shift_result = shift; | |
667 | return 1000000000UL / ppn; | |
668 | } | |
669 | ||
7575c917 BH |
670 | static int bfin_mac_hwtstamp_set(struct net_device *netdev, |
671 | struct ifreq *ifr) | |
fe92afed BS |
672 | { |
673 | struct hwtstamp_config config; | |
674 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
675 | u16 ptpctl; | |
676 | u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; | |
677 | ||
678 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
679 | return -EFAULT; | |
680 | ||
681 | pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
682 | __func__, config.flags, config.tx_type, config.rx_filter); | |
683 | ||
684 | /* reserved for future extensions */ | |
685 | if (config.flags) | |
686 | return -EINVAL; | |
687 | ||
688 | if ((config.tx_type != HWTSTAMP_TX_OFF) && | |
689 | (config.tx_type != HWTSTAMP_TX_ON)) | |
690 | return -ERANGE; | |
691 | ||
692 | ptpctl = bfin_read_EMAC_PTP_CTL(); | |
693 | ||
694 | switch (config.rx_filter) { | |
695 | case HWTSTAMP_FILTER_NONE: | |
696 | /* | |
697 | * Dont allow any timestamping | |
698 | */ | |
699 | ptpfv3 = 0xFFFFFFFF; | |
700 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
701 | break; | |
702 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
703 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
704 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
705 | /* | |
706 | * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) | |
707 | * to enable all the field matches. | |
708 | */ | |
709 | ptpctl &= ~0x1F00; | |
710 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
711 | /* | |
712 | * Keep the default values of the EMAC_PTP_FOFF register. | |
713 | */ | |
714 | ptpfoff = 0x4A24170C; | |
715 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
716 | /* | |
717 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
718 | * registers. | |
719 | */ | |
720 | ptpfv1 = 0x11040800; | |
721 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
722 | ptpfv2 = 0x0140013F; | |
723 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
724 | /* | |
725 | * The default value (0xFFFC) allows the timestamping of both | |
726 | * received Sync messages and Delay_Req messages. | |
727 | */ | |
728 | ptpfv3 = 0xFFFFFFFC; | |
729 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
730 | ||
731 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
732 | break; | |
733 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
734 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
735 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
736 | /* Clear all five comparison mask bits (bits[12:8]) in the | |
737 | * EMAC_PTP_CTL register to enable all the field matches. | |
738 | */ | |
739 | ptpctl &= ~0x1F00; | |
740 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
741 | /* | |
742 | * Keep the default values of the EMAC_PTP_FOFF register, except set | |
743 | * the PTPCOF field to 0x2A. | |
744 | */ | |
745 | ptpfoff = 0x2A24170C; | |
746 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
747 | /* | |
748 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
749 | * registers. | |
750 | */ | |
751 | ptpfv1 = 0x11040800; | |
752 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
753 | ptpfv2 = 0x0140013F; | |
754 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
755 | /* | |
756 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set | |
757 | * the value to 0xFFF0. | |
758 | */ | |
759 | ptpfv3 = 0xFFFFFFF0; | |
760 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
761 | ||
762 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
763 | break; | |
764 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
765 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
766 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
767 | /* | |
768 | * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the | |
769 | * EFTM and PTPCM field comparison. | |
770 | */ | |
771 | ptpctl &= ~0x1100; | |
772 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
773 | /* | |
774 | * Keep the default values of all the fields of the EMAC_PTP_FOFF | |
775 | * register, except set the PTPCOF field to 0x0E. | |
776 | */ | |
777 | ptpfoff = 0x0E24170C; | |
778 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
779 | /* | |
780 | * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which | |
781 | * corresponds to PTP messages on the MAC layer. | |
782 | */ | |
783 | ptpfv1 = 0x110488F7; | |
784 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
785 | ptpfv2 = 0x0140013F; | |
786 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
787 | /* | |
788 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp | |
789 | * messages, set the value to 0xFFF0. | |
790 | */ | |
791 | ptpfv3 = 0xFFFFFFF0; | |
792 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
793 | ||
794 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
795 | break; | |
796 | default: | |
797 | return -ERANGE; | |
798 | } | |
799 | ||
800 | if (config.tx_type == HWTSTAMP_TX_OFF && | |
801 | bfin_mac_hwtstamp_is_none(config.rx_filter)) { | |
802 | ptpctl &= ~PTP_EN; | |
803 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
804 | ||
805 | SSYNC(); | |
806 | } else { | |
807 | ptpctl |= PTP_EN; | |
808 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
809 | ||
810 | /* | |
811 | * clear any existing timestamp | |
812 | */ | |
813 | bfin_read_EMAC_PTP_RXSNAPLO(); | |
814 | bfin_read_EMAC_PTP_RXSNAPHI(); | |
815 | ||
816 | bfin_read_EMAC_PTP_TXSNAPLO(); | |
817 | bfin_read_EMAC_PTP_TXSNAPHI(); | |
818 | ||
fe92afed | 819 | SSYNC(); |
fe92afed BS |
820 | } |
821 | ||
822 | lp->stamp_cfg = config; | |
823 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
824 | -EFAULT : 0; | |
825 | } | |
826 | ||
7575c917 BH |
827 | static int bfin_mac_hwtstamp_get(struct net_device *netdev, |
828 | struct ifreq *ifr) | |
829 | { | |
830 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
831 | ||
832 | return copy_to_user(ifr->ifr_data, &lp->stamp_cfg, | |
833 | sizeof(lp->stamp_cfg)) ? | |
834 | -EFAULT : 0; | |
835 | } | |
836 | ||
fe92afed BS |
837 | static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) |
838 | { | |
839 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
fe92afed | 840 | |
2244d07b | 841 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { |
fe92afed BS |
842 | int timeout_cnt = MAX_TIMEOUT_CNT; |
843 | ||
844 | /* When doing time stamping, keep the connection to the socket | |
845 | * a while longer | |
846 | */ | |
2244d07b | 847 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
fe92afed BS |
848 | |
849 | /* | |
850 | * The timestamping is done at the EMAC module's MII/RMII interface | |
851 | * when the module sees the Start of Frame of an event message packet. This | |
852 | * interface is the closest possible place to the physical Ethernet transmission | |
853 | * medium, providing the best timing accuracy. | |
854 | */ | |
855 | while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) | |
856 | udelay(1); | |
857 | if (timeout_cnt == 0) | |
c6dd5098 | 858 | netdev_err(netdev, "timestamp the TX packet failed\n"); |
fe92afed BS |
859 | else { |
860 | struct skb_shared_hwtstamps shhwtstamps; | |
861 | u64 ns; | |
862 | u64 regval; | |
863 | ||
864 | regval = bfin_read_EMAC_PTP_TXSNAPLO(); | |
865 | regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; | |
866 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
bc3c5f63 | 867 | ns = regval << lp->shift; |
fe92afed | 868 | shhwtstamps.hwtstamp = ns_to_ktime(ns); |
fe92afed | 869 | skb_tstamp_tx(skb, &shhwtstamps); |
fe92afed BS |
870 | } |
871 | } | |
872 | } | |
873 | ||
874 | static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
875 | { | |
876 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
877 | u32 valid; | |
878 | u64 regval, ns; | |
879 | struct skb_shared_hwtstamps *shhwtstamps; | |
880 | ||
881 | if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) | |
882 | return; | |
883 | ||
884 | valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; | |
885 | if (!valid) | |
886 | return; | |
887 | ||
888 | shhwtstamps = skb_hwtstamps(skb); | |
889 | ||
890 | regval = bfin_read_EMAC_PTP_RXSNAPLO(); | |
891 | regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; | |
bc3c5f63 | 892 | ns = regval << lp->shift; |
fe92afed BS |
893 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
894 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
fe92afed BS |
895 | } |
896 | ||
fe92afed BS |
897 | static void bfin_mac_hwtstamp_init(struct net_device *netdev) |
898 | { | |
899 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
dd87b22f | 900 | u64 addend, ppb; |
bc3c5f63 | 901 | u32 input_clk, phc_clk; |
fe92afed BS |
902 | |
903 | /* Initialize hardware timer */ | |
bc3c5f63 RC |
904 | input_clk = get_sclk(); |
905 | phc_clk = bfin_select_phc_clock(input_clk, &lp->shift); | |
906 | addend = phc_clk * (1ULL << 32); | |
907 | do_div(addend, input_clk); | |
908 | bfin_write_EMAC_PTP_ADDEND((u32)addend); | |
909 | ||
910 | lp->addend = addend; | |
dd87b22f RC |
911 | ppb = 1000000000ULL * input_clk; |
912 | do_div(ppb, phc_clk); | |
913 | lp->max_ppb = ppb - 1000000000ULL - 1ULL; | |
fe92afed BS |
914 | |
915 | /* Initialize hwstamp config */ | |
916 | lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; | |
917 | lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; | |
918 | } | |
919 | ||
dd87b22f RC |
920 | static u64 bfin_ptp_time_read(struct bfin_mac_local *lp) |
921 | { | |
922 | u64 ns; | |
923 | u32 lo, hi; | |
924 | ||
925 | lo = bfin_read_EMAC_PTP_TIMELO(); | |
926 | hi = bfin_read_EMAC_PTP_TIMEHI(); | |
927 | ||
928 | ns = ((u64) hi) << 32; | |
929 | ns |= lo; | |
930 | ns <<= lp->shift; | |
931 | ||
932 | return ns; | |
933 | } | |
934 | ||
935 | static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns) | |
936 | { | |
937 | u32 hi, lo; | |
938 | ||
939 | ns >>= lp->shift; | |
940 | hi = ns >> 32; | |
941 | lo = ns & 0xffffffff; | |
942 | ||
943 | bfin_write_EMAC_PTP_TIMELO(lo); | |
944 | bfin_write_EMAC_PTP_TIMEHI(hi); | |
945 | } | |
946 | ||
947 | /* PTP Hardware Clock operations */ | |
948 | ||
949 | static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
950 | { | |
951 | u64 adj; | |
952 | u32 diff, addend; | |
953 | int neg_adj = 0; | |
954 | struct bfin_mac_local *lp = | |
955 | container_of(ptp, struct bfin_mac_local, caps); | |
956 | ||
957 | if (ppb < 0) { | |
958 | neg_adj = 1; | |
959 | ppb = -ppb; | |
960 | } | |
961 | addend = lp->addend; | |
962 | adj = addend; | |
963 | adj *= ppb; | |
964 | diff = div_u64(adj, 1000000000ULL); | |
965 | ||
966 | addend = neg_adj ? addend - diff : addend + diff; | |
967 | ||
968 | bfin_write_EMAC_PTP_ADDEND(addend); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
974 | { | |
975 | s64 now; | |
976 | unsigned long flags; | |
977 | struct bfin_mac_local *lp = | |
978 | container_of(ptp, struct bfin_mac_local, caps); | |
979 | ||
980 | spin_lock_irqsave(&lp->phc_lock, flags); | |
981 | ||
982 | now = bfin_ptp_time_read(lp); | |
983 | now += delta; | |
984 | bfin_ptp_time_write(lp, now); | |
985 | ||
986 | spin_unlock_irqrestore(&lp->phc_lock, flags); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) | |
992 | { | |
993 | u64 ns; | |
994 | u32 remainder; | |
995 | unsigned long flags; | |
996 | struct bfin_mac_local *lp = | |
997 | container_of(ptp, struct bfin_mac_local, caps); | |
998 | ||
999 | spin_lock_irqsave(&lp->phc_lock, flags); | |
1000 | ||
1001 | ns = bfin_ptp_time_read(lp); | |
1002 | ||
1003 | spin_unlock_irqrestore(&lp->phc_lock, flags); | |
1004 | ||
1005 | ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); | |
1006 | ts->tv_nsec = remainder; | |
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static int bfin_ptp_settime(struct ptp_clock_info *ptp, | |
1011 | const struct timespec *ts) | |
1012 | { | |
1013 | u64 ns; | |
1014 | unsigned long flags; | |
1015 | struct bfin_mac_local *lp = | |
1016 | container_of(ptp, struct bfin_mac_local, caps); | |
1017 | ||
1018 | ns = ts->tv_sec * 1000000000ULL; | |
1019 | ns += ts->tv_nsec; | |
1020 | ||
1021 | spin_lock_irqsave(&lp->phc_lock, flags); | |
1022 | ||
1023 | bfin_ptp_time_write(lp, ns); | |
1024 | ||
1025 | spin_unlock_irqrestore(&lp->phc_lock, flags); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int bfin_ptp_enable(struct ptp_clock_info *ptp, | |
1031 | struct ptp_clock_request *rq, int on) | |
1032 | { | |
1033 | return -EOPNOTSUPP; | |
1034 | } | |
1035 | ||
1036 | static struct ptp_clock_info bfin_ptp_caps = { | |
1037 | .owner = THIS_MODULE, | |
1038 | .name = "BF518 clock", | |
1039 | .max_adj = 0, | |
1040 | .n_alarm = 0, | |
1041 | .n_ext_ts = 0, | |
1042 | .n_per_out = 0, | |
4986b4f0 | 1043 | .n_pins = 0, |
dd87b22f RC |
1044 | .pps = 0, |
1045 | .adjfreq = bfin_ptp_adjfreq, | |
1046 | .adjtime = bfin_ptp_adjtime, | |
1047 | .gettime = bfin_ptp_gettime, | |
1048 | .settime = bfin_ptp_settime, | |
1049 | .enable = bfin_ptp_enable, | |
1050 | }; | |
1051 | ||
1052 | static int bfin_phc_init(struct net_device *netdev, struct device *dev) | |
1053 | { | |
1054 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
1055 | ||
1056 | lp->caps = bfin_ptp_caps; | |
1057 | lp->caps.max_adj = lp->max_ppb; | |
1058 | lp->clock = ptp_clock_register(&lp->caps, dev); | |
1059 | if (IS_ERR(lp->clock)) | |
1060 | return PTR_ERR(lp->clock); | |
1061 | ||
1062 | lp->phc_index = ptp_clock_index(lp->clock); | |
1063 | spin_lock_init(&lp->phc_lock); | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static void bfin_phc_release(struct bfin_mac_local *lp) | |
1069 | { | |
1070 | ptp_clock_unregister(lp->clock); | |
1071 | } | |
1072 | ||
fe92afed BS |
1073 | #else |
1074 | # define bfin_mac_hwtstamp_is_none(cfg) 0 | |
1075 | # define bfin_mac_hwtstamp_init(dev) | |
7575c917 BH |
1076 | # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP) |
1077 | # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP) | |
fe92afed BS |
1078 | # define bfin_rx_hwtstamp(dev, skb) |
1079 | # define bfin_tx_hwtstamp(dev, skb) | |
dd87b22f RC |
1080 | # define bfin_phc_init(netdev, dev) 0 |
1081 | # define bfin_phc_release(lp) | |
fe92afed BS |
1082 | #endif |
1083 | ||
4fcc3d34 SZ |
1084 | static inline void _tx_reclaim_skb(void) |
1085 | { | |
1086 | do { | |
1087 | tx_list_head->desc_a.config &= ~DMAEN; | |
1088 | tx_list_head->status.status_word = 0; | |
1089 | if (tx_list_head->skb) { | |
1090 | dev_kfree_skb(tx_list_head->skb); | |
1091 | tx_list_head->skb = NULL; | |
1092 | } | |
1093 | tx_list_head = tx_list_head->next; | |
1094 | ||
1095 | } while (tx_list_head->status.status_word != 0); | |
1096 | } | |
1097 | ||
1098 | static void tx_reclaim_skb(struct bfin_mac_local *lp) | |
e190d6b1 BW |
1099 | { |
1100 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
1101 | ||
4fcc3d34 SZ |
1102 | if (tx_list_head->status.status_word != 0) |
1103 | _tx_reclaim_skb(); | |
e190d6b1 | 1104 | |
4fcc3d34 | 1105 | if (current_tx_ptr->next == tx_list_head) { |
e190d6b1 | 1106 | while (tx_list_head->status.status_word == 0) { |
4fcc3d34 | 1107 | /* slow down polling to avoid too many queue stop. */ |
015dac88 | 1108 | udelay(10); |
4fcc3d34 SZ |
1109 | /* reclaim skb if DMA is not running. */ |
1110 | if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) | |
1111 | break; | |
1112 | if (timeout_cnt-- < 0) | |
e190d6b1 | 1113 | break; |
e190d6b1 | 1114 | } |
4fcc3d34 SZ |
1115 | |
1116 | if (timeout_cnt >= 0) | |
1117 | _tx_reclaim_skb(); | |
1118 | else | |
1119 | netif_stop_queue(lp->ndev); | |
e190d6b1 BW |
1120 | } |
1121 | ||
4fcc3d34 SZ |
1122 | if (current_tx_ptr->next != tx_list_head && |
1123 | netif_queue_stopped(lp->ndev)) | |
1124 | netif_wake_queue(lp->ndev); | |
1125 | ||
1126 | if (tx_list_head != current_tx_ptr) { | |
1127 | /* shorten the timer interval if tx queue is stopped */ | |
1128 | if (netif_queue_stopped(lp->ndev)) | |
1129 | lp->tx_reclaim_timer.expires = | |
1130 | jiffies + (TX_RECLAIM_JIFFIES >> 4); | |
1131 | else | |
1132 | lp->tx_reclaim_timer.expires = | |
1133 | jiffies + TX_RECLAIM_JIFFIES; | |
1134 | ||
1135 | mod_timer(&lp->tx_reclaim_timer, | |
1136 | lp->tx_reclaim_timer.expires); | |
1137 | } | |
e190d6b1 | 1138 | |
e190d6b1 | 1139 | return; |
4fcc3d34 | 1140 | } |
e190d6b1 | 1141 | |
4fcc3d34 SZ |
1142 | static void tx_reclaim_skb_timeout(unsigned long lp) |
1143 | { | |
1144 | tx_reclaim_skb((struct bfin_mac_local *)lp); | |
e190d6b1 BW |
1145 | } |
1146 | ||
7ef0a7ee | 1147 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
1148 | struct net_device *dev) |
1149 | { | |
4fcc3d34 | 1150 | struct bfin_mac_local *lp = netdev_priv(dev); |
a50c0c05 | 1151 | u16 *data; |
015dac88 | 1152 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
fe92afed | 1153 | |
e190d6b1 BW |
1154 | current_tx_ptr->skb = skb; |
1155 | ||
015dac88 MH |
1156 | if (data_align == 0x2) { |
1157 | /* move skb->data to current_tx_ptr payload */ | |
1158 | data = (u16 *)(skb->data) - 1; | |
fe92afed BS |
1159 | *data = (u16)(skb->len); |
1160 | /* | |
1161 | * When transmitting an Ethernet packet, the PTP_TSYNC module requires | |
1162 | * a DMA_Length_Word field associated with the packet. The lower 12 bits | |
1163 | * of this field are the length of the packet payload in bytes and the higher | |
1164 | * 4 bits are the timestamping enable field. | |
1165 | */ | |
2244d07b | 1166 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
fe92afed BS |
1167 | *data |= 0x1000; |
1168 | ||
015dac88 MH |
1169 | current_tx_ptr->desc_a.start_addr = (u32)data; |
1170 | /* this is important! */ | |
1171 | blackfin_dcache_flush_range((u32)data, | |
1172 | (u32)((u8 *)data + skb->len + 4)); | |
e190d6b1 | 1173 | } else { |
015dac88 | 1174 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
fe92afed | 1175 | /* enable timestamping for the sent packet */ |
2244d07b | 1176 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
fe92afed | 1177 | *((u16 *)(current_tx_ptr->packet)) |= 0x1000; |
015dac88 MH |
1178 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, |
1179 | skb->len); | |
1180 | current_tx_ptr->desc_a.start_addr = | |
1181 | (u32)current_tx_ptr->packet; | |
015dac88 MH |
1182 | blackfin_dcache_flush_range( |
1183 | (u32)current_tx_ptr->packet, | |
1184 | (u32)(current_tx_ptr->packet + skb->len + 2)); | |
e190d6b1 BW |
1185 | } |
1186 | ||
805a8ab3 SZ |
1187 | /* make sure the internal data buffers in the core are drained |
1188 | * so that the DMA descriptors are completely written when the | |
1189 | * DMA engine goes to fetch them below | |
1190 | */ | |
1191 | SSYNC(); | |
1192 | ||
4fcc3d34 SZ |
1193 | /* always clear status buffer before start tx dma */ |
1194 | current_tx_ptr->status.status_word = 0; | |
1195 | ||
e190d6b1 BW |
1196 | /* enable this packet's dma */ |
1197 | current_tx_ptr->desc_a.config |= DMAEN; | |
1198 | ||
1199 | /* tx dma is running, just return */ | |
015dac88 | 1200 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
e190d6b1 BW |
1201 | goto out; |
1202 | ||
1203 | /* tx dma is not running */ | |
1204 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
1205 | /* dma enabled, read from memory, size is 6 */ | |
1206 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
1207 | /* Turn on the EMAC tx */ | |
1208 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1209 | ||
1210 | out: | |
fe92afed BS |
1211 | bfin_tx_hwtstamp(dev, skb); |
1212 | ||
e190d6b1 | 1213 | current_tx_ptr = current_tx_ptr->next; |
09f75cd7 JG |
1214 | dev->stats.tx_packets++; |
1215 | dev->stats.tx_bytes += (skb->len); | |
4fcc3d34 SZ |
1216 | |
1217 | tx_reclaim_skb(lp); | |
1218 | ||
6ed10654 | 1219 | return NETDEV_TX_OK; |
e190d6b1 BW |
1220 | } |
1221 | ||
ad2864d8 | 1222 | #define IP_HEADER_OFF 0 |
ec497b32 PM |
1223 | #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ |
1224 | RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) | |
1225 | ||
7ef0a7ee | 1226 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
1227 | { |
1228 | struct sk_buff *skb, *new_skb; | |
e190d6b1 | 1229 | unsigned short len; |
fe92afed | 1230 | struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev); |
ad2864d8 SZ |
1231 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
1232 | unsigned int i; | |
1233 | unsigned char fcs[ETH_FCS_LEN + 1]; | |
1234 | #endif | |
e190d6b1 | 1235 | |
ec497b32 PM |
1236 | /* check if frame status word reports an error condition |
1237 | * we which case we simply drop the packet | |
1238 | */ | |
1239 | if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { | |
c6dd5098 | 1240 | netdev_notice(dev, "rx: receive error - packet dropped\n"); |
ec497b32 PM |
1241 | dev->stats.rx_dropped++; |
1242 | goto out; | |
1243 | } | |
1244 | ||
e190d6b1 BW |
1245 | /* allocate a new skb for next time receive */ |
1246 | skb = current_rx_ptr->skb; | |
fe92afed | 1247 | |
1ab0d2ec | 1248 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 | 1249 | if (!new_skb) { |
09f75cd7 | 1250 | dev->stats.rx_dropped++; |
e190d6b1 BW |
1251 | goto out; |
1252 | } | |
1253 | /* reserve 2 bytes for RXDWA padding */ | |
015dac88 | 1254 | skb_reserve(new_skb, NET_IP_ALIGN); |
6e01d1a4 AD |
1255 | /* Invidate the data cache of skb->data range when it is write back |
1256 | * cache. It will prevent overwritting the new data from DMA | |
1257 | */ | |
1258 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
1259 | (unsigned long)new_skb->end); | |
1260 | ||
f6e1e4f3 SZ |
1261 | current_rx_ptr->skb = new_skb; |
1262 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
1263 | ||
e190d6b1 | 1264 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
ad2864d8 SZ |
1265 | /* Deduce Ethernet FCS length from Ethernet payload length */ |
1266 | len -= ETH_FCS_LEN; | |
e190d6b1 | 1267 | skb_put(skb, len); |
e190d6b1 | 1268 | |
e190d6b1 | 1269 | skb->protocol = eth_type_trans(skb, dev); |
fe92afed BS |
1270 | |
1271 | bfin_rx_hwtstamp(dev, skb); | |
1272 | ||
e190d6b1 | 1273 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
ad2864d8 SZ |
1274 | /* Checksum offloading only works for IPv4 packets with the standard IP header |
1275 | * length of 20 bytes, because the blackfin MAC checksum calculation is | |
1276 | * based on that assumption. We must NOT use the calculated checksum if our | |
1277 | * IP version or header break that assumption. | |
1278 | */ | |
1279 | if (skb->data[IP_HEADER_OFF] == 0x45) { | |
1280 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
1281 | /* | |
1282 | * Deduce Ethernet FCS from hardware generated IP payload checksum. | |
1283 | * IP checksum is based on 16-bit one's complement algorithm. | |
1284 | * To deduce a value from checksum is equal to add its inversion. | |
1285 | * If the IP payload len is odd, the inversed FCS should also | |
1286 | * begin from odd address and leave first byte zero. | |
1287 | */ | |
1288 | if (skb->len % 2) { | |
1289 | fcs[0] = 0; | |
1290 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1291 | fcs[i + 1] = ~skb->data[skb->len + i]; | |
1292 | skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); | |
1293 | } else { | |
1294 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1295 | fcs[i] = ~skb->data[skb->len + i]; | |
1296 | skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); | |
1297 | } | |
1298 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1299 | } | |
e190d6b1 BW |
1300 | #endif |
1301 | ||
1302 | netif_rx(skb); | |
09f75cd7 JG |
1303 | dev->stats.rx_packets++; |
1304 | dev->stats.rx_bytes += len; | |
ec497b32 | 1305 | out: |
e190d6b1 BW |
1306 | current_rx_ptr->status.status_word = 0x00000000; |
1307 | current_rx_ptr = current_rx_ptr->next; | |
e190d6b1 BW |
1308 | } |
1309 | ||
1310 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 1311 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
1312 | { |
1313 | struct net_device *dev = dev_id; | |
1314 | int number = 0; | |
1315 | ||
1316 | get_one_packet: | |
1317 | if (current_rx_ptr->status.status_word == 0) { | |
1318 | /* no more new packet received */ | |
1319 | if (number == 0) { | |
1320 | if (current_rx_ptr->next->status.status_word != 0) { | |
1321 | current_rx_ptr = current_rx_ptr->next; | |
1322 | goto real_rx; | |
1323 | } | |
1324 | } | |
1325 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
1326 | DMA_DONE | DMA_ERR); | |
1327 | return IRQ_HANDLED; | |
1328 | } | |
1329 | ||
1330 | real_rx: | |
7ef0a7ee | 1331 | bfin_mac_rx(dev); |
e190d6b1 BW |
1332 | number++; |
1333 | goto get_one_packet; | |
1334 | } | |
1335 | ||
1336 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 1337 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 | 1338 | { |
4fcc3d34 SZ |
1339 | struct bfin_mac_local *lp = netdev_priv(dev); |
1340 | ||
e190d6b1 | 1341 | disable_irq(IRQ_MAC_RX); |
7ef0a7ee | 1342 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
4fcc3d34 | 1343 | tx_reclaim_skb(lp); |
e190d6b1 BW |
1344 | enable_irq(IRQ_MAC_RX); |
1345 | } | |
1346 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1347 | ||
7ef0a7ee | 1348 | static void bfin_mac_disable(void) |
e190d6b1 BW |
1349 | { |
1350 | unsigned int opmode; | |
1351 | ||
1352 | opmode = bfin_read_EMAC_OPMODE(); | |
1353 | opmode &= (~RE); | |
1354 | opmode &= (~TE); | |
1355 | /* Turn off the EMAC */ | |
1356 | bfin_write_EMAC_OPMODE(opmode); | |
1357 | } | |
1358 | ||
1359 | /* | |
1360 | * Enable Interrupts, Receive, and Transmit | |
1361 | */ | |
02460d08 | 1362 | static int bfin_mac_enable(struct phy_device *phydev) |
e190d6b1 | 1363 | { |
2bfa0f0c | 1364 | int ret; |
e190d6b1 BW |
1365 | u32 opmode; |
1366 | ||
c6dd5098 | 1367 | pr_debug("%s\n", __func__); |
e190d6b1 BW |
1368 | |
1369 | /* Set RX DMA */ | |
1370 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
1371 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
1372 | ||
1373 | /* Wait MII done */ | |
2bfa0f0c MF |
1374 | ret = bfin_mdio_poll(); |
1375 | if (ret) | |
1376 | return ret; | |
e190d6b1 BW |
1377 | |
1378 | /* We enable only RX here */ | |
1379 | /* ASTP : Enable Automatic Pad Stripping | |
1380 | PR : Promiscuous Mode for test | |
1381 | PSF : Receive frames with total length less than 64 bytes. | |
1382 | FDMODE : Full Duplex Mode | |
1383 | LB : Internal Loopback for test | |
1384 | RE : Receiver Enable */ | |
1385 | opmode = bfin_read_EMAC_OPMODE(); | |
1386 | if (opmode & FDMODE) | |
1387 | opmode |= PSF; | |
1388 | else | |
1389 | opmode |= DRO | DC | PSF; | |
1390 | opmode |= RE; | |
1391 | ||
02460d08 SZ |
1392 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
1393 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
72f49050 MF |
1394 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) |
1395 | if (__SILICON_REVISION__ < 3) { | |
1396 | /* | |
1397 | * This isn't publicly documented (fun times!), but in | |
1398 | * silicon <=0.2, the RX and TX pins are clocked together. | |
1399 | * So in order to recv, we must enable the transmit side | |
1400 | * as well. This will cause a spurious TX interrupt too, | |
1401 | * but we can easily consume that. | |
1402 | */ | |
1403 | opmode |= TE; | |
1404 | } | |
e190d6b1 | 1405 | #endif |
02460d08 SZ |
1406 | } |
1407 | ||
e190d6b1 BW |
1408 | /* Turn on the EMAC rx */ |
1409 | bfin_write_EMAC_OPMODE(opmode); | |
2bfa0f0c MF |
1410 | |
1411 | return 0; | |
e190d6b1 BW |
1412 | } |
1413 | ||
1414 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 1415 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 | 1416 | { |
4fcc3d34 SZ |
1417 | struct bfin_mac_local *lp = netdev_priv(dev); |
1418 | ||
b39d66a8 | 1419 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 | 1420 | |
7ef0a7ee | 1421 | bfin_mac_disable(); |
e190d6b1 | 1422 | |
4fcc3d34 SZ |
1423 | del_timer(&lp->tx_reclaim_timer); |
1424 | ||
1425 | /* reset tx queue and free skb */ | |
1426 | while (tx_list_head != current_tx_ptr) { | |
1427 | tx_list_head->desc_a.config &= ~DMAEN; | |
1428 | tx_list_head->status.status_word = 0; | |
1429 | if (tx_list_head->skb) { | |
1430 | dev_kfree_skb(tx_list_head->skb); | |
1431 | tx_list_head->skb = NULL; | |
1432 | } | |
1433 | tx_list_head = tx_list_head->next; | |
1434 | } | |
1435 | ||
1436 | if (netif_queue_stopped(lp->ndev)) | |
1437 | netif_wake_queue(lp->ndev); | |
e190d6b1 | 1438 | |
02460d08 | 1439 | bfin_mac_enable(lp->phydev); |
e190d6b1 BW |
1440 | |
1441 | /* We can accept TX packets again */ | |
1ae5dc34 | 1442 | dev->trans_start = jiffies; /* prevent tx timeout */ |
e190d6b1 BW |
1443 | netif_wake_queue(dev); |
1444 | } | |
1445 | ||
7ef0a7ee | 1446 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
1447 | { |
1448 | u32 emac_hashhi, emac_hashlo; | |
22bedad3 | 1449 | struct netdev_hw_addr *ha; |
775919bc AW |
1450 | u32 crc; |
1451 | ||
1452 | emac_hashhi = emac_hashlo = 0; | |
1453 | ||
22bedad3 | 1454 | netdev_for_each_mc_addr(ha, dev) { |
f767b6df | 1455 | crc = ether_crc(ETH_ALEN, ha->addr); |
775919bc AW |
1456 | crc >>= 26; |
1457 | ||
1458 | if (crc & 0x20) | |
1459 | emac_hashhi |= 1 << (crc & 0x1f); | |
1460 | else | |
1461 | emac_hashlo |= 1 << (crc & 0x1f); | |
1462 | } | |
1463 | ||
1464 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
1465 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
775919bc AW |
1466 | } |
1467 | ||
e190d6b1 BW |
1468 | /* |
1469 | * This routine will, depending on the values passed to it, | |
1470 | * either make it accept multicast packets, go into | |
1471 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1472 | * a select set of multicast packets | |
1473 | */ | |
7ef0a7ee | 1474 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
1475 | { |
1476 | u32 sysctl; | |
1477 | ||
1478 | if (dev->flags & IFF_PROMISC) { | |
c6dd5098 | 1479 | netdev_info(dev, "set promisc mode\n"); |
e190d6b1 | 1480 | sysctl = bfin_read_EMAC_OPMODE(); |
c0da776b | 1481 | sysctl |= PR; |
e190d6b1 | 1482 | bfin_write_EMAC_OPMODE(sysctl); |
775919bc | 1483 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
1484 | /* accept all multicast */ |
1485 | sysctl = bfin_read_EMAC_OPMODE(); | |
1486 | sysctl |= PAM; | |
1487 | bfin_write_EMAC_OPMODE(sysctl); | |
4cd24eaf | 1488 | } else if (!netdev_mc_empty(dev)) { |
775919bc AW |
1489 | /* set up multicast hash table */ |
1490 | sysctl = bfin_read_EMAC_OPMODE(); | |
1491 | sysctl |= HM; | |
1492 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 1493 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
1494 | } else { |
1495 | /* clear promisc or multicast mode */ | |
1496 | sysctl = bfin_read_EMAC_OPMODE(); | |
1497 | sysctl &= ~(RAF | PAM); | |
1498 | bfin_write_EMAC_OPMODE(sysctl); | |
1499 | } | |
1500 | } | |
1501 | ||
fe92afed BS |
1502 | static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1503 | { | |
02460d08 SZ |
1504 | struct bfin_mac_local *lp = netdev_priv(netdev); |
1505 | ||
1506 | if (!netif_running(netdev)) | |
1507 | return -EINVAL; | |
1508 | ||
fe92afed BS |
1509 | switch (cmd) { |
1510 | case SIOCSHWTSTAMP: | |
7575c917 BH |
1511 | return bfin_mac_hwtstamp_set(netdev, ifr); |
1512 | case SIOCGHWTSTAMP: | |
1513 | return bfin_mac_hwtstamp_get(netdev, ifr); | |
fe92afed | 1514 | default: |
02460d08 SZ |
1515 | if (lp->phydev) |
1516 | return phy_mii_ioctl(lp->phydev, ifr, cmd); | |
1517 | else | |
1518 | return -EOPNOTSUPP; | |
fe92afed BS |
1519 | } |
1520 | } | |
1521 | ||
e190d6b1 BW |
1522 | /* |
1523 | * this puts the device in an inactive state | |
1524 | */ | |
7ef0a7ee | 1525 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
1526 | { |
1527 | /* Turn off the EMAC */ | |
1528 | bfin_write_EMAC_OPMODE(0x00000000); | |
1529 | /* Turn off the EMAC RX DMA */ | |
1530 | bfin_write_DMA1_CONFIG(0x0000); | |
1531 | bfin_write_DMA2_CONFIG(0x0000); | |
1532 | } | |
1533 | ||
1534 | /* | |
1535 | * Open and Initialize the interface | |
1536 | * | |
1537 | * Set up everything, reset the card, etc.. | |
1538 | */ | |
7ef0a7ee | 1539 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 1540 | { |
7ef0a7ee | 1541 | struct bfin_mac_local *lp = netdev_priv(dev); |
2bfa0f0c | 1542 | int ret; |
b39d66a8 | 1543 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1544 | |
1545 | /* | |
1546 | * Check that the address is valid. If its not, refuse | |
1547 | * to bring the device up. The user must specify an | |
1548 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
1549 | */ | |
1550 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
c6dd5098 | 1551 | netdev_warn(dev, "no valid ethernet hw addr\n"); |
e190d6b1 BW |
1552 | return -EINVAL; |
1553 | } | |
1554 | ||
1555 | /* initial rx and tx list */ | |
1ab0d2ec | 1556 | ret = desc_list_init(dev); |
2bfa0f0c MF |
1557 | if (ret) |
1558 | return ret; | |
e190d6b1 | 1559 | |
4ae5a3ad | 1560 | phy_start(lp->phydev); |
e190d6b1 | 1561 | setup_system_regs(dev); |
ee02fee8 | 1562 | setup_mac_addr(dev->dev_addr); |
2bfa0f0c | 1563 | |
7ef0a7ee | 1564 | bfin_mac_disable(); |
02460d08 | 1565 | ret = bfin_mac_enable(lp->phydev); |
2bfa0f0c MF |
1566 | if (ret) |
1567 | return ret; | |
e190d6b1 | 1568 | pr_debug("hardware init finished\n"); |
2bfa0f0c | 1569 | |
e190d6b1 BW |
1570 | netif_start_queue(dev); |
1571 | netif_carrier_on(dev); | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | /* | |
e190d6b1 BW |
1577 | * this makes the board clean up everything that it can |
1578 | * and not talk to the outside world. Caused by | |
1579 | * an 'ifconfig ethX down' | |
1580 | */ | |
7ef0a7ee | 1581 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 1582 | { |
7ef0a7ee | 1583 | struct bfin_mac_local *lp = netdev_priv(dev); |
b39d66a8 | 1584 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1585 | |
1586 | netif_stop_queue(dev); | |
1587 | netif_carrier_off(dev); | |
1588 | ||
4ae5a3ad | 1589 | phy_stop(lp->phydev); |
136492b2 | 1590 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 1591 | |
e190d6b1 | 1592 | /* clear everything */ |
7ef0a7ee | 1593 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
1594 | |
1595 | /* free the rx/tx buffers */ | |
1596 | desc_list_free(); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
b63dc8fe MF |
1601 | static const struct net_device_ops bfin_mac_netdev_ops = { |
1602 | .ndo_open = bfin_mac_open, | |
1603 | .ndo_stop = bfin_mac_close, | |
1604 | .ndo_start_xmit = bfin_mac_hard_start_xmit, | |
1605 | .ndo_set_mac_address = bfin_mac_set_mac_address, | |
1606 | .ndo_tx_timeout = bfin_mac_timeout, | |
afc4b13d | 1607 | .ndo_set_rx_mode = bfin_mac_set_multicast_list, |
fe92afed | 1608 | .ndo_do_ioctl = bfin_mac_ioctl, |
b63dc8fe MF |
1609 | .ndo_validate_addr = eth_validate_addr, |
1610 | .ndo_change_mtu = eth_change_mtu, | |
1611 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1612 | .ndo_poll_controller = bfin_mac_poll, | |
1613 | #endif | |
1614 | }; | |
1615 | ||
49f7315b | 1616 | static int bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 1617 | { |
7ef0a7ee BW |
1618 | struct net_device *ndev; |
1619 | struct bfin_mac_local *lp; | |
080c8255 | 1620 | struct platform_device *pd; |
02460d08 | 1621 | struct bfin_mii_bus_platform_data *mii_bus_data; |
080c8255 | 1622 | int rc; |
7ef0a7ee BW |
1623 | |
1624 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
41de8d4c | 1625 | if (!ndev) |
7ef0a7ee | 1626 | return -ENOMEM; |
7ef0a7ee BW |
1627 | |
1628 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1629 | platform_set_drvdata(pdev, ndev); | |
1630 | lp = netdev_priv(ndev); | |
4fcc3d34 | 1631 | lp->ndev = ndev; |
e190d6b1 BW |
1632 | |
1633 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
1634 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
1635 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
1636 | |
1637 | /* probe mac */ | |
1638 | /*todo: how to proble? which is revision_register */ | |
1639 | bfin_write_EMAC_ADDRLO(0x12345678); | |
1640 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
1641 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
1642 | rc = -ENODEV; | |
1643 | goto out_err_probe_mac; | |
e190d6b1 BW |
1644 | } |
1645 | ||
e190d6b1 | 1646 | |
7ef0a7ee BW |
1647 | /* |
1648 | * Is it valid? (Did bootloader initialize it?) | |
1649 | * Grab the MAC from the board somehow | |
1650 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1651 | */ | |
5055d2f2 DK |
1652 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
1653 | if (bfin_get_ether_addr(ndev->dev_addr) || | |
1654 | !is_valid_ether_addr(ndev->dev_addr)) { | |
1655 | /* Still not valid, get a random one */ | |
1656 | netdev_warn(ndev, "Setting Ethernet MAC to a random one\n"); | |
1657 | eth_hw_addr_random(ndev); | |
1658 | } | |
1659 | } | |
e190d6b1 | 1660 | |
7ef0a7ee | 1661 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1662 | |
a63b82c4 | 1663 | if (!dev_get_platdata(&pdev->dev)) { |
080c8255 GY |
1664 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); |
1665 | rc = -ENODEV; | |
1666 | goto out_err_probe_mac; | |
7ef0a7ee | 1667 | } |
a63b82c4 | 1668 | pd = dev_get_platdata(&pdev->dev); |
080c8255 | 1669 | lp->mii_bus = platform_get_drvdata(pd); |
0e995cd3 SZ |
1670 | if (!lp->mii_bus) { |
1671 | dev_err(&pdev->dev, "Cannot get mii_bus!\n"); | |
1672 | rc = -ENODEV; | |
02460d08 | 1673 | goto out_err_probe_mac; |
0e995cd3 | 1674 | } |
080c8255 | 1675 | lp->mii_bus->priv = ndev; |
a63b82c4 | 1676 | mii_bus_data = dev_get_platdata(&pd->dev); |
4ae5a3ad | 1677 | |
02460d08 | 1678 | rc = mii_probe(ndev, mii_bus_data->phy_mode); |
7ef0a7ee BW |
1679 | if (rc) { |
1680 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1681 | goto out_err_mii_probe; | |
1682 | } | |
4ae5a3ad | 1683 | |
c599bd6b MF |
1684 | lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask; |
1685 | lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask; | |
1686 | ||
e190d6b1 | 1687 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1688 | ether_setup(ndev); |
1689 | ||
149da651 | 1690 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
679dce39 | 1691 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1692 | |
4fcc3d34 SZ |
1693 | init_timer(&lp->tx_reclaim_timer); |
1694 | lp->tx_reclaim_timer.data = (unsigned long)lp; | |
1695 | lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout; | |
1696 | ||
e190d6b1 BW |
1697 | spin_lock_init(&lp->lock); |
1698 | ||
1699 | /* now, enable interrupts */ | |
1700 | /* register irq handler */ | |
7ef0a7ee | 1701 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
63aca0f7 | 1702 | 0, "EMAC_RX", ndev); |
7ef0a7ee BW |
1703 | if (rc) { |
1704 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1705 | rc = -EBUSY; | |
1706 | goto out_err_request_irq; | |
e190d6b1 BW |
1707 | } |
1708 | ||
7ef0a7ee BW |
1709 | rc = register_netdev(ndev); |
1710 | if (rc) { | |
1711 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1712 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1713 | } |
1714 | ||
fe92afed | 1715 | bfin_mac_hwtstamp_init(ndev); |
2c006994 WY |
1716 | rc = bfin_phc_init(ndev, &pdev->dev); |
1717 | if (rc) { | |
dd87b22f RC |
1718 | dev_err(&pdev->dev, "Cannot register PHC device!\n"); |
1719 | goto out_err_phc; | |
1720 | } | |
fe92afed | 1721 | |
7ef0a7ee | 1722 | /* now, print out the card info, in a short format.. */ |
c6dd5098 | 1723 | netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); |
e190d6b1 | 1724 | |
7ef0a7ee | 1725 | return 0; |
e190d6b1 | 1726 | |
dd87b22f | 1727 | out_err_phc: |
7ef0a7ee BW |
1728 | out_err_reg_ndev: |
1729 | free_irq(IRQ_MAC_RX, ndev); | |
1730 | out_err_request_irq: | |
1731 | out_err_mii_probe: | |
298cf9be | 1732 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 1733 | mdiobus_free(lp->mii_bus); |
7ef0a7ee | 1734 | out_err_probe_mac: |
7ef0a7ee | 1735 | free_netdev(ndev); |
e190d6b1 | 1736 | |
7ef0a7ee | 1737 | return rc; |
e190d6b1 BW |
1738 | } |
1739 | ||
49f7315b | 1740 | static int bfin_mac_remove(struct platform_device *pdev) |
e190d6b1 BW |
1741 | { |
1742 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1743 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 | 1744 | |
dd87b22f RC |
1745 | bfin_phc_release(lp); |
1746 | ||
080c8255 | 1747 | lp->mii_bus->priv = NULL; |
7ef0a7ee | 1748 | |
e190d6b1 BW |
1749 | unregister_netdev(ndev); |
1750 | ||
1751 | free_irq(IRQ_MAC_RX, ndev); | |
1752 | ||
1753 | free_netdev(ndev); | |
1754 | ||
e190d6b1 BW |
1755 | return 0; |
1756 | } | |
1757 | ||
496a34c2 BW |
1758 | #ifdef CONFIG_PM |
1759 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1760 | { |
496a34c2 | 1761 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1762 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1763 | |
53fd3f28 MH |
1764 | if (lp->wol) { |
1765 | bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); | |
1766 | bfin_write_EMAC_WKUP_CTL(MPKE); | |
1767 | enable_irq_wake(IRQ_MAC_WAKEDET); | |
1768 | } else { | |
1769 | if (netif_running(net_dev)) | |
1770 | bfin_mac_close(net_dev); | |
1771 | } | |
496a34c2 | 1772 | |
e190d6b1 BW |
1773 | return 0; |
1774 | } | |
1775 | ||
1776 | static int bfin_mac_resume(struct platform_device *pdev) | |
1777 | { | |
496a34c2 | 1778 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1779 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1780 | |
53fd3f28 MH |
1781 | if (lp->wol) { |
1782 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1783 | bfin_write_EMAC_WKUP_CTL(0); | |
1784 | disable_irq_wake(IRQ_MAC_WAKEDET); | |
1785 | } else { | |
1786 | if (netif_running(net_dev)) | |
1787 | bfin_mac_open(net_dev); | |
1788 | } | |
496a34c2 | 1789 | |
e190d6b1 BW |
1790 | return 0; |
1791 | } | |
496a34c2 BW |
1792 | #else |
1793 | #define bfin_mac_suspend NULL | |
1794 | #define bfin_mac_resume NULL | |
1795 | #endif /* CONFIG_PM */ | |
e190d6b1 | 1796 | |
49f7315b | 1797 | static int bfin_mii_bus_probe(struct platform_device *pdev) |
080c8255 GY |
1798 | { |
1799 | struct mii_bus *miibus; | |
02460d08 SZ |
1800 | struct bfin_mii_bus_platform_data *mii_bus_pd; |
1801 | const unsigned short *pin_req; | |
080c8255 GY |
1802 | int rc, i; |
1803 | ||
02460d08 SZ |
1804 | mii_bus_pd = dev_get_platdata(&pdev->dev); |
1805 | if (!mii_bus_pd) { | |
1806 | dev_err(&pdev->dev, "No peripherals in platform data!\n"); | |
1807 | return -EINVAL; | |
1808 | } | |
1809 | ||
080c8255 GY |
1810 | /* |
1811 | * We are setting up a network card, | |
1812 | * so set the GPIO pins to Ethernet mode | |
1813 | */ | |
02460d08 | 1814 | pin_req = mii_bus_pd->mac_peripherals; |
c6dd5098 | 1815 | rc = peripheral_request_list(pin_req, KBUILD_MODNAME); |
080c8255 GY |
1816 | if (rc) { |
1817 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
1818 | return rc; | |
1819 | } | |
1820 | ||
1821 | rc = -ENOMEM; | |
1822 | miibus = mdiobus_alloc(); | |
1823 | if (miibus == NULL) | |
1824 | goto out_err_alloc; | |
1825 | miibus->read = bfin_mdiobus_read; | |
1826 | miibus->write = bfin_mdiobus_write; | |
1827 | miibus->reset = bfin_mdiobus_reset; | |
1828 | ||
1829 | miibus->parent = &pdev->dev; | |
1830 | miibus->name = "bfin_mii_bus"; | |
02460d08 SZ |
1831 | miibus->phy_mask = mii_bus_pd->phy_mask; |
1832 | ||
75432fd2 FF |
1833 | snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x", |
1834 | pdev->name, pdev->id); | |
080c8255 | 1835 | miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
02460d08 SZ |
1836 | if (!miibus->irq) |
1837 | goto out_err_irq_alloc; | |
1838 | ||
1839 | for (i = rc; i < PHY_MAX_ADDR; ++i) | |
080c8255 GY |
1840 | miibus->irq[i] = PHY_POLL; |
1841 | ||
02460d08 SZ |
1842 | rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR); |
1843 | if (rc != mii_bus_pd->phydev_number) | |
1844 | dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n", | |
1845 | mii_bus_pd->phydev_number); | |
1846 | for (i = 0; i < rc; ++i) { | |
1847 | unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr; | |
1848 | if (phyaddr < PHY_MAX_ADDR) | |
1849 | miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq; | |
1850 | else | |
1851 | dev_err(&pdev->dev, | |
1852 | "Invalid PHY address %i for phydev %i\n", | |
1853 | phyaddr, i); | |
1854 | } | |
1855 | ||
080c8255 GY |
1856 | rc = mdiobus_register(miibus); |
1857 | if (rc) { | |
1858 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1859 | goto out_err_mdiobus_register; | |
1860 | } | |
1861 | ||
1862 | platform_set_drvdata(pdev, miibus); | |
1863 | return 0; | |
1864 | ||
1865 | out_err_mdiobus_register: | |
7f267de4 | 1866 | kfree(miibus->irq); |
02460d08 | 1867 | out_err_irq_alloc: |
080c8255 GY |
1868 | mdiobus_free(miibus); |
1869 | out_err_alloc: | |
1870 | peripheral_free_list(pin_req); | |
1871 | ||
1872 | return rc; | |
1873 | } | |
1874 | ||
49f7315b | 1875 | static int bfin_mii_bus_remove(struct platform_device *pdev) |
080c8255 GY |
1876 | { |
1877 | struct mii_bus *miibus = platform_get_drvdata(pdev); | |
02460d08 SZ |
1878 | struct bfin_mii_bus_platform_data *mii_bus_pd = |
1879 | dev_get_platdata(&pdev->dev); | |
1880 | ||
080c8255 | 1881 | mdiobus_unregister(miibus); |
7f267de4 | 1882 | kfree(miibus->irq); |
080c8255 | 1883 | mdiobus_free(miibus); |
02460d08 SZ |
1884 | peripheral_free_list(mii_bus_pd->mac_peripherals); |
1885 | ||
080c8255 GY |
1886 | return 0; |
1887 | } | |
1888 | ||
1889 | static struct platform_driver bfin_mii_bus_driver = { | |
1890 | .probe = bfin_mii_bus_probe, | |
49f7315b | 1891 | .remove = bfin_mii_bus_remove, |
080c8255 GY |
1892 | .driver = { |
1893 | .name = "bfin_mii_bus", | |
1894 | .owner = THIS_MODULE, | |
1895 | }, | |
1896 | }; | |
1897 | ||
e190d6b1 BW |
1898 | static struct platform_driver bfin_mac_driver = { |
1899 | .probe = bfin_mac_probe, | |
49f7315b | 1900 | .remove = bfin_mac_remove, |
e190d6b1 BW |
1901 | .resume = bfin_mac_resume, |
1902 | .suspend = bfin_mac_suspend, | |
1903 | .driver = { | |
c6dd5098 | 1904 | .name = KBUILD_MODNAME, |
72abb461 KS |
1905 | .owner = THIS_MODULE, |
1906 | }, | |
e190d6b1 BW |
1907 | }; |
1908 | ||
1909 | static int __init bfin_mac_init(void) | |
1910 | { | |
080c8255 GY |
1911 | int ret; |
1912 | ret = platform_driver_register(&bfin_mii_bus_driver); | |
1913 | if (!ret) | |
1914 | return platform_driver_register(&bfin_mac_driver); | |
1915 | return -ENODEV; | |
e190d6b1 BW |
1916 | } |
1917 | ||
1918 | module_init(bfin_mac_init); | |
1919 | ||
1920 | static void __exit bfin_mac_cleanup(void) | |
1921 | { | |
1922 | platform_driver_unregister(&bfin_mac_driver); | |
080c8255 | 1923 | platform_driver_unregister(&bfin_mii_bus_driver); |
e190d6b1 BW |
1924 | } |
1925 | ||
1926 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1927 |