Commit | Line | Data |
---|---|---|
c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
9 | * Copyright (c) 2014 Advanced Micro Devices, Inc. | |
10 | * | |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
59 | * Copyright (c) 2014 Advanced Micro Devices, Inc. | |
60 | * All rights reserved. | |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
9227dc5e | 117 | #include <linux/platform_device.h> |
c5aa9e3b LT |
118 | #include <linux/spinlock.h> |
119 | #include <linux/tcp.h> | |
120 | #include <linux/if_vlan.h> | |
c5aa9e3b LT |
121 | #include <net/busy_poll.h> |
122 | #include <linux/clk.h> | |
123 | #include <linux/if_ether.h> | |
23e4eef7 | 124 | #include <linux/net_tstamp.h> |
88131a81 | 125 | #include <linux/phy.h> |
c5aa9e3b LT |
126 | |
127 | #include "xgbe.h" | |
128 | #include "xgbe-common.h" | |
129 | ||
9227dc5e LT |
130 | static int xgbe_one_poll(struct napi_struct *, int); |
131 | static int xgbe_all_poll(struct napi_struct *, int); | |
c5aa9e3b | 132 | |
4780b7ca LT |
133 | static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) |
134 | { | |
135 | struct xgbe_channel *channel_mem, *channel; | |
136 | struct xgbe_ring *tx_ring, *rx_ring; | |
137 | unsigned int count, i; | |
9227dc5e | 138 | int ret = -ENOMEM; |
4780b7ca LT |
139 | |
140 | count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); | |
141 | ||
142 | channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); | |
143 | if (!channel_mem) | |
144 | goto err_channel; | |
145 | ||
146 | tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), | |
147 | GFP_KERNEL); | |
148 | if (!tx_ring) | |
149 | goto err_tx_ring; | |
150 | ||
151 | rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), | |
152 | GFP_KERNEL); | |
153 | if (!rx_ring) | |
154 | goto err_rx_ring; | |
155 | ||
156 | for (i = 0, channel = channel_mem; i < count; i++, channel++) { | |
157 | snprintf(channel->name, sizeof(channel->name), "channel-%d", i); | |
158 | channel->pdata = pdata; | |
159 | channel->queue_index = i; | |
160 | channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + | |
161 | (DMA_CH_INC * i); | |
162 | ||
9227dc5e LT |
163 | if (pdata->per_channel_irq) { |
164 | /* Get the DMA interrupt (offset 1) */ | |
165 | ret = platform_get_irq(pdata->pdev, i + 1); | |
166 | if (ret < 0) { | |
167 | netdev_err(pdata->netdev, | |
168 | "platform_get_irq %u failed\n", | |
169 | i + 1); | |
170 | goto err_irq; | |
171 | } | |
172 | ||
173 | channel->dma_irq = ret; | |
174 | } | |
175 | ||
4780b7ca LT |
176 | if (i < pdata->tx_ring_count) { |
177 | spin_lock_init(&tx_ring->lock); | |
178 | channel->tx_ring = tx_ring++; | |
179 | } | |
180 | ||
181 | if (i < pdata->rx_ring_count) { | |
182 | spin_lock_init(&rx_ring->lock); | |
183 | channel->rx_ring = rx_ring++; | |
184 | } | |
185 | ||
34bf65df LT |
186 | netif_dbg(pdata, drv, pdata->netdev, |
187 | "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", | |
188 | channel->name, channel->dma_regs, channel->dma_irq, | |
189 | channel->tx_ring, channel->rx_ring); | |
4780b7ca LT |
190 | } |
191 | ||
192 | pdata->channel = channel_mem; | |
193 | pdata->channel_count = count; | |
194 | ||
195 | return 0; | |
196 | ||
9227dc5e LT |
197 | err_irq: |
198 | kfree(rx_ring); | |
199 | ||
4780b7ca LT |
200 | err_rx_ring: |
201 | kfree(tx_ring); | |
202 | ||
203 | err_tx_ring: | |
204 | kfree(channel_mem); | |
205 | ||
206 | err_channel: | |
9227dc5e | 207 | return ret; |
4780b7ca LT |
208 | } |
209 | ||
210 | static void xgbe_free_channels(struct xgbe_prv_data *pdata) | |
211 | { | |
212 | if (!pdata->channel) | |
213 | return; | |
214 | ||
215 | kfree(pdata->channel->rx_ring); | |
216 | kfree(pdata->channel->tx_ring); | |
217 | kfree(pdata->channel); | |
218 | ||
219 | pdata->channel = NULL; | |
220 | pdata->channel_count = 0; | |
221 | } | |
222 | ||
c5aa9e3b LT |
223 | static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) |
224 | { | |
225 | return (ring->rdesc_count - (ring->cur - ring->dirty)); | |
226 | } | |
227 | ||
270894e7 LT |
228 | static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) |
229 | { | |
230 | return (ring->cur - ring->dirty); | |
231 | } | |
232 | ||
16958a2b LT |
233 | static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, |
234 | struct xgbe_ring *ring, unsigned int count) | |
235 | { | |
236 | struct xgbe_prv_data *pdata = channel->pdata; | |
237 | ||
238 | if (count > xgbe_tx_avail_desc(ring)) { | |
34bf65df LT |
239 | netif_info(pdata, drv, pdata->netdev, |
240 | "Tx queue stopped, not enough descriptors available\n"); | |
16958a2b LT |
241 | netif_stop_subqueue(pdata->netdev, channel->queue_index); |
242 | ring->tx.queue_stopped = 1; | |
243 | ||
244 | /* If we haven't notified the hardware because of xmit_more | |
245 | * support, tell it now | |
246 | */ | |
247 | if (ring->tx.xmit_more) | |
248 | pdata->hw_if.tx_start_xmit(channel, ring); | |
249 | ||
250 | return NETDEV_TX_BUSY; | |
251 | } | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
c5aa9e3b LT |
256 | static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) |
257 | { | |
258 | unsigned int rx_buf_size; | |
259 | ||
260 | if (mtu > XGMAC_JUMBO_PACKET_MTU) { | |
261 | netdev_alert(netdev, "MTU exceeds maximum supported value\n"); | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
265 | rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
08dcc47c LT |
266 | rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); |
267 | ||
d0a8ba6c LT |
268 | rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & |
269 | ~(XGBE_RX_BUF_ALIGN - 1); | |
c5aa9e3b LT |
270 | |
271 | return rx_buf_size; | |
272 | } | |
273 | ||
274 | static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
275 | { | |
276 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
277 | struct xgbe_channel *channel; | |
9867e8fb | 278 | enum xgbe_int int_id; |
c5aa9e3b LT |
279 | unsigned int i; |
280 | ||
281 | channel = pdata->channel; | |
282 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
9867e8fb LT |
283 | if (channel->tx_ring && channel->rx_ring) |
284 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
285 | else if (channel->tx_ring) | |
286 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
287 | else if (channel->rx_ring) | |
288 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
289 | else | |
290 | continue; | |
291 | ||
292 | hw_if->enable_int(channel, int_id); | |
c5aa9e3b LT |
293 | } |
294 | } | |
295 | ||
296 | static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
297 | { | |
298 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
299 | struct xgbe_channel *channel; | |
9867e8fb | 300 | enum xgbe_int int_id; |
c5aa9e3b LT |
301 | unsigned int i; |
302 | ||
303 | channel = pdata->channel; | |
304 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
9867e8fb LT |
305 | if (channel->tx_ring && channel->rx_ring) |
306 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
307 | else if (channel->tx_ring) | |
308 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
309 | else if (channel->rx_ring) | |
310 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
311 | else | |
312 | continue; | |
313 | ||
314 | hw_if->disable_int(channel, int_id); | |
c5aa9e3b LT |
315 | } |
316 | } | |
317 | ||
318 | static irqreturn_t xgbe_isr(int irq, void *data) | |
319 | { | |
320 | struct xgbe_prv_data *pdata = data; | |
321 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
322 | struct xgbe_channel *channel; | |
323 | unsigned int dma_isr, dma_ch_isr; | |
23e4eef7 | 324 | unsigned int mac_isr, mac_tssr; |
c5aa9e3b LT |
325 | unsigned int i; |
326 | ||
327 | /* The DMA interrupt status register also reports MAC and MTL | |
328 | * interrupts. So for polling mode, we just need to check for | |
329 | * this register to be non-zero | |
330 | */ | |
331 | dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); | |
332 | if (!dma_isr) | |
333 | goto isr_done; | |
334 | ||
34bf65df | 335 | netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); |
c5aa9e3b LT |
336 | |
337 | for (i = 0; i < pdata->channel_count; i++) { | |
338 | if (!(dma_isr & (1 << i))) | |
339 | continue; | |
340 | ||
341 | channel = pdata->channel + i; | |
342 | ||
343 | dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); | |
34bf65df LT |
344 | netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", |
345 | i, dma_ch_isr); | |
c5aa9e3b | 346 | |
fd972b73 LT |
347 | /* The TI or RI interrupt bits may still be set even if using |
348 | * per channel DMA interrupts. Check to be sure those are not | |
349 | * enabled before using the private data napi structure. | |
9227dc5e | 350 | */ |
fd972b73 LT |
351 | if (!pdata->per_channel_irq && |
352 | (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || | |
353 | XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { | |
c5aa9e3b LT |
354 | if (napi_schedule_prep(&pdata->napi)) { |
355 | /* Disable Tx and Rx interrupts */ | |
356 | xgbe_disable_rx_tx_ints(pdata); | |
357 | ||
358 | /* Turn on polling */ | |
359 | __napi_schedule(&pdata->napi); | |
360 | } | |
361 | } | |
362 | ||
72c9ac4e LT |
363 | if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) |
364 | pdata->ext_stats.rx_buffer_unavailable++; | |
365 | ||
c5aa9e3b LT |
366 | /* Restart the device on a Fatal Bus Error */ |
367 | if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) | |
368 | schedule_work(&pdata->restart_work); | |
369 | ||
370 | /* Clear all interrupt signals */ | |
371 | XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); | |
372 | } | |
373 | ||
374 | if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { | |
375 | mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); | |
376 | ||
377 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) | |
378 | hw_if->tx_mmc_int(pdata); | |
379 | ||
380 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) | |
381 | hw_if->rx_mmc_int(pdata); | |
23e4eef7 LT |
382 | |
383 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { | |
384 | mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); | |
385 | ||
386 | if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { | |
387 | /* Read Tx Timestamp to clear interrupt */ | |
388 | pdata->tx_tstamp = | |
389 | hw_if->get_tx_tstamp(pdata); | |
390 | schedule_work(&pdata->tx_tstamp_work); | |
391 | } | |
392 | } | |
c5aa9e3b LT |
393 | } |
394 | ||
c5aa9e3b LT |
395 | isr_done: |
396 | return IRQ_HANDLED; | |
397 | } | |
398 | ||
9227dc5e LT |
399 | static irqreturn_t xgbe_dma_isr(int irq, void *data) |
400 | { | |
401 | struct xgbe_channel *channel = data; | |
402 | ||
403 | /* Per channel DMA interrupts are enabled, so we use the per | |
404 | * channel napi structure and not the private data napi structure | |
405 | */ | |
406 | if (napi_schedule_prep(&channel->napi)) { | |
407 | /* Disable Tx and Rx interrupts */ | |
f9c5c62d | 408 | disable_irq_nosync(channel->dma_irq); |
9227dc5e LT |
409 | |
410 | /* Turn on polling */ | |
411 | __napi_schedule(&channel->napi); | |
412 | } | |
413 | ||
414 | return IRQ_HANDLED; | |
415 | } | |
416 | ||
c635eaac | 417 | static void xgbe_tx_timer(unsigned long data) |
c5aa9e3b | 418 | { |
c635eaac | 419 | struct xgbe_channel *channel = (struct xgbe_channel *)data; |
c5aa9e3b | 420 | struct xgbe_prv_data *pdata = channel->pdata; |
9227dc5e | 421 | struct napi_struct *napi; |
c5aa9e3b LT |
422 | |
423 | DBGPR("-->xgbe_tx_timer\n"); | |
424 | ||
9227dc5e LT |
425 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
426 | ||
9227dc5e | 427 | if (napi_schedule_prep(napi)) { |
c5aa9e3b | 428 | /* Disable Tx and Rx interrupts */ |
9227dc5e | 429 | if (pdata->per_channel_irq) |
078b29d7 | 430 | disable_irq_nosync(channel->dma_irq); |
9227dc5e LT |
431 | else |
432 | xgbe_disable_rx_tx_ints(pdata); | |
c5aa9e3b LT |
433 | |
434 | /* Turn on polling */ | |
9227dc5e | 435 | __napi_schedule(napi); |
c5aa9e3b LT |
436 | } |
437 | ||
438 | channel->tx_timer_active = 0; | |
439 | ||
c5aa9e3b | 440 | DBGPR("<--xgbe_tx_timer\n"); |
c5aa9e3b LT |
441 | } |
442 | ||
7c12aa08 LT |
443 | static void xgbe_service(struct work_struct *work) |
444 | { | |
445 | struct xgbe_prv_data *pdata = container_of(work, | |
446 | struct xgbe_prv_data, | |
447 | service_work); | |
448 | ||
449 | pdata->phy_if.phy_status(pdata); | |
450 | } | |
451 | ||
452 | static void xgbe_service_timer(unsigned long data) | |
453 | { | |
454 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
455 | ||
456 | schedule_work(&pdata->service_work); | |
457 | ||
458 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
459 | } | |
460 | ||
461 | static void xgbe_init_timers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
462 | { |
463 | struct xgbe_channel *channel; | |
464 | unsigned int i; | |
465 | ||
7c12aa08 LT |
466 | setup_timer(&pdata->service_timer, xgbe_service_timer, |
467 | (unsigned long)pdata); | |
c5aa9e3b LT |
468 | |
469 | channel = pdata->channel; | |
470 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
471 | if (!channel->tx_ring) | |
472 | break; | |
473 | ||
c635eaac LT |
474 | setup_timer(&channel->tx_timer, xgbe_tx_timer, |
475 | (unsigned long)channel); | |
c5aa9e3b | 476 | } |
7c12aa08 | 477 | } |
c5aa9e3b | 478 | |
7c12aa08 LT |
479 | static void xgbe_start_timers(struct xgbe_prv_data *pdata) |
480 | { | |
481 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
c5aa9e3b LT |
482 | } |
483 | ||
7c12aa08 | 484 | static void xgbe_stop_timers(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
485 | { |
486 | struct xgbe_channel *channel; | |
487 | unsigned int i; | |
488 | ||
7c12aa08 | 489 | del_timer_sync(&pdata->service_timer); |
c5aa9e3b LT |
490 | |
491 | channel = pdata->channel; | |
492 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
493 | if (!channel->tx_ring) | |
494 | break; | |
495 | ||
c635eaac | 496 | del_timer_sync(&channel->tx_timer); |
c5aa9e3b | 497 | } |
c5aa9e3b LT |
498 | } |
499 | ||
500 | void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) | |
501 | { | |
502 | unsigned int mac_hfr0, mac_hfr1, mac_hfr2; | |
503 | struct xgbe_hw_features *hw_feat = &pdata->hw_feat; | |
504 | ||
505 | DBGPR("-->xgbe_get_all_hw_features\n"); | |
506 | ||
507 | mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); | |
508 | mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); | |
509 | mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); | |
510 | ||
511 | memset(hw_feat, 0, sizeof(*hw_feat)); | |
512 | ||
a9a4a2d9 LT |
513 | hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); |
514 | ||
c5aa9e3b LT |
515 | /* Hardware feature register 0 */ |
516 | hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); | |
517 | hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); | |
518 | hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); | |
519 | hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); | |
520 | hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); | |
521 | hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); | |
522 | hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); | |
523 | hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); | |
524 | hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); | |
525 | hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); | |
526 | hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); | |
527 | hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, | |
528 | ADDMACADRSEL); | |
529 | hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); | |
530 | hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); | |
531 | ||
532 | /* Hardware feature register 1 */ | |
533 | hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
534 | RXFIFOSIZE); | |
535 | hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
536 | TXFIFOSIZE); | |
73c25916 | 537 | hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); |
386d325d | 538 | hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); |
c5aa9e3b LT |
539 | hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); |
540 | hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); | |
541 | hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); | |
542 | hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); | |
cf180b8a | 543 | hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); |
fca2d994 | 544 | hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); |
c5aa9e3b LT |
545 | hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, |
546 | HASHTBLSZ); | |
547 | hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
548 | L3L4FNUM); | |
549 | ||
550 | /* Hardware feature register 2 */ | |
551 | hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); | |
552 | hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); | |
553 | hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); | |
554 | hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); | |
555 | hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); | |
556 | hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); | |
557 | ||
b85e4d89 LT |
558 | /* Translate the Hash Table size into actual number */ |
559 | switch (hw_feat->hash_table_size) { | |
560 | case 0: | |
561 | break; | |
562 | case 1: | |
563 | hw_feat->hash_table_size = 64; | |
564 | break; | |
565 | case 2: | |
566 | hw_feat->hash_table_size = 128; | |
567 | break; | |
568 | case 3: | |
569 | hw_feat->hash_table_size = 256; | |
570 | break; | |
571 | } | |
572 | ||
386d325d LT |
573 | /* Translate the address width setting into actual number */ |
574 | switch (hw_feat->dma_width) { | |
575 | case 0: | |
576 | hw_feat->dma_width = 32; | |
577 | break; | |
578 | case 1: | |
579 | hw_feat->dma_width = 40; | |
580 | break; | |
581 | case 2: | |
582 | hw_feat->dma_width = 48; | |
583 | break; | |
584 | default: | |
585 | hw_feat->dma_width = 32; | |
586 | } | |
587 | ||
211fcf6d | 588 | /* The Queue, Channel and TC counts are zero based so increment them |
c5aa9e3b LT |
589 | * to get the actual number |
590 | */ | |
591 | hw_feat->rx_q_cnt++; | |
592 | hw_feat->tx_q_cnt++; | |
593 | hw_feat->rx_ch_cnt++; | |
594 | hw_feat->tx_ch_cnt++; | |
211fcf6d | 595 | hw_feat->tc_cnt++; |
c5aa9e3b LT |
596 | |
597 | DBGPR("<--xgbe_get_all_hw_features\n"); | |
598 | } | |
599 | ||
600 | static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) | |
601 | { | |
9227dc5e LT |
602 | struct xgbe_channel *channel; |
603 | unsigned int i; | |
604 | ||
605 | if (pdata->per_channel_irq) { | |
606 | channel = pdata->channel; | |
607 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
608 | if (add) | |
609 | netif_napi_add(pdata->netdev, &channel->napi, | |
610 | xgbe_one_poll, NAPI_POLL_WEIGHT); | |
611 | ||
612 | napi_enable(&channel->napi); | |
613 | } | |
614 | } else { | |
615 | if (add) | |
616 | netif_napi_add(pdata->netdev, &pdata->napi, | |
617 | xgbe_all_poll, NAPI_POLL_WEIGHT); | |
618 | ||
619 | napi_enable(&pdata->napi); | |
620 | } | |
c5aa9e3b LT |
621 | } |
622 | ||
ff42606e | 623 | static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) |
c5aa9e3b | 624 | { |
9227dc5e LT |
625 | struct xgbe_channel *channel; |
626 | unsigned int i; | |
627 | ||
628 | if (pdata->per_channel_irq) { | |
629 | channel = pdata->channel; | |
630 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
631 | napi_disable(&channel->napi); | |
ff42606e | 632 | |
9227dc5e LT |
633 | if (del) |
634 | netif_napi_del(&channel->napi); | |
635 | } | |
636 | } else { | |
637 | napi_disable(&pdata->napi); | |
638 | ||
639 | if (del) | |
640 | netif_napi_del(&pdata->napi); | |
641 | } | |
c5aa9e3b LT |
642 | } |
643 | ||
c30e76a7 LT |
644 | static int xgbe_request_irqs(struct xgbe_prv_data *pdata) |
645 | { | |
646 | struct xgbe_channel *channel; | |
647 | struct net_device *netdev = pdata->netdev; | |
648 | unsigned int i; | |
649 | int ret; | |
650 | ||
651 | ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, | |
652 | netdev->name, pdata); | |
653 | if (ret) { | |
654 | netdev_alert(netdev, "error requesting irq %d\n", | |
655 | pdata->dev_irq); | |
656 | return ret; | |
657 | } | |
658 | ||
659 | if (!pdata->per_channel_irq) | |
660 | return 0; | |
661 | ||
662 | channel = pdata->channel; | |
663 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
664 | snprintf(channel->dma_irq_name, | |
665 | sizeof(channel->dma_irq_name) - 1, | |
666 | "%s-TxRx-%u", netdev_name(netdev), | |
667 | channel->queue_index); | |
668 | ||
669 | ret = devm_request_irq(pdata->dev, channel->dma_irq, | |
670 | xgbe_dma_isr, 0, | |
671 | channel->dma_irq_name, channel); | |
672 | if (ret) { | |
673 | netdev_alert(netdev, "error requesting irq %d\n", | |
674 | channel->dma_irq); | |
675 | goto err_irq; | |
676 | } | |
677 | } | |
678 | ||
679 | return 0; | |
680 | ||
681 | err_irq: | |
682 | /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ | |
683 | for (i--, channel--; i < pdata->channel_count; i--, channel--) | |
684 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
685 | ||
686 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | static void xgbe_free_irqs(struct xgbe_prv_data *pdata) | |
692 | { | |
693 | struct xgbe_channel *channel; | |
694 | unsigned int i; | |
695 | ||
696 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); | |
697 | ||
698 | if (!pdata->per_channel_irq) | |
699 | return; | |
700 | ||
701 | channel = pdata->channel; | |
702 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
703 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
704 | } | |
705 | ||
c5aa9e3b LT |
706 | void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) |
707 | { | |
708 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
709 | ||
710 | DBGPR("-->xgbe_init_tx_coalesce\n"); | |
711 | ||
712 | pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; | |
713 | pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; | |
714 | ||
715 | hw_if->config_tx_coalesce(pdata); | |
716 | ||
717 | DBGPR("<--xgbe_init_tx_coalesce\n"); | |
718 | } | |
719 | ||
720 | void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) | |
721 | { | |
722 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
723 | ||
724 | DBGPR("-->xgbe_init_rx_coalesce\n"); | |
725 | ||
726 | pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); | |
4a57ebcc | 727 | pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; |
c5aa9e3b LT |
728 | pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; |
729 | ||
730 | hw_if->config_rx_coalesce(pdata); | |
731 | ||
732 | DBGPR("<--xgbe_init_rx_coalesce\n"); | |
733 | } | |
734 | ||
08dcc47c | 735 | static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
736 | { |
737 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
738 | struct xgbe_channel *channel; | |
739 | struct xgbe_ring *ring; | |
740 | struct xgbe_ring_data *rdata; | |
741 | unsigned int i, j; | |
742 | ||
08dcc47c | 743 | DBGPR("-->xgbe_free_tx_data\n"); |
c5aa9e3b LT |
744 | |
745 | channel = pdata->channel; | |
746 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
747 | ring = channel->tx_ring; | |
748 | if (!ring) | |
749 | break; | |
750 | ||
751 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 752 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 753 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
754 | } |
755 | } | |
756 | ||
08dcc47c | 757 | DBGPR("<--xgbe_free_tx_data\n"); |
c5aa9e3b LT |
758 | } |
759 | ||
08dcc47c | 760 | static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
761 | { |
762 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
763 | struct xgbe_channel *channel; | |
764 | struct xgbe_ring *ring; | |
765 | struct xgbe_ring_data *rdata; | |
766 | unsigned int i, j; | |
767 | ||
08dcc47c | 768 | DBGPR("-->xgbe_free_rx_data\n"); |
c5aa9e3b LT |
769 | |
770 | channel = pdata->channel; | |
771 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
772 | ring = channel->rx_ring; | |
773 | if (!ring) | |
774 | break; | |
775 | ||
776 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 777 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 778 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
779 | } |
780 | } | |
781 | ||
08dcc47c | 782 | DBGPR("<--xgbe_free_rx_data\n"); |
c5aa9e3b LT |
783 | } |
784 | ||
88131a81 LT |
785 | static int xgbe_phy_init(struct xgbe_prv_data *pdata) |
786 | { | |
88131a81 LT |
787 | pdata->phy_link = -1; |
788 | pdata->phy_speed = SPEED_UNKNOWN; | |
88131a81 | 789 | |
7c12aa08 | 790 | return pdata->phy_if.phy_reset(pdata); |
88131a81 LT |
791 | } |
792 | ||
c5aa9e3b LT |
793 | int xgbe_powerdown(struct net_device *netdev, unsigned int caller) |
794 | { | |
795 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
796 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
797 | unsigned long flags; | |
798 | ||
799 | DBGPR("-->xgbe_powerdown\n"); | |
800 | ||
801 | if (!netif_running(netdev) || | |
802 | (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { | |
803 | netdev_alert(netdev, "Device is already powered down\n"); | |
804 | DBGPR("<--xgbe_powerdown\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | ||
c5aa9e3b LT |
808 | spin_lock_irqsave(&pdata->lock, flags); |
809 | ||
810 | if (caller == XGMAC_DRIVER_CONTEXT) | |
811 | netif_device_detach(netdev); | |
812 | ||
813 | netif_tx_stop_all_queues(netdev); | |
c5aa9e3b | 814 | |
7c12aa08 LT |
815 | xgbe_stop_timers(pdata); |
816 | flush_workqueue(pdata->dev_workqueue); | |
817 | ||
c5aa9e3b LT |
818 | hw_if->powerdown_tx(pdata); |
819 | hw_if->powerdown_rx(pdata); | |
820 | ||
c30e76a7 LT |
821 | xgbe_napi_disable(pdata, 0); |
822 | ||
c5aa9e3b LT |
823 | pdata->power_down = 1; |
824 | ||
825 | spin_unlock_irqrestore(&pdata->lock, flags); | |
826 | ||
827 | DBGPR("<--xgbe_powerdown\n"); | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | int xgbe_powerup(struct net_device *netdev, unsigned int caller) | |
833 | { | |
834 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
835 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
836 | unsigned long flags; | |
837 | ||
838 | DBGPR("-->xgbe_powerup\n"); | |
839 | ||
840 | if (!netif_running(netdev) || | |
841 | (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { | |
842 | netdev_alert(netdev, "Device is already powered up\n"); | |
843 | DBGPR("<--xgbe_powerup\n"); | |
844 | return -EINVAL; | |
845 | } | |
846 | ||
847 | spin_lock_irqsave(&pdata->lock, flags); | |
848 | ||
849 | pdata->power_down = 0; | |
850 | ||
c30e76a7 LT |
851 | xgbe_napi_enable(pdata, 0); |
852 | ||
c5aa9e3b LT |
853 | hw_if->powerup_tx(pdata); |
854 | hw_if->powerup_rx(pdata); | |
855 | ||
856 | if (caller == XGMAC_DRIVER_CONTEXT) | |
857 | netif_device_attach(netdev); | |
858 | ||
c5aa9e3b LT |
859 | netif_tx_start_all_queues(netdev); |
860 | ||
7c12aa08 LT |
861 | xgbe_start_timers(pdata); |
862 | ||
c5aa9e3b LT |
863 | spin_unlock_irqrestore(&pdata->lock, flags); |
864 | ||
865 | DBGPR("<--xgbe_powerup\n"); | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | static int xgbe_start(struct xgbe_prv_data *pdata) | |
871 | { | |
872 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 873 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
c5aa9e3b | 874 | struct net_device *netdev = pdata->netdev; |
c30e76a7 | 875 | int ret; |
c5aa9e3b LT |
876 | |
877 | DBGPR("-->xgbe_start\n"); | |
878 | ||
c5aa9e3b LT |
879 | hw_if->init(pdata); |
880 | ||
7c12aa08 LT |
881 | ret = phy_if->phy_start(pdata); |
882 | if (ret) | |
883 | goto err_phy; | |
c5aa9e3b | 884 | |
c30e76a7 LT |
885 | xgbe_napi_enable(pdata, 1); |
886 | ||
887 | ret = xgbe_request_irqs(pdata); | |
888 | if (ret) | |
889 | goto err_napi; | |
890 | ||
c5aa9e3b LT |
891 | hw_if->enable_tx(pdata); |
892 | hw_if->enable_rx(pdata); | |
893 | ||
c5aa9e3b LT |
894 | netif_tx_start_all_queues(netdev); |
895 | ||
7c12aa08 LT |
896 | xgbe_start_timers(pdata); |
897 | schedule_work(&pdata->service_work); | |
898 | ||
c5aa9e3b LT |
899 | DBGPR("<--xgbe_start\n"); |
900 | ||
901 | return 0; | |
c30e76a7 LT |
902 | |
903 | err_napi: | |
904 | xgbe_napi_disable(pdata, 1); | |
905 | ||
7c12aa08 | 906 | phy_if->phy_stop(pdata); |
c30e76a7 | 907 | |
7c12aa08 | 908 | err_phy: |
c30e76a7 LT |
909 | hw_if->exit(pdata); |
910 | ||
911 | return ret; | |
c5aa9e3b LT |
912 | } |
913 | ||
914 | static void xgbe_stop(struct xgbe_prv_data *pdata) | |
915 | { | |
916 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 917 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
5fb4b86a | 918 | struct xgbe_channel *channel; |
c5aa9e3b | 919 | struct net_device *netdev = pdata->netdev; |
5fb4b86a LT |
920 | struct netdev_queue *txq; |
921 | unsigned int i; | |
c5aa9e3b LT |
922 | |
923 | DBGPR("-->xgbe_stop\n"); | |
924 | ||
c5aa9e3b | 925 | netif_tx_stop_all_queues(netdev); |
c5aa9e3b | 926 | |
7c12aa08 LT |
927 | xgbe_stop_timers(pdata); |
928 | flush_workqueue(pdata->dev_workqueue); | |
c5aa9e3b LT |
929 | |
930 | hw_if->disable_tx(pdata); | |
931 | hw_if->disable_rx(pdata); | |
932 | ||
c30e76a7 LT |
933 | xgbe_free_irqs(pdata); |
934 | ||
935 | xgbe_napi_disable(pdata, 1); | |
936 | ||
7c12aa08 | 937 | phy_if->phy_stop(pdata); |
c30e76a7 LT |
938 | |
939 | hw_if->exit(pdata); | |
940 | ||
5fb4b86a LT |
941 | channel = pdata->channel; |
942 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
943 | if (!channel->tx_ring) | |
944 | continue; | |
945 | ||
946 | txq = netdev_get_tx_queue(netdev, channel->queue_index); | |
947 | netdev_tx_reset_queue(txq); | |
948 | } | |
949 | ||
c5aa9e3b LT |
950 | DBGPR("<--xgbe_stop\n"); |
951 | } | |
952 | ||
916102c6 | 953 | static void xgbe_restart_dev(struct xgbe_prv_data *pdata) |
c5aa9e3b | 954 | { |
c5aa9e3b LT |
955 | DBGPR("-->xgbe_restart_dev\n"); |
956 | ||
957 | /* If not running, "restart" will happen on open */ | |
958 | if (!netif_running(pdata->netdev)) | |
959 | return; | |
960 | ||
961 | xgbe_stop(pdata); | |
c5aa9e3b | 962 | |
08dcc47c LT |
963 | xgbe_free_tx_data(pdata); |
964 | xgbe_free_rx_data(pdata); | |
c5aa9e3b | 965 | |
c5aa9e3b LT |
966 | xgbe_start(pdata); |
967 | ||
968 | DBGPR("<--xgbe_restart_dev\n"); | |
969 | } | |
970 | ||
971 | static void xgbe_restart(struct work_struct *work) | |
972 | { | |
973 | struct xgbe_prv_data *pdata = container_of(work, | |
974 | struct xgbe_prv_data, | |
975 | restart_work); | |
976 | ||
977 | rtnl_lock(); | |
978 | ||
916102c6 | 979 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
980 | |
981 | rtnl_unlock(); | |
982 | } | |
983 | ||
23e4eef7 LT |
984 | static void xgbe_tx_tstamp(struct work_struct *work) |
985 | { | |
986 | struct xgbe_prv_data *pdata = container_of(work, | |
987 | struct xgbe_prv_data, | |
988 | tx_tstamp_work); | |
989 | struct skb_shared_hwtstamps hwtstamps; | |
990 | u64 nsec; | |
991 | unsigned long flags; | |
992 | ||
993 | if (pdata->tx_tstamp) { | |
994 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
995 | pdata->tx_tstamp); | |
996 | ||
997 | memset(&hwtstamps, 0, sizeof(hwtstamps)); | |
998 | hwtstamps.hwtstamp = ns_to_ktime(nsec); | |
999 | skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); | |
1000 | } | |
1001 | ||
1002 | dev_kfree_skb_any(pdata->tx_tstamp_skb); | |
1003 | ||
1004 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1005 | pdata->tx_tstamp_skb = NULL; | |
1006 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1007 | } | |
1008 | ||
1009 | static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1010 | struct ifreq *ifreq) | |
1011 | { | |
1012 | if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, | |
1013 | sizeof(pdata->tstamp_config))) | |
1014 | return -EFAULT; | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1020 | struct ifreq *ifreq) | |
1021 | { | |
1022 | struct hwtstamp_config config; | |
1023 | unsigned int mac_tscr; | |
1024 | ||
1025 | if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) | |
1026 | return -EFAULT; | |
1027 | ||
1028 | if (config.flags) | |
1029 | return -EINVAL; | |
1030 | ||
1031 | mac_tscr = 0; | |
1032 | ||
1033 | switch (config.tx_type) { | |
1034 | case HWTSTAMP_TX_OFF: | |
1035 | break; | |
1036 | ||
1037 | case HWTSTAMP_TX_ON: | |
1038 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1039 | break; | |
1040 | ||
1041 | default: | |
1042 | return -ERANGE; | |
1043 | } | |
1044 | ||
1045 | switch (config.rx_filter) { | |
1046 | case HWTSTAMP_FILTER_NONE: | |
1047 | break; | |
1048 | ||
1049 | case HWTSTAMP_FILTER_ALL: | |
1050 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); | |
1051 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1052 | break; | |
1053 | ||
1054 | /* PTP v2, UDP, any kind of event packet */ | |
1055 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1056 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1057 | /* PTP v1, UDP, any kind of event packet */ | |
1058 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1059 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1060 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1061 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1062 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1063 | break; | |
1064 | ||
1065 | /* PTP v2, UDP, Sync packet */ | |
1066 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1067 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1068 | /* PTP v1, UDP, Sync packet */ | |
1069 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1070 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1071 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1072 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1073 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1074 | break; | |
1075 | ||
1076 | /* PTP v2, UDP, Delay_req packet */ | |
1077 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1078 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1079 | /* PTP v1, UDP, Delay_req packet */ | |
1080 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1081 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1082 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1083 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1084 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1085 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1086 | break; | |
1087 | ||
1088 | /* 802.AS1, Ethernet, any kind of event packet */ | |
1089 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1090 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1091 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1092 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1093 | break; | |
1094 | ||
1095 | /* 802.AS1, Ethernet, Sync packet */ | |
1096 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1097 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1098 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1099 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1100 | break; | |
1101 | ||
1102 | /* 802.AS1, Ethernet, Delay_req packet */ | |
1103 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1104 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1105 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1106 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1107 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1108 | break; | |
1109 | ||
1110 | /* PTP v2/802.AS1, any layer, any kind of event packet */ | |
1111 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1112 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1113 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1114 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1115 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1116 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1117 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1118 | break; | |
1119 | ||
1120 | /* PTP v2/802.AS1, any layer, Sync packet */ | |
1121 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1122 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1123 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1124 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1125 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1126 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1127 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1128 | break; | |
1129 | ||
1130 | /* PTP v2/802.AS1, any layer, Delay_req packet */ | |
1131 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1132 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1133 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1134 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1135 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1136 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1137 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1138 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1139 | break; | |
1140 | ||
1141 | default: | |
1142 | return -ERANGE; | |
1143 | } | |
1144 | ||
1145 | pdata->hw_if.config_tstamp(pdata, mac_tscr); | |
1146 | ||
1147 | memcpy(&pdata->tstamp_config, &config, sizeof(config)); | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, | |
1153 | struct sk_buff *skb, | |
1154 | struct xgbe_packet_data *packet) | |
1155 | { | |
1156 | unsigned long flags; | |
1157 | ||
1158 | if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { | |
1159 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1160 | if (pdata->tx_tstamp_skb) { | |
1161 | /* Another timestamp in progress, ignore this one */ | |
1162 | XGMAC_SET_BITS(packet->attributes, | |
1163 | TX_PACKET_ATTRIBUTES, PTP, 0); | |
1164 | } else { | |
1165 | pdata->tx_tstamp_skb = skb_get(skb); | |
1166 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1167 | } | |
1168 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1169 | } | |
1170 | ||
1171 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) | |
1172 | skb_tx_timestamp(skb); | |
1173 | } | |
1174 | ||
c5aa9e3b LT |
1175 | static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) |
1176 | { | |
df8a39de JP |
1177 | if (skb_vlan_tag_present(skb)) |
1178 | packet->vlan_ctag = skb_vlan_tag_get(skb); | |
c5aa9e3b LT |
1179 | } |
1180 | ||
1181 | static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) | |
1182 | { | |
1183 | int ret; | |
1184 | ||
1185 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1186 | TSO_ENABLE)) | |
1187 | return 0; | |
1188 | ||
1189 | ret = skb_cow_head(skb, 0); | |
1190 | if (ret) | |
1191 | return ret; | |
1192 | ||
1193 | packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1194 | packet->tcp_header_len = tcp_hdrlen(skb); | |
1195 | packet->tcp_payload_len = skb->len - packet->header_len; | |
1196 | packet->mss = skb_shinfo(skb)->gso_size; | |
1197 | DBGPR(" packet->header_len=%u\n", packet->header_len); | |
1198 | DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", | |
1199 | packet->tcp_header_len, packet->tcp_payload_len); | |
1200 | DBGPR(" packet->mss=%u\n", packet->mss); | |
1201 | ||
5fb4b86a LT |
1202 | /* Update the number of packets that will ultimately be transmitted |
1203 | * along with the extra bytes for each extra packet | |
1204 | */ | |
1205 | packet->tx_packets = skb_shinfo(skb)->gso_segs; | |
1206 | packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; | |
1207 | ||
c5aa9e3b LT |
1208 | return 0; |
1209 | } | |
1210 | ||
1211 | static int xgbe_is_tso(struct sk_buff *skb) | |
1212 | { | |
1213 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1214 | return 0; | |
1215 | ||
1216 | if (!skb_is_gso(skb)) | |
1217 | return 0; | |
1218 | ||
1219 | DBGPR(" TSO packet to be processed\n"); | |
1220 | ||
1221 | return 1; | |
1222 | } | |
1223 | ||
23e4eef7 LT |
1224 | static void xgbe_packet_info(struct xgbe_prv_data *pdata, |
1225 | struct xgbe_ring *ring, struct sk_buff *skb, | |
c5aa9e3b LT |
1226 | struct xgbe_packet_data *packet) |
1227 | { | |
1228 | struct skb_frag_struct *frag; | |
1229 | unsigned int context_desc; | |
1230 | unsigned int len; | |
1231 | unsigned int i; | |
1232 | ||
16958a2b LT |
1233 | packet->skb = skb; |
1234 | ||
c5aa9e3b LT |
1235 | context_desc = 0; |
1236 | packet->rdesc_count = 0; | |
1237 | ||
5fb4b86a LT |
1238 | packet->tx_packets = 1; |
1239 | packet->tx_bytes = skb->len; | |
1240 | ||
c5aa9e3b | 1241 | if (xgbe_is_tso(skb)) { |
a7beaf23 | 1242 | /* TSO requires an extra descriptor if mss is different */ |
c5aa9e3b LT |
1243 | if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { |
1244 | context_desc = 1; | |
1245 | packet->rdesc_count++; | |
1246 | } | |
1247 | ||
a7beaf23 | 1248 | /* TSO requires an extra descriptor for TSO header */ |
c5aa9e3b LT |
1249 | packet->rdesc_count++; |
1250 | ||
1251 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1252 | TSO_ENABLE, 1); | |
1253 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1254 | CSUM_ENABLE, 1); | |
1255 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) | |
1256 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1257 | CSUM_ENABLE, 1); | |
1258 | ||
df8a39de | 1259 | if (skb_vlan_tag_present(skb)) { |
c5aa9e3b | 1260 | /* VLAN requires an extra descriptor if tag is different */ |
df8a39de | 1261 | if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) |
c5aa9e3b LT |
1262 | /* We can share with the TSO context descriptor */ |
1263 | if (!context_desc) { | |
1264 | context_desc = 1; | |
1265 | packet->rdesc_count++; | |
1266 | } | |
1267 | ||
1268 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1269 | VLAN_CTAG, 1); | |
1270 | } | |
1271 | ||
23e4eef7 LT |
1272 | if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
1273 | (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) | |
1274 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1275 | PTP, 1); | |
1276 | ||
c5aa9e3b LT |
1277 | for (len = skb_headlen(skb); len;) { |
1278 | packet->rdesc_count++; | |
d0a8ba6c | 1279 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1280 | } |
1281 | ||
1282 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1283 | frag = &skb_shinfo(skb)->frags[i]; | |
1284 | for (len = skb_frag_size(frag); len; ) { | |
1285 | packet->rdesc_count++; | |
d0a8ba6c | 1286 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1287 | } |
1288 | } | |
1289 | } | |
1290 | ||
1291 | static int xgbe_open(struct net_device *netdev) | |
1292 | { | |
1293 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1294 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1295 | int ret; | |
1296 | ||
1297 | DBGPR("-->xgbe_open\n"); | |
1298 | ||
88131a81 LT |
1299 | /* Initialize the phy */ |
1300 | ret = xgbe_phy_init(pdata); | |
1301 | if (ret) | |
1302 | return ret; | |
1303 | ||
23e4eef7 LT |
1304 | /* Enable the clocks */ |
1305 | ret = clk_prepare_enable(pdata->sysclk); | |
c5aa9e3b | 1306 | if (ret) { |
23e4eef7 | 1307 | netdev_alert(netdev, "dma clk_prepare_enable failed\n"); |
7c12aa08 | 1308 | return ret; |
c5aa9e3b LT |
1309 | } |
1310 | ||
23e4eef7 LT |
1311 | ret = clk_prepare_enable(pdata->ptpclk); |
1312 | if (ret) { | |
1313 | netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); | |
1314 | goto err_sysclk; | |
1315 | } | |
1316 | ||
c5aa9e3b LT |
1317 | /* Calculate the Rx buffer size before allocating rings */ |
1318 | ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); | |
1319 | if (ret < 0) | |
23e4eef7 | 1320 | goto err_ptpclk; |
c5aa9e3b LT |
1321 | pdata->rx_buf_size = ret; |
1322 | ||
4780b7ca LT |
1323 | /* Allocate the channel and ring structures */ |
1324 | ret = xgbe_alloc_channels(pdata); | |
1325 | if (ret) | |
1326 | goto err_ptpclk; | |
1327 | ||
c5aa9e3b LT |
1328 | /* Allocate the ring descriptors and buffers */ |
1329 | ret = desc_if->alloc_ring_resources(pdata); | |
1330 | if (ret) | |
4780b7ca | 1331 | goto err_channels; |
c5aa9e3b | 1332 | |
7c12aa08 | 1333 | INIT_WORK(&pdata->service_work, xgbe_service); |
c5aa9e3b | 1334 | INIT_WORK(&pdata->restart_work, xgbe_restart); |
23e4eef7 | 1335 | INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); |
7c12aa08 | 1336 | xgbe_init_timers(pdata); |
c5aa9e3b | 1337 | |
c5aa9e3b LT |
1338 | ret = xgbe_start(pdata); |
1339 | if (ret) | |
c30e76a7 | 1340 | goto err_rings; |
c5aa9e3b | 1341 | |
7c12aa08 LT |
1342 | clear_bit(XGBE_DOWN, &pdata->dev_state); |
1343 | ||
c5aa9e3b LT |
1344 | DBGPR("<--xgbe_open\n"); |
1345 | ||
1346 | return 0; | |
1347 | ||
4780b7ca | 1348 | err_rings: |
c5aa9e3b LT |
1349 | desc_if->free_ring_resources(pdata); |
1350 | ||
4780b7ca LT |
1351 | err_channels: |
1352 | xgbe_free_channels(pdata); | |
1353 | ||
23e4eef7 LT |
1354 | err_ptpclk: |
1355 | clk_disable_unprepare(pdata->ptpclk); | |
1356 | ||
1357 | err_sysclk: | |
1358 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b LT |
1359 | |
1360 | return ret; | |
1361 | } | |
1362 | ||
1363 | static int xgbe_close(struct net_device *netdev) | |
1364 | { | |
1365 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1366 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1367 | ||
1368 | DBGPR("-->xgbe_close\n"); | |
1369 | ||
1370 | /* Stop the device */ | |
1371 | xgbe_stop(pdata); | |
1372 | ||
4780b7ca | 1373 | /* Free the ring descriptors and buffers */ |
c5aa9e3b LT |
1374 | desc_if->free_ring_resources(pdata); |
1375 | ||
e98c72c9 LT |
1376 | /* Free the channel and ring structures */ |
1377 | xgbe_free_channels(pdata); | |
1378 | ||
23e4eef7 LT |
1379 | /* Disable the clocks */ |
1380 | clk_disable_unprepare(pdata->ptpclk); | |
1381 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b | 1382 | |
7c12aa08 | 1383 | set_bit(XGBE_DOWN, &pdata->dev_state); |
88131a81 | 1384 | |
c5aa9e3b LT |
1385 | DBGPR("<--xgbe_close\n"); |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) | |
1391 | { | |
1392 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1393 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1394 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
1395 | struct xgbe_channel *channel; | |
1396 | struct xgbe_ring *ring; | |
1397 | struct xgbe_packet_data *packet; | |
5fb4b86a | 1398 | struct netdev_queue *txq; |
c5aa9e3b LT |
1399 | int ret; |
1400 | ||
1401 | DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); | |
1402 | ||
1403 | channel = pdata->channel + skb->queue_mapping; | |
5fb4b86a | 1404 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
c5aa9e3b LT |
1405 | ring = channel->tx_ring; |
1406 | packet = &ring->packet_data; | |
1407 | ||
1408 | ret = NETDEV_TX_OK; | |
1409 | ||
c5aa9e3b | 1410 | if (skb->len == 0) { |
34bf65df LT |
1411 | netif_err(pdata, tx_err, netdev, |
1412 | "empty skb received from stack\n"); | |
c5aa9e3b LT |
1413 | dev_kfree_skb_any(skb); |
1414 | goto tx_netdev_return; | |
1415 | } | |
1416 | ||
1417 | /* Calculate preliminary packet info */ | |
1418 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 | 1419 | xgbe_packet_info(pdata, ring, skb, packet); |
c5aa9e3b LT |
1420 | |
1421 | /* Check that there are enough descriptors available */ | |
16958a2b LT |
1422 | ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); |
1423 | if (ret) | |
c5aa9e3b | 1424 | goto tx_netdev_return; |
c5aa9e3b LT |
1425 | |
1426 | ret = xgbe_prep_tso(skb, packet); | |
1427 | if (ret) { | |
34bf65df LT |
1428 | netif_err(pdata, tx_err, netdev, |
1429 | "error processing TSO packet\n"); | |
c5aa9e3b LT |
1430 | dev_kfree_skb_any(skb); |
1431 | goto tx_netdev_return; | |
1432 | } | |
1433 | xgbe_prep_vlan(skb, packet); | |
1434 | ||
1435 | if (!desc_if->map_tx_skb(channel, skb)) { | |
1436 | dev_kfree_skb_any(skb); | |
1437 | goto tx_netdev_return; | |
1438 | } | |
1439 | ||
23e4eef7 LT |
1440 | xgbe_prep_tx_tstamp(pdata, skb, packet); |
1441 | ||
5fb4b86a LT |
1442 | /* Report on the actual number of bytes (to be) sent */ |
1443 | netdev_tx_sent_queue(txq, packet->tx_bytes); | |
1444 | ||
c5aa9e3b | 1445 | /* Configure required descriptor fields for transmission */ |
a9d41981 | 1446 | hw_if->dev_xmit(channel); |
c5aa9e3b | 1447 | |
34bf65df LT |
1448 | if (netif_msg_pktdata(pdata)) |
1449 | xgbe_print_pkt(netdev, skb, true); | |
c5aa9e3b | 1450 | |
16958a2b LT |
1451 | /* Stop the queue in advance if there may not be enough descriptors */ |
1452 | xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); | |
1453 | ||
1454 | ret = NETDEV_TX_OK; | |
1455 | ||
c5aa9e3b | 1456 | tx_netdev_return: |
c5aa9e3b LT |
1457 | return ret; |
1458 | } | |
1459 | ||
1460 | static void xgbe_set_rx_mode(struct net_device *netdev) | |
1461 | { | |
1462 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1463 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
1464 | |
1465 | DBGPR("-->xgbe_set_rx_mode\n"); | |
1466 | ||
b876382b | 1467 | hw_if->config_rx_mode(pdata); |
c5aa9e3b LT |
1468 | |
1469 | DBGPR("<--xgbe_set_rx_mode\n"); | |
1470 | } | |
1471 | ||
1472 | static int xgbe_set_mac_address(struct net_device *netdev, void *addr) | |
1473 | { | |
1474 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1475 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1476 | struct sockaddr *saddr = addr; | |
1477 | ||
1478 | DBGPR("-->xgbe_set_mac_address\n"); | |
1479 | ||
1480 | if (!is_valid_ether_addr(saddr->sa_data)) | |
1481 | return -EADDRNOTAVAIL; | |
1482 | ||
1483 | memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); | |
1484 | ||
1485 | hw_if->set_mac_address(pdata, netdev->dev_addr); | |
1486 | ||
1487 | DBGPR("<--xgbe_set_mac_address\n"); | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
23e4eef7 LT |
1492 | static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) |
1493 | { | |
1494 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1495 | int ret; | |
1496 | ||
1497 | switch (cmd) { | |
1498 | case SIOCGHWTSTAMP: | |
1499 | ret = xgbe_get_hwtstamp_settings(pdata, ifreq); | |
1500 | break; | |
1501 | ||
1502 | case SIOCSHWTSTAMP: | |
1503 | ret = xgbe_set_hwtstamp_settings(pdata, ifreq); | |
1504 | break; | |
1505 | ||
1506 | default: | |
1507 | ret = -EOPNOTSUPP; | |
1508 | } | |
1509 | ||
1510 | return ret; | |
1511 | } | |
1512 | ||
c5aa9e3b LT |
1513 | static int xgbe_change_mtu(struct net_device *netdev, int mtu) |
1514 | { | |
1515 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1516 | int ret; | |
1517 | ||
1518 | DBGPR("-->xgbe_change_mtu\n"); | |
1519 | ||
1520 | ret = xgbe_calc_rx_buf_size(netdev, mtu); | |
1521 | if (ret < 0) | |
1522 | return ret; | |
1523 | ||
1524 | pdata->rx_buf_size = ret; | |
1525 | netdev->mtu = mtu; | |
1526 | ||
916102c6 | 1527 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
1528 | |
1529 | DBGPR("<--xgbe_change_mtu\n"); | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
a8373f1a LT |
1534 | static void xgbe_tx_timeout(struct net_device *netdev) |
1535 | { | |
1536 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1537 | ||
1538 | netdev_warn(netdev, "tx timeout, device restarting\n"); | |
1539 | schedule_work(&pdata->restart_work); | |
1540 | } | |
1541 | ||
c5aa9e3b LT |
1542 | static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, |
1543 | struct rtnl_link_stats64 *s) | |
1544 | { | |
1545 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1546 | struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; | |
1547 | ||
1548 | DBGPR("-->%s\n", __func__); | |
1549 | ||
1550 | pdata->hw_if.read_mmc_stats(pdata); | |
1551 | ||
1552 | s->rx_packets = pstats->rxframecount_gb; | |
1553 | s->rx_bytes = pstats->rxoctetcount_gb; | |
1554 | s->rx_errors = pstats->rxframecount_gb - | |
1555 | pstats->rxbroadcastframes_g - | |
1556 | pstats->rxmulticastframes_g - | |
1557 | pstats->rxunicastframes_g; | |
1558 | s->multicast = pstats->rxmulticastframes_g; | |
1559 | s->rx_length_errors = pstats->rxlengtherror; | |
1560 | s->rx_crc_errors = pstats->rxcrcerror; | |
1561 | s->rx_fifo_errors = pstats->rxfifooverflow; | |
1562 | ||
1563 | s->tx_packets = pstats->txframecount_gb; | |
1564 | s->tx_bytes = pstats->txoctetcount_gb; | |
1565 | s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; | |
1566 | s->tx_dropped = netdev->stats.tx_dropped; | |
1567 | ||
1568 | DBGPR("<--%s\n", __func__); | |
1569 | ||
1570 | return s; | |
1571 | } | |
1572 | ||
801c62d9 LT |
1573 | static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, |
1574 | u16 vid) | |
1575 | { | |
1576 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1577 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1578 | ||
1579 | DBGPR("-->%s\n", __func__); | |
1580 | ||
1581 | set_bit(vid, pdata->active_vlans); | |
1582 | hw_if->update_vlan_hash_table(pdata); | |
1583 | ||
1584 | DBGPR("<--%s\n", __func__); | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, | |
1590 | u16 vid) | |
1591 | { | |
1592 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1593 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1594 | ||
1595 | DBGPR("-->%s\n", __func__); | |
1596 | ||
1597 | clear_bit(vid, pdata->active_vlans); | |
1598 | hw_if->update_vlan_hash_table(pdata); | |
1599 | ||
1600 | DBGPR("<--%s\n", __func__); | |
1601 | ||
1602 | return 0; | |
1603 | } | |
1604 | ||
c5aa9e3b LT |
1605 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1606 | static void xgbe_poll_controller(struct net_device *netdev) | |
1607 | { | |
1608 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
9227dc5e LT |
1609 | struct xgbe_channel *channel; |
1610 | unsigned int i; | |
c5aa9e3b LT |
1611 | |
1612 | DBGPR("-->xgbe_poll_controller\n"); | |
1613 | ||
9227dc5e LT |
1614 | if (pdata->per_channel_irq) { |
1615 | channel = pdata->channel; | |
1616 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
1617 | xgbe_dma_isr(channel->dma_irq, channel); | |
1618 | } else { | |
1619 | disable_irq(pdata->dev_irq); | |
1620 | xgbe_isr(pdata->dev_irq, pdata); | |
1621 | enable_irq(pdata->dev_irq); | |
1622 | } | |
c5aa9e3b LT |
1623 | |
1624 | DBGPR("<--xgbe_poll_controller\n"); | |
1625 | } | |
1626 | #endif /* End CONFIG_NET_POLL_CONTROLLER */ | |
1627 | ||
fca2d994 LT |
1628 | static int xgbe_setup_tc(struct net_device *netdev, u8 tc) |
1629 | { | |
1630 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1631 | unsigned int offset, queue; | |
1632 | u8 i; | |
1633 | ||
1634 | if (tc && (tc != pdata->hw_feat.tc_cnt)) | |
1635 | return -EINVAL; | |
1636 | ||
1637 | if (tc) { | |
1638 | netdev_set_num_tc(netdev, tc); | |
1639 | for (i = 0, queue = 0, offset = 0; i < tc; i++) { | |
1640 | while ((queue < pdata->tx_q_count) && | |
1641 | (pdata->q2tc_map[queue] == i)) | |
1642 | queue++; | |
1643 | ||
34bf65df LT |
1644 | netif_dbg(pdata, drv, netdev, "TC%u using TXq%u-%u\n", |
1645 | i, offset, queue - 1); | |
fca2d994 LT |
1646 | netdev_set_tc_queue(netdev, i, queue - offset, offset); |
1647 | offset = queue; | |
1648 | } | |
1649 | } else { | |
1650 | netdev_reset_tc(netdev); | |
1651 | } | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
c5aa9e3b LT |
1656 | static int xgbe_set_features(struct net_device *netdev, |
1657 | netdev_features_t features) | |
1658 | { | |
1659 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1660 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
5b9dfe29 LT |
1661 | netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; |
1662 | int ret = 0; | |
c5aa9e3b | 1663 | |
5b9dfe29 | 1664 | rxhash = pdata->netdev_features & NETIF_F_RXHASH; |
801c62d9 LT |
1665 | rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; |
1666 | rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; | |
1667 | rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; | |
c5aa9e3b | 1668 | |
5b9dfe29 LT |
1669 | if ((features & NETIF_F_RXHASH) && !rxhash) |
1670 | ret = hw_if->enable_rss(pdata); | |
1671 | else if (!(features & NETIF_F_RXHASH) && rxhash) | |
1672 | ret = hw_if->disable_rss(pdata); | |
1673 | if (ret) | |
1674 | return ret; | |
1675 | ||
801c62d9 | 1676 | if ((features & NETIF_F_RXCSUM) && !rxcsum) |
c5aa9e3b | 1677 | hw_if->enable_rx_csum(pdata); |
801c62d9 | 1678 | else if (!(features & NETIF_F_RXCSUM) && rxcsum) |
c5aa9e3b | 1679 | hw_if->disable_rx_csum(pdata); |
c5aa9e3b | 1680 | |
801c62d9 | 1681 | if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) |
c5aa9e3b | 1682 | hw_if->enable_rx_vlan_stripping(pdata); |
801c62d9 | 1683 | else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) |
c5aa9e3b | 1684 | hw_if->disable_rx_vlan_stripping(pdata); |
801c62d9 LT |
1685 | |
1686 | if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) | |
1687 | hw_if->enable_rx_vlan_filtering(pdata); | |
1688 | else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) | |
1689 | hw_if->disable_rx_vlan_filtering(pdata); | |
c5aa9e3b LT |
1690 | |
1691 | pdata->netdev_features = features; | |
1692 | ||
1693 | DBGPR("<--xgbe_set_features\n"); | |
1694 | ||
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static const struct net_device_ops xgbe_netdev_ops = { | |
1699 | .ndo_open = xgbe_open, | |
1700 | .ndo_stop = xgbe_close, | |
1701 | .ndo_start_xmit = xgbe_xmit, | |
1702 | .ndo_set_rx_mode = xgbe_set_rx_mode, | |
1703 | .ndo_set_mac_address = xgbe_set_mac_address, | |
1704 | .ndo_validate_addr = eth_validate_addr, | |
23e4eef7 | 1705 | .ndo_do_ioctl = xgbe_ioctl, |
c5aa9e3b | 1706 | .ndo_change_mtu = xgbe_change_mtu, |
a8373f1a | 1707 | .ndo_tx_timeout = xgbe_tx_timeout, |
c5aa9e3b | 1708 | .ndo_get_stats64 = xgbe_get_stats64, |
801c62d9 LT |
1709 | .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, |
1710 | .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, | |
c5aa9e3b LT |
1711 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1712 | .ndo_poll_controller = xgbe_poll_controller, | |
1713 | #endif | |
fca2d994 | 1714 | .ndo_setup_tc = xgbe_setup_tc, |
c5aa9e3b LT |
1715 | .ndo_set_features = xgbe_set_features, |
1716 | }; | |
1717 | ||
1718 | struct net_device_ops *xgbe_get_netdev_ops(void) | |
1719 | { | |
1720 | return (struct net_device_ops *)&xgbe_netdev_ops; | |
1721 | } | |
1722 | ||
9867e8fb LT |
1723 | static void xgbe_rx_refresh(struct xgbe_channel *channel) |
1724 | { | |
1725 | struct xgbe_prv_data *pdata = channel->pdata; | |
270894e7 | 1726 | struct xgbe_hw_if *hw_if = &pdata->hw_if; |
9867e8fb LT |
1727 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1728 | struct xgbe_ring *ring = channel->rx_ring; | |
1729 | struct xgbe_ring_data *rdata; | |
1730 | ||
270894e7 LT |
1731 | while (ring->dirty != ring->cur) { |
1732 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); | |
1733 | ||
1734 | /* Reset rdata values */ | |
1735 | desc_if->unmap_rdata(pdata, rdata); | |
1736 | ||
1737 | if (desc_if->map_rx_buffer(pdata, ring, rdata)) | |
1738 | break; | |
1739 | ||
8dee19e6 | 1740 | hw_if->rx_desc_reset(pdata, rdata, ring->dirty); |
270894e7 LT |
1741 | |
1742 | ring->dirty++; | |
1743 | } | |
9867e8fb | 1744 | |
ceb8f6be LT |
1745 | /* Make sure everything is written before the register write */ |
1746 | wmb(); | |
1747 | ||
9867e8fb LT |
1748 | /* Update the Rx Tail Pointer Register with address of |
1749 | * the last cleaned entry */ | |
270894e7 | 1750 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); |
9867e8fb LT |
1751 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, |
1752 | lower_32_bits(rdata->rdesc_dma)); | |
1753 | } | |
1754 | ||
7d9ca345 LT |
1755 | static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, |
1756 | struct napi_struct *napi, | |
08dcc47c | 1757 | struct xgbe_ring_data *rdata, |
7d9ca345 | 1758 | unsigned int len) |
08dcc47c | 1759 | { |
08dcc47c LT |
1760 | struct sk_buff *skb; |
1761 | u8 *packet; | |
1762 | unsigned int copy_len; | |
1763 | ||
385565a1 | 1764 | skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); |
08dcc47c LT |
1765 | if (!skb) |
1766 | return NULL; | |
1767 | ||
7d9ca345 LT |
1768 | /* Start with the header buffer which may contain just the header |
1769 | * or the header plus data | |
1770 | */ | |
cfbfd86b LT |
1771 | dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, |
1772 | rdata->rx.hdr.dma_off, | |
1773 | rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); | |
7d9ca345 | 1774 | |
c9f140eb LT |
1775 | packet = page_address(rdata->rx.hdr.pa.pages) + |
1776 | rdata->rx.hdr.pa.pages_offset; | |
7d9ca345 | 1777 | copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len; |
c9f140eb | 1778 | copy_len = min(rdata->rx.hdr.dma_len, copy_len); |
08dcc47c LT |
1779 | skb_copy_to_linear_data(skb, packet, copy_len); |
1780 | skb_put(skb, copy_len); | |
1781 | ||
7d9ca345 LT |
1782 | len -= copy_len; |
1783 | if (len) { | |
1784 | /* Add the remaining data as a frag */ | |
cfbfd86b LT |
1785 | dma_sync_single_range_for_cpu(pdata->dev, |
1786 | rdata->rx.buf.dma_base, | |
1787 | rdata->rx.buf.dma_off, | |
1788 | rdata->rx.buf.dma_len, | |
1789 | DMA_FROM_DEVICE); | |
7d9ca345 LT |
1790 | |
1791 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
1792 | rdata->rx.buf.pa.pages, | |
1793 | rdata->rx.buf.pa.pages_offset, | |
1794 | len, rdata->rx.buf.dma_len); | |
1795 | rdata->rx.buf.pa.pages = NULL; | |
1796 | } | |
08dcc47c LT |
1797 | |
1798 | return skb; | |
1799 | } | |
1800 | ||
c5aa9e3b LT |
1801 | static int xgbe_tx_poll(struct xgbe_channel *channel) |
1802 | { | |
1803 | struct xgbe_prv_data *pdata = channel->pdata; | |
1804 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1805 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
1806 | struct xgbe_ring *ring = channel->tx_ring; | |
1807 | struct xgbe_ring_data *rdata; | |
1808 | struct xgbe_ring_desc *rdesc; | |
1809 | struct net_device *netdev = pdata->netdev; | |
5fb4b86a | 1810 | struct netdev_queue *txq; |
c5aa9e3b | 1811 | int processed = 0; |
5fb4b86a | 1812 | unsigned int tx_packets = 0, tx_bytes = 0; |
c5aa9e3b LT |
1813 | |
1814 | DBGPR("-->xgbe_tx_poll\n"); | |
1815 | ||
1816 | /* Nothing to do if there isn't a Tx ring for this channel */ | |
1817 | if (!ring) | |
1818 | return 0; | |
1819 | ||
5fb4b86a LT |
1820 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
1821 | ||
d0a8ba6c | 1822 | while ((processed < XGBE_TX_DESC_MAX_PROC) && |
244d62be | 1823 | (ring->dirty != ring->cur)) { |
d0a8ba6c | 1824 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); |
c5aa9e3b LT |
1825 | rdesc = rdata->rdesc; |
1826 | ||
1827 | if (!hw_if->tx_complete(rdesc)) | |
1828 | break; | |
1829 | ||
5449e271 LT |
1830 | /* Make sure descriptor fields are read after reading the OWN |
1831 | * bit */ | |
ceb8f6be | 1832 | dma_rmb(); |
5449e271 | 1833 | |
34bf65df LT |
1834 | if (netif_msg_tx_done(pdata)) |
1835 | xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); | |
c5aa9e3b | 1836 | |
5fb4b86a LT |
1837 | if (hw_if->is_last_desc(rdesc)) { |
1838 | tx_packets += rdata->tx.packets; | |
1839 | tx_bytes += rdata->tx.bytes; | |
1840 | } | |
1841 | ||
c5aa9e3b | 1842 | /* Free the SKB and reset the descriptor for re-use */ |
08dcc47c | 1843 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
1844 | hw_if->tx_desc_reset(rdata); |
1845 | ||
1846 | processed++; | |
1847 | ring->dirty++; | |
1848 | } | |
1849 | ||
5fb4b86a | 1850 | if (!processed) |
a83ef427 | 1851 | return 0; |
5fb4b86a LT |
1852 | |
1853 | netdev_tx_completed_queue(txq, tx_packets, tx_bytes); | |
1854 | ||
c5aa9e3b | 1855 | if ((ring->tx.queue_stopped == 1) && |
d0a8ba6c | 1856 | (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { |
c5aa9e3b | 1857 | ring->tx.queue_stopped = 0; |
5fb4b86a | 1858 | netif_tx_wake_queue(txq); |
c5aa9e3b LT |
1859 | } |
1860 | ||
1861 | DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); | |
1862 | ||
c5aa9e3b LT |
1863 | return processed; |
1864 | } | |
1865 | ||
1866 | static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) | |
1867 | { | |
1868 | struct xgbe_prv_data *pdata = channel->pdata; | |
1869 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
1870 | struct xgbe_ring *ring = channel->rx_ring; |
1871 | struct xgbe_ring_data *rdata; | |
1872 | struct xgbe_packet_data *packet; | |
1873 | struct net_device *netdev = pdata->netdev; | |
9227dc5e | 1874 | struct napi_struct *napi; |
c5aa9e3b | 1875 | struct sk_buff *skb; |
23e4eef7 LT |
1876 | struct skb_shared_hwtstamps *hwtstamps; |
1877 | unsigned int incomplete, error, context_next, context; | |
7d9ca345 | 1878 | unsigned int len, rdesc_len, max_len; |
55ca6bcd LT |
1879 | unsigned int received = 0; |
1880 | int packet_count = 0; | |
c5aa9e3b LT |
1881 | |
1882 | DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); | |
1883 | ||
1884 | /* Nothing to do if there isn't a Rx ring for this channel */ | |
1885 | if (!ring) | |
1886 | return 0; | |
1887 | ||
7d9ca345 LT |
1888 | incomplete = 0; |
1889 | context_next = 0; | |
1890 | ||
9227dc5e LT |
1891 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
1892 | ||
23e4eef7 | 1893 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
c5aa9e3b | 1894 | packet = &ring->packet_data; |
55ca6bcd | 1895 | while (packet_count < budget) { |
c5aa9e3b LT |
1896 | DBGPR(" cur = %d\n", ring->cur); |
1897 | ||
23e4eef7 LT |
1898 | /* First time in loop see if we need to restore state */ |
1899 | if (!received && rdata->state_saved) { | |
23e4eef7 LT |
1900 | skb = rdata->state.skb; |
1901 | error = rdata->state.error; | |
1902 | len = rdata->state.len; | |
1903 | } else { | |
1904 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 LT |
1905 | skb = NULL; |
1906 | error = 0; | |
1907 | len = 0; | |
1908 | } | |
c5aa9e3b LT |
1909 | |
1910 | read_again: | |
23e4eef7 LT |
1911 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
1912 | ||
270894e7 | 1913 | if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) |
9867e8fb LT |
1914 | xgbe_rx_refresh(channel); |
1915 | ||
c5aa9e3b LT |
1916 | if (hw_if->dev_read(channel)) |
1917 | break; | |
1918 | ||
1919 | received++; | |
1920 | ring->cur++; | |
c5aa9e3b | 1921 | |
c5aa9e3b LT |
1922 | incomplete = XGMAC_GET_BITS(packet->attributes, |
1923 | RX_PACKET_ATTRIBUTES, | |
1924 | INCOMPLETE); | |
23e4eef7 LT |
1925 | context_next = XGMAC_GET_BITS(packet->attributes, |
1926 | RX_PACKET_ATTRIBUTES, | |
1927 | CONTEXT_NEXT); | |
1928 | context = XGMAC_GET_BITS(packet->attributes, | |
1929 | RX_PACKET_ATTRIBUTES, | |
1930 | CONTEXT); | |
c5aa9e3b LT |
1931 | |
1932 | /* Earlier error, just drain the remaining data */ | |
23e4eef7 | 1933 | if ((incomplete || context_next) && error) |
c5aa9e3b LT |
1934 | goto read_again; |
1935 | ||
1936 | if (error || packet->errors) { | |
1937 | if (packet->errors) | |
34bf65df LT |
1938 | netif_err(pdata, rx_err, netdev, |
1939 | "error in received packet\n"); | |
c5aa9e3b | 1940 | dev_kfree_skb(skb); |
55ca6bcd | 1941 | goto next_packet; |
c5aa9e3b LT |
1942 | } |
1943 | ||
23e4eef7 | 1944 | if (!context) { |
7d9ca345 LT |
1945 | /* Length is cumulative, get this descriptor's length */ |
1946 | rdesc_len = rdata->rx.len - len; | |
1947 | len += rdesc_len; | |
1948 | ||
1949 | if (rdesc_len && !skb) { | |
1950 | skb = xgbe_create_skb(pdata, napi, rdata, | |
1951 | rdesc_len); | |
1952 | if (!skb) | |
08dcc47c | 1953 | error = 1; |
7d9ca345 | 1954 | } else if (rdesc_len) { |
cfbfd86b LT |
1955 | dma_sync_single_range_for_cpu(pdata->dev, |
1956 | rdata->rx.buf.dma_base, | |
1957 | rdata->rx.buf.dma_off, | |
c9f140eb | 1958 | rdata->rx.buf.dma_len, |
174fd259 LT |
1959 | DMA_FROM_DEVICE); |
1960 | ||
1961 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
c9f140eb LT |
1962 | rdata->rx.buf.pa.pages, |
1963 | rdata->rx.buf.pa.pages_offset, | |
7d9ca345 LT |
1964 | rdesc_len, |
1965 | rdata->rx.buf.dma_len); | |
c9f140eb | 1966 | rdata->rx.buf.pa.pages = NULL; |
174fd259 | 1967 | } |
c5aa9e3b | 1968 | } |
c5aa9e3b | 1969 | |
23e4eef7 | 1970 | if (incomplete || context_next) |
c5aa9e3b LT |
1971 | goto read_again; |
1972 | ||
23e4eef7 | 1973 | if (!skb) |
55ca6bcd | 1974 | goto next_packet; |
23e4eef7 | 1975 | |
c5aa9e3b LT |
1976 | /* Be sure we don't exceed the configured MTU */ |
1977 | max_len = netdev->mtu + ETH_HLEN; | |
1978 | if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
1979 | (skb->protocol == htons(ETH_P_8021Q))) | |
1980 | max_len += VLAN_HLEN; | |
1981 | ||
1982 | if (skb->len > max_len) { | |
34bf65df LT |
1983 | netif_err(pdata, rx_err, netdev, |
1984 | "packet length exceeds configured MTU\n"); | |
c5aa9e3b | 1985 | dev_kfree_skb(skb); |
55ca6bcd | 1986 | goto next_packet; |
c5aa9e3b LT |
1987 | } |
1988 | ||
34bf65df LT |
1989 | if (netif_msg_pktdata(pdata)) |
1990 | xgbe_print_pkt(netdev, skb, false); | |
c5aa9e3b LT |
1991 | |
1992 | skb_checksum_none_assert(skb); | |
1993 | if (XGMAC_GET_BITS(packet->attributes, | |
1994 | RX_PACKET_ATTRIBUTES, CSUM_DONE)) | |
1995 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1996 | ||
1997 | if (XGMAC_GET_BITS(packet->attributes, | |
1998 | RX_PACKET_ATTRIBUTES, VLAN_CTAG)) | |
1999 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
2000 | packet->vlan_ctag); | |
2001 | ||
23e4eef7 LT |
2002 | if (XGMAC_GET_BITS(packet->attributes, |
2003 | RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { | |
2004 | u64 nsec; | |
2005 | ||
2006 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
2007 | packet->rx_tstamp); | |
2008 | hwtstamps = skb_hwtstamps(skb); | |
2009 | hwtstamps->hwtstamp = ns_to_ktime(nsec); | |
2010 | } | |
2011 | ||
5b9dfe29 LT |
2012 | if (XGMAC_GET_BITS(packet->attributes, |
2013 | RX_PACKET_ATTRIBUTES, RSS_HASH)) | |
2014 | skb_set_hash(skb, packet->rss_hash, | |
2015 | packet->rss_hash_type); | |
2016 | ||
c5aa9e3b LT |
2017 | skb->dev = netdev; |
2018 | skb->protocol = eth_type_trans(skb, netdev); | |
2019 | skb_record_rx_queue(skb, channel->queue_index); | |
9227dc5e | 2020 | skb_mark_napi_id(skb, napi); |
c5aa9e3b | 2021 | |
9227dc5e | 2022 | napi_gro_receive(napi, skb); |
55ca6bcd LT |
2023 | |
2024 | next_packet: | |
2025 | packet_count++; | |
c5aa9e3b LT |
2026 | } |
2027 | ||
23e4eef7 LT |
2028 | /* Check if we need to save state before leaving */ |
2029 | if (received && (incomplete || context_next)) { | |
2030 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); | |
2031 | rdata->state_saved = 1; | |
23e4eef7 LT |
2032 | rdata->state.skb = skb; |
2033 | rdata->state.len = len; | |
2034 | rdata->state.error = error; | |
2035 | } | |
2036 | ||
55ca6bcd | 2037 | DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); |
c5aa9e3b | 2038 | |
55ca6bcd | 2039 | return packet_count; |
c5aa9e3b LT |
2040 | } |
2041 | ||
9227dc5e LT |
2042 | static int xgbe_one_poll(struct napi_struct *napi, int budget) |
2043 | { | |
2044 | struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, | |
2045 | napi); | |
2046 | int processed = 0; | |
2047 | ||
2048 | DBGPR("-->xgbe_one_poll: budget=%d\n", budget); | |
2049 | ||
2050 | /* Cleanup Tx ring first */ | |
2051 | xgbe_tx_poll(channel); | |
2052 | ||
2053 | /* Process Rx ring next */ | |
2054 | processed = xgbe_rx_poll(channel, budget); | |
2055 | ||
2056 | /* If we processed everything, we are done */ | |
2057 | if (processed < budget) { | |
2058 | /* Turn off polling */ | |
2059 | napi_complete(napi); | |
2060 | ||
2061 | /* Enable Tx and Rx interrupts */ | |
2062 | enable_irq(channel->dma_irq); | |
2063 | } | |
2064 | ||
2065 | DBGPR("<--xgbe_one_poll: received = %d\n", processed); | |
2066 | ||
2067 | return processed; | |
2068 | } | |
2069 | ||
2070 | static int xgbe_all_poll(struct napi_struct *napi, int budget) | |
c5aa9e3b LT |
2071 | { |
2072 | struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, | |
2073 | napi); | |
2074 | struct xgbe_channel *channel; | |
9867e8fb LT |
2075 | int ring_budget; |
2076 | int processed, last_processed; | |
c5aa9e3b LT |
2077 | unsigned int i; |
2078 | ||
9227dc5e | 2079 | DBGPR("-->xgbe_all_poll: budget=%d\n", budget); |
c5aa9e3b | 2080 | |
c5aa9e3b | 2081 | processed = 0; |
9867e8fb LT |
2082 | ring_budget = budget / pdata->rx_ring_count; |
2083 | do { | |
2084 | last_processed = processed; | |
2085 | ||
2086 | channel = pdata->channel; | |
2087 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
2088 | /* Cleanup Tx ring first */ | |
2089 | xgbe_tx_poll(channel); | |
2090 | ||
2091 | /* Process Rx ring next */ | |
2092 | if (ring_budget > (budget - processed)) | |
2093 | ring_budget = budget - processed; | |
2094 | processed += xgbe_rx_poll(channel, ring_budget); | |
2095 | } | |
2096 | } while ((processed < budget) && (processed != last_processed)); | |
c5aa9e3b LT |
2097 | |
2098 | /* If we processed everything, we are done */ | |
2099 | if (processed < budget) { | |
2100 | /* Turn off polling */ | |
2101 | napi_complete(napi); | |
2102 | ||
2103 | /* Enable Tx and Rx interrupts */ | |
2104 | xgbe_enable_rx_tx_ints(pdata); | |
2105 | } | |
2106 | ||
9227dc5e | 2107 | DBGPR("<--xgbe_all_poll: received = %d\n", processed); |
c5aa9e3b LT |
2108 | |
2109 | return processed; | |
2110 | } | |
2111 | ||
34bf65df LT |
2112 | void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
2113 | unsigned int idx, unsigned int count, unsigned int flag) | |
c5aa9e3b LT |
2114 | { |
2115 | struct xgbe_ring_data *rdata; | |
2116 | struct xgbe_ring_desc *rdesc; | |
2117 | ||
2118 | while (count--) { | |
d0a8ba6c | 2119 | rdata = XGBE_GET_DESC_DATA(ring, idx); |
c5aa9e3b | 2120 | rdesc = rdata->rdesc; |
34bf65df LT |
2121 | netdev_dbg(pdata->netdev, |
2122 | "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, | |
2123 | (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", | |
2124 | le32_to_cpu(rdesc->desc0), | |
2125 | le32_to_cpu(rdesc->desc1), | |
2126 | le32_to_cpu(rdesc->desc2), | |
2127 | le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2128 | idx++; |
2129 | } | |
2130 | } | |
2131 | ||
34bf65df | 2132 | void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
c5aa9e3b LT |
2133 | unsigned int idx) |
2134 | { | |
34bf65df LT |
2135 | struct xgbe_ring_data *rdata; |
2136 | struct xgbe_ring_desc *rdesc; | |
2137 | ||
2138 | rdata = XGBE_GET_DESC_DATA(ring, idx); | |
2139 | rdesc = rdata->rdesc; | |
2140 | netdev_dbg(pdata->netdev, | |
2141 | "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", | |
2142 | idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), | |
2143 | le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2144 | } |
2145 | ||
2146 | void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) | |
2147 | { | |
2148 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
2149 | unsigned char *buf = skb->data; | |
2150 | unsigned char buffer[128]; | |
2151 | unsigned int i, j; | |
2152 | ||
34bf65df | 2153 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2154 | |
34bf65df LT |
2155 | netdev_dbg(netdev, "%s packet of %d bytes\n", |
2156 | (tx_rx ? "TX" : "RX"), skb->len); | |
c5aa9e3b | 2157 | |
34bf65df LT |
2158 | netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); |
2159 | netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); | |
2160 | netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); | |
c5aa9e3b LT |
2161 | |
2162 | for (i = 0, j = 0; i < skb->len;) { | |
2163 | j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", | |
2164 | buf[i++]); | |
2165 | ||
2166 | if ((i % 32) == 0) { | |
34bf65df | 2167 | netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); |
c5aa9e3b LT |
2168 | j = 0; |
2169 | } else if ((i % 16) == 0) { | |
2170 | buffer[j++] = ' '; | |
2171 | buffer[j++] = ' '; | |
2172 | } else if ((i % 4) == 0) { | |
2173 | buffer[j++] = ' '; | |
2174 | } | |
2175 | } | |
2176 | if (i % 32) | |
34bf65df | 2177 | netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); |
c5aa9e3b | 2178 | |
34bf65df | 2179 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2180 | } |