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amd-xgbe: Perform Tx coalescing on a packet basis
[deliverable/linux.git] / drivers / net / ethernet / amd / xgbe / xgbe.h
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#ifndef __XGBE_H__
118#define __XGBE_H__
119
120#include <linux/dma-mapping.h>
121#include <linux/netdevice.h>
122#include <linux/workqueue.h>
123#include <linux/phy.h>
801c62d9
LT		 124#include <linux/if_vlan.h>
125#include <linux/bitops.h>
23e4eef7
LT		 126#include <linux/ptp_clock_kernel.h>
127#include <linux/clocksource.h>
128#include <linux/net_tstamp.h>
fca2d994 129#include <net/dcbnl.h>
c5aa9e3b 130
c5aa9e3b
LT		 131#define XGBE_DRV_NAME "amd-xgbe"
132#define XGBE_DRV_VERSION "1.0.0-a"
133#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
134
135/* Descriptor related defines */
d0a8ba6c
LT		 136#define XGBE_TX_DESC_CNT 512
137#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139#define XGBE_RX_DESC_CNT 512
c5aa9e3b 140
d0a8ba6c 141#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
c5aa9e3b 142
d0a8ba6c
LT		 143#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144#define XGBE_RX_BUF_ALIGN 64
08dcc47c 145#define XGBE_SKB_ALLOC_SIZE 256
174fd259 146#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
c5aa9e3b 147
d5c48582 148#define XGBE_MAX_DMA_CHANNELS 16
fca2d994 149#define XGBE_MAX_QUEUES 16
16edd34e 150#define XGBE_DMA_STOP_TIMEOUT 5
d0a8ba6c
LT		 151
152/* DMA cache settings - Outer sharable, write-back, write-allocate */
cfa50c78
LT		 153#define XGBE_DMA_OS_AXDOMAIN 0x2
154#define XGBE_DMA_OS_ARCACHE 0xb
155#define XGBE_DMA_OS_AWCACHE 0xf
156
157/* DMA cache settings - System, no caches used */
158#define XGBE_DMA_SYS_AXDOMAIN 0x3
159#define XGBE_DMA_SYS_ARCACHE 0x0
160#define XGBE_DMA_SYS_AWCACHE 0x0
d0a8ba6c
LT		 161
162#define XGBE_DMA_INTERRUPT_MASK 0x31c7
c5aa9e3b
LT		 163
164#define XGMAC_MIN_PACKET 60
165#define XGMAC_STD_PACKET_MTU 1500
166#define XGMAC_MAX_STD_PACKET 1518
167#define XGMAC_JUMBO_PACKET_MTU 9000
168#define XGMAC_MAX_JUMBO_PACKET 9018
169
c5aa9e3b
LT		 170/* MDIO bus phy name */
171#define XGBE_PHY_NAME "amd_xgbe_phy"
172#define XGBE_PRTAD 0
173
23e4eef7
LT		 174/* Device-tree clock names */
175#define XGBE_DMA_CLOCK "dma_clk"
176#define XGBE_PTP_CLOCK "ptp_clk"
9227dc5e 177#define XGBE_DMA_IRQS "amd,per-channel-interrupt"
23e4eef7
LT		 178
179/* Timestamp support - values based on 50MHz PTP clock
180 * 50MHz => 20 nsec
181 */
182#define XGBE_TSTAMP_SSINC 20
183#define XGBE_TSTAMP_SNSINC 0
184
c5aa9e3b
LT		 185/* Driver PMT macros */
186#define XGMAC_DRIVER_CONTEXT 1
187#define XGMAC_IOCTL_CONTEXT 2
188
f076f453 189#define XGBE_FIFO_MAX 81920
d0a8ba6c
LT		 190#define XGBE_FIFO_SIZE_B(x) (x)
191#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
c5aa9e3b 192
fca2d994 193#define XGBE_TC_MIN_QUANTUM 10
c5aa9e3b
LT		 194
195/* Helper macro for descriptor handling
d0a8ba6c 196 * Always use XGBE_GET_DESC_DATA to access the descriptor data
c5aa9e3b
LT		 197 * since the index is free-running and needs to be and-ed
198 * with the descriptor count value of the ring to index to
199 * the proper descriptor data.
200 */
d0a8ba6c 201#define XGBE_GET_DESC_DATA(_ring, _idx) \
c5aa9e3b
LT		 202 ((_ring)->rdata + \
203 ((_idx) & ((_ring)->rdesc_count - 1)))
204
c5aa9e3b 205/* Default coalescing parameters */
9867e8fb
LT		 206#define XGMAC_INIT_DMA_TX_USECS 50
207#define XGMAC_INIT_DMA_TX_FRAMES 25
c5aa9e3b
LT		 208
209#define XGMAC_MAX_DMA_RIWT 0xff
9867e8fb
LT		 210#define XGMAC_INIT_DMA_RX_USECS 30
211#define XGMAC_INIT_DMA_RX_FRAMES 25
c5aa9e3b
LT		 212
213/* Flow control queue count */
214#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
215
b85e4d89
LT		 216/* Maximum MAC address hash table size (256 bits = 8 bytes) */
217#define XGBE_MAC_HASH_TABLE_SIZE 8
c5aa9e3b 218
5b9dfe29
LT		 219/* Receive Side Scaling */
220#define XGBE_RSS_HASH_KEY_SIZE 40
221#define XGBE_RSS_MAX_TABLE_SIZE 256
222#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
223#define XGBE_RSS_HASH_KEY_TYPE 1
224
c5aa9e3b
LT		 225struct xgbe_prv_data;
226
227struct xgbe_packet_data {
228 unsigned int attributes;
229
230 unsigned int errors;
231
232 unsigned int rdesc_count;
233 unsigned int length;
234
235 unsigned int header_len;
236 unsigned int tcp_header_len;
237 unsigned int tcp_payload_len;
238 unsigned short mss;
239
240 unsigned short vlan_ctag;
23e4eef7
LT		 241
242 u64 rx_tstamp;
5b9dfe29
LT		 243
244 u32 rss_hash;
245 enum pkt_hash_types rss_hash_type;
5fb4b86a
LT		 246
247 unsigned int tx_packets;
248 unsigned int tx_bytes;
c5aa9e3b
LT		 249};
250
251/* Common Rx and Tx descriptor mapping */
252struct xgbe_ring_desc {
5226cfc5
LT		 253 __le32 desc0;
254 __le32 desc1;
255 __le32 desc2;
256 __le32 desc3;
c5aa9e3b
LT		 257};
258
08dcc47c
LT		 259/* Page allocation related values */
260struct xgbe_page_alloc {
261 struct page *pages;
262 unsigned int pages_len;
263 unsigned int pages_offset;
264
265 dma_addr_t pages_dma;
266};
267
174fd259
LT		 268/* Ring entry buffer data */
269struct xgbe_buffer_data {
270 struct xgbe_page_alloc pa;
271 struct xgbe_page_alloc pa_unmap;
272
273 dma_addr_t dma;
274 unsigned int dma_len;
275};
276
c9f140eb
LT		 277/* Tx-related ring data */
278struct xgbe_tx_ring_data {
5fb4b86a
LT		 279 unsigned int packets; /* BQL packet count */
280 unsigned int bytes; /* BQL byte count */
c9f140eb
LT		 281};
282
283/* Rx-related ring data */
284struct xgbe_rx_ring_data {
285 struct xgbe_buffer_data hdr; /* Header locations */
286 struct xgbe_buffer_data buf; /* Payload locations */
287
288 unsigned short hdr_len; /* Length of received header */
289 unsigned short len; /* Length of received packet */
290};
291
c5aa9e3b
LT		 292/* Structure used to hold information related to the descriptor
293 * and the packet associated with the descriptor (always use
d0a8ba6c 294 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
c5aa9e3b
LT		 295 */
296struct xgbe_ring_data {
297 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
298 dma_addr_t rdesc_dma; /* DMA address of descriptor */
299
300 struct sk_buff *skb; /* Virtual address of SKB */
301 dma_addr_t skb_dma; /* DMA address of SKB data */
302 unsigned int skb_dma_len; /* Length of SKB DMA area */
c5aa9e3b 303
c9f140eb
LT		 304 struct xgbe_tx_ring_data tx; /* Tx-related data */
305 struct xgbe_rx_ring_data rx; /* Rx-related data */
c5aa9e3b
LT		 306
307 unsigned int interrupt; /* Interrupt indicator */
308
309 unsigned int mapped_as_page;
23e4eef7
LT		 310
311 /* Incomplete receive save location. If the budget is exhausted
312 * or the last descriptor (last normal descriptor or a following
313 * context descriptor) has not been DMA'd yet the current state
314 * of the receive processing needs to be saved.
315 */
316 unsigned int state_saved;
317 struct {
318 unsigned int incomplete;
319 unsigned int context_next;
320 struct sk_buff *skb;
321 unsigned int len;
322 unsigned int error;
323 } state;
c5aa9e3b
LT		 324};
325
326struct xgbe_ring {
327 /* Ring lock - used just for TX rings at the moment */
328 spinlock_t lock;
329
330 /* Per packet related information */
331 struct xgbe_packet_data packet_data;
332
333 /* Virtual/DMA addresses and count of allocated descriptor memory */
334 struct xgbe_ring_desc *rdesc;
335 dma_addr_t rdesc_dma;
336 unsigned int rdesc_count;
337
338 /* Array of descriptor data corresponding the descriptor memory
d0a8ba6c 339 * (always use the XGBE_GET_DESC_DATA macro to access this data)
c5aa9e3b
LT		 340 */
341 struct xgbe_ring_data *rdata;
342
08dcc47c 343 /* Page allocation for RX buffers */
174fd259
LT		 344 struct xgbe_page_alloc rx_hdr_pa;
345 struct xgbe_page_alloc rx_buf_pa;
08dcc47c 346
c5aa9e3b
LT		 347 /* Ring index values
348 * cur - Tx: index of descriptor to be used for current transfer
349 * Rx: index of descriptor to check for packet availability
350 * dirty - Tx: index of descriptor to check for transfer complete
351 * Rx: count of descriptors in which a packet has been received
352 * (used with skb_realloc_index to refresh the ring)
353 */
354 unsigned int cur;
355 unsigned int dirty;
356
357 /* Coalesce frame count used for interrupt bit setting */
358 unsigned int coalesce_count;
359
360 union {
361 struct {
362 unsigned int queue_stopped;
363 unsigned short cur_mss;
364 unsigned short cur_vlan_ctag;
365 } tx;
366
367 struct {
368 unsigned int realloc_index;
369 unsigned int realloc_threshold;
370 } rx;
371 };
372} ____cacheline_aligned;
373
374/* Structure used to describe the descriptor rings associated with
375 * a DMA channel.
376 */
377struct xgbe_channel {
378 char name[16];
379
380 /* Address of private data area for device */
381 struct xgbe_prv_data *pdata;
382
383 /* Queue index and base address of queue's DMA registers */
384 unsigned int queue_index;
385 void __iomem *dma_regs;
386
9227dc5e
LT		 387 /* Per channel interrupt irq number */
388 int dma_irq;
389
390 /* Netdev related settings */
391 struct napi_struct napi;
392
c5aa9e3b
LT		 393 unsigned int saved_ier;
394
395 unsigned int tx_timer_active;
396 struct hrtimer tx_timer;
397
398 struct xgbe_ring *tx_ring;
399 struct xgbe_ring *rx_ring;
400} ____cacheline_aligned;
401
402enum xgbe_int {
c5aa9e3b
LT		 403 XGMAC_INT_DMA_CH_SR_TI,
404 XGMAC_INT_DMA_CH_SR_TPS,
405 XGMAC_INT_DMA_CH_SR_TBU,
406 XGMAC_INT_DMA_CH_SR_RI,
407 XGMAC_INT_DMA_CH_SR_RBU,
408 XGMAC_INT_DMA_CH_SR_RPS,
9867e8fb 409 XGMAC_INT_DMA_CH_SR_TI_RI,
c5aa9e3b
LT		 410 XGMAC_INT_DMA_CH_SR_FBE,
411 XGMAC_INT_DMA_ALL,
412};
413
414enum xgbe_int_state {
415 XGMAC_INT_STATE_SAVE,
416 XGMAC_INT_STATE_RESTORE,
417};
418
419enum xgbe_mtl_fifo_size {
420 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
421 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
422 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
423 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
424 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
425 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
426 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
427 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
428 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
429 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
430 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
431};
432
433struct xgbe_mmc_stats {
434 /* Tx Stats */
435 u64 txoctetcount_gb;
436 u64 txframecount_gb;
437 u64 txbroadcastframes_g;
438 u64 txmulticastframes_g;
439 u64 tx64octets_gb;
440 u64 tx65to127octets_gb;
441 u64 tx128to255octets_gb;
442 u64 tx256to511octets_gb;
443 u64 tx512to1023octets_gb;
444 u64 tx1024tomaxoctets_gb;
445 u64 txunicastframes_gb;
446 u64 txmulticastframes_gb;
447 u64 txbroadcastframes_gb;
448 u64 txunderflowerror;
449 u64 txoctetcount_g;
450 u64 txframecount_g;
451 u64 txpauseframes;
452 u64 txvlanframes_g;
453
454 /* Rx Stats */
455 u64 rxframecount_gb;
456 u64 rxoctetcount_gb;
457 u64 rxoctetcount_g;
458 u64 rxbroadcastframes_g;
459 u64 rxmulticastframes_g;
460 u64 rxcrcerror;
461 u64 rxrunterror;
462 u64 rxjabbererror;
463 u64 rxundersize_g;
464 u64 rxoversize_g;
465 u64 rx64octets_gb;
466 u64 rx65to127octets_gb;
467 u64 rx128to255octets_gb;
468 u64 rx256to511octets_gb;
469 u64 rx512to1023octets_gb;
470 u64 rx1024tomaxoctets_gb;
471 u64 rxunicastframes_g;
472 u64 rxlengtherror;
473 u64 rxoutofrangetype;
474 u64 rxpauseframes;
475 u64 rxfifooverflow;
476 u64 rxvlanframes_gb;
477 u64 rxwatchdogerror;
478};
479
480struct xgbe_hw_if {
481 int (*tx_complete)(struct xgbe_ring_desc *);
482
483 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
484 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
b85e4d89 485 int (*add_mac_addresses)(struct xgbe_prv_data *);
c5aa9e3b
LT		 486 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
487
488 int (*enable_rx_csum)(struct xgbe_prv_data *);
489 int (*disable_rx_csum)(struct xgbe_prv_data *);
490
491 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
492 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
801c62d9
LT		 493 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
494 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
495 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
c5aa9e3b
LT		 496
497 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
498 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
499 int (*set_gmii_speed)(struct xgbe_prv_data *);
500 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
501 int (*set_xgmii_speed)(struct xgbe_prv_data *);
502
503 void (*enable_tx)(struct xgbe_prv_data *);
504 void (*disable_tx)(struct xgbe_prv_data *);
505 void (*enable_rx)(struct xgbe_prv_data *);
506 void (*disable_rx)(struct xgbe_prv_data *);
507
508 void (*powerup_tx)(struct xgbe_prv_data *);
509 void (*powerdown_tx)(struct xgbe_prv_data *);
510 void (*powerup_rx)(struct xgbe_prv_data *);
511 void (*powerdown_rx)(struct xgbe_prv_data *);
512
513 int (*init)(struct xgbe_prv_data *);
514 int (*exit)(struct xgbe_prv_data *);
515
516 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
517 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
a9d41981 518 void (*dev_xmit)(struct xgbe_channel *);
c5aa9e3b
LT		 519 int (*dev_read)(struct xgbe_channel *);
520 void (*tx_desc_init)(struct xgbe_channel *);
521 void (*rx_desc_init)(struct xgbe_channel *);
522 void (*rx_desc_reset)(struct xgbe_ring_data *);
523 void (*tx_desc_reset)(struct xgbe_ring_data *);
524 int (*is_last_desc)(struct xgbe_ring_desc *);
525 int (*is_context_desc)(struct xgbe_ring_desc *);
526
527 /* For FLOW ctrl */
528 int (*config_tx_flow_control)(struct xgbe_prv_data *);
529 int (*config_rx_flow_control)(struct xgbe_prv_data *);
530
531 /* For RX coalescing */
532 int (*config_rx_coalesce)(struct xgbe_prv_data *);
533 int (*config_tx_coalesce)(struct xgbe_prv_data *);
534 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
535 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
536
537 /* For RX and TX threshold config */
538 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
539 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
540
541 /* For RX and TX Store and Forward Mode config */
542 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
543 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
544
545 /* For TX DMA Operate on Second Frame config */
546 int (*config_osp_mode)(struct xgbe_prv_data *);
547
548 /* For RX and TX PBL config */
549 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
550 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
551 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
552 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
553 int (*config_pblx8)(struct xgbe_prv_data *);
554
555 /* For MMC statistics */
556 void (*rx_mmc_int)(struct xgbe_prv_data *);
557 void (*tx_mmc_int)(struct xgbe_prv_data *);
558 void (*read_mmc_stats)(struct xgbe_prv_data *);
23e4eef7
LT		 559
560 /* For Timestamp config */
561 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
562 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
563 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
564 unsigned int nsec);
565 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
566 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
fca2d994
LT		 567
568 /* For Data Center Bridging config */
569 void (*config_dcb_tc)(struct xgbe_prv_data *);
570 void (*config_dcb_pfc)(struct xgbe_prv_data *);
5b9dfe29
LT		 571
572 /* For Receive Side Scaling */
573 int (*enable_rss)(struct xgbe_prv_data *);
574 int (*disable_rss)(struct xgbe_prv_data *);
f6ac8628
LT		 575 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
576 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
c5aa9e3b
LT		 577};
578
579struct xgbe_desc_if {
580 int (*alloc_ring_resources)(struct xgbe_prv_data *);
581 void (*free_ring_resources)(struct xgbe_prv_data *);
582 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
08dcc47c
LT		 583 void (*realloc_rx_buffer)(struct xgbe_channel *);
584 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
c5aa9e3b
LT		 585 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
586 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
587};
588
589/* This structure contains flags that indicate what hardware features
590 * or configurations are present in the device.
591 */
592struct xgbe_hw_features {
a9a4a2d9
LT		 593 /* HW Version */
594 unsigned int version;
595
c5aa9e3b
LT		 596 /* HW Feature Register0 */
597 unsigned int gmii; /* 1000 Mbps support */
598 unsigned int vlhash; /* VLAN Hash Filter */
599 unsigned int sma; /* SMA(MDIO) Interface */
600 unsigned int rwk; /* PMT remote wake-up packet */
601 unsigned int mgk; /* PMT magic packet */
602 unsigned int mmc; /* RMON module */
603 unsigned int aoe; /* ARP Offload */
604 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
605 unsigned int eee; /* Energy Efficient Ethernet */
606 unsigned int tx_coe; /* Tx Checksum Offload */
607 unsigned int rx_coe; /* Rx Checksum Offload */
608 unsigned int addn_mac; /* Additional MAC Addresses */
609 unsigned int ts_src; /* Timestamp Source */
610 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
611
612 /* HW Feature Register1 */
613 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
614 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
615 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
616 unsigned int dcb; /* DCB Feature */
617 unsigned int sph; /* Split Header Feature */
618 unsigned int tso; /* TCP Segmentation Offload */
619 unsigned int dma_debug; /* DMA Debug Registers */
620 unsigned int rss; /* Receive Side Scaling */
fca2d994 621 unsigned int tc_cnt; /* Number of Traffic Classes */
c5aa9e3b
LT		 622 unsigned int hash_table_size; /* Hash Table Size */
623 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
624
625 /* HW Feature Register2 */
626 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
627 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
628 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
629 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
630 unsigned int pps_out_num; /* Number of PPS outputs */
631 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
632};
633
634struct xgbe_prv_data {
635 struct net_device *netdev;
636 struct platform_device *pdev;
637 struct device *dev;
638
639 /* XGMAC/XPCS related mmio registers */
640 void __iomem *xgmac_regs; /* XGMAC CSRs */
641 void __iomem *xpcs_regs; /* XPCS MMD registers */
642
643 /* Overall device lock */
644 spinlock_t lock;
645
646 /* XPCS indirect addressing mutex */
647 struct mutex xpcs_mutex;
648
5b9dfe29
LT		 649 /* RSS addressing mutex */
650 struct mutex rss_mutex;
651
9227dc5e
LT		 652 int dev_irq;
653 unsigned int per_channel_irq;
c5aa9e3b
LT		 654
655 struct xgbe_hw_if hw_if;
656 struct xgbe_desc_if desc_if;
657
cfa50c78
LT		 658 /* AXI DMA settings */
659 unsigned int axdomain;
660 unsigned int arcache;
661 unsigned int awcache;
662
c5aa9e3b
LT		 663 /* Rings for Tx/Rx on a DMA channel */
664 struct xgbe_channel *channel;
665 unsigned int channel_count;
666 unsigned int tx_ring_count;
667 unsigned int tx_desc_count;
668 unsigned int rx_ring_count;
669 unsigned int rx_desc_count;
670
853eb16b
LT		 671 unsigned int tx_q_count;
672 unsigned int rx_q_count;
673
c5aa9e3b
LT		 674 /* Tx/Rx common settings */
675 unsigned int pblx8;
676
677 /* Tx settings */
678 unsigned int tx_sf_mode;
679 unsigned int tx_threshold;
680 unsigned int tx_pbl;
681 unsigned int tx_osp_mode;
682
683 /* Rx settings */
684 unsigned int rx_sf_mode;
685 unsigned int rx_threshold;
686 unsigned int rx_pbl;
687
688 /* Tx coalescing settings */
689 unsigned int tx_usecs;
690 unsigned int tx_frames;
691
692 /* Rx coalescing settings */
693 unsigned int rx_riwt;
694 unsigned int rx_frames;
695
08dcc47c 696 /* Current Rx buffer size */
c5aa9e3b
LT		 697 unsigned int rx_buf_size;
698
699 /* Flow control settings */
700 unsigned int pause_autoneg;
701 unsigned int tx_pause;
702 unsigned int rx_pause;
703
5b9dfe29
LT		 704 /* Receive Side Scaling settings */
705 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
706 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
707 u32 rss_options;
708
c5aa9e3b
LT		 709 /* MDIO settings */
710 struct module *phy_module;
711 char *mii_bus_id;
712 struct mii_bus *mii;
713 int mdio_mmd;
714 struct phy_device *phydev;
715 int default_autoneg;
716 int default_speed;
717
718 /* Current PHY settings */
719 phy_interface_t phy_mode;
720 int phy_link;
721 int phy_speed;
722 unsigned int phy_tx_pause;
723 unsigned int phy_rx_pause;
724
725 /* Netdev related settings */
726 netdev_features_t netdev_features;
727 struct napi_struct napi;
728 struct xgbe_mmc_stats mmc_stats;
729
801c62d9
LT		 730 /* Filtering support */
731 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
732
23e4eef7
LT		 733 /* Device clocks */
734 struct clk *sysclk;
735 struct clk *ptpclk;
736
737 /* Timestamp support */
738 spinlock_t tstamp_lock;
739 struct ptp_clock_info ptp_clock_info;
740 struct ptp_clock *ptp_clock;
741 struct hwtstamp_config tstamp_config;
742 struct cyclecounter tstamp_cc;
743 struct timecounter tstamp_tc;
744 unsigned int tstamp_addend;
745 struct work_struct tx_tstamp_work;
746 struct sk_buff *tx_tstamp_skb;
747 u64 tx_tstamp;
c5aa9e3b 748
fca2d994
LT		 749 /* DCB support */
750 struct ieee_ets *ets;
751 struct ieee_pfc *pfc;
752 unsigned int q2tc_map[XGBE_MAX_QUEUES];
753 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
754
c5aa9e3b
LT		 755 /* Hardware features of the device */
756 struct xgbe_hw_features hw_feat;
757
758 /* Device restart work structure */
759 struct work_struct restart_work;
760
761 /* Keeps track of power mode */
762 unsigned int power_down;
763
764#ifdef CONFIG_DEBUG_FS
765 struct dentry *xgbe_debugfs;
766
767 unsigned int debugfs_xgmac_reg;
768
769 unsigned int debugfs_xpcs_mmd;
770 unsigned int debugfs_xpcs_reg;
771#endif
772};
773
774/* Function prototypes*/
775
776void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
777void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
778struct net_device_ops *xgbe_get_netdev_ops(void);
779struct ethtool_ops *xgbe_get_ethtool_ops(void);
fca2d994
LT		 780#ifdef CONFIG_AMD_XGBE_DCB
781const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
782#endif
c5aa9e3b
LT		 783
784int xgbe_mdio_register(struct xgbe_prv_data *);
785void xgbe_mdio_unregister(struct xgbe_prv_data *);
786void xgbe_dump_phy_registers(struct xgbe_prv_data *);
23e4eef7
LT		 787void xgbe_ptp_register(struct xgbe_prv_data *);
788void xgbe_ptp_unregister(struct xgbe_prv_data *);
c5aa9e3b
LT		 789void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
790 unsigned int);
791void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
792 unsigned int);
793void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
794void xgbe_get_all_hw_features(struct xgbe_prv_data *);
795int xgbe_powerup(struct net_device *, unsigned int);
796int xgbe_powerdown(struct net_device *, unsigned int);
797void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
798void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
799
800#ifdef CONFIG_DEBUG_FS
801void xgbe_debugfs_init(struct xgbe_prv_data *);
802void xgbe_debugfs_exit(struct xgbe_prv_data *);
803#else
804static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
805static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
806#endif /* CONFIG_DEBUG_FS */
807
808/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
809#if 0
810#define XGMAC_ENABLE_TX_DESC_DUMP
811#define XGMAC_ENABLE_RX_DESC_DUMP
812#endif
813
814/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
815#if 0
816#define XGMAC_ENABLE_TX_PKT_DUMP
817#define XGMAC_ENABLE_RX_PKT_DUMP
818#endif
819
820/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
821#if 0
822#define YDEBUG
823#define YDEBUG_MDIO
824#endif
825
826/* For debug prints */
827#ifdef YDEBUG
828#define DBGPR(x...) pr_alert(x)
829#define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
830#else
831#define DBGPR(x...) do { } while (0)
832#define DBGPHY_REGS(x...) do { } while (0)
833#endif
834
835#ifdef YDEBUG_MDIO
836#define DBGPR_MDIO(x...) pr_alert(x)
837#else
838#define DBGPR_MDIO(x...) do { } while (0)
839#endif
840
841#endif
Linux kernel - Deliverables
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