[deliverable/linux.git] / drivers / net / ethernet / apm / xgene / xgene_enet_hw.h

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Ravi Patel <rapatel@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __XGENE_ENET_HW_H__
#define __XGENE_ENET_HW_H__

#include "xgene_enet_main.h"

struct xgene_enet_pdata;
struct xgene_enet_stats;

/* clears and then set bits */
static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
{
	u32 end = start + len - 1;
	u32 mask = GENMASK(end, start);

	*dst &= ~mask;
	*dst |= (val << start) & mask;
}

static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
{
	return (val & GENMASK(end, start)) >> start;
}

enum xgene_enet_rm {
	RM0,
	RM3 = 3
};

#define CSR_RING_ID		0x0008
#define OVERWRITE		BIT(31)
#define IS_BUFFER_POOL		BIT(20)
#define PREFETCH_BUF_EN		BIT(21)
#define CSR_RING_ID_BUF		0x000c
#define CSR_RING_NE_INT_MODE	0x017c
#define CSR_RING_CONFIG		0x006c
#define CSR_RING_WR_BASE	0x0070
#define NUM_RING_CONFIG		5
#define BUFPOOL_MODE		3
#define INC_DEC_CMD_ADDR	0x002c
#define UDP_HDR_SIZE		2
#define BUF_LEN_CODE_2K		0x5000

#define CREATE_MASK(pos, len)		GENMASK((pos)+(len)-1, (pos))
#define CREATE_MASK_ULL(pos, len)	GENMASK_ULL((pos)+(len)-1, (pos))

/* Empty slot soft signature */
#define EMPTY_SLOT_INDEX	1
#define EMPTY_SLOT		~0ULL

#define WORK_DESC_SIZE		32
#define BUFPOOL_DESC_SIZE	16

#define RING_OWNER_MASK		GENMASK(9, 6)
#define RING_BUFNUM_MASK	GENMASK(5, 0)

#define SELTHRSH_POS		3
#define SELTHRSH_LEN		3
#define RINGADDRL_POS		5
#define RINGADDRL_LEN		27
#define RINGADDRH_POS		0
#define RINGADDRH_LEN		6
#define RINGSIZE_POS		23
#define RINGSIZE_LEN		3
#define RINGTYPE_POS		19
#define RINGTYPE_LEN		2
#define RINGMODE_POS		20
#define RINGMODE_LEN		3
#define RECOMTIMEOUTL_POS	28
#define RECOMTIMEOUTL_LEN	3
#define RECOMTIMEOUTH_POS	0
#define RECOMTIMEOUTH_LEN	2
#define NUMMSGSINQ_POS		1
#define NUMMSGSINQ_LEN		16
#define ACCEPTLERR		BIT(19)
#define QCOHERENT		BIT(4)
#define RECOMBBUF		BIT(27)

#define BLOCK_ETH_CSR_OFFSET		0x2000
#define BLOCK_ETH_RING_IF_OFFSET	0x9000
#define BLOCK_ETH_DIAG_CSR_OFFSET	0xD000

#define BLOCK_ETH_MAC_OFFSET		0x0000
#define BLOCK_ETH_MAC_CSR_OFFSET	0x2800

#define MAC_ADDR_REG_OFFSET		0x00
#define MAC_COMMAND_REG_OFFSET		0x04
#define MAC_WRITE_REG_OFFSET		0x08
#define MAC_READ_REG_OFFSET		0x0c
#define MAC_COMMAND_DONE_REG_OFFSET	0x10

#define MII_MGMT_CONFIG_ADDR		0x20
#define MII_MGMT_COMMAND_ADDR		0x24
#define MII_MGMT_ADDRESS_ADDR		0x28
#define MII_MGMT_CONTROL_ADDR		0x2c
#define MII_MGMT_STATUS_ADDR		0x30
#define MII_MGMT_INDICATORS_ADDR	0x34

#define BUSY_MASK			BIT(0)
#define READ_CYCLE_MASK			BIT(0)
#define PHY_CONTROL_SET(dst, val)	xgene_set_bits(dst, val, 0, 16)

#define ENET_SPARE_CFG_REG_ADDR		0x0750
#define RSIF_CONFIG_REG_ADDR		0x0010
#define RSIF_RAM_DBG_REG0_ADDR		0x0048
#define RGMII_REG_0_ADDR		0x07e0
#define CFG_LINK_AGGR_RESUME_0_ADDR	0x07c8
#define DEBUG_REG_ADDR			0x0700
#define CFG_BYPASS_ADDR			0x0294
#define CLE_BYPASS_REG0_0_ADDR		0x0490
#define CLE_BYPASS_REG1_0_ADDR		0x0494
#define CFG_RSIF_FPBUFF_TIMEOUT_EN	BIT(31)
#define RESUME_TX			BIT(0)
#define CFG_SPEED_1250			BIT(24)
#define TX_PORT0			BIT(0)
#define CFG_BYPASS_UNISEC_TX		BIT(2)
#define CFG_BYPASS_UNISEC_RX		BIT(1)
#define CFG_CLE_BYPASS_EN0		BIT(31)
#define CFG_TXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 29, 3)

#define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)
#define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)
#define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)
#define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)
#define CFG_WAITASYNCRD_SET(dst, val)		xgene_set_bits(dst, val, 0, 16)
#define ICM_CONFIG0_REG_0_ADDR		0x0400
#define ICM_CONFIG2_REG_0_ADDR		0x0410
#define RX_DV_GATE_REG_0_ADDR		0x05fc
#define TX_DV_GATE_EN0			BIT(2)
#define RX_DV_GATE_EN0			BIT(1)
#define RESUME_RX0			BIT(0)
#define ENET_CFGSSQMIWQASSOC_ADDR		0xe0
#define ENET_CFGSSQMIFPQASSOC_ADDR		0xdc
#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR	0xf0
#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR		0xf4
#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR		0x70
#define ENET_BLOCK_MEM_RDY_ADDR			0x74
#define MAC_CONFIG_1_ADDR			0x00
#define MAC_CONFIG_2_ADDR			0x04
#define MAX_FRAME_LEN_ADDR			0x10
#define INTERFACE_CONTROL_ADDR			0x38
#define STATION_ADDR0_ADDR			0x40
#define STATION_ADDR1_ADDR			0x44
#define PHY_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 8, 5)
#define REG_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 0, 5)
#define ENET_INTERFACE_MODE2_SET(dst, val)	xgene_set_bits(dst, val, 8, 2)
#define MGMT_CLOCK_SEL_SET(dst, val)		xgene_set_bits(dst, val, 0, 3)
#define SOFT_RESET1			BIT(31)
#define TX_EN				BIT(0)
#define RX_EN				BIT(2)
#define ENET_LHD_MODE			BIT(25)
#define ENET_GHD_MODE			BIT(26)
#define FULL_DUPLEX2			BIT(0)
#define SCAN_AUTO_INCR			BIT(5)
#define TBYT_ADDR			0x38
#define TPKT_ADDR			0x39
#define TDRP_ADDR			0x45
#define TFCS_ADDR			0x47
#define TUND_ADDR			0x4a

#define TSO_IPPROTO_TCP			1

#define USERINFO_POS			0
#define USERINFO_LEN			32
#define FPQNUM_POS			32
#define FPQNUM_LEN			12
#define LERR_POS			60
#define LERR_LEN			3
#define STASH_POS			52
#define STASH_LEN			2
#define BUFDATALEN_POS			48
#define BUFDATALEN_LEN			12
#define DATAADDR_POS			0
#define DATAADDR_LEN			42
#define COHERENT_POS			63
#define HENQNUM_POS			48
#define HENQNUM_LEN			12
#define TYPESEL_POS			44
#define TYPESEL_LEN			4
#define ETHHDR_POS			12
#define ETHHDR_LEN			8
#define IC_POS				35	/* Insert CRC */
#define TCPHDR_POS			0
#define TCPHDR_LEN			6
#define IPHDR_POS			6
#define IPHDR_LEN			6
#define EC_POS				22	/* Enable checksum */
#define EC_LEN				1
#define IS_POS				24	/* IP protocol select */
#define IS_LEN				1
#define TYPE_ETH_WORK_MESSAGE_POS	44

struct xgene_enet_raw_desc {
	__le64 m0;
	__le64 m1;
	__le64 m2;
	__le64 m3;
};

struct xgene_enet_raw_desc16 {
	__le64 m0;
	__le64 m1;
};

static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
{
	__le64 *desc_slot = desc_slot_ptr;

	desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
}

static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
{
	__le64 *desc_slot = desc_slot_ptr;

	return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
}

enum xgene_enet_ring_cfgsize {
	RING_CFGSIZE_512B,
	RING_CFGSIZE_2KB,
	RING_CFGSIZE_16KB,
	RING_CFGSIZE_64KB,
	RING_CFGSIZE_512KB,
	RING_CFGSIZE_INVALID
};

enum xgene_enet_ring_type {
	RING_DISABLED,
	RING_REGULAR,
	RING_BUFPOOL
};

enum xgene_ring_owner {
	RING_OWNER_ETH0,
	RING_OWNER_CPU = 15,
	RING_OWNER_INVALID
};

enum xgene_enet_ring_bufnum {
	RING_BUFNUM_REGULAR = 0x0,
	RING_BUFNUM_BUFPOOL = 0x20,
	RING_BUFNUM_INVALID
};

enum xgene_enet_cmd {
	XGENE_ENET_WR_CMD = BIT(31),
	XGENE_ENET_RD_CMD = BIT(30)
};

enum xgene_enet_err_code {
	HBF_READ_DATA = 3,
	HBF_LL_READ = 4,
	BAD_WORK_MSG = 6,
	BUFPOOL_TIMEOUT = 15,
	INGRESS_CRC = 16,
	INGRESS_CHECKSUM = 17,
	INGRESS_TRUNC_FRAME = 18,
	INGRESS_PKT_LEN = 19,
	INGRESS_PKT_UNDER = 20,
	INGRESS_FIFO_OVERRUN = 21,
	INGRESS_CHECKSUM_COMPUTE = 26,
	ERR_CODE_INVALID
};

static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
{
	return (id & RING_OWNER_MASK) >> 6;
}

static inline u8 xgene_enet_ring_bufnum(u16 id)
{
	return id & RING_BUFNUM_MASK;
}

static inline bool xgene_enet_is_bufpool(u16 id)
{
	return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
}

static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
{
	bool is_bufpool = xgene_enet_is_bufpool(id);

	return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
		      size / WORK_DESC_SIZE;
}

struct xgene_enet_desc_ring *xgene_enet_setup_ring(
		struct xgene_enet_desc_ring *ring);
void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring);
void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
			    struct xgene_enet_pdata *pdata,
			    enum xgene_enet_err_code status);

int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);

extern struct xgene_mac_ops xgene_gmac_ops;
extern struct xgene_port_ops xgene_gport_ops;

#endif /* __XGENE_ENET_HW_H__ */
Commit	Line	Data
e6ad7673 IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Ravi Patel <rapatel@apm.com>
	6	* Keyur Chudgar <kchudgar@apm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __XGENE_ENET_HW_H__
	23	#define __XGENE_ENET_HW_H__
	24
	25	#include "xgene_enet_main.h"
	26
	27	struct xgene_enet_pdata;
	28	struct xgene_enet_stats;
	29
	30	/* clears and then set bits */
	31	static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
	32	{
	33	u32 end = start + len - 1;
	34	u32 mask = GENMASK(end, start);
	35
	36	*dst &= ~mask;
	37	*dst \|= (val << start) & mask;
	38	}
	39
	40	static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
	41	{
	42	return (val & GENMASK(end, start)) >> start;
	43	}
	44
0148d38d IS	45	enum xgene_enet_rm {
	46	RM0,
	47	RM3 = 3
	48	};
	49
e6ad7673 IS	50	#define CSR_RING_ID 0x0008
	51	#define OVERWRITE BIT(31)
	52	#define IS_BUFFER_POOL BIT(20)
	53	#define PREFETCH_BUF_EN BIT(21)
	54	#define CSR_RING_ID_BUF 0x000c
	55	#define CSR_RING_NE_INT_MODE 0x017c
	56	#define CSR_RING_CONFIG 0x006c
	57	#define CSR_RING_WR_BASE 0x0070
	58	#define NUM_RING_CONFIG 5
	59	#define BUFPOOL_MODE 3
e6ad7673 IS	60	#define INC_DEC_CMD_ADDR 0x002c
	61	#define UDP_HDR_SIZE 2
	62	#define BUF_LEN_CODE_2K 0x5000
	63
	64	#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
	65	#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
	66
	67	/* Empty slot soft signature */
	68	#define EMPTY_SLOT_INDEX 1
	69	#define EMPTY_SLOT ~0ULL
	70
	71	#define WORK_DESC_SIZE 32
	72	#define BUFPOOL_DESC_SIZE 16
	73
	74	#define RING_OWNER_MASK GENMASK(9, 6)
	75	#define RING_BUFNUM_MASK GENMASK(5, 0)
	76
	77	#define SELTHRSH_POS 3
	78	#define SELTHRSH_LEN 3
	79	#define RINGADDRL_POS 5
	80	#define RINGADDRL_LEN 27
	81	#define RINGADDRH_POS 0
	82	#define RINGADDRH_LEN 6
	83	#define RINGSIZE_POS 23
	84	#define RINGSIZE_LEN 3
	85	#define RINGTYPE_POS 19
	86	#define RINGTYPE_LEN 2
	87	#define RINGMODE_POS 20
	88	#define RINGMODE_LEN 3
	89	#define RECOMTIMEOUTL_POS 28
	90	#define RECOMTIMEOUTL_LEN 3
	91	#define RECOMTIMEOUTH_POS 0
	92	#define RECOMTIMEOUTH_LEN 2
	93	#define NUMMSGSINQ_POS 1
	94	#define NUMMSGSINQ_LEN 16
	95	#define ACCEPTLERR BIT(19)
	96	#define QCOHERENT BIT(4)
	97	#define RECOMBBUF BIT(27)
	98
	99	#define BLOCK_ETH_CSR_OFFSET 0x2000
	100	#define BLOCK_ETH_RING_IF_OFFSET 0x9000
e6ad7673 IS	101	#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
	102
	103	#define BLOCK_ETH_MAC_OFFSET 0x0000
e6ad7673 IS	104	#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
	105
	106	#define MAC_ADDR_REG_OFFSET 0x00
	107	#define MAC_COMMAND_REG_OFFSET 0x04
	108	#define MAC_WRITE_REG_OFFSET 0x08
	109	#define MAC_READ_REG_OFFSET 0x0c
	110	#define MAC_COMMAND_DONE_REG_OFFSET 0x10
	111
e6ad7673 IS	112	#define MII_MGMT_CONFIG_ADDR 0x20
	113	#define MII_MGMT_COMMAND_ADDR 0x24
	114	#define MII_MGMT_ADDRESS_ADDR 0x28
	115	#define MII_MGMT_CONTROL_ADDR 0x2c
	116	#define MII_MGMT_STATUS_ADDR 0x30
	117	#define MII_MGMT_INDICATORS_ADDR 0x34
	118
	119	#define BUSY_MASK BIT(0)
	120	#define READ_CYCLE_MASK BIT(0)
	121	#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
	122
	123	#define ENET_SPARE_CFG_REG_ADDR 0x0750
	124	#define RSIF_CONFIG_REG_ADDR 0x0010
	125	#define RSIF_RAM_DBG_REG0_ADDR 0x0048
	126	#define RGMII_REG_0_ADDR 0x07e0
	127	#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
	128	#define DEBUG_REG_ADDR 0x0700
	129	#define CFG_BYPASS_ADDR 0x0294
	130	#define CLE_BYPASS_REG0_0_ADDR 0x0490
	131	#define CLE_BYPASS_REG1_0_ADDR 0x0494
	132	#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
	133	#define RESUME_TX BIT(0)
	134	#define CFG_SPEED_1250 BIT(24)
	135	#define TX_PORT0 BIT(0)
	136	#define CFG_BYPASS_UNISEC_TX BIT(2)
	137	#define CFG_BYPASS_UNISEC_RX BIT(1)
	138	#define CFG_CLE_BYPASS_EN0 BIT(31)
	139	#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
	140
	141	#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
	142	#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
	143	#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
	144	#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
	145	#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
	146	#define ICM_CONFIG0_REG_0_ADDR 0x0400
	147	#define ICM_CONFIG2_REG_0_ADDR 0x0410
	148	#define RX_DV_GATE_REG_0_ADDR 0x05fc
	149	#define TX_DV_GATE_EN0 BIT(2)
	150	#define RX_DV_GATE_EN0 BIT(1)
	151	#define RESUME_RX0 BIT(0)
	152	#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
	153	#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
	154	#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
	155	#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
	156	#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
	157	#define ENET_BLOCK_MEM_RDY_ADDR 0x74
	158	#define MAC_CONFIG_1_ADDR 0x00
	159	#define MAC_CONFIG_2_ADDR 0x04
	160	#define MAX_FRAME_LEN_ADDR 0x10
	161	#define INTERFACE_CONTROL_ADDR 0x38
	162	#define STATION_ADDR0_ADDR 0x40
	163	#define STATION_ADDR1_ADDR 0x44
	164	#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
	165	#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
	166	#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
	167	#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
	168	#define SOFT_RESET1 BIT(31)
	169	#define TX_EN BIT(0)
	170	#define RX_EN BIT(2)
	171	#define ENET_LHD_MODE BIT(25)
	172	#define ENET_GHD_MODE BIT(26)
	173	#define FULL_DUPLEX2 BIT(0)
	174	#define SCAN_AUTO_INCR BIT(5)
	175	#define TBYT_ADDR 0x38
176	#define TPKT_ADDR 0x39
177	#define TDRP_ADDR 0x45
178	#define TFCS_ADDR 0x47
179	#define TUND_ADDR 0x4a
180
181	#define TSO_IPPROTO_TCP 1
e6ad7673 IS	182
	183	#define USERINFO_POS 0
	184	#define USERINFO_LEN 32
	185	#define FPQNUM_POS 32
	186	#define FPQNUM_LEN 12
	187	#define LERR_POS 60
	188	#define LERR_LEN 3
	189	#define STASH_POS 52
	190	#define STASH_LEN 2
	191	#define BUFDATALEN_POS 48
	192	#define BUFDATALEN_LEN 12
	193	#define DATAADDR_POS 0
	194	#define DATAADDR_LEN 42
	195	#define COHERENT_POS 63
	196	#define HENQNUM_POS 48
	197	#define HENQNUM_LEN 12
	198	#define TYPESEL_POS 44
	199	#define TYPESEL_LEN 4
	200	#define ETHHDR_POS 12
	201	#define ETHHDR_LEN 8
	202	#define IC_POS 35 /* Insert CRC */
	203	#define TCPHDR_POS 0
	204	#define TCPHDR_LEN 6
	205	#define IPHDR_POS 6
	206	#define IPHDR_LEN 6
	207	#define EC_POS 22 /* Enable checksum */
	208	#define EC_LEN 1
	209	#define IS_POS 24 /* IP protocol select */
	210	#define IS_LEN 1
	211	#define TYPE_ETH_WORK_MESSAGE_POS 44
	212
	213	struct xgene_enet_raw_desc {
	214	__le64 m0;
	215	__le64 m1;
	216	__le64 m2;
	217	__le64 m3;
	218	};
	219
	220	struct xgene_enet_raw_desc16 {
	221	__le64 m0;
	222	__le64 m1;
	223	};
	224
	225	static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
	226	{
	227	__le64 *desc_slot = desc_slot_ptr;
	228
	229	desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
	230	}
	231
	232	static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
	233	{
	234	__le64 *desc_slot = desc_slot_ptr;
	235
	236	return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
	237	}
	238
	239	enum xgene_enet_ring_cfgsize {
	240	RING_CFGSIZE_512B,
	241	RING_CFGSIZE_2KB,
	242	RING_CFGSIZE_16KB,
	243	RING_CFGSIZE_64KB,
	244	RING_CFGSIZE_512KB,
	245	RING_CFGSIZE_INVALID
246	};
247
248	enum xgene_enet_ring_type {
249	RING_DISABLED,
250	RING_REGULAR,
251	RING_BUFPOOL
252	};
253
254	enum xgene_ring_owner {
255	RING_OWNER_ETH0,
256	RING_OWNER_CPU = 15,
257	RING_OWNER_INVALID
258	};
259
260	enum xgene_enet_ring_bufnum {
261	RING_BUFNUM_REGULAR = 0x0,
262	RING_BUFNUM_BUFPOOL = 0x20,
263	RING_BUFNUM_INVALID
264	};
265
266	enum xgene_enet_cmd {
267	XGENE_ENET_WR_CMD = BIT(31),
268	XGENE_ENET_RD_CMD = BIT(30)
269	};
270
271	enum xgene_enet_err_code {
272	HBF_READ_DATA = 3,
273	HBF_LL_READ = 4,
274	BAD_WORK_MSG = 6,
275	BUFPOOL_TIMEOUT = 15,
276	INGRESS_CRC = 16,
277	INGRESS_CHECKSUM = 17,
278	INGRESS_TRUNC_FRAME = 18,
279	INGRESS_PKT_LEN = 19,
280	INGRESS_PKT_UNDER = 20,
281	INGRESS_FIFO_OVERRUN = 21,
282	INGRESS_CHECKSUM_COMPUTE = 26,
283	ERR_CODE_INVALID
284	};
285
286	static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
287	{
288	return (id & RING_OWNER_MASK) >> 6;
289	}
290
291	static inline u8 xgene_enet_ring_bufnum(u16 id)
292	{
293	return id & RING_BUFNUM_MASK;
294	}
295
296	static inline bool xgene_enet_is_bufpool(u16 id)
297	{
298	return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
299	}
300
301	static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
302	{
303	bool is_bufpool = xgene_enet_is_bufpool(id);
304
305	return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
306	size / WORK_DESC_SIZE;
307	}
308
309	struct xgene_enet_desc_ring *xgene_enet_setup_ring(
310	struct xgene_enet_desc_ring *ring);
311	void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring);
312	void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
313	struct xgene_enet_pdata *pdata,
314	enum xgene_enet_err_code status);
315
e6ad7673 IS	316	int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
	317	void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
	318
d0eb7458 IS	319	extern struct xgene_mac_ops xgene_gmac_ops;
	320	extern struct xgene_port_ops xgene_gport_ops;
	321
e6ad7673	322	#endif /* __XGENE_ENET_HW_H__ */