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0148d38d IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Keyur Chudgar <kchudgar@apm.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "xgene_enet_main.h" | |
22 | #include "xgene_enet_hw.h" | |
23 | #include "xgene_enet_xgmac.h" | |
24 | ||
25 | static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, | |
26 | u32 offset, u32 val) | |
27 | { | |
28 | void __iomem *addr = pdata->eth_csr_addr + offset; | |
29 | ||
30 | iowrite32(val, addr); | |
31 | } | |
32 | ||
33 | static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, | |
34 | u32 offset, u32 val) | |
35 | { | |
36 | void __iomem *addr = pdata->eth_ring_if_addr + offset; | |
37 | ||
38 | iowrite32(val, addr); | |
39 | } | |
40 | ||
41 | static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, | |
42 | u32 offset, u32 val) | |
43 | { | |
44 | void __iomem *addr = pdata->eth_diag_csr_addr + offset; | |
45 | ||
46 | iowrite32(val, addr); | |
47 | } | |
48 | ||
49 | static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr, | |
50 | void __iomem *cmd, void __iomem *cmd_done, | |
51 | u32 wr_addr, u32 wr_data) | |
52 | { | |
53 | u32 done; | |
54 | u8 wait = 10; | |
55 | ||
56 | iowrite32(wr_addr, addr); | |
57 | iowrite32(wr_data, wr); | |
58 | iowrite32(XGENE_ENET_WR_CMD, cmd); | |
59 | ||
60 | /* wait for write command to complete */ | |
61 | while (!(done = ioread32(cmd_done)) && wait--) | |
62 | udelay(1); | |
63 | ||
64 | if (!done) | |
65 | return false; | |
66 | ||
67 | iowrite32(0, cmd); | |
68 | ||
69 | return true; | |
70 | } | |
71 | ||
72 | static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, | |
73 | u32 wr_addr, u32 wr_data) | |
74 | { | |
75 | void __iomem *addr, *wr, *cmd, *cmd_done; | |
76 | ||
77 | addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; | |
78 | wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; | |
79 | cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; | |
80 | cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; | |
81 | ||
82 | if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) | |
83 | netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", | |
84 | wr_addr); | |
85 | } | |
86 | ||
87 | static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, | |
88 | u32 offset, u32 *val) | |
89 | { | |
90 | void __iomem *addr = pdata->eth_csr_addr + offset; | |
91 | ||
92 | *val = ioread32(addr); | |
93 | } | |
94 | ||
95 | static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, | |
96 | u32 offset, u32 *val) | |
97 | { | |
98 | void __iomem *addr = pdata->eth_diag_csr_addr + offset; | |
99 | ||
100 | *val = ioread32(addr); | |
101 | } | |
102 | ||
103 | static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd, | |
104 | void __iomem *cmd, void __iomem *cmd_done, | |
105 | u32 rd_addr, u32 *rd_data) | |
106 | { | |
107 | u32 done; | |
108 | u8 wait = 10; | |
109 | ||
110 | iowrite32(rd_addr, addr); | |
111 | iowrite32(XGENE_ENET_RD_CMD, cmd); | |
112 | ||
113 | /* wait for read command to complete */ | |
114 | while (!(done = ioread32(cmd_done)) && wait--) | |
115 | udelay(1); | |
116 | ||
117 | if (!done) | |
118 | return false; | |
119 | ||
120 | *rd_data = ioread32(rd); | |
121 | iowrite32(0, cmd); | |
122 | ||
123 | return true; | |
124 | } | |
125 | ||
126 | static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, | |
127 | u32 rd_addr, u32 *rd_data) | |
128 | { | |
129 | void __iomem *addr, *rd, *cmd, *cmd_done; | |
130 | ||
131 | addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; | |
132 | rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; | |
133 | cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; | |
134 | cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; | |
135 | ||
136 | if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data)) | |
137 | netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", | |
138 | rd_addr); | |
139 | } | |
140 | ||
141 | static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) | |
142 | { | |
143 | struct net_device *ndev = pdata->ndev; | |
144 | u32 data; | |
145 | u8 wait = 10; | |
146 | ||
147 | xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); | |
148 | do { | |
149 | usleep_range(100, 110); | |
150 | xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); | |
151 | } while ((data != 0xffffffff) && wait--); | |
152 | ||
153 | if (data != 0xffffffff) { | |
154 | netdev_err(ndev, "Failed to release memory from shutdown\n"); | |
155 | return -ENODEV; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) | |
162 | { | |
163 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0); | |
164 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0); | |
165 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0); | |
166 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0); | |
167 | } | |
168 | ||
169 | static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata) | |
170 | { | |
171 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST); | |
172 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0); | |
173 | } | |
174 | ||
175 | static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata) | |
176 | { | |
177 | u32 addr0, addr1; | |
178 | u8 *dev_addr = pdata->ndev->dev_addr; | |
179 | ||
180 | addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
181 | (dev_addr[1] << 8) | dev_addr[0]; | |
182 | addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); | |
183 | ||
184 | xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0); | |
185 | xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1); | |
186 | } | |
187 | ||
188 | static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata) | |
189 | { | |
190 | u32 data; | |
191 | ||
192 | xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); | |
193 | ||
194 | return data; | |
195 | } | |
196 | ||
197 | static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) | |
198 | { | |
199 | u32 data; | |
200 | ||
201 | xgene_xgmac_reset(pdata); | |
202 | ||
203 | xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); | |
204 | data |= HSTPPEN; | |
205 | data &= ~HSTLENCHK; | |
206 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); | |
207 | ||
208 | xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600); | |
209 | xgene_xgmac_set_mac_addr(pdata); | |
210 | ||
211 | xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); | |
212 | data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; | |
213 | xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); | |
214 | ||
215 | xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX); | |
216 | xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0); | |
217 | xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); | |
218 | data |= BIT(12); | |
219 | xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); | |
220 | xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82); | |
221 | } | |
222 | ||
223 | static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata) | |
224 | { | |
225 | u32 data; | |
226 | ||
227 | xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); | |
228 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); | |
229 | } | |
230 | ||
231 | static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata) | |
232 | { | |
233 | u32 data; | |
234 | ||
235 | xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); | |
236 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN); | |
237 | } | |
238 | ||
239 | static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata) | |
240 | { | |
241 | u32 data; | |
242 | ||
243 | xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); | |
244 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN); | |
245 | } | |
246 | ||
247 | static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata) | |
248 | { | |
249 | u32 data; | |
250 | ||
251 | xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); | |
252 | xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN); | |
253 | } | |
254 | ||
c3f4465d | 255 | static int xgene_enet_reset(struct xgene_enet_pdata *pdata) |
0148d38d | 256 | { |
c3f4465d IS |
257 | if (!xgene_ring_mgr_init(pdata)) |
258 | return -ENODEV; | |
259 | ||
0148d38d IS |
260 | clk_prepare_enable(pdata->clk); |
261 | clk_disable_unprepare(pdata->clk); | |
262 | clk_prepare_enable(pdata->clk); | |
263 | ||
264 | xgene_enet_ecc_init(pdata); | |
265 | xgene_enet_config_ring_if_assoc(pdata); | |
c3f4465d IS |
266 | |
267 | return 0; | |
0148d38d IS |
268 | } |
269 | ||
270 | static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, | |
271 | u32 dst_ring_num, u16 bufpool_id) | |
272 | { | |
273 | u32 cb, fpsel; | |
274 | ||
275 | xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); | |
276 | cb |= CFG_CLE_BYPASS_EN0; | |
277 | CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); | |
278 | xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb); | |
279 | ||
280 | fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; | |
281 | xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); | |
282 | CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); | |
283 | CFG_CLE_FPSEL0_SET(&cb, fpsel); | |
284 | xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb); | |
285 | } | |
286 | ||
287 | static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) | |
288 | { | |
289 | clk_disable_unprepare(pdata->clk); | |
290 | } | |
291 | ||
dc8385f0 | 292 | static void xgene_enet_link_state(struct work_struct *work) |
0148d38d IS |
293 | { |
294 | struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work), | |
295 | struct xgene_enet_pdata, link_work); | |
296 | struct net_device *ndev = pdata->ndev; | |
297 | u32 link_status, poll_interval; | |
298 | ||
299 | link_status = xgene_enet_link_status(pdata); | |
300 | if (link_status) { | |
301 | if (!netif_carrier_ok(ndev)) { | |
302 | netif_carrier_on(ndev); | |
303 | xgene_xgmac_init(pdata); | |
304 | xgene_xgmac_rx_enable(pdata); | |
305 | xgene_xgmac_tx_enable(pdata); | |
306 | netdev_info(ndev, "Link is Up - 10Gbps\n"); | |
307 | } | |
308 | poll_interval = PHY_POLL_LINK_ON; | |
309 | } else { | |
310 | if (netif_carrier_ok(ndev)) { | |
311 | xgene_xgmac_rx_disable(pdata); | |
312 | xgene_xgmac_tx_disable(pdata); | |
313 | netif_carrier_off(ndev); | |
314 | netdev_info(ndev, "Link is Down\n"); | |
315 | } | |
316 | poll_interval = PHY_POLL_LINK_OFF; | |
317 | } | |
318 | ||
319 | schedule_delayed_work(&pdata->link_work, poll_interval); | |
320 | } | |
321 | ||
322 | struct xgene_mac_ops xgene_xgmac_ops = { | |
323 | .init = xgene_xgmac_init, | |
324 | .reset = xgene_xgmac_reset, | |
325 | .rx_enable = xgene_xgmac_rx_enable, | |
326 | .tx_enable = xgene_xgmac_tx_enable, | |
327 | .rx_disable = xgene_xgmac_rx_disable, | |
328 | .tx_disable = xgene_xgmac_tx_disable, | |
329 | .set_mac_addr = xgene_xgmac_set_mac_addr, | |
dc8385f0 | 330 | .link_state = xgene_enet_link_state |
0148d38d IS |
331 | }; |
332 | ||
333 | struct xgene_port_ops xgene_xgport_ops = { | |
334 | .reset = xgene_enet_reset, | |
335 | .cle_bypass = xgene_enet_xgcle_bypass, | |
336 | .shutdown = xgene_enet_shutdown, | |
337 | }; |