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[deliverable/linux.git] / drivers / net / ethernet / atheros / alx / main.c
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ab69bde6
JB		 1/*
2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
3 *
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * This file incorporates work covered by the following copyright and
18 * permission notice:
19 *
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
21 *
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
33 */
34
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/if_vlan.h>
41#include <linux/mdio.h>
42#include <linux/aer.h>
43#include <linux/bitops.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <net/ip6_checksum.h>
47#include <linux/crc32.h>
48#include "alx.h"
49#include "hw.h"
50#include "reg.h"
51
52const char alx_drv_name[] = "alx";
53
54
55static void alx_free_txbuf(struct alx_priv *alx, int entry)
56{
57 struct alx_buffer *txb = &alx->txq.bufs[entry];
58
59 if (dma_unmap_len(txb, size)) {
60 dma_unmap_single(&alx->hw.pdev->dev,
61 dma_unmap_addr(txb, dma),
62 dma_unmap_len(txb, size),
63 DMA_TO_DEVICE);
64 dma_unmap_len_set(txb, size, 0);
65 }
66
67 if (txb->skb) {
68 dev_kfree_skb_any(txb->skb);
69 txb->skb = NULL;
70 }
71}
72
73static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
74{
75 struct alx_rx_queue *rxq = &alx->rxq;
76 struct sk_buff *skb;
77 struct alx_buffer *cur_buf;
78 dma_addr_t dma;
79 u16 cur, next, count = 0;
80
81 next = cur = rxq->write_idx;
82 if (++next == alx->rx_ringsz)
83 next = 0;
84 cur_buf = &rxq->bufs[cur];
85
86 while (!cur_buf->skb && next != rxq->read_idx) {
87 struct alx_rfd *rfd = &rxq->rfd[cur];
88
89 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size, gfp);
90 if (!skb)
91 break;
92 dma = dma_map_single(&alx->hw.pdev->dev,
93 skb->data, alx->rxbuf_size,
94 DMA_FROM_DEVICE);
95 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
96 dev_kfree_skb(skb);
97 break;
98 }
99
100 /* Unfortunately, RX descriptor buffers must be 4-byte
101 * aligned, so we can't use IP alignment.
102 */
103 if (WARN_ON(dma & 3)) {
104 dev_kfree_skb(skb);
105 break;
106 }
107
108 cur_buf->skb = skb;
109 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
110 dma_unmap_addr_set(cur_buf, dma, dma);
111 rfd->addr = cpu_to_le64(dma);
112
113 cur = next;
114 if (++next == alx->rx_ringsz)
115 next = 0;
116 cur_buf = &rxq->bufs[cur];
117 count++;
118 }
119
120 if (count) {
121 /* flush all updates before updating hardware */
122 wmb();
123 rxq->write_idx = cur;
124 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
125 }
126
127 return count;
128}
129
130static inline int alx_tpd_avail(struct alx_priv *alx)
131{
132 struct alx_tx_queue *txq = &alx->txq;
133
134 if (txq->write_idx >= txq->read_idx)
135 return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
136 return txq->read_idx - txq->write_idx - 1;
137}
138
139static bool alx_clean_tx_irq(struct alx_priv *alx)
140{
141 struct alx_tx_queue *txq = &alx->txq;
142 u16 hw_read_idx, sw_read_idx;
143 unsigned int total_bytes = 0, total_packets = 0;
144 int budget = ALX_DEFAULT_TX_WORK;
145
146 sw_read_idx = txq->read_idx;
147 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
148
149 if (sw_read_idx != hw_read_idx) {
150 while (sw_read_idx != hw_read_idx && budget > 0) {
151 struct sk_buff *skb;
152
153 skb = txq->bufs[sw_read_idx].skb;
154 if (skb) {
155 total_bytes += skb->len;
156 total_packets++;
157 budget--;
158 }
159
160 alx_free_txbuf(alx, sw_read_idx);
161
162 if (++sw_read_idx == alx->tx_ringsz)
163 sw_read_idx = 0;
164 }
165 txq->read_idx = sw_read_idx;
166
167 netdev_completed_queue(alx->dev, total_packets, total_bytes);
168 }
169
170 if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
171 alx_tpd_avail(alx) > alx->tx_ringsz/4)
172 netif_wake_queue(alx->dev);
173
174 return sw_read_idx == hw_read_idx;
175}
176
177static void alx_schedule_link_check(struct alx_priv *alx)
178{
179 schedule_work(&alx->link_check_wk);
180}
181
182static void alx_schedule_reset(struct alx_priv *alx)
183{
184 schedule_work(&alx->reset_wk);
185}
186
7a05dc64 187static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
ab69bde6
JB		 188{
189 struct alx_rx_queue *rxq = &alx->rxq;
190 struct alx_rrd *rrd;
191 struct alx_buffer *rxb;
192 struct sk_buff *skb;
193 u16 length, rfd_cleaned = 0;
7a05dc64 194 int work = 0;
ab69bde6 195
7a05dc64 196 while (work < budget) {
ab69bde6
JB		 197 rrd = &rxq->rrd[rxq->rrd_read_idx];
198 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
199 break;
200 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
201
202 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
203 RRD_SI) != rxq->read_idx ||
204 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
205 RRD_NOR) != 1) {
206 alx_schedule_reset(alx);
7a05dc64 207 return work;
ab69bde6
JB		 208 }
209
210 rxb = &rxq->bufs[rxq->read_idx];
211 dma_unmap_single(&alx->hw.pdev->dev,
212 dma_unmap_addr(rxb, dma),
213 dma_unmap_len(rxb, size),
214 DMA_FROM_DEVICE);
215 dma_unmap_len_set(rxb, size, 0);
216 skb = rxb->skb;
217 rxb->skb = NULL;
218
219 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
220 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
221 rrd->word3 = 0;
222 dev_kfree_skb_any(skb);
223 goto next_pkt;
224 }
225
226 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
227 RRD_PKTLEN) - ETH_FCS_LEN;
228 skb_put(skb, length);
229 skb->protocol = eth_type_trans(skb, alx->dev);
230
231 skb_checksum_none_assert(skb);
232 if (alx->dev->features & NETIF_F_RXCSUM &&
233 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
234 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
235 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
236 RRD_PID)) {
237 case RRD_PID_IPV6UDP:
238 case RRD_PID_IPV4UDP:
239 case RRD_PID_IPV4TCP:
240 case RRD_PID_IPV6TCP:
241 skb->ip_summed = CHECKSUM_UNNECESSARY;
242 break;
243 }
244 }
245
246 napi_gro_receive(&alx->napi, skb);
7a05dc64 247 work++;
ab69bde6
JB		 248
249next_pkt:
250 if (++rxq->read_idx == alx->rx_ringsz)
251 rxq->read_idx = 0;
252 if (++rxq->rrd_read_idx == alx->rx_ringsz)
253 rxq->rrd_read_idx = 0;
254
255 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
256 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
257 }
258
259 if (rfd_cleaned)
260 alx_refill_rx_ring(alx, GFP_ATOMIC);
261
7a05dc64 262 return work;
ab69bde6
JB		 263}
264
265static int alx_poll(struct napi_struct *napi, int budget)
266{
267 struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
268 struct alx_hw *hw = &alx->hw;
ab69bde6 269 unsigned long flags;
7a05dc64
ED		 270 bool tx_complete;
271 int work;
ab69bde6 272
7a05dc64
ED		 273 tx_complete = alx_clean_tx_irq(alx);
274 work = alx_clean_rx_irq(alx, budget);
ab69bde6 275
7a05dc64
ED		 276 if (!tx_complete || work == budget)
277 return budget;
ab69bde6
JB		 278
279 napi_complete(&alx->napi);
280
281 /* enable interrupt */
282 spin_lock_irqsave(&alx->irq_lock, flags);
283 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
284 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
285 spin_unlock_irqrestore(&alx->irq_lock, flags);
286
287 alx_post_write(hw);
288
7a05dc64 289 return work;
ab69bde6
JB		 290}
291
292static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
293{
294 struct alx_hw *hw = &alx->hw;
295 bool write_int_mask = false;
296
297 spin_lock(&alx->irq_lock);
298
299 /* ACK interrupt */
300 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
301 intr &= alx->int_mask;
302
303 if (intr & ALX_ISR_FATAL) {
304 netif_warn(alx, hw, alx->dev,
305 "fatal interrupt 0x%x, resetting\n", intr);
306 alx_schedule_reset(alx);
307 goto out;
308 }
309
310 if (intr & ALX_ISR_ALERT)
311 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
312
313 if (intr & ALX_ISR_PHY) {
314 /* suppress PHY interrupt, because the source
315 * is from PHY internal. only the internal status
316 * is cleared, the interrupt status could be cleared.
317 */
318 alx->int_mask &= ~ALX_ISR_PHY;
319 write_int_mask = true;
320 alx_schedule_link_check(alx);
321 }
322
323 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
324 napi_schedule(&alx->napi);
325 /* mask rx/tx interrupt, enable them when napi complete */
326 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
327 write_int_mask = true;
328 }
329
330 if (write_int_mask)
331 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
332
333 alx_write_mem32(hw, ALX_ISR, 0);
334
335 out:
336 spin_unlock(&alx->irq_lock);
337 return IRQ_HANDLED;
338}
339
340static irqreturn_t alx_intr_msi(int irq, void *data)
341{
342 struct alx_priv *alx = data;
343
344 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
345}
346
347static irqreturn_t alx_intr_legacy(int irq, void *data)
348{
349 struct alx_priv *alx = data;
350 struct alx_hw *hw = &alx->hw;
351 u32 intr;
352
353 intr = alx_read_mem32(hw, ALX_ISR);
354
355 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
356 return IRQ_NONE;
357
358 return alx_intr_handle(alx, intr);
359}
360
361static void alx_init_ring_ptrs(struct alx_priv *alx)
362{
363 struct alx_hw *hw = &alx->hw;
364 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
365
366 alx->rxq.read_idx = 0;
367 alx->rxq.write_idx = 0;
368 alx->rxq.rrd_read_idx = 0;
369 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
370 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
371 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
372 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
373 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
374 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
375
376 alx->txq.read_idx = 0;
377 alx->txq.write_idx = 0;
378 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
379 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
380 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
381
382 /* load these pointers into the chip */
383 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
384}
385
386static void alx_free_txring_buf(struct alx_priv *alx)
387{
388 struct alx_tx_queue *txq = &alx->txq;
389 int i;
390
391 if (!txq->bufs)
392 return;
393
394 for (i = 0; i < alx->tx_ringsz; i++)
395 alx_free_txbuf(alx, i);
396
397 memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
398 memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
399 txq->write_idx = 0;
400 txq->read_idx = 0;
401
402 netdev_reset_queue(alx->dev);
403}
404
405static void alx_free_rxring_buf(struct alx_priv *alx)
406{
407 struct alx_rx_queue *rxq = &alx->rxq;
408 struct alx_buffer *cur_buf;
409 u16 i;
410
411 if (rxq == NULL)
412 return;
413
414 for (i = 0; i < alx->rx_ringsz; i++) {
415 cur_buf = rxq->bufs + i;
416 if (cur_buf->skb) {
417 dma_unmap_single(&alx->hw.pdev->dev,
418 dma_unmap_addr(cur_buf, dma),
419 dma_unmap_len(cur_buf, size),
420 DMA_FROM_DEVICE);
421 dev_kfree_skb(cur_buf->skb);
422 cur_buf->skb = NULL;
423 dma_unmap_len_set(cur_buf, size, 0);
424 dma_unmap_addr_set(cur_buf, dma, 0);
425 }
426 }
427
428 rxq->write_idx = 0;
429 rxq->read_idx = 0;
430 rxq->rrd_read_idx = 0;
431}
432
433static void alx_free_buffers(struct alx_priv *alx)
434{
435 alx_free_txring_buf(alx);
436 alx_free_rxring_buf(alx);
437}
438
439static int alx_reinit_rings(struct alx_priv *alx)
440{
441 alx_free_buffers(alx);
442
443 alx_init_ring_ptrs(alx);
444
445 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
446 return -ENOMEM;
447
448 return 0;
449}
450
451static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
452{
453 u32 crc32, bit, reg;
454
455 crc32 = ether_crc(ETH_ALEN, addr);
456 reg = (crc32 >> 31) & 0x1;
457 bit = (crc32 >> 26) & 0x1F;
458
459 mc_hash[reg] |= BIT(bit);
460}
461
462static void __alx_set_rx_mode(struct net_device *netdev)
463{
464 struct alx_priv *alx = netdev_priv(netdev);
465 struct alx_hw *hw = &alx->hw;
466 struct netdev_hw_addr *ha;
467 u32 mc_hash[2] = {};
468
469 if (!(netdev->flags & IFF_ALLMULTI)) {
470 netdev_for_each_mc_addr(ha, netdev)
471 alx_add_mc_addr(hw, ha->addr, mc_hash);
472
473 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
474 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
475 }
476
477 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
478 if (netdev->flags & IFF_PROMISC)
479 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
480 if (netdev->flags & IFF_ALLMULTI)
481 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
482
483 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
484}
485
486static void alx_set_rx_mode(struct net_device *netdev)
487{
488 __alx_set_rx_mode(netdev);
489}
490
491static int alx_set_mac_address(struct net_device *netdev, void *data)
492{
493 struct alx_priv *alx = netdev_priv(netdev);
494 struct alx_hw *hw = &alx->hw;
495 struct sockaddr *addr = data;
496
497 if (!is_valid_ether_addr(addr->sa_data))
498 return -EADDRNOTAVAIL;
499
500 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
501 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
502
503 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
504 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
505 alx_set_macaddr(hw, hw->mac_addr);
506
507 return 0;
508}
509
510static int alx_alloc_descriptors(struct alx_priv *alx)
511{
512 alx->txq.bufs = kcalloc(alx->tx_ringsz,
513 sizeof(struct alx_buffer),
514 GFP_KERNEL);
515 if (!alx->txq.bufs)
516 return -ENOMEM;
517
518 alx->rxq.bufs = kcalloc(alx->rx_ringsz,
519 sizeof(struct alx_buffer),
520 GFP_KERNEL);
521 if (!alx->rxq.bufs)
522 goto out_free;
523
524 /* physical tx/rx ring descriptors
525 *
526 * Allocate them as a single chunk because they must not cross a
527 * 4G boundary (hardware has a single register for high 32 bits
528 * of addresses only)
529 */
530 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
531 sizeof(struct alx_rrd) * alx->rx_ringsz +
532 sizeof(struct alx_rfd) * alx->rx_ringsz;
533 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
534 alx->descmem.size,
535 &alx->descmem.dma,
536 GFP_KERNEL);
537 if (!alx->descmem.virt)
538 goto out_free;
539
60f40107 540 alx->txq.tpd = alx->descmem.virt;
ab69bde6
JB		 541 alx->txq.tpd_dma = alx->descmem.dma;
542
543 /* alignment requirement for next block */
544 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
545
546 alx->rxq.rrd =
547 (void *)((u8 *)alx->descmem.virt +
548 sizeof(struct alx_txd) * alx->tx_ringsz);
549 alx->rxq.rrd_dma = alx->descmem.dma +
550 sizeof(struct alx_txd) * alx->tx_ringsz;
551
552 /* alignment requirement for next block */
553 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
554
555 alx->rxq.rfd =
556 (void *)((u8 *)alx->descmem.virt +
557 sizeof(struct alx_txd) * alx->tx_ringsz +
558 sizeof(struct alx_rrd) * alx->rx_ringsz);
559 alx->rxq.rfd_dma = alx->descmem.dma +
560 sizeof(struct alx_txd) * alx->tx_ringsz +
561 sizeof(struct alx_rrd) * alx->rx_ringsz;
562
563 return 0;
564out_free:
565 kfree(alx->txq.bufs);
566 kfree(alx->rxq.bufs);
567 return -ENOMEM;
568}
569
570static int alx_alloc_rings(struct alx_priv *alx)
571{
572 int err;
573
574 err = alx_alloc_descriptors(alx);
575 if (err)
576 return err;
577
578 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
579 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
580 alx->tx_ringsz = alx->tx_ringsz;
581
582 netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
583
584 alx_reinit_rings(alx);
585 return 0;
586}
587
588static void alx_free_rings(struct alx_priv *alx)
589{
590 netif_napi_del(&alx->napi);
591 alx_free_buffers(alx);
592
593 kfree(alx->txq.bufs);
594 kfree(alx->rxq.bufs);
595
596 dma_free_coherent(&alx->hw.pdev->dev,
597 alx->descmem.size,
598 alx->descmem.virt,
599 alx->descmem.dma);
600}
601
602static void alx_config_vector_mapping(struct alx_priv *alx)
603{
604 struct alx_hw *hw = &alx->hw;
605
606 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
607 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
608 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
609}
610
611static void alx_irq_enable(struct alx_priv *alx)
612{
613 struct alx_hw *hw = &alx->hw;
614
615 /* level-1 interrupt switch */
616 alx_write_mem32(hw, ALX_ISR, 0);
617 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
618 alx_post_write(hw);
619}
620
621static void alx_irq_disable(struct alx_priv *alx)
622{
623 struct alx_hw *hw = &alx->hw;
624
625 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
626 alx_write_mem32(hw, ALX_IMR, 0);
627 alx_post_write(hw);
628
629 synchronize_irq(alx->hw.pdev->irq);
630}
631
632static int alx_request_irq(struct alx_priv *alx)
633{
634 struct pci_dev *pdev = alx->hw.pdev;
635 struct alx_hw *hw = &alx->hw;
636 int err;
637 u32 msi_ctrl;
638
639 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
640
641 if (!pci_enable_msi(alx->hw.pdev)) {
642 alx->msi = true;
643
644 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
645 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
646 err = request_irq(pdev->irq, alx_intr_msi, 0,
647 alx->dev->name, alx);
648 if (!err)
649 goto out;
650 /* fall back to legacy interrupt */
651 pci_disable_msi(alx->hw.pdev);
652 }
653
654 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
655 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
656 alx->dev->name, alx);
657out:
658 if (!err)
659 alx_config_vector_mapping(alx);
660 return err;
661}
662
663static void alx_free_irq(struct alx_priv *alx)
664{
665 struct pci_dev *pdev = alx->hw.pdev;
666
667 free_irq(pdev->irq, alx);
668
669 if (alx->msi) {
670 pci_disable_msi(alx->hw.pdev);
671 alx->msi = false;
672 }
673}
674
675static int alx_identify_hw(struct alx_priv *alx)
676{
677 struct alx_hw *hw = &alx->hw;
678 int rev = alx_hw_revision(hw);
679
680 if (rev > ALX_REV_C0)
681 return -EINVAL;
682
683 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
684
685 return 0;
686}
687
688static int alx_init_sw(struct alx_priv *alx)
689{
690 struct pci_dev *pdev = alx->hw.pdev;
691 struct alx_hw *hw = &alx->hw;
692 int err;
693
694 err = alx_identify_hw(alx);
695 if (err) {
696 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
697 return err;
698 }
699
700 alx->hw.lnk_patch =
701 pdev->device == ALX_DEV_ID_AR8161 &&
702 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
703 pdev->subsystem_device == 0x0091 &&
704 pdev->revision == 0;
705
706 hw->smb_timer = 400;
707 hw->mtu = alx->dev->mtu;
708 alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8);
709 alx->tx_ringsz = 256;
710 alx->rx_ringsz = 512;
ab69bde6
JB		 711 hw->imt = 200;
712 alx->int_mask = ALX_ISR_MISC;
713 hw->dma_chnl = hw->max_dma_chnl;
714 hw->ith_tpd = alx->tx_ringsz / 3;
715 hw->link_speed = SPEED_UNKNOWN;
a5b87cc9 716 hw->duplex = DUPLEX_UNKNOWN;
ab69bde6
JB		 717 hw->adv_cfg = ADVERTISED_Autoneg |
718 ADVERTISED_10baseT_Half |
719 ADVERTISED_10baseT_Full |
720 ADVERTISED_100baseT_Full |
721 ADVERTISED_100baseT_Half |
722 ADVERTISED_1000baseT_Full;
723 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
724
725 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
726 ALX_MAC_CTRL_MHASH_ALG_HI5B |
727 ALX_MAC_CTRL_BRD_EN |
728 ALX_MAC_CTRL_PCRCE |
729 ALX_MAC_CTRL_CRCE |
730 ALX_MAC_CTRL_RXFC_EN |
731 ALX_MAC_CTRL_TXFC_EN |
732 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
733
734 return err;
735}
736
737
738static netdev_features_t alx_fix_features(struct net_device *netdev,
739 netdev_features_t features)
740{
741 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
742 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
743
744 return features;
745}
746
747static void alx_netif_stop(struct alx_priv *alx)
748{
749 alx->dev->trans_start = jiffies;
750 if (netif_carrier_ok(alx->dev)) {
751 netif_carrier_off(alx->dev);
752 netif_tx_disable(alx->dev);
753 napi_disable(&alx->napi);
754 }
755}
756
757static void alx_halt(struct alx_priv *alx)
758{
759 struct alx_hw *hw = &alx->hw;
760
761 alx_netif_stop(alx);
762 hw->link_speed = SPEED_UNKNOWN;
a5b87cc9 763 hw->duplex = DUPLEX_UNKNOWN;
ab69bde6
JB		 764
765 alx_reset_mac(hw);
766
767 /* disable l0s/l1 */
768 alx_enable_aspm(hw, false, false);
769 alx_irq_disable(alx);
770 alx_free_buffers(alx);
771}
772
773static void alx_configure(struct alx_priv *alx)
774{
775 struct alx_hw *hw = &alx->hw;
776
777 alx_configure_basic(hw);
778 alx_disable_rss(hw);
779 __alx_set_rx_mode(alx->dev);
780
781 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
782}
783
784static void alx_activate(struct alx_priv *alx)
785{
786 /* hardware setting lost, restore it */
787 alx_reinit_rings(alx);
788 alx_configure(alx);
789
790 /* clear old interrupts */
791 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
792
793 alx_irq_enable(alx);
794
795 alx_schedule_link_check(alx);
796}
797
798static void alx_reinit(struct alx_priv *alx)
799{
800 ASSERT_RTNL();
801
802 alx_halt(alx);
803 alx_activate(alx);
804}
805
806static int alx_change_mtu(struct net_device *netdev, int mtu)
807{
808 struct alx_priv *alx = netdev_priv(netdev);
809 int max_frame = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
810
811 if ((max_frame < ALX_MIN_FRAME_SIZE) ||
812 (max_frame > ALX_MAX_FRAME_SIZE))
813 return -EINVAL;
814
815 if (netdev->mtu == mtu)
816 return 0;
817
818 netdev->mtu = mtu;
819 alx->hw.mtu = mtu;
820 alx->rxbuf_size = mtu > ALX_DEF_RXBUF_SIZE ?
821 ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE;
822 netdev_update_features(netdev);
823 if (netif_running(netdev))
824 alx_reinit(alx);
825 return 0;
826}
827
828static void alx_netif_start(struct alx_priv *alx)
829{
830 netif_tx_wake_all_queues(alx->dev);
831 napi_enable(&alx->napi);
832 netif_carrier_on(alx->dev);
833}
834
835static int __alx_open(struct alx_priv *alx, bool resume)
836{
837 int err;
838
839 if (!resume)
840 netif_carrier_off(alx->dev);
841
842 err = alx_alloc_rings(alx);
843 if (err)
844 return err;
845
846 alx_configure(alx);
847
848 err = alx_request_irq(alx);
849 if (err)
850 goto out_free_rings;
851
852 /* clear old interrupts */
853 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
854
855 alx_irq_enable(alx);
856
857 if (!resume)
858 netif_tx_start_all_queues(alx->dev);
859
860 alx_schedule_link_check(alx);
861 return 0;
862
863out_free_rings:
864 alx_free_rings(alx);
865 return err;
866}
867
868static void __alx_stop(struct alx_priv *alx)
869{
870 alx_halt(alx);
871 alx_free_irq(alx);
872 alx_free_rings(alx);
873}
874
a5b87cc9 875static const char *alx_speed_desc(struct alx_hw *hw)
ab69bde6 876{
a5b87cc9
JB		 877 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
878 case ADVERTISED_1000baseT_Full:
ab69bde6 879 return "1 Gbps Full";
a5b87cc9 880 case ADVERTISED_100baseT_Full:
ab69bde6 881 return "100 Mbps Full";
a5b87cc9 882 case ADVERTISED_100baseT_Half:
ab69bde6 883 return "100 Mbps Half";
a5b87cc9 884 case ADVERTISED_10baseT_Full:
ab69bde6 885 return "10 Mbps Full";
a5b87cc9 886 case ADVERTISED_10baseT_Half:
ab69bde6
JB		 887 return "10 Mbps Half";
888 default:
889 return "Unknown speed";
890 }
891}
892
893static void alx_check_link(struct alx_priv *alx)
894{
895 struct alx_hw *hw = &alx->hw;
896 unsigned long flags;
a5b87cc9
JB		 897 int old_speed;
898 u8 old_duplex;
ab69bde6
JB		 899 int err;
900
901 /* clear PHY internal interrupt status, otherwise the main
902 * interrupt status will be asserted forever
903 */
904 alx_clear_phy_intr(hw);
905
a5b87cc9
JB		 906 old_speed = hw->link_speed;
907 old_duplex = hw->duplex;
908 err = alx_read_phy_link(hw);
ab69bde6
JB		 909 if (err < 0)
910 goto reset;
911
912 spin_lock_irqsave(&alx->irq_lock, flags);
913 alx->int_mask |= ALX_ISR_PHY;
914 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
915 spin_unlock_irqrestore(&alx->irq_lock, flags);
916
a5b87cc9 917 if (old_speed == hw->link_speed)
ab69bde6 918 return;
ab69bde6 919
a5b87cc9 920 if (hw->link_speed != SPEED_UNKNOWN) {
ab69bde6 921 netif_info(alx, link, alx->dev,
a5b87cc9 922 "NIC Up: %s\n", alx_speed_desc(hw));
ab69bde6
JB		 923 alx_post_phy_link(hw);
924 alx_enable_aspm(hw, true, true);
925 alx_start_mac(hw);
926
927 if (old_speed == SPEED_UNKNOWN)
928 alx_netif_start(alx);
929 } else {
930 /* link is now down */
931 alx_netif_stop(alx);
932 netif_info(alx, link, alx->dev, "Link Down\n");
933 err = alx_reset_mac(hw);
934 if (err)
935 goto reset;
936 alx_irq_disable(alx);
937
938 /* MAC reset causes all HW settings to be lost, restore all */
939 err = alx_reinit_rings(alx);
940 if (err)
941 goto reset;
942 alx_configure(alx);
943 alx_enable_aspm(hw, false, true);
944 alx_post_phy_link(hw);
945 alx_irq_enable(alx);
946 }
947
948 return;
949
950reset:
951 alx_schedule_reset(alx);
952}
953
954static int alx_open(struct net_device *netdev)
955{
956 return __alx_open(netdev_priv(netdev), false);
957}
958
959static int alx_stop(struct net_device *netdev)
960{
961 __alx_stop(netdev_priv(netdev));
962 return 0;
963}
964
ab69bde6
JB		 965static void alx_link_check(struct work_struct *work)
966{
967 struct alx_priv *alx;
968
969 alx = container_of(work, struct alx_priv, link_check_wk);
970
971 rtnl_lock();
972 alx_check_link(alx);
973 rtnl_unlock();
974}
975
976static void alx_reset(struct work_struct *work)
977{
978 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
979
980 rtnl_lock();
981 alx_reinit(alx);
982 rtnl_unlock();
983}
984
985static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
986{
987 u8 cso, css;
988
989 if (skb->ip_summed != CHECKSUM_PARTIAL)
990 return 0;
991
992 cso = skb_checksum_start_offset(skb);
993 if (cso & 1)
994 return -EINVAL;
995
996 css = cso + skb->csum_offset;
997 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
998 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
999 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1000
1001 return 0;
1002}
1003
1004static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
1005{
1006 struct alx_tx_queue *txq = &alx->txq;
1007 struct alx_txd *tpd, *first_tpd;
1008 dma_addr_t dma;
1009 int maplen, f, first_idx = txq->write_idx;
1010
1011 first_tpd = &txq->tpd[txq->write_idx];
1012 tpd = first_tpd;
1013
1014 maplen = skb_headlen(skb);
1015 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
1016 DMA_TO_DEVICE);
1017 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1018 goto err_dma;
1019
1020 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1021 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1022
1023 tpd->adrl.addr = cpu_to_le64(dma);
1024 tpd->len = cpu_to_le16(maplen);
1025
1026 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1027 struct skb_frag_struct *frag;
1028
1029 frag = &skb_shinfo(skb)->frags[f];
1030
1031 if (++txq->write_idx == alx->tx_ringsz)
1032 txq->write_idx = 0;
1033 tpd = &txq->tpd[txq->write_idx];
1034
1035 tpd->word1 = first_tpd->word1;
1036
1037 maplen = skb_frag_size(frag);
1038 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
1039 maplen, DMA_TO_DEVICE);
1040 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1041 goto err_dma;
1042 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1043 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1044
1045 tpd->adrl.addr = cpu_to_le64(dma);
1046 tpd->len = cpu_to_le16(maplen);
1047 }
1048
1049 /* last TPD, set EOP flag and store skb */
1050 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1051 txq->bufs[txq->write_idx].skb = skb;
1052
1053 if (++txq->write_idx == alx->tx_ringsz)
1054 txq->write_idx = 0;
1055
1056 return 0;
1057
1058err_dma:
1059 f = first_idx;
1060 while (f != txq->write_idx) {
1061 alx_free_txbuf(alx, f);
1062 if (++f == alx->tx_ringsz)
1063 f = 0;
1064 }
1065 return -ENOMEM;
1066}
1067
1068static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1069 struct net_device *netdev)
1070{
1071 struct alx_priv *alx = netdev_priv(netdev);
1072 struct alx_tx_queue *txq = &alx->txq;
1073 struct alx_txd *first;
1074 int tpdreq = skb_shinfo(skb)->nr_frags + 1;
1075
1076 if (alx_tpd_avail(alx) < tpdreq) {
1077 netif_stop_queue(alx->dev);
1078 goto drop;
1079 }
1080
1081 first = &txq->tpd[txq->write_idx];
1082 memset(first, 0, sizeof(*first));
1083
1084 if (alx_tx_csum(skb, first))
1085 goto drop;
1086
1087 if (alx_map_tx_skb(alx, skb) < 0)
1088 goto drop;
1089
1090 netdev_sent_queue(alx->dev, skb->len);
1091
1092 /* flush updates before updating hardware */
1093 wmb();
1094 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
1095
1096 if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
1097 netif_stop_queue(alx->dev);
1098
1099 return NETDEV_TX_OK;
1100
1101drop:
548ff1ed 1102 dev_kfree_skb_any(skb);
ab69bde6
JB		 1103 return NETDEV_TX_OK;
1104}
1105
1106static void alx_tx_timeout(struct net_device *dev)
1107{
1108 struct alx_priv *alx = netdev_priv(dev);
1109
1110 alx_schedule_reset(alx);
1111}
1112
1113static int alx_mdio_read(struct net_device *netdev,
1114 int prtad, int devad, u16 addr)
1115{
1116 struct alx_priv *alx = netdev_priv(netdev);
1117 struct alx_hw *hw = &alx->hw;
1118 u16 val;
1119 int err;
1120
1121 if (prtad != hw->mdio.prtad)
1122 return -EINVAL;
1123
1124 if (devad == MDIO_DEVAD_NONE)
1125 err = alx_read_phy_reg(hw, addr, &val);
1126 else
1127 err = alx_read_phy_ext(hw, devad, addr, &val);
1128
1129 if (err)
1130 return err;
1131 return val;
1132}
1133
1134static int alx_mdio_write(struct net_device *netdev,
1135 int prtad, int devad, u16 addr, u16 val)
1136{
1137 struct alx_priv *alx = netdev_priv(netdev);
1138 struct alx_hw *hw = &alx->hw;
1139
1140 if (prtad != hw->mdio.prtad)
1141 return -EINVAL;
1142
1143 if (devad == MDIO_DEVAD_NONE)
1144 return alx_write_phy_reg(hw, addr, val);
1145
1146 return alx_write_phy_ext(hw, devad, addr, val);
1147}
1148
1149static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1150{
1151 struct alx_priv *alx = netdev_priv(netdev);
1152
1153 if (!netif_running(netdev))
1154 return -EAGAIN;
1155
1156 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1157}
1158
1159#ifdef CONFIG_NET_POLL_CONTROLLER
1160static void alx_poll_controller(struct net_device *netdev)
1161{
1162 struct alx_priv *alx = netdev_priv(netdev);
1163
1164 if (alx->msi)
1165 alx_intr_msi(0, alx);
1166 else
1167 alx_intr_legacy(0, alx);
1168}
1169#endif
1170
f1b6b106
SD		 1171static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
1172 struct rtnl_link_stats64 *net_stats)
1173{
1174 struct alx_priv *alx = netdev_priv(dev);
1175 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1176
1177 spin_lock(&alx->stats_lock);
1178
1179 alx_update_hw_stats(&alx->hw);
1180
1181 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1182 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1183 net_stats->multicast = hw_stats->rx_mcast;
1184 net_stats->collisions = hw_stats->tx_single_col +
1185 hw_stats->tx_multi_col +
1186 hw_stats->tx_late_col +
1187 hw_stats->tx_abort_col;
1188
1189 net_stats->rx_errors = hw_stats->rx_frag +
1190 hw_stats->rx_fcs_err +
1191 hw_stats->rx_len_err +
1192 hw_stats->rx_ov_sz +
1193 hw_stats->rx_ov_rrd +
1194 hw_stats->rx_align_err +
1195 hw_stats->rx_ov_rxf;
1196
1197 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1198 net_stats->rx_length_errors = hw_stats->rx_len_err;
1199 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1200 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1201 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1202
1203 net_stats->tx_errors = hw_stats->tx_late_col +
1204 hw_stats->tx_abort_col +
1205 hw_stats->tx_underrun +
1206 hw_stats->tx_trunc;
1207
1208 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1209 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1210 net_stats->tx_window_errors = hw_stats->tx_late_col;
1211
1212 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1213 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1214
1215 spin_unlock(&alx->stats_lock);
1216
1217 return net_stats;
1218}
1219
ab69bde6
JB		 1220static const struct net_device_ops alx_netdev_ops = {
1221 .ndo_open = alx_open,
1222 .ndo_stop = alx_stop,
1223 .ndo_start_xmit = alx_start_xmit,
f1b6b106 1224 .ndo_get_stats64 = alx_get_stats64,
ab69bde6
JB		 1225 .ndo_set_rx_mode = alx_set_rx_mode,
1226 .ndo_validate_addr = eth_validate_addr,
1227 .ndo_set_mac_address = alx_set_mac_address,
1228 .ndo_change_mtu = alx_change_mtu,
1229 .ndo_do_ioctl = alx_ioctl,
1230 .ndo_tx_timeout = alx_tx_timeout,
1231 .ndo_fix_features = alx_fix_features,
1232#ifdef CONFIG_NET_POLL_CONTROLLER
1233 .ndo_poll_controller = alx_poll_controller,
1234#endif
1235};
1236
1237static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1238{
1239 struct net_device *netdev;
1240 struct alx_priv *alx;
1241 struct alx_hw *hw;
1242 bool phy_configured;
c3eb7a77 1243 int bars, err;
ab69bde6
JB		 1244
1245 err = pci_enable_device_mem(pdev);
1246 if (err)
1247 return err;
1248
1249 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1250 * shared register for the high 32 bits, so only a single, aligned,
1251 * 4 GB physical address range can be used for descriptors.
1252 */
8d7f1fbf 1253 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
ab69bde6
JB		 1254 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1255 } else {
8d7f1fbf 1256 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
ab69bde6 1257 if (err) {
8d7f1fbf
PST		 1258 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1259 goto out_pci_disable;
ab69bde6
JB		 1260 }
1261 }
1262
1263 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1264 err = pci_request_selected_regions(pdev, bars, alx_drv_name);
1265 if (err) {
1266 dev_err(&pdev->dev,
1267 "pci_request_selected_regions failed(bars:%d)\n", bars);
1268 goto out_pci_disable;
1269 }
1270
1271 pci_enable_pcie_error_reporting(pdev);
1272 pci_set_master(pdev);
1273
c3eb7a77 1274 if (!pdev->pm_cap) {
ab69bde6
JB		 1275 dev_err(&pdev->dev,
1276 "Can't find power management capability, aborting\n");
1277 err = -EIO;
1278 goto out_pci_release;
1279 }
1280
ab69bde6
JB		 1281 netdev = alloc_etherdev(sizeof(*alx));
1282 if (!netdev) {
1283 err = -ENOMEM;
1284 goto out_pci_release;
1285 }
1286
1287 SET_NETDEV_DEV(netdev, &pdev->dev);
1288 alx = netdev_priv(netdev);
a8798a5c
ML		 1289 spin_lock_init(&alx->hw.mdio_lock);
1290 spin_lock_init(&alx->irq_lock);
3e5ccc29 1291 spin_lock_init(&alx->stats_lock);
ab69bde6
JB		 1292 alx->dev = netdev;
1293 alx->hw.pdev = pdev;
1294 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1295 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1296 hw = &alx->hw;
1297 pci_set_drvdata(pdev, alx);
1298
1299 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1300 if (!hw->hw_addr) {
1301 dev_err(&pdev->dev, "cannot map device registers\n");
1302 err = -EIO;
1303 goto out_free_netdev;
1304 }
1305
1306 netdev->netdev_ops = &alx_netdev_ops;
7ad24ea4 1307 netdev->ethtool_ops = &alx_ethtool_ops;
ab69bde6
JB		 1308 netdev->irq = pdev->irq;
1309 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1310
1311 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1312 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1313
1314 err = alx_init_sw(alx);
1315 if (err) {
1316 dev_err(&pdev->dev, "net device private data init failed\n");
1317 goto out_unmap;
1318 }
1319
1320 alx_reset_pcie(hw);
1321
1322 phy_configured = alx_phy_configured(hw);
1323
1324 if (!phy_configured)
1325 alx_reset_phy(hw);
1326
1327 err = alx_reset_mac(hw);
1328 if (err) {
1329 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1330 goto out_unmap;
1331 }
1332
1333 /* setup link to put it in a known good starting state */
1334 if (!phy_configured) {
1335 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1336 if (err) {
1337 dev_err(&pdev->dev,
1338 "failed to configure PHY speed/duplex (err=%d)\n",
1339 err);
1340 goto out_unmap;
1341 }
1342 }
1343
1344 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
1345
1346 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1347 dev_warn(&pdev->dev,
1348 "Invalid permanent address programmed, using random one\n");
1349 eth_hw_addr_random(netdev);
1350 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1351 }
1352
1353 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1354 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1355 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1356
1357 hw->mdio.prtad = 0;
1358 hw->mdio.mmds = 0;
1359 hw->mdio.dev = netdev;
1360 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1361 MDIO_SUPPORTS_C22 |
1362 MDIO_EMULATE_C22;
1363 hw->mdio.mdio_read = alx_mdio_read;
1364 hw->mdio.mdio_write = alx_mdio_write;
1365
1366 if (!alx_get_phy_info(hw)) {
1367 dev_err(&pdev->dev, "failed to identify PHY\n");
1368 err = -EIO;
1369 goto out_unmap;
1370 }
1371
1372 INIT_WORK(&alx->link_check_wk, alx_link_check);
1373 INIT_WORK(&alx->reset_wk, alx_reset);
ab69bde6
JB		 1374 netif_carrier_off(netdev);
1375
1376 err = register_netdev(netdev);
1377 if (err) {
1378 dev_err(&pdev->dev, "register netdevice failed\n");
1379 goto out_unmap;
1380 }
1381
ab69bde6
JB		 1382 netdev_info(netdev,
1383 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1384 netdev->dev_addr);
1385
1386 return 0;
1387
1388out_unmap:
1389 iounmap(hw->hw_addr);
1390out_free_netdev:
1391 free_netdev(netdev);
1392out_pci_release:
1393 pci_release_selected_regions(pdev, bars);
1394out_pci_disable:
1395 pci_disable_device(pdev);
1396 return err;
1397}
1398
1399static void alx_remove(struct pci_dev *pdev)
1400{
1401 struct alx_priv *alx = pci_get_drvdata(pdev);
1402 struct alx_hw *hw = &alx->hw;
1403
1404 cancel_work_sync(&alx->link_check_wk);
1405 cancel_work_sync(&alx->reset_wk);
1406
1407 /* restore permanent mac address */
1408 alx_set_macaddr(hw, hw->perm_addr);
1409
1410 unregister_netdev(alx->dev);
1411 iounmap(hw->hw_addr);
1412 pci_release_selected_regions(pdev,
1413 pci_select_bars(pdev, IORESOURCE_MEM));
1414
1415 pci_disable_pcie_error_reporting(pdev);
1416 pci_disable_device(pdev);
ab69bde6
JB		 1417
1418 free_netdev(alx->dev);
1419}
1420
1421#ifdef CONFIG_PM_SLEEP
1422static int alx_suspend(struct device *dev)
1423{
1424 struct pci_dev *pdev = to_pci_dev(dev);
bc2bebe8 1425 struct alx_priv *alx = pci_get_drvdata(pdev);
ab69bde6 1426
bc2bebe8
JB		 1427 if (!netif_running(alx->dev))
1428 return 0;
1429 netif_device_detach(alx->dev);
1430 __alx_stop(alx);
ab69bde6
JB		 1431 return 0;
1432}
1433
1434static int alx_resume(struct device *dev)
1435{
1436 struct pci_dev *pdev = to_pci_dev(dev);
1437 struct alx_priv *alx = pci_get_drvdata(pdev);
b54629e2 1438 struct alx_hw *hw = &alx->hw;
1439
1440 alx_reset_phy(hw);
ab69bde6 1441
bc2bebe8
JB		 1442 if (!netif_running(alx->dev))
1443 return 0;
1444 netif_device_attach(alx->dev);
1445 return __alx_open(alx, true);
ab69bde6 1446}
bc2bebe8
JB		 1447
1448static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1449#define ALX_PM_OPS (&alx_pm_ops)
1450#else
1451#define ALX_PM_OPS NULL
ab69bde6
JB		 1452#endif
1453
bc2bebe8 1454
ab69bde6
JB		 1455static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1456 pci_channel_state_t state)
1457{
1458 struct alx_priv *alx = pci_get_drvdata(pdev);
1459 struct net_device *netdev = alx->dev;
1460 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1461
1462 dev_info(&pdev->dev, "pci error detected\n");
1463
1464 rtnl_lock();
1465
1466 if (netif_running(netdev)) {
1467 netif_device_detach(netdev);
1468 alx_halt(alx);
1469 }
1470
1471 if (state == pci_channel_io_perm_failure)
1472 rc = PCI_ERS_RESULT_DISCONNECT;
1473 else
1474 pci_disable_device(pdev);
1475
1476 rtnl_unlock();
1477
1478 return rc;
1479}
1480
1481static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1482{
1483 struct alx_priv *alx = pci_get_drvdata(pdev);
1484 struct alx_hw *hw = &alx->hw;
1485 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1486
1487 dev_info(&pdev->dev, "pci error slot reset\n");
1488
1489 rtnl_lock();
1490
1491 if (pci_enable_device(pdev)) {
1492 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1493 goto out;
1494 }
1495
1496 pci_set_master(pdev);
ab69bde6
JB		 1497
1498 alx_reset_pcie(hw);
1499 if (!alx_reset_mac(hw))
1500 rc = PCI_ERS_RESULT_RECOVERED;
1501out:
1502 pci_cleanup_aer_uncorrect_error_status(pdev);
1503
1504 rtnl_unlock();
1505
1506 return rc;
1507}
1508
1509static void alx_pci_error_resume(struct pci_dev *pdev)
1510{
1511 struct alx_priv *alx = pci_get_drvdata(pdev);
1512 struct net_device *netdev = alx->dev;
1513
1514 dev_info(&pdev->dev, "pci error resume\n");
1515
1516 rtnl_lock();
1517
1518 if (netif_running(netdev)) {
1519 alx_activate(alx);
1520 netif_device_attach(netdev);
1521 }
1522
1523 rtnl_unlock();
1524}
1525
1526static const struct pci_error_handlers alx_err_handlers = {
1527 .error_detected = alx_pci_error_detected,
1528 .slot_reset = alx_pci_error_slot_reset,
1529 .resume = alx_pci_error_resume,
1530};
1531
9baa3c34 1532static const struct pci_device_id alx_pci_tbl[] = {
ab69bde6
JB		 1533 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
1534 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1535 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
1536 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1537 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
1538 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1539 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
1540 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
1541 {}
1542};
1543
1544static struct pci_driver alx_driver = {
1545 .name = alx_drv_name,
1546 .id_table = alx_pci_tbl,
1547 .probe = alx_probe,
1548 .remove = alx_remove,
ab69bde6
JB		 1549 .err_handler = &alx_err_handlers,
1550 .driver.pm = ALX_PM_OPS,
1551};
1552
1553module_pci_driver(alx_driver);
1554MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
1555MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
1556MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
1557MODULE_DESCRIPTION(
1558 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
1559MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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