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52dfc830 MR |
1 | #ifndef _NB8800_H_ |
2 | #define _NB8800_H_ | |
3 | ||
4 | #include <linux/types.h> | |
5 | #include <linux/skbuff.h> | |
6 | #include <linux/phy.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/bitops.h> | |
9 | ||
10 | #define RX_DESC_COUNT 256 | |
11 | #define TX_DESC_COUNT 256 | |
12 | ||
13 | #define NB8800_DESC_LOW 4 | |
14 | ||
15 | #define RX_BUF_SIZE 1552 | |
16 | ||
17 | #define RX_COPYBREAK 256 | |
18 | #define RX_COPYHDR 128 | |
19 | ||
20 | #define MAX_MDC_CLOCK 2500000 | |
21 | ||
22 | /* Stargate Solutions SSN8800 core registers */ | |
23 | #define NB8800_TX_CTL1 0x000 | |
24 | #define TX_TPD BIT(5) | |
25 | #define TX_APPEND_FCS BIT(4) | |
26 | #define TX_PAD_EN BIT(3) | |
27 | #define TX_RETRY_EN BIT(2) | |
28 | #define TX_EN BIT(0) | |
29 | ||
30 | #define NB8800_TX_CTL2 0x001 | |
31 | ||
32 | #define NB8800_RX_CTL 0x004 | |
33 | #define RX_BC_DISABLE BIT(7) | |
34 | #define RX_RUNT BIT(6) | |
35 | #define RX_AF_EN BIT(5) | |
36 | #define RX_PAUSE_EN BIT(3) | |
37 | #define RX_SEND_CRC BIT(2) | |
38 | #define RX_PAD_STRIP BIT(1) | |
39 | #define RX_EN BIT(0) | |
40 | ||
41 | #define NB8800_RANDOM_SEED 0x008 | |
42 | #define NB8800_TX_SDP 0x14 | |
43 | #define NB8800_TX_TPDP1 0x18 | |
44 | #define NB8800_TX_TPDP2 0x19 | |
45 | #define NB8800_SLOT_TIME 0x1c | |
46 | ||
47 | #define NB8800_MDIO_CMD 0x020 | |
48 | #define MDIO_CMD_GO BIT(31) | |
49 | #define MDIO_CMD_WR BIT(26) | |
50 | #define MDIO_CMD_ADDR(x) ((x) << 21) | |
51 | #define MDIO_CMD_REG(x) ((x) << 16) | |
52 | #define MDIO_CMD_DATA(x) ((x) << 0) | |
53 | ||
54 | #define NB8800_MDIO_STS 0x024 | |
55 | #define MDIO_STS_ERR BIT(31) | |
56 | ||
57 | #define NB8800_MC_ADDR(i) (0x028 + (i)) | |
58 | #define NB8800_MC_INIT 0x02e | |
59 | #define NB8800_UC_ADDR(i) (0x03c + (i)) | |
60 | ||
61 | #define NB8800_MAC_MODE 0x044 | |
62 | #define RGMII_MODE BIT(7) | |
63 | #define HALF_DUPLEX BIT(4) | |
64 | #define BURST_EN BIT(3) | |
65 | #define LOOPBACK_EN BIT(2) | |
66 | #define GMAC_MODE BIT(0) | |
67 | ||
68 | #define NB8800_IC_THRESHOLD 0x050 | |
69 | #define NB8800_PE_THRESHOLD 0x051 | |
70 | #define NB8800_PF_THRESHOLD 0x052 | |
71 | #define NB8800_TX_BUFSIZE 0x054 | |
72 | #define NB8800_FIFO_CTL 0x056 | |
73 | #define NB8800_PQ1 0x060 | |
74 | #define NB8800_PQ2 0x061 | |
75 | #define NB8800_SRC_ADDR(i) (0x06a + (i)) | |
76 | #define NB8800_STAT_DATA 0x078 | |
77 | #define NB8800_STAT_INDEX 0x07c | |
78 | #define NB8800_STAT_CLEAR 0x07d | |
79 | ||
80 | #define NB8800_SLEEP_MODE 0x07e | |
81 | #define SLEEP_MODE BIT(0) | |
82 | ||
83 | #define NB8800_WAKEUP 0x07f | |
84 | #define WAKEUP BIT(0) | |
85 | ||
86 | /* Aurora NB8800 host interface registers */ | |
87 | #define NB8800_TXC_CR 0x100 | |
88 | #define TCR_LK BIT(12) | |
89 | #define TCR_DS BIT(11) | |
90 | #define TCR_BTS(x) (((x) & 0x7) << 8) | |
91 | #define TCR_DIE BIT(7) | |
92 | #define TCR_TFI(x) (((x) & 0x7) << 4) | |
93 | #define TCR_LE BIT(3) | |
94 | #define TCR_RS BIT(2) | |
95 | #define TCR_DM BIT(1) | |
96 | #define TCR_EN BIT(0) | |
97 | ||
98 | #define NB8800_TXC_SR 0x104 | |
99 | #define TSR_DE BIT(3) | |
100 | #define TSR_DI BIT(2) | |
101 | #define TSR_TO BIT(1) | |
102 | #define TSR_TI BIT(0) | |
103 | ||
104 | #define NB8800_TX_SAR 0x108 | |
105 | #define NB8800_TX_DESC_ADDR 0x10c | |
106 | ||
107 | #define NB8800_TX_REPORT_ADDR 0x110 | |
108 | #define TX_BYTES_TRANSFERRED(x) (((x) >> 16) & 0xffff) | |
109 | #define TX_FIRST_DEFERRAL BIT(7) | |
110 | #define TX_EARLY_COLLISIONS(x) (((x) >> 3) & 0xf) | |
111 | #define TX_LATE_COLLISION BIT(2) | |
112 | #define TX_PACKET_DROPPED BIT(1) | |
113 | #define TX_FIFO_UNDERRUN BIT(0) | |
114 | #define IS_TX_ERROR(r) ((r) & 0x07) | |
115 | ||
116 | #define NB8800_TX_FIFO_SR 0x114 | |
117 | #define NB8800_TX_ITR 0x118 | |
118 | ||
119 | #define NB8800_RXC_CR 0x200 | |
120 | #define RCR_FL BIT(13) | |
121 | #define RCR_LK BIT(12) | |
122 | #define RCR_DS BIT(11) | |
123 | #define RCR_BTS(x) (((x) & 7) << 8) | |
124 | #define RCR_DIE BIT(7) | |
125 | #define RCR_RFI(x) (((x) & 7) << 4) | |
126 | #define RCR_LE BIT(3) | |
127 | #define RCR_RS BIT(2) | |
128 | #define RCR_DM BIT(1) | |
129 | #define RCR_EN BIT(0) | |
130 | ||
131 | #define NB8800_RXC_SR 0x204 | |
132 | #define RSR_DE BIT(3) | |
133 | #define RSR_DI BIT(2) | |
134 | #define RSR_RO BIT(1) | |
135 | #define RSR_RI BIT(0) | |
136 | ||
137 | #define NB8800_RX_SAR 0x208 | |
138 | #define NB8800_RX_DESC_ADDR 0x20c | |
139 | ||
140 | #define NB8800_RX_REPORT_ADDR 0x210 | |
141 | #define RX_BYTES_TRANSFERRED(x) (((x) >> 16) & 0xFFFF) | |
142 | #define RX_MULTICAST_PKT BIT(9) | |
143 | #define RX_BROADCAST_PKT BIT(8) | |
144 | #define RX_LENGTH_ERR BIT(7) | |
145 | #define RX_FCS_ERR BIT(6) | |
146 | #define RX_RUNT_PKT BIT(5) | |
147 | #define RX_FIFO_OVERRUN BIT(4) | |
148 | #define RX_LATE_COLLISION BIT(3) | |
149 | #define RX_ALIGNMENT_ERROR BIT(2) | |
150 | #define RX_ERROR_MASK 0xfc | |
151 | #define IS_RX_ERROR(r) ((r) & RX_ERROR_MASK) | |
152 | ||
153 | #define NB8800_RX_FIFO_SR 0x214 | |
154 | #define NB8800_RX_ITR 0x218 | |
155 | ||
156 | /* Sigma Designs SMP86xx additional registers */ | |
157 | #define NB8800_TANGOX_PAD_MODE 0x400 | |
158 | #define PAD_MODE_MASK 0x7 | |
159 | #define PAD_MODE_MII 0x0 | |
160 | #define PAD_MODE_RGMII 0x1 | |
161 | #define PAD_MODE_GTX_CLK_INV BIT(3) | |
162 | #define PAD_MODE_GTX_CLK_DELAY BIT(4) | |
163 | ||
164 | #define NB8800_TANGOX_MDIO_CLKDIV 0x420 | |
165 | #define NB8800_TANGOX_RESET 0x424 | |
166 | ||
167 | /* Hardware DMA descriptor */ | |
168 | struct nb8800_dma_desc { | |
169 | u32 s_addr; /* start address */ | |
170 | u32 n_addr; /* next descriptor address */ | |
171 | u32 r_addr; /* report address */ | |
172 | u32 config; | |
173 | } __aligned(8); | |
174 | ||
175 | #define DESC_ID BIT(23) | |
176 | #define DESC_EOC BIT(22) | |
177 | #define DESC_EOF BIT(21) | |
178 | #define DESC_LK BIT(20) | |
179 | #define DESC_DS BIT(19) | |
180 | #define DESC_BTS(x) (((x) & 0x7) << 16) | |
181 | ||
182 | /* DMA descriptor and associated data for rx. | |
183 | * Allocated from coherent memory. | |
184 | */ | |
185 | struct nb8800_rx_desc { | |
186 | /* DMA descriptor */ | |
187 | struct nb8800_dma_desc desc; | |
188 | ||
189 | /* Status report filled in by hardware */ | |
190 | u32 report; | |
191 | }; | |
192 | ||
193 | /* Address of buffer on rx ring */ | |
194 | struct nb8800_rx_buf { | |
195 | struct page *page; | |
196 | unsigned long offset; | |
197 | }; | |
198 | ||
199 | /* DMA descriptors and associated data for tx. | |
200 | * Allocated from coherent memory. | |
201 | */ | |
202 | struct nb8800_tx_desc { | |
203 | /* DMA descriptor. The second descriptor is used if packet | |
204 | * data is unaligned. | |
205 | */ | |
206 | struct nb8800_dma_desc desc[2]; | |
207 | ||
208 | /* Status report filled in by hardware */ | |
209 | u32 report; | |
210 | ||
211 | /* Bounce buffer for initial unaligned part of packet */ | |
212 | u8 buf[8] __aligned(8); | |
213 | }; | |
214 | ||
215 | /* Packet in tx queue */ | |
216 | struct nb8800_tx_buf { | |
217 | /* Currently queued skb */ | |
218 | struct sk_buff *skb; | |
219 | ||
220 | /* DMA address of the first descriptor */ | |
221 | dma_addr_t dma_desc; | |
222 | ||
223 | /* DMA address of packet data */ | |
224 | dma_addr_t dma_addr; | |
225 | ||
226 | /* Length of DMA mapping, less than skb->len if alignment | |
227 | * buffer is used. | |
228 | */ | |
229 | unsigned int dma_len; | |
230 | ||
231 | /* Number of packets in chain starting here */ | |
232 | unsigned int chain_len; | |
233 | ||
234 | /* Packet chain ready to be submitted to hardware */ | |
235 | bool ready; | |
236 | }; | |
237 | ||
238 | struct nb8800_priv { | |
239 | struct napi_struct napi; | |
240 | ||
241 | void __iomem *base; | |
242 | ||
243 | /* RX DMA descriptors */ | |
244 | struct nb8800_rx_desc *rx_descs; | |
245 | ||
246 | /* RX buffers referenced by DMA descriptors */ | |
247 | struct nb8800_rx_buf *rx_bufs; | |
248 | ||
249 | /* Current end of chain */ | |
250 | u32 rx_eoc; | |
251 | ||
252 | /* Value for rx interrupt time register in NAPI interrupt mode */ | |
253 | u32 rx_itr_irq; | |
254 | ||
255 | /* Value for rx interrupt time register in NAPI poll mode */ | |
256 | u32 rx_itr_poll; | |
257 | ||
258 | /* Value for config field of rx DMA descriptors */ | |
259 | u32 rx_dma_config; | |
260 | ||
261 | /* TX DMA descriptors */ | |
262 | struct nb8800_tx_desc *tx_descs; | |
263 | ||
264 | /* TX packet queue */ | |
265 | struct nb8800_tx_buf *tx_bufs; | |
266 | ||
267 | /* Number of free tx queue entries */ | |
268 | atomic_t tx_free; | |
269 | ||
270 | /* First free tx queue entry */ | |
271 | u32 tx_next; | |
272 | ||
273 | /* Next buffer to transmit */ | |
274 | u32 tx_queue; | |
275 | ||
276 | /* Start of current packet chain */ | |
277 | struct nb8800_tx_buf *tx_chain; | |
278 | ||
279 | /* Next buffer to reclaim */ | |
280 | u32 tx_done; | |
281 | ||
282 | /* Lock for DMA activation */ | |
283 | spinlock_t tx_lock; | |
284 | ||
285 | struct mii_bus *mii_bus; | |
286 | struct device_node *phy_node; | |
52dfc830 MR |
287 | |
288 | /* PHY connection type from DT */ | |
289 | int phy_mode; | |
290 | ||
291 | /* Current link status */ | |
292 | int speed; | |
293 | int duplex; | |
294 | int link; | |
295 | ||
296 | /* Pause settings */ | |
297 | bool pause_aneg; | |
298 | bool pause_rx; | |
299 | bool pause_tx; | |
300 | ||
301 | /* DMA base address of rx descriptors, see rx_descs above */ | |
302 | dma_addr_t rx_desc_dma; | |
303 | ||
304 | /* DMA base address of tx descriptors, see tx_descs above */ | |
305 | dma_addr_t tx_desc_dma; | |
306 | ||
307 | struct clk *clk; | |
308 | }; | |
309 | ||
310 | struct nb8800_ops { | |
311 | int (*init)(struct net_device *dev); | |
312 | int (*reset)(struct net_device *dev); | |
313 | }; | |
314 | ||
315 | #endif /* _NB8800_H_ */ |