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bnx2: Dump additional BC_STATE during firmware sync timeout.
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
dc187cb3 3 * Copyright (c) 2004-2011 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
555069da 17#include <linux/stringify.h>
f2a4f052
MC		 18#include <linux/kernel.h>
19#include <linux/timer.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/vmalloc.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/dma-mapping.h>
1977f032 31#include <linux/bitops.h>
f2a4f052
MC		 32#include <asm/io.h>
33#include <asm/irq.h>
34#include <linux/delay.h>
35#include <asm/byteorder.h>
c86a31f4 36#include <asm/page.h>
f2a4f052
MC		 37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
01789349 40#include <linux/if.h>
f2a4f052 41#include <linux/if_vlan.h>
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
57579f76 49#include <linux/firmware.h>
706bf240 50#include <linux/log2.h>
cd709aa9 51#include <linux/aer.h>
f2a4f052 52
4edd473f
MC		 53#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
b6016b76
MC		 57#include "bnx2.h"
58#include "bnx2_fw.h"
b3448b0b 59
b6016b76 60#define DRV_MODULE_NAME "bnx2"
c2c20ef4
MC		 61#define DRV_MODULE_VERSION "2.2.1"
62#define DRV_MODULE_RELDATE "Dec 18, 2011"
63#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
22fa159d 64#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
c2c20ef4 65#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
22fa159d
MC		 66#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
67#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 68
69#define RUN_AT(x) (jiffies + (x))
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
fefa8645 74static char version[] __devinitdata =
b6016b76
MC		 75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 78MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 81MODULE_FIRMWARE(FW_MIPS_FILE_06);
82MODULE_FIRMWARE(FW_RV2P_FILE_06);
83MODULE_FIRMWARE(FW_MIPS_FILE_09);
84MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 85MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 86
87static int disable_msi = 0;
88
89module_param(disable_msi, int, 0);
90MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
5b0c76ad
MC		 98 BCM5708,
99 BCM5708S,
bac0dff6 100 BCM5709,
27a005b8 101 BCM5709S,
7bb0a04f 102 BCM5716,
1caacecb 103 BCM5716S,
b6016b76
MC		 104} board_t;
105
106/* indexed by board_t, above */
fefa8645 107static struct {
b6016b76
MC		 108 char *name;
109} board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 121 };
122
7bb0a04f 123static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 146 { 0, }
147};
148
0ced9d01 149static const struct flash_spec flash_table[] =
b6016b76 150{
e30372c9
MC		 151#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 153 /* Slow EEPROM */
37137709 154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
37137709
MC		 158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
b6016b76
MC		 163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
37137709 165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
37137709 171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
37137709
MC		 175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
b6016b76
MC		 236};
237
0ced9d01 238static const struct flash_spec flash_5709 = {
e30372c9
MC		 239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245};
246
b6016b76
MC		 247MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
4327ba43 249static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 250static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 251
35e9010b 252static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 253{
2f8af120 254 u32 diff;
e89bbf10 255
11848b96
MC		 256 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
257 barrier();
faac9c4b
MC		 258
259 /* The ring uses 256 indices for 255 entries, one of them
260 * needs to be skipped.
261 */
35e9010b 262 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 263 if (unlikely(diff >= TX_DESC_CNT)) {
264 diff &= 0xffff;
265 if (diff == TX_DESC_CNT)
266 diff = MAX_TX_DESC_CNT;
267 }
807540ba 268 return bp->tx_ring_size - diff;
e89bbf10
MC		 269}
270
b6016b76
MC		 271static u32
272bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
273{
1b8227c4
MC		 274 u32 val;
275
276 spin_lock_bh(&bp->indirect_lock);
b6016b76 277 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 278 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
279 spin_unlock_bh(&bp->indirect_lock);
280 return val;
b6016b76
MC		 281}
282
283static void
284bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285{
1b8227c4 286 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
288 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 289 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 290}
291
2726d6e1
MC		 292static void
293bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294{
295 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
296}
297
298static u32
299bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300{
807540ba 301 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 302}
303
b6016b76
MC		 304static void
305bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
306{
307 offset += cid_addr;
1b8227c4 308 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 309 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
310 int i;
311
312 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
313 REG_WR(bp, BNX2_CTX_CTX_CTRL,
314 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
315 for (i = 0; i < 5; i++) {
59b47d8a
MC		 316 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
317 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
318 break;
319 udelay(5);
320 }
321 } else {
322 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
323 REG_WR(bp, BNX2_CTX_DATA, val);
324 }
1b8227c4 325 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 326}
327
4edd473f
MC		 328#ifdef BCM_CNIC
329static int
330bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331{
332 struct bnx2 *bp = netdev_priv(dev);
333 struct drv_ctl_io *io = &info->data.io;
334
335 switch (info->cmd) {
336 case DRV_CTL_IO_WR_CMD:
337 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 break;
339 case DRV_CTL_IO_RD_CMD:
340 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 break;
342 case DRV_CTL_CTX_WR_CMD:
343 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
344 break;
345 default:
346 return -EINVAL;
347 }
348 return 0;
349}
350
351static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352{
353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
354 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
355 int sb_id;
356
357 if (bp->flags & BNX2_FLAG_USING_MSIX) {
358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
359 bnapi->cnic_present = 0;
360 sb_id = bp->irq_nvecs;
361 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 } else {
363 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
364 bnapi->cnic_tag = bnapi->last_status_idx;
365 bnapi->cnic_present = 1;
366 sb_id = 0;
367 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
368 }
369
370 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
371 cp->irq_arr[0].status_blk = (void *)
372 ((unsigned long) bnapi->status_blk.msi +
373 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
374 cp->irq_arr[0].status_blk_num = sb_id;
375 cp->num_irq = 1;
376}
377
378static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
379 void *data)
380{
381 struct bnx2 *bp = netdev_priv(dev);
382 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
383
384 if (ops == NULL)
385 return -EINVAL;
386
387 if (cp->drv_state & CNIC_DRV_STATE_REGD)
388 return -EBUSY;
389
41c2178a
MC		 390 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
391 return -ENODEV;
392
4edd473f
MC		 393 bp->cnic_data = data;
394 rcu_assign_pointer(bp->cnic_ops, ops);
395
396 cp->num_irq = 0;
397 cp->drv_state = CNIC_DRV_STATE_REGD;
398
399 bnx2_setup_cnic_irq_info(bp);
400
401 return 0;
402}
403
404static int bnx2_unregister_cnic(struct net_device *dev)
405{
406 struct bnx2 *bp = netdev_priv(dev);
407 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
408 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
409
c5a88950 410 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 411 cp->drv_state = 0;
412 bnapi->cnic_present = 0;
2cfa5a04 413 RCU_INIT_POINTER(bp->cnic_ops, NULL);
c5a88950 414 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 415 synchronize_rcu();
416 return 0;
417}
418
419struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
420{
421 struct bnx2 *bp = netdev_priv(dev);
422 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
423
7625eb2f
MC		 424 if (!cp->max_iscsi_conn)
425 return NULL;
426
4edd473f
MC		 427 cp->drv_owner = THIS_MODULE;
428 cp->chip_id = bp->chip_id;
429 cp->pdev = bp->pdev;
430 cp->io_base = bp->regview;
431 cp->drv_ctl = bnx2_drv_ctl;
432 cp->drv_register_cnic = bnx2_register_cnic;
433 cp->drv_unregister_cnic = bnx2_unregister_cnic;
434
435 return cp;
436}
437EXPORT_SYMBOL(bnx2_cnic_probe);
438
439static void
440bnx2_cnic_stop(struct bnx2 *bp)
441{
442 struct cnic_ops *c_ops;
443 struct cnic_ctl_info info;
444
c5a88950 445 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 446 c_ops = rcu_dereference_protected(bp->cnic_ops,
447 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 448 if (c_ops) {
449 info.cmd = CNIC_CTL_STOP_CMD;
450 c_ops->cnic_ctl(bp->cnic_data, &info);
451 }
c5a88950 452 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 453}
454
455static void
456bnx2_cnic_start(struct bnx2 *bp)
457{
458 struct cnic_ops *c_ops;
459 struct cnic_ctl_info info;
460
c5a88950 461 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 462 c_ops = rcu_dereference_protected(bp->cnic_ops,
463 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 464 if (c_ops) {
465 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
466 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
467
468 bnapi->cnic_tag = bnapi->last_status_idx;
469 }
470 info.cmd = CNIC_CTL_START_CMD;
471 c_ops->cnic_ctl(bp->cnic_data, &info);
472 }
c5a88950 473 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 474}
475
476#else
477
478static void
479bnx2_cnic_stop(struct bnx2 *bp)
480{
481}
482
483static void
484bnx2_cnic_start(struct bnx2 *bp)
485{
486}
487
488#endif
489
b6016b76
MC		 490static int
491bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
492{
493 u32 val1;
494 int i, ret;
495
583c28e5 496 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 497 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
498 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
499
500 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
501 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
502
503 udelay(40);
504 }
505
506 val1 = (bp->phy_addr << 21) | (reg << 16) |
507 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
508 BNX2_EMAC_MDIO_COMM_START_BUSY;
509 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
510
511 for (i = 0; i < 50; i++) {
512 udelay(10);
513
514 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
515 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
516 udelay(5);
517
518 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
519 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
520
521 break;
522 }
523 }
524
525 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
526 *val = 0x0;
527 ret = -EBUSY;
528 }
529 else {
530 *val = val1;
531 ret = 0;
532 }
533
583c28e5 534 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 535 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
536 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
537
538 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
539 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
540
541 udelay(40);
542 }
543
544 return ret;
545}
546
547static int
548bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
549{
550 u32 val1;
551 int i, ret;
552
583c28e5 553 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 554 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
555 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
556
557 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
558 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
559
560 udelay(40);
561 }
562
563 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
564 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
565 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
566 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 567
b6016b76
MC		 568 for (i = 0; i < 50; i++) {
569 udelay(10);
570
571 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
572 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
573 udelay(5);
574 break;
575 }
576 }
577
578 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
579 ret = -EBUSY;
580 else
581 ret = 0;
582
583c28e5 583 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 584 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
585 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
586
587 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
588 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
589
590 udelay(40);
591 }
592
593 return ret;
594}
595
596static void
597bnx2_disable_int(struct bnx2 *bp)
598{
b4b36042
MC		 599 int i;
600 struct bnx2_napi *bnapi;
601
602 for (i = 0; i < bp->irq_nvecs; i++) {
603 bnapi = &bp->bnx2_napi[i];
604 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
605 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
606 }
b6016b76
MC		 607 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
608}
609
610static void
611bnx2_enable_int(struct bnx2 *bp)
612{
b4b36042
MC		 613 int i;
614 struct bnx2_napi *bnapi;
35efa7c1 615
b4b36042
MC		 616 for (i = 0; i < bp->irq_nvecs; i++) {
617 bnapi = &bp->bnx2_napi[i];
1269a8a6 618
b4b36042
MC		 619 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
620 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
621 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
622 bnapi->last_status_idx);
b6016b76 623
b4b36042
MC		 624 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
625 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
626 bnapi->last_status_idx);
627 }
bf5295bb 628 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 629}
630
631static void
632bnx2_disable_int_sync(struct bnx2 *bp)
633{
b4b36042
MC		 634 int i;
635
b6016b76 636 atomic_inc(&bp->intr_sem);
3767546c
MC		 637 if (!netif_running(bp->dev))
638 return;
639
b6016b76 640 bnx2_disable_int(bp);
b4b36042
MC		 641 for (i = 0; i < bp->irq_nvecs; i++)
642 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 643}
644
35efa7c1
MC		 645static void
646bnx2_napi_disable(struct bnx2 *bp)
647{
b4b36042
MC		 648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 652}
653
654static void
655bnx2_napi_enable(struct bnx2 *bp)
656{
b4b36042
MC		 657 int i;
658
659 for (i = 0; i < bp->irq_nvecs; i++)
660 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 661}
662
b6016b76 663static void
212f9934 664bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 665{
212f9934
MC		 666 if (stop_cnic)
667 bnx2_cnic_stop(bp);
b6016b76 668 if (netif_running(bp->dev)) {
35efa7c1 669 bnx2_napi_disable(bp);
b6016b76 670 netif_tx_disable(bp->dev);
b6016b76 671 }
b7466560 672 bnx2_disable_int_sync(bp);
a0ba6760 673 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 674}
675
676static void
212f9934 677bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 678{
679 if (atomic_dec_and_test(&bp->intr_sem)) {
680 if (netif_running(bp->dev)) {
706bf240 681 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 682 spin_lock_bh(&bp->phy_lock);
683 if (bp->link_up)
684 netif_carrier_on(bp->dev);
685 spin_unlock_bh(&bp->phy_lock);
35efa7c1 686 bnx2_napi_enable(bp);
b6016b76 687 bnx2_enable_int(bp);
212f9934
MC		 688 if (start_cnic)
689 bnx2_cnic_start(bp);
b6016b76
MC		 690 }
691 }
692}
693
35e9010b
MC		 694static void
695bnx2_free_tx_mem(struct bnx2 *bp)
696{
697 int i;
698
699 for (i = 0; i < bp->num_tx_rings; i++) {
700 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
701 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
702
703 if (txr->tx_desc_ring) {
36227e88
SG		 704 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
705 txr->tx_desc_ring,
706 txr->tx_desc_mapping);
35e9010b
MC		 707 txr->tx_desc_ring = NULL;
708 }
709 kfree(txr->tx_buf_ring);
710 txr->tx_buf_ring = NULL;
711 }
712}
713
bb4f98ab
MC		 714static void
715bnx2_free_rx_mem(struct bnx2 *bp)
716{
717 int i;
718
719 for (i = 0; i < bp->num_rx_rings; i++) {
720 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
721 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
722 int j;
723
724 for (j = 0; j < bp->rx_max_ring; j++) {
725 if (rxr->rx_desc_ring[j])
36227e88
SG		 726 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
727 rxr->rx_desc_ring[j],
728 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 729 rxr->rx_desc_ring[j] = NULL;
730 }
25b0b999 731 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 732 rxr->rx_buf_ring = NULL;
733
734 for (j = 0; j < bp->rx_max_pg_ring; j++) {
735 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 736 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
737 rxr->rx_pg_desc_ring[j],
738 rxr->rx_pg_desc_mapping[j]);
3298a738 739 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 740 }
25b0b999 741 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 742 rxr->rx_pg_ring = NULL;
743 }
744}
745
35e9010b
MC		 746static int
747bnx2_alloc_tx_mem(struct bnx2 *bp)
748{
749 int i;
750
751 for (i = 0; i < bp->num_tx_rings; i++) {
752 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
753 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
754
755 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
756 if (txr->tx_buf_ring == NULL)
757 return -ENOMEM;
758
759 txr->tx_desc_ring =
36227e88
SG		 760 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
761 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 762 if (txr->tx_desc_ring == NULL)
763 return -ENOMEM;
764 }
765 return 0;
766}
767
bb4f98ab
MC		 768static int
769bnx2_alloc_rx_mem(struct bnx2 *bp)
770{
771 int i;
772
773 for (i = 0; i < bp->num_rx_rings; i++) {
774 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
775 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
776 int j;
777
778 rxr->rx_buf_ring =
89bf67f1 779 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 780 if (rxr->rx_buf_ring == NULL)
781 return -ENOMEM;
782
bb4f98ab
MC		 783 for (j = 0; j < bp->rx_max_ring; j++) {
784 rxr->rx_desc_ring[j] =
36227e88
SG		 785 dma_alloc_coherent(&bp->pdev->dev,
786 RXBD_RING_SIZE,
787 &rxr->rx_desc_mapping[j],
788 GFP_KERNEL);
bb4f98ab
MC		 789 if (rxr->rx_desc_ring[j] == NULL)
790 return -ENOMEM;
791
792 }
793
794 if (bp->rx_pg_ring_size) {
89bf67f1 795 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 796 bp->rx_max_pg_ring);
797 if (rxr->rx_pg_ring == NULL)
798 return -ENOMEM;
799
bb4f98ab
MC		 800 }
801
802 for (j = 0; j < bp->rx_max_pg_ring; j++) {
803 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 804 dma_alloc_coherent(&bp->pdev->dev,
805 RXBD_RING_SIZE,
806 &rxr->rx_pg_desc_mapping[j],
807 GFP_KERNEL);
bb4f98ab
MC		 808 if (rxr->rx_pg_desc_ring[j] == NULL)
809 return -ENOMEM;
810
811 }
812 }
813 return 0;
814}
815
b6016b76
MC		 816static void
817bnx2_free_mem(struct bnx2 *bp)
818{
13daffa2 819 int i;
43e80b89 820 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 821
35e9010b 822 bnx2_free_tx_mem(bp);
bb4f98ab 823 bnx2_free_rx_mem(bp);
35e9010b 824
59b47d8a
MC		 825 for (i = 0; i < bp->ctx_pages; i++) {
826 if (bp->ctx_blk[i]) {
36227e88
SG		 827 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
828 bp->ctx_blk[i],
829 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 830 bp->ctx_blk[i] = NULL;
831 }
832 }
43e80b89 833 if (bnapi->status_blk.msi) {
36227e88
SG		 834 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
835 bnapi->status_blk.msi,
836 bp->status_blk_mapping);
43e80b89 837 bnapi->status_blk.msi = NULL;
0f31f994 838 bp->stats_blk = NULL;
b6016b76 839 }
b6016b76
MC		 840}
841
842static int
843bnx2_alloc_mem(struct bnx2 *bp)
844{
35e9010b 845 int i, status_blk_size, err;
43e80b89
MC		 846 struct bnx2_napi *bnapi;
847 void *status_blk;
b6016b76 848
0f31f994
MC		 849 /* Combine status and statistics blocks into one allocation. */
850 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 851 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 852 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
853 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 854 bp->status_stats_size = status_blk_size +
855 sizeof(struct statistics_block);
856
36227e88
SG		 857 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
858 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 859 if (status_blk == NULL)
b6016b76
MC		 860 goto alloc_mem_err;
861
43e80b89 862 memset(status_blk, 0, bp->status_stats_size);
b6016b76 863
43e80b89
MC		 864 bnapi = &bp->bnx2_napi[0];
865 bnapi->status_blk.msi = status_blk;
866 bnapi->hw_tx_cons_ptr =
867 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
868 bnapi->hw_rx_cons_ptr =
869 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 870 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 871 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 872 struct status_block_msix *sblk;
873
874 bnapi = &bp->bnx2_napi[i];
b4b36042 875
64699336 876 sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
43e80b89
MC		 877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 882 bnapi->int_num = i << 24;
883 }
884 }
35efa7c1 885
43e80b89 886 bp->stats_blk = status_blk + status_blk_size;
b6016b76 887
0f31f994 888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 889
59b47d8a
MC		 890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
893 bp->ctx_pages = 1;
894 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 896 BCM_PAGE_SIZE,
36227e88
SG		 897 &bp->ctx_blk_mapping[i],
898 GFP_KERNEL);
59b47d8a
MC		 899 if (bp->ctx_blk[i] == NULL)
900 goto alloc_mem_err;
901 }
902 }
35e9010b 903
bb4f98ab
MC		 904 err = bnx2_alloc_rx_mem(bp);
905 if (err)
906 goto alloc_mem_err;
907
35e9010b
MC		 908 err = bnx2_alloc_tx_mem(bp);
909 if (err)
910 goto alloc_mem_err;
911
b6016b76
MC		 912 return 0;
913
914alloc_mem_err:
915 bnx2_free_mem(bp);
916 return -ENOMEM;
917}
918
e3648b3d
MC		 919static void
920bnx2_report_fw_link(struct bnx2 *bp)
921{
922 u32 fw_link_status = 0;
923
583c28e5 924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 925 return;
926
e3648b3d
MC		 927 if (bp->link_up) {
928 u32 bmsr;
929
930 switch (bp->line_speed) {
931 case SPEED_10:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
936 break;
937 case SPEED_100:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
942 break;
943 case SPEED_1000:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
948 break;
949 case SPEED_2500:
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
952 else
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
954 break;
955 }
956
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
958
959 if (bp->autoneg) {
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
961
ca58c3af
MC		 962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 964
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
968 else
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
970 }
971 }
972 else
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
974
2726d6e1 975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 976}
977
9b1084b8
MC		 978static char *
979bnx2_xceiver_str(struct bnx2 *bp)
980{
807540ba 981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 983 "Copper");
9b1084b8
MC		 984}
985
b6016b76
MC		 986static void
987bnx2_report_link(struct bnx2 *bp)
988{
989 if (bp->link_up) {
990 netif_carrier_on(bp->dev);
3a9c6a49
JP		 991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
993 bp->line_speed,
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 995
996 if (bp->flow_ctrl) {
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 998 pr_cont(", receive ");
b6016b76 999 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 1000 pr_cont("& transmit ");
b6016b76
MC		 1001 }
1002 else {
3a9c6a49 1003 pr_cont(", transmit ");
b6016b76 1004 }
3a9c6a49 1005 pr_cont("flow control ON");
b6016b76 1006 }
3a9c6a49
JP		 1007 pr_cont("\n");
1008 } else {
b6016b76 1009 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
b6016b76 1012 }
e3648b3d
MC		 1013
1014 bnx2_report_fw_link(bp);
b6016b76
MC		 1015}
1016
1017static void
1018bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019{
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
6aa20a22 1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
583c28e5 1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
ca58c3af
MC		 1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1050
583c28e5 1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091}
1092
27a005b8
MC		 1093static int
1094bnx2_5709s_linkup(struct bnx2 *bp)
1095{
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130}
1131
b6016b76 1132static int
5b0c76ad
MC		 1133bnx2_5708s_linkup(struct bnx2 *bp)
1134{
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159}
1160
1161static int
1162bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1163{
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
ca58c3af 1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
ca58c3af
MC		 1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196}
1197
1198static int
1199bnx2_copper_linkup(struct bnx2 *bp)
1200{
1201 u32 bmcr;
1202
ca58c3af 1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
ca58c3af
MC		 1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262}
1263
83e3fc89 1264static void
bb4f98ab 1265bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1266{
bb4f98ab 1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
22fa159d
MC		 1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1275
83e3fc89
MC		 1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1277}
1278
bb4f98ab
MC		 1279static void
1280bnx2_init_all_rx_contexts(struct bnx2 *bp)
1281{
1282 int i;
1283 u32 cid;
1284
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1286 if (i == 1)
1287 cid = RX_RSS_CID;
1288 bnx2_init_rx_context(bp, cid);
1289 }
1290}
1291
344478db 1292static void
b6016b76
MC		 1293bnx2_set_mac_link(struct bnx2 *bp)
1294{
1295 u32 val;
1296
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1301 }
1302
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1305
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1308 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1309
1310 if (bp->link_up) {
5b0c76ad
MC		 1311 switch (bp->line_speed) {
1312 case SPEED_10:
59b47d8a
MC		 1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1315 break;
1316 }
1317 /* fall through */
1318 case SPEED_100:
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1320 break;
1321 case SPEED_2500:
59b47d8a 1322 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1323 /* fall through */
1324 case SPEED_1000:
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1326 break;
1327 }
b6016b76
MC		 1328 }
1329 else {
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1331 }
1332
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1337
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1340
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1344
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1348
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1352
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1355
22fa159d 1356 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1357}
1358
27a005b8
MC		 1359static void
1360bnx2_enable_bmsr1(struct bnx2 *bp)
1361{
583c28e5 1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1366}
1367
1368static void
1369bnx2_disable_bmsr1(struct bnx2 *bp)
1370{
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1375}
1376
605a9e20
MC		 1377static int
1378bnx2_test_and_enable_2g5(struct bnx2 *bp)
1379{
1380 u32 up1;
1381 int ret = 1;
1382
583c28e5 1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1384 return 0;
1385
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1388
27a005b8
MC		 1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1391
605a9e20
MC		 1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1396 ret = 0;
1397 }
1398
27a005b8
MC		 1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1402
605a9e20
MC		 1403 return ret;
1404}
1405
1406static int
1407bnx2_test_and_disable_2g5(struct bnx2 *bp)
1408{
1409 u32 up1;
1410 int ret = 0;
1411
583c28e5 1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1413 return 0;
1414
27a005b8
MC		 1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1417
605a9e20
MC		 1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 ret = 1;
1423 }
1424
27a005b8
MC		 1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1428
605a9e20
MC		 1429 return ret;
1430}
1431
1432static void
1433bnx2_enable_forced_2g5(struct bnx2 *bp)
1434{
cbd6890c
MC		 1435 u32 uninitialized_var(bmcr);
1436 int err;
605a9e20 1437
583c28e5 1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1439 return;
1440
27a005b8
MC		 1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1442 u32 val;
1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1451 }
27a005b8
MC		 1452
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1456
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1459 if (!err)
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1461 } else {
1462 return;
605a9e20
MC		 1463 }
1464
cbd6890c
MC		 1465 if (err)
1466 return;
1467
605a9e20
MC		 1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1472 }
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1474}
1475
1476static void
1477bnx2_disable_forced_2g5(struct bnx2 *bp)
1478{
cbd6890c
MC		 1479 u32 uninitialized_var(bmcr);
1480 int err;
605a9e20 1481
583c28e5 1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1483 return;
1484
27a005b8
MC		 1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1486 u32 val;
1487
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1493 }
27a005b8
MC		 1494
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1498
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501 if (!err)
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1503 } else {
1504 return;
605a9e20
MC		 1505 }
1506
cbd6890c
MC		 1507 if (err)
1508 return;
1509
605a9e20
MC		 1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513}
1514
b2fadeae
MC		 1515static void
1516bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517{
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526}
1527
b6016b76
MC		 1528static int
1529bnx2_set_link(struct bnx2 *bp)
1530{
1531 u32 bmsr;
1532 u8 link_up;
1533
80be4434 1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
583c28e5 1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1540 return 0;
1541
b6016b76
MC		 1542 link_up = bp->link_up;
1543
27a005b8
MC		 1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
b6016b76 1548
583c28e5 1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1551 u32 val, an_dbg;
b6016b76 1552
583c28e5 1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1554 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1556 }
b6016b76 1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
583c28e5 1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
27a005b8
MC		 1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
b6016b76
MC		 1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
583c28e5 1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
b6016b76 1590
583c28e5 1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
583c28e5 1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1599 }
b6016b76
MC		 1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610}
1611
1612static int
1613bnx2_reset_phy(struct bnx2 *bp)
1614{
1615 int i;
1616 u32 reg;
1617
ca58c3af 1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1619
1620#define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
ca58c3af 1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634}
1635
1636static u32
1637bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638{
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
583c28e5 1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668}
1669
a2f13890 1670static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1671
b6016b76 1672static int
0d8a6571 1673bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1674__releases(&bp->phy_lock)
1675__acquires(&bp->phy_lock)
0d8a6571
MC		 1676{
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
2726d6e1 1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1723
1724 spin_unlock_bh(&bp->phy_lock);
a2f13890 1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729}
1730
1731static int
1732bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1733__releases(&bp->phy_lock)
1734__acquires(&bp->phy_lock)
b6016b76 1735{
605a9e20 1736 u32 adv, bmcr;
b6016b76
MC		 1737 u32 new_adv = 0;
1738
583c28e5 1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1740 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1741
b6016b76
MC		 1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
5b0c76ad
MC		 1744 int force_link_down = 0;
1745
605a9e20
MC		 1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
ca58c3af 1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
ca58c3af 1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1758 new_bmcr |= BMCR_SPEED1000;
605a9e20 1759
27a005b8
MC		 1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1773 }
1774
b6016b76 1775 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1776 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
5b0c76ad 1780 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
5b0c76ad 1783 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
ca58c3af 1786 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
ca58c3af 1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
ca58c3af 1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1795 bnx2_report_link(bp);
b6016b76 1796 }
ca58c3af
MC		 1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
b6016b76
MC		 1802 }
1803 return 0;
1804 }
1805
605a9e20 1806 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1807
b6016b76
MC		 1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
ca58c3af
MC		 1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
ca58c3af 1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1824 }
1825
ca58c3af
MC		 1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1828 BMCR_ANENABLE);
f8dd064e
MC		 1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
40105c0b 1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
b6016b76
MC		 1843 }
1844
1845 return 0;
1846}
1847
1848#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1852
1853#define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1860
b6016b76
MC		 1861#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
0d8a6571
MC		 1863static void
1864bnx2_set_default_remote_link(struct bnx2 *bp)
1865{
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
2726d6e1 1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1870 else
2726d6e1 1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908}
1909
deaf391b
MC		 1910static void
1911bnx2_set_default_link(struct bnx2 *bp)
1912{
ab59859d
HH		 1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
0d8a6571 1917
deaf391b
MC		 1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
583c28e5 1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
2726d6e1 1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934}
1935
df149d70
MC		 1936static void
1937bnx2_send_heart_beat(struct bnx2 *bp)
1938{
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948}
1949
0d8a6571
MC		 1950static void
1951bnx2_remote_phy_event(struct bnx2 *bp)
1952{
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
2726d6e1 1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1958
df149d70
MC		 1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
0d8a6571
MC		 1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
0d8a6571
MC		 1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
0d8a6571
MC		 2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025}
2026
2027static int
2028bnx2_set_remote_link(struct bnx2 *bp)
2029{
2030 u32 evt_code;
2031
2726d6e1 2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
df149d70 2039 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2040 break;
2041 }
2042 return 0;
2043}
2044
b6016b76
MC		 2045static int
2046bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2047__releases(&bp->phy_lock)
2048__acquires(&bp->phy_lock)
b6016b76
MC		 2049{
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
ca58c3af 2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
37f07023
MC		 2057 u32 new_adv = 0;
2058 u32 new_adv1000 = 0;
b6016b76 2059
ca58c3af 2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
37f07023
MC		 2067 new_adv = ethtool_adv_to_mii_adv_t(bp->advertising);
2068 new_adv |= ADVERTISE_CSMA;
2069 new_adv |= bnx2_phy_get_pause_adv(bp);
b6016b76 2070
37f07023 2071 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
28011cf1 2072
37f07023
MC		 2073 if ((adv1000_reg != new_adv1000) ||
2074 (adv_reg != new_adv) ||
b6016b76
MC		 2075 ((bmcr & BMCR_ANENABLE) == 0)) {
2076
37f07023
MC		 2077 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2078 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
ca58c3af 2079 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2080 BMCR_ANENABLE);
2081 }
2082 else if (bp->link_up) {
2083 /* Flow ctrl may have changed from auto to forced */
2084 /* or vice-versa. */
2085
2086 bnx2_resolve_flow_ctrl(bp);
2087 bnx2_set_mac_link(bp);
2088 }
2089 return 0;
2090 }
2091
2092 new_bmcr = 0;
2093 if (bp->req_line_speed == SPEED_100) {
2094 new_bmcr |= BMCR_SPEED100;
2095 }
2096 if (bp->req_duplex == DUPLEX_FULL) {
2097 new_bmcr |= BMCR_FULLDPLX;
2098 }
2099 if (new_bmcr != bmcr) {
2100 u32 bmsr;
b6016b76 2101
ca58c3af
MC		 2102 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2103 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2104
b6016b76
MC		 2105 if (bmsr & BMSR_LSTATUS) {
2106 /* Force link down */
ca58c3af 2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2108 spin_unlock_bh(&bp->phy_lock);
2109 msleep(50);
2110 spin_lock_bh(&bp->phy_lock);
2111
ca58c3af
MC		 2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2114 }
2115
ca58c3af 2116 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2117
2118 /* Normally, the new speed is setup after the link has
2119 * gone down and up again. In some cases, link will not go
2120 * down so we need to set up the new speed here.
2121 */
2122 if (bmsr & BMSR_LSTATUS) {
2123 bp->line_speed = bp->req_line_speed;
2124 bp->duplex = bp->req_duplex;
2125 bnx2_resolve_flow_ctrl(bp);
2126 bnx2_set_mac_link(bp);
2127 }
27a005b8
MC		 2128 } else {
2129 bnx2_resolve_flow_ctrl(bp);
2130 bnx2_set_mac_link(bp);
b6016b76
MC		 2131 }
2132 return 0;
2133}
2134
2135static int
0d8a6571 2136bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2137__releases(&bp->phy_lock)
2138__acquires(&bp->phy_lock)
b6016b76
MC		 2139{
2140 if (bp->loopback == MAC_LOOPBACK)
2141 return 0;
2142
583c28e5 2143 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2144 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2145 }
2146 else {
807540ba 2147 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2148 }
2149}
2150
27a005b8 2151static int
9a120bc5 2152bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2153{
2154 u32 val;
2155
2156 bp->mii_bmcr = MII_BMCR + 0x10;
2157 bp->mii_bmsr = MII_BMSR + 0x10;
2158 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2159 bp->mii_adv = MII_ADVERTISE + 0x10;
2160 bp->mii_lpa = MII_LPA + 0x10;
2161 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2162
2163 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2164 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2165
2166 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2167 if (reset_phy)
2168 bnx2_reset_phy(bp);
27a005b8
MC		 2169
2170 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2171
2172 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2173 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2174 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2175 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2176
2177 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2178 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2179 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2180 val |= BCM5708S_UP1_2G5;
2181 else
2182 val &= ~BCM5708S_UP1_2G5;
2183 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2184
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2186 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2187 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2188 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2189
2190 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2191
2192 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2193 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2194 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2195
2196 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2197
2198 return 0;
2199}
2200
b6016b76 2201static int
9a120bc5 2202bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2203{
2204 u32 val;
2205
9a120bc5
MC		 2206 if (reset_phy)
2207 bnx2_reset_phy(bp);
27a005b8
MC		 2208
2209 bp->mii_up1 = BCM5708S_UP1;
2210
5b0c76ad
MC		 2211 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2212 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2213 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2214
2215 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2216 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2217 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2218
2219 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2220 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2221 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2222
583c28e5 2223 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2224 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2225 val |= BCM5708S_UP1_2G5;
2226 bnx2_write_phy(bp, BCM5708S_UP1, val);
2227 }
2228
2229 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2230 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2231 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2232 /* increase tx signal amplitude */
2233 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2234 BCM5708S_BLK_ADDR_TX_MISC);
2235 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2236 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2237 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2238 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2239 }
2240
2726d6e1 2241 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2242 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2243
2244 if (val) {
2245 u32 is_backplane;
2246
2726d6e1 2247 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2248 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250 BCM5708S_BLK_ADDR_TX_MISC);
2251 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2252 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2253 BCM5708S_BLK_ADDR_DIG);
2254 }
2255 }
2256 return 0;
2257}
2258
2259static int
9a120bc5 2260bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2261{
9a120bc5
MC		 2262 if (reset_phy)
2263 bnx2_reset_phy(bp);
27a005b8 2264
583c28e5 2265 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2266
59b47d8a
MC		 2267 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2268 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2269
2270 if (bp->dev->mtu > 1500) {
2271 u32 val;
2272
2273 /* Set extended packet length bit */
2274 bnx2_write_phy(bp, 0x18, 0x7);
2275 bnx2_read_phy(bp, 0x18, &val);
2276 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2277
2278 bnx2_write_phy(bp, 0x1c, 0x6c00);
2279 bnx2_read_phy(bp, 0x1c, &val);
2280 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2281 }
2282 else {
2283 u32 val;
2284
2285 bnx2_write_phy(bp, 0x18, 0x7);
2286 bnx2_read_phy(bp, 0x18, &val);
2287 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2288
2289 bnx2_write_phy(bp, 0x1c, 0x6c00);
2290 bnx2_read_phy(bp, 0x1c, &val);
2291 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2292 }
2293
2294 return 0;
2295}
2296
2297static int
9a120bc5 2298bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2299{
5b0c76ad
MC		 2300 u32 val;
2301
9a120bc5
MC		 2302 if (reset_phy)
2303 bnx2_reset_phy(bp);
27a005b8 2304
583c28e5 2305 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2306 bnx2_write_phy(bp, 0x18, 0x0c00);
2307 bnx2_write_phy(bp, 0x17, 0x000a);
2308 bnx2_write_phy(bp, 0x15, 0x310b);
2309 bnx2_write_phy(bp, 0x17, 0x201f);
2310 bnx2_write_phy(bp, 0x15, 0x9506);
2311 bnx2_write_phy(bp, 0x17, 0x401f);
2312 bnx2_write_phy(bp, 0x15, 0x14e2);
2313 bnx2_write_phy(bp, 0x18, 0x0400);
2314 }
2315
583c28e5 2316 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2317 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2318 MII_BNX2_DSP_EXPAND_REG | 0x8);
2319 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2320 val &= ~(1 << 8);
2321 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2322 }
2323
b6016b76 2324 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2325 /* Set extended packet length bit */
2326 bnx2_write_phy(bp, 0x18, 0x7);
2327 bnx2_read_phy(bp, 0x18, &val);
2328 bnx2_write_phy(bp, 0x18, val | 0x4000);
2329
2330 bnx2_read_phy(bp, 0x10, &val);
2331 bnx2_write_phy(bp, 0x10, val | 0x1);
2332 }
2333 else {
b6016b76
MC		 2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2337
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val & ~0x1);
2340 }
2341
5b0c76ad
MC		 2342 /* ethernet@wirespeed */
2343 bnx2_write_phy(bp, 0x18, 0x7007);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2346 return 0;
2347}
2348
2349
2350static int
9a120bc5 2351bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2352__releases(&bp->phy_lock)
2353__acquires(&bp->phy_lock)
b6016b76
MC		 2354{
2355 u32 val;
2356 int rc = 0;
2357
583c28e5
MC		 2358 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2359 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2360
ca58c3af
MC		 2361 bp->mii_bmcr = MII_BMCR;
2362 bp->mii_bmsr = MII_BMSR;
27a005b8 2363 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2364 bp->mii_adv = MII_ADVERTISE;
2365 bp->mii_lpa = MII_LPA;
2366
b6016b76
MC		 2367 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2368
583c28e5 2369 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2370 goto setup_phy;
2371
b6016b76
MC		 2372 bnx2_read_phy(bp, MII_PHYSID1, &val);
2373 bp->phy_id = val << 16;
2374 bnx2_read_phy(bp, MII_PHYSID2, &val);
2375 bp->phy_id |= val & 0xffff;
2376
583c28e5 2377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2378 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2379 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2380 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2381 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2382 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2383 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2384 }
2385 else {
9a120bc5 2386 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2387 }
2388
0d8a6571
MC		 2389setup_phy:
2390 if (!rc)
2391 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2392
2393 return rc;
2394}
2395
2396static int
2397bnx2_set_mac_loopback(struct bnx2 *bp)
2398{
2399 u32 mac_mode;
2400
2401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2402 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2403 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2404 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2405 bp->link_up = 1;
2406 return 0;
2407}
2408
bc5a0690
MC		 2409static int bnx2_test_link(struct bnx2 *);
2410
2411static int
2412bnx2_set_phy_loopback(struct bnx2 *bp)
2413{
2414 u32 mac_mode;
2415 int rc, i;
2416
2417 spin_lock_bh(&bp->phy_lock);
ca58c3af 2418 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2419 BMCR_SPEED1000);
2420 spin_unlock_bh(&bp->phy_lock);
2421 if (rc)
2422 return rc;
2423
2424 for (i = 0; i < 10; i++) {
2425 if (bnx2_test_link(bp) == 0)
2426 break;
80be4434 2427 msleep(100);
bc5a0690
MC		 2428 }
2429
2430 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2431 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2432 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2433 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2434
2435 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2436 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2437 bp->link_up = 1;
2438 return 0;
2439}
2440
ecdbf6e0
JH		 2441static void
2442bnx2_dump_mcp_state(struct bnx2 *bp)
2443{
2444 struct net_device *dev = bp->dev;
2445 u32 mcp_p0, mcp_p1;
2446
2447 netdev_err(dev, "<--- start MCP states dump --->\n");
2448 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2449 mcp_p0 = BNX2_MCP_STATE_P0;
2450 mcp_p1 = BNX2_MCP_STATE_P1;
2451 } else {
2452 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2453 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2454 }
2455 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2456 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2457 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2458 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2459 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2460 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2461 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2462 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2463 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2464 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2465 netdev_err(dev, "DEBUG: shmem states:\n");
2466 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2467 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2468 bnx2_shmem_rd(bp, BNX2_FW_MB),
2469 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2470 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2471 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2472 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2473 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2474 pr_cont(" condition[%08x]\n",
2475 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
13e63517 2476 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
ecdbf6e0
JH		 2477 DP_SHMEM_LINE(bp, 0x3cc);
2478 DP_SHMEM_LINE(bp, 0x3dc);
2479 DP_SHMEM_LINE(bp, 0x3ec);
2480 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2481 netdev_err(dev, "<--- end MCP states dump --->\n");
2482}
2483
b6016b76 2484static int
a2f13890 2485bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2486{
2487 int i;
2488 u32 val;
2489
b6016b76
MC		 2490 bp->fw_wr_seq++;
2491 msg_data |= bp->fw_wr_seq;
2492
2726d6e1 2493 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2494
a2f13890
MC		 2495 if (!ack)
2496 return 0;
2497
b6016b76 2498 /* wait for an acknowledgement. */
40105c0b 2499 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2500 msleep(10);
b6016b76 2501
2726d6e1 2502 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2503
2504 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2505 break;
2506 }
b090ae2b
MC		 2507 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2508 return 0;
b6016b76
MC		 2509
2510 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2511 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2512 msg_data &= ~BNX2_DRV_MSG_CODE;
2513 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2514
2726d6e1 2515 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2516 if (!silent) {
2517 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2518 bnx2_dump_mcp_state(bp);
2519 }
b6016b76 2520
b6016b76
MC		 2521 return -EBUSY;
2522 }
2523
b090ae2b
MC		 2524 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2525 return -EIO;
2526
b6016b76
MC		 2527 return 0;
2528}
2529
59b47d8a
MC		 2530static int
2531bnx2_init_5709_context(struct bnx2 *bp)
2532{
2533 int i, ret = 0;
2534 u32 val;
2535
2536 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2537 val |= (BCM_PAGE_BITS - 8) << 16;
2538 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2539 for (i = 0; i < 10; i++) {
2540 val = REG_RD(bp, BNX2_CTX_COMMAND);
2541 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2542 break;
2543 udelay(2);
2544 }
2545 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2546 return -EBUSY;
2547
59b47d8a
MC		 2548 for (i = 0; i < bp->ctx_pages; i++) {
2549 int j;
2550
352f7687
MC		 2551 if (bp->ctx_blk[i])
2552 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2553 else
2554 return -ENOMEM;
2555
59b47d8a
MC		 2556 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2557 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2558 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2559 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2560 (u64) bp->ctx_blk_mapping[i] >> 32);
2561 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2562 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2563 for (j = 0; j < 10; j++) {
2564
2565 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2566 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2567 break;
2568 udelay(5);
2569 }
2570 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2571 ret = -EBUSY;
2572 break;
2573 }
2574 }
2575 return ret;
2576}
2577
b6016b76
MC		 2578static void
2579bnx2_init_context(struct bnx2 *bp)
2580{
2581 u32 vcid;
2582
2583 vcid = 96;
2584 while (vcid) {
2585 u32 vcid_addr, pcid_addr, offset;
7947b20e 2586 int i;
b6016b76
MC		 2587
2588 vcid--;
2589
2590 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2591 u32 new_vcid;
2592
2593 vcid_addr = GET_PCID_ADDR(vcid);
2594 if (vcid & 0x8) {
2595 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2596 }
2597 else {
2598 new_vcid = vcid;
2599 }
2600 pcid_addr = GET_PCID_ADDR(new_vcid);
2601 }
2602 else {
2603 vcid_addr = GET_CID_ADDR(vcid);
2604 pcid_addr = vcid_addr;
2605 }
2606
7947b20e
MC		 2607 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2608 vcid_addr += (i << PHY_CTX_SHIFT);
2609 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2610
5d5d0015 2611 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2612 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2613
7947b20e
MC		 2614 /* Zero out the context. */
2615 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2616 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2617 }
b6016b76
MC		 2618 }
2619}
2620
2621static int
2622bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2623{
2624 u16 *good_mbuf;
2625 u32 good_mbuf_cnt;
2626 u32 val;
2627
2628 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
e404decb 2629 if (good_mbuf == NULL)
b6016b76 2630 return -ENOMEM;
b6016b76
MC		 2631
2632 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2633 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2634
2635 good_mbuf_cnt = 0;
2636
2637 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2638 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2639 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2640 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2641 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2642
2726d6e1 2643 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2644
2645 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2646
2647 /* The addresses with Bit 9 set are bad memory blocks. */
2648 if (!(val & (1 << 9))) {
2649 good_mbuf[good_mbuf_cnt] = (u16) val;
2650 good_mbuf_cnt++;
2651 }
2652
2726d6e1 2653 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2654 }
2655
2656 /* Free the good ones back to the mbuf pool thus discarding
2657 * all the bad ones. */
2658 while (good_mbuf_cnt) {
2659 good_mbuf_cnt--;
2660
2661 val = good_mbuf[good_mbuf_cnt];
2662 val = (val << 9) | val | 1;
2663
2726d6e1 2664 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2665 }
2666 kfree(good_mbuf);
2667 return 0;
2668}
2669
2670static void
5fcaed01 2671bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2672{
2673 u32 val;
b6016b76
MC		 2674
2675 val = (mac_addr[0] << 8) | mac_addr[1];
2676
5fcaed01 2677 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2678
6aa20a22 2679 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2680 (mac_addr[4] << 8) | mac_addr[5];
2681
5fcaed01 2682 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2683}
2684
47bf4246 2685static inline int
a2df00aa 2686bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2687{
2688 dma_addr_t mapping;
bb4f98ab 2689 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2690 struct rx_bd *rxbd =
bb4f98ab 2691 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2692 struct page *page = alloc_page(gfp);
47bf4246
MC		 2693
2694 if (!page)
2695 return -ENOMEM;
36227e88 2696 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2697 PCI_DMA_FROMDEVICE);
36227e88 2698 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2699 __free_page(page);
2700 return -EIO;
2701 }
2702
47bf4246 2703 rx_pg->page = page;
1a4ccc2d 2704 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2705 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2706 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2707 return 0;
2708}
2709
2710static void
bb4f98ab 2711bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2712{
bb4f98ab 2713 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2714 struct page *page = rx_pg->page;
2715
2716 if (!page)
2717 return;
2718
36227e88
SG		 2719 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2720 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2721
2722 __free_page(page);
2723 rx_pg->page = NULL;
2724}
2725
b6016b76 2726static inline int
dd2bc8e9 2727bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76 2728{
dd2bc8e9 2729 u8 *data;
bb4f98ab 2730 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2731 dma_addr_t mapping;
bb4f98ab 2732 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76 2733
dd2bc8e9
ED		 2734 data = kmalloc(bp->rx_buf_size, gfp);
2735 if (!data)
b6016b76 2736 return -ENOMEM;
b6016b76 2737
dd2bc8e9
ED		 2738 mapping = dma_map_single(&bp->pdev->dev,
2739 get_l2_fhdr(data),
2740 bp->rx_buf_use_size,
36227e88
SG		 2741 PCI_DMA_FROMDEVICE);
2742 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
dd2bc8e9 2743 kfree(data);
3d16af86
BL		 2744 return -EIO;
2745 }
b6016b76 2746
dd2bc8e9 2747 rx_buf->data = data;
1a4ccc2d 2748 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2749
2750 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2751 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2752
bb4f98ab 2753 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2754
2755 return 0;
2756}
2757
da3e4fbe 2758static int
35efa7c1 2759bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2760{
43e80b89 2761 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2762 u32 new_link_state, old_link_state;
da3e4fbe 2763 int is_set = 1;
b6016b76 2764
da3e4fbe
MC		 2765 new_link_state = sblk->status_attn_bits & event;
2766 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2767 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2768 if (new_link_state)
2769 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2770 else
2771 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2772 } else
2773 is_set = 0;
2774
2775 return is_set;
2776}
2777
2778static void
35efa7c1 2779bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2780{
74ecc62d
MC		 2781 spin_lock(&bp->phy_lock);
2782
2783 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2784 bnx2_set_link(bp);
35efa7c1 2785 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2786 bnx2_set_remote_link(bp);
2787
74ecc62d
MC		 2788 spin_unlock(&bp->phy_lock);
2789
b6016b76
MC		 2790}
2791
ead7270b 2792static inline u16
35efa7c1 2793bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2794{
2795 u16 cons;
2796
43e80b89
MC		 2797 /* Tell compiler that status block fields can change. */
2798 barrier();
2799 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2800 barrier();
ead7270b
MC		 2801 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2802 cons++;
2803 return cons;
2804}
2805
57851d84
MC		 2806static int
2807bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2808{
35e9010b 2809 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2810 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240 2811 int tx_pkt = 0, index;
e9831909 2812 unsigned int tx_bytes = 0;
706bf240
BL		 2813 struct netdev_queue *txq;
2814
2815 index = (bnapi - bp->bnx2_napi);
2816 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2817
35efa7c1 2818 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2819 sw_cons = txr->tx_cons;
b6016b76
MC		 2820
2821 while (sw_cons != hw_cons) {
3d16af86 2822 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2823 struct sk_buff *skb;
2824 int i, last;
2825
2826 sw_ring_cons = TX_RING_IDX(sw_cons);
2827
35e9010b 2828 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2829 skb = tx_buf->skb;
1d39ed56 2830
d62fda08
ED		 2831 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2832 prefetch(&skb->end);
2833
b6016b76 2834 /* partial BD completions possible with TSO packets */
d62fda08 2835 if (tx_buf->is_gso) {
b6016b76
MC		 2836 u16 last_idx, last_ring_idx;
2837
d62fda08
ED		 2838 last_idx = sw_cons + tx_buf->nr_frags + 1;
2839 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2840 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2841 last_idx++;
2842 }
2843 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2844 break;
2845 }
2846 }
1d39ed56 2847
36227e88 2848 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2849 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2850
2851 tx_buf->skb = NULL;
d62fda08 2852 last = tx_buf->nr_frags;
b6016b76
MC		 2853
2854 for (i = 0; i < last; i++) {
2855 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2856
36227e88 2857 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2858 dma_unmap_addr(
e95524a7
AD		 2859 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2860 mapping),
9e903e08 2861 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7 2862 PCI_DMA_TODEVICE);
b6016b76
MC		 2863 }
2864
2865 sw_cons = NEXT_TX_BD(sw_cons);
2866
e9831909 2867 tx_bytes += skb->len;
745720e5 2868 dev_kfree_skb(skb);
57851d84
MC		 2869 tx_pkt++;
2870 if (tx_pkt == budget)
2871 break;
b6016b76 2872
d62fda08
ED		 2873 if (hw_cons == sw_cons)
2874 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2875 }
2876
e9831909 2877 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
35e9010b
MC		 2878 txr->hw_tx_cons = hw_cons;
2879 txr->tx_cons = sw_cons;
706bf240 2880
2f8af120 2881 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2882 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2883 * memory barrier, there is a small possibility that bnx2_start_xmit()
2884 * will miss it and cause the queue to be stopped forever.
2885 */
2886 smp_mb();
b6016b76 2887
706bf240 2888 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2889 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2890 __netif_tx_lock(txq, smp_processor_id());
2891 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2892 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2893 netif_tx_wake_queue(txq);
2894 __netif_tx_unlock(txq);
b6016b76 2895 }
706bf240 2896
57851d84 2897 return tx_pkt;
b6016b76
MC		 2898}
2899
1db82f2a 2900static void
bb4f98ab 2901bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2902 struct sk_buff *skb, int count)
1db82f2a
MC		 2903{
2904 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2905 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2906 int i;
3d16af86 2907 u16 hw_prod, prod;
bb4f98ab 2908 u16 cons = rxr->rx_pg_cons;
1db82f2a 2909
3d16af86
BL		 2910 cons_rx_pg = &rxr->rx_pg_ring[cons];
2911
2912 /* The caller was unable to allocate a new page to replace the
2913 * last one in the frags array, so we need to recycle that page
2914 * and then free the skb.
2915 */
2916 if (skb) {
2917 struct page *page;
2918 struct skb_shared_info *shinfo;
2919
2920 shinfo = skb_shinfo(skb);
2921 shinfo->nr_frags--;
b7b6a688
IC		 2922 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2923 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2924
2925 cons_rx_pg->page = page;
2926 dev_kfree_skb(skb);
2927 }
2928
2929 hw_prod = rxr->rx_pg_prod;
2930
1db82f2a
MC		 2931 for (i = 0; i < count; i++) {
2932 prod = RX_PG_RING_IDX(hw_prod);
2933
bb4f98ab
MC		 2934 prod_rx_pg = &rxr->rx_pg_ring[prod];
2935 cons_rx_pg = &rxr->rx_pg_ring[cons];
2936 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2937 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2938
1db82f2a
MC		 2939 if (prod != cons) {
2940 prod_rx_pg->page = cons_rx_pg->page;
2941 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2942 dma_unmap_addr_set(prod_rx_pg, mapping,
2943 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2944
2945 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2946 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2947
2948 }
2949 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2950 hw_prod = NEXT_RX_BD(hw_prod);
2951 }
bb4f98ab
MC		 2952 rxr->rx_pg_prod = hw_prod;
2953 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2954}
2955
b6016b76 2956static inline void
dd2bc8e9
ED		 2957bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2958 u8 *data, u16 cons, u16 prod)
b6016b76 2959{
236b6394
MC		 2960 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2961 struct rx_bd *cons_bd, *prod_bd;
2962
bb4f98ab
MC		 2963 cons_rx_buf = &rxr->rx_buf_ring[cons];
2964 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2965
36227e88 2966 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2967 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2968 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2969
bb4f98ab 2970 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2971
dd2bc8e9 2972 prod_rx_buf->data = data;
b6016b76 2973
236b6394
MC		 2974 if (cons == prod)
2975 return;
b6016b76 2976
1a4ccc2d
FT		 2977 dma_unmap_addr_set(prod_rx_buf, mapping,
2978 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2979
bb4f98ab
MC		 2980 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2981 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2982 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2983 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2984}
2985
dd2bc8e9
ED		 2986static struct sk_buff *
2987bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
a1f60190
MC		 2988 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2989 u32 ring_idx)
85833c62
MC		 2990{
2991 int err;
2992 u16 prod = ring_idx & 0xffff;
dd2bc8e9 2993 struct sk_buff *skb;
85833c62 2994
dd2bc8e9 2995 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
85833c62 2996 if (unlikely(err)) {
dd2bc8e9
ED		 2997 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
2998error:
1db82f2a
MC		 2999 if (hdr_len) {
3000 unsigned int raw_len = len + 4;
3001 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3002
bb4f98ab 3003 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3004 }
dd2bc8e9 3005 return NULL;
85833c62
MC		 3006 }
3007
36227e88 3008 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62 3009 PCI_DMA_FROMDEVICE);
d3836f21 3010 skb = build_skb(data, 0);
dd2bc8e9
ED		 3011 if (!skb) {
3012 kfree(data);
3013 goto error;
3014 }
3015 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
1db82f2a
MC		 3016 if (hdr_len == 0) {
3017 skb_put(skb, len);
dd2bc8e9 3018 return skb;
1db82f2a
MC		 3019 } else {
3020 unsigned int i, frag_len, frag_size, pages;
3021 struct sw_pg *rx_pg;
bb4f98ab
MC		 3022 u16 pg_cons = rxr->rx_pg_cons;
3023 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3024
3025 frag_size = len + 4 - hdr_len;
3026 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3027 skb_put(skb, hdr_len);
3028
3029 for (i = 0; i < pages; i++) {
3d16af86
BL		 3030 dma_addr_t mapping_old;
3031
1db82f2a
MC		 3032 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3033 if (unlikely(frag_len <= 4)) {
3034 unsigned int tail = 4 - frag_len;
3035
bb4f98ab
MC		 3036 rxr->rx_pg_cons = pg_cons;
3037 rxr->rx_pg_prod = pg_prod;
3038 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3039 pages - i);
1db82f2a
MC		 3040 skb->len -= tail;
3041 if (i == 0) {
3042 skb->tail -= tail;
3043 } else {
3044 skb_frag_t *frag =
3045 &skb_shinfo(skb)->frags[i - 1];
9e903e08 3046 skb_frag_size_sub(frag, tail);
1db82f2a 3047 skb->data_len -= tail;
1db82f2a 3048 }
dd2bc8e9 3049 return skb;
1db82f2a 3050 }
bb4f98ab 3051 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3052
3d16af86
BL		 3053 /* Don't unmap yet. If we're unable to allocate a new
3054 * page, we need to recycle the page and the DMA addr.
3055 */
1a4ccc2d 3056 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3057 if (i == pages - 1)
3058 frag_len -= 4;
3059
3060 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3061 rx_pg->page = NULL;
3062
bb4f98ab 3063 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3064 RX_PG_RING_IDX(pg_prod),
3065 GFP_ATOMIC);
1db82f2a 3066 if (unlikely(err)) {
bb4f98ab
MC		 3067 rxr->rx_pg_cons = pg_cons;
3068 rxr->rx_pg_prod = pg_prod;
3069 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3070 pages - i);
dd2bc8e9 3071 return NULL;
1db82f2a
MC		 3072 }
3073
36227e88 3074 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3075 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3076
1db82f2a
MC		 3077 frag_size -= frag_len;
3078 skb->data_len += frag_len;
a1f4e8bc 3079 skb->truesize += PAGE_SIZE;
1db82f2a
MC		 3080 skb->len += frag_len;
3081
3082 pg_prod = NEXT_RX_BD(pg_prod);
3083 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3084 }
bb4f98ab
MC		 3085 rxr->rx_pg_prod = pg_prod;
3086 rxr->rx_pg_cons = pg_cons;
1db82f2a 3087 }
dd2bc8e9 3088 return skb;
85833c62
MC		 3089}
3090
c09c2627 3091static inline u16
35efa7c1 3092bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3093{
bb4f98ab
MC		 3094 u16 cons;
3095
43e80b89
MC		 3096 /* Tell compiler that status block fields can change. */
3097 barrier();
3098 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3099 barrier();
c09c2627
MC		 3100 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3101 cons++;
3102 return cons;
3103}
3104
b6016b76 3105static int
35efa7c1 3106bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3107{
bb4f98ab 3108 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3109 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3110 struct l2_fhdr *rx_hdr;
1db82f2a 3111 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3112
35efa7c1 3113 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3114 sw_cons = rxr->rx_cons;
3115 sw_prod = rxr->rx_prod;
b6016b76
MC		 3116
3117 /* Memory barrier necessary as speculative reads of the rx
3118 * buffer can be ahead of the index in the status block
3119 */
3120 rmb();
3121 while (sw_cons != hw_cons) {
1db82f2a 3122 unsigned int len, hdr_len;
ade2bfe7 3123 u32 status;
a33fa66b 3124 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3125 struct sk_buff *skb;
236b6394 3126 dma_addr_t dma_addr;
dd2bc8e9 3127 u8 *data;
b6016b76
MC		 3128
3129 sw_ring_cons = RX_RING_IDX(sw_cons);
3130 sw_ring_prod = RX_RING_IDX(sw_prod);
3131
bb4f98ab 3132 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
dd2bc8e9
ED		 3133 data = rx_buf->data;
3134 rx_buf->data = NULL;
aabef8b2 3135
dd2bc8e9
ED		 3136 rx_hdr = get_l2_fhdr(data);
3137 prefetch(rx_hdr);
236b6394 3138
1a4ccc2d 3139 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3140
36227e88 3141 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3142 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3143 PCI_DMA_FROMDEVICE);
b6016b76 3144
dd2bc8e9
ED		 3145 next_rx_buf =
3146 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3147 prefetch(get_l2_fhdr(next_rx_buf->data));
3148
1db82f2a 3149 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3150 status = rx_hdr->l2_fhdr_status;
b6016b76 3151
1db82f2a
MC		 3152 hdr_len = 0;
3153 if (status & L2_FHDR_STATUS_SPLIT) {
3154 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3155 pg_ring_used = 1;
3156 } else if (len > bp->rx_jumbo_thresh) {
3157 hdr_len = bp->rx_jumbo_thresh;
3158 pg_ring_used = 1;
3159 }
3160
990ec380
MC		 3161 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3162 L2_FHDR_ERRORS_PHY_DECODE |
3163 L2_FHDR_ERRORS_ALIGNMENT |
3164 L2_FHDR_ERRORS_TOO_SHORT |
3165 L2_FHDR_ERRORS_GIANT_FRAME))) {
3166
dd2bc8e9 3167 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
990ec380
MC		 3168 sw_ring_prod);
3169 if (pg_ring_used) {
3170 int pages;
3171
3172 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3173
3174 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3175 }
3176 goto next_rx;
3177 }
3178
1db82f2a 3179 len -= 4;
b6016b76 3180
5d5d0015 3181 if (len <= bp->rx_copy_thresh) {
dd2bc8e9
ED		 3182 skb = netdev_alloc_skb(bp->dev, len + 6);
3183 if (skb == NULL) {
3184 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
85833c62
MC		 3185 sw_ring_prod);
3186 goto next_rx;
3187 }
b6016b76
MC		 3188
3189 /* aligned copy */
dd2bc8e9
ED		 3190 memcpy(skb->data,
3191 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3192 len + 6);
3193 skb_reserve(skb, 6);
3194 skb_put(skb, len);
b6016b76 3195
dd2bc8e9 3196 bnx2_reuse_rx_data(bp, rxr, data,
b6016b76
MC		 3197 sw_ring_cons, sw_ring_prod);
3198
dd2bc8e9
ED		 3199 } else {
3200 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3201 (sw_ring_cons << 16) | sw_ring_prod);
3202 if (!skb)
3203 goto next_rx;
3204 }
f22828e8 3205 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211
JG		 3206 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3207 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3208
b6016b76
MC		 3209 skb->protocol = eth_type_trans(skb, bp->dev);
3210
3211 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3212 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3213
745720e5 3214 dev_kfree_skb(skb);
b6016b76
MC		 3215 goto next_rx;
3216
3217 }
3218
bc8acf2c 3219 skb_checksum_none_assert(skb);
8d7dfc2b 3220 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3221 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3222 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3223
ade2bfe7
MC		 3224 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3225 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3226 skb->ip_summed = CHECKSUM_UNNECESSARY;
3227 }
fdc8541d
MC		 3228 if ((bp->dev->features & NETIF_F_RXHASH) &&
3229 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3230 L2_FHDR_STATUS_USE_RXHASH))
3231 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3232
0c8dfc83 3233 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3234 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3235 rx_pkt++;
3236
3237next_rx:
b6016b76
MC		 3238 sw_cons = NEXT_RX_BD(sw_cons);
3239 sw_prod = NEXT_RX_BD(sw_prod);
3240
3241 if ((rx_pkt == budget))
3242 break;
f4e418f7
MC		 3243
3244 /* Refresh hw_cons to see if there is new work */
3245 if (sw_cons == hw_cons) {
35efa7c1 3246 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3247 rmb();
3248 }
b6016b76 3249 }
bb4f98ab
MC		 3250 rxr->rx_cons = sw_cons;
3251 rxr->rx_prod = sw_prod;
b6016b76 3252
1db82f2a 3253 if (pg_ring_used)
bb4f98ab 3254 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3255
bb4f98ab 3256 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3257
bb4f98ab 3258 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3259
3260 mmiowb();
3261
3262 return rx_pkt;
3263
3264}
3265
3266/* MSI ISR - The only difference between this and the INTx ISR
3267 * is that the MSI interrupt is always serviced.
3268 */
3269static irqreturn_t
7d12e780 3270bnx2_msi(int irq, void *dev_instance)
b6016b76 3271{
f0ea2e63
MC		 3272 struct bnx2_napi *bnapi = dev_instance;
3273 struct bnx2 *bp = bnapi->bp;
b6016b76 3274
43e80b89 3275 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3276 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3277 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3278 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3279
3280 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3281 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3282 return IRQ_HANDLED;
b6016b76 3283
288379f0 3284 napi_schedule(&bnapi->napi);
b6016b76 3285
73eef4cd 3286 return IRQ_HANDLED;
b6016b76
MC		 3287}
3288
8e6a72c4
MC		 3289static irqreturn_t
3290bnx2_msi_1shot(int irq, void *dev_instance)
3291{
f0ea2e63
MC		 3292 struct bnx2_napi *bnapi = dev_instance;
3293 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3294
43e80b89 3295 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3296
3297 /* Return here if interrupt is disabled. */
3298 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3299 return IRQ_HANDLED;
3300
288379f0 3301 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3302
3303 return IRQ_HANDLED;
3304}
3305
b6016b76 3306static irqreturn_t
7d12e780 3307bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3308{
f0ea2e63
MC		 3309 struct bnx2_napi *bnapi = dev_instance;
3310 struct bnx2 *bp = bnapi->bp;
43e80b89 3311 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3312
3313 /* When using INTx, it is possible for the interrupt to arrive
3314 * at the CPU before the status block posted prior to the
3315 * interrupt. Reading a register will flush the status block.
3316 * When using MSI, the MSI message will always complete after
3317 * the status block write.
3318 */
35efa7c1 3319 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3320 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3321 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3322 return IRQ_NONE;
b6016b76
MC		 3323
3324 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3325 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3326 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3327
b8a7ce7b
MC		 3328 /* Read back to deassert IRQ immediately to avoid too many
3329 * spurious interrupts.
3330 */
3331 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3332
b6016b76 3333 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3334 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3335 return IRQ_HANDLED;
b6016b76 3336
288379f0 3337 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3338 bnapi->last_status_idx = sblk->status_idx;
288379f0 3339 __napi_schedule(&bnapi->napi);
b8a7ce7b 3340 }
b6016b76 3341
73eef4cd 3342 return IRQ_HANDLED;
b6016b76
MC		 3343}
3344
f4e418f7 3345static inline int
43e80b89 3346bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3347{
35e9010b 3348 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3349 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3350
bb4f98ab 3351 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3352 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3353 return 1;
43e80b89
MC		 3354 return 0;
3355}
3356
3357#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3358 STATUS_ATTN_BITS_TIMER_ABORT)
3359
3360static inline int
3361bnx2_has_work(struct bnx2_napi *bnapi)
3362{
3363 struct status_block *sblk = bnapi->status_blk.msi;
3364
3365 if (bnx2_has_fast_work(bnapi))
3366 return 1;
f4e418f7 3367
4edd473f
MC		 3368#ifdef BCM_CNIC
3369 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3370 return 1;
3371#endif
3372
da3e4fbe
MC		 3373 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3374 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3375 return 1;
3376
3377 return 0;
3378}
3379
efba0180
MC		 3380static void
3381bnx2_chk_missed_msi(struct bnx2 *bp)
3382{
3383 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3384 u32 msi_ctrl;
3385
3386 if (bnx2_has_work(bnapi)) {
3387 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3388 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3389 return;
3390
3391 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3392 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3393 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3394 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3395 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3396 }
3397 }
3398
3399 bp->idle_chk_status_idx = bnapi->last_status_idx;
3400}
3401
4edd473f
MC		 3402#ifdef BCM_CNIC
3403static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3404{
3405 struct cnic_ops *c_ops;
3406
3407 if (!bnapi->cnic_present)
3408 return;
3409
3410 rcu_read_lock();
3411 c_ops = rcu_dereference(bp->cnic_ops);
3412 if (c_ops)
3413 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3414 bnapi->status_blk.msi);
3415 rcu_read_unlock();
3416}
3417#endif
3418
43e80b89 3419static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3420{
43e80b89 3421 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3422 u32 status_attn_bits = sblk->status_attn_bits;
3423 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3424
da3e4fbe
MC		 3425 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3426 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3427
35efa7c1 3428 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3429
3430 /* This is needed to take care of transient status
3431 * during link changes.
3432 */
3433 REG_WR(bp, BNX2_HC_COMMAND,
3434 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3435 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3436 }
43e80b89
MC		 3437}
3438
3439static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3440 int work_done, int budget)
3441{
3442 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3443 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3444
35e9010b 3445 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3446 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3447
bb4f98ab 3448 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3449 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3450
6f535763
DM		 3451 return work_done;
3452}
3453
f0ea2e63
MC		 3454static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3455{
3456 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3457 struct bnx2 *bp = bnapi->bp;
3458 int work_done = 0;
3459 struct status_block_msix *sblk = bnapi->status_blk.msix;
3460
3461 while (1) {
3462 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3463 if (unlikely(work_done >= budget))
3464 break;
3465
3466 bnapi->last_status_idx = sblk->status_idx;
3467 /* status idx must be read before checking for more work. */
3468 rmb();
3469 if (likely(!bnx2_has_fast_work(bnapi))) {
3470
288379f0 3471 napi_complete(napi);
f0ea2e63
MC		 3472 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3473 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3474 bnapi->last_status_idx);
3475 break;
3476 }
3477 }
3478 return work_done;
3479}
3480
6f535763
DM		 3481static int bnx2_poll(struct napi_struct *napi, int budget)
3482{
35efa7c1
MC		 3483 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3484 struct bnx2 *bp = bnapi->bp;
6f535763 3485 int work_done = 0;
43e80b89 3486 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3487
3488 while (1) {
43e80b89
MC		 3489 bnx2_poll_link(bp, bnapi);
3490
35efa7c1 3491 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3492
4edd473f
MC		 3493#ifdef BCM_CNIC
3494 bnx2_poll_cnic(bp, bnapi);
3495#endif
3496
35efa7c1 3497 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3498 * much work has been processed, so we must read it before
3499 * checking for more work.
3500 */
35efa7c1 3501 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3502
3503 if (unlikely(work_done >= budget))
3504 break;
3505
6dee6421 3506 rmb();
35efa7c1 3507 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3508 napi_complete(napi);
f86e82fb 3509 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3510 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3511 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3512 bnapi->last_status_idx);
6dee6421 3513 break;
6f535763 3514 }
1269a8a6
MC		 3515 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3516 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3517 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3518 bnapi->last_status_idx);
1269a8a6 3519
6f535763
DM		 3520 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3521 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3522 bnapi->last_status_idx);
6f535763
DM		 3523 break;
3524 }
b6016b76
MC		 3525 }
3526
bea3348e 3527 return work_done;
b6016b76
MC		 3528}
3529
932ff279 3530/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3531 * from set_multicast.
3532 */
3533static void
3534bnx2_set_rx_mode(struct net_device *dev)
3535{
972ec0d4 3536 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3537 u32 rx_mode, sort_mode;
ccffad25 3538 struct netdev_hw_addr *ha;
b6016b76 3539 int i;
b6016b76 3540
9f52b564
MC		 3541 if (!netif_running(dev))
3542 return;
3543
c770a65c 3544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3545
3546 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3547 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3548 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
7d0fd211
JG		 3549 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3550 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3551 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3552 if (dev->flags & IFF_PROMISC) {
3553 /* Promiscuous mode. */
3554 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3555 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3556 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3557 }
3558 else if (dev->flags & IFF_ALLMULTI) {
3559 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3560 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3561 0xffffffff);
3562 }
3563 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3564 }
3565 else {
3566 /* Accept one or more multicast(s). */
b6016b76
MC		 3567 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3568 u32 regidx;
3569 u32 bit;
3570 u32 crc;
3571
3572 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3573
22bedad3
JP		 3574 netdev_for_each_mc_addr(ha, dev) {
3575 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3576 bit = crc & 0xff;
3577 regidx = (bit & 0xe0) >> 5;
3578 bit &= 0x1f;
3579 mc_filter[regidx] |= (1 << bit);
3580 }
3581
3582 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3583 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3584 mc_filter[i]);
3585 }
3586
3587 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3588 }
3589
32e7bfc4 3590 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3591 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3592 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3593 BNX2_RPM_SORT_USER0_PROM_VLAN;
3594 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3595 /* Add all entries into to the match filter list */
ccffad25 3596 i = 0;
32e7bfc4 3597 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3598 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3599 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3600 sort_mode |= (1 <<
3601 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3602 i++;
5fcaed01
BL		 3603 }
3604
3605 }
3606
b6016b76
MC		 3607 if (rx_mode != bp->rx_mode) {
3608 bp->rx_mode = rx_mode;
3609 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3610 }
3611
3612 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3613 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3614 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3615
c770a65c 3616 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3617}
3618
7880b72e 3619static int
57579f76
MC		 3620check_fw_section(const struct firmware *fw,
3621 const struct bnx2_fw_file_section *section,
3622 u32 alignment, bool non_empty)
3623{
3624 u32 offset = be32_to_cpu(section->offset);
3625 u32 len = be32_to_cpu(section->len);
3626
3627 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3628 return -EINVAL;
3629 if ((non_empty && len == 0) || len > fw->size - offset ||
3630 len & (alignment - 1))
3631 return -EINVAL;
3632 return 0;
3633}
3634
7880b72e 3635static int
57579f76
MC		 3636check_mips_fw_entry(const struct firmware *fw,
3637 const struct bnx2_mips_fw_file_entry *entry)
3638{
3639 if (check_fw_section(fw, &entry->text, 4, true) ||
3640 check_fw_section(fw, &entry->data, 4, false) ||
3641 check_fw_section(fw, &entry->rodata, 4, false))
3642 return -EINVAL;
3643 return 0;
3644}
3645
7880b72e 3646static void bnx2_release_firmware(struct bnx2 *bp)
3647{
3648 if (bp->rv2p_firmware) {
3649 release_firmware(bp->mips_firmware);
3650 release_firmware(bp->rv2p_firmware);
3651 bp->rv2p_firmware = NULL;
3652 }
3653}
3654
3655static int bnx2_request_uncached_firmware(struct bnx2 *bp)
b6016b76 3656{
57579f76 3657 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3658 const struct bnx2_mips_fw_file *mips_fw;
3659 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3660 int rc;
3661
3662 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3663 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3664 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3665 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3666 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3667 else
3668 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3669 } else {
3670 mips_fw_file = FW_MIPS_FILE_06;
3671 rv2p_fw_file = FW_RV2P_FILE_06;
3672 }
3673
3674 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3675 if (rc) {
3a9c6a49 3676 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
7880b72e 3677 goto out;
57579f76
MC		 3678 }
3679
3680 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3681 if (rc) {
3a9c6a49 3682 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
7880b72e 3683 goto err_release_mips_firmware;
57579f76 3684 }
5ee1c326
BB		 3685 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3686 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3687 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3690 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3691 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3692 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3693 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
7880b72e 3694 rc = -EINVAL;
3695 goto err_release_firmware;
57579f76 3696 }
5ee1c326
BB		 3697 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3698 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3699 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3700 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
7880b72e 3701 rc = -EINVAL;
3702 goto err_release_firmware;
57579f76 3703 }
7880b72e 3704out:
3705 return rc;
57579f76 3706
7880b72e 3707err_release_firmware:
3708 release_firmware(bp->rv2p_firmware);
3709 bp->rv2p_firmware = NULL;
3710err_release_mips_firmware:
3711 release_firmware(bp->mips_firmware);
3712 goto out;
3713}
3714
3715static int bnx2_request_firmware(struct bnx2 *bp)
3716{
3717 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
57579f76
MC		 3718}
3719
3720static u32
3721rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3722{
3723 switch (idx) {
3724 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3725 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3726 rv2p_code |= RV2P_BD_PAGE_SIZE;
3727 break;
3728 }
3729 return rv2p_code;
3730}
3731
3732static int
3733load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3734 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3735{
3736 u32 rv2p_code_len, file_offset;
3737 __be32 *rv2p_code;
b6016b76 3738 int i;
57579f76
MC		 3739 u32 val, cmd, addr;
3740
3741 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3742 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3743
3744 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3745
57579f76
MC		 3746 if (rv2p_proc == RV2P_PROC1) {
3747 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3748 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3749 } else {
3750 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3751 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3752 }
b6016b76
MC		 3753
3754 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3755 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3756 rv2p_code++;
57579f76 3757 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3758 rv2p_code++;
3759
57579f76
MC		 3760 val = (i / 8) | cmd;
3761 REG_WR(bp, addr, val);
3762 }
3763
3764 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3765 for (i = 0; i < 8; i++) {
3766 u32 loc, code;
3767
3768 loc = be32_to_cpu(fw_entry->fixup[i]);
3769 if (loc && ((loc * 4) < rv2p_code_len)) {
3770 code = be32_to_cpu(*(rv2p_code + loc - 1));
3771 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3772 code = be32_to_cpu(*(rv2p_code + loc));
3773 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3774 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3775
3776 val = (loc / 2) | cmd;
3777 REG_WR(bp, addr, val);
b6016b76
MC		 3778 }
3779 }
3780
3781 /* Reset the processor, un-stall is done later. */
3782 if (rv2p_proc == RV2P_PROC1) {
3783 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3784 }
3785 else {
3786 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3787 }
57579f76
MC		 3788
3789 return 0;
b6016b76
MC		 3790}
3791
af3ee519 3792static int
57579f76
MC		 3793load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3794 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3795{
57579f76
MC		 3796 u32 addr, len, file_offset;
3797 __be32 *data;
b6016b76
MC		 3798 u32 offset;
3799 u32 val;
3800
3801 /* Halt the CPU. */
2726d6e1 3802 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3803 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3804 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3805 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3806
3807 /* Load the Text area. */
57579f76
MC		 3808 addr = be32_to_cpu(fw_entry->text.addr);
3809 len = be32_to_cpu(fw_entry->text.len);
3810 file_offset = be32_to_cpu(fw_entry->text.offset);
3811 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3812
57579f76
MC		 3813 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3814 if (len) {
b6016b76
MC		 3815 int j;
3816
57579f76
MC		 3817 for (j = 0; j < (len / 4); j++, offset += 4)
3818 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3819 }
3820
57579f76
MC		 3821 /* Load the Data area. */
3822 addr = be32_to_cpu(fw_entry->data.addr);
3823 len = be32_to_cpu(fw_entry->data.len);
3824 file_offset = be32_to_cpu(fw_entry->data.offset);
3825 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3826
57579f76
MC		 3827 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3828 if (len) {
b6016b76
MC		 3829 int j;
3830
57579f76
MC		 3831 for (j = 0; j < (len / 4); j++, offset += 4)
3832 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3833 }
3834
3835 /* Load the Read-Only area. */
57579f76
MC		 3836 addr = be32_to_cpu(fw_entry->rodata.addr);
3837 len = be32_to_cpu(fw_entry->rodata.len);
3838 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3839 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3840
3841 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3842 if (len) {
b6016b76
MC		 3843 int j;
3844
57579f76
MC		 3845 for (j = 0; j < (len / 4); j++, offset += 4)
3846 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3847 }
3848
3849 /* Clear the pre-fetch instruction. */
2726d6e1 3850 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3851
3852 val = be32_to_cpu(fw_entry->start_addr);
3853 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3854
3855 /* Start the CPU. */
2726d6e1 3856 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3857 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3858 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3859 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3860
3861 return 0;
b6016b76
MC		 3862}
3863
fba9fe91 3864static int
b6016b76
MC		 3865bnx2_init_cpus(struct bnx2 *bp)
3866{
57579f76
MC		 3867 const struct bnx2_mips_fw_file *mips_fw =
3868 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3869 const struct bnx2_rv2p_fw_file *rv2p_fw =
3870 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3871 int rc;
b6016b76
MC		 3872
3873 /* Initialize the RV2P processor. */
57579f76
MC		 3874 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3875 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3876
3877 /* Initialize the RX Processor. */
57579f76 3878 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3879 if (rc)
3880 goto init_cpu_err;
3881
b6016b76 3882 /* Initialize the TX Processor. */
57579f76 3883 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3884 if (rc)
3885 goto init_cpu_err;
3886
b6016b76 3887 /* Initialize the TX Patch-up Processor. */
57579f76 3888 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3889 if (rc)
3890 goto init_cpu_err;
3891
b6016b76 3892 /* Initialize the Completion Processor. */
57579f76 3893 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3894 if (rc)
3895 goto init_cpu_err;
3896
d43584c8 3897 /* Initialize the Command Processor. */
57579f76 3898 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3899
fba9fe91 3900init_cpu_err:
fba9fe91 3901 return rc;
b6016b76
MC		 3902}
3903
3904static int
829ca9a3 3905bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3906{
3907 u16 pmcsr;
3908
3909 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3910
3911 switch (state) {
829ca9a3 3912 case PCI_D0: {
b6016b76
MC		 3913 u32 val;
3914
3915 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3916 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3917 PCI_PM_CTRL_PME_STATUS);
3918
3919 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3920 /* delay required during transition out of D3hot */
3921 msleep(20);
3922
3923 val = REG_RD(bp, BNX2_EMAC_MODE);
3924 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3925 val &= ~BNX2_EMAC_MODE_MPKT;
3926 REG_WR(bp, BNX2_EMAC_MODE, val);
3927
3928 val = REG_RD(bp, BNX2_RPM_CONFIG);
3929 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3930 REG_WR(bp, BNX2_RPM_CONFIG, val);
3931 break;
3932 }
829ca9a3 3933 case PCI_D3hot: {
b6016b76
MC		 3934 int i;
3935 u32 val, wol_msg;
3936
3937 if (bp->wol) {
3938 u32 advertising;
3939 u8 autoneg;
3940
3941 autoneg = bp->autoneg;
3942 advertising = bp->advertising;
3943
239cd343
MC		 3944 if (bp->phy_port == PORT_TP) {
3945 bp->autoneg = AUTONEG_SPEED;
3946 bp->advertising = ADVERTISED_10baseT_Half |
3947 ADVERTISED_10baseT_Full |
3948 ADVERTISED_100baseT_Half |
3949 ADVERTISED_100baseT_Full |
3950 ADVERTISED_Autoneg;
3951 }
b6016b76 3952
239cd343
MC		 3953 spin_lock_bh(&bp->phy_lock);
3954 bnx2_setup_phy(bp, bp->phy_port);
3955 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3956
3957 bp->autoneg = autoneg;
3958 bp->advertising = advertising;
3959
5fcaed01 3960 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3961
3962 val = REG_RD(bp, BNX2_EMAC_MODE);
3963
3964 /* Enable port mode. */
3965 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3966 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3967 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3968 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3969 if (bp->phy_port == PORT_TP)
3970 val |= BNX2_EMAC_MODE_PORT_MII;
3971 else {
3972 val |= BNX2_EMAC_MODE_PORT_GMII;
3973 if (bp->line_speed == SPEED_2500)
3974 val |= BNX2_EMAC_MODE_25G_MODE;
3975 }
b6016b76
MC		 3976
3977 REG_WR(bp, BNX2_EMAC_MODE, val);
3978
3979 /* receive all multicast */
3980 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3981 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3982 0xffffffff);
3983 }
3984 REG_WR(bp, BNX2_EMAC_RX_MODE,
3985 BNX2_EMAC_RX_MODE_SORT_MODE);
3986
3987 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3988 BNX2_RPM_SORT_USER0_MC_EN;
3989 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3990 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3991 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3992 BNX2_RPM_SORT_USER0_ENA);
3993
3994 /* Need to enable EMAC and RPM for WOL. */
3995 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3996 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3997 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3998 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3999
4000 val = REG_RD(bp, BNX2_RPM_CONFIG);
4001 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4002 REG_WR(bp, BNX2_RPM_CONFIG, val);
4003
4004 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4005 }
4006 else {
4007 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4008 }
4009
f86e82fb 4010 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 4011 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4012 1, 0);
b6016b76
MC		 4013
4014 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4015 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4016 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4017
4018 if (bp->wol)
4019 pmcsr |= 3;
4020 }
4021 else {
4022 pmcsr |= 3;
4023 }
4024 if (bp->wol) {
4025 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4026 }
4027 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4028 pmcsr);
4029
4030 /* No more memory access after this point until
4031 * device is brought back to D0.
4032 */
4033 udelay(50);
4034 break;
4035 }
4036 default:
4037 return -EINVAL;
4038 }
4039 return 0;
4040}
4041
4042static int
4043bnx2_acquire_nvram_lock(struct bnx2 *bp)
4044{
4045 u32 val;
4046 int j;
4047
4048 /* Request access to the flash interface. */
4049 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4050 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4051 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4052 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4053 break;
4054
4055 udelay(5);
4056 }
4057
4058 if (j >= NVRAM_TIMEOUT_COUNT)
4059 return -EBUSY;
4060
4061 return 0;
4062}
4063
4064static int
4065bnx2_release_nvram_lock(struct bnx2 *bp)
4066{
4067 int j;
4068 u32 val;
4069
4070 /* Relinquish nvram interface. */
4071 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4072
4073 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4074 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4075 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4076 break;
4077
4078 udelay(5);
4079 }
4080
4081 if (j >= NVRAM_TIMEOUT_COUNT)
4082 return -EBUSY;
4083
4084 return 0;
4085}
4086
4087
4088static int
4089bnx2_enable_nvram_write(struct bnx2 *bp)
4090{
4091 u32 val;
4092
4093 val = REG_RD(bp, BNX2_MISC_CFG);
4094 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4095
e30372c9 4096 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4097 int j;
4098
4099 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4100 REG_WR(bp, BNX2_NVM_COMMAND,
4101 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4102
4103 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4104 udelay(5);
4105
4106 val = REG_RD(bp, BNX2_NVM_COMMAND);
4107 if (val & BNX2_NVM_COMMAND_DONE)
4108 break;
4109 }
4110
4111 if (j >= NVRAM_TIMEOUT_COUNT)
4112 return -EBUSY;
4113 }
4114 return 0;
4115}
4116
4117static void
4118bnx2_disable_nvram_write(struct bnx2 *bp)
4119{
4120 u32 val;
4121
4122 val = REG_RD(bp, BNX2_MISC_CFG);
4123 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4124}
4125
4126
4127static void
4128bnx2_enable_nvram_access(struct bnx2 *bp)
4129{
4130 u32 val;
4131
4132 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4133 /* Enable both bits, even on read. */
6aa20a22 4134 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4135 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4136}
4137
4138static void
4139bnx2_disable_nvram_access(struct bnx2 *bp)
4140{
4141 u32 val;
4142
4143 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4144 /* Disable both bits, even after read. */
6aa20a22 4145 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4146 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4147 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4148}
4149
4150static int
4151bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4152{
4153 u32 cmd;
4154 int j;
4155
e30372c9 4156 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4157 /* Buffered flash, no erase needed */
4158 return 0;
4159
4160 /* Build an erase command */
4161 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4162 BNX2_NVM_COMMAND_DOIT;
4163
4164 /* Need to clear DONE bit separately. */
4165 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4166
4167 /* Address of the NVRAM to read from. */
4168 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4169
4170 /* Issue an erase command. */
4171 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4172
4173 /* Wait for completion. */
4174 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4175 u32 val;
4176
4177 udelay(5);
4178
4179 val = REG_RD(bp, BNX2_NVM_COMMAND);
4180 if (val & BNX2_NVM_COMMAND_DONE)
4181 break;
4182 }
4183
4184 if (j >= NVRAM_TIMEOUT_COUNT)
4185 return -EBUSY;
4186
4187 return 0;
4188}
4189
4190static int
4191bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4192{
4193 u32 cmd;
4194 int j;
4195
4196 /* Build the command word. */
4197 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4198
e30372c9
MC		 4199 /* Calculate an offset of a buffered flash, not needed for 5709. */
4200 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4201 offset = ((offset / bp->flash_info->page_size) <<
4202 bp->flash_info->page_bits) +
4203 (offset % bp->flash_info->page_size);
4204 }
4205
4206 /* Need to clear DONE bit separately. */
4207 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4208
4209 /* Address of the NVRAM to read from. */
4210 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4211
4212 /* Issue a read command. */
4213 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4214
4215 /* Wait for completion. */
4216 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4217 u32 val;
4218
4219 udelay(5);
4220
4221 val = REG_RD(bp, BNX2_NVM_COMMAND);
4222 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4223 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4224 memcpy(ret_val, &v, 4);
b6016b76
MC		 4225 break;
4226 }
4227 }
4228 if (j >= NVRAM_TIMEOUT_COUNT)
4229 return -EBUSY;
4230
4231 return 0;
4232}
4233
4234
4235static int
4236bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4237{
b491edd5
AV		 4238 u32 cmd;
4239 __be32 val32;
b6016b76
MC		 4240 int j;
4241
4242 /* Build the command word. */
4243 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4244
e30372c9
MC		 4245 /* Calculate an offset of a buffered flash, not needed for 5709. */
4246 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4247 offset = ((offset / bp->flash_info->page_size) <<
4248 bp->flash_info->page_bits) +
4249 (offset % bp->flash_info->page_size);
4250 }
4251
4252 /* Need to clear DONE bit separately. */
4253 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4254
4255 memcpy(&val32, val, 4);
b6016b76
MC		 4256
4257 /* Write the data. */
b491edd5 4258 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4259
4260 /* Address of the NVRAM to write to. */
4261 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4262
4263 /* Issue the write command. */
4264 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4265
4266 /* Wait for completion. */
4267 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4268 udelay(5);
4269
4270 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4271 break;
4272 }
4273 if (j >= NVRAM_TIMEOUT_COUNT)
4274 return -EBUSY;
4275
4276 return 0;
4277}
4278
4279static int
4280bnx2_init_nvram(struct bnx2 *bp)
4281{
4282 u32 val;
e30372c9 4283 int j, entry_count, rc = 0;
0ced9d01 4284 const struct flash_spec *flash;
b6016b76 4285
e30372c9
MC		 4286 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4287 bp->flash_info = &flash_5709;
4288 goto get_flash_size;
4289 }
4290
b6016b76
MC		 4291 /* Determine the selected interface. */
4292 val = REG_RD(bp, BNX2_NVM_CFG1);
4293
ff8ac609 4294 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4295
b6016b76
MC		 4296 if (val & 0x40000000) {
4297
4298 /* Flash interface has been reconfigured */
4299 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4300 j++, flash++) {
4301 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4302 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4303 bp->flash_info = flash;
4304 break;
4305 }
4306 }
4307 }
4308 else {
37137709 4309 u32 mask;
b6016b76
MC		 4310 /* Not yet been reconfigured */
4311
37137709
MC		 4312 if (val & (1 << 23))
4313 mask = FLASH_BACKUP_STRAP_MASK;
4314 else
4315 mask = FLASH_STRAP_MASK;
4316
b6016b76
MC		 4317 for (j = 0, flash = &flash_table[0]; j < entry_count;
4318 j++, flash++) {
4319
37137709 4320 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4321 bp->flash_info = flash;
4322
4323 /* Request access to the flash interface. */
4324 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4325 return rc;
4326
4327 /* Enable access to flash interface */
4328 bnx2_enable_nvram_access(bp);
4329
4330 /* Reconfigure the flash interface */
4331 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4332 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4333 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4334 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4335
4336 /* Disable access to flash interface */
4337 bnx2_disable_nvram_access(bp);
4338 bnx2_release_nvram_lock(bp);
4339
4340 break;
4341 }
4342 }
4343 } /* if (val & 0x40000000) */
4344
4345 if (j == entry_count) {
4346 bp->flash_info = NULL;
3a9c6a49 4347 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4348 return -ENODEV;
b6016b76
MC		 4349 }
4350
e30372c9 4351get_flash_size:
2726d6e1 4352 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4353 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4354 if (val)
4355 bp->flash_size = val;
4356 else
4357 bp->flash_size = bp->flash_info->total_size;
4358
b6016b76
MC		 4359 return rc;
4360}
4361
4362static int
4363bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4364 int buf_size)
4365{
4366 int rc = 0;
4367 u32 cmd_flags, offset32, len32, extra;
4368
4369 if (buf_size == 0)
4370 return 0;
4371
4372 /* Request access to the flash interface. */
4373 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4374 return rc;
4375
4376 /* Enable access to flash interface */
4377 bnx2_enable_nvram_access(bp);
4378
4379 len32 = buf_size;
4380 offset32 = offset;
4381 extra = 0;
4382
4383 cmd_flags = 0;
4384
4385 if (offset32 & 3) {
4386 u8 buf[4];
4387 u32 pre_len;
4388
4389 offset32 &= ~3;
4390 pre_len = 4 - (offset & 3);
4391
4392 if (pre_len >= len32) {
4393 pre_len = len32;
4394 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4395 BNX2_NVM_COMMAND_LAST;
4396 }
4397 else {
4398 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4399 }
4400
4401 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4402
4403 if (rc)
4404 return rc;
4405
4406 memcpy(ret_buf, buf + (offset & 3), pre_len);
4407
4408 offset32 += 4;
4409 ret_buf += pre_len;
4410 len32 -= pre_len;
4411 }
4412 if (len32 & 3) {
4413 extra = 4 - (len32 & 3);
4414 len32 = (len32 + 4) & ~3;
4415 }
4416
4417 if (len32 == 4) {
4418 u8 buf[4];
4419
4420 if (cmd_flags)
4421 cmd_flags = BNX2_NVM_COMMAND_LAST;
4422 else
4423 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4424 BNX2_NVM_COMMAND_LAST;
4425
4426 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4427
4428 memcpy(ret_buf, buf, 4 - extra);
4429 }
4430 else if (len32 > 0) {
4431 u8 buf[4];
4432
4433 /* Read the first word. */
4434 if (cmd_flags)
4435 cmd_flags = 0;
4436 else
4437 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4438
4439 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4440
4441 /* Advance to the next dword. */
4442 offset32 += 4;
4443 ret_buf += 4;
4444 len32 -= 4;
4445
4446 while (len32 > 4 && rc == 0) {
4447 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4448
4449 /* Advance to the next dword. */
4450 offset32 += 4;
4451 ret_buf += 4;
4452 len32 -= 4;
4453 }
4454
4455 if (rc)
4456 return rc;
4457
4458 cmd_flags = BNX2_NVM_COMMAND_LAST;
4459 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4460
4461 memcpy(ret_buf, buf, 4 - extra);
4462 }
4463
4464 /* Disable access to flash interface */
4465 bnx2_disable_nvram_access(bp);
4466
4467 bnx2_release_nvram_lock(bp);
4468
4469 return rc;
4470}
4471
4472static int
4473bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4474 int buf_size)
4475{
4476 u32 written, offset32, len32;
e6be763f 4477 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4478 int rc = 0;
4479 int align_start, align_end;
4480
4481 buf = data_buf;
4482 offset32 = offset;
4483 len32 = buf_size;
4484 align_start = align_end = 0;
4485
4486 if ((align_start = (offset32 & 3))) {
4487 offset32 &= ~3;
c873879c
MC		 4488 len32 += align_start;
4489 if (len32 < 4)
4490 len32 = 4;
b6016b76
MC		 4491 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4492 return rc;
4493 }
4494
4495 if (len32 & 3) {
c873879c
MC		 4496 align_end = 4 - (len32 & 3);
4497 len32 += align_end;
4498 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4499 return rc;
b6016b76
MC		 4500 }
4501
4502 if (align_start || align_end) {
e6be763f
MC		 4503 align_buf = kmalloc(len32, GFP_KERNEL);
4504 if (align_buf == NULL)
b6016b76
MC		 4505 return -ENOMEM;
4506 if (align_start) {
e6be763f 4507 memcpy(align_buf, start, 4);
b6016b76
MC		 4508 }
4509 if (align_end) {
e6be763f 4510 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4511 }
e6be763f
MC		 4512 memcpy(align_buf + align_start, data_buf, buf_size);
4513 buf = align_buf;
b6016b76
MC		 4514 }
4515
e30372c9 4516 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4517 flash_buffer = kmalloc(264, GFP_KERNEL);
4518 if (flash_buffer == NULL) {
4519 rc = -ENOMEM;
4520 goto nvram_write_end;
4521 }
4522 }
4523
b6016b76
MC		 4524 written = 0;
4525 while ((written < len32) && (rc == 0)) {
4526 u32 page_start, page_end, data_start, data_end;
4527 u32 addr, cmd_flags;
4528 int i;
b6016b76
MC		 4529
4530 /* Find the page_start addr */
4531 page_start = offset32 + written;
4532 page_start -= (page_start % bp->flash_info->page_size);
4533 /* Find the page_end addr */
4534 page_end = page_start + bp->flash_info->page_size;
4535 /* Find the data_start addr */
4536 data_start = (written == 0) ? offset32 : page_start;
4537 /* Find the data_end addr */
6aa20a22 4538 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4539 (offset32 + len32) : page_end;
4540
4541 /* Request access to the flash interface. */
4542 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4543 goto nvram_write_end;
4544
4545 /* Enable access to flash interface */
4546 bnx2_enable_nvram_access(bp);
4547
4548 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4549 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4550 int j;
4551
4552 /* Read the whole page into the buffer
4553 * (non-buffer flash only) */
4554 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4555 if (j == (bp->flash_info->page_size - 4)) {
4556 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4557 }
4558 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4559 page_start + j,
4560 &flash_buffer[j],
b6016b76
MC		 4561 cmd_flags);
4562
4563 if (rc)
4564 goto nvram_write_end;
4565
4566 cmd_flags = 0;
4567 }
4568 }
4569
4570 /* Enable writes to flash interface (unlock write-protect) */
4571 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4572 goto nvram_write_end;
4573
b6016b76
MC		 4574 /* Loop to write back the buffer data from page_start to
4575 * data_start */
4576 i = 0;
e30372c9 4577 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4578 /* Erase the page */
4579 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4580 goto nvram_write_end;
4581
4582 /* Re-enable the write again for the actual write */
4583 bnx2_enable_nvram_write(bp);
4584
b6016b76
MC		 4585 for (addr = page_start; addr < data_start;
4586 addr += 4, i += 4) {
6aa20a22 4587
b6016b76
MC		 4588 rc = bnx2_nvram_write_dword(bp, addr,
4589 &flash_buffer[i], cmd_flags);
4590
4591 if (rc != 0)
4592 goto nvram_write_end;
4593
4594 cmd_flags = 0;
4595 }
4596 }
4597
4598 /* Loop to write the new data from data_start to data_end */
bae25761 4599 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4600 if ((addr == page_end - 4) ||
e30372c9 4601 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4602 (addr == data_end - 4))) {
4603
4604 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4605 }
4606 rc = bnx2_nvram_write_dword(bp, addr, buf,
4607 cmd_flags);
4608
4609 if (rc != 0)
4610 goto nvram_write_end;
4611
4612 cmd_flags = 0;
4613 buf += 4;
4614 }
4615
4616 /* Loop to write back the buffer data from data_end
4617 * to page_end */
e30372c9 4618 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4619 for (addr = data_end; addr < page_end;
4620 addr += 4, i += 4) {
6aa20a22 4621
b6016b76
MC		 4622 if (addr == page_end-4) {
4623 cmd_flags = BNX2_NVM_COMMAND_LAST;
4624 }
4625 rc = bnx2_nvram_write_dword(bp, addr,
4626 &flash_buffer[i], cmd_flags);
4627
4628 if (rc != 0)
4629 goto nvram_write_end;
4630
4631 cmd_flags = 0;
4632 }
4633 }
4634
4635 /* Disable writes to flash interface (lock write-protect) */
4636 bnx2_disable_nvram_write(bp);
4637
4638 /* Disable access to flash interface */
4639 bnx2_disable_nvram_access(bp);
4640 bnx2_release_nvram_lock(bp);
4641
4642 /* Increment written */
4643 written += data_end - data_start;
4644 }
4645
4646nvram_write_end:
e6be763f
MC		 4647 kfree(flash_buffer);
4648 kfree(align_buf);
b6016b76
MC		 4649 return rc;
4650}
4651
0d8a6571 4652static void
7c62e83b 4653bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4654{
7c62e83b 4655 u32 val, sig = 0;
0d8a6571 4656
583c28e5 4657 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4658 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4659
4660 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4661 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4662
2726d6e1 4663 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4664 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4665 return;
4666
7c62e83b
MC		 4667 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4668 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4669 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4670 }
4671
4672 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4673 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4674 u32 link;
4675
583c28e5 4676 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4677
7c62e83b
MC		 4678 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4679 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4680 bp->phy_port = PORT_FIBRE;
4681 else
4682 bp->phy_port = PORT_TP;
489310a4 4683
7c62e83b
MC		 4684 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4685 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4686 }
7c62e83b
MC		 4687
4688 if (netif_running(bp->dev) && sig)
4689 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4690}
4691
b4b36042
MC		 4692static void
4693bnx2_setup_msix_tbl(struct bnx2 *bp)
4694{
4695 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4696
4697 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4698 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4699}
4700
b6016b76
MC		 4701static int
4702bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4703{
4704 u32 val;
4705 int i, rc = 0;
489310a4 4706 u8 old_port;
b6016b76
MC		 4707
4708 /* Wait for the current PCI transaction to complete before
4709 * issuing a reset. */
a5dac108
EW		 4710 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4711 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4712 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4713 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4714 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4715 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4716 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4717 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4718 udelay(5);
4719 } else { /* 5709 */
4720 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4721 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4722 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4723 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4724
4725 for (i = 0; i < 100; i++) {
4726 msleep(1);
4727 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4728 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4729 break;
4730 }
4731 }
b6016b76 4732
b090ae2b 4733 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4734 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4735
b6016b76
MC		 4736 /* Deposit a driver reset signature so the firmware knows that
4737 * this is a soft reset. */
2726d6e1
MC		 4738 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4739 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4740
b6016b76
MC		 4741 /* Do a dummy read to force the chip to complete all current transaction
4742 * before we issue a reset. */
4743 val = REG_RD(bp, BNX2_MISC_ID);
4744
234754d5
MC		 4745 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4746 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4747 REG_RD(bp, BNX2_MISC_COMMAND);
4748 udelay(5);
b6016b76 4749
234754d5
MC		 4750 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4751 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4752
be7ff1af 4753 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4754
234754d5
MC		 4755 } else {
4756 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4757 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4758 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4759
4760 /* Chip reset. */
4761 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4762
594a9dfa
MC		 4763 /* Reading back any register after chip reset will hang the
4764 * bus on 5706 A0 and A1. The msleep below provides plenty
4765 * of margin for write posting.
4766 */
234754d5 4767 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4768 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4769 msleep(20);
b6016b76 4770
234754d5
MC		 4771 /* Reset takes approximate 30 usec */
4772 for (i = 0; i < 10; i++) {
4773 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4774 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4775 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4776 break;
4777 udelay(10);
4778 }
4779
4780 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4781 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4782 pr_err("Chip reset did not complete\n");
234754d5
MC		 4783 return -EBUSY;
4784 }
b6016b76
MC		 4785 }
4786
4787 /* Make sure byte swapping is properly configured. */
4788 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4789 if (val != 0x01020304) {
3a9c6a49 4790 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4791 return -ENODEV;
4792 }
4793
b6016b76 4794 /* Wait for the firmware to finish its initialization. */
a2f13890 4795 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4796 if (rc)
4797 return rc;
b6016b76 4798
0d8a6571 4799 spin_lock_bh(&bp->phy_lock);
489310a4 4800 old_port = bp->phy_port;
7c62e83b 4801 bnx2_init_fw_cap(bp);
583c28e5
MC		 4802 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4803 old_port != bp->phy_port)
0d8a6571
MC		 4804 bnx2_set_default_remote_link(bp);
4805 spin_unlock_bh(&bp->phy_lock);
4806
b6016b76
MC		 4807 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4808 /* Adjust the voltage regular to two steps lower. The default
4809 * of this register is 0x0000000e. */
4810 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4811
4812 /* Remove bad rbuf memory from the free pool. */
4813 rc = bnx2_alloc_bad_rbuf(bp);
4814 }
4815
c441b8d2 4816 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4817 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4818 /* Prevent MSIX table reads and write from timing out */
4819 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4820 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4821 }
b4b36042 4822
b6016b76
MC		 4823 return rc;
4824}
4825
4826static int
4827bnx2_init_chip(struct bnx2 *bp)
4828{
d8026d93 4829 u32 val, mtu;
b4b36042 4830 int rc, i;
b6016b76
MC		 4831
4832 /* Make sure the interrupt is not active. */
4833 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4834
4835 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4836 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4837#ifdef __BIG_ENDIAN
6aa20a22 4838 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4839#endif
6aa20a22 4840 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4841 DMA_READ_CHANS << 12 |
4842 DMA_WRITE_CHANS << 16;
4843
4844 val |= (0x2 << 20) | (1 << 11);
4845
f86e82fb 4846 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4847 val |= (1 << 23);
4848
4849 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4850 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4851 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4852
4853 REG_WR(bp, BNX2_DMA_CONFIG, val);
4854
4855 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4856 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4857 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4858 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4859 }
4860
f86e82fb 4861 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4862 u16 val16;
4863
4864 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4865 &val16);
4866 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4867 val16 & ~PCI_X_CMD_ERO);
4868 }
4869
4870 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4871 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4872 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4873 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4874
4875 /* Initialize context mapping and zero out the quick contexts. The
4876 * context block must have already been enabled. */
641bdcd5
MC		 4877 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4878 rc = bnx2_init_5709_context(bp);
4879 if (rc)
4880 return rc;
4881 } else
59b47d8a 4882 bnx2_init_context(bp);
b6016b76 4883
fba9fe91
MC		 4884 if ((rc = bnx2_init_cpus(bp)) != 0)
4885 return rc;
4886
b6016b76
MC		 4887 bnx2_init_nvram(bp);
4888
5fcaed01 4889 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4890
4891 val = REG_RD(bp, BNX2_MQ_CONFIG);
4892 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4893 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4894 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4895 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4896 if (CHIP_REV(bp) == CHIP_REV_Ax)
4897 val |= BNX2_MQ_CONFIG_HALT_DIS;
4898 }
68c9f75a 4899
b6016b76
MC		 4900 REG_WR(bp, BNX2_MQ_CONFIG, val);
4901
4902 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4903 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4904 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4905
4906 val = (BCM_PAGE_BITS - 8) << 24;
4907 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4908
4909 /* Configure page size. */
4910 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4911 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4912 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4913 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4914
4915 val = bp->mac_addr[0] +
4916 (bp->mac_addr[1] << 8) +
4917 (bp->mac_addr[2] << 16) +
4918 bp->mac_addr[3] +
4919 (bp->mac_addr[4] << 8) +
4920 (bp->mac_addr[5] << 16);
4921 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4922
4923 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4924 mtu = bp->dev->mtu;
4925 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4926 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4927 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4928 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4929
d8026d93
MC		 4930 if (mtu < 1500)
4931 mtu = 1500;
4932
4933 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4934 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4935 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4936
155d5561 4937 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4938 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4939 bp->bnx2_napi[i].last_status_idx = 0;
4940
efba0180
MC		 4941 bp->idle_chk_status_idx = 0xffff;
4942
b6016b76
MC		 4943 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4944
4945 /* Set up how to generate a link change interrupt. */
4946 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4947
4948 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4949 (u64) bp->status_blk_mapping & 0xffffffff);
4950 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4951
4952 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4953 (u64) bp->stats_blk_mapping & 0xffffffff);
4954 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4955 (u64) bp->stats_blk_mapping >> 32);
4956
6aa20a22 4957 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4958 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4959
4960 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4961 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4962
4963 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4964 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4965
4966 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4967
4968 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4969
4970 REG_WR(bp, BNX2_HC_COM_TICKS,
4971 (bp->com_ticks_int << 16) | bp->com_ticks);
4972
4973 REG_WR(bp, BNX2_HC_CMD_TICKS,
4974 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4975
61d9e3fa 4976 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4977 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4978 else
7ea6920e 4979 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4980 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4981
4982 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4983 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4984 else {
8e6a72c4
MC		 4985 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4986 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4987 }
4988
efde73a3 4989 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4990 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4991 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4992
5e9ad9e1
MC		 4993 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4994 }
4995
4996 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4997 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4998
4999 REG_WR(bp, BNX2_HC_CONFIG, val);
5000
22fa159d
MC		 5001 if (bp->rx_ticks < 25)
5002 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5003 else
5004 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5005
5e9ad9e1
MC		 5006 for (i = 1; i < bp->irq_nvecs; i++) {
5007 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5008 BNX2_HC_SB_CONFIG_1;
5009
6f743ca0 5010 REG_WR(bp, base,
c76c0475 5011 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 5012 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 5013 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5014
6f743ca0 5015 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5016 (bp->tx_quick_cons_trip_int << 16) |
5017 bp->tx_quick_cons_trip);
5018
6f743ca0 5019 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5020 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5021
5e9ad9e1
MC		 5022 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5023 (bp->rx_quick_cons_trip_int << 16) |
5024 bp->rx_quick_cons_trip);
8e6a72c4 5025
5e9ad9e1
MC		 5026 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5027 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5028 }
8e6a72c4 5029
b6016b76
MC		 5030 /* Clear internal stats counters. */
5031 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5032
da3e4fbe 5033 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5034
5035 /* Initialize the receive filter. */
5036 bnx2_set_rx_mode(bp->dev);
5037
0aa38df7
MC		 5038 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5039 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5040 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5041 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5042 }
b090ae2b 5043 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5044 1, 0);
b6016b76 5045
df149d70 5046 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5047 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5048
5049 udelay(20);
5050
bf5295bb
MC		 5051 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5052
b090ae2b 5053 return rc;
b6016b76
MC		 5054}
5055
c76c0475
MC		 5056static void
5057bnx2_clear_ring_states(struct bnx2 *bp)
5058{
5059 struct bnx2_napi *bnapi;
35e9010b 5060 struct bnx2_tx_ring_info *txr;
bb4f98ab 5061 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5062 int i;
5063
5064 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5065 bnapi = &bp->bnx2_napi[i];
35e9010b 5066 txr = &bnapi->tx_ring;
bb4f98ab 5067 rxr = &bnapi->rx_ring;
c76c0475 5068
35e9010b
MC		 5069 txr->tx_cons = 0;
5070 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5071 rxr->rx_prod_bseq = 0;
5072 rxr->rx_prod = 0;
5073 rxr->rx_cons = 0;
5074 rxr->rx_pg_prod = 0;
5075 rxr->rx_pg_cons = 0;
c76c0475
MC		 5076 }
5077}
5078
59b47d8a 5079static void
35e9010b 5080bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5081{
5082 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5083 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5084
5085 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5086 offset0 = BNX2_L2CTX_TYPE_XI;
5087 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5088 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5089 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5090 } else {
5091 offset0 = BNX2_L2CTX_TYPE;
5092 offset1 = BNX2_L2CTX_CMD_TYPE;
5093 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5094 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5095 }
5096 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5097 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5098
5099 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5100 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5101
35e9010b 5102 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5103 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5104
35e9010b 5105 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5106 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5107}
b6016b76
MC		 5108
5109static void
35e9010b 5110bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5111{
5112 struct tx_bd *txbd;
c76c0475
MC		 5113 u32 cid = TX_CID;
5114 struct bnx2_napi *bnapi;
35e9010b 5115 struct bnx2_tx_ring_info *txr;
c76c0475 5116
35e9010b
MC		 5117 bnapi = &bp->bnx2_napi[ring_num];
5118 txr = &bnapi->tx_ring;
5119
5120 if (ring_num == 0)
5121 cid = TX_CID;
5122 else
5123 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5124
2f8af120
MC		 5125 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5126
35e9010b 5127 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5128
35e9010b
MC		 5129 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5130 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5131
35e9010b
MC		 5132 txr->tx_prod = 0;
5133 txr->tx_prod_bseq = 0;
6aa20a22 5134
35e9010b
MC		 5135 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5136 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5137
35e9010b 5138 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5139}
5140
5141static void
5d5d0015
MC		 5142bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5143 int num_rings)
b6016b76 5144{
b6016b76 5145 int i;
5d5d0015 5146 struct rx_bd *rxbd;
6aa20a22 5147
5d5d0015 5148 for (i = 0; i < num_rings; i++) {
13daffa2 5149 int j;
b6016b76 5150
5d5d0015 5151 rxbd = &rx_ring[i][0];
13daffa2 5152 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5153 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5154 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5155 }
5d5d0015 5156 if (i == (num_rings - 1))
13daffa2
MC		 5157 j = 0;
5158 else
5159 j = i + 1;
5d5d0015
MC		 5160 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5161 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5162 }
5d5d0015
MC		 5163}
5164
5165static void
bb4f98ab 5166bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5167{
5168 int i;
5169 u16 prod, ring_prod;
bb4f98ab
MC		 5170 u32 cid, rx_cid_addr, val;
5171 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5172 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5173
5174 if (ring_num == 0)
5175 cid = RX_CID;
5176 else
5177 cid = RX_RSS_CID + ring_num - 1;
5178
5179 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5180
bb4f98ab 5181 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5182 bp->rx_buf_use_size, bp->rx_max_ring);
5183
bb4f98ab 5184 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5185
5186 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5187 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5188 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5189 }
5190
62a8313c 5191 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5192 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5193 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5194 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5195 PAGE_SIZE, bp->rx_max_pg_ring);
5196 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5197 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5198 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5199 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5200
bb4f98ab 5201 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5202 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5203
bb4f98ab 5204 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5205 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5206
5207 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5208 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5209 }
b6016b76 5210
bb4f98ab 5211 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5212 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5213
bb4f98ab 5214 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5215 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5216
bb4f98ab 5217 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5218 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5219 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5220 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5221 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5222 break;
b929e53c 5223 }
47bf4246
MC		 5224 prod = NEXT_RX_BD(prod);
5225 ring_prod = RX_PG_RING_IDX(prod);
5226 }
bb4f98ab 5227 rxr->rx_pg_prod = prod;
47bf4246 5228
bb4f98ab 5229 ring_prod = prod = rxr->rx_prod;
236b6394 5230 for (i = 0; i < bp->rx_ring_size; i++) {
dd2bc8e9 5231 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5232 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5233 ring_num, i, bp->rx_ring_size);
b6016b76 5234 break;
b929e53c 5235 }
b6016b76
MC		 5236 prod = NEXT_RX_BD(prod);
5237 ring_prod = RX_RING_IDX(prod);
5238 }
bb4f98ab 5239 rxr->rx_prod = prod;
b6016b76 5240
bb4f98ab
MC		 5241 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5242 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5243 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5244
bb4f98ab
MC		 5245 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5246 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5247
5248 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5249}
5250
35e9010b
MC		 5251static void
5252bnx2_init_all_rings(struct bnx2 *bp)
5253{
5254 int i;
5e9ad9e1 5255 u32 val;
35e9010b
MC		 5256
5257 bnx2_clear_ring_states(bp);
5258
5259 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5260 for (i = 0; i < bp->num_tx_rings; i++)
5261 bnx2_init_tx_ring(bp, i);
5262
5263 if (bp->num_tx_rings > 1)
5264 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5265 (TX_TSS_CID << 7));
5266
5e9ad9e1
MC		 5267 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5268 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5269
bb4f98ab
MC		 5270 for (i = 0; i < bp->num_rx_rings; i++)
5271 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5272
5273 if (bp->num_rx_rings > 1) {
22fa159d 5274 u32 tbl_32 = 0;
5e9ad9e1
MC		 5275
5276 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5277 int shift = (i % 8) << 2;
5278
5279 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5280 if ((i % 8) == 7) {
5281 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5282 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5283 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5284 BNX2_RLUP_RSS_COMMAND_WRITE |
5285 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5286 tbl_32 = 0;
5287 }
5e9ad9e1
MC		 5288 }
5289
5290 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5291 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5292
5293 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5294
5295 }
35e9010b
MC		 5296}
5297
5d5d0015 5298static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5299{
5d5d0015 5300 u32 max, num_rings = 1;
13daffa2 5301
5d5d0015
MC		 5302 while (ring_size > MAX_RX_DESC_CNT) {
5303 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5304 num_rings++;
5305 }
5306 /* round to next power of 2 */
5d5d0015 5307 max = max_size;
13daffa2
MC		 5308 while ((max & num_rings) == 0)
5309 max >>= 1;
5310
5311 if (num_rings != max)
5312 max <<= 1;
5313
5d5d0015
MC		 5314 return max;
5315}
5316
5317static void
5318bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5319{
84eaa187 5320 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5321
5322 /* 8 for CRC and VLAN */
d89cb6af 5323 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5324
84eaa187 5325 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
dd2bc8e9 5326 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
84eaa187 5327
601d3d18 5328 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5329 bp->rx_pg_ring_size = 0;
5330 bp->rx_max_pg_ring = 0;
5331 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5332 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5333 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5334
5335 jumbo_size = size * pages;
5336 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5337 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5338
5339 bp->rx_pg_ring_size = jumbo_size;
5340 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5341 MAX_RX_PG_RINGS);
5342 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5343 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5344 bp->rx_copy_thresh = 0;
5345 }
5d5d0015
MC		 5346
5347 bp->rx_buf_use_size = rx_size;
dd2bc8e9
ED		 5348 /* hw alignment + build_skb() overhead*/
5349 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5350 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
d89cb6af 5351 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5352 bp->rx_ring_size = size;
5353 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5354 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5355}
5356
b6016b76
MC		 5357static void
5358bnx2_free_tx_skbs(struct bnx2 *bp)
5359{
5360 int i;
5361
35e9010b
MC		 5362 for (i = 0; i < bp->num_tx_rings; i++) {
5363 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5364 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5365 int j;
b6016b76 5366
35e9010b 5367 if (txr->tx_buf_ring == NULL)
b6016b76 5368 continue;
b6016b76 5369
35e9010b 5370 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5371 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5372 struct sk_buff *skb = tx_buf->skb;
e95524a7 5373 int k, last;
35e9010b
MC		 5374
5375 if (skb == NULL) {
5376 j++;
5377 continue;
5378 }
5379
36227e88 5380 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5381 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5382 skb_headlen(skb),
5383 PCI_DMA_TODEVICE);
b6016b76 5384
35e9010b 5385 tx_buf->skb = NULL;
b6016b76 5386
e95524a7
AD		 5387 last = tx_buf->nr_frags;
5388 j++;
5389 for (k = 0; k < last; k++, j++) {
5390 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5391 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5392 dma_unmap_addr(tx_buf, mapping),
9e903e08 5393 skb_frag_size(&skb_shinfo(skb)->frags[k]),
e95524a7
AD		 5394 PCI_DMA_TODEVICE);
5395 }
35e9010b 5396 dev_kfree_skb(skb);
b6016b76 5397 }
e9831909 5398 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
b6016b76 5399 }
b6016b76
MC		 5400}
5401
5402static void
5403bnx2_free_rx_skbs(struct bnx2 *bp)
5404{
5405 int i;
5406
bb4f98ab
MC		 5407 for (i = 0; i < bp->num_rx_rings; i++) {
5408 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5409 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5410 int j;
b6016b76 5411
bb4f98ab
MC		 5412 if (rxr->rx_buf_ring == NULL)
5413 return;
b6016b76 5414
bb4f98ab
MC		 5415 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5416 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
dd2bc8e9 5417 u8 *data = rx_buf->data;
b6016b76 5418
dd2bc8e9 5419 if (data == NULL)
bb4f98ab 5420 continue;
b6016b76 5421
36227e88 5422 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5423 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5424 bp->rx_buf_use_size,
5425 PCI_DMA_FROMDEVICE);
b6016b76 5426
dd2bc8e9 5427 rx_buf->data = NULL;
bb4f98ab 5428
dd2bc8e9 5429 kfree(data);
bb4f98ab
MC		 5430 }
5431 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5432 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5433 }
5434}
5435
5436static void
5437bnx2_free_skbs(struct bnx2 *bp)
5438{
5439 bnx2_free_tx_skbs(bp);
5440 bnx2_free_rx_skbs(bp);
5441}
5442
5443static int
5444bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5445{
5446 int rc;
5447
5448 rc = bnx2_reset_chip(bp, reset_code);
5449 bnx2_free_skbs(bp);
5450 if (rc)
5451 return rc;
5452
fba9fe91
MC		 5453 if ((rc = bnx2_init_chip(bp)) != 0)
5454 return rc;
5455
35e9010b 5456 bnx2_init_all_rings(bp);
b6016b76
MC		 5457 return 0;
5458}
5459
5460static int
9a120bc5 5461bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5462{
5463 int rc;
5464
5465 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5466 return rc;
5467
80be4434 5468 spin_lock_bh(&bp->phy_lock);
9a120bc5 5469 bnx2_init_phy(bp, reset_phy);
b6016b76 5470 bnx2_set_link(bp);
543a827d
MC		 5471 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5472 bnx2_remote_phy_event(bp);
0d8a6571 5473 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5474 return 0;
5475}
5476
74bf4ba3
MC		 5477static int
5478bnx2_shutdown_chip(struct bnx2 *bp)
5479{
5480 u32 reset_code;
5481
5482 if (bp->flags & BNX2_FLAG_NO_WOL)
5483 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5484 else if (bp->wol)
5485 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5486 else
5487 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5488
5489 return bnx2_reset_chip(bp, reset_code);
5490}
5491
b6016b76
MC		 5492static int
5493bnx2_test_registers(struct bnx2 *bp)
5494{
5495 int ret;
5bae30c9 5496 int i, is_5709;
f71e1309 5497 static const struct {
b6016b76
MC		 5498 u16 offset;
5499 u16 flags;
5bae30c9 5500#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5501 u32 rw_mask;
5502 u32 ro_mask;
5503 } reg_tbl[] = {
5504 { 0x006c, 0, 0x00000000, 0x0000003f },
5505 { 0x0090, 0, 0xffffffff, 0x00000000 },
5506 { 0x0094, 0, 0x00000000, 0x00000000 },
5507
5bae30c9
MC		 5508 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5509 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5510 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5511 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5512 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5513 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5514 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5515 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5516 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5517
5518 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5519 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5520 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5521 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5522 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5523 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5524
5525 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5526 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5527 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5528
5529 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5530 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5531
5532 { 0x1408, 0, 0x01c00800, 0x00000000 },
5533 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5534 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5535 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5536 { 0x14b0, 0, 0x00000002, 0x00000001 },
5537 { 0x14b8, 0, 0x00000000, 0x00000000 },
5538 { 0x14c0, 0, 0x00000000, 0x00000009 },
5539 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5540 { 0x14cc, 0, 0x00000000, 0x00000001 },
5541 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5542
5543 { 0x1800, 0, 0x00000000, 0x00000001 },
5544 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5545
5546 { 0x2800, 0, 0x00000000, 0x00000001 },
5547 { 0x2804, 0, 0x00000000, 0x00003f01 },
5548 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5549 { 0x2810, 0, 0xffff0000, 0x00000000 },
5550 { 0x2814, 0, 0xffff0000, 0x00000000 },
5551 { 0x2818, 0, 0xffff0000, 0x00000000 },
5552 { 0x281c, 0, 0xffff0000, 0x00000000 },
5553 { 0x2834, 0, 0xffffffff, 0x00000000 },
5554 { 0x2840, 0, 0x00000000, 0xffffffff },
5555 { 0x2844, 0, 0x00000000, 0xffffffff },
5556 { 0x2848, 0, 0xffffffff, 0x00000000 },
5557 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5558
5559 { 0x2c00, 0, 0x00000000, 0x00000011 },
5560 { 0x2c04, 0, 0x00000000, 0x00030007 },
5561
b6016b76
MC		 5562 { 0x3c00, 0, 0x00000000, 0x00000001 },
5563 { 0x3c04, 0, 0x00000000, 0x00070000 },
5564 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5565 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5566 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5567 { 0x3c14, 0, 0x00000000, 0xffffffff },
5568 { 0x3c18, 0, 0x00000000, 0xffffffff },
5569 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5570 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5571
5572 { 0x5004, 0, 0x00000000, 0x0000007f },
5573 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5574
b6016b76
MC		 5575 { 0x5c00, 0, 0x00000000, 0x00000001 },
5576 { 0x5c04, 0, 0x00000000, 0x0003000f },
5577 { 0x5c08, 0, 0x00000003, 0x00000000 },
5578 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5579 { 0x5c10, 0, 0x00000000, 0xffffffff },
5580 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5581 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5582 { 0x5c88, 0, 0x00000000, 0x00077373 },
5583 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5584
5585 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5586 { 0x680c, 0, 0xffffffff, 0x00000000 },
5587 { 0x6810, 0, 0xffffffff, 0x00000000 },
5588 { 0x6814, 0, 0xffffffff, 0x00000000 },
5589 { 0x6818, 0, 0xffffffff, 0x00000000 },
5590 { 0x681c, 0, 0xffffffff, 0x00000000 },
5591 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5592 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5593 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5594 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5595 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5596 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5597 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5598 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5599 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5600 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5601 { 0x684c, 0, 0xffffffff, 0x00000000 },
5602 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5603 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5604 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5605 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5606 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5607 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5608
5609 { 0xffff, 0, 0x00000000, 0x00000000 },
5610 };
5611
5612 ret = 0;
5bae30c9
MC		 5613 is_5709 = 0;
5614 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5615 is_5709 = 1;
5616
b6016b76
MC		 5617 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5618 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5619 u16 flags = reg_tbl[i].flags;
5620
5621 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5622 continue;
b6016b76
MC		 5623
5624 offset = (u32) reg_tbl[i].offset;
5625 rw_mask = reg_tbl[i].rw_mask;
5626 ro_mask = reg_tbl[i].ro_mask;
5627
14ab9b86 5628 save_val = readl(bp->regview + offset);
b6016b76 5629
14ab9b86 5630 writel(0, bp->regview + offset);
b6016b76 5631
14ab9b86 5632 val = readl(bp->regview + offset);
b6016b76
MC		 5633 if ((val & rw_mask) != 0) {
5634 goto reg_test_err;
5635 }
5636
5637 if ((val & ro_mask) != (save_val & ro_mask)) {
5638 goto reg_test_err;
5639 }
5640
14ab9b86 5641 writel(0xffffffff, bp->regview + offset);
b6016b76 5642
14ab9b86 5643 val = readl(bp->regview + offset);
b6016b76
MC		 5644 if ((val & rw_mask) != rw_mask) {
5645 goto reg_test_err;
5646 }
5647
5648 if ((val & ro_mask) != (save_val & ro_mask)) {
5649 goto reg_test_err;
5650 }
5651
14ab9b86 5652 writel(save_val, bp->regview + offset);
b6016b76
MC		 5653 continue;
5654
5655reg_test_err:
14ab9b86 5656 writel(save_val, bp->regview + offset);
b6016b76
MC		 5657 ret = -ENODEV;
5658 break;
5659 }
5660 return ret;
5661}
5662
5663static int
5664bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5665{
f71e1309 5666 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5667 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5668 int i;
5669
5670 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5671 u32 offset;
5672
5673 for (offset = 0; offset < size; offset += 4) {
5674
2726d6e1 5675 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5676
2726d6e1 5677 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5678 test_pattern[i]) {
5679 return -ENODEV;
5680 }
5681 }
5682 }
5683 return 0;
5684}
5685
5686static int
5687bnx2_test_memory(struct bnx2 *bp)
5688{
5689 int ret = 0;
5690 int i;
5bae30c9 5691 static struct mem_entry {
b6016b76
MC		 5692 u32 offset;
5693 u32 len;
5bae30c9 5694 } mem_tbl_5706[] = {
b6016b76 5695 { 0x60000, 0x4000 },
5b0c76ad 5696 { 0xa0000, 0x3000 },
b6016b76
MC		 5697 { 0xe0000, 0x4000 },
5698 { 0x120000, 0x4000 },
5699 { 0x1a0000, 0x4000 },
5700 { 0x160000, 0x4000 },
5701 { 0xffffffff, 0 },
5bae30c9
MC		 5702 },
5703 mem_tbl_5709[] = {
5704 { 0x60000, 0x4000 },
5705 { 0xa0000, 0x3000 },
5706 { 0xe0000, 0x4000 },
5707 { 0x120000, 0x4000 },
5708 { 0x1a0000, 0x4000 },
5709 { 0xffffffff, 0 },
b6016b76 5710 };
5bae30c9
MC		 5711 struct mem_entry *mem_tbl;
5712
5713 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5714 mem_tbl = mem_tbl_5709;
5715 else
5716 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5717
5718 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5719 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5720 mem_tbl[i].len)) != 0) {
5721 return ret;
5722 }
5723 }
6aa20a22 5724
b6016b76
MC		 5725 return ret;
5726}
5727
bc5a0690
MC		 5728#define BNX2_MAC_LOOPBACK 0
5729#define BNX2_PHY_LOOPBACK 1
5730
b6016b76 5731static int
bc5a0690 5732bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5733{
5734 unsigned int pkt_size, num_pkts, i;
dd2bc8e9
ED		 5735 struct sk_buff *skb;
5736 u8 *data;
b6016b76 5737 unsigned char *packet;
bc5a0690 5738 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5739 dma_addr_t map;
5740 struct tx_bd *txbd;
5741 struct sw_bd *rx_buf;
5742 struct l2_fhdr *rx_hdr;
5743 int ret = -ENODEV;
c76c0475 5744 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5745 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5746 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5747
5748 tx_napi = bnapi;
b6016b76 5749
35e9010b 5750 txr = &tx_napi->tx_ring;
bb4f98ab 5751 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5752 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5753 bp->loopback = MAC_LOOPBACK;
5754 bnx2_set_mac_loopback(bp);
5755 }
5756 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5757 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5758 return 0;
5759
80be4434 5760 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5761 bnx2_set_phy_loopback(bp);
5762 }
5763 else
5764 return -EINVAL;
b6016b76 5765
84eaa187 5766 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5767 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5768 if (!skb)
5769 return -ENOMEM;
b6016b76 5770 packet = skb_put(skb, pkt_size);
6634292b 5771 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5772 memset(packet + 6, 0x0, 8);
5773 for (i = 14; i < pkt_size; i++)
5774 packet[i] = (unsigned char) (i & 0xff);
5775
36227e88
SG		 5776 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5777 PCI_DMA_TODEVICE);
5778 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5779 dev_kfree_skb(skb);
5780 return -EIO;
5781 }
b6016b76 5782
bf5295bb
MC		 5783 REG_WR(bp, BNX2_HC_COMMAND,
5784 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5785
b6016b76
MC		 5786 REG_RD(bp, BNX2_HC_COMMAND);
5787
5788 udelay(5);
35efa7c1 5789 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5790
b6016b76
MC		 5791 num_pkts = 0;
5792
35e9010b 5793 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5794
5795 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5796 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5797 txbd->tx_bd_mss_nbytes = pkt_size;
5798 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5799
5800 num_pkts++;
35e9010b
MC		 5801 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5802 txr->tx_prod_bseq += pkt_size;
b6016b76 5803
35e9010b
MC		 5804 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5805 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5806
5807 udelay(100);
5808
bf5295bb
MC		 5809 REG_WR(bp, BNX2_HC_COMMAND,
5810 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5811
b6016b76
MC		 5812 REG_RD(bp, BNX2_HC_COMMAND);
5813
5814 udelay(5);
5815
36227e88 5816 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5817 dev_kfree_skb(skb);
b6016b76 5818
35e9010b 5819 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5820 goto loopback_test_done;
b6016b76 5821
35efa7c1 5822 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5823 if (rx_idx != rx_start_idx + num_pkts) {
5824 goto loopback_test_done;
5825 }
5826
bb4f98ab 5827 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
dd2bc8e9 5828 data = rx_buf->data;
b6016b76 5829
dd2bc8e9
ED		 5830 rx_hdr = get_l2_fhdr(data);
5831 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
b6016b76 5832
36227e88 5833 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5834 dma_unmap_addr(rx_buf, mapping),
dd2bc8e9 5835 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
b6016b76 5836
ade2bfe7 5837 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5838 (L2_FHDR_ERRORS_BAD_CRC |
5839 L2_FHDR_ERRORS_PHY_DECODE |
5840 L2_FHDR_ERRORS_ALIGNMENT |
5841 L2_FHDR_ERRORS_TOO_SHORT |
5842 L2_FHDR_ERRORS_GIANT_FRAME)) {
5843
5844 goto loopback_test_done;
5845 }
5846
5847 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5848 goto loopback_test_done;
5849 }
5850
5851 for (i = 14; i < pkt_size; i++) {
dd2bc8e9 5852 if (*(data + i) != (unsigned char) (i & 0xff)) {
b6016b76
MC		 5853 goto loopback_test_done;
5854 }
5855 }
5856
5857 ret = 0;
5858
5859loopback_test_done:
5860 bp->loopback = 0;
5861 return ret;
5862}
5863
bc5a0690
MC		 5864#define BNX2_MAC_LOOPBACK_FAILED 1
5865#define BNX2_PHY_LOOPBACK_FAILED 2
5866#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5867 BNX2_PHY_LOOPBACK_FAILED)
5868
5869static int
5870bnx2_test_loopback(struct bnx2 *bp)
5871{
5872 int rc = 0;
5873
5874 if (!netif_running(bp->dev))
5875 return BNX2_LOOPBACK_FAILED;
5876
5877 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5878 spin_lock_bh(&bp->phy_lock);
9a120bc5 5879 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5880 spin_unlock_bh(&bp->phy_lock);
5881 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5882 rc |= BNX2_MAC_LOOPBACK_FAILED;
5883 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5884 rc |= BNX2_PHY_LOOPBACK_FAILED;
5885 return rc;
5886}
5887
b6016b76
MC		 5888#define NVRAM_SIZE 0x200
5889#define CRC32_RESIDUAL 0xdebb20e3
5890
5891static int
5892bnx2_test_nvram(struct bnx2 *bp)
5893{
b491edd5 5894 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5895 u8 *data = (u8 *) buf;
5896 int rc = 0;
5897 u32 magic, csum;
5898
5899 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5900 goto test_nvram_done;
5901
5902 magic = be32_to_cpu(buf[0]);
5903 if (magic != 0x669955aa) {
5904 rc = -ENODEV;
5905 goto test_nvram_done;
5906 }
5907
5908 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5909 goto test_nvram_done;
5910
5911 csum = ether_crc_le(0x100, data);
5912 if (csum != CRC32_RESIDUAL) {
5913 rc = -ENODEV;
5914 goto test_nvram_done;
5915 }
5916
5917 csum = ether_crc_le(0x100, data + 0x100);
5918 if (csum != CRC32_RESIDUAL) {
5919 rc = -ENODEV;
5920 }
5921
5922test_nvram_done:
5923 return rc;
5924}
5925
5926static int
5927bnx2_test_link(struct bnx2 *bp)
5928{
5929 u32 bmsr;
5930
9f52b564
MC		 5931 if (!netif_running(bp->dev))
5932 return -ENODEV;
5933
583c28e5 5934 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5935 if (bp->link_up)
5936 return 0;
5937 return -ENODEV;
5938 }
c770a65c 5939 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5940 bnx2_enable_bmsr1(bp);
5941 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5942 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5943 bnx2_disable_bmsr1(bp);
c770a65c 5944 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5945
b6016b76
MC		 5946 if (bmsr & BMSR_LSTATUS) {
5947 return 0;
5948 }
5949 return -ENODEV;
5950}
5951
5952static int
5953bnx2_test_intr(struct bnx2 *bp)
5954{
5955 int i;
b6016b76
MC		 5956 u16 status_idx;
5957
5958 if (!netif_running(bp->dev))
5959 return -ENODEV;
5960
5961 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5962
5963 /* This register is not touched during run-time. */
bf5295bb 5964 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5965 REG_RD(bp, BNX2_HC_COMMAND);
5966
5967 for (i = 0; i < 10; i++) {
5968 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5969 status_idx) {
5970
5971 break;
5972 }
5973
5974 msleep_interruptible(10);
5975 }
5976 if (i < 10)
5977 return 0;
5978
5979 return -ENODEV;
5980}
5981
38ea3686 5982/* Determining link for parallel detection. */
b2fadeae
MC		 5983static int
5984bnx2_5706_serdes_has_link(struct bnx2 *bp)
5985{
5986 u32 mode_ctl, an_dbg, exp;
5987
38ea3686
MC		 5988 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5989 return 0;
5990
b2fadeae
MC		 5991 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5993
5994 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5995 return 0;
5996
5997 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5998 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5999 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6000
f3014c0c 6001 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 6002 return 0;
6003
6004 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6005 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6006 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6007
6008 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6009 return 0;
6010
6011 return 1;
6012}
6013
b6016b76 6014static void
48b01e2d 6015bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 6016{
b2fadeae
MC		 6017 int check_link = 1;
6018
48b01e2d 6019 spin_lock(&bp->phy_lock);
b2fadeae 6020 if (bp->serdes_an_pending) {
48b01e2d 6021 bp->serdes_an_pending--;
b2fadeae
MC		 6022 check_link = 0;
6023 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6024 u32 bmcr;
b6016b76 6025
ac392abc 6026 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6027
ca58c3af 6028 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6029
48b01e2d 6030 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6031 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6032 bmcr &= ~BMCR_ANENABLE;
6033 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6034 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6035 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6036 }
b6016b76 6037 }
48b01e2d
MC		 6038 }
6039 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6040 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6041 u32 phy2;
b6016b76 6042
48b01e2d
MC		 6043 bnx2_write_phy(bp, 0x17, 0x0f01);
6044 bnx2_read_phy(bp, 0x15, &phy2);
6045 if (phy2 & 0x20) {
6046 u32 bmcr;
cd339a0e 6047
ca58c3af 6048 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6049 bmcr |= BMCR_ANENABLE;
ca58c3af 6050 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6051
583c28e5 6052 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6053 }
6054 } else
ac392abc 6055 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6056
a2724e25 6057 if (check_link) {
b2fadeae
MC		 6058 u32 val;
6059
6060 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6061 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6062 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6063
a2724e25
MC		 6064 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6065 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6066 bnx2_5706s_force_link_dn(bp, 1);
6067 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6068 } else
6069 bnx2_set_link(bp);
6070 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6071 bnx2_set_link(bp);
b2fadeae 6072 }
48b01e2d
MC		 6073 spin_unlock(&bp->phy_lock);
6074}
b6016b76 6075
f8dd064e
MC		 6076static void
6077bnx2_5708_serdes_timer(struct bnx2 *bp)
6078{
583c28e5 6079 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6080 return;
6081
583c28e5 6082 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6083 bp->serdes_an_pending = 0;
6084 return;
6085 }
b6016b76 6086
f8dd064e
MC		 6087 spin_lock(&bp->phy_lock);
6088 if (bp->serdes_an_pending)
6089 bp->serdes_an_pending--;
6090 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6091 u32 bmcr;
b6016b76 6092
ca58c3af 6093 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6094 if (bmcr & BMCR_ANENABLE) {
605a9e20 6095 bnx2_enable_forced_2g5(bp);
40105c0b 6096 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6097 } else {
605a9e20 6098 bnx2_disable_forced_2g5(bp);
f8dd064e 6099 bp->serdes_an_pending = 2;
ac392abc 6100 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6101 }
b6016b76 6102
f8dd064e 6103 } else
ac392abc 6104 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6105
f8dd064e
MC		 6106 spin_unlock(&bp->phy_lock);
6107}
6108
48b01e2d
MC		 6109static void
6110bnx2_timer(unsigned long data)
6111{
6112 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6113
48b01e2d
MC		 6114 if (!netif_running(bp->dev))
6115 return;
b6016b76 6116
48b01e2d
MC		 6117 if (atomic_read(&bp->intr_sem) != 0)
6118 goto bnx2_restart_timer;
b6016b76 6119
efba0180
MC		 6120 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6121 BNX2_FLAG_USING_MSI)
6122 bnx2_chk_missed_msi(bp);
6123
df149d70 6124 bnx2_send_heart_beat(bp);
b6016b76 6125
2726d6e1
MC		 6126 bp->stats_blk->stat_FwRxDrop =
6127 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6128
02537b06 6129 /* workaround occasional corrupted counters */
61d9e3fa 6130 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6131 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6132 BNX2_HC_COMMAND_STATS_NOW);
6133
583c28e5 6134 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6135 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6136 bnx2_5706_serdes_timer(bp);
27a005b8 6137 else
f8dd064e 6138 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6139 }
6140
6141bnx2_restart_timer:
cd339a0e 6142 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6143}
6144
8e6a72c4
MC		 6145static int
6146bnx2_request_irq(struct bnx2 *bp)
6147{
6d866ffc 6148 unsigned long flags;
b4b36042
MC		 6149 struct bnx2_irq *irq;
6150 int rc = 0, i;
8e6a72c4 6151
f86e82fb 6152 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6153 flags = 0;
6154 else
6155 flags = IRQF_SHARED;
b4b36042
MC		 6156
6157 for (i = 0; i < bp->irq_nvecs; i++) {
6158 irq = &bp->irq_tbl[i];
c76c0475 6159 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6160 &bp->bnx2_napi[i]);
b4b36042
MC		 6161 if (rc)
6162 break;
6163 irq->requested = 1;
6164 }
8e6a72c4
MC		 6165 return rc;
6166}
6167
6168static void
a29ba9d2 6169__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6170{
b4b36042
MC		 6171 struct bnx2_irq *irq;
6172 int i;
8e6a72c4 6173
b4b36042
MC		 6174 for (i = 0; i < bp->irq_nvecs; i++) {
6175 irq = &bp->irq_tbl[i];
6176 if (irq->requested)
f0ea2e63 6177 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6178 irq->requested = 0;
6d866ffc 6179 }
a29ba9d2
MC		 6180}
6181
6182static void
6183bnx2_free_irq(struct bnx2 *bp)
6184{
6185
6186 __bnx2_free_irq(bp);
f86e82fb 6187 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6188 pci_disable_msi(bp->pdev);
f86e82fb 6189 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6190 pci_disable_msix(bp->pdev);
6191
f86e82fb 6192 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6193}
6194
6195static void
5e9ad9e1 6196bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6197{
379b39a2 6198 int i, total_vecs, rc;
57851d84 6199 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6200 struct net_device *dev = bp->dev;
6201 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6202
b4b36042
MC		 6203 bnx2_setup_msix_tbl(bp);
6204 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6205 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6206 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6207
e2eb8e38
BL		 6208 /* Need to flush the previous three writes to ensure MSI-X
6209 * is setup properly */
6210 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6211
57851d84
MC		 6212 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6213 msix_ent[i].entry = i;
6214 msix_ent[i].vector = 0;
6215 }
6216
379b39a2
MC		 6217 total_vecs = msix_vecs;
6218#ifdef BCM_CNIC
6219 total_vecs++;
6220#endif
6221 rc = -ENOSPC;
6222 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6223 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6224 if (rc <= 0)
6225 break;
6226 if (rc > 0)
6227 total_vecs = rc;
6228 }
6229
57851d84
MC		 6230 if (rc != 0)
6231 return;
6232
379b39a2
MC		 6233 msix_vecs = total_vecs;
6234#ifdef BCM_CNIC
6235 msix_vecs--;
6236#endif
5e9ad9e1 6237 bp->irq_nvecs = msix_vecs;
f86e82fb 6238 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6239 for (i = 0; i < total_vecs; i++) {
57851d84 6240 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6241 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6242 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6243 }
6d866ffc
MC		 6244}
6245
657d92fe 6246static int
6d866ffc
MC		 6247bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6248{
5e9ad9e1 6249 int cpus = num_online_cpus();
b033281f
MC		 6250 int msix_vecs;
6251
6252 if (!bp->num_req_rx_rings)
6253 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6254 else if (!bp->num_req_tx_rings)
6255 msix_vecs = max(cpus, bp->num_req_rx_rings);
6256 else
6257 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6258
6259 msix_vecs = min(msix_vecs, RX_MAX_RINGS);
5e9ad9e1 6260
6d866ffc
MC		 6261 bp->irq_tbl[0].handler = bnx2_interrupt;
6262 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6263 bp->irq_nvecs = 1;
6264 bp->irq_tbl[0].vector = bp->pdev->irq;
6265
3d5f3a7b 6266 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6267 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6268
f86e82fb
DM		 6269 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6270 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6271 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6272 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6274 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6275 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6276 } else
6277 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6278
6279 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6280 }
6281 }
706bf240 6282
b033281f
MC		 6283 if (!bp->num_req_tx_rings)
6284 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6285 else
6286 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6287
6288 if (!bp->num_req_rx_rings)
6289 bp->num_rx_rings = bp->irq_nvecs;
6290 else
6291 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6292
657d92fe 6293 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6294
657d92fe 6295 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6296}
6297
b6016b76
MC		 6298/* Called with rtnl_lock */
6299static int
6300bnx2_open(struct net_device *dev)
6301{
972ec0d4 6302 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6303 int rc;
6304
7880b72e 6305 rc = bnx2_request_firmware(bp);
6306 if (rc < 0)
6307 goto out;
6308
1b2f922f
MC		 6309 netif_carrier_off(dev);
6310
829ca9a3 6311 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6312 bnx2_disable_int(bp);
6313
657d92fe
BH		 6314 rc = bnx2_setup_int_mode(bp, disable_msi);
6315 if (rc)
6316 goto open_err;
4327ba43 6317 bnx2_init_napi(bp);
35e9010b 6318 bnx2_napi_enable(bp);
b6016b76 6319 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6320 if (rc)
6321 goto open_err;
b6016b76 6322
8e6a72c4 6323 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6324 if (rc)
6325 goto open_err;
b6016b76 6326
9a120bc5 6327 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6328 if (rc)
6329 goto open_err;
6aa20a22 6330
cd339a0e 6331 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6332
6333 atomic_set(&bp->intr_sem, 0);
6334
354fcd77
MC		 6335 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6336
b6016b76
MC		 6337 bnx2_enable_int(bp);
6338
f86e82fb 6339 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6340 /* Test MSI to make sure it is working
6341 * If MSI test fails, go back to INTx mode
6342 */
6343 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6344 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6345
6346 bnx2_disable_int(bp);
8e6a72c4 6347 bnx2_free_irq(bp);
b6016b76 6348
6d866ffc
MC		 6349 bnx2_setup_int_mode(bp, 1);
6350
9a120bc5 6351 rc = bnx2_init_nic(bp, 0);
b6016b76 6352
8e6a72c4
MC		 6353 if (!rc)
6354 rc = bnx2_request_irq(bp);
6355
b6016b76 6356 if (rc) {
b6016b76 6357 del_timer_sync(&bp->timer);
2739a8bb 6358 goto open_err;
b6016b76
MC		 6359 }
6360 bnx2_enable_int(bp);
6361 }
6362 }
f86e82fb 6363 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6364 netdev_info(dev, "using MSI\n");
f86e82fb 6365 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6366 netdev_info(dev, "using MSIX\n");
b6016b76 6367
706bf240 6368 netif_tx_start_all_queues(dev);
7880b72e 6369out:
6370 return rc;
2739a8bb
MC		 6371
6372open_err:
6373 bnx2_napi_disable(bp);
6374 bnx2_free_skbs(bp);
6375 bnx2_free_irq(bp);
6376 bnx2_free_mem(bp);
f048fa9c 6377 bnx2_del_napi(bp);
7880b72e 6378 bnx2_release_firmware(bp);
6379 goto out;
b6016b76
MC		 6380}
6381
6382static void
c4028958 6383bnx2_reset_task(struct work_struct *work)
b6016b76 6384{
c4028958 6385 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6386 int rc;
b6016b76 6387
51bf6bb4
MC		 6388 rtnl_lock();
6389 if (!netif_running(bp->dev)) {
6390 rtnl_unlock();
afdc08b9 6391 return;
51bf6bb4 6392 }
afdc08b9 6393
212f9934 6394 bnx2_netif_stop(bp, true);
b6016b76 6395
cd634019
MC		 6396 rc = bnx2_init_nic(bp, 1);
6397 if (rc) {
6398 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6399 bnx2_napi_enable(bp);
6400 dev_close(bp->dev);
6401 rtnl_unlock();
6402 return;
6403 }
b6016b76
MC		 6404
6405 atomic_set(&bp->intr_sem, 1);
212f9934 6406 bnx2_netif_start(bp, true);
51bf6bb4 6407 rtnl_unlock();
b6016b76
MC		 6408}
6409
555069da
MC		 6410#define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6411
6412static void
6413bnx2_dump_ftq(struct bnx2 *bp)
6414{
6415 int i;
6416 u32 reg, bdidx, cid, valid;
6417 struct net_device *dev = bp->dev;
6418 static const struct ftq_reg {
6419 char *name;
6420 u32 off;
6421 } ftq_arr[] = {
6422 BNX2_FTQ_ENTRY(RV2P_P),
6423 BNX2_FTQ_ENTRY(RV2P_T),
6424 BNX2_FTQ_ENTRY(RV2P_M),
6425 BNX2_FTQ_ENTRY(TBDR_),
6426 BNX2_FTQ_ENTRY(TDMA_),
6427 BNX2_FTQ_ENTRY(TXP_),
6428 BNX2_FTQ_ENTRY(TXP_),
6429 BNX2_FTQ_ENTRY(TPAT_),
6430 BNX2_FTQ_ENTRY(RXP_C),
6431 BNX2_FTQ_ENTRY(RXP_),
6432 BNX2_FTQ_ENTRY(COM_COMXQ_),
6433 BNX2_FTQ_ENTRY(COM_COMTQ_),
6434 BNX2_FTQ_ENTRY(COM_COMQ_),
6435 BNX2_FTQ_ENTRY(CP_CPQ_),
6436 };
6437
6438 netdev_err(dev, "<--- start FTQ dump --->\n");
6439 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6440 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6441 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6442
6443 netdev_err(dev, "CPU states:\n");
6444 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6445 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6446 reg, bnx2_reg_rd_ind(bp, reg),
6447 bnx2_reg_rd_ind(bp, reg + 4),
6448 bnx2_reg_rd_ind(bp, reg + 8),
6449 bnx2_reg_rd_ind(bp, reg + 0x1c),
6450 bnx2_reg_rd_ind(bp, reg + 0x1c),
6451 bnx2_reg_rd_ind(bp, reg + 0x20));
6452
6453 netdev_err(dev, "<--- end FTQ dump --->\n");
6454 netdev_err(dev, "<--- start TBDC dump --->\n");
6455 netdev_err(dev, "TBDC free cnt: %ld\n",
6456 REG_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6457 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6458 for (i = 0; i < 0x20; i++) {
6459 int j = 0;
6460
6461 REG_WR(bp, BNX2_TBDC_BD_ADDR, i);
6462 REG_WR(bp, BNX2_TBDC_CAM_OPCODE,
6463 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6464 REG_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6465 while ((REG_RD(bp, BNX2_TBDC_COMMAND) &
6466 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6467 j++;
6468
6469 cid = REG_RD(bp, BNX2_TBDC_CID);
6470 bdidx = REG_RD(bp, BNX2_TBDC_BIDX);
6471 valid = REG_RD(bp, BNX2_TBDC_CAM_OPCODE);
6472 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6473 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6474 bdidx >> 24, (valid >> 8) & 0x0ff);
6475 }
6476 netdev_err(dev, "<--- end TBDC dump --->\n");
6477}
6478
20175c57
MC		 6479static void
6480bnx2_dump_state(struct bnx2 *bp)
6481{
6482 struct net_device *dev = bp->dev;
ecdbf6e0 6483 u32 val1, val2;
5804a8fb
MC		 6484
6485 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6486 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6487 atomic_read(&bp->intr_sem), val1);
6488 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6489 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6490 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6491 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6492 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6493 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6494 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6495 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49
JP		 6496 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6497 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6498 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6499 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6500 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6501}
6502
b6016b76
MC		 6503static void
6504bnx2_tx_timeout(struct net_device *dev)
6505{
972ec0d4 6506 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6507
555069da 6508 bnx2_dump_ftq(bp);
20175c57 6509 bnx2_dump_state(bp);
ecdbf6e0 6510 bnx2_dump_mcp_state(bp);
20175c57 6511
b6016b76
MC		 6512 /* This allows the netif to be shutdown gracefully before resetting */
6513 schedule_work(&bp->reset_task);
6514}
6515
932ff279 6516/* Called with netif_tx_lock.
2f8af120
MC		 6517 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6518 * netif_wake_queue().
b6016b76 6519 */
61357325 6520static netdev_tx_t
b6016b76
MC		 6521bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6522{
972ec0d4 6523 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6524 dma_addr_t mapping;
6525 struct tx_bd *txbd;
3d16af86 6526 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6527 u32 len, vlan_tag_flags, last_frag, mss;
6528 u16 prod, ring_prod;
6529 int i;
706bf240
BL		 6530 struct bnx2_napi *bnapi;
6531 struct bnx2_tx_ring_info *txr;
6532 struct netdev_queue *txq;
6533
6534 /* Determine which tx ring we will be placed on */
6535 i = skb_get_queue_mapping(skb);
6536 bnapi = &bp->bnx2_napi[i];
6537 txr = &bnapi->tx_ring;
6538 txq = netdev_get_tx_queue(dev, i);
b6016b76 6539
35e9010b 6540 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6541 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6542 netif_tx_stop_queue(txq);
3a9c6a49 6543 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6544
6545 return NETDEV_TX_BUSY;
6546 }
6547 len = skb_headlen(skb);
35e9010b 6548 prod = txr->tx_prod;
b6016b76
MC		 6549 ring_prod = TX_RING_IDX(prod);
6550
6551 vlan_tag_flags = 0;
84fa7933 6552 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6553 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6554 }
6555
eab6d18d 6556 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6557 vlan_tag_flags |=
6558 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6559 }
7d0fd211 6560
fde82055 6561 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6562 u32 tcp_opt_len;
eddc9ec5 6563 struct iphdr *iph;
b6016b76 6564
b6016b76
MC		 6565 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6566
4666f87a
MC		 6567 tcp_opt_len = tcp_optlen(skb);
6568
6569 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6570 u32 tcp_off = skb_transport_offset(skb) -
6571 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6572
4666f87a
MC		 6573 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6574 TX_BD_FLAGS_SW_FLAGS;
6575 if (likely(tcp_off == 0))
6576 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6577 else {
6578 tcp_off >>= 3;
6579 vlan_tag_flags |= ((tcp_off & 0x3) <<
6580 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6581 ((tcp_off & 0x10) <<
6582 TX_BD_FLAGS_TCP6_OFF4_SHL);
6583 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6584 }
6585 } else {
4666f87a 6586 iph = ip_hdr(skb);
4666f87a
MC		 6587 if (tcp_opt_len || (iph->ihl > 5)) {
6588 vlan_tag_flags |= ((iph->ihl - 5) +
6589 (tcp_opt_len >> 2)) << 8;
6590 }
b6016b76 6591 }
4666f87a 6592 } else
b6016b76 6593 mss = 0;
b6016b76 6594
36227e88
SG		 6595 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6596 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6597 dev_kfree_skb(skb);
6598 return NETDEV_TX_OK;
6599 }
6600
35e9010b 6601 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6602 tx_buf->skb = skb;
1a4ccc2d 6603 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6604
35e9010b 6605 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6606
6607 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6608 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6609 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6610 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6611
6612 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6613 tx_buf->nr_frags = last_frag;
6614 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6615
6616 for (i = 0; i < last_frag; i++) {
9e903e08 6617 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
b6016b76
MC		 6618
6619 prod = NEXT_TX_BD(prod);
6620 ring_prod = TX_RING_IDX(prod);
35e9010b 6621 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76 6622
9e903e08 6623 len = skb_frag_size(frag);
b7b6a688 6624 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
5d6bcdfe 6625 DMA_TO_DEVICE);
36227e88 6626 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6627 goto dma_error;
1a4ccc2d 6628 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6629 mapping);
b6016b76
MC		 6630
6631 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6632 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6633 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6634 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6635
6636 }
6637 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6638
94bf91ba
VZ		 6639 /* Sync BD data before updating TX mailbox */
6640 wmb();
6641
e9831909
ED		 6642 netdev_tx_sent_queue(txq, skb->len);
6643
b6016b76 6644 prod = NEXT_TX_BD(prod);
35e9010b 6645 txr->tx_prod_bseq += skb->len;
b6016b76 6646
35e9010b
MC		 6647 REG_WR16(bp, txr->tx_bidx_addr, prod);
6648 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6649
6650 mmiowb();
6651
35e9010b 6652 txr->tx_prod = prod;
b6016b76 6653
35e9010b 6654 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6655 netif_tx_stop_queue(txq);
11848b96
MC		 6656
6657 /* netif_tx_stop_queue() must be done before checking
6658 * tx index in bnx2_tx_avail() below, because in
6659 * bnx2_tx_int(), we update tx index before checking for
6660 * netif_tx_queue_stopped().
6661 */
6662 smp_mb();
35e9010b 6663 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6664 netif_tx_wake_queue(txq);
b6016b76
MC		 6665 }
6666
e95524a7
AD		 6667 return NETDEV_TX_OK;
6668dma_error:
6669 /* save value of frag that failed */
6670 last_frag = i;
6671
6672 /* start back at beginning and unmap skb */
6673 prod = txr->tx_prod;
6674 ring_prod = TX_RING_IDX(prod);
6675 tx_buf = &txr->tx_buf_ring[ring_prod];
6676 tx_buf->skb = NULL;
36227e88 6677 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6678 skb_headlen(skb), PCI_DMA_TODEVICE);
6679
6680 /* unmap remaining mapped pages */
6681 for (i = 0; i < last_frag; i++) {
6682 prod = NEXT_TX_BD(prod);
6683 ring_prod = TX_RING_IDX(prod);
6684 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6685 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
9e903e08 6686 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7
AD		 6687 PCI_DMA_TODEVICE);
6688 }
6689
6690 dev_kfree_skb(skb);
b6016b76
MC		 6691 return NETDEV_TX_OK;
6692}
6693
6694/* Called with rtnl_lock */
6695static int
6696bnx2_close(struct net_device *dev)
6697{
972ec0d4 6698 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6699
bea3348e 6700 bnx2_disable_int_sync(bp);
35efa7c1 6701 bnx2_napi_disable(bp);
b6016b76 6702 del_timer_sync(&bp->timer);
74bf4ba3 6703 bnx2_shutdown_chip(bp);
8e6a72c4 6704 bnx2_free_irq(bp);
b6016b76
MC		 6705 bnx2_free_skbs(bp);
6706 bnx2_free_mem(bp);
f048fa9c 6707 bnx2_del_napi(bp);
b6016b76
MC		 6708 bp->link_up = 0;
6709 netif_carrier_off(bp->dev);
829ca9a3 6710 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6711 return 0;
6712}
6713
354fcd77
MC		 6714static void
6715bnx2_save_stats(struct bnx2 *bp)
6716{
6717 u32 *hw_stats = (u32 *) bp->stats_blk;
6718 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6719 int i;
6720
6721 /* The 1st 10 counters are 64-bit counters */
6722 for (i = 0; i < 20; i += 2) {
6723 u32 hi;
6724 u64 lo;
6725
c9885fe5
PR		 6726 hi = temp_stats[i] + hw_stats[i];
6727 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6728 if (lo > 0xffffffff)
6729 hi++;
c9885fe5
PR		 6730 temp_stats[i] = hi;
6731 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6732 }
6733
6734 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6735 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6736}
6737
5d07bf26
ED		 6738#define GET_64BIT_NET_STATS64(ctr) \
6739 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6740
a4743058 6741#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6742 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6743 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6744
a4743058 6745#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6746 (unsigned long) (bp->stats_blk->ctr + \
6747 bp->temp_stats_blk->ctr)
a4743058 6748
5d07bf26
ED		 6749static struct rtnl_link_stats64 *
6750bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6751{
972ec0d4 6752 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6753
5d07bf26 6754 if (bp->stats_blk == NULL)
b6016b76 6755 return net_stats;
5d07bf26 6756
b6016b76 6757 net_stats->rx_packets =
a4743058
MC		 6758 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6759 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6760 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6761
6762 net_stats->tx_packets =
a4743058
MC		 6763 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6764 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6765 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6766
6767 net_stats->rx_bytes =
a4743058 6768 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6769
6770 net_stats->tx_bytes =
a4743058 6771 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6772
6aa20a22 6773 net_stats->multicast =
6fdae995 6774 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6775
6aa20a22 6776 net_stats->collisions =
a4743058 6777 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6778
6aa20a22 6779 net_stats->rx_length_errors =
a4743058
MC		 6780 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6781 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6782
6aa20a22 6783 net_stats->rx_over_errors =
a4743058
MC		 6784 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6785 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6786
6aa20a22 6787 net_stats->rx_frame_errors =
a4743058 6788 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6789
6aa20a22 6790 net_stats->rx_crc_errors =
a4743058 6791 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6792
6793 net_stats->rx_errors = net_stats->rx_length_errors +
6794 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6795 net_stats->rx_crc_errors;
6796
6797 net_stats->tx_aborted_errors =
a4743058
MC		 6798 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6799 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6800
5b0c76ad
MC		 6801 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6802 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6803 net_stats->tx_carrier_errors = 0;
6804 else {
6805 net_stats->tx_carrier_errors =
a4743058 6806 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6807 }
6808
6809 net_stats->tx_errors =
a4743058 6810 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6811 net_stats->tx_aborted_errors +
6812 net_stats->tx_carrier_errors;
6813
cea94db9 6814 net_stats->rx_missed_errors =
a4743058
MC		 6815 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6816 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6817 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6818
b6016b76
MC		 6819 return net_stats;
6820}
6821
6822/* All ethtool functions called with rtnl_lock */
6823
6824static int
6825bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6826{
972ec0d4 6827 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6828 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6829
6830 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6831 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6832 support_serdes = 1;
6833 support_copper = 1;
6834 } else if (bp->phy_port == PORT_FIBRE)
6835 support_serdes = 1;
6836 else
6837 support_copper = 1;
6838
6839 if (support_serdes) {
b6016b76
MC		 6840 cmd->supported |= SUPPORTED_1000baseT_Full |
6841 SUPPORTED_FIBRE;
583c28e5 6842 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6843 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6844
b6016b76 6845 }
7b6b8347 6846 if (support_copper) {
b6016b76
MC		 6847 cmd->supported |= SUPPORTED_10baseT_Half |
6848 SUPPORTED_10baseT_Full |
6849 SUPPORTED_100baseT_Half |
6850 SUPPORTED_100baseT_Full |
6851 SUPPORTED_1000baseT_Full |
6852 SUPPORTED_TP;
6853
b6016b76
MC		 6854 }
6855
7b6b8347
MC		 6856 spin_lock_bh(&bp->phy_lock);
6857 cmd->port = bp->phy_port;
b6016b76
MC		 6858 cmd->advertising = bp->advertising;
6859
6860 if (bp->autoneg & AUTONEG_SPEED) {
6861 cmd->autoneg = AUTONEG_ENABLE;
70739497 6862 } else {
b6016b76
MC		 6863 cmd->autoneg = AUTONEG_DISABLE;
6864 }
6865
6866 if (netif_carrier_ok(dev)) {
70739497 6867 ethtool_cmd_speed_set(cmd, bp->line_speed);
b6016b76
MC		 6868 cmd->duplex = bp->duplex;
6869 }
6870 else {
70739497 6871 ethtool_cmd_speed_set(cmd, -1);
b6016b76
MC		 6872 cmd->duplex = -1;
6873 }
7b6b8347 6874 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6875
6876 cmd->transceiver = XCVR_INTERNAL;
6877 cmd->phy_address = bp->phy_addr;
6878
6879 return 0;
6880}
6aa20a22 6881
b6016b76
MC		 6882static int
6883bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6884{
972ec0d4 6885 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6886 u8 autoneg = bp->autoneg;
6887 u8 req_duplex = bp->req_duplex;
6888 u16 req_line_speed = bp->req_line_speed;
6889 u32 advertising = bp->advertising;
7b6b8347
MC		 6890 int err = -EINVAL;
6891
6892 spin_lock_bh(&bp->phy_lock);
6893
6894 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6895 goto err_out_unlock;
6896
583c28e5
MC		 6897 if (cmd->port != bp->phy_port &&
6898 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6899 goto err_out_unlock;
b6016b76 6900
d6b14486
MC		 6901 /* If device is down, we can store the settings only if the user
6902 * is setting the currently active port.
6903 */
6904 if (!netif_running(dev) && cmd->port != bp->phy_port)
6905 goto err_out_unlock;
6906
b6016b76
MC		 6907 if (cmd->autoneg == AUTONEG_ENABLE) {
6908 autoneg |= AUTONEG_SPEED;
6909
beb499af
MC		 6910 advertising = cmd->advertising;
6911 if (cmd->port == PORT_TP) {
6912 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6913 if (!advertising)
b6016b76 6914 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6915 } else {
6916 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6917 if (!advertising)
6918 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6919 }
6920 advertising |= ADVERTISED_Autoneg;
6921 }
6922 else {
25db0338 6923 u32 speed = ethtool_cmd_speed(cmd);
7b6b8347 6924 if (cmd->port == PORT_FIBRE) {
25db0338
DD		 6925 if ((speed != SPEED_1000 &&
6926 speed != SPEED_2500) ||
80be4434 6927 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6928 goto err_out_unlock;
80be4434 6929
25db0338 6930 if (speed == SPEED_2500 &&
583c28e5 6931 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6932 goto err_out_unlock;
25db0338 6933 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 6934 goto err_out_unlock;
6935
b6016b76 6936 autoneg &= ~AUTONEG_SPEED;
25db0338 6937 req_line_speed = speed;
b6016b76
MC		 6938 req_duplex = cmd->duplex;
6939 advertising = 0;
6940 }
6941
6942 bp->autoneg = autoneg;
6943 bp->advertising = advertising;
6944 bp->req_line_speed = req_line_speed;
6945 bp->req_duplex = req_duplex;
6946
d6b14486
MC		 6947 err = 0;
6948 /* If device is down, the new settings will be picked up when it is
6949 * brought up.
6950 */
6951 if (netif_running(dev))
6952 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6953
7b6b8347 6954err_out_unlock:
c770a65c 6955 spin_unlock_bh(&bp->phy_lock);
b6016b76 6956
7b6b8347 6957 return err;
b6016b76
MC		 6958}
6959
6960static void
6961bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6962{
972ec0d4 6963 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6964
68aad78c
RJ		 6965 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6966 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6967 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
6968 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
b6016b76
MC		 6969}
6970
244ac4f4
MC		 6971#define BNX2_REGDUMP_LEN (32 * 1024)
6972
6973static int
6974bnx2_get_regs_len(struct net_device *dev)
6975{
6976 return BNX2_REGDUMP_LEN;
6977}
6978
6979static void
6980bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6981{
6982 u32 *p = _p, i, offset;
6983 u8 *orig_p = _p;
6984 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6985 static const u32 reg_boundaries[] = {
6986 0x0000, 0x0098, 0x0400, 0x045c,
6987 0x0800, 0x0880, 0x0c00, 0x0c10,
6988 0x0c30, 0x0d08, 0x1000, 0x101c,
6989 0x1040, 0x1048, 0x1080, 0x10a4,
6990 0x1400, 0x1490, 0x1498, 0x14f0,
6991 0x1500, 0x155c, 0x1580, 0x15dc,
6992 0x1600, 0x1658, 0x1680, 0x16d8,
6993 0x1800, 0x1820, 0x1840, 0x1854,
6994 0x1880, 0x1894, 0x1900, 0x1984,
6995 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6996 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6997 0x2000, 0x2030, 0x23c0, 0x2400,
6998 0x2800, 0x2820, 0x2830, 0x2850,
6999 0x2b40, 0x2c10, 0x2fc0, 0x3058,
7000 0x3c00, 0x3c94, 0x4000, 0x4010,
7001 0x4080, 0x4090, 0x43c0, 0x4458,
7002 0x4c00, 0x4c18, 0x4c40, 0x4c54,
7003 0x4fc0, 0x5010, 0x53c0, 0x5444,
7004 0x5c00, 0x5c18, 0x5c80, 0x5c90,
7005 0x5fc0, 0x6000, 0x6400, 0x6428,
7006 0x6800, 0x6848, 0x684c, 0x6860,
7007 0x6888, 0x6910, 0x8000
7008 };
244ac4f4
MC		 7009
7010 regs->version = 0;
7011
7012 memset(p, 0, BNX2_REGDUMP_LEN);
7013
7014 if (!netif_running(bp->dev))
7015 return;
7016
7017 i = 0;
7018 offset = reg_boundaries[0];
7019 p += offset;
7020 while (offset < BNX2_REGDUMP_LEN) {
7021 *p++ = REG_RD(bp, offset);
7022 offset += 4;
7023 if (offset == reg_boundaries[i + 1]) {
7024 offset = reg_boundaries[i + 2];
7025 p = (u32 *) (orig_p + offset);
7026 i += 2;
7027 }
7028 }
7029}
7030
b6016b76
MC		 7031static void
7032bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7033{
972ec0d4 7034 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7035
f86e82fb 7036 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 7037 wol->supported = 0;
7038 wol->wolopts = 0;
7039 }
7040 else {
7041 wol->supported = WAKE_MAGIC;
7042 if (bp->wol)
7043 wol->wolopts = WAKE_MAGIC;
7044 else
7045 wol->wolopts = 0;
7046 }
7047 memset(&wol->sopass, 0, sizeof(wol->sopass));
7048}
7049
7050static int
7051bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7052{
972ec0d4 7053 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7054
7055 if (wol->wolopts & ~WAKE_MAGIC)
7056 return -EINVAL;
7057
7058 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 7059 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 7060 return -EINVAL;
7061
7062 bp->wol = 1;
7063 }
7064 else {
7065 bp->wol = 0;
7066 }
7067 return 0;
7068}
7069
7070static int
7071bnx2_nway_reset(struct net_device *dev)
7072{
972ec0d4 7073 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7074 u32 bmcr;
7075
9f52b564
MC		 7076 if (!netif_running(dev))
7077 return -EAGAIN;
7078
b6016b76
MC		 7079 if (!(bp->autoneg & AUTONEG_SPEED)) {
7080 return -EINVAL;
7081 }
7082
c770a65c 7083 spin_lock_bh(&bp->phy_lock);
b6016b76 7084
583c28e5 7085 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 7086 int rc;
7087
7088 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7089 spin_unlock_bh(&bp->phy_lock);
7090 return rc;
7091 }
7092
b6016b76 7093 /* Force a link down visible on the other side */
583c28e5 7094 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 7095 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 7096 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7097
7098 msleep(20);
7099
c770a65c 7100 spin_lock_bh(&bp->phy_lock);
f8dd064e 7101
40105c0b 7102 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 7103 bp->serdes_an_pending = 1;
7104 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 7105 }
7106
ca58c3af 7107 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 7108 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 7109 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 7110
c770a65c 7111 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7112
7113 return 0;
7114}
7115
7959ea25
ON		 7116static u32
7117bnx2_get_link(struct net_device *dev)
7118{
7119 struct bnx2 *bp = netdev_priv(dev);
7120
7121 return bp->link_up;
7122}
7123
b6016b76
MC		 7124static int
7125bnx2_get_eeprom_len(struct net_device *dev)
7126{
972ec0d4 7127 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7128
1122db71 7129 if (bp->flash_info == NULL)
b6016b76
MC		 7130 return 0;
7131
1122db71 7132 return (int) bp->flash_size;
b6016b76
MC		 7133}
7134
7135static int
7136bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7137 u8 *eebuf)
7138{
972ec0d4 7139 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7140 int rc;
7141
9f52b564
MC		 7142 if (!netif_running(dev))
7143 return -EAGAIN;
7144
1064e944 7145 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7146
7147 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7148
7149 return rc;
7150}
7151
7152static int
7153bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7154 u8 *eebuf)
7155{
972ec0d4 7156 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7157 int rc;
7158
9f52b564
MC		 7159 if (!netif_running(dev))
7160 return -EAGAIN;
7161
1064e944 7162 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7163
7164 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7165
7166 return rc;
7167}
7168
7169static int
7170bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7171{
972ec0d4 7172 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7173
7174 memset(coal, 0, sizeof(struct ethtool_coalesce));
7175
7176 coal->rx_coalesce_usecs = bp->rx_ticks;
7177 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7178 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7179 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7180
7181 coal->tx_coalesce_usecs = bp->tx_ticks;
7182 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7183 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7184 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7185
7186 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7187
7188 return 0;
7189}
7190
7191static int
7192bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7193{
972ec0d4 7194 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7195
7196 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7197 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7198
6aa20a22 7199 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7200 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7201
7202 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7203 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7204
7205 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7206 if (bp->rx_quick_cons_trip_int > 0xff)
7207 bp->rx_quick_cons_trip_int = 0xff;
7208
7209 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7210 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7211
7212 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7213 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7214
7215 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7216 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7217
7218 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7219 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7220 0xff;
7221
7222 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7223 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7224 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7225 bp->stats_ticks = USEC_PER_SEC;
7226 }
7ea6920e
MC		 7227 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7228 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7229 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7230
7231 if (netif_running(bp->dev)) {
212f9934 7232 bnx2_netif_stop(bp, true);
9a120bc5 7233 bnx2_init_nic(bp, 0);
212f9934 7234 bnx2_netif_start(bp, true);
b6016b76
MC		 7235 }
7236
7237 return 0;
7238}
7239
7240static void
7241bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7242{
972ec0d4 7243 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7244
13daffa2 7245 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
47bf4246 7246 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7247
7248 ering->rx_pending = bp->rx_ring_size;
47bf4246 7249 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7250
7251 ering->tx_max_pending = MAX_TX_DESC_CNT;
7252 ering->tx_pending = bp->tx_ring_size;
7253}
7254
7255static int
b033281f 7256bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
b6016b76 7257{
13daffa2 7258 if (netif_running(bp->dev)) {
354fcd77
MC		 7259 /* Reset will erase chipset stats; save them */
7260 bnx2_save_stats(bp);
7261
212f9934 7262 bnx2_netif_stop(bp, true);
13daffa2 7263 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
b033281f
MC		 7264 if (reset_irq) {
7265 bnx2_free_irq(bp);
7266 bnx2_del_napi(bp);
7267 } else {
7268 __bnx2_free_irq(bp);
7269 }
13daffa2
MC		 7270 bnx2_free_skbs(bp);
7271 bnx2_free_mem(bp);
7272 }
7273
5d5d0015
MC		 7274 bnx2_set_rx_ring_size(bp, rx);
7275 bp->tx_ring_size = tx;
b6016b76
MC		 7276
7277 if (netif_running(bp->dev)) {
b033281f
MC		 7278 int rc = 0;
7279
7280 if (reset_irq) {
7281 rc = bnx2_setup_int_mode(bp, disable_msi);
7282 bnx2_init_napi(bp);
7283 }
7284
7285 if (!rc)
7286 rc = bnx2_alloc_mem(bp);
13daffa2 7287
a29ba9d2
MC		 7288 if (!rc)
7289 rc = bnx2_request_irq(bp);
7290
6fefb65e
MC		 7291 if (!rc)
7292 rc = bnx2_init_nic(bp, 0);
7293
7294 if (rc) {
7295 bnx2_napi_enable(bp);
7296 dev_close(bp->dev);
13daffa2 7297 return rc;
6fefb65e 7298 }
e9f26c49
MC		 7299#ifdef BCM_CNIC
7300 mutex_lock(&bp->cnic_lock);
7301 /* Let cnic know about the new status block. */
7302 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7303 bnx2_setup_cnic_irq_info(bp);
7304 mutex_unlock(&bp->cnic_lock);
7305#endif
212f9934 7306 bnx2_netif_start(bp, true);
b6016b76 7307 }
b6016b76
MC		 7308 return 0;
7309}
7310
5d5d0015
MC		 7311static int
7312bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7313{
7314 struct bnx2 *bp = netdev_priv(dev);
7315 int rc;
7316
7317 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7318 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7319 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7320
7321 return -EINVAL;
7322 }
b033281f
MC		 7323 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7324 false);
5d5d0015
MC		 7325 return rc;
7326}
7327
b6016b76
MC		 7328static void
7329bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7330{
972ec0d4 7331 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7332
7333 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7334 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7335 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7336}
7337
7338static int
7339bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7340{
972ec0d4 7341 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7342
7343 bp->req_flow_ctrl = 0;
7344 if (epause->rx_pause)
7345 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7346 if (epause->tx_pause)
7347 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7348
7349 if (epause->autoneg) {
7350 bp->autoneg |= AUTONEG_FLOW_CTRL;
7351 }
7352 else {
7353 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7354 }
7355
9f52b564
MC		 7356 if (netif_running(dev)) {
7357 spin_lock_bh(&bp->phy_lock);
7358 bnx2_setup_phy(bp, bp->phy_port);
7359 spin_unlock_bh(&bp->phy_lock);
7360 }
b6016b76
MC		 7361
7362 return 0;
7363}
7364
14ab9b86 7365static struct {
b6016b76 7366 char string[ETH_GSTRING_LEN];
790dab2f 7367} bnx2_stats_str_arr[] = {
b6016b76
MC		 7368 { "rx_bytes" },
7369 { "rx_error_bytes" },
7370 { "tx_bytes" },
7371 { "tx_error_bytes" },
7372 { "rx_ucast_packets" },
7373 { "rx_mcast_packets" },
7374 { "rx_bcast_packets" },
7375 { "tx_ucast_packets" },
7376 { "tx_mcast_packets" },
7377 { "tx_bcast_packets" },
7378 { "tx_mac_errors" },
7379 { "tx_carrier_errors" },
7380 { "rx_crc_errors" },
7381 { "rx_align_errors" },
7382 { "tx_single_collisions" },
7383 { "tx_multi_collisions" },
7384 { "tx_deferred" },
7385 { "tx_excess_collisions" },
7386 { "tx_late_collisions" },
7387 { "tx_total_collisions" },
7388 { "rx_fragments" },
7389 { "rx_jabbers" },
7390 { "rx_undersize_packets" },
7391 { "rx_oversize_packets" },
7392 { "rx_64_byte_packets" },
7393 { "rx_65_to_127_byte_packets" },
7394 { "rx_128_to_255_byte_packets" },
7395 { "rx_256_to_511_byte_packets" },
7396 { "rx_512_to_1023_byte_packets" },
7397 { "rx_1024_to_1522_byte_packets" },
7398 { "rx_1523_to_9022_byte_packets" },
7399 { "tx_64_byte_packets" },
7400 { "tx_65_to_127_byte_packets" },
7401 { "tx_128_to_255_byte_packets" },
7402 { "tx_256_to_511_byte_packets" },
7403 { "tx_512_to_1023_byte_packets" },
7404 { "tx_1024_to_1522_byte_packets" },
7405 { "tx_1523_to_9022_byte_packets" },
7406 { "rx_xon_frames" },
7407 { "rx_xoff_frames" },
7408 { "tx_xon_frames" },
7409 { "tx_xoff_frames" },
7410 { "rx_mac_ctrl_frames" },
7411 { "rx_filtered_packets" },
790dab2f 7412 { "rx_ftq_discards" },
b6016b76 7413 { "rx_discards" },
cea94db9 7414 { "rx_fw_discards" },
b6016b76
MC		 7415};
7416
0db83cd8 7417#define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
790dab2f 7418
b6016b76
MC		 7419#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7420
f71e1309 7421static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7422 STATS_OFFSET32(stat_IfHCInOctets_hi),
7423 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7424 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7425 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7426 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7427 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7428 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7429 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7430 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7431 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7432 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7433 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7434 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7435 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7436 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7437 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7438 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7439 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7440 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7441 STATS_OFFSET32(stat_EtherStatsCollisions),
7442 STATS_OFFSET32(stat_EtherStatsFragments),
7443 STATS_OFFSET32(stat_EtherStatsJabbers),
7444 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7445 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7446 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7447 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7448 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7449 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7450 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7451 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7452 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7453 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7454 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7455 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7456 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7457 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7458 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7459 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7460 STATS_OFFSET32(stat_XonPauseFramesReceived),
7461 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7462 STATS_OFFSET32(stat_OutXonSent),
7463 STATS_OFFSET32(stat_OutXoffSent),
7464 STATS_OFFSET32(stat_MacControlFramesReceived),
7465 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7466 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7467 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7468 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7469};
7470
7471/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7472 * skipped because of errata.
6aa20a22 7473 */
14ab9b86 7474static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7475 8,0,8,8,8,8,8,8,8,8,
7476 4,0,4,4,4,4,4,4,4,4,
7477 4,4,4,4,4,4,4,4,4,4,
7478 4,4,4,4,4,4,4,4,4,4,
790dab2f 7479 4,4,4,4,4,4,4,
b6016b76
MC		 7480};
7481
5b0c76ad
MC		 7482static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7483 8,0,8,8,8,8,8,8,8,8,
7484 4,4,4,4,4,4,4,4,4,4,
7485 4,4,4,4,4,4,4,4,4,4,
7486 4,4,4,4,4,4,4,4,4,4,
790dab2f 7487 4,4,4,4,4,4,4,
5b0c76ad
MC		 7488};
7489
b6016b76
MC		 7490#define BNX2_NUM_TESTS 6
7491
14ab9b86 7492static struct {
b6016b76
MC		 7493 char string[ETH_GSTRING_LEN];
7494} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7495 { "register_test (offline)" },
7496 { "memory_test (offline)" },
7497 { "loopback_test (offline)" },
7498 { "nvram_test (online)" },
7499 { "interrupt_test (online)" },
7500 { "link_test (online)" },
7501};
7502
7503static int
b9f2c044 7504bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7505{
b9f2c044
JG		 7506 switch (sset) {
7507 case ETH_SS_TEST:
7508 return BNX2_NUM_TESTS;
7509 case ETH_SS_STATS:
7510 return BNX2_NUM_STATS;
7511 default:
7512 return -EOPNOTSUPP;
7513 }
b6016b76
MC		 7514}
7515
7516static void
7517bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7518{
972ec0d4 7519 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7520
9f52b564
MC		 7521 bnx2_set_power_state(bp, PCI_D0);
7522
b6016b76
MC		 7523 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7524 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7525 int i;
7526
212f9934 7527 bnx2_netif_stop(bp, true);
b6016b76
MC		 7528 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7529 bnx2_free_skbs(bp);
7530
7531 if (bnx2_test_registers(bp) != 0) {
7532 buf[0] = 1;
7533 etest->flags |= ETH_TEST_FL_FAILED;
7534 }
7535 if (bnx2_test_memory(bp) != 0) {
7536 buf[1] = 1;
7537 etest->flags |= ETH_TEST_FL_FAILED;
7538 }
bc5a0690 7539 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7540 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7541
9f52b564
MC		 7542 if (!netif_running(bp->dev))
7543 bnx2_shutdown_chip(bp);
b6016b76 7544 else {
9a120bc5 7545 bnx2_init_nic(bp, 1);
212f9934 7546 bnx2_netif_start(bp, true);
b6016b76
MC		 7547 }
7548
7549 /* wait for link up */
80be4434
MC		 7550 for (i = 0; i < 7; i++) {
7551 if (bp->link_up)
7552 break;
7553 msleep_interruptible(1000);
7554 }
b6016b76
MC		 7555 }
7556
7557 if (bnx2_test_nvram(bp) != 0) {
7558 buf[3] = 1;
7559 etest->flags |= ETH_TEST_FL_FAILED;
7560 }
7561 if (bnx2_test_intr(bp) != 0) {
7562 buf[4] = 1;
7563 etest->flags |= ETH_TEST_FL_FAILED;
7564 }
7565
7566 if (bnx2_test_link(bp) != 0) {
7567 buf[5] = 1;
7568 etest->flags |= ETH_TEST_FL_FAILED;
7569
7570 }
9f52b564
MC		 7571 if (!netif_running(bp->dev))
7572 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7573}
7574
7575static void
7576bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7577{
7578 switch (stringset) {
7579 case ETH_SS_STATS:
7580 memcpy(buf, bnx2_stats_str_arr,
7581 sizeof(bnx2_stats_str_arr));
7582 break;
7583 case ETH_SS_TEST:
7584 memcpy(buf, bnx2_tests_str_arr,
7585 sizeof(bnx2_tests_str_arr));
7586 break;
7587 }
7588}
7589
b6016b76
MC		 7590static void
7591bnx2_get_ethtool_stats(struct net_device *dev,
7592 struct ethtool_stats *stats, u64 *buf)
7593{
972ec0d4 7594 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7595 int i;
7596 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7597 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7598 u8 *stats_len_arr = NULL;
b6016b76
MC		 7599
7600 if (hw_stats == NULL) {
7601 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7602 return;
7603 }
7604
5b0c76ad
MC		 7605 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7606 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7607 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7608 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7609 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7610 else
7611 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7612
7613 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7614 unsigned long offset;
7615
b6016b76
MC		 7616 if (stats_len_arr[i] == 0) {
7617 /* skip this counter */
7618 buf[i] = 0;
7619 continue;
7620 }
354fcd77
MC		 7621
7622 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7623 if (stats_len_arr[i] == 4) {
7624 /* 4-byte counter */
354fcd77
MC		 7625 buf[i] = (u64) *(hw_stats + offset) +
7626 *(temp_stats + offset);
b6016b76
MC		 7627 continue;
7628 }
7629 /* 8-byte counter */
354fcd77
MC		 7630 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7631 *(hw_stats + offset + 1) +
7632 (((u64) *(temp_stats + offset)) << 32) +
7633 *(temp_stats + offset + 1);
b6016b76
MC		 7634 }
7635}
7636
7637static int
2e17e1aa 7638bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7639{
972ec0d4 7640 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7641
2e17e1aa 7642 switch (state) {
7643 case ETHTOOL_ID_ACTIVE:
7644 bnx2_set_power_state(bp, PCI_D0);
9f52b564 7645
2e17e1aa 7646 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7647 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7648 return 1; /* cycle on/off once per second */
b6016b76 7649
2e17e1aa 7650 case ETHTOOL_ID_ON:
7651 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7652 BNX2_EMAC_LED_1000MB_OVERRIDE |
7653 BNX2_EMAC_LED_100MB_OVERRIDE |
7654 BNX2_EMAC_LED_10MB_OVERRIDE |
7655 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7656 BNX2_EMAC_LED_TRAFFIC);
7657 break;
b6016b76 7658
2e17e1aa 7659 case ETHTOOL_ID_OFF:
7660 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7661 break;
9f52b564 7662
2e17e1aa 7663 case ETHTOOL_ID_INACTIVE:
7664 REG_WR(bp, BNX2_EMAC_LED, 0);
7665 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7666
7667 if (!netif_running(dev))
7668 bnx2_set_power_state(bp, PCI_D3hot);
7669 break;
7670 }
9f52b564 7671
b6016b76
MC		 7672 return 0;
7673}
7674
c8f44aff
MM		 7675static netdev_features_t
7676bnx2_fix_features(struct net_device *dev, netdev_features_t features)
4666f87a
MC		 7677{
7678 struct bnx2 *bp = netdev_priv(dev);
7679
8d7dfc2b
MM		 7680 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7681 features |= NETIF_F_HW_VLAN_RX;
7682
7683 return features;
4666f87a
MC		 7684}
7685
fdc8541d 7686static int
c8f44aff 7687bnx2_set_features(struct net_device *dev, netdev_features_t features)
fdc8541d 7688{
7d0fd211 7689 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7690
7c810477 7691 /* TSO with VLAN tag won't work with current firmware */
8d7dfc2b
MM		 7692 if (features & NETIF_F_HW_VLAN_TX)
7693 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7694 else
7695 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7696
8d7dfc2b 7697 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7d0fd211
JG		 7698 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7699 netif_running(dev)) {
7700 bnx2_netif_stop(bp, false);
8d7dfc2b 7701 dev->features = features;
7d0fd211
JG		 7702 bnx2_set_rx_mode(dev);
7703 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7704 bnx2_netif_start(bp, false);
8d7dfc2b 7705 return 1;
7d0fd211
JG		 7706 }
7707
7708 return 0;
fdc8541d
MC		 7709}
7710
b033281f
MC		 7711static void bnx2_get_channels(struct net_device *dev,
7712 struct ethtool_channels *channels)
7713{
7714 struct bnx2 *bp = netdev_priv(dev);
7715 u32 max_rx_rings = 1;
7716 u32 max_tx_rings = 1;
7717
7718 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7719 max_rx_rings = RX_MAX_RINGS;
7720 max_tx_rings = TX_MAX_RINGS;
7721 }
7722
7723 channels->max_rx = max_rx_rings;
7724 channels->max_tx = max_tx_rings;
7725 channels->max_other = 0;
7726 channels->max_combined = 0;
7727 channels->rx_count = bp->num_rx_rings;
7728 channels->tx_count = bp->num_tx_rings;
7729 channels->other_count = 0;
7730 channels->combined_count = 0;
7731}
7732
7733static int bnx2_set_channels(struct net_device *dev,
7734 struct ethtool_channels *channels)
7735{
7736 struct bnx2 *bp = netdev_priv(dev);
7737 u32 max_rx_rings = 1;
7738 u32 max_tx_rings = 1;
7739 int rc = 0;
7740
7741 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7742 max_rx_rings = RX_MAX_RINGS;
7743 max_tx_rings = TX_MAX_RINGS;
7744 }
7745 if (channels->rx_count > max_rx_rings ||
7746 channels->tx_count > max_tx_rings)
7747 return -EINVAL;
7748
7749 bp->num_req_rx_rings = channels->rx_count;
7750 bp->num_req_tx_rings = channels->tx_count;
7751
7752 if (netif_running(dev))
7753 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7754 bp->tx_ring_size, true);
7755
7756 return rc;
7757}
7758
7282d491 7759static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7760 .get_settings = bnx2_get_settings,
7761 .set_settings = bnx2_set_settings,
7762 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7763 .get_regs_len = bnx2_get_regs_len,
7764 .get_regs = bnx2_get_regs,
b6016b76
MC		 7765 .get_wol = bnx2_get_wol,
7766 .set_wol = bnx2_set_wol,
7767 .nway_reset = bnx2_nway_reset,
7959ea25 7768 .get_link = bnx2_get_link,
b6016b76
MC		 7769 .get_eeprom_len = bnx2_get_eeprom_len,
7770 .get_eeprom = bnx2_get_eeprom,
7771 .set_eeprom = bnx2_set_eeprom,
7772 .get_coalesce = bnx2_get_coalesce,
7773 .set_coalesce = bnx2_set_coalesce,
7774 .get_ringparam = bnx2_get_ringparam,
7775 .set_ringparam = bnx2_set_ringparam,
7776 .get_pauseparam = bnx2_get_pauseparam,
7777 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7778 .self_test = bnx2_self_test,
7779 .get_strings = bnx2_get_strings,
2e17e1aa 7780 .set_phys_id = bnx2_set_phys_id,
b6016b76 7781 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7782 .get_sset_count = bnx2_get_sset_count,
b033281f
MC		 7783 .get_channels = bnx2_get_channels,
7784 .set_channels = bnx2_set_channels,
b6016b76
MC		 7785};
7786
7787/* Called with rtnl_lock */
7788static int
7789bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7790{
14ab9b86 7791 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7792 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7793 int err;
7794
7795 switch(cmd) {
7796 case SIOCGMIIPHY:
7797 data->phy_id = bp->phy_addr;
7798
7799 /* fallthru */
7800 case SIOCGMIIREG: {
7801 u32 mii_regval;
7802
583c28e5 7803 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7804 return -EOPNOTSUPP;
7805
dad3e452
MC		 7806 if (!netif_running(dev))
7807 return -EAGAIN;
7808
c770a65c 7809 spin_lock_bh(&bp->phy_lock);
b6016b76 7810 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7811 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7812
7813 data->val_out = mii_regval;
7814
7815 return err;
7816 }
7817
7818 case SIOCSMIIREG:
583c28e5 7819 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7820 return -EOPNOTSUPP;
7821
dad3e452
MC		 7822 if (!netif_running(dev))
7823 return -EAGAIN;
7824
c770a65c 7825 spin_lock_bh(&bp->phy_lock);
b6016b76 7826 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7827 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7828
7829 return err;
7830
7831 default:
7832 /* do nothing */
7833 break;
7834 }
7835 return -EOPNOTSUPP;
7836}
7837
7838/* Called with rtnl_lock */
7839static int
7840bnx2_change_mac_addr(struct net_device *dev, void *p)
7841{
7842 struct sockaddr *addr = p;
972ec0d4 7843 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7844
73eef4cd 7845 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 7846 return -EADDRNOTAVAIL;
73eef4cd 7847
b6016b76
MC		 7848 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7849 if (netif_running(dev))
5fcaed01 7850 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7851
7852 return 0;
7853}
7854
7855/* Called with rtnl_lock */
7856static int
7857bnx2_change_mtu(struct net_device *dev, int new_mtu)
7858{
972ec0d4 7859 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7860
7861 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7862 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7863 return -EINVAL;
7864
7865 dev->mtu = new_mtu;
b033281f
MC		 7866 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7867 false);
b6016b76
MC		 7868}
7869
257ddbda 7870#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7871static void
7872poll_bnx2(struct net_device *dev)
7873{
972ec0d4 7874 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7875 int i;
b6016b76 7876
b2af2c1d 7877 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7878 struct bnx2_irq *irq = &bp->irq_tbl[i];
7879
7880 disable_irq(irq->vector);
7881 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7882 enable_irq(irq->vector);
b2af2c1d 7883 }
b6016b76
MC		 7884}
7885#endif
7886
253c8b75
MC		 7887static void __devinit
7888bnx2_get_5709_media(struct bnx2 *bp)
7889{
7890 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7891 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7892 u32 strap;
7893
7894 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7895 return;
7896 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7897 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7898 return;
7899 }
7900
7901 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7902 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7903 else
7904 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7905
7906 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7907 switch (strap) {
7908 case 0x4:
7909 case 0x5:
7910 case 0x6:
583c28e5 7911 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7912 return;
7913 }
7914 } else {
7915 switch (strap) {
7916 case 0x1:
7917 case 0x2:
7918 case 0x4:
583c28e5 7919 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7920 return;
7921 }
7922 }
7923}
7924
883e5151
MC		 7925static void __devinit
7926bnx2_get_pci_speed(struct bnx2 *bp)
7927{
7928 u32 reg;
7929
7930 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7931 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7932 u32 clkreg;
7933
f86e82fb 7934 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7935
7936 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7937
7938 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7939 switch (clkreg) {
7940 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7941 bp->bus_speed_mhz = 133;
7942 break;
7943
7944 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7945 bp->bus_speed_mhz = 100;
7946 break;
7947
7948 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7949 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7950 bp->bus_speed_mhz = 66;
7951 break;
7952
7953 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7954 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7955 bp->bus_speed_mhz = 50;
7956 break;
7957
7958 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7959 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7960 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7961 bp->bus_speed_mhz = 33;
7962 break;
7963 }
7964 }
7965 else {
7966 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7967 bp->bus_speed_mhz = 66;
7968 else
7969 bp->bus_speed_mhz = 33;
7970 }
7971
7972 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7973 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7974
7975}
7976
76d99061
MC		 7977static void __devinit
7978bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7979{
df25bc38 7980 int rc, i, j;
76d99061 7981 u8 *data;
df25bc38 7982 unsigned int block_end, rosize, len;
76d99061 7983
012093f6
MC		 7984#define BNX2_VPD_NVRAM_OFFSET 0x300
7985#define BNX2_VPD_LEN 128
76d99061
MC		 7986#define BNX2_MAX_VER_SLEN 30
7987
7988 data = kmalloc(256, GFP_KERNEL);
7989 if (!data)
7990 return;
7991
012093f6
MC		 7992 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7993 BNX2_VPD_LEN);
76d99061
MC		 7994 if (rc)
7995 goto vpd_done;
7996
012093f6
MC		 7997 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7998 data[i] = data[i + BNX2_VPD_LEN + 3];
7999 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
8000 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
8001 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 8002 }
8003
df25bc38
MC		 8004 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
8005 if (i < 0)
8006 goto vpd_done;
76d99061 8007
df25bc38
MC		 8008 rosize = pci_vpd_lrdt_size(&data[i]);
8009 i += PCI_VPD_LRDT_TAG_SIZE;
8010 block_end = i + rosize;
76d99061 8011
df25bc38
MC		 8012 if (block_end > BNX2_VPD_LEN)
8013 goto vpd_done;
76d99061 8014
df25bc38
MC		 8015 j = pci_vpd_find_info_keyword(data, i, rosize,
8016 PCI_VPD_RO_KEYWORD_MFR_ID);
8017 if (j < 0)
8018 goto vpd_done;
76d99061 8019
df25bc38 8020 len = pci_vpd_info_field_size(&data[j]);
76d99061 8021
df25bc38
MC		 8022 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8023 if (j + len > block_end || len != 4 ||
8024 memcmp(&data[j], "1028", 4))
8025 goto vpd_done;
4067a854 8026
df25bc38
MC		 8027 j = pci_vpd_find_info_keyword(data, i, rosize,
8028 PCI_VPD_RO_KEYWORD_VENDOR0);
8029 if (j < 0)
8030 goto vpd_done;
4067a854 8031
df25bc38 8032 len = pci_vpd_info_field_size(&data[j]);
4067a854 8033
df25bc38
MC		 8034 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8035 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 8036 goto vpd_done;
df25bc38
MC		 8037
8038 memcpy(bp->fw_version, &data[j], len);
8039 bp->fw_version[len] = ' ';
76d99061
MC		 8040
8041vpd_done:
8042 kfree(data);
8043}
8044
b6016b76
MC		 8045static int __devinit
8046bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8047{
8048 struct bnx2 *bp;
58fc2ea4 8049 int rc, i, j;
b6016b76 8050 u32 reg;
40453c83 8051 u64 dma_mask, persist_dma_mask;
cd709aa9 8052 int err;
b6016b76 8053
b6016b76 8054 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 8055 bp = netdev_priv(dev);
b6016b76
MC		 8056
8057 bp->flags = 0;
8058 bp->phy_flags = 0;
8059
354fcd77
MC		 8060 bp->temp_stats_blk =
8061 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
8062
8063 if (bp->temp_stats_blk == NULL) {
8064 rc = -ENOMEM;
8065 goto err_out;
8066 }
8067
b6016b76
MC		 8068 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8069 rc = pci_enable_device(pdev);
8070 if (rc) {
3a9c6a49 8071 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 8072 goto err_out;
8073 }
8074
8075 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 8076 dev_err(&pdev->dev,
3a9c6a49 8077 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 8078 rc = -ENODEV;
8079 goto err_out_disable;
8080 }
8081
8082 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8083 if (rc) {
3a9c6a49 8084 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 8085 goto err_out_disable;
8086 }
8087
8088 pci_set_master(pdev);
8089
8090 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
8091 if (bp->pm_cap == 0) {
9b91cf9d 8092 dev_err(&pdev->dev,
3a9c6a49 8093 "Cannot find power management capability, aborting\n");
b6016b76
MC		 8094 rc = -EIO;
8095 goto err_out_release;
8096 }
8097
b6016b76
MC		 8098 bp->dev = dev;
8099 bp->pdev = pdev;
8100
8101 spin_lock_init(&bp->phy_lock);
1b8227c4 8102 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 8103#ifdef BCM_CNIC
8104 mutex_init(&bp->cnic_lock);
8105#endif
c4028958 8106 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76 8107
c0357e97
FR		 8108 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8109 TX_MAX_TSS_RINGS + 1));
b6016b76 8110 if (!bp->regview) {
3a9c6a49 8111 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 8112 rc = -ENOMEM;
8113 goto err_out_release;
8114 }
8115
be7ff1af
MC		 8116 bnx2_set_power_state(bp, PCI_D0);
8117
b6016b76
MC		 8118 /* Configure byte swap and enable write to the reg_window registers.
8119 * Rely on CPU to do target byte swapping on big endian systems
8120 * The chip's target access swapping will not swap all accesses
8121 */
be7ff1af
MC		 8122 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8123 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
8124 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76
MC		 8125
8126 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
8127
883e5151 8128 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
e82760e7
JM		 8129 if (!pci_is_pcie(pdev)) {
8130 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 8131 rc = -EIO;
8132 goto err_out_unmap;
8133 }
f86e82fb 8134 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 8135 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 8136 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 8137
8138 /* AER (Advanced Error Reporting) hooks */
8139 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8140 if (!err)
8141 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 8142
883e5151 8143 } else {
59b47d8a
MC		 8144 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8145 if (bp->pcix_cap == 0) {
8146 dev_err(&pdev->dev,
3a9c6a49 8147 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 8148 rc = -EIO;
8149 goto err_out_unmap;
8150 }
61d9e3fa 8151 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 8152 }
8153
b4b36042
MC		 8154 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
8155 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 8156 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 8157 }
8158
8e6a72c4
MC		 8159 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
8160 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 8161 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 8162 }
8163
40453c83
MC		 8164 /* 5708 cannot support DMA addresses > 40-bit. */
8165 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 8166 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8167 else
6a35528a 8168 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8169
8170 /* Configure DMA attributes. */
8171 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8172 dev->features |= NETIF_F_HIGHDMA;
8173 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8174 if (rc) {
8175 dev_err(&pdev->dev,
3a9c6a49 8176 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8177 goto err_out_unmap;
8178 }
284901a9 8179 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8180 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8181 goto err_out_unmap;
8182 }
8183
f86e82fb 8184 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8185 bnx2_get_pci_speed(bp);
b6016b76
MC		 8186
8187 /* 5706A0 may falsely detect SERR and PERR. */
8188 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8189 reg = REG_RD(bp, PCI_COMMAND);
8190 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8191 REG_WR(bp, PCI_COMMAND, reg);
8192 }
8193 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8194 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8195
9b91cf9d 8196 dev_err(&pdev->dev,
3a9c6a49 8197 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8198 goto err_out_unmap;
8199 }
8200
8201 bnx2_init_nvram(bp);
8202
2726d6e1 8203 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8204
8205 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8206 BNX2_SHM_HDR_SIGNATURE_SIG) {
8207 u32 off = PCI_FUNC(pdev->devfn) << 2;
8208
2726d6e1 8209 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8210 } else
e3648b3d
MC		 8211 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8212
b6016b76
MC		 8213 /* Get the permanent MAC address. First we need to make sure the
8214 * firmware is actually running.
8215 */
2726d6e1 8216 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8217
8218 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8219 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8220 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8221 rc = -ENODEV;
8222 goto err_out_unmap;
8223 }
8224
76d99061
MC		 8225 bnx2_read_vpd_fw_ver(bp);
8226
8227 j = strlen(bp->fw_version);
2726d6e1 8228 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8229 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8230 u8 num, k, skip0;
8231
76d99061
MC		 8232 if (i == 0) {
8233 bp->fw_version[j++] = 'b';
8234 bp->fw_version[j++] = 'c';
8235 bp->fw_version[j++] = ' ';
8236 }
58fc2ea4
MC		 8237 num = (u8) (reg >> (24 - (i * 8)));
8238 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8239 if (num >= k || !skip0 || k == 1) {
8240 bp->fw_version[j++] = (num / k) + '0';
8241 skip0 = 0;
8242 }
8243 }
8244 if (i != 2)
8245 bp->fw_version[j++] = '.';
8246 }
2726d6e1 8247 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8248 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8249 bp->wol = 1;
8250
8251 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8252 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8253
8254 for (i = 0; i < 30; i++) {
2726d6e1 8255 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8256 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8257 break;
8258 msleep(10);
8259 }
8260 }
2726d6e1 8261 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8262 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8263 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8264 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8265 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8266
76d99061
MC		 8267 if (j < 32)
8268 bp->fw_version[j++] = ' ';
8269 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8270 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8271 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8272 memcpy(&bp->fw_version[j], &reg, 4);
8273 j += 4;
8274 }
8275 }
b6016b76 8276
2726d6e1 8277 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8278 bp->mac_addr[0] = (u8) (reg >> 8);
8279 bp->mac_addr[1] = (u8) reg;
8280
2726d6e1 8281 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8282 bp->mac_addr[2] = (u8) (reg >> 24);
8283 bp->mac_addr[3] = (u8) (reg >> 16);
8284 bp->mac_addr[4] = (u8) (reg >> 8);
8285 bp->mac_addr[5] = (u8) reg;
8286
8287 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8288 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8289
cf7474a6 8290 bp->tx_quick_cons_trip_int = 2;
b6016b76 8291 bp->tx_quick_cons_trip = 20;
cf7474a6 8292 bp->tx_ticks_int = 18;
b6016b76 8293 bp->tx_ticks = 80;
6aa20a22 8294
cf7474a6
MC		 8295 bp->rx_quick_cons_trip_int = 2;
8296 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8297 bp->rx_ticks_int = 18;
8298 bp->rx_ticks = 18;
8299
7ea6920e 8300 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8301
ac392abc 8302 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8303
5b0c76ad
MC		 8304 bp->phy_addr = 1;
8305
b6016b76 8306 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8307 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8308 bnx2_get_5709_media(bp);
8309 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8310 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8311
0d8a6571 8312 bp->phy_port = PORT_TP;
583c28e5 8313 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8314 bp->phy_port = PORT_FIBRE;
2726d6e1 8315 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8316 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8317 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8318 bp->wol = 0;
8319 }
38ea3686
MC		 8320 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8321 /* Don't do parallel detect on this board because of
8322 * some board problems. The link will not go down
8323 * if we do parallel detect.
8324 */
8325 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8326 pdev->subsystem_device == 0x310c)
8327 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8328 } else {
5b0c76ad 8329 bp->phy_addr = 2;
5b0c76ad 8330 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8331 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8332 }
261dd5ca
MC		 8333 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8334 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8335 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8336 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8337 (CHIP_REV(bp) == CHIP_REV_Ax ||
8338 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8339 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8340
7c62e83b
MC		 8341 bnx2_init_fw_cap(bp);
8342
16088272
MC		 8343 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8344 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8345 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8346 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8347 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8348 bp->wol = 0;
8349 }
dda1e390 8350
b6016b76
MC		 8351 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8352 bp->tx_quick_cons_trip_int =
8353 bp->tx_quick_cons_trip;
8354 bp->tx_ticks_int = bp->tx_ticks;
8355 bp->rx_quick_cons_trip_int =
8356 bp->rx_quick_cons_trip;
8357 bp->rx_ticks_int = bp->rx_ticks;
8358 bp->comp_prod_trip_int = bp->comp_prod_trip;
8359 bp->com_ticks_int = bp->com_ticks;
8360 bp->cmd_ticks_int = bp->cmd_ticks;
8361 }
8362
f9317a40
MC		 8363 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8364 *
8365 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8366 * with byte enables disabled on the unused 32-bit word. This is legal
8367 * but causes problems on the AMD 8132 which will eventually stop
8368 * responding after a while.
8369 *
8370 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8371 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8372 */
8373 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8374 struct pci_dev *amd_8132 = NULL;
8375
8376 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8377 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8378 amd_8132))) {
f9317a40 8379
44c10138
AK		 8380 if (amd_8132->revision >= 0x10 &&
8381 amd_8132->revision <= 0x13) {
f9317a40
MC		 8382 disable_msi = 1;
8383 pci_dev_put(amd_8132);
8384 break;
8385 }
8386 }
8387 }
8388
deaf391b 8389 bnx2_set_default_link(bp);
b6016b76
MC		 8390 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8391
cd339a0e 8392 init_timer(&bp->timer);
ac392abc 8393 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8394 bp->timer.data = (unsigned long) bp;
8395 bp->timer.function = bnx2_timer;
8396
7625eb2f 8397#ifdef BCM_CNIC
41c2178a
MC		 8398 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8399 bp->cnic_eth_dev.max_iscsi_conn =
8400 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8401 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
7625eb2f 8402#endif
c239f279
MC		 8403 pci_save_state(pdev);
8404
b6016b76
MC		 8405 return 0;
8406
8407err_out_unmap:
4bb9ebc7 8408 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8409 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8410 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8411 }
c239f279 8412
c0357e97
FR		 8413 pci_iounmap(pdev, bp->regview);
8414 bp->regview = NULL;
b6016b76
MC		 8415
8416err_out_release:
8417 pci_release_regions(pdev);
8418
8419err_out_disable:
8420 pci_disable_device(pdev);
8421 pci_set_drvdata(pdev, NULL);
8422
8423err_out:
8424 return rc;
8425}
8426
883e5151
MC		 8427static char * __devinit
8428bnx2_bus_string(struct bnx2 *bp, char *str)
8429{
8430 char *s = str;
8431
f86e82fb 8432 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8433 s += sprintf(s, "PCI Express");
8434 } else {
8435 s += sprintf(s, "PCI");
f86e82fb 8436 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8437 s += sprintf(s, "-X");
f86e82fb 8438 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8439 s += sprintf(s, " 32-bit");
8440 else
8441 s += sprintf(s, " 64-bit");
8442 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8443 }
8444 return str;
8445}
8446
f048fa9c
MC		 8447static void
8448bnx2_del_napi(struct bnx2 *bp)
8449{
8450 int i;
8451
8452 for (i = 0; i < bp->irq_nvecs; i++)
8453 netif_napi_del(&bp->bnx2_napi[i].napi);
8454}
8455
8456static void
35efa7c1
MC		 8457bnx2_init_napi(struct bnx2 *bp)
8458{
b4b36042 8459 int i;
35efa7c1 8460
4327ba43 8461 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8462 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8463 int (*poll)(struct napi_struct *, int);
8464
8465 if (i == 0)
8466 poll = bnx2_poll;
8467 else
f0ea2e63 8468 poll = bnx2_poll_msix;
35e9010b
MC		 8469
8470 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8471 bnapi->bp = bp;
8472 }
35efa7c1
MC		 8473}
8474
0421eae6
SH		 8475static const struct net_device_ops bnx2_netdev_ops = {
8476 .ndo_open = bnx2_open,
8477 .ndo_start_xmit = bnx2_start_xmit,
8478 .ndo_stop = bnx2_close,
5d07bf26 8479 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8480 .ndo_set_rx_mode = bnx2_set_rx_mode,
8481 .ndo_do_ioctl = bnx2_ioctl,
8482 .ndo_validate_addr = eth_validate_addr,
8483 .ndo_set_mac_address = bnx2_change_mac_addr,
8484 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b
MM		 8485 .ndo_fix_features = bnx2_fix_features,
8486 .ndo_set_features = bnx2_set_features,
0421eae6 8487 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8488#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8489 .ndo_poll_controller = poll_bnx2,
8490#endif
8491};
8492
b6016b76
MC		 8493static int __devinit
8494bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8495{
8496 static int version_printed = 0;
c0357e97 8497 struct net_device *dev;
b6016b76 8498 struct bnx2 *bp;
0795af57 8499 int rc;
883e5151 8500 char str[40];
b6016b76
MC		 8501
8502 if (version_printed++ == 0)
3a9c6a49 8503 pr_info("%s", version);
b6016b76
MC		 8504
8505 /* dev zeroed in init_etherdev */
706bf240 8506 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8507 if (!dev)
8508 return -ENOMEM;
8509
8510 rc = bnx2_init_board(pdev, dev);
c0357e97
FR		 8511 if (rc < 0)
8512 goto err_free;
b6016b76 8513
0421eae6 8514 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8515 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8516 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8517
972ec0d4 8518 bp = netdev_priv(dev);
b6016b76 8519
1b2f922f
MC		 8520 pci_set_drvdata(pdev, dev);
8521
8522 memcpy(dev->dev_addr, bp->mac_addr, 6);
8523 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8524
8d7dfc2b
MM		 8525 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8526 NETIF_F_TSO | NETIF_F_TSO_ECN |
8527 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8528
8529 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8530 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8531
8532 dev->vlan_features = dev->hw_features;
8533 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8534 dev->features |= dev->hw_features;
01789349 8535 dev->priv_flags |= IFF_UNICAST_FLT;
8d7dfc2b 8536
b6016b76 8537 if ((rc = register_netdev(dev))) {
9b91cf9d 8538 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8539 goto error;
b6016b76
MC		 8540 }
8541
c0357e97
FR		 8542 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
8543 "node addr %pM\n", board_info[ent->driver_data].name,
3a9c6a49
JP		 8544 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8545 ((CHIP_ID(bp) & 0x0ff0) >> 4),
c0357e97
FR		 8546 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8547 pdev->irq, dev->dev_addr);
b6016b76 8548
b6016b76 8549 return 0;
57579f76
MC		 8550
8551error:
c0357e97 8552 iounmap(bp->regview);
57579f76
MC		 8553 pci_release_regions(pdev);
8554 pci_disable_device(pdev);
8555 pci_set_drvdata(pdev, NULL);
c0357e97 8556err_free:
57579f76
MC		 8557 free_netdev(dev);
8558 return rc;
b6016b76
MC		 8559}
8560
8561static void __devexit
8562bnx2_remove_one(struct pci_dev *pdev)
8563{
8564 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8565 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8566
8567 unregister_netdev(dev);
8568
8333a46a 8569 del_timer_sync(&bp->timer);
cd634019 8570 cancel_work_sync(&bp->reset_task);
8333a46a 8571
c0357e97 8572 pci_iounmap(bp->pdev, bp->regview);
b6016b76 8573
354fcd77
MC		 8574 kfree(bp->temp_stats_blk);
8575
4bb9ebc7 8576 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8577 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8578 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8579 }
cd709aa9 8580
7880b72e 8581 bnx2_release_firmware(bp);
8582
c239f279 8583 free_netdev(dev);
cd709aa9 8584
b6016b76
MC		 8585 pci_release_regions(pdev);
8586 pci_disable_device(pdev);
8587 pci_set_drvdata(pdev, NULL);
8588}
8589
8590static int
829ca9a3 8591bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8592{
8593 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8594 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8595
6caebb02
MC		 8596 /* PCI register 4 needs to be saved whether netif_running() or not.
8597 * MSI address and data need to be saved if using MSI and
8598 * netif_running().
8599 */
8600 pci_save_state(pdev);
b6016b76
MC		 8601 if (!netif_running(dev))
8602 return 0;
8603
23f333a2 8604 cancel_work_sync(&bp->reset_task);
212f9934 8605 bnx2_netif_stop(bp, true);
b6016b76
MC		 8606 netif_device_detach(dev);
8607 del_timer_sync(&bp->timer);
74bf4ba3 8608 bnx2_shutdown_chip(bp);
b6016b76 8609 bnx2_free_skbs(bp);
829ca9a3 8610 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8611 return 0;
8612}
8613
8614static int
8615bnx2_resume(struct pci_dev *pdev)
8616{
8617 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8618 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8619
6caebb02 8620 pci_restore_state(pdev);
b6016b76
MC		 8621 if (!netif_running(dev))
8622 return 0;
8623
829ca9a3 8624 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8625 netif_device_attach(dev);
9a120bc5 8626 bnx2_init_nic(bp, 1);
212f9934 8627 bnx2_netif_start(bp, true);
b6016b76
MC		 8628 return 0;
8629}
8630
6ff2da49
WX		 8631/**
8632 * bnx2_io_error_detected - called when PCI error is detected
8633 * @pdev: Pointer to PCI device
8634 * @state: The current pci connection state
8635 *
8636 * This function is called after a PCI bus error affecting
8637 * this device has been detected.
8638 */
8639static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8640 pci_channel_state_t state)
8641{
8642 struct net_device *dev = pci_get_drvdata(pdev);
8643 struct bnx2 *bp = netdev_priv(dev);
8644
8645 rtnl_lock();
8646 netif_device_detach(dev);
8647
2ec3de26
DN		 8648 if (state == pci_channel_io_perm_failure) {
8649 rtnl_unlock();
8650 return PCI_ERS_RESULT_DISCONNECT;
8651 }
8652
6ff2da49 8653 if (netif_running(dev)) {
212f9934 8654 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8655 del_timer_sync(&bp->timer);
8656 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8657 }
8658
8659 pci_disable_device(pdev);
8660 rtnl_unlock();
8661
8662 /* Request a slot slot reset. */
8663 return PCI_ERS_RESULT_NEED_RESET;
8664}
8665
8666/**
8667 * bnx2_io_slot_reset - called after the pci bus has been reset.
8668 * @pdev: Pointer to PCI device
8669 *
8670 * Restart the card from scratch, as if from a cold-boot.
8671 */
8672static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8673{
8674 struct net_device *dev = pci_get_drvdata(pdev);
8675 struct bnx2 *bp = netdev_priv(dev);
cd709aa9
JF		 8676 pci_ers_result_t result;
8677 int err;
6ff2da49
WX		 8678
8679 rtnl_lock();
8680 if (pci_enable_device(pdev)) {
8681 dev_err(&pdev->dev,
3a9c6a49 8682 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8683 result = PCI_ERS_RESULT_DISCONNECT;
8684 } else {
8685 pci_set_master(pdev);
8686 pci_restore_state(pdev);
8687 pci_save_state(pdev);
8688
8689 if (netif_running(dev)) {
8690 bnx2_set_power_state(bp, PCI_D0);
8691 bnx2_init_nic(bp, 1);
8692 }
8693 result = PCI_ERS_RESULT_RECOVERED;
6ff2da49 8694 }
cd709aa9 8695 rtnl_unlock();
6ff2da49 8696
4bb9ebc7 8697 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8698 return result;
8699
cd709aa9
JF		 8700 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8701 if (err) {
8702 dev_err(&pdev->dev,
8703 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8704 err); /* non-fatal, continue */
6ff2da49
WX		 8705 }
8706
cd709aa9 8707 return result;
6ff2da49
WX		 8708}
8709
8710/**
8711 * bnx2_io_resume - called when traffic can start flowing again.
8712 * @pdev: Pointer to PCI device
8713 *
8714 * This callback is called when the error recovery driver tells us that
8715 * its OK to resume normal operation.
8716 */
8717static void bnx2_io_resume(struct pci_dev *pdev)
8718{
8719 struct net_device *dev = pci_get_drvdata(pdev);
8720 struct bnx2 *bp = netdev_priv(dev);
8721
8722 rtnl_lock();
8723 if (netif_running(dev))
212f9934 8724 bnx2_netif_start(bp, true);
6ff2da49
WX		 8725
8726 netif_device_attach(dev);
8727 rtnl_unlock();
8728}
8729
8730static struct pci_error_handlers bnx2_err_handler = {
8731 .error_detected = bnx2_io_error_detected,
8732 .slot_reset = bnx2_io_slot_reset,
8733 .resume = bnx2_io_resume,
8734};
8735
b6016b76 8736static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8737 .name = DRV_MODULE_NAME,
8738 .id_table = bnx2_pci_tbl,
8739 .probe = bnx2_init_one,
8740 .remove = __devexit_p(bnx2_remove_one),
8741 .suspend = bnx2_suspend,
8742 .resume = bnx2_resume,
6ff2da49 8743 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8744};
8745
8746static int __init bnx2_init(void)
8747{
29917620 8748 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8749}
8750
8751static void __exit bnx2_cleanup(void)
8752{
8753 pci_unregister_driver(&bnx2_pci_driver);
8754}
8755
8756module_init(bnx2_init);
8757module_exit(bnx2_cleanup);
8758
8759
8760
Linux kernel - Deliverables
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