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arch: Mass conversion of smp_mb__*()
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_cmn.c
CommitLineData
9f6c9258
DK		 1/* bnx2x_cmn.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
9f6c9258
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
9f6c9258 20#include <linux/etherdevice.h>
9bcc0893 21#include <linux/if_vlan.h>
a6b7a407 22#include <linux/interrupt.h>
9f6c9258 23#include <linux/ip.h>
9969085e 24#include <net/tcp.h>
f2e0899f 25#include <net/ipv6.h>
7f3e01fe 26#include <net/ip6_checksum.h>
076bb0c8 27#include <net/busy_poll.h>
c0cba59e 28#include <linux/prefetch.h>
9f6c9258 29#include "bnx2x_cmn.h"
523224a3 30#include "bnx2x_init.h"
042181f5 31#include "bnx2x_sp.h"
9f6c9258 32
a8f47eb7 33static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
34static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
35static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
36static int bnx2x_poll(struct napi_struct *napi, int budget);
37
38static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
39{
40 int i;
41
42 /* Add NAPI objects */
43 for_each_rx_queue_cnic(bp, i) {
44 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
45 bnx2x_poll, NAPI_POLL_WEIGHT);
46 napi_hash_add(&bnx2x_fp(bp, i, napi));
47 }
48}
49
50static void bnx2x_add_all_napi(struct bnx2x *bp)
51{
52 int i;
53
54 /* Add NAPI objects */
55 for_each_eth_queue(bp, i) {
56 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
57 bnx2x_poll, NAPI_POLL_WEIGHT);
58 napi_hash_add(&bnx2x_fp(bp, i, napi));
59 }
60}
61
62static int bnx2x_calc_num_queues(struct bnx2x *bp)
63{
7d0445d6 64 int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues();
ff2ad307
MS		 65
66 /* Reduce memory usage in kdump environment by using only one queue */
67 if (reset_devices)
68 nq = 1;
69
7d0445d6
MS		 70 nq = clamp(nq, 1, BNX2X_MAX_QUEUES(bp));
71 return nq;
a8f47eb7 72}
73
b3b83c3f
DK		 74/**
75 * bnx2x_move_fp - move content of the fastpath structure.
76 *
77 * @bp: driver handle
78 * @from: source FP index
79 * @to: destination FP index
80 *
81 * Makes sure the contents of the bp->fp[to].napi is kept
72754080
AE		 82 * intact. This is done by first copying the napi struct from
83 * the target to the source, and then mem copying the entire
65565884
MS		 84 * source onto the target. Update txdata pointers and related
85 * content.
b3b83c3f
DK		 86 */
87static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
88{
89 struct bnx2x_fastpath *from_fp = &bp->fp[from];
90 struct bnx2x_fastpath *to_fp = &bp->fp[to];
15192a8c
BW		 91 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
92 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
93 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
94 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
65565884
MS		 95 int old_max_eth_txqs, new_max_eth_txqs;
96 int old_txdata_index = 0, new_txdata_index = 0;
34d5626a 97 struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
72754080
AE		 98
99 /* Copy the NAPI object as it has been already initialized */
100 from_fp->napi = to_fp->napi;
101
b3b83c3f
DK		 102 /* Move bnx2x_fastpath contents */
103 memcpy(to_fp, from_fp, sizeof(*to_fp));
104 to_fp->index = to;
65565884 105
34d5626a
YM		 106 /* Retain the tpa_info of the original `to' version as we don't want
107 * 2 FPs to contain the same tpa_info pointer.
108 */
109 to_fp->tpa_info = old_tpa_info;
110
15192a8c
BW		 111 /* move sp_objs contents as well, as their indices match fp ones */
112 memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
113
114 /* move fp_stats contents as well, as their indices match fp ones */
115 memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
116
65565884
MS		 117 /* Update txdata pointers in fp and move txdata content accordingly:
118 * Each fp consumes 'max_cos' txdata structures, so the index should be
119 * decremented by max_cos x delta.
120 */
121
122 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
123 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
124 (bp)->max_cos;
125 if (from == FCOE_IDX(bp)) {
126 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
127 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
128 }
129
4864a16a
YM		 130 memcpy(&bp->bnx2x_txq[new_txdata_index],
131 &bp->bnx2x_txq[old_txdata_index],
65565884
MS		 132 sizeof(struct bnx2x_fp_txdata));
133 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
b3b83c3f
DK		 134}
135
8ca5e17e
AE		 136/**
137 * bnx2x_fill_fw_str - Fill buffer with FW version string.
138 *
139 * @bp: driver handle
140 * @buf: character buffer to fill with the fw name
141 * @buf_len: length of the above buffer
142 *
143 */
144void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
145{
146 if (IS_PF(bp)) {
147 u8 phy_fw_ver[PHY_FW_VER_LEN];
148
149 phy_fw_ver[0] = '\0';
150 bnx2x_get_ext_phy_fw_version(&bp->link_params,
151 phy_fw_ver, PHY_FW_VER_LEN);
152 strlcpy(buf, bp->fw_ver, buf_len);
153 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
154 "bc %d.%d.%d%s%s",
155 (bp->common.bc_ver & 0xff0000) >> 16,
156 (bp->common.bc_ver & 0xff00) >> 8,
157 (bp->common.bc_ver & 0xff),
158 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
159 } else {
6411280a 160 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
8ca5e17e
AE		 161 }
162}
163
4864a16a
YM		 164/**
165 * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
166 *
167 * @bp: driver handle
168 * @delta: number of eth queues which were not allocated
169 */
170static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
171{
172 int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
173
174 /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
16a5fd92 175 * backward along the array could cause memory to be overridden
4864a16a
YM		 176 */
177 for (cos = 1; cos < bp->max_cos; cos++) {
178 for (i = 0; i < old_eth_num - delta; i++) {
179 struct bnx2x_fastpath *fp = &bp->fp[i];
180 int new_idx = cos * (old_eth_num - delta) + i;
181
182 memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
183 sizeof(struct bnx2x_fp_txdata));
184 fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
185 }
186 }
187}
188
a8f47eb7 189int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
619c5cb6 190
9f6c9258
DK		 191/* free skb in the packet ring at pos idx
192 * return idx of last bd freed
193 */
6383c0b3 194static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
2df1a70a
TH		 195 u16 idx, unsigned int *pkts_compl,
196 unsigned int *bytes_compl)
9f6c9258 197{
6383c0b3 198 struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
9f6c9258
DK		 199 struct eth_tx_start_bd *tx_start_bd;
200 struct eth_tx_bd *tx_data_bd;
201 struct sk_buff *skb = tx_buf->skb;
202 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
203 int nbd;
95e92fd4 204 u16 split_bd_len = 0;
9f6c9258
DK		 205
206 /* prefetch skb end pointer to speedup dev_kfree_skb() */
207 prefetch(&skb->end);
208
51c1a580 209 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
6383c0b3 210 txdata->txq_index, idx, tx_buf, skb);
9f6c9258 211
6383c0b3 212 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
9f6c9258
DK		 213
214 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
215#ifdef BNX2X_STOP_ON_ERROR
216 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
217 BNX2X_ERR("BAD nbd!\n");
218 bnx2x_panic();
219 }
220#endif
221 new_cons = nbd + tx_buf->first_bd;
222
223 /* Get the next bd */
224 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
225
226 /* Skip a parse bd... */
227 --nbd;
228 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
229
95e92fd4 230 /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
9f6c9258 231 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
95e92fd4
MS		 232 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
233 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
9f6c9258
DK		 234 --nbd;
235 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
236 }
237
95e92fd4
MS		 238 /* unmap first bd */
239 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
240 BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
241 DMA_TO_DEVICE);
242
9f6c9258
DK		 243 /* now free frags */
244 while (nbd > 0) {
245
6383c0b3 246 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
9f6c9258
DK		 247 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
248 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
249 if (--nbd)
250 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
251 }
252
253 /* release skb */
254 WARN_ON(!skb);
d8290ae5 255 if (likely(skb)) {
2df1a70a
TH		 256 (*pkts_compl)++;
257 (*bytes_compl) += skb->len;
258 }
d8290ae5 259
40955532 260 dev_kfree_skb_any(skb);
9f6c9258
DK		 261 tx_buf->first_bd = 0;
262 tx_buf->skb = NULL;
263
264 return new_cons;
265}
266
6383c0b3 267int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
9f6c9258 268{
9f6c9258 269 struct netdev_queue *txq;
6383c0b3 270 u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
2df1a70a 271 unsigned int pkts_compl = 0, bytes_compl = 0;
9f6c9258
DK		 272
273#ifdef BNX2X_STOP_ON_ERROR
274 if (unlikely(bp->panic))
275 return -1;
276#endif
277
6383c0b3
AE		 278 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
279 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
280 sw_cons = txdata->tx_pkt_cons;
9f6c9258
DK		 281
282 while (sw_cons != hw_cons) {
283 u16 pkt_cons;
284
285 pkt_cons = TX_BD(sw_cons);
286
51c1a580
MS		 287 DP(NETIF_MSG_TX_DONE,
288 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
6383c0b3 289 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
9f6c9258 290
2df1a70a 291 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
2de67439 292 &pkts_compl, &bytes_compl);
2df1a70a 293
9f6c9258
DK		 294 sw_cons++;
295 }
296
2df1a70a
TH		 297 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298
6383c0b3
AE		 299 txdata->tx_pkt_cons = sw_cons;
300 txdata->tx_bd_cons = bd_cons;
9f6c9258
DK		 301
302 /* Need to make the tx_bd_cons update visible to start_xmit()
303 * before checking for netif_tx_queue_stopped(). Without the
304 * memory barrier, there is a small possibility that
305 * start_xmit() will miss it and cause the queue to be stopped
306 * forever.
619c5cb6
VZ		 307 * On the other hand we need an rmb() here to ensure the proper
308 * ordering of bit testing in the following
309 * netif_tx_queue_stopped(txq) call.
9f6c9258
DK		 310 */
311 smp_mb();
312
9f6c9258 313 if (unlikely(netif_tx_queue_stopped(txq))) {
16a5fd92 314 /* Taking tx_lock() is needed to prevent re-enabling the queue
9f6c9258
DK		 315 * while it's empty. This could have happen if rx_action() gets
316 * suspended in bnx2x_tx_int() after the condition before
317 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
318 *
319 * stops the queue->sees fresh tx_bd_cons->releases the queue->
320 * sends some packets consuming the whole queue again->
321 * stops the queue
322 */
323
324 __netif_tx_lock(txq, smp_processor_id());
325
326 if ((netif_tx_queue_stopped(txq)) &&
327 (bp->state == BNX2X_STATE_OPEN) &&
7df2dc6b 328 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
9f6c9258
DK		 329 netif_tx_wake_queue(txq);
330
331 __netif_tx_unlock(txq);
332 }
333 return 0;
334}
335
336static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
337 u16 idx)
338{
339 u16 last_max = fp->last_max_sge;
340
341 if (SUB_S16(idx, last_max) > 0)
342 fp->last_max_sge = idx;
343}
344
621b4d66
DK		 345static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
346 u16 sge_len,
347 struct eth_end_agg_rx_cqe *cqe)
9f6c9258
DK		 348{
349 struct bnx2x *bp = fp->bp;
9f6c9258
DK		 350 u16 last_max, last_elem, first_elem;
351 u16 delta = 0;
352 u16 i;
353
354 if (!sge_len)
355 return;
356
357 /* First mark all used pages */
358 for (i = 0; i < sge_len; i++)
619c5cb6 359 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
621b4d66 360 RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
9f6c9258
DK		 361
362 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
621b4d66 363 sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
9f6c9258
DK		 364
365 /* Here we assume that the last SGE index is the biggest */
366 prefetch((void *)(fp->sge_mask));
523224a3 367 bnx2x_update_last_max_sge(fp,
621b4d66 368 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
9f6c9258
DK		 369
370 last_max = RX_SGE(fp->last_max_sge);
619c5cb6
VZ		 371 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
372 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
9f6c9258
DK		 373
374 /* If ring is not full */
375 if (last_elem + 1 != first_elem)
376 last_elem++;
377
378 /* Now update the prod */
379 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
380 if (likely(fp->sge_mask[i]))
381 break;
382
619c5cb6
VZ		 383 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
384 delta += BIT_VEC64_ELEM_SZ;
9f6c9258
DK		 385 }
386
387 if (delta > 0) {
388 fp->rx_sge_prod += delta;
389 /* clear page-end entries */
390 bnx2x_clear_sge_mask_next_elems(fp);
391 }
392
393 DP(NETIF_MSG_RX_STATUS,
394 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
395 fp->last_max_sge, fp->rx_sge_prod);
396}
397
2de67439 398/* Get Toeplitz hash value in the skb using the value from the
e52fcb24
ED		 399 * CQE (calculated by HW).
400 */
401static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
a334b5fb 402 const struct eth_fast_path_rx_cqe *cqe,
5495ab75 403 enum pkt_hash_types *rxhash_type)
e52fcb24 404{
2de67439 405 /* Get Toeplitz hash from CQE */
e52fcb24 406 if ((bp->dev->features & NETIF_F_RXHASH) &&
a334b5fb
ED		 407 (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
408 enum eth_rss_hash_type htype;
409
410 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
5495ab75
TH		 411 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
412 (htype == TCP_IPV6_HASH_TYPE)) ?
413 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
414
e52fcb24 415 return le32_to_cpu(cqe->rss_hash_result);
a334b5fb 416 }
5495ab75 417 *rxhash_type = PKT_HASH_TYPE_NONE;
e52fcb24
ED		 418 return 0;
419}
420
9f6c9258 421static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
e52fcb24 422 u16 cons, u16 prod,
619c5cb6 423 struct eth_fast_path_rx_cqe *cqe)
9f6c9258
DK		 424{
425 struct bnx2x *bp = fp->bp;
426 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
427 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
428 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
429 dma_addr_t mapping;
619c5cb6
VZ		 430 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
431 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
9f6c9258 432
619c5cb6
VZ		 433 /* print error if current state != stop */
434 if (tpa_info->tpa_state != BNX2X_TPA_STOP)
9f6c9258
DK		 435 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
436
e52fcb24 437 /* Try to map an empty data buffer from the aggregation info */
619c5cb6 438 mapping = dma_map_single(&bp->pdev->dev,
e52fcb24 439 first_buf->data + NET_SKB_PAD,
619c5cb6
VZ		 440 fp->rx_buf_size, DMA_FROM_DEVICE);
441 /*
442 * ...if it fails - move the skb from the consumer to the producer
443 * and set the current aggregation state as ERROR to drop it
444 * when TPA_STOP arrives.
445 */
446
447 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
448 /* Move the BD from the consumer to the producer */
e52fcb24 449 bnx2x_reuse_rx_data(fp, cons, prod);
619c5cb6
VZ		 450 tpa_info->tpa_state = BNX2X_TPA_ERROR;
451 return;
452 }
9f6c9258 453
e52fcb24
ED		 454 /* move empty data from pool to prod */
455 prod_rx_buf->data = first_buf->data;
619c5cb6 456 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
e52fcb24 457 /* point prod_bd to new data */
9f6c9258
DK		 458 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
459 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
460
619c5cb6
VZ		 461 /* move partial skb from cons to pool (don't unmap yet) */
462 *first_buf = *cons_rx_buf;
463
464 /* mark bin state as START */
465 tpa_info->parsing_flags =
466 le16_to_cpu(cqe->pars_flags.flags);
467 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
468 tpa_info->tpa_state = BNX2X_TPA_START;
469 tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
470 tpa_info->placement_offset = cqe->placement_offset;
5495ab75 471 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
621b4d66
DK		 472 if (fp->mode == TPA_MODE_GRO) {
473 u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
924d75ab 474 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
621b4d66
DK		 475 tpa_info->gro_size = gro_size;
476 }
619c5cb6 477
9f6c9258
DK		 478#ifdef BNX2X_STOP_ON_ERROR
479 fp->tpa_queue_used |= (1 << queue);
480#ifdef _ASM_GENERIC_INT_L64_H
481 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
482#else
483 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
484#endif
485 fp->tpa_queue_used);
486#endif
487}
488
e4e3c02a
VZ		 489/* Timestamp option length allowed for TPA aggregation:
490 *
491 * nop nop kind length echo val
492 */
493#define TPA_TSTAMP_OPT_LEN 12
494/**
cbf1de72 495 * bnx2x_set_gro_params - compute GRO values
e4e3c02a 496 *
cbf1de72 497 * @skb: packet skb
e8920674
DK		 498 * @parsing_flags: parsing flags from the START CQE
499 * @len_on_bd: total length of the first packet for the
500 * aggregation.
cbf1de72 501 * @pkt_len: length of all segments
e8920674
DK		 502 *
503 * Approximate value of the MSS for this aggregation calculated using
504 * the first packet of it.
2de67439 505 * Compute number of aggregated segments, and gso_type.
e4e3c02a 506 */
cbf1de72 507static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
ab5777d7
YM		 508 u16 len_on_bd, unsigned int pkt_len,
509 u16 num_of_coalesced_segs)
e4e3c02a 510{
cbf1de72 511 /* TPA aggregation won't have either IP options or TCP options
619c5cb6 512 * other than timestamp or IPv6 extension headers.
e4e3c02a 513 */
619c5cb6
VZ		 514 u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
515
516 if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
cbf1de72 517 PRS_FLAG_OVERETH_IPV6) {
619c5cb6 518 hdrs_len += sizeof(struct ipv6hdr);
cbf1de72
YM		 519 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
520 } else {
619c5cb6 521 hdrs_len += sizeof(struct iphdr);
cbf1de72
YM		 522 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
523 }
e4e3c02a
VZ		 524
525 /* Check if there was a TCP timestamp, if there is it's will
526 * always be 12 bytes length: nop nop kind length echo val.
527 *
528 * Otherwise FW would close the aggregation.
529 */
530 if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
531 hdrs_len += TPA_TSTAMP_OPT_LEN;
532
cbf1de72
YM		 533 skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
534
535 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
536 * to skb_shinfo(skb)->gso_segs
537 */
ab5777d7 538 NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
e4e3c02a
VZ		 539}
540
996dedba
MS		 541static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
542 u16 index, gfp_t gfp_mask)
1191cb83 543{
996dedba 544 struct page *page = alloc_pages(gfp_mask, PAGES_PER_SGE_SHIFT);
1191cb83
ED		 545 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
546 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
547 dma_addr_t mapping;
548
549 if (unlikely(page == NULL)) {
550 BNX2X_ERR("Can't alloc sge\n");
551 return -ENOMEM;
552 }
553
554 mapping = dma_map_page(&bp->pdev->dev, page, 0,
924d75ab 555 SGE_PAGES, DMA_FROM_DEVICE);
1191cb83
ED		 556 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
557 __free_pages(page, PAGES_PER_SGE_SHIFT);
558 BNX2X_ERR("Can't map sge\n");
559 return -ENOMEM;
560 }
561
562 sw_buf->page = page;
563 dma_unmap_addr_set(sw_buf, mapping, mapping);
564
565 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
566 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
567
568 return 0;
569}
570
9f6c9258 571static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
621b4d66
DK		 572 struct bnx2x_agg_info *tpa_info,
573 u16 pages,
574 struct sk_buff *skb,
619c5cb6
VZ		 575 struct eth_end_agg_rx_cqe *cqe,
576 u16 cqe_idx)
9f6c9258
DK		 577{
578 struct sw_rx_page *rx_pg, old_rx_pg;
621b4d66
DK		 579 u32 i, frag_len, frag_size;
580 int err, j, frag_id = 0;
619c5cb6 581 u16 len_on_bd = tpa_info->len_on_bd;
621b4d66 582 u16 full_page = 0, gro_size = 0;
9f6c9258 583
619c5cb6 584 frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
621b4d66
DK		 585
586 if (fp->mode == TPA_MODE_GRO) {
587 gro_size = tpa_info->gro_size;
588 full_page = tpa_info->full_page;
589 }
9f6c9258
DK		 590
591 /* This is needed in order to enable forwarding support */
cbf1de72
YM		 592 if (frag_size)
593 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
ab5777d7
YM		 594 le16_to_cpu(cqe->pkt_len),
595 le16_to_cpu(cqe->num_of_coalesced_segs));
621b4d66 596
9f6c9258 597#ifdef BNX2X_STOP_ON_ERROR
924d75ab 598 if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
9f6c9258
DK		 599 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
600 pages, cqe_idx);
619c5cb6 601 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
9f6c9258
DK		 602 bnx2x_panic();
603 return -EINVAL;
604 }
605#endif
606
607 /* Run through the SGL and compose the fragmented skb */
608 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
619c5cb6 609 u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
9f6c9258
DK		 610
611 /* FW gives the indices of the SGE as if the ring is an array
612 (meaning that "next" element will consume 2 indices) */
621b4d66
DK		 613 if (fp->mode == TPA_MODE_GRO)
614 frag_len = min_t(u32, frag_size, (u32)full_page);
615 else /* LRO */
924d75ab 616 frag_len = min_t(u32, frag_size, (u32)SGE_PAGES);
621b4d66 617
9f6c9258
DK		 618 rx_pg = &fp->rx_page_ring[sge_idx];
619 old_rx_pg = *rx_pg;
620
621 /* If we fail to allocate a substitute page, we simply stop
622 where we are and drop the whole packet */
996dedba 623 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, GFP_ATOMIC);
9f6c9258 624 if (unlikely(err)) {
15192a8c 625 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
9f6c9258
DK		 626 return err;
627 }
628
16a5fd92 629 /* Unmap the page as we're going to pass it to the stack */
9f6c9258
DK		 630 dma_unmap_page(&bp->pdev->dev,
631 dma_unmap_addr(&old_rx_pg, mapping),
924d75ab 632 SGE_PAGES, DMA_FROM_DEVICE);
9f6c9258 633 /* Add one frag and update the appropriate fields in the skb */
621b4d66
DK		 634 if (fp->mode == TPA_MODE_LRO)
635 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
636 else { /* GRO */
637 int rem;
638 int offset = 0;
639 for (rem = frag_len; rem > 0; rem -= gro_size) {
640 int len = rem > gro_size ? gro_size : rem;
641 skb_fill_page_desc(skb, frag_id++,
642 old_rx_pg.page, offset, len);
643 if (offset)
644 get_page(old_rx_pg.page);
645 offset += len;
646 }
647 }
9f6c9258
DK		 648
649 skb->data_len += frag_len;
924d75ab 650 skb->truesize += SGE_PAGES;
9f6c9258
DK		 651 skb->len += frag_len;
652
653 frag_size -= frag_len;
654 }
655
656 return 0;
657}
658
d46d132c
ED		 659static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
660{
661 if (fp->rx_frag_size)
662 put_page(virt_to_head_page(data));
663 else
664 kfree(data);
665}
666
996dedba 667static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
d46d132c 668{
996dedba
MS		 669 if (fp->rx_frag_size) {
670 /* GFP_KERNEL allocations are used only during initialization */
671 if (unlikely(gfp_mask & __GFP_WAIT))
672 return (void *)__get_free_page(gfp_mask);
673
d46d132c 674 return netdev_alloc_frag(fp->rx_frag_size);
996dedba 675 }
d46d132c 676
996dedba 677 return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
d46d132c
ED		 678}
679
9969085e
YM		 680#ifdef CONFIG_INET
681static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
682{
683 const struct iphdr *iph = ip_hdr(skb);
684 struct tcphdr *th;
685
686 skb_set_transport_header(skb, sizeof(struct iphdr));
687 th = tcp_hdr(skb);
688
689 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
690 iph->saddr, iph->daddr, 0);
691}
692
693static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
694{
695 struct ipv6hdr *iph = ipv6_hdr(skb);
696 struct tcphdr *th;
697
698 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
699 th = tcp_hdr(skb);
700
701 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
702 &iph->saddr, &iph->daddr, 0);
703}
2c2d06d5
YM		 704
705static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
706 void (*gro_func)(struct bnx2x*, struct sk_buff*))
707{
708 skb_set_network_header(skb, 0);
709 gro_func(bp, skb);
710 tcp_gro_complete(skb);
711}
9969085e
YM		 712#endif
713
714static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
715 struct sk_buff *skb)
716{
717#ifdef CONFIG_INET
cbf1de72 718 if (skb_shinfo(skb)->gso_size) {
9969085e
YM		 719 switch (be16_to_cpu(skb->protocol)) {
720 case ETH_P_IP:
2c2d06d5 721 bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
9969085e
YM		 722 break;
723 case ETH_P_IPV6:
2c2d06d5 724 bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
9969085e
YM		 725 break;
726 default:
2c2d06d5 727 BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
9969085e
YM		 728 be16_to_cpu(skb->protocol));
729 }
9969085e
YM		 730 }
731#endif
60e66fee 732 skb_record_rx_queue(skb, fp->rx_queue);
9969085e
YM		 733 napi_gro_receive(&fp->napi, skb);
734}
735
1191cb83
ED		 736static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
737 struct bnx2x_agg_info *tpa_info,
738 u16 pages,
739 struct eth_end_agg_rx_cqe *cqe,
740 u16 cqe_idx)
9f6c9258 741{
619c5cb6 742 struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
621b4d66 743 u8 pad = tpa_info->placement_offset;
619c5cb6 744 u16 len = tpa_info->len_on_bd;
e52fcb24 745 struct sk_buff *skb = NULL;
621b4d66 746 u8 *new_data, *data = rx_buf->data;
619c5cb6
VZ		 747 u8 old_tpa_state = tpa_info->tpa_state;
748
749 tpa_info->tpa_state = BNX2X_TPA_STOP;
750
751 /* If we there was an error during the handling of the TPA_START -
752 * drop this aggregation.
753 */
754 if (old_tpa_state == BNX2X_TPA_ERROR)
755 goto drop;
756
e52fcb24 757 /* Try to allocate the new data */
996dedba 758 new_data = bnx2x_frag_alloc(fp, GFP_ATOMIC);
9f6c9258
DK		 759 /* Unmap skb in the pool anyway, as we are going to change
760 pool entry status to BNX2X_TPA_STOP even if new skb allocation
761 fails. */
762 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
a8c94b91 763 fp->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 764 if (likely(new_data))
d46d132c 765 skb = build_skb(data, fp->rx_frag_size);
9f6c9258 766
e52fcb24 767 if (likely(skb)) {
9f6c9258 768#ifdef BNX2X_STOP_ON_ERROR
a8c94b91 769 if (pad + len > fp->rx_buf_size) {
51c1a580 770 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
a8c94b91 771 pad, len, fp->rx_buf_size);
9f6c9258
DK		 772 bnx2x_panic();
773 return;
774 }
775#endif
776
e52fcb24 777 skb_reserve(skb, pad + NET_SKB_PAD);
9f6c9258 778 skb_put(skb, len);
5495ab75 779 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
9f6c9258
DK		 780
781 skb->protocol = eth_type_trans(skb, bp->dev);
782 skb->ip_summed = CHECKSUM_UNNECESSARY;
783
621b4d66
DK		 784 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
785 skb, cqe, cqe_idx)) {
619c5cb6 786 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
86a9bad3 787 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tpa_info->vlan_tag);
9969085e 788 bnx2x_gro_receive(bp, fp, skb);
9f6c9258 789 } else {
51c1a580
MS		 790 DP(NETIF_MSG_RX_STATUS,
791 "Failed to allocate new pages - dropping packet!\n");
40955532 792 dev_kfree_skb_any(skb);
9f6c9258
DK		 793 }
794
e52fcb24
ED		 795 /* put new data in bin */
796 rx_buf->data = new_data;
9f6c9258 797
619c5cb6 798 return;
9f6c9258 799 }
d46d132c 800 bnx2x_frag_free(fp, new_data);
619c5cb6
VZ		 801drop:
802 /* drop the packet and keep the buffer in the bin */
803 DP(NETIF_MSG_RX_STATUS,
804 "Failed to allocate or map a new skb - dropping packet!\n");
15192a8c 805 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
9f6c9258
DK		 806}
807
996dedba
MS		 808static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
809 u16 index, gfp_t gfp_mask)
1191cb83
ED		 810{
811 u8 *data;
812 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
813 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
814 dma_addr_t mapping;
815
996dedba 816 data = bnx2x_frag_alloc(fp, gfp_mask);
1191cb83
ED		 817 if (unlikely(data == NULL))
818 return -ENOMEM;
819
820 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
821 fp->rx_buf_size,
822 DMA_FROM_DEVICE);
823 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
d46d132c 824 bnx2x_frag_free(fp, data);
1191cb83
ED		 825 BNX2X_ERR("Can't map rx data\n");
826 return -ENOMEM;
827 }
828
829 rx_buf->data = data;
830 dma_unmap_addr_set(rx_buf, mapping, mapping);
831
832 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
833 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
834
835 return 0;
836}
837
15192a8c
BW		 838static
839void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
840 struct bnx2x_fastpath *fp,
841 struct bnx2x_eth_q_stats *qstats)
d6cb3e41 842{
e488921f
MS		 843 /* Do nothing if no L4 csum validation was done.
844 * We do not check whether IP csum was validated. For IPv4 we assume
845 * that if the card got as far as validating the L4 csum, it also
846 * validated the IP csum. IPv6 has no IP csum.
847 */
d6cb3e41 848 if (cqe->fast_path_cqe.status_flags &
e488921f 849 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
d6cb3e41
ED		 850 return;
851
e488921f 852 /* If L4 validation was done, check if an error was found. */
d6cb3e41
ED		 853
854 if (cqe->fast_path_cqe.type_error_flags &
855 (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
856 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
15192a8c 857 qstats->hw_csum_err++;
d6cb3e41
ED		 858 else
859 skb->ip_summed = CHECKSUM_UNNECESSARY;
860}
9f6c9258 861
a8f47eb7 862static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
9f6c9258
DK		 863{
864 struct bnx2x *bp = fp->bp;
865 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
75b29459 866 u16 sw_comp_cons, sw_comp_prod;
9f6c9258 867 int rx_pkt = 0;
75b29459
DK		 868 union eth_rx_cqe *cqe;
869 struct eth_fast_path_rx_cqe *cqe_fp;
9f6c9258
DK		 870
871#ifdef BNX2X_STOP_ON_ERROR
872 if (unlikely(bp->panic))
873 return 0;
874#endif
b3529744
EB		 875 if (budget <= 0)
876 return rx_pkt;
9f6c9258 877
9f6c9258
DK		 878 bd_cons = fp->rx_bd_cons;
879 bd_prod = fp->rx_bd_prod;
880 bd_prod_fw = bd_prod;
881 sw_comp_cons = fp->rx_comp_cons;
882 sw_comp_prod = fp->rx_comp_prod;
883
75b29459
DK		 884 comp_ring_cons = RCQ_BD(sw_comp_cons);
885 cqe = &fp->rx_comp_ring[comp_ring_cons];
886 cqe_fp = &cqe->fast_path_cqe;
9f6c9258
DK		 887
888 DP(NETIF_MSG_RX_STATUS,
75b29459 889 "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
9f6c9258 890
75b29459 891 while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
9f6c9258
DK		 892 struct sw_rx_bd *rx_buf = NULL;
893 struct sk_buff *skb;
9f6c9258 894 u8 cqe_fp_flags;
619c5cb6 895 enum eth_rx_cqe_type cqe_fp_type;
621b4d66 896 u16 len, pad, queue;
e52fcb24 897 u8 *data;
bd5cef03 898 u32 rxhash;
5495ab75 899 enum pkt_hash_types rxhash_type;
9f6c9258 900
619c5cb6
VZ		 901#ifdef BNX2X_STOP_ON_ERROR
902 if (unlikely(bp->panic))
903 return 0;
904#endif
905
9f6c9258
DK		 906 bd_prod = RX_BD(bd_prod);
907 bd_cons = RX_BD(bd_cons);
908
619c5cb6
VZ		 909 cqe_fp_flags = cqe_fp->type_error_flags;
910 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
9f6c9258 911
51c1a580
MS		 912 DP(NETIF_MSG_RX_STATUS,
913 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
914 CQE_TYPE(cqe_fp_flags),
619c5cb6
VZ		 915 cqe_fp_flags, cqe_fp->status_flags,
916 le32_to_cpu(cqe_fp->rss_hash_result),
621b4d66
DK		 917 le16_to_cpu(cqe_fp->vlan_tag),
918 le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
9f6c9258
DK		 919
920 /* is this a slowpath msg? */
619c5cb6 921 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
9f6c9258
DK		 922 bnx2x_sp_event(fp, cqe);
923 goto next_cqe;
e52fcb24 924 }
621b4d66 925
e52fcb24
ED		 926 rx_buf = &fp->rx_buf_ring[bd_cons];
927 data = rx_buf->data;
9f6c9258 928
e52fcb24 929 if (!CQE_TYPE_FAST(cqe_fp_type)) {
621b4d66
DK		 930 struct bnx2x_agg_info *tpa_info;
931 u16 frag_size, pages;
619c5cb6 932#ifdef BNX2X_STOP_ON_ERROR
e52fcb24
ED		 933 /* sanity check */
934 if (fp->disable_tpa &&
935 (CQE_TYPE_START(cqe_fp_type) ||
936 CQE_TYPE_STOP(cqe_fp_type)))
51c1a580 937 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
e52fcb24 938 CQE_TYPE(cqe_fp_type));
619c5cb6 939#endif
9f6c9258 940
e52fcb24
ED		 941 if (CQE_TYPE_START(cqe_fp_type)) {
942 u16 queue = cqe_fp->queue_index;
943 DP(NETIF_MSG_RX_STATUS,
944 "calling tpa_start on queue %d\n",
945 queue);
9f6c9258 946
e52fcb24
ED		 947 bnx2x_tpa_start(fp, queue,
948 bd_cons, bd_prod,
949 cqe_fp);
621b4d66 950
e52fcb24 951 goto next_rx;
621b4d66
DK		 952 }
953 queue = cqe->end_agg_cqe.queue_index;
954 tpa_info = &fp->tpa_info[queue];
955 DP(NETIF_MSG_RX_STATUS,
956 "calling tpa_stop on queue %d\n",
957 queue);
958
959 frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
960 tpa_info->len_on_bd;
961
962 if (fp->mode == TPA_MODE_GRO)
963 pages = (frag_size + tpa_info->full_page - 1) /
964 tpa_info->full_page;
965 else
966 pages = SGE_PAGE_ALIGN(frag_size) >>
967 SGE_PAGE_SHIFT;
968
969 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
970 &cqe->end_agg_cqe, comp_ring_cons);
9f6c9258 971#ifdef BNX2X_STOP_ON_ERROR
621b4d66
DK		 972 if (bp->panic)
973 return 0;
9f6c9258
DK		 974#endif
975
621b4d66
DK		 976 bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
977 goto next_cqe;
e52fcb24
ED		 978 }
979 /* non TPA */
621b4d66 980 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
e52fcb24
ED		 981 pad = cqe_fp->placement_offset;
982 dma_sync_single_for_cpu(&bp->pdev->dev,
9f6c9258 983 dma_unmap_addr(rx_buf, mapping),
e52fcb24
ED		 984 pad + RX_COPY_THRESH,
985 DMA_FROM_DEVICE);
986 pad += NET_SKB_PAD;
987 prefetch(data + pad); /* speedup eth_type_trans() */
988 /* is this an error packet? */
989 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
51c1a580 990 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
e52fcb24
ED		 991 "ERROR flags %x rx packet %u\n",
992 cqe_fp_flags, sw_comp_cons);
15192a8c 993 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
e52fcb24
ED		 994 goto reuse_rx;
995 }
9f6c9258 996
e52fcb24
ED		 997 /* Since we don't have a jumbo ring
998 * copy small packets if mtu > 1500
999 */
1000 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1001 (len <= RX_COPY_THRESH)) {
1002 skb = netdev_alloc_skb_ip_align(bp->dev, len);
1003 if (skb == NULL) {
51c1a580 1004 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
e52fcb24 1005 "ERROR packet dropped because of alloc failure\n");
15192a8c 1006 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
9f6c9258
DK		 1007 goto reuse_rx;
1008 }
e52fcb24
ED		 1009 memcpy(skb->data, data + pad, len);
1010 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1011 } else {
996dedba
MS		 1012 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1013 GFP_ATOMIC) == 0)) {
9f6c9258 1014 dma_unmap_single(&bp->pdev->dev,
e52fcb24 1015 dma_unmap_addr(rx_buf, mapping),
a8c94b91 1016 fp->rx_buf_size,
9f6c9258 1017 DMA_FROM_DEVICE);
d46d132c 1018 skb = build_skb(data, fp->rx_frag_size);
e52fcb24 1019 if (unlikely(!skb)) {
d46d132c 1020 bnx2x_frag_free(fp, data);
15192a8c
BW		 1021 bnx2x_fp_qstats(bp, fp)->
1022 rx_skb_alloc_failed++;
e52fcb24
ED		 1023 goto next_rx;
1024 }
9f6c9258 1025 skb_reserve(skb, pad);
9f6c9258 1026 } else {
51c1a580
MS		 1027 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1028 "ERROR packet dropped because of alloc failure\n");
15192a8c 1029 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
9f6c9258 1030reuse_rx:
e52fcb24 1031 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
9f6c9258
DK		 1032 goto next_rx;
1033 }
036d2df9 1034 }
9f6c9258 1035
036d2df9
DK		 1036 skb_put(skb, len);
1037 skb->protocol = eth_type_trans(skb, bp->dev);
9f6c9258 1038
036d2df9 1039 /* Set Toeplitz hash for a none-LRO skb */
5495ab75
TH		 1040 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1041 skb_set_hash(skb, rxhash, rxhash_type);
9f6c9258 1042
036d2df9 1043 skb_checksum_none_assert(skb);
f85582f8 1044
d6cb3e41 1045 if (bp->dev->features & NETIF_F_RXCSUM)
15192a8c
BW		 1046 bnx2x_csum_validate(skb, cqe, fp,
1047 bnx2x_fp_qstats(bp, fp));
9f6c9258 1048
f233cafe 1049 skb_record_rx_queue(skb, fp->rx_queue);
9f6c9258 1050
619c5cb6
VZ		 1051 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1052 PARSING_FLAGS_VLAN)
86a9bad3 1053 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
619c5cb6 1054 le16_to_cpu(cqe_fp->vlan_tag));
9f6c9258 1055
8b80cda5 1056 skb_mark_napi_id(skb, &fp->napi);
8f20aa57
DK		 1057
1058 if (bnx2x_fp_ll_polling(fp))
1059 netif_receive_skb(skb);
1060 else
1061 napi_gro_receive(&fp->napi, skb);
9f6c9258 1062next_rx:
e52fcb24 1063 rx_buf->data = NULL;
9f6c9258
DK		 1064
1065 bd_cons = NEXT_RX_IDX(bd_cons);
1066 bd_prod = NEXT_RX_IDX(bd_prod);
1067 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1068 rx_pkt++;
1069next_cqe:
1070 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1071 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1072
75b29459
DK		 1073 /* mark CQE as free */
1074 BNX2X_SEED_CQE(cqe_fp);
1075
9f6c9258
DK		 1076 if (rx_pkt == budget)
1077 break;
75b29459
DK		 1078
1079 comp_ring_cons = RCQ_BD(sw_comp_cons);
1080 cqe = &fp->rx_comp_ring[comp_ring_cons];
1081 cqe_fp = &cqe->fast_path_cqe;
9f6c9258
DK		 1082 } /* while */
1083
1084 fp->rx_bd_cons = bd_cons;
1085 fp->rx_bd_prod = bd_prod_fw;
1086 fp->rx_comp_cons = sw_comp_cons;
1087 fp->rx_comp_prod = sw_comp_prod;
1088
1089 /* Update producers */
1090 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1091 fp->rx_sge_prod);
1092
1093 fp->rx_pkt += rx_pkt;
1094 fp->rx_calls++;
1095
1096 return rx_pkt;
1097}
1098
1099static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1100{
1101 struct bnx2x_fastpath *fp = fp_cookie;
1102 struct bnx2x *bp = fp->bp;
6383c0b3 1103 u8 cos;
9f6c9258 1104
51c1a580
MS		 1105 DP(NETIF_MSG_INTR,
1106 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
523224a3 1107 fp->index, fp->fw_sb_id, fp->igu_sb_id);
ecf01c22 1108
523224a3 1109 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9f6c9258
DK		 1110
1111#ifdef BNX2X_STOP_ON_ERROR
1112 if (unlikely(bp->panic))
1113 return IRQ_HANDLED;
1114#endif
1115
1116 /* Handle Rx and Tx according to MSI-X vector */
6383c0b3 1117 for_each_cos_in_tx_queue(fp, cos)
65565884 1118 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
6383c0b3 1119
523224a3 1120 prefetch(&fp->sb_running_index[SM_RX_ID]);
9f6c9258
DK		 1121 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1122
1123 return IRQ_HANDLED;
1124}
1125
9f6c9258
DK		 1126/* HW Lock for shared dual port PHYs */
1127void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1128{
1129 mutex_lock(&bp->port.phy_mutex);
1130
8203c4b6 1131 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
9f6c9258
DK		 1132}
1133
1134void bnx2x_release_phy_lock(struct bnx2x *bp)
1135{
8203c4b6 1136 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
9f6c9258
DK		 1137
1138 mutex_unlock(&bp->port.phy_mutex);
1139}
1140
0793f83f
DK		 1141/* calculates MF speed according to current linespeed and MF configuration */
1142u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1143{
1144 u16 line_speed = bp->link_vars.line_speed;
1145 if (IS_MF(bp)) {
faa6fcbb
DK		 1146 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1147 bp->mf_config[BP_VN(bp)]);
1148
1149 /* Calculate the current MAX line speed limit for the MF
1150 * devices
0793f83f 1151 */
faa6fcbb
DK		 1152 if (IS_MF_SI(bp))
1153 line_speed = (line_speed * maxCfg) / 100;
1154 else { /* SD mode */
0793f83f
DK		 1155 u16 vn_max_rate = maxCfg * 100;
1156
1157 if (vn_max_rate < line_speed)
1158 line_speed = vn_max_rate;
faa6fcbb 1159 }
0793f83f
DK		 1160 }
1161
1162 return line_speed;
1163}
1164
2ae17f66
VZ		 1165/**
1166 * bnx2x_fill_report_data - fill link report data to report
1167 *
1168 * @bp: driver handle
1169 * @data: link state to update
1170 *
1171 * It uses a none-atomic bit operations because is called under the mutex.
1172 */
1191cb83
ED		 1173static void bnx2x_fill_report_data(struct bnx2x *bp,
1174 struct bnx2x_link_report_data *data)
2ae17f66
VZ		 1175{
1176 u16 line_speed = bnx2x_get_mf_speed(bp);
1177
1178 memset(data, 0, sizeof(*data));
1179
16a5fd92 1180 /* Fill the report data: effective line speed */
2ae17f66
VZ		 1181 data->line_speed = line_speed;
1182
1183 /* Link is down */
1184 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1185 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1186 &data->link_report_flags);
1187
1188 /* Full DUPLEX */
1189 if (bp->link_vars.duplex == DUPLEX_FULL)
1190 __set_bit(BNX2X_LINK_REPORT_FD, &data->link_report_flags);
1191
1192 /* Rx Flow Control is ON */
1193 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1194 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
1195
1196 /* Tx Flow Control is ON */
1197 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1198 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
1199}
1200
1201/**
1202 * bnx2x_link_report - report link status to OS.
1203 *
1204 * @bp: driver handle
1205 *
1206 * Calls the __bnx2x_link_report() under the same locking scheme
1207 * as a link/PHY state managing code to ensure a consistent link
1208 * reporting.
1209 */
1210
9f6c9258
DK		 1211void bnx2x_link_report(struct bnx2x *bp)
1212{
2ae17f66
VZ		 1213 bnx2x_acquire_phy_lock(bp);
1214 __bnx2x_link_report(bp);
1215 bnx2x_release_phy_lock(bp);
1216}
9f6c9258 1217
2ae17f66
VZ		 1218/**
1219 * __bnx2x_link_report - report link status to OS.
1220 *
1221 * @bp: driver handle
1222 *
16a5fd92 1223 * None atomic implementation.
2ae17f66
VZ		 1224 * Should be called under the phy_lock.
1225 */
1226void __bnx2x_link_report(struct bnx2x *bp)
1227{
1228 struct bnx2x_link_report_data cur_data;
9f6c9258 1229
2ae17f66 1230 /* reread mf_cfg */
ad5afc89 1231 if (IS_PF(bp) && !CHIP_IS_E1(bp))
2ae17f66
VZ		 1232 bnx2x_read_mf_cfg(bp);
1233
1234 /* Read the current link report info */
1235 bnx2x_fill_report_data(bp, &cur_data);
1236
1237 /* Don't report link down or exactly the same link status twice */
1238 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1239 (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1240 &bp->last_reported_link.link_report_flags) &&
1241 test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1242 &cur_data.link_report_flags)))
1243 return;
1244
1245 bp->link_cnt++;
9f6c9258 1246
2ae17f66
VZ		 1247 /* We are going to report a new link parameters now -
1248 * remember the current data for the next time.
1249 */
1250 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
9f6c9258 1251
2ae17f66
VZ		 1252 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1253 &cur_data.link_report_flags)) {
1254 netif_carrier_off(bp->dev);
1255 netdev_err(bp->dev, "NIC Link is Down\n");
1256 return;
1257 } else {
94f05b0f
JP		 1258 const char *duplex;
1259 const char *flow;
1260
2ae17f66 1261 netif_carrier_on(bp->dev);
9f6c9258 1262
2ae17f66
VZ		 1263 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1264 &cur_data.link_report_flags))
94f05b0f 1265 duplex = "full";
9f6c9258 1266 else
94f05b0f 1267 duplex = "half";
9f6c9258 1268
2ae17f66
VZ		 1269 /* Handle the FC at the end so that only these flags would be
1270 * possibly set. This way we may easily check if there is no FC
1271 * enabled.
1272 */
1273 if (cur_data.link_report_flags) {
1274 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1275 &cur_data.link_report_flags)) {
2ae17f66
VZ		 1276 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1277 &cur_data.link_report_flags))
94f05b0f
JP		 1278 flow = "ON - receive & transmit";
1279 else
1280 flow = "ON - receive";
9f6c9258 1281 } else {
94f05b0f 1282 flow = "ON - transmit";
9f6c9258 1283 }
94f05b0f
JP		 1284 } else {
1285 flow = "none";
9f6c9258 1286 }
94f05b0f
JP		 1287 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1288 cur_data.line_speed, duplex, flow);
9f6c9258
DK		 1289 }
1290}
1291
1191cb83
ED		 1292static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1293{
1294 int i;
1295
1296 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1297 struct eth_rx_sge *sge;
1298
1299 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1300 sge->addr_hi =
1301 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1302 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1303
1304 sge->addr_lo =
1305 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1306 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1307 }
1308}
1309
1310static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1311 struct bnx2x_fastpath *fp, int last)
1312{
1313 int i;
1314
1315 for (i = 0; i < last; i++) {
1316 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1317 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1318 u8 *data = first_buf->data;
1319
1320 if (data == NULL) {
1321 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1322 continue;
1323 }
1324 if (tpa_info->tpa_state == BNX2X_TPA_START)
1325 dma_unmap_single(&bp->pdev->dev,
1326 dma_unmap_addr(first_buf, mapping),
1327 fp->rx_buf_size, DMA_FROM_DEVICE);
d46d132c 1328 bnx2x_frag_free(fp, data);
1191cb83
ED		 1329 first_buf->data = NULL;
1330 }
1331}
1332
55c11941
MS		 1333void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1334{
1335 int j;
1336
1337 for_each_rx_queue_cnic(bp, j) {
1338 struct bnx2x_fastpath *fp = &bp->fp[j];
1339
1340 fp->rx_bd_cons = 0;
1341
1342 /* Activate BD ring */
1343 /* Warning!
1344 * this will generate an interrupt (to the TSTORM)
1345 * must only be done after chip is initialized
1346 */
1347 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1348 fp->rx_sge_prod);
1349 }
1350}
1351
9f6c9258
DK		 1352void bnx2x_init_rx_rings(struct bnx2x *bp)
1353{
1354 int func = BP_FUNC(bp);
523224a3 1355 u16 ring_prod;
9f6c9258 1356 int i, j;
25141580 1357
b3b83c3f 1358 /* Allocate TPA resources */
55c11941 1359 for_each_eth_queue(bp, j) {
523224a3 1360 struct bnx2x_fastpath *fp = &bp->fp[j];
9f6c9258 1361
a8c94b91
VZ		 1362 DP(NETIF_MSG_IFUP,
1363 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1364
523224a3 1365 if (!fp->disable_tpa) {
16a5fd92 1366 /* Fill the per-aggregation pool */
dfacf138 1367 for (i = 0; i < MAX_AGG_QS(bp); i++) {
619c5cb6
VZ		 1368 struct bnx2x_agg_info *tpa_info =
1369 &fp->tpa_info[i];
1370 struct sw_rx_bd *first_buf =
1371 &tpa_info->first_buf;
1372
996dedba
MS		 1373 first_buf->data =
1374 bnx2x_frag_alloc(fp, GFP_KERNEL);
e52fcb24 1375 if (!first_buf->data) {
51c1a580
MS		 1376 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1377 j);
9f6c9258
DK		 1378 bnx2x_free_tpa_pool(bp, fp, i);
1379 fp->disable_tpa = 1;
1380 break;
1381 }
619c5cb6
VZ		 1382 dma_unmap_addr_set(first_buf, mapping, 0);
1383 tpa_info->tpa_state = BNX2X_TPA_STOP;
9f6c9258 1384 }
523224a3
DK		 1385
1386 /* "next page" elements initialization */
1387 bnx2x_set_next_page_sgl(fp);
1388
1389 /* set SGEs bit mask */
1390 bnx2x_init_sge_ring_bit_mask(fp);
1391
1392 /* Allocate SGEs and initialize the ring elements */
1393 for (i = 0, ring_prod = 0;
1394 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1395
996dedba
MS		 1396 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1397 GFP_KERNEL) < 0) {
51c1a580
MS		 1398 BNX2X_ERR("was only able to allocate %d rx sges\n",
1399 i);
1400 BNX2X_ERR("disabling TPA for queue[%d]\n",
1401 j);
523224a3 1402 /* Cleanup already allocated elements */
619c5cb6
VZ		 1403 bnx2x_free_rx_sge_range(bp, fp,
1404 ring_prod);
1405 bnx2x_free_tpa_pool(bp, fp,
dfacf138 1406 MAX_AGG_QS(bp));
523224a3
DK		 1407 fp->disable_tpa = 1;
1408 ring_prod = 0;
1409 break;
1410 }
1411 ring_prod = NEXT_SGE_IDX(ring_prod);
1412 }
1413
1414 fp->rx_sge_prod = ring_prod;
9f6c9258
DK		 1415 }
1416 }
1417
55c11941 1418 for_each_eth_queue(bp, j) {
9f6c9258
DK		 1419 struct bnx2x_fastpath *fp = &bp->fp[j];
1420
1421 fp->rx_bd_cons = 0;
9f6c9258 1422
b3b83c3f
DK		 1423 /* Activate BD ring */
1424 /* Warning!
1425 * this will generate an interrupt (to the TSTORM)
1426 * must only be done after chip is initialized
1427 */
1428 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1429 fp->rx_sge_prod);
9f6c9258 1430
9f6c9258
DK		 1431 if (j != 0)
1432 continue;
1433
619c5cb6 1434 if (CHIP_IS_E1(bp)) {
f2e0899f
DK		 1435 REG_WR(bp, BAR_USTRORM_INTMEM +
1436 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1437 U64_LO(fp->rx_comp_mapping));
1438 REG_WR(bp, BAR_USTRORM_INTMEM +
1439 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1440 U64_HI(fp->rx_comp_mapping));
1441 }
9f6c9258
DK		 1442 }
1443}
f85582f8 1444
55c11941 1445static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
9f6c9258 1446{
6383c0b3 1447 u8 cos;
55c11941 1448 struct bnx2x *bp = fp->bp;
9f6c9258 1449
55c11941
MS		 1450 for_each_cos_in_tx_queue(fp, cos) {
1451 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1452 unsigned pkts_compl = 0, bytes_compl = 0;
9f6c9258 1453
55c11941
MS		 1454 u16 sw_prod = txdata->tx_pkt_prod;
1455 u16 sw_cons = txdata->tx_pkt_cons;
9f6c9258 1456
55c11941
MS		 1457 while (sw_cons != sw_prod) {
1458 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1459 &pkts_compl, &bytes_compl);
1460 sw_cons++;
9f6c9258 1461 }
55c11941
MS		 1462
1463 netdev_tx_reset_queue(
1464 netdev_get_tx_queue(bp->dev,
1465 txdata->txq_index));
1466 }
1467}
1468
1469static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1470{
1471 int i;
1472
1473 for_each_tx_queue_cnic(bp, i) {
1474 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1475 }
1476}
1477
1478static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1479{
1480 int i;
1481
1482 for_each_eth_queue(bp, i) {
1483 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
9f6c9258
DK		 1484 }
1485}
1486
b3b83c3f
DK		 1487static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1488{
1489 struct bnx2x *bp = fp->bp;
1490 int i;
1491
1492 /* ring wasn't allocated */
1493 if (fp->rx_buf_ring == NULL)
1494 return;
1495
1496 for (i = 0; i < NUM_RX_BD; i++) {
1497 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
e52fcb24 1498 u8 *data = rx_buf->data;
b3b83c3f 1499
e52fcb24 1500 if (data == NULL)
b3b83c3f 1501 continue;
b3b83c3f
DK		 1502 dma_unmap_single(&bp->pdev->dev,
1503 dma_unmap_addr(rx_buf, mapping),
1504 fp->rx_buf_size, DMA_FROM_DEVICE);
1505
e52fcb24 1506 rx_buf->data = NULL;
d46d132c 1507 bnx2x_frag_free(fp, data);
b3b83c3f
DK		 1508 }
1509}
1510
55c11941
MS		 1511static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1512{
1513 int j;
1514
1515 for_each_rx_queue_cnic(bp, j) {
1516 bnx2x_free_rx_bds(&bp->fp[j]);
1517 }
1518}
1519
9f6c9258
DK		 1520static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1521{
b3b83c3f 1522 int j;
9f6c9258 1523
55c11941 1524 for_each_eth_queue(bp, j) {
9f6c9258
DK		 1525 struct bnx2x_fastpath *fp = &bp->fp[j];
1526
b3b83c3f 1527 bnx2x_free_rx_bds(fp);
9f6c9258 1528
9f6c9258 1529 if (!fp->disable_tpa)
dfacf138 1530 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
9f6c9258
DK		 1531 }
1532}
1533
a8f47eb7 1534static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
55c11941
MS		 1535{
1536 bnx2x_free_tx_skbs_cnic(bp);
1537 bnx2x_free_rx_skbs_cnic(bp);
1538}
1539
9f6c9258
DK		 1540void bnx2x_free_skbs(struct bnx2x *bp)
1541{
1542 bnx2x_free_tx_skbs(bp);
1543 bnx2x_free_rx_skbs(bp);
1544}
1545
e3835b99
DK		 1546void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1547{
1548 /* load old values */
1549 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1550
1551 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1552 /* leave all but MAX value */
1553 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1554
1555 /* set new MAX value */
1556 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1557 & FUNC_MF_CFG_MAX_BW_MASK;
1558
1559 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1560 }
1561}
1562
ca92429f
DK		 1563/**
1564 * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1565 *
1566 * @bp: driver handle
1567 * @nvecs: number of vectors to be released
1568 */
1569static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
9f6c9258 1570{
ca92429f 1571 int i, offset = 0;
9f6c9258 1572
ca92429f
DK		 1573 if (nvecs == offset)
1574 return;
ad5afc89
AE		 1575
1576 /* VFs don't have a default SB */
1577 if (IS_PF(bp)) {
1578 free_irq(bp->msix_table[offset].vector, bp->dev);
1579 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1580 bp->msix_table[offset].vector);
1581 offset++;
1582 }
55c11941
MS		 1583
1584 if (CNIC_SUPPORT(bp)) {
1585 if (nvecs == offset)
1586 return;
1587 offset++;
1588 }
ca92429f 1589
ec6ba945 1590 for_each_eth_queue(bp, i) {
ca92429f
DK		 1591 if (nvecs == offset)
1592 return;
51c1a580
MS		 1593 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1594 i, bp->msix_table[offset].vector);
9f6c9258 1595
ca92429f 1596 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
9f6c9258
DK		 1597 }
1598}
1599
d6214d7a 1600void bnx2x_free_irq(struct bnx2x *bp)
9f6c9258 1601{
30a5de77 1602 if (bp->flags & USING_MSIX_FLAG &&
ad5afc89
AE		 1603 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1604 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1605
1606 /* vfs don't have a default status block */
1607 if (IS_PF(bp))
1608 nvecs++;
1609
1610 bnx2x_free_msix_irqs(bp, nvecs);
1611 } else {
30a5de77 1612 free_irq(bp->dev->irq, bp->dev);
ad5afc89 1613 }
9f6c9258
DK		 1614}
1615
0e8d2ec5 1616int bnx2x_enable_msix(struct bnx2x *bp)
9f6c9258 1617{
1ab4434c 1618 int msix_vec = 0, i, rc;
9f6c9258 1619
1ab4434c
AE		 1620 /* VFs don't have a default status block */
1621 if (IS_PF(bp)) {
1622 bp->msix_table[msix_vec].entry = msix_vec;
1623 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1624 bp->msix_table[0].entry);
1625 msix_vec++;
1626 }
9f6c9258 1627
55c11941
MS		 1628 /* Cnic requires an msix vector for itself */
1629 if (CNIC_SUPPORT(bp)) {
1630 bp->msix_table[msix_vec].entry = msix_vec;
1631 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1632 msix_vec, bp->msix_table[msix_vec].entry);
1633 msix_vec++;
1634 }
1635
6383c0b3 1636 /* We need separate vectors for ETH queues only (not FCoE) */
ec6ba945 1637 for_each_eth_queue(bp, i) {
d6214d7a 1638 bp->msix_table[msix_vec].entry = msix_vec;
51c1a580
MS		 1639 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1640 msix_vec, msix_vec, i);
d6214d7a 1641 msix_vec++;
9f6c9258
DK		 1642 }
1643
1ab4434c
AE		 1644 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1645 msix_vec);
d6214d7a 1646
a5444b17
AG		 1647 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1648 BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
9f6c9258
DK		 1649 /*
1650 * reconfigure number of tx/rx queues according to available
1651 * MSI-X vectors
1652 */
a5444b17 1653 if (rc == -ENOSPC) {
30a5de77 1654 /* Get by with single vector */
a5444b17
AG		 1655 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1656 if (rc < 0) {
30a5de77
DK		 1657 BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1658 rc);
1659 goto no_msix;
1660 }
1661
1662 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1663 bp->flags |= USING_SINGLE_MSIX_FLAG;
1664
55c11941
MS		 1665 BNX2X_DEV_INFO("set number of queues to 1\n");
1666 bp->num_ethernet_queues = 1;
1667 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
30a5de77 1668 } else if (rc < 0) {
a5444b17 1669 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
30a5de77 1670 goto no_msix;
a5444b17
AG		 1671 } else if (rc < msix_vec) {
1672 /* how less vectors we will have? */
1673 int diff = msix_vec - rc;
1674
1675 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1676
1677 /*
1678 * decrease number of queues by number of unallocated entries
1679 */
1680 bp->num_ethernet_queues -= diff;
1681 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1682
1683 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1684 bp->num_queues);
9f6c9258
DK		 1685 }
1686
1687 bp->flags |= USING_MSIX_FLAG;
1688
1689 return 0;
30a5de77
DK		 1690
1691no_msix:
1692 /* fall to INTx if not enough memory */
1693 if (rc == -ENOMEM)
1694 bp->flags |= DISABLE_MSI_FLAG;
1695
1696 return rc;
9f6c9258
DK		 1697}
1698
1699static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1700{
ca92429f 1701 int i, rc, offset = 0;
9f6c9258 1702
ad5afc89
AE		 1703 /* no default status block for vf */
1704 if (IS_PF(bp)) {
1705 rc = request_irq(bp->msix_table[offset++].vector,
1706 bnx2x_msix_sp_int, 0,
1707 bp->dev->name, bp->dev);
1708 if (rc) {
1709 BNX2X_ERR("request sp irq failed\n");
1710 return -EBUSY;
1711 }
9f6c9258
DK		 1712 }
1713
55c11941
MS		 1714 if (CNIC_SUPPORT(bp))
1715 offset++;
1716
ec6ba945 1717 for_each_eth_queue(bp, i) {
9f6c9258
DK		 1718 struct bnx2x_fastpath *fp = &bp->fp[i];
1719 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1720 bp->dev->name, i);
1721
d6214d7a 1722 rc = request_irq(bp->msix_table[offset].vector,
9f6c9258
DK		 1723 bnx2x_msix_fp_int, 0, fp->name, fp);
1724 if (rc) {
ca92429f
DK		 1725 BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i,
1726 bp->msix_table[offset].vector, rc);
1727 bnx2x_free_msix_irqs(bp, offset);
9f6c9258
DK		 1728 return -EBUSY;
1729 }
1730
d6214d7a 1731 offset++;
9f6c9258
DK		 1732 }
1733
ec6ba945 1734 i = BNX2X_NUM_ETH_QUEUES(bp);
ad5afc89
AE		 1735 if (IS_PF(bp)) {
1736 offset = 1 + CNIC_SUPPORT(bp);
1737 netdev_info(bp->dev,
1738 "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1739 bp->msix_table[0].vector,
1740 0, bp->msix_table[offset].vector,
1741 i - 1, bp->msix_table[offset + i - 1].vector);
1742 } else {
1743 offset = CNIC_SUPPORT(bp);
1744 netdev_info(bp->dev,
1745 "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n",
1746 0, bp->msix_table[offset].vector,
1747 i - 1, bp->msix_table[offset + i - 1].vector);
1748 }
9f6c9258
DK		 1749 return 0;
1750}
1751
d6214d7a 1752int bnx2x_enable_msi(struct bnx2x *bp)
9f6c9258
DK		 1753{
1754 int rc;
1755
1756 rc = pci_enable_msi(bp->pdev);
1757 if (rc) {
51c1a580 1758 BNX2X_DEV_INFO("MSI is not attainable\n");
9f6c9258
DK		 1759 return -1;
1760 }
1761 bp->flags |= USING_MSI_FLAG;
1762
1763 return 0;
1764}
1765
1766static int bnx2x_req_irq(struct bnx2x *bp)
1767{
1768 unsigned long flags;
30a5de77 1769 unsigned int irq;
9f6c9258 1770
30a5de77 1771 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
9f6c9258
DK		 1772 flags = 0;
1773 else
1774 flags = IRQF_SHARED;
1775
30a5de77
DK		 1776 if (bp->flags & USING_MSIX_FLAG)
1777 irq = bp->msix_table[0].vector;
1778 else
1779 irq = bp->pdev->irq;
1780
1781 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
9f6c9258
DK		 1782}
1783
c957d09f 1784static int bnx2x_setup_irqs(struct bnx2x *bp)
619c5cb6
VZ		 1785{
1786 int rc = 0;
30a5de77
DK		 1787 if (bp->flags & USING_MSIX_FLAG &&
1788 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
619c5cb6
VZ		 1789 rc = bnx2x_req_msix_irqs(bp);
1790 if (rc)
1791 return rc;
1792 } else {
619c5cb6
VZ		 1793 rc = bnx2x_req_irq(bp);
1794 if (rc) {
1795 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
1796 return rc;
1797 }
1798 if (bp->flags & USING_MSI_FLAG) {
1799 bp->dev->irq = bp->pdev->irq;
30a5de77
DK		 1800 netdev_info(bp->dev, "using MSI IRQ %d\n",
1801 bp->dev->irq);
1802 }
1803 if (bp->flags & USING_MSIX_FLAG) {
1804 bp->dev->irq = bp->msix_table[0].vector;
1805 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1806 bp->dev->irq);
619c5cb6
VZ		 1807 }
1808 }
1809
1810 return 0;
1811}
1812
55c11941
MS		 1813static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1814{
1815 int i;
1816
8f20aa57
DK		 1817 for_each_rx_queue_cnic(bp, i) {
1818 bnx2x_fp_init_lock(&bp->fp[i]);
55c11941 1819 napi_enable(&bnx2x_fp(bp, i, napi));
8f20aa57 1820 }
55c11941
MS		 1821}
1822
1191cb83 1823static void bnx2x_napi_enable(struct bnx2x *bp)
9f6c9258
DK		 1824{
1825 int i;
1826
8f20aa57
DK		 1827 for_each_eth_queue(bp, i) {
1828 bnx2x_fp_init_lock(&bp->fp[i]);
9f6c9258 1829 napi_enable(&bnx2x_fp(bp, i, napi));
8f20aa57 1830 }
9f6c9258
DK		 1831}
1832
55c11941
MS		 1833static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1834{
1835 int i;
1836
8f20aa57 1837 for_each_rx_queue_cnic(bp, i) {
55c11941 1838 napi_disable(&bnx2x_fp(bp, i, napi));
9a2620c8
YM		 1839 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1840 usleep_range(1000, 2000);
8f20aa57 1841 }
55c11941
MS		 1842}
1843
1191cb83 1844static void bnx2x_napi_disable(struct bnx2x *bp)
9f6c9258
DK		 1845{
1846 int i;
1847
8f20aa57 1848 for_each_eth_queue(bp, i) {
9f6c9258 1849 napi_disable(&bnx2x_fp(bp, i, napi));
9a2620c8
YM		 1850 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1851 usleep_range(1000, 2000);
8f20aa57 1852 }
9f6c9258
DK		 1853}
1854
1855void bnx2x_netif_start(struct bnx2x *bp)
1856{
4b7ed897
DK		 1857 if (netif_running(bp->dev)) {
1858 bnx2x_napi_enable(bp);
55c11941
MS		 1859 if (CNIC_LOADED(bp))
1860 bnx2x_napi_enable_cnic(bp);
4b7ed897
DK		 1861 bnx2x_int_enable(bp);
1862 if (bp->state == BNX2X_STATE_OPEN)
1863 netif_tx_wake_all_queues(bp->dev);
9f6c9258
DK		 1864 }
1865}
1866
1867void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1868{
1869 bnx2x_int_disable_sync(bp, disable_hw);
1870 bnx2x_napi_disable(bp);
55c11941
MS		 1871 if (CNIC_LOADED(bp))
1872 bnx2x_napi_disable_cnic(bp);
9f6c9258 1873}
9f6c9258 1874
f663dd9a 1875u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 1876 void *accel_priv, select_queue_fallback_t fallback)
8307fa3e 1877{
8307fa3e 1878 struct bnx2x *bp = netdev_priv(dev);
cdb9d6ae 1879
55c11941 1880 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
8307fa3e
VZ		 1881 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1882 u16 ether_type = ntohs(hdr->h_proto);
1883
1884 /* Skip VLAN tag if present */
1885 if (ether_type == ETH_P_8021Q) {
1886 struct vlan_ethhdr *vhdr =
1887 (struct vlan_ethhdr *)skb->data;
1888
1889 ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
1890 }
1891
1892 /* If ethertype is FCoE or FIP - use FCoE ring */
1893 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
6383c0b3 1894 return bnx2x_fcoe_tx(bp, txq_index);
8307fa3e 1895 }
55c11941 1896
cdb9d6ae 1897 /* select a non-FCoE queue */
99932d4f 1898 return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
8307fa3e
VZ		 1899}
1900
d6214d7a
DK		 1901void bnx2x_set_num_queues(struct bnx2x *bp)
1902{
96305234 1903 /* RSS queues */
55c11941 1904 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
ec6ba945 1905
a3348722
BW		 1906 /* override in STORAGE SD modes */
1907 if (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))
55c11941
MS		 1908 bp->num_ethernet_queues = 1;
1909
ec6ba945 1910 /* Add special queues */
55c11941
MS		 1911 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1912 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
65565884
MS		 1913
1914 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
ec6ba945
VZ		 1915}
1916
cdb9d6ae
VZ		 1917/**
1918 * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1919 *
1920 * @bp: Driver handle
1921 *
1922 * We currently support for at most 16 Tx queues for each CoS thus we will
1923 * allocate a multiple of 16 for ETH L2 rings according to the value of the
1924 * bp->max_cos.
1925 *
1926 * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1927 * index after all ETH L2 indices.
1928 *
1929 * If the actual number of Tx queues (for each CoS) is less than 16 then there
1930 * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
16a5fd92 1931 * 16..31,...) with indices that are not coupled with any real Tx queue.
cdb9d6ae
VZ		 1932 *
1933 * The proper configuration of skb->queue_mapping is handled by
1934 * bnx2x_select_queue() and __skb_tx_hash().
1935 *
1936 * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1937 * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1938 */
55c11941 1939static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
ec6ba945 1940{
6383c0b3 1941 int rc, tx, rx;
ec6ba945 1942
65565884 1943 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
55c11941 1944 rx = BNX2X_NUM_ETH_QUEUES(bp);
ec6ba945 1945
6383c0b3 1946/* account for fcoe queue */
55c11941
MS		 1947 if (include_cnic && !NO_FCOE(bp)) {
1948 rx++;
1949 tx++;
6383c0b3 1950 }
6383c0b3
AE		 1951
1952 rc = netif_set_real_num_tx_queues(bp->dev, tx);
1953 if (rc) {
1954 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1955 return rc;
1956 }
1957 rc = netif_set_real_num_rx_queues(bp->dev, rx);
1958 if (rc) {
1959 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
1960 return rc;
1961 }
1962
51c1a580 1963 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
6383c0b3
AE		 1964 tx, rx);
1965
ec6ba945
VZ		 1966 return rc;
1967}
1968
1191cb83 1969static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
a8c94b91
VZ		 1970{
1971 int i;
1972
1973 for_each_queue(bp, i) {
1974 struct bnx2x_fastpath *fp = &bp->fp[i];
e52fcb24 1975 u32 mtu;
a8c94b91
VZ		 1976
1977 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
1978 if (IS_FCOE_IDX(i))
1979 /*
1980 * Although there are no IP frames expected to arrive to
1981 * this ring we still want to add an
1982 * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
1983 * overrun attack.
1984 */
e52fcb24 1985 mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
a8c94b91 1986 else
e52fcb24
ED		 1987 mtu = bp->dev->mtu;
1988 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
1989 IP_HEADER_ALIGNMENT_PADDING +
1990 ETH_OVREHEAD +
1991 mtu +
1992 BNX2X_FW_RX_ALIGN_END;
16a5fd92 1993 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
d46d132c
ED		 1994 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
1995 fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
1996 else
1997 fp->rx_frag_size = 0;
a8c94b91
VZ		 1998 }
1999}
2000
60cad4e6 2001static int bnx2x_init_rss(struct bnx2x *bp)
619c5cb6
VZ		 2002{
2003 int i;
619c5cb6
VZ		 2004 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2005
16a5fd92 2006 /* Prepare the initial contents for the indirection table if RSS is
619c5cb6
VZ		 2007 * enabled
2008 */
5d317c6a
MS		 2009 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2010 bp->rss_conf_obj.ind_table[i] =
96305234
DK		 2011 bp->fp->cl_id +
2012 ethtool_rxfh_indir_default(i, num_eth_queues);
619c5cb6
VZ		 2013
2014 /*
2015 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2016 * per-port, so if explicit configuration is needed , do it only
2017 * for a PMF.
2018 *
2019 * For 57712 and newer on the other hand it's a per-function
2020 * configuration.
2021 */
5d317c6a 2022 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
619c5cb6
VZ		 2023}
2024
60cad4e6
AE		 2025int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2026 bool config_hash, bool enable)
619c5cb6 2027{
3b603066 2028 struct bnx2x_config_rss_params params = {NULL};
619c5cb6
VZ		 2029
2030 /* Although RSS is meaningless when there is a single HW queue we
2031 * still need it enabled in order to have HW Rx hash generated.
2032 *
2033 * if (!is_eth_multi(bp))
2034 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
2035 */
2036
96305234 2037 params.rss_obj = rss_obj;
619c5cb6
VZ		 2038
2039 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2040
60cad4e6
AE		 2041 if (enable) {
2042 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
2043
2044 /* RSS configuration */
2045 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
2046 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
2047 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
2048 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
2049 if (rss_obj->udp_rss_v4)
2050 __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
2051 if (rss_obj->udp_rss_v6)
2052 __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
2053 } else {
2054 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
2055 }
619c5cb6 2056
96305234
DK		 2057 /* Hash bits */
2058 params.rss_result_mask = MULTI_MASK;
619c5cb6 2059
5d317c6a 2060 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
619c5cb6 2061
96305234
DK		 2062 if (config_hash) {
2063 /* RSS keys */
60cad4e6 2064 prandom_bytes(params.rss_key, T_ETH_RSS_KEY * 4);
96305234 2065 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
619c5cb6
VZ		 2066 }
2067
60cad4e6
AE		 2068 if (IS_PF(bp))
2069 return bnx2x_config_rss(bp, &params);
2070 else
2071 return bnx2x_vfpf_config_rss(bp, &params);
619c5cb6
VZ		 2072}
2073
1191cb83 2074static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
619c5cb6 2075{
3b603066 2076 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6
VZ		 2077
2078 /* Prepare parameters for function state transitions */
2079 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2080
2081 func_params.f_obj = &bp->func_obj;
2082 func_params.cmd = BNX2X_F_CMD_HW_INIT;
2083
2084 func_params.params.hw_init.load_phase = load_code;
2085
2086 return bnx2x_func_state_change(bp, &func_params);
2087}
2088
2089/*
2090 * Cleans the object that have internal lists without sending
16a5fd92 2091 * ramrods. Should be run when interrupts are disabled.
619c5cb6 2092 */
7fa6f340 2093void bnx2x_squeeze_objects(struct bnx2x *bp)
619c5cb6
VZ		 2094{
2095 int rc;
2096 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3b603066 2097 struct bnx2x_mcast_ramrod_params rparam = {NULL};
15192a8c 2098 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6
VZ		 2099
2100 /***************** Cleanup MACs' object first *************************/
2101
2102 /* Wait for completion of requested */
2103 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2104 /* Perform a dry cleanup */
2105 __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2106
2107 /* Clean ETH primary MAC */
2108 __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
15192a8c 2109 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
619c5cb6
VZ		 2110 &ramrod_flags);
2111 if (rc != 0)
2112 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2113
2114 /* Cleanup UC list */
2115 vlan_mac_flags = 0;
2116 __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2117 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2118 &ramrod_flags);
2119 if (rc != 0)
2120 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2121
2122 /***************** Now clean mcast object *****************************/
2123 rparam.mcast_obj = &bp->mcast_obj;
2124 __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2125
8b09be5f
YM		 2126 /* Add a DEL command... - Since we're doing a driver cleanup only,
2127 * we take a lock surrounding both the initial send and the CONTs,
2128 * as we don't want a true completion to disrupt us in the middle.
2129 */
2130 netif_addr_lock_bh(bp->dev);
619c5cb6
VZ		 2131 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2132 if (rc < 0)
51c1a580
MS		 2133 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2134 rc);
619c5cb6
VZ		 2135
2136 /* ...and wait until all pending commands are cleared */
2137 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2138 while (rc != 0) {
2139 if (rc < 0) {
2140 BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2141 rc);
8b09be5f 2142 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 2143 return;
2144 }
2145
2146 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2147 }
8b09be5f 2148 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 2149}
2150
2151#ifndef BNX2X_STOP_ON_ERROR
2152#define LOAD_ERROR_EXIT(bp, label) \
2153 do { \
2154 (bp)->state = BNX2X_STATE_ERROR; \
2155 goto label; \
2156 } while (0)
55c11941
MS		 2157
2158#define LOAD_ERROR_EXIT_CNIC(bp, label) \
2159 do { \
2160 bp->cnic_loaded = false; \
2161 goto label; \
2162 } while (0)
2163#else /*BNX2X_STOP_ON_ERROR*/
619c5cb6
VZ		 2164#define LOAD_ERROR_EXIT(bp, label) \
2165 do { \
2166 (bp)->state = BNX2X_STATE_ERROR; \
2167 (bp)->panic = 1; \
2168 return -EBUSY; \
2169 } while (0)
55c11941
MS		 2170#define LOAD_ERROR_EXIT_CNIC(bp, label) \
2171 do { \
2172 bp->cnic_loaded = false; \
2173 (bp)->panic = 1; \
2174 return -EBUSY; \
2175 } while (0)
2176#endif /*BNX2X_STOP_ON_ERROR*/
619c5cb6 2177
ad5afc89
AE		 2178static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2179{
2180 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2181 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2182 return;
2183}
2184
2185static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
452427b0 2186{
8db573ba 2187 int num_groups, vf_headroom = 0;
ad5afc89 2188 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
452427b0 2189
ad5afc89
AE		 2190 /* number of queues for statistics is number of eth queues + FCoE */
2191 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
452427b0 2192
ad5afc89
AE		 2193 /* Total number of FW statistics requests =
2194 * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2195 * and fcoe l2 queue) stats + num of queues (which includes another 1
2196 * for fcoe l2 queue if applicable)
2197 */
2198 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
452427b0 2199
8db573ba
AE		 2200 /* vf stats appear in the request list, but their data is allocated by
2201 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2202 * it is used to determine where to place the vf stats queries in the
2203 * request struct
2204 */
2205 if (IS_SRIOV(bp))
6411280a 2206 vf_headroom = bnx2x_vf_headroom(bp);
8db573ba 2207
ad5afc89
AE		 2208 /* Request is built from stats_query_header and an array of
2209 * stats_query_cmd_group each of which contains
2210 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2211 * configured in the stats_query_header.
2212 */
2213 num_groups =
8db573ba
AE		 2214 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2215 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
ad5afc89
AE		 2216 1 : 0));
2217
8db573ba
AE		 2218 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2219 bp->fw_stats_num, vf_headroom, num_groups);
ad5afc89
AE		 2220 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2221 num_groups * sizeof(struct stats_query_cmd_group);
2222
2223 /* Data for statistics requests + stats_counter
2224 * stats_counter holds per-STORM counters that are incremented
2225 * when STORM has finished with the current request.
2226 * memory for FCoE offloaded statistics are counted anyway,
2227 * even if they will not be sent.
2228 * VF stats are not accounted for here as the data of VF stats is stored
2229 * in memory allocated by the VF, not here.
2230 */
2231 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2232 sizeof(struct per_pf_stats) +
2233 sizeof(struct fcoe_statistics_params) +
2234 sizeof(struct per_queue_stats) * num_queue_stats +
2235 sizeof(struct stats_counter);
2236
cd2b0389
JP		 2237 bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2238 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2239 if (!bp->fw_stats)
2240 goto alloc_mem_err;
ad5afc89
AE		 2241
2242 /* Set shortcuts */
2243 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2244 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2245 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2246 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2247 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2248 bp->fw_stats_req_sz;
2249
6bf07b8e 2250 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
ad5afc89
AE		 2251 U64_HI(bp->fw_stats_req_mapping),
2252 U64_LO(bp->fw_stats_req_mapping));
6bf07b8e 2253 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
ad5afc89
AE		 2254 U64_HI(bp->fw_stats_data_mapping),
2255 U64_LO(bp->fw_stats_data_mapping));
2256 return 0;
2257
2258alloc_mem_err:
2259 bnx2x_free_fw_stats_mem(bp);
2260 BNX2X_ERR("Can't allocate FW stats memory\n");
2261 return -ENOMEM;
2262}
2263
2264/* send load request to mcp and analyze response */
2265static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2266{
178135c1
DK		 2267 u32 param;
2268
ad5afc89
AE		 2269 /* init fw_seq */
2270 bp->fw_seq =
2271 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2272 DRV_MSG_SEQ_NUMBER_MASK);
2273 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2274
2275 /* Get current FW pulse sequence */
2276 bp->fw_drv_pulse_wr_seq =
2277 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2278 DRV_PULSE_SEQ_MASK);
2279 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2280
178135c1
DK		 2281 param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2282
2283 if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2284 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2285
ad5afc89 2286 /* load request */
178135c1 2287 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
ad5afc89
AE		 2288
2289 /* if mcp fails to respond we must abort */
2290 if (!(*load_code)) {
2291 BNX2X_ERR("MCP response failure, aborting\n");
2292 return -EBUSY;
2293 }
2294
2295 /* If mcp refused (e.g. other port is in diagnostic mode) we
2296 * must abort
2297 */
2298 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2299 BNX2X_ERR("MCP refused load request, aborting\n");
2300 return -EBUSY;
2301 }
2302 return 0;
2303}
2304
2305/* check whether another PF has already loaded FW to chip. In
2306 * virtualized environments a pf from another VM may have already
2307 * initialized the device including loading FW
2308 */
91ebb929 2309int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err)
ad5afc89
AE		 2310{
2311 /* is another pf loaded on this engine? */
2312 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2313 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2314 /* build my FW version dword */
2315 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2316 (BCM_5710_FW_MINOR_VERSION << 8) +
2317 (BCM_5710_FW_REVISION_VERSION << 16) +
2318 (BCM_5710_FW_ENGINEERING_VERSION << 24);
2319
2320 /* read loaded FW from chip */
2321 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2322
2323 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2324 loaded_fw, my_fw);
2325
2326 /* abort nic load if version mismatch */
2327 if (my_fw != loaded_fw) {
91ebb929
YM		 2328 if (print_err)
2329 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
2330 loaded_fw, my_fw);
2331 else
2332 BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n",
2333 loaded_fw, my_fw);
ad5afc89
AE		 2334 return -EBUSY;
2335 }
2336 }
2337 return 0;
2338}
2339
2340/* returns the "mcp load_code" according to global load_count array */
2341static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2342{
2343 int path = BP_PATH(bp);
2344
2345 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 2346 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2347 bnx2x_load_count[path][2]);
2348 bnx2x_load_count[path][0]++;
2349 bnx2x_load_count[path][1 + port]++;
ad5afc89 2350 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 2351 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2352 bnx2x_load_count[path][2]);
2353 if (bnx2x_load_count[path][0] == 1)
ad5afc89 2354 return FW_MSG_CODE_DRV_LOAD_COMMON;
a8f47eb7 2355 else if (bnx2x_load_count[path][1 + port] == 1)
ad5afc89
AE		 2356 return FW_MSG_CODE_DRV_LOAD_PORT;
2357 else
2358 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2359}
2360
2361/* mark PMF if applicable */
2362static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2363{
2364 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2365 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2366 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2367 bp->port.pmf = 1;
2368 /* We need the barrier to ensure the ordering between the
2369 * writing to bp->port.pmf here and reading it from the
2370 * bnx2x_periodic_task().
2371 */
2372 smp_mb();
2373 } else {
2374 bp->port.pmf = 0;
452427b0
YM		 2375 }
2376
ad5afc89
AE		 2377 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2378}
2379
2380static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2381{
2382 if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2383 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2384 (bp->common.shmem2_base)) {
2385 if (SHMEM2_HAS(bp, dcc_support))
2386 SHMEM2_WR(bp, dcc_support,
2387 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2388 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2389 if (SHMEM2_HAS(bp, afex_driver_support))
2390 SHMEM2_WR(bp, afex_driver_support,
2391 SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2392 }
2393
2394 /* Set AFEX default VLAN tag to an invalid value */
2395 bp->afex_def_vlan_tag = -1;
452427b0
YM		 2396}
2397
1191cb83
ED		 2398/**
2399 * bnx2x_bz_fp - zero content of the fastpath structure.
2400 *
2401 * @bp: driver handle
2402 * @index: fastpath index to be zeroed
2403 *
2404 * Makes sure the contents of the bp->fp[index].napi is kept
2405 * intact.
2406 */
2407static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2408{
2409 struct bnx2x_fastpath *fp = &bp->fp[index];
65565884 2410 int cos;
1191cb83 2411 struct napi_struct orig_napi = fp->napi;
15192a8c 2412 struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
d76a6111 2413
1191cb83 2414 /* bzero bnx2x_fastpath contents */
c3146eb6
DK		 2415 if (fp->tpa_info)
2416 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2417 sizeof(struct bnx2x_agg_info));
2418 memset(fp, 0, sizeof(*fp));
1191cb83
ED		 2419
2420 /* Restore the NAPI object as it has been already initialized */
2421 fp->napi = orig_napi;
15192a8c 2422 fp->tpa_info = orig_tpa_info;
1191cb83
ED		 2423 fp->bp = bp;
2424 fp->index = index;
2425 if (IS_ETH_FP(fp))
2426 fp->max_cos = bp->max_cos;
2427 else
2428 /* Special queues support only one CoS */
2429 fp->max_cos = 1;
2430
65565884 2431 /* Init txdata pointers */
65565884
MS		 2432 if (IS_FCOE_FP(fp))
2433 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
65565884
MS		 2434 if (IS_ETH_FP(fp))
2435 for_each_cos_in_tx_queue(fp, cos)
2436 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2437 BNX2X_NUM_ETH_QUEUES(bp) + index];
2438
16a5fd92 2439 /* set the tpa flag for each queue. The tpa flag determines the queue
1191cb83
ED		 2440 * minimal size so it must be set prior to queue memory allocation
2441 */
2442 fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2443 (bp->flags & GRO_ENABLE_FLAG &&
2444 bnx2x_mtu_allows_gro(bp->dev->mtu)));
2445 if (bp->flags & TPA_ENABLE_FLAG)
2446 fp->mode = TPA_MODE_LRO;
2447 else if (bp->flags & GRO_ENABLE_FLAG)
2448 fp->mode = TPA_MODE_GRO;
2449
1191cb83
ED		 2450 /* We don't want TPA on an FCoE L2 ring */
2451 if (IS_FCOE_FP(fp))
2452 fp->disable_tpa = 1;
55c11941
MS		 2453}
2454
2455int bnx2x_load_cnic(struct bnx2x *bp)
2456{
2457 int i, rc, port = BP_PORT(bp);
2458
2459 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2460
2461 mutex_init(&bp->cnic_mutex);
2462
ad5afc89
AE		 2463 if (IS_PF(bp)) {
2464 rc = bnx2x_alloc_mem_cnic(bp);
2465 if (rc) {
2466 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2467 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2468 }
55c11941
MS		 2469 }
2470
2471 rc = bnx2x_alloc_fp_mem_cnic(bp);
2472 if (rc) {
2473 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2474 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2475 }
2476
2477 /* Update the number of queues with the cnic queues */
2478 rc = bnx2x_set_real_num_queues(bp, 1);
2479 if (rc) {
2480 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2481 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2482 }
2483
2484 /* Add all CNIC NAPI objects */
2485 bnx2x_add_all_napi_cnic(bp);
2486 DP(NETIF_MSG_IFUP, "cnic napi added\n");
2487 bnx2x_napi_enable_cnic(bp);
2488
2489 rc = bnx2x_init_hw_func_cnic(bp);
2490 if (rc)
2491 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2492
2493 bnx2x_nic_init_cnic(bp);
2494
ad5afc89
AE		 2495 if (IS_PF(bp)) {
2496 /* Enable Timer scan */
2497 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2498
2499 /* setup cnic queues */
2500 for_each_cnic_queue(bp, i) {
2501 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2502 if (rc) {
2503 BNX2X_ERR("Queue setup failed\n");
2504 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2505 }
55c11941
MS		 2506 }
2507 }
2508
2509 /* Initialize Rx filter. */
8b09be5f 2510 bnx2x_set_rx_mode_inner(bp);
55c11941
MS		 2511
2512 /* re-read iscsi info */
2513 bnx2x_get_iscsi_info(bp);
2514 bnx2x_setup_cnic_irq_info(bp);
2515 bnx2x_setup_cnic_info(bp);
2516 bp->cnic_loaded = true;
2517 if (bp->state == BNX2X_STATE_OPEN)
2518 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2519
55c11941
MS		 2520 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2521
2522 return 0;
2523
2524#ifndef BNX2X_STOP_ON_ERROR
2525load_error_cnic2:
2526 /* Disable Timer scan */
2527 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2528
2529load_error_cnic1:
2530 bnx2x_napi_disable_cnic(bp);
2531 /* Update the number of queues without the cnic queues */
d9d81862 2532 if (bnx2x_set_real_num_queues(bp, 0))
55c11941
MS		 2533 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2534load_error_cnic0:
2535 BNX2X_ERR("CNIC-related load failed\n");
2536 bnx2x_free_fp_mem_cnic(bp);
2537 bnx2x_free_mem_cnic(bp);
2538 return rc;
2539#endif /* ! BNX2X_STOP_ON_ERROR */
1191cb83
ED		 2540}
2541
9f6c9258
DK		 2542/* must be called with rtnl_lock */
2543int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2544{
619c5cb6 2545 int port = BP_PORT(bp);
ad5afc89 2546 int i, rc = 0, load_code = 0;
9f6c9258 2547
55c11941
MS		 2548 DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2549 DP(NETIF_MSG_IFUP,
2550 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2551
9f6c9258 2552#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 2553 if (unlikely(bp->panic)) {
2554 BNX2X_ERR("Can't load NIC when there is panic\n");
9f6c9258 2555 return -EPERM;
51c1a580 2556 }
9f6c9258
DK		 2557#endif
2558
2559 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2560
16a5fd92 2561 /* zero the structure w/o any lock, before SP handler is initialized */
2ae17f66
VZ		 2562 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2563 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2564 &bp->last_reported_link.link_report_flags);
2ae17f66 2565
ad5afc89
AE		 2566 if (IS_PF(bp))
2567 /* must be called before memory allocation and HW init */
2568 bnx2x_ilt_set_info(bp);
523224a3 2569
6383c0b3
AE		 2570 /*
2571 * Zero fastpath structures preserving invariants like napi, which are
2572 * allocated only once, fp index, max_cos, bp pointer.
65565884 2573 * Also set fp->disable_tpa and txdata_ptr.
b3b83c3f 2574 */
51c1a580 2575 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
b3b83c3f
DK		 2576 for_each_queue(bp, i)
2577 bnx2x_bz_fp(bp, i);
55c11941
MS		 2578 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2579 bp->num_cnic_queues) *
2580 sizeof(struct bnx2x_fp_txdata));
b3b83c3f 2581
55c11941 2582 bp->fcoe_init = false;
6383c0b3 2583
a8c94b91
VZ		 2584 /* Set the receive queues buffer size */
2585 bnx2x_set_rx_buf_size(bp);
2586
ad5afc89
AE		 2587 if (IS_PF(bp)) {
2588 rc = bnx2x_alloc_mem(bp);
2589 if (rc) {
2590 BNX2X_ERR("Unable to allocate bp memory\n");
2591 return rc;
2592 }
2593 }
2594
ad5afc89
AE		 2595 /* need to be done after alloc mem, since it's self adjusting to amount
2596 * of memory available for RSS queues
2597 */
2598 rc = bnx2x_alloc_fp_mem(bp);
2599 if (rc) {
2600 BNX2X_ERR("Unable to allocate memory for fps\n");
2601 LOAD_ERROR_EXIT(bp, load_error0);
2602 }
d6214d7a 2603
e3ed4eae
DK		 2604 /* Allocated memory for FW statistics */
2605 if (bnx2x_alloc_fw_stats_mem(bp))
2606 LOAD_ERROR_EXIT(bp, load_error0);
2607
8d9ac297
AE		 2608 /* request pf to initialize status blocks */
2609 if (IS_VF(bp)) {
2610 rc = bnx2x_vfpf_init(bp);
2611 if (rc)
2612 LOAD_ERROR_EXIT(bp, load_error0);
2613 }
2614
b3b83c3f
DK		 2615 /* As long as bnx2x_alloc_mem() may possibly update
2616 * bp->num_queues, bnx2x_set_real_num_queues() should always
55c11941 2617 * come after it. At this stage cnic queues are not counted.
b3b83c3f 2618 */
55c11941 2619 rc = bnx2x_set_real_num_queues(bp, 0);
d6214d7a 2620 if (rc) {
ec6ba945 2621 BNX2X_ERR("Unable to set real_num_queues\n");
619c5cb6 2622 LOAD_ERROR_EXIT(bp, load_error0);
9f6c9258
DK		 2623 }
2624
6383c0b3 2625 /* configure multi cos mappings in kernel.
16a5fd92
YM		 2626 * this configuration may be overridden by a multi class queue
2627 * discipline or by a dcbx negotiation result.
6383c0b3
AE		 2628 */
2629 bnx2x_setup_tc(bp->dev, bp->max_cos);
2630
26614ba5
MS		 2631 /* Add all NAPI objects */
2632 bnx2x_add_all_napi(bp);
55c11941 2633 DP(NETIF_MSG_IFUP, "napi added\n");
9f6c9258
DK		 2634 bnx2x_napi_enable(bp);
2635
ad5afc89
AE		 2636 if (IS_PF(bp)) {
2637 /* set pf load just before approaching the MCP */
2638 bnx2x_set_pf_load(bp);
2639
2640 /* if mcp exists send load request and analyze response */
2641 if (!BP_NOMCP(bp)) {
2642 /* attempt to load pf */
2643 rc = bnx2x_nic_load_request(bp, &load_code);
2644 if (rc)
2645 LOAD_ERROR_EXIT(bp, load_error1);
2646
2647 /* what did mcp say? */
91ebb929 2648 rc = bnx2x_compare_fw_ver(bp, load_code, true);
ad5afc89
AE		 2649 if (rc) {
2650 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
d1e2d966
AE		 2651 LOAD_ERROR_EXIT(bp, load_error2);
2652 }
ad5afc89
AE		 2653 } else {
2654 load_code = bnx2x_nic_load_no_mcp(bp, port);
d1e2d966 2655 }
9f6c9258 2656
ad5afc89
AE		 2657 /* mark pmf if applicable */
2658 bnx2x_nic_load_pmf(bp, load_code);
9f6c9258 2659
ad5afc89
AE		 2660 /* Init Function state controlling object */
2661 bnx2x__init_func_obj(bp);
6383c0b3 2662
ad5afc89
AE		 2663 /* Initialize HW */
2664 rc = bnx2x_init_hw(bp, load_code);
2665 if (rc) {
2666 BNX2X_ERR("HW init failed, aborting\n");
2667 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2668 LOAD_ERROR_EXIT(bp, load_error2);
2669 }
9f6c9258
DK		 2670 }
2671
ecf01c22
YM		 2672 bnx2x_pre_irq_nic_init(bp);
2673
d6214d7a
DK		 2674 /* Connect to IRQs */
2675 rc = bnx2x_setup_irqs(bp);
523224a3 2676 if (rc) {
ad5afc89
AE		 2677 BNX2X_ERR("setup irqs failed\n");
2678 if (IS_PF(bp))
2679 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
619c5cb6 2680 LOAD_ERROR_EXIT(bp, load_error2);
523224a3
DK		 2681 }
2682
619c5cb6 2683 /* Init per-function objects */
ad5afc89 2684 if (IS_PF(bp)) {
ecf01c22
YM		 2685 /* Setup NIC internals and enable interrupts */
2686 bnx2x_post_irq_nic_init(bp, load_code);
2687
ad5afc89 2688 bnx2x_init_bp_objs(bp);
b56e9670 2689 bnx2x_iov_nic_init(bp);
a3348722 2690
ad5afc89
AE		 2691 /* Set AFEX default VLAN tag to an invalid value */
2692 bp->afex_def_vlan_tag = -1;
2693 bnx2x_nic_load_afex_dcc(bp, load_code);
2694 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2695 rc = bnx2x_func_start(bp);
2696 if (rc) {
2697 BNX2X_ERR("Function start failed!\n");
2698 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9f6c9258 2699
619c5cb6 2700 LOAD_ERROR_EXIT(bp, load_error3);
9f6c9258 2701 }
9f6c9258 2702
ad5afc89
AE		 2703 /* Send LOAD_DONE command to MCP */
2704 if (!BP_NOMCP(bp)) {
2705 load_code = bnx2x_fw_command(bp,
2706 DRV_MSG_CODE_LOAD_DONE, 0);
2707 if (!load_code) {
2708 BNX2X_ERR("MCP response failure, aborting\n");
2709 rc = -EBUSY;
2710 LOAD_ERROR_EXIT(bp, load_error3);
2711 }
2712 }
9f6c9258 2713
0c14e5ce
AE		 2714 /* initialize FW coalescing state machines in RAM */
2715 bnx2x_update_coalesce(bp);
60cad4e6 2716 }
0c14e5ce 2717
60cad4e6
AE		 2718 /* setup the leading queue */
2719 rc = bnx2x_setup_leading(bp);
2720 if (rc) {
2721 BNX2X_ERR("Setup leading failed!\n");
2722 LOAD_ERROR_EXIT(bp, load_error3);
2723 }
ad5afc89 2724
60cad4e6
AE		 2725 /* set up the rest of the queues */
2726 for_each_nondefault_eth_queue(bp, i) {
2727 if (IS_PF(bp))
2728 rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2729 else /* VF */
2730 rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
ad5afc89 2731 if (rc) {
60cad4e6 2732 BNX2X_ERR("Queue %d setup failed\n", i);
ad5afc89
AE		 2733 LOAD_ERROR_EXIT(bp, load_error3);
2734 }
60cad4e6 2735 }
8d9ac297 2736
60cad4e6
AE		 2737 /* setup rss */
2738 rc = bnx2x_init_rss(bp);
2739 if (rc) {
2740 BNX2X_ERR("PF RSS init failed\n");
2741 LOAD_ERROR_EXIT(bp, load_error3);
51c1a580 2742 }
619c5cb6 2743
523224a3
DK		 2744 /* Now when Clients are configured we are ready to work */
2745 bp->state = BNX2X_STATE_OPEN;
2746
619c5cb6 2747 /* Configure a ucast MAC */
ad5afc89
AE		 2748 if (IS_PF(bp))
2749 rc = bnx2x_set_eth_mac(bp, true);
8d9ac297 2750 else /* vf */
f8f4f61a
DK		 2751 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2752 true);
51c1a580
MS		 2753 if (rc) {
2754 BNX2X_ERR("Setting Ethernet MAC failed\n");
55c11941 2755 LOAD_ERROR_EXIT(bp, load_error3);
51c1a580 2756 }
6e30dd4e 2757
ad5afc89 2758 if (IS_PF(bp) && bp->pending_max) {
e3835b99
DK		 2759 bnx2x_update_max_mf_config(bp, bp->pending_max);
2760 bp->pending_max = 0;
2761 }
2762
ad5afc89
AE		 2763 if (bp->port.pmf) {
2764 rc = bnx2x_initial_phy_init(bp, load_mode);
2765 if (rc)
2766 LOAD_ERROR_EXIT(bp, load_error3);
2767 }
c63da990 2768 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
9f6c9258 2769
619c5cb6
VZ		 2770 /* Start fast path */
2771
2772 /* Initialize Rx filter. */
8b09be5f 2773 bnx2x_set_rx_mode_inner(bp);
6e30dd4e 2774
619c5cb6 2775 /* Start the Tx */
9f6c9258
DK		 2776 switch (load_mode) {
2777 case LOAD_NORMAL:
16a5fd92 2778 /* Tx queue should be only re-enabled */
523224a3 2779 netif_tx_wake_all_queues(bp->dev);
9f6c9258
DK		 2780 break;
2781
2782 case LOAD_OPEN:
2783 netif_tx_start_all_queues(bp->dev);
4e857c58 2784 smp_mb__after_atomic();
9f6c9258
DK		 2785 break;
2786
2787 case LOAD_DIAG:
8970b2e4 2788 case LOAD_LOOPBACK_EXT:
9f6c9258
DK		 2789 bp->state = BNX2X_STATE_DIAG;
2790 break;
2791
2792 default:
2793 break;
2794 }
2795
00253a8c 2796 if (bp->port.pmf)
4c704899 2797 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
00253a8c 2798 else
9f6c9258
DK		 2799 bnx2x__link_status_update(bp);
2800
2801 /* start the timer */
2802 mod_timer(&bp->timer, jiffies + bp->current_interval);
2803
55c11941
MS		 2804 if (CNIC_ENABLED(bp))
2805 bnx2x_load_cnic(bp);
9f6c9258 2806
42f8277f
YM		 2807 if (IS_PF(bp))
2808 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2809
ad5afc89
AE		 2810 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2811 /* mark driver is loaded in shmem2 */
9ce392d4
YM		 2812 u32 val;
2813 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2814 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2815 val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2816 DRV_FLAGS_CAPABILITIES_LOADED_L2);
2817 }
2818
619c5cb6 2819 /* Wait for all pending SP commands to complete */
ad5afc89 2820 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
619c5cb6 2821 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
5d07d868 2822 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
619c5cb6
VZ		 2823 return -EBUSY;
2824 }
6891dd25 2825
9876879f
BW		 2826 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2827 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2828 bnx2x_dcbx_init(bp, false);
2829
55c11941
MS		 2830 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2831
9f6c9258
DK		 2832 return 0;
2833
619c5cb6 2834#ifndef BNX2X_STOP_ON_ERROR
9f6c9258 2835load_error3:
ad5afc89
AE		 2836 if (IS_PF(bp)) {
2837 bnx2x_int_disable_sync(bp, 1);
d6214d7a 2838
ad5afc89
AE		 2839 /* Clean queueable objects */
2840 bnx2x_squeeze_objects(bp);
2841 }
619c5cb6 2842
9f6c9258
DK		 2843 /* Free SKBs, SGEs, TPA pool and driver internals */
2844 bnx2x_free_skbs(bp);
ec6ba945 2845 for_each_rx_queue(bp, i)
9f6c9258 2846 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 2847
9f6c9258 2848 /* Release IRQs */
d6214d7a
DK		 2849 bnx2x_free_irq(bp);
2850load_error2:
ad5afc89 2851 if (IS_PF(bp) && !BP_NOMCP(bp)) {
d6214d7a
DK		 2852 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2853 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2854 }
2855
2856 bp->port.pmf = 0;
9f6c9258
DK		 2857load_error1:
2858 bnx2x_napi_disable(bp);
722c6f58 2859 bnx2x_del_all_napi(bp);
ad5afc89 2860
889b9af3 2861 /* clear pf_load status, as it was already set */
ad5afc89
AE		 2862 if (IS_PF(bp))
2863 bnx2x_clear_pf_load(bp);
d6214d7a 2864load_error0:
ad5afc89 2865 bnx2x_free_fw_stats_mem(bp);
e3ed4eae 2866 bnx2x_free_fp_mem(bp);
9f6c9258
DK		 2867 bnx2x_free_mem(bp);
2868
2869 return rc;
619c5cb6 2870#endif /* ! BNX2X_STOP_ON_ERROR */
9f6c9258
DK		 2871}
2872
7fa6f340 2873int bnx2x_drain_tx_queues(struct bnx2x *bp)
ad5afc89
AE		 2874{
2875 u8 rc = 0, cos, i;
2876
2877 /* Wait until tx fastpath tasks complete */
2878 for_each_tx_queue(bp, i) {
2879 struct bnx2x_fastpath *fp = &bp->fp[i];
2880
2881 for_each_cos_in_tx_queue(fp, cos)
2882 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2883 if (rc)
2884 return rc;
2885 }
2886 return 0;
2887}
2888
9f6c9258 2889/* must be called with rtnl_lock */
5d07d868 2890int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
9f6c9258
DK		 2891{
2892 int i;
c9ee9206
VZ		 2893 bool global = false;
2894
55c11941
MS		 2895 DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2896
9ce392d4 2897 /* mark driver is unloaded in shmem2 */
ad5afc89 2898 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
9ce392d4
YM		 2899 u32 val;
2900 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2901 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2902 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2903 }
2904
80bfe5cc 2905 if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
ad5afc89
AE		 2906 (bp->state == BNX2X_STATE_CLOSED ||
2907 bp->state == BNX2X_STATE_ERROR)) {
c9ee9206
VZ		 2908 /* We can get here if the driver has been unloaded
2909 * during parity error recovery and is either waiting for a
2910 * leader to complete or for other functions to unload and
2911 * then ifdown has been issued. In this case we want to
2912 * unload and let other functions to complete a recovery
2913 * process.
2914 */
9f6c9258
DK		 2915 bp->recovery_state = BNX2X_RECOVERY_DONE;
2916 bp->is_leader = 0;
c9ee9206
VZ		 2917 bnx2x_release_leader_lock(bp);
2918 smp_mb();
2919
51c1a580
MS		 2920 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2921 BNX2X_ERR("Can't unload in closed or error state\n");
9f6c9258
DK		 2922 return -EINVAL;
2923 }
2924
80bfe5cc 2925 /* Nothing to do during unload if previous bnx2x_nic_load()
16a5fd92 2926 * have not completed successfully - all resources are released.
80bfe5cc
YM		 2927 *
2928 * we can get here only after unsuccessful ndo_* callback, during which
2929 * dev->IFF_UP flag is still on.
2930 */
2931 if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
2932 return 0;
2933
2934 /* It's important to set the bp->state to the value different from
87b7ba3d
VZ		 2935 * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
2936 * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
2937 */
2938 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
2939 smp_mb();
2940
78c3bcc5
AE		 2941 /* indicate to VFs that the PF is going down */
2942 bnx2x_iov_channel_down(bp);
2943
55c11941
MS		 2944 if (CNIC_LOADED(bp))
2945 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
2946
9505ee37
VZ		 2947 /* Stop Tx */
2948 bnx2x_tx_disable(bp);
65565884 2949 netdev_reset_tc(bp->dev);
9505ee37 2950
9f6c9258 2951 bp->rx_mode = BNX2X_RX_MODE_NONE;
9f6c9258 2952
9f6c9258 2953 del_timer_sync(&bp->timer);
f85582f8 2954
ad5afc89
AE		 2955 if (IS_PF(bp)) {
2956 /* Set ALWAYS_ALIVE bit in shmem */
2957 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2958 bnx2x_drv_pulse(bp);
2959 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2960 bnx2x_save_statistics(bp);
2961 }
9f6c9258 2962
ad5afc89
AE		 2963 /* wait till consumers catch up with producers in all queues */
2964 bnx2x_drain_tx_queues(bp);
9f6c9258 2965
9b176b6b
AE		 2966 /* if VF indicate to PF this function is going down (PF will delete sp
2967 * elements and clear initializations
2968 */
2969 if (IS_VF(bp))
2970 bnx2x_vfpf_close_vf(bp);
2971 else if (unload_mode != UNLOAD_RECOVERY)
2972 /* if this is a normal/close unload need to clean up chip*/
5d07d868 2973 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
523224a3 2974 else {
c9ee9206
VZ		 2975 /* Send the UNLOAD_REQUEST to the MCP */
2976 bnx2x_send_unload_req(bp, unload_mode);
2977
16a5fd92 2978 /* Prevent transactions to host from the functions on the
c9ee9206 2979 * engine that doesn't reset global blocks in case of global
16a5fd92 2980 * attention once global blocks are reset and gates are opened
c9ee9206
VZ		 2981 * (the engine which leader will perform the recovery
2982 * last).
2983 */
2984 if (!CHIP_IS_E1x(bp))
2985 bnx2x_pf_disable(bp);
2986
2987 /* Disable HW interrupts, NAPI */
523224a3 2988 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 2989 /* Delete all NAPI objects */
2990 bnx2x_del_all_napi(bp);
55c11941
MS		 2991 if (CNIC_LOADED(bp))
2992 bnx2x_del_all_napi_cnic(bp);
523224a3 2993 /* Release IRQs */
d6214d7a 2994 bnx2x_free_irq(bp);
c9ee9206
VZ		 2995
2996 /* Report UNLOAD_DONE to MCP */
5d07d868 2997 bnx2x_send_unload_done(bp, false);
523224a3 2998 }
9f6c9258 2999
619c5cb6 3000 /*
16a5fd92 3001 * At this stage no more interrupts will arrive so we may safely clean
619c5cb6
VZ		 3002 * the queueable objects here in case they failed to get cleaned so far.
3003 */
ad5afc89
AE		 3004 if (IS_PF(bp))
3005 bnx2x_squeeze_objects(bp);
619c5cb6 3006
79616895
VZ		 3007 /* There should be no more pending SP commands at this stage */
3008 bp->sp_state = 0;
3009
9f6c9258
DK		 3010 bp->port.pmf = 0;
3011
a0d307b2
DK		 3012 /* clear pending work in rtnl task */
3013 bp->sp_rtnl_state = 0;
3014 smp_mb();
3015
9f6c9258
DK		 3016 /* Free SKBs, SGEs, TPA pool and driver internals */
3017 bnx2x_free_skbs(bp);
55c11941
MS		 3018 if (CNIC_LOADED(bp))
3019 bnx2x_free_skbs_cnic(bp);
ec6ba945 3020 for_each_rx_queue(bp, i)
9f6c9258 3021 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 3022
ad5afc89
AE		 3023 bnx2x_free_fp_mem(bp);
3024 if (CNIC_LOADED(bp))
55c11941 3025 bnx2x_free_fp_mem_cnic(bp);
9f6c9258 3026
ad5afc89 3027 if (IS_PF(bp)) {
ad5afc89
AE		 3028 if (CNIC_LOADED(bp))
3029 bnx2x_free_mem_cnic(bp);
3030 }
b4cddbd6
AE		 3031 bnx2x_free_mem(bp);
3032
9f6c9258 3033 bp->state = BNX2X_STATE_CLOSED;
55c11941 3034 bp->cnic_loaded = false;
9f6c9258 3035
42f8277f
YM		 3036 /* Clear driver version indication in shmem */
3037 if (IS_PF(bp))
3038 bnx2x_update_mng_version(bp);
3039
c9ee9206
VZ		 3040 /* Check if there are pending parity attentions. If there are - set
3041 * RECOVERY_IN_PROGRESS.
3042 */
ad5afc89 3043 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
c9ee9206
VZ		 3044 bnx2x_set_reset_in_progress(bp);
3045
3046 /* Set RESET_IS_GLOBAL if needed */
3047 if (global)
3048 bnx2x_set_reset_global(bp);
3049 }
3050
9f6c9258
DK		 3051 /* The last driver must disable a "close the gate" if there is no
3052 * parity attention or "process kill" pending.
3053 */
ad5afc89
AE		 3054 if (IS_PF(bp) &&
3055 !bnx2x_clear_pf_load(bp) &&
3056 bnx2x_reset_is_done(bp, BP_PATH(bp)))
9f6c9258
DK		 3057 bnx2x_disable_close_the_gate(bp);
3058
55c11941
MS		 3059 DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
3060
9f6c9258
DK		 3061 return 0;
3062}
f85582f8 3063
9f6c9258
DK		 3064int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
3065{
3066 u16 pmcsr;
3067
adf5f6a1 3068 /* If there is no power capability, silently succeed */
29ed74c3 3069 if (!bp->pdev->pm_cap) {
51c1a580 3070 BNX2X_DEV_INFO("No power capability. Breaking.\n");
adf5f6a1
DK		 3071 return 0;
3072 }
3073
29ed74c3 3074 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
9f6c9258
DK		 3075
3076 switch (state) {
3077 case PCI_D0:
29ed74c3 3078 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
9f6c9258
DK		 3079 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3080 PCI_PM_CTRL_PME_STATUS));
3081
3082 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3083 /* delay required during transition out of D3hot */
3084 msleep(20);
3085 break;
3086
3087 case PCI_D3hot:
3088 /* If there are other clients above don't
3089 shut down the power */
3090 if (atomic_read(&bp->pdev->enable_cnt) != 1)
3091 return 0;
3092 /* Don't shut down the power for emulation and FPGA */
3093 if (CHIP_REV_IS_SLOW(bp))
3094 return 0;
3095
3096 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3097 pmcsr |= 3;
3098
3099 if (bp->wol)
3100 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3101
29ed74c3 3102 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
9f6c9258
DK		 3103 pmcsr);
3104
3105 /* No more memory access after this point until
3106 * device is brought back to D0.
3107 */
3108 break;
3109
3110 default:
51c1a580 3111 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
9f6c9258
DK		 3112 return -EINVAL;
3113 }
3114 return 0;
3115}
3116
9f6c9258
DK		 3117/*
3118 * net_device service functions
3119 */
a8f47eb7 3120static int bnx2x_poll(struct napi_struct *napi, int budget)
9f6c9258
DK		 3121{
3122 int work_done = 0;
6383c0b3 3123 u8 cos;
9f6c9258
DK		 3124 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3125 napi);
3126 struct bnx2x *bp = fp->bp;
3127
3128 while (1) {
3129#ifdef BNX2X_STOP_ON_ERROR
3130 if (unlikely(bp->panic)) {
3131 napi_complete(napi);
3132 return 0;
3133 }
3134#endif
8f20aa57
DK		 3135 if (!bnx2x_fp_lock_napi(fp))
3136 return work_done;
9f6c9258 3137
6383c0b3 3138 for_each_cos_in_tx_queue(fp, cos)
65565884
MS		 3139 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
3140 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
6383c0b3 3141
9f6c9258
DK		 3142 if (bnx2x_has_rx_work(fp)) {
3143 work_done += bnx2x_rx_int(fp, budget - work_done);
3144
3145 /* must not complete if we consumed full budget */
8f20aa57
DK		 3146 if (work_done >= budget) {
3147 bnx2x_fp_unlock_napi(fp);
9f6c9258 3148 break;
8f20aa57 3149 }
9f6c9258
DK		 3150 }
3151
3152 /* Fall out from the NAPI loop if needed */
8f20aa57
DK		 3153 if (!bnx2x_fp_unlock_napi(fp) &&
3154 !(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
55c11941 3155
ec6ba945
VZ		 3156 /* No need to update SB for FCoE L2 ring as long as
3157 * it's connected to the default SB and the SB
3158 * has been updated when NAPI was scheduled.
3159 */
3160 if (IS_FCOE_FP(fp)) {
3161 napi_complete(napi);
3162 break;
3163 }
9f6c9258 3164 bnx2x_update_fpsb_idx(fp);
f85582f8
DK		 3165 /* bnx2x_has_rx_work() reads the status block,
3166 * thus we need to ensure that status block indices
3167 * have been actually read (bnx2x_update_fpsb_idx)
3168 * prior to this check (bnx2x_has_rx_work) so that
3169 * we won't write the "newer" value of the status block
3170 * to IGU (if there was a DMA right after
3171 * bnx2x_has_rx_work and if there is no rmb, the memory
3172 * reading (bnx2x_update_fpsb_idx) may be postponed
3173 * to right before bnx2x_ack_sb). In this case there
3174 * will never be another interrupt until there is
3175 * another update of the status block, while there
3176 * is still unhandled work.
3177 */
9f6c9258
DK		 3178 rmb();
3179
3180 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3181 napi_complete(napi);
3182 /* Re-enable interrupts */
51c1a580 3183 DP(NETIF_MSG_RX_STATUS,
523224a3
DK		 3184 "Update index to %d\n", fp->fp_hc_idx);
3185 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3186 le16_to_cpu(fp->fp_hc_idx),
9f6c9258
DK		 3187 IGU_INT_ENABLE, 1);
3188 break;
3189 }
3190 }
3191 }
3192
3193 return work_done;
3194}
3195
e0d1095a 3196#ifdef CONFIG_NET_RX_BUSY_POLL
8f20aa57
DK		 3197/* must be called with local_bh_disable()d */
3198int bnx2x_low_latency_recv(struct napi_struct *napi)
3199{
3200 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3201 napi);
3202 struct bnx2x *bp = fp->bp;
3203 int found = 0;
3204
3205 if ((bp->state == BNX2X_STATE_CLOSED) ||
3206 (bp->state == BNX2X_STATE_ERROR) ||
3207 (bp->flags & (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG)))
3208 return LL_FLUSH_FAILED;
3209
3210 if (!bnx2x_fp_lock_poll(fp))
3211 return LL_FLUSH_BUSY;
3212
75b29459 3213 if (bnx2x_has_rx_work(fp))
8f20aa57 3214 found = bnx2x_rx_int(fp, 4);
8f20aa57
DK		 3215
3216 bnx2x_fp_unlock_poll(fp);
3217
3218 return found;
3219}
3220#endif
3221
9f6c9258
DK		 3222/* we split the first BD into headers and data BDs
3223 * to ease the pain of our fellow microcode engineers
3224 * we use one mapping for both BDs
9f6c9258 3225 */
91226790
DK		 3226static u16 bnx2x_tx_split(struct bnx2x *bp,
3227 struct bnx2x_fp_txdata *txdata,
3228 struct sw_tx_bd *tx_buf,
3229 struct eth_tx_start_bd **tx_bd, u16 hlen,
3230 u16 bd_prod)
9f6c9258
DK		 3231{
3232 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
3233 struct eth_tx_bd *d_tx_bd;
3234 dma_addr_t mapping;
3235 int old_len = le16_to_cpu(h_tx_bd->nbytes);
3236
3237 /* first fix first BD */
9f6c9258
DK		 3238 h_tx_bd->nbytes = cpu_to_le16(hlen);
3239
91226790
DK		 3240 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x)\n",
3241 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo);
9f6c9258
DK		 3242
3243 /* now get a new data BD
3244 * (after the pbd) and fill it */
3245 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
6383c0b3 3246 d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
9f6c9258
DK		 3247
3248 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
3249 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
3250
3251 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3252 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3253 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
3254
3255 /* this marks the BD as one that has no individual mapping */
3256 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
3257
3258 DP(NETIF_MSG_TX_QUEUED,
3259 "TSO split data size is %d (%x:%x)\n",
3260 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
3261
3262 /* update tx_bd */
3263 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
3264
3265 return bd_prod;
3266}
3267
86564c3f
YM		 3268#define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32)))
3269#define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16)))
91226790 3270static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
9f6c9258 3271{
86564c3f
YM		 3272 __sum16 tsum = (__force __sum16) csum;
3273
9f6c9258 3274 if (fix > 0)
86564c3f
YM		 3275 tsum = ~csum_fold(csum_sub((__force __wsum) csum,
3276 csum_partial(t_header - fix, fix, 0)));
9f6c9258
DK		 3277
3278 else if (fix < 0)
86564c3f
YM		 3279 tsum = ~csum_fold(csum_add((__force __wsum) csum,
3280 csum_partial(t_header, -fix, 0)));
9f6c9258 3281
e2593fcd 3282 return bswab16(tsum);
9f6c9258
DK		 3283}
3284
91226790 3285static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
9f6c9258
DK		 3286{
3287 u32 rc;
a848ade4
DK		 3288 __u8 prot = 0;
3289 __be16 protocol;
9f6c9258
DK		 3290
3291 if (skb->ip_summed != CHECKSUM_PARTIAL)
a848ade4 3292 return XMIT_PLAIN;
9f6c9258 3293
a848ade4
DK		 3294 protocol = vlan_get_protocol(skb);
3295 if (protocol == htons(ETH_P_IPV6)) {
3296 rc = XMIT_CSUM_V6;
3297 prot = ipv6_hdr(skb)->nexthdr;
3298 } else {
3299 rc = XMIT_CSUM_V4;
3300 prot = ip_hdr(skb)->protocol;
3301 }
9f6c9258 3302
a848ade4
DK		 3303 if (!CHIP_IS_E1x(bp) && skb->encapsulation) {
3304 if (inner_ip_hdr(skb)->version == 6) {
3305 rc |= XMIT_CSUM_ENC_V6;
3306 if (inner_ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3307 rc |= XMIT_CSUM_TCP;
9f6c9258 3308 } else {
a848ade4
DK		 3309 rc |= XMIT_CSUM_ENC_V4;
3310 if (inner_ip_hdr(skb)->protocol == IPPROTO_TCP)
9f6c9258
DK		 3311 rc |= XMIT_CSUM_TCP;
3312 }
3313 }
a848ade4
DK		 3314 if (prot == IPPROTO_TCP)
3315 rc |= XMIT_CSUM_TCP;
9f6c9258 3316
36a8f39e
ED		 3317 if (skb_is_gso(skb)) {
3318 if (skb_is_gso_v6(skb)) {
3319 rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP);
3320 if (rc & XMIT_CSUM_ENC)
3321 rc |= XMIT_GSO_ENC_V6;
3322 } else {
3323 rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP);
3324 if (rc & XMIT_CSUM_ENC)
3325 rc |= XMIT_GSO_ENC_V4;
3326 }
a848ade4 3327 }
9f6c9258
DK		 3328
3329 return rc;
3330}
3331
3332#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3333/* check if packet requires linearization (packet is too fragmented)
3334 no need to check fragmentation if page size > 8K (there will be no
3335 violation to FW restrictions) */
3336static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3337 u32 xmit_type)
3338{
3339 int to_copy = 0;
3340 int hlen = 0;
3341 int first_bd_sz = 0;
3342
3343 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
3344 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
3345
3346 if (xmit_type & XMIT_GSO) {
3347 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
3348 /* Check if LSO packet needs to be copied:
3349 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
3350 int wnd_size = MAX_FETCH_BD - 3;
3351 /* Number of windows to check */
3352 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
3353 int wnd_idx = 0;
3354 int frag_idx = 0;
3355 u32 wnd_sum = 0;
3356
3357 /* Headers length */
3358 hlen = (int)(skb_transport_header(skb) - skb->data) +
3359 tcp_hdrlen(skb);
3360
3361 /* Amount of data (w/o headers) on linear part of SKB*/
3362 first_bd_sz = skb_headlen(skb) - hlen;
3363
3364 wnd_sum = first_bd_sz;
3365
3366 /* Calculate the first sum - it's special */
3367 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
3368 wnd_sum +=
9e903e08 3369 skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]);
9f6c9258
DK		 3370
3371 /* If there was data on linear skb data - check it */
3372 if (first_bd_sz > 0) {
3373 if (unlikely(wnd_sum < lso_mss)) {
3374 to_copy = 1;
3375 goto exit_lbl;
3376 }
3377
3378 wnd_sum -= first_bd_sz;
3379 }
3380
3381 /* Others are easier: run through the frag list and
3382 check all windows */
3383 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
3384 wnd_sum +=
9e903e08 3385 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]);
9f6c9258
DK		 3386
3387 if (unlikely(wnd_sum < lso_mss)) {
3388 to_copy = 1;
3389 break;
3390 }
3391 wnd_sum -=
9e903e08 3392 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]);
9f6c9258
DK		 3393 }
3394 } else {
3395 /* in non-LSO too fragmented packet should always
3396 be linearized */
3397 to_copy = 1;
3398 }
3399 }
3400
3401exit_lbl:
3402 if (unlikely(to_copy))
3403 DP(NETIF_MSG_TX_QUEUED,
51c1a580 3404 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
9f6c9258
DK		 3405 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
3406 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
3407
3408 return to_copy;
3409}
3410#endif
3411
91226790
DK		 3412static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
3413 u32 xmit_type)
f2e0899f 3414{
a848ade4
DK		 3415 struct ipv6hdr *ipv6;
3416
2297a2da
VZ		 3417 *parsing_data |= (skb_shinfo(skb)->gso_size <<
3418 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
3419 ETH_TX_PARSE_BD_E2_LSO_MSS;
a848ade4
DK		 3420
3421 if (xmit_type & XMIT_GSO_ENC_V6)
3422 ipv6 = inner_ipv6_hdr(skb);
3423 else if (xmit_type & XMIT_GSO_V6)
3424 ipv6 = ipv6_hdr(skb);
3425 else
3426 ipv6 = NULL;
3427
3428 if (ipv6 && ipv6->nexthdr == NEXTHDR_IPV6)
2297a2da 3429 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
f2e0899f
DK		 3430}
3431
3432/**
e8920674 3433 * bnx2x_set_pbd_gso - update PBD in GSO case.
f2e0899f 3434 *
e8920674
DK		 3435 * @skb: packet skb
3436 * @pbd: parse BD
3437 * @xmit_type: xmit flags
f2e0899f 3438 */
91226790
DK		 3439static void bnx2x_set_pbd_gso(struct sk_buff *skb,
3440 struct eth_tx_parse_bd_e1x *pbd,
057cf65e 3441 struct eth_tx_start_bd *tx_start_bd,
91226790 3442 u32 xmit_type)
f2e0899f
DK		 3443{
3444 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
86564c3f 3445 pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq);
91226790 3446 pbd->tcp_flags = pbd_tcp_flags(tcp_hdr(skb));
f2e0899f
DK		 3447
3448 if (xmit_type & XMIT_GSO_V4) {
86564c3f 3449 pbd->ip_id = bswab16(ip_hdr(skb)->id);
f2e0899f 3450 pbd->tcp_pseudo_csum =
86564c3f
YM		 3451 bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
3452 ip_hdr(skb)->daddr,
3453 0, IPPROTO_TCP, 0));
f2e0899f 3454
057cf65e
YM		 3455 /* GSO on 57710/57711 needs FW to calculate IP checksum */
3456 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
3457 } else {
f2e0899f 3458 pbd->tcp_pseudo_csum =
86564c3f
YM		 3459 bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3460 &ipv6_hdr(skb)->daddr,
3461 0, IPPROTO_TCP, 0));
057cf65e 3462 }
f2e0899f 3463
86564c3f
YM		 3464 pbd->global_data |=
3465 cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
f2e0899f 3466}
f85582f8 3467
a848ade4
DK		 3468/**
3469 * bnx2x_set_pbd_csum_enc - update PBD with checksum and return header length
3470 *
3471 * @bp: driver handle
3472 * @skb: packet skb
3473 * @parsing_data: data to be updated
3474 * @xmit_type: xmit flags
3475 *
3476 * 57712/578xx related, when skb has encapsulation
3477 */
3478static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
3479 u32 *parsing_data, u32 xmit_type)
3480{
3481 *parsing_data |=
3482 ((((u8 *)skb_inner_transport_header(skb) - skb->data) >> 1) <<
3483 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
3484 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
3485
3486 if (xmit_type & XMIT_CSUM_TCP) {
3487 *parsing_data |= ((inner_tcp_hdrlen(skb) / 4) <<
3488 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3489 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3490
3491 return skb_inner_transport_header(skb) +
3492 inner_tcp_hdrlen(skb) - skb->data;
3493 }
3494
3495 /* We support checksum offload for TCP and UDP only.
3496 * No need to pass the UDP header length - it's a constant.
3497 */
3498 return skb_inner_transport_header(skb) +
3499 sizeof(struct udphdr) - skb->data;
3500}
3501
f2e0899f 3502/**
e8920674 3503 * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length
f2e0899f 3504 *
e8920674
DK		 3505 * @bp: driver handle
3506 * @skb: packet skb
3507 * @parsing_data: data to be updated
3508 * @xmit_type: xmit flags
f2e0899f 3509 *
91226790 3510 * 57712/578xx related
f2e0899f 3511 */
91226790
DK		 3512static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3513 u32 *parsing_data, u32 xmit_type)
f2e0899f 3514{
e39aece7 3515 *parsing_data |=
2de67439 3516 ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
91226790
DK		 3517 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
3518 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
f2e0899f 3519
e39aece7
VZ		 3520 if (xmit_type & XMIT_CSUM_TCP) {
3521 *parsing_data |= ((tcp_hdrlen(skb) / 4) <<
3522 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3523 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
f2e0899f 3524
e39aece7 3525 return skb_transport_header(skb) + tcp_hdrlen(skb) - skb->data;
924d75ab
YM		 3526 }
3527 /* We support checksum offload for TCP and UDP only.
3528 * No need to pass the UDP header length - it's a constant.
3529 */
3530 return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data;
f2e0899f
DK		 3531}
3532
a848ade4 3533/* set FW indication according to inner or outer protocols if tunneled */
91226790
DK		 3534static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3535 struct eth_tx_start_bd *tx_start_bd,
3536 u32 xmit_type)
93ef5c02 3537{
93ef5c02
DK		 3538 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
3539
a848ade4 3540 if (xmit_type & (XMIT_CSUM_ENC_V6 | XMIT_CSUM_V6))
91226790 3541 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
93ef5c02
DK		 3542
3543 if (!(xmit_type & XMIT_CSUM_TCP))
3544 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP;
93ef5c02
DK		 3545}
3546
f2e0899f 3547/**
e8920674 3548 * bnx2x_set_pbd_csum - update PBD with checksum and return header length
f2e0899f 3549 *
e8920674
DK		 3550 * @bp: driver handle
3551 * @skb: packet skb
3552 * @pbd: parse BD to be updated
3553 * @xmit_type: xmit flags
f2e0899f 3554 */
91226790
DK		 3555static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3556 struct eth_tx_parse_bd_e1x *pbd,
3557 u32 xmit_type)
f2e0899f 3558{
e39aece7 3559 u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
f2e0899f
DK		 3560
3561 /* for now NS flag is not used in Linux */
3562 pbd->global_data =
86564c3f
YM		 3563 cpu_to_le16(hlen |
3564 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3565 ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
f2e0899f
DK		 3566
3567 pbd->ip_hlen_w = (skb_transport_header(skb) -
e39aece7 3568 skb_network_header(skb)) >> 1;
f2e0899f 3569
e39aece7
VZ		 3570 hlen += pbd->ip_hlen_w;
3571
3572 /* We support checksum offload for TCP and UDP only */
3573 if (xmit_type & XMIT_CSUM_TCP)
3574 hlen += tcp_hdrlen(skb) / 2;
3575 else
3576 hlen += sizeof(struct udphdr) / 2;
f2e0899f
DK		 3577
3578 pbd->total_hlen_w = cpu_to_le16(hlen);
3579 hlen = hlen*2;
3580
3581 if (xmit_type & XMIT_CSUM_TCP) {
86564c3f 3582 pbd->tcp_pseudo_csum = bswab16(tcp_hdr(skb)->check);
f2e0899f
DK		 3583
3584 } else {
3585 s8 fix = SKB_CS_OFF(skb); /* signed! */
3586
3587 DP(NETIF_MSG_TX_QUEUED,
3588 "hlen %d fix %d csum before fix %x\n",
3589 le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb));
3590
3591 /* HW bug: fixup the CSUM */
3592 pbd->tcp_pseudo_csum =
3593 bnx2x_csum_fix(skb_transport_header(skb),
3594 SKB_CS(skb), fix);
3595
3596 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
3597 pbd->tcp_pseudo_csum);
3598 }
3599
3600 return hlen;
3601}
f85582f8 3602
a848ade4
DK		 3603static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
3604 struct eth_tx_parse_bd_e2 *pbd_e2,
3605 struct eth_tx_parse_2nd_bd *pbd2,
3606 u16 *global_data,
3607 u32 xmit_type)
3608{
e287a75c 3609 u16 hlen_w = 0;
a848ade4 3610 u8 outerip_off, outerip_len = 0;
e768fb29 3611
e287a75c
DK		 3612 /* from outer IP to transport */
3613 hlen_w = (skb_inner_transport_header(skb) -
3614 skb_network_header(skb)) >> 1;
a848ade4
DK		 3615
3616 /* transport len */
e768fb29 3617 hlen_w += inner_tcp_hdrlen(skb) >> 1;
a848ade4 3618
e287a75c 3619 pbd2->fw_ip_hdr_to_payload_w = hlen_w;
a848ade4 3620
e768fb29
DK		 3621 /* outer IP header info */
3622 if (xmit_type & XMIT_CSUM_V4) {
e287a75c 3623 struct iphdr *iph = ip_hdr(skb);
1b4fc0e2
DK		 3624 u32 csum = (__force u32)(~iph->check) -
3625 (__force u32)iph->tot_len -
3626 (__force u32)iph->frag_off;
c957d09f 3627
a848ade4 3628 pbd2->fw_ip_csum_wo_len_flags_frag =
c957d09f 3629 bswab16(csum_fold((__force __wsum)csum));
a848ade4
DK		 3630 } else {
3631 pbd2->fw_ip_hdr_to_payload_w =
e287a75c 3632 hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
a848ade4
DK		 3633 }
3634
3635 pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
3636
3637 pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb));
3638
3639 if (xmit_type & XMIT_GSO_V4) {
e287a75c 3640 pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id);
a848ade4
DK		 3641
3642 pbd_e2->data.tunnel_data.pseudo_csum =
3643 bswab16(~csum_tcpudp_magic(
3644 inner_ip_hdr(skb)->saddr,
3645 inner_ip_hdr(skb)->daddr,
3646 0, IPPROTO_TCP, 0));
3647
3648 outerip_len = ip_hdr(skb)->ihl << 1;
3649 } else {
3650 pbd_e2->data.tunnel_data.pseudo_csum =
3651 bswab16(~csum_ipv6_magic(
3652 &inner_ipv6_hdr(skb)->saddr,
3653 &inner_ipv6_hdr(skb)->daddr,
3654 0, IPPROTO_TCP, 0));
3655 }
3656
3657 outerip_off = (skb_network_header(skb) - skb->data) >> 1;
3658
3659 *global_data |=
3660 outerip_off |
3661 (!!(xmit_type & XMIT_CSUM_V6) <<
3662 ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT) |
3663 (outerip_len <<
3664 ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) |
3665 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3666 ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT);
65bc0cfe
DK		 3667
3668 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
3669 SET_FLAG(*global_data, ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST, 1);
3670 pbd2->tunnel_udp_hdr_start_w = skb_transport_offset(skb) >> 1;
3671 }
a848ade4
DK		 3672}
3673
9f6c9258
DK		 3674/* called with netif_tx_lock
3675 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
3676 * netif_wake_queue()
3677 */
3678netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3679{
3680 struct bnx2x *bp = netdev_priv(dev);
6383c0b3 3681
9f6c9258 3682 struct netdev_queue *txq;
6383c0b3 3683 struct bnx2x_fp_txdata *txdata;
9f6c9258 3684 struct sw_tx_bd *tx_buf;
619c5cb6 3685 struct eth_tx_start_bd *tx_start_bd, *first_bd;
9f6c9258 3686 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
523224a3 3687 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
f2e0899f 3688 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
a848ade4 3689 struct eth_tx_parse_2nd_bd *pbd2 = NULL;
2297a2da 3690 u32 pbd_e2_parsing_data = 0;
9f6c9258 3691 u16 pkt_prod, bd_prod;
65565884 3692 int nbd, txq_index;
9f6c9258
DK		 3693 dma_addr_t mapping;
3694 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3695 int i;
3696 u8 hlen = 0;
3697 __le16 pkt_size = 0;
3698 struct ethhdr *eth;
3699 u8 mac_type = UNICAST_ADDRESS;
3700
3701#ifdef BNX2X_STOP_ON_ERROR
3702 if (unlikely(bp->panic))
3703 return NETDEV_TX_BUSY;
3704#endif
3705
6383c0b3
AE		 3706 txq_index = skb_get_queue_mapping(skb);
3707 txq = netdev_get_tx_queue(dev, txq_index);
3708
55c11941 3709 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
6383c0b3 3710
65565884 3711 txdata = &bp->bnx2x_txq[txq_index];
6383c0b3
AE		 3712
3713 /* enable this debug print to view the transmission queue being used
51c1a580 3714 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
6383c0b3 3715 txq_index, fp_index, txdata_index); */
9f6c9258 3716
16a5fd92 3717 /* enable this debug print to view the transmission details
51c1a580
MS		 3718 DP(NETIF_MSG_TX_QUEUED,
3719 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
6383c0b3 3720 txdata->cid, fp_index, txdata_index, txdata, fp); */
9f6c9258 3721
6383c0b3 3722 if (unlikely(bnx2x_tx_avail(bp, txdata) <
7df2dc6b
DK		 3723 skb_shinfo(skb)->nr_frags +
3724 BDS_PER_TX_PKT +
3725 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) {
2384d6aa 3726 /* Handle special storage cases separately */
c96bdc0c
DK		 3727 if (txdata->tx_ring_size == 0) {
3728 struct bnx2x_eth_q_stats *q_stats =
3729 bnx2x_fp_qstats(bp, txdata->parent_fp);
3730 q_stats->driver_filtered_tx_pkt++;
3731 dev_kfree_skb(skb);
3732 return NETDEV_TX_OK;
3733 }
2de67439
YM		 3734 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3735 netif_tx_stop_queue(txq);
c96bdc0c 3736 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
2384d6aa 3737
9f6c9258
DK		 3738 return NETDEV_TX_BUSY;
3739 }
3740
51c1a580 3741 DP(NETIF_MSG_TX_QUEUED,
04c46736 3742 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x len %d\n",
6383c0b3 3743 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
04c46736
YM		 3744 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type,
3745 skb->len);
9f6c9258
DK		 3746
3747 eth = (struct ethhdr *)skb->data;
3748
3749 /* set flag according to packet type (UNICAST_ADDRESS is default)*/
3750 if (unlikely(is_multicast_ether_addr(eth->h_dest))) {
3751 if (is_broadcast_ether_addr(eth->h_dest))
3752 mac_type = BROADCAST_ADDRESS;
3753 else
3754 mac_type = MULTICAST_ADDRESS;
3755 }
3756
91226790 3757#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT)
9f6c9258
DK		 3758 /* First, check if we need to linearize the skb (due to FW
3759 restrictions). No need to check fragmentation if page size > 8K
3760 (there will be no violation to FW restrictions) */
3761 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3762 /* Statistics of linearization */
3763 bp->lin_cnt++;
3764 if (skb_linearize(skb) != 0) {
51c1a580
MS		 3765 DP(NETIF_MSG_TX_QUEUED,
3766 "SKB linearization failed - silently dropping this SKB\n");
9f6c9258
DK		 3767 dev_kfree_skb_any(skb);
3768 return NETDEV_TX_OK;
3769 }
3770 }
3771#endif
619c5cb6
VZ		 3772 /* Map skb linear data for DMA */
3773 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3774 skb_headlen(skb), DMA_TO_DEVICE);
3775 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
51c1a580
MS		 3776 DP(NETIF_MSG_TX_QUEUED,
3777 "SKB mapping failed - silently dropping this SKB\n");
619c5cb6
VZ		 3778 dev_kfree_skb_any(skb);
3779 return NETDEV_TX_OK;
3780 }
9f6c9258
DK		 3781 /*
3782 Please read carefully. First we use one BD which we mark as start,
3783 then we have a parsing info BD (used for TSO or xsum),
3784 and only then we have the rest of the TSO BDs.
3785 (don't forget to mark the last one as last,
3786 and to unmap only AFTER you write to the BD ...)
3787 And above all, all pdb sizes are in words - NOT DWORDS!
3788 */
3789
619c5cb6
VZ		 3790 /* get current pkt produced now - advance it just before sending packet
3791 * since mapping of pages may fail and cause packet to be dropped
3792 */
6383c0b3
AE		 3793 pkt_prod = txdata->tx_pkt_prod;
3794 bd_prod = TX_BD(txdata->tx_bd_prod);
9f6c9258 3795
619c5cb6
VZ		 3796 /* get a tx_buf and first BD
3797 * tx_start_bd may be changed during SPLIT,
3798 * but first_bd will always stay first
3799 */
6383c0b3
AE		 3800 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
3801 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
619c5cb6 3802 first_bd = tx_start_bd;
9f6c9258
DK		 3803
3804 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
f85582f8 3805
91226790
DK		 3806 /* header nbd: indirectly zero other flags! */
3807 tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT;
9f6c9258
DK		 3808
3809 /* remember the first BD of the packet */
6383c0b3 3810 tx_buf->first_bd = txdata->tx_bd_prod;
9f6c9258
DK		 3811 tx_buf->skb = skb;
3812 tx_buf->flags = 0;
3813
3814 DP(NETIF_MSG_TX_QUEUED,
3815 "sending pkt %u @%p next_idx %u bd %u @%p\n",
6383c0b3 3816 pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd);
9f6c9258 3817
eab6d18d 3818 if (vlan_tx_tag_present(skb)) {
523224a3
DK		 3819 tx_start_bd->vlan_or_ethertype =
3820 cpu_to_le16(vlan_tx_tag_get(skb));
3821 tx_start_bd->bd_flags.as_bitfield |=
3822 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
dc1ba591
AE		 3823 } else {
3824 /* when transmitting in a vf, start bd must hold the ethertype
3825 * for fw to enforce it
3826 */
91226790 3827 if (IS_VF(bp))
dc1ba591
AE		 3828 tx_start_bd->vlan_or_ethertype =
3829 cpu_to_le16(ntohs(eth->h_proto));
91226790 3830 else
dc1ba591
AE		 3831 /* used by FW for packet accounting */
3832 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
dc1ba591 3833 }
9f6c9258 3834
91226790
DK		 3835 nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
3836
9f6c9258
DK		 3837 /* turn on parsing and get a BD */
3838 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9f6c9258 3839
93ef5c02
DK		 3840 if (xmit_type & XMIT_CSUM)
3841 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
9f6c9258 3842
619c5cb6 3843 if (!CHIP_IS_E1x(bp)) {
6383c0b3 3844 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
f2e0899f 3845 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
a848ade4
DK		 3846
3847 if (xmit_type & XMIT_CSUM_ENC) {
3848 u16 global_data = 0;
3849
3850 /* Set PBD in enc checksum offload case */
3851 hlen = bnx2x_set_pbd_csum_enc(bp, skb,
3852 &pbd_e2_parsing_data,
3853 xmit_type);
3854
3855 /* turn on 2nd parsing and get a BD */
3856 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3857
3858 pbd2 = &txdata->tx_desc_ring[bd_prod].parse_2nd_bd;
3859
3860 memset(pbd2, 0, sizeof(*pbd2));
3861
3862 pbd_e2->data.tunnel_data.ip_hdr_start_inner_w =
3863 (skb_inner_network_header(skb) -
3864 skb->data) >> 1;
3865
3866 if (xmit_type & XMIT_GSO_ENC)
3867 bnx2x_update_pbds_gso_enc(skb, pbd_e2, pbd2,
3868 &global_data,
3869 xmit_type);
3870
3871 pbd2->global_data = cpu_to_le16(global_data);
3872
3873 /* add addition parse BD indication to start BD */
3874 SET_FLAG(tx_start_bd->general_data,
3875 ETH_TX_START_BD_PARSE_NBDS, 1);
3876 /* set encapsulation flag in start BD */
3877 SET_FLAG(tx_start_bd->general_data,
3878 ETH_TX_START_BD_TUNNEL_EXIST, 1);
3879 nbd++;
3880 } else if (xmit_type & XMIT_CSUM) {
91226790 3881 /* Set PBD in checksum offload case w/o encapsulation */
2297a2da
VZ		 3882 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3883 &pbd_e2_parsing_data,
3884 xmit_type);
a848ade4 3885 }
dc1ba591 3886
babe723d
YM		 3887 /* Add the macs to the parsing BD if this is a vf or if
3888 * Tx Switching is enabled.
3889 */
91226790
DK		 3890 if (IS_VF(bp)) {
3891 /* override GRE parameters in BD */
3892 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
3893 &pbd_e2->data.mac_addr.src_mid,
3894 &pbd_e2->data.mac_addr.src_lo,
619c5cb6 3895 eth->h_source);
91226790 3896
babe723d
YM		 3897 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
3898 &pbd_e2->data.mac_addr.dst_mid,
3899 &pbd_e2->data.mac_addr.dst_lo,
3900 eth->h_dest);
3901 } else if (bp->flags & TX_SWITCHING) {
91226790
DK		 3902 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
3903 &pbd_e2->data.mac_addr.dst_mid,
3904 &pbd_e2->data.mac_addr.dst_lo,
619c5cb6
VZ		 3905 eth->h_dest);
3906 }
96bed4b9
YM		 3907
3908 SET_FLAG(pbd_e2_parsing_data,
3909 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
f2e0899f 3910 } else {
96bed4b9 3911 u16 global_data = 0;
6383c0b3 3912 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
f2e0899f
DK		 3913 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
3914 /* Set PBD in checksum offload case */
3915 if (xmit_type & XMIT_CSUM)
3916 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
9f6c9258 3917
96bed4b9
YM		 3918 SET_FLAG(global_data,
3919 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
3920 pbd_e1x->global_data |= cpu_to_le16(global_data);
9f6c9258
DK		 3921 }
3922
f85582f8 3923 /* Setup the data pointer of the first BD of the packet */
9f6c9258
DK		 3924 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3925 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9f6c9258
DK		 3926 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
3927 pkt_size = tx_start_bd->nbytes;
3928
51c1a580 3929 DP(NETIF_MSG_TX_QUEUED,
91226790 3930 "first bd @%p addr (%x:%x) nbytes %d flags %x vlan %x\n",
9f6c9258 3931 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
91226790 3932 le16_to_cpu(tx_start_bd->nbytes),
523224a3
DK		 3933 tx_start_bd->bd_flags.as_bitfield,
3934 le16_to_cpu(tx_start_bd->vlan_or_ethertype));
9f6c9258
DK		 3935
3936 if (xmit_type & XMIT_GSO) {
3937
3938 DP(NETIF_MSG_TX_QUEUED,
3939 "TSO packet len %d hlen %d total len %d tso size %d\n",
3940 skb->len, hlen, skb_headlen(skb),
3941 skb_shinfo(skb)->gso_size);
3942
3943 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
3944
91226790
DK		 3945 if (unlikely(skb_headlen(skb) > hlen)) {
3946 nbd++;
6383c0b3
AE		 3947 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
3948 &tx_start_bd, hlen,
91226790
DK		 3949 bd_prod);
3950 }
619c5cb6 3951 if (!CHIP_IS_E1x(bp))
2297a2da
VZ		 3952 bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
3953 xmit_type);
f2e0899f 3954 else
44dbc78e 3955 bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type);
9f6c9258 3956 }
2297a2da
VZ		 3957
3958 /* Set the PBD's parsing_data field if not zero
3959 * (for the chips newer than 57711).
3960 */
3961 if (pbd_e2_parsing_data)
3962 pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data);
3963
9f6c9258
DK		 3964 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
3965
f85582f8 3966 /* Handle fragmented skb */
9f6c9258
DK		 3967 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3968 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3969
9e903e08
ED		 3970 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
3971 skb_frag_size(frag), DMA_TO_DEVICE);
619c5cb6 3972 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2df1a70a 3973 unsigned int pkts_compl = 0, bytes_compl = 0;
619c5cb6 3974
51c1a580
MS		 3975 DP(NETIF_MSG_TX_QUEUED,
3976 "Unable to map page - dropping packet...\n");
619c5cb6
VZ		 3977
3978 /* we need unmap all buffers already mapped
3979 * for this SKB;
3980 * first_bd->nbd need to be properly updated
3981 * before call to bnx2x_free_tx_pkt
3982 */
3983 first_bd->nbd = cpu_to_le16(nbd);
6383c0b3 3984 bnx2x_free_tx_pkt(bp, txdata,
2df1a70a
TH		 3985 TX_BD(txdata->tx_pkt_prod),
3986 &pkts_compl, &bytes_compl);
619c5cb6
VZ		 3987 return NETDEV_TX_OK;
3988 }
3989
9f6c9258 3990 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
6383c0b3 3991 tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
9f6c9258 3992 if (total_pkt_bd == NULL)
6383c0b3 3993 total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
9f6c9258 3994
9f6c9258
DK		 3995 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3996 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9e903e08
ED		 3997 tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag));
3998 le16_add_cpu(&pkt_size, skb_frag_size(frag));
619c5cb6 3999 nbd++;
9f6c9258
DK		 4000
4001 DP(NETIF_MSG_TX_QUEUED,
4002 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
4003 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
4004 le16_to_cpu(tx_data_bd->nbytes));
4005 }
4006
4007 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
4008
619c5cb6
VZ		 4009 /* update with actual num BDs */
4010 first_bd->nbd = cpu_to_le16(nbd);
4011
9f6c9258
DK		 4012 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
4013
4014 /* now send a tx doorbell, counting the next BD
4015 * if the packet contains or ends with it
4016 */
4017 if (TX_BD_POFF(bd_prod) < nbd)
4018 nbd++;
4019
619c5cb6
VZ		 4020 /* total_pkt_bytes should be set on the first data BD if
4021 * it's not an LSO packet and there is more than one
4022 * data BD. In this case pkt_size is limited by an MTU value.
4023 * However we prefer to set it for an LSO packet (while we don't
4024 * have to) in order to save some CPU cycles in a none-LSO
4025 * case, when we much more care about them.
4026 */
9f6c9258
DK		 4027 if (total_pkt_bd != NULL)
4028 total_pkt_bd->total_pkt_bytes = pkt_size;
4029
523224a3 4030 if (pbd_e1x)
9f6c9258 4031 DP(NETIF_MSG_TX_QUEUED,
51c1a580 4032 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
523224a3
DK		 4033 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
4034 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
4035 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
4036 le16_to_cpu(pbd_e1x->total_hlen_w));
f2e0899f
DK		 4037 if (pbd_e2)
4038 DP(NETIF_MSG_TX_QUEUED,
4039 "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n",
91226790
DK		 4040 pbd_e2,
4041 pbd_e2->data.mac_addr.dst_hi,
4042 pbd_e2->data.mac_addr.dst_mid,
4043 pbd_e2->data.mac_addr.dst_lo,
4044 pbd_e2->data.mac_addr.src_hi,
4045 pbd_e2->data.mac_addr.src_mid,
4046 pbd_e2->data.mac_addr.src_lo,
f2e0899f 4047 pbd_e2->parsing_data);
9f6c9258
DK		 4048 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
4049
2df1a70a
TH		 4050 netdev_tx_sent_queue(txq, skb->len);
4051
8373c57d
WB		 4052 skb_tx_timestamp(skb);
4053
6383c0b3 4054 txdata->tx_pkt_prod++;
9f6c9258
DK		 4055 /*
4056 * Make sure that the BD data is updated before updating the producer
4057 * since FW might read the BD right after the producer is updated.
4058 * This is only applicable for weak-ordered memory model archs such
4059 * as IA-64. The following barrier is also mandatory since FW will
4060 * assumes packets must have BDs.
4061 */
4062 wmb();
4063
6383c0b3 4064 txdata->tx_db.data.prod += nbd;
9f6c9258 4065 barrier();
f85582f8 4066
6383c0b3 4067 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
9f6c9258
DK		 4068
4069 mmiowb();
4070
6383c0b3 4071 txdata->tx_bd_prod += nbd;
9f6c9258 4072
7df2dc6b 4073 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
9f6c9258
DK		 4074 netif_tx_stop_queue(txq);
4075
4076 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
4077 * ordering of set_bit() in netif_tx_stop_queue() and read of
4078 * fp->bd_tx_cons */
4079 smp_mb();
4080
15192a8c 4081 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
7df2dc6b 4082 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
9f6c9258
DK		 4083 netif_tx_wake_queue(txq);
4084 }
6383c0b3 4085 txdata->tx_pkt++;
9f6c9258
DK		 4086
4087 return NETDEV_TX_OK;
4088}
f85582f8 4089
6383c0b3
AE		 4090/**
4091 * bnx2x_setup_tc - routine to configure net_device for multi tc
4092 *
4093 * @netdev: net device to configure
4094 * @tc: number of traffic classes to enable
4095 *
4096 * callback connected to the ndo_setup_tc function pointer
4097 */
4098int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
4099{
4100 int cos, prio, count, offset;
4101 struct bnx2x *bp = netdev_priv(dev);
4102
4103 /* setup tc must be called under rtnl lock */
4104 ASSERT_RTNL();
4105
16a5fd92 4106 /* no traffic classes requested. Aborting */
6383c0b3
AE		 4107 if (!num_tc) {
4108 netdev_reset_tc(dev);
4109 return 0;
4110 }
4111
4112 /* requested to support too many traffic classes */
4113 if (num_tc > bp->max_cos) {
6bf07b8e 4114 BNX2X_ERR("support for too many traffic classes requested: %d. Max supported is %d\n",
51c1a580 4115 num_tc, bp->max_cos);
6383c0b3
AE		 4116 return -EINVAL;
4117 }
4118
4119 /* declare amount of supported traffic classes */
4120 if (netdev_set_num_tc(dev, num_tc)) {
51c1a580 4121 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
6383c0b3
AE		 4122 return -EINVAL;
4123 }
4124
4125 /* configure priority to traffic class mapping */
4126 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
4127 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
51c1a580
MS		 4128 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4129 "mapping priority %d to tc %d\n",
6383c0b3
AE		 4130 prio, bp->prio_to_cos[prio]);
4131 }
4132
16a5fd92 4133 /* Use this configuration to differentiate tc0 from other COSes
6383c0b3
AE		 4134 This can be used for ets or pfc, and save the effort of setting
4135 up a multio class queue disc or negotiating DCBX with a switch
4136 netdev_set_prio_tc_map(dev, 0, 0);
94f05b0f 4137 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0);
6383c0b3
AE		 4138 for (prio = 1; prio < 16; prio++) {
4139 netdev_set_prio_tc_map(dev, prio, 1);
94f05b0f 4140 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1);
6383c0b3
AE		 4141 } */
4142
4143 /* configure traffic class to transmission queue mapping */
4144 for (cos = 0; cos < bp->max_cos; cos++) {
4145 count = BNX2X_NUM_ETH_QUEUES(bp);
65565884 4146 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
6383c0b3 4147 netdev_set_tc_queue(dev, cos, count, offset);
51c1a580
MS		 4148 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4149 "mapping tc %d to offset %d count %d\n",
6383c0b3
AE		 4150 cos, offset, count);
4151 }
4152
4153 return 0;
4154}
4155
9f6c9258
DK		 4156/* called with rtnl_lock */
4157int bnx2x_change_mac_addr(struct net_device *dev, void *p)
4158{
4159 struct sockaddr *addr = p;
4160 struct bnx2x *bp = netdev_priv(dev);
619c5cb6 4161 int rc = 0;
9f6c9258 4162
51c1a580
MS		 4163 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) {
4164 BNX2X_ERR("Requested MAC address is not valid\n");
614c76df 4165 return -EINVAL;
51c1a580 4166 }
614c76df 4167
a3348722
BW		 4168 if ((IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)) &&
4169 !is_zero_ether_addr(addr->sa_data)) {
51c1a580 4170 BNX2X_ERR("Can't configure non-zero address on iSCSI or FCoE functions in MF-SD mode\n");
9f6c9258 4171 return -EINVAL;
51c1a580 4172 }
9f6c9258 4173
619c5cb6
VZ		 4174 if (netif_running(dev)) {
4175 rc = bnx2x_set_eth_mac(bp, false);
4176 if (rc)
4177 return rc;
4178 }
4179
9f6c9258 4180 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
619c5cb6 4181
523224a3 4182 if (netif_running(dev))
619c5cb6 4183 rc = bnx2x_set_eth_mac(bp, true);
9f6c9258 4184
619c5cb6 4185 return rc;
9f6c9258
DK		 4186}
4187
b3b83c3f
DK		 4188static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
4189{
4190 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
4191 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
6383c0b3 4192 u8 cos;
b3b83c3f
DK		 4193
4194 /* Common */
55c11941 4195
b3b83c3f
DK		 4196 if (IS_FCOE_IDX(fp_index)) {
4197 memset(sb, 0, sizeof(union host_hc_status_block));
4198 fp->status_blk_mapping = 0;
b3b83c3f 4199 } else {
b3b83c3f 4200 /* status blocks */
619c5cb6 4201 if (!CHIP_IS_E1x(bp))
b3b83c3f
DK		 4202 BNX2X_PCI_FREE(sb->e2_sb,
4203 bnx2x_fp(bp, fp_index,
4204 status_blk_mapping),
4205 sizeof(struct host_hc_status_block_e2));
4206 else
4207 BNX2X_PCI_FREE(sb->e1x_sb,
4208 bnx2x_fp(bp, fp_index,
4209 status_blk_mapping),
4210 sizeof(struct host_hc_status_block_e1x));
b3b83c3f 4211 }
55c11941 4212
b3b83c3f
DK		 4213 /* Rx */
4214 if (!skip_rx_queue(bp, fp_index)) {
4215 bnx2x_free_rx_bds(fp);
4216
4217 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4218 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
4219 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
4220 bnx2x_fp(bp, fp_index, rx_desc_mapping),
4221 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4222
4223 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
4224 bnx2x_fp(bp, fp_index, rx_comp_mapping),
4225 sizeof(struct eth_fast_path_rx_cqe) *
4226 NUM_RCQ_BD);
4227
4228 /* SGE ring */
4229 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
4230 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
4231 bnx2x_fp(bp, fp_index, rx_sge_mapping),
4232 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4233 }
4234
4235 /* Tx */
4236 if (!skip_tx_queue(bp, fp_index)) {
4237 /* fastpath tx rings: tx_buf tx_desc */
6383c0b3 4238 for_each_cos_in_tx_queue(fp, cos) {
65565884 4239 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 4240
51c1a580 4241 DP(NETIF_MSG_IFDOWN,
94f05b0f 4242 "freeing tx memory of fp %d cos %d cid %d\n",
6383c0b3
AE		 4243 fp_index, cos, txdata->cid);
4244
4245 BNX2X_FREE(txdata->tx_buf_ring);
4246 BNX2X_PCI_FREE(txdata->tx_desc_ring,
4247 txdata->tx_desc_mapping,
4248 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4249 }
b3b83c3f
DK		 4250 }
4251 /* end of fastpath */
4252}
4253
a8f47eb7 4254static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
55c11941
MS		 4255{
4256 int i;
4257 for_each_cnic_queue(bp, i)
4258 bnx2x_free_fp_mem_at(bp, i);
4259}
4260
b3b83c3f
DK		 4261void bnx2x_free_fp_mem(struct bnx2x *bp)
4262{
4263 int i;
55c11941 4264 for_each_eth_queue(bp, i)
b3b83c3f
DK		 4265 bnx2x_free_fp_mem_at(bp, i);
4266}
4267
1191cb83 4268static void set_sb_shortcuts(struct bnx2x *bp, int index)
b3b83c3f
DK		 4269{
4270 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
619c5cb6 4271 if (!CHIP_IS_E1x(bp)) {
b3b83c3f
DK		 4272 bnx2x_fp(bp, index, sb_index_values) =
4273 (__le16 *)status_blk.e2_sb->sb.index_values;
4274 bnx2x_fp(bp, index, sb_running_index) =
4275 (__le16 *)status_blk.e2_sb->sb.running_index;
4276 } else {
4277 bnx2x_fp(bp, index, sb_index_values) =
4278 (__le16 *)status_blk.e1x_sb->sb.index_values;
4279 bnx2x_fp(bp, index, sb_running_index) =
4280 (__le16 *)status_blk.e1x_sb->sb.running_index;
4281 }
4282}
4283
1191cb83
ED		 4284/* Returns the number of actually allocated BDs */
4285static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
4286 int rx_ring_size)
4287{
4288 struct bnx2x *bp = fp->bp;
4289 u16 ring_prod, cqe_ring_prod;
4290 int i, failure_cnt = 0;
4291
4292 fp->rx_comp_cons = 0;
4293 cqe_ring_prod = ring_prod = 0;
4294
4295 /* This routine is called only during fo init so
4296 * fp->eth_q_stats.rx_skb_alloc_failed = 0
4297 */
4298 for (i = 0; i < rx_ring_size; i++) {
996dedba 4299 if (bnx2x_alloc_rx_data(bp, fp, ring_prod, GFP_KERNEL) < 0) {
1191cb83
ED		 4300 failure_cnt++;
4301 continue;
4302 }
4303 ring_prod = NEXT_RX_IDX(ring_prod);
4304 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4305 WARN_ON(ring_prod <= (i - failure_cnt));
4306 }
4307
4308 if (failure_cnt)
4309 BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
4310 i - failure_cnt, fp->index);
4311
4312 fp->rx_bd_prod = ring_prod;
4313 /* Limit the CQE producer by the CQE ring size */
4314 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
4315 cqe_ring_prod);
4316 fp->rx_pkt = fp->rx_calls = 0;
4317
15192a8c 4318 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
1191cb83
ED		 4319
4320 return i - failure_cnt;
4321}
4322
4323static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
4324{
4325 int i;
4326
4327 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4328 struct eth_rx_cqe_next_page *nextpg;
4329
4330 nextpg = (struct eth_rx_cqe_next_page *)
4331 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4332 nextpg->addr_hi =
4333 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4334 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4335 nextpg->addr_lo =
4336 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4337 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4338 }
4339}
4340
b3b83c3f
DK		 4341static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
4342{
4343 union host_hc_status_block *sb;
4344 struct bnx2x_fastpath *fp = &bp->fp[index];
4345 int ring_size = 0;
6383c0b3 4346 u8 cos;
c2188952 4347 int rx_ring_size = 0;
b3b83c3f 4348
a3348722
BW		 4349 if (!bp->rx_ring_size &&
4350 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
614c76df
DK		 4351 rx_ring_size = MIN_RX_SIZE_NONTPA;
4352 bp->rx_ring_size = rx_ring_size;
55c11941 4353 } else if (!bp->rx_ring_size) {
c2188952
VZ		 4354 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
4355
065f8b92
YM		 4356 if (CHIP_IS_E3(bp)) {
4357 u32 cfg = SHMEM_RD(bp,
4358 dev_info.port_hw_config[BP_PORT(bp)].
4359 default_cfg);
4360
4361 /* Decrease ring size for 1G functions */
4362 if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
4363 PORT_HW_CFG_NET_SERDES_IF_SGMII)
4364 rx_ring_size /= 10;
4365 }
d760fc37 4366
c2188952
VZ		 4367 /* allocate at least number of buffers required by FW */
4368 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4369 MIN_RX_SIZE_TPA, rx_ring_size);
4370
4371 bp->rx_ring_size = rx_ring_size;
614c76df 4372 } else /* if rx_ring_size specified - use it */
c2188952 4373 rx_ring_size = bp->rx_ring_size;
b3b83c3f 4374
04c46736
YM		 4375 DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size);
4376
b3b83c3f
DK		 4377 /* Common */
4378 sb = &bnx2x_fp(bp, index, status_blk);
55c11941 4379
b3b83c3f 4380 if (!IS_FCOE_IDX(index)) {
b3b83c3f 4381 /* status blocks */
cd2b0389
JP		 4382 if (!CHIP_IS_E1x(bp)) {
4383 sb->e2_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4384 sizeof(struct host_hc_status_block_e2));
4385 if (!sb->e2_sb)
4386 goto alloc_mem_err;
4387 } else {
4388 sb->e1x_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4389 sizeof(struct host_hc_status_block_e1x));
4390 if (!sb->e1x_sb)
4391 goto alloc_mem_err;
4392 }
b3b83c3f 4393 }
8eef2af1
DK		 4394
4395 /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to
4396 * set shortcuts for it.
4397 */
4398 if (!IS_FCOE_IDX(index))
4399 set_sb_shortcuts(bp, index);
b3b83c3f
DK		 4400
4401 /* Tx */
4402 if (!skip_tx_queue(bp, index)) {
4403 /* fastpath tx rings: tx_buf tx_desc */
6383c0b3 4404 for_each_cos_in_tx_queue(fp, cos) {
65565884 4405 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 4406
51c1a580
MS		 4407 DP(NETIF_MSG_IFUP,
4408 "allocating tx memory of fp %d cos %d\n",
6383c0b3
AE		 4409 index, cos);
4410
cd2b0389
JP		 4411 txdata->tx_buf_ring = kcalloc(NUM_TX_BD,
4412 sizeof(struct sw_tx_bd),
4413 GFP_KERNEL);
4414 if (!txdata->tx_buf_ring)
4415 goto alloc_mem_err;
4416 txdata->tx_desc_ring = BNX2X_PCI_ALLOC(&txdata->tx_desc_mapping,
4417 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4418 if (!txdata->tx_desc_ring)
4419 goto alloc_mem_err;
6383c0b3 4420 }
b3b83c3f
DK		 4421 }
4422
4423 /* Rx */
4424 if (!skip_rx_queue(bp, index)) {
4425 /* fastpath rx rings: rx_buf rx_desc rx_comp */
cd2b0389
JP		 4426 bnx2x_fp(bp, index, rx_buf_ring) =
4427 kcalloc(NUM_RX_BD, sizeof(struct sw_rx_bd), GFP_KERNEL);
4428 if (!bnx2x_fp(bp, index, rx_buf_ring))
4429 goto alloc_mem_err;
4430 bnx2x_fp(bp, index, rx_desc_ring) =
4431 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_desc_mapping),
4432 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4433 if (!bnx2x_fp(bp, index, rx_desc_ring))
4434 goto alloc_mem_err;
b3b83c3f 4435
75b29459 4436 /* Seed all CQEs by 1s */
cd2b0389
JP		 4437 bnx2x_fp(bp, index, rx_comp_ring) =
4438 BNX2X_PCI_FALLOC(&bnx2x_fp(bp, index, rx_comp_mapping),
4439 sizeof(struct eth_fast_path_rx_cqe) * NUM_RCQ_BD);
4440 if (!bnx2x_fp(bp, index, rx_comp_ring))
4441 goto alloc_mem_err;
b3b83c3f
DK		 4442
4443 /* SGE ring */
cd2b0389
JP		 4444 bnx2x_fp(bp, index, rx_page_ring) =
4445 kcalloc(NUM_RX_SGE, sizeof(struct sw_rx_page),
4446 GFP_KERNEL);
4447 if (!bnx2x_fp(bp, index, rx_page_ring))
4448 goto alloc_mem_err;
4449 bnx2x_fp(bp, index, rx_sge_ring) =
4450 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_sge_mapping),
4451 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4452 if (!bnx2x_fp(bp, index, rx_sge_ring))
4453 goto alloc_mem_err;
b3b83c3f
DK		 4454 /* RX BD ring */
4455 bnx2x_set_next_page_rx_bd(fp);
4456
4457 /* CQ ring */
4458 bnx2x_set_next_page_rx_cq(fp);
4459
4460 /* BDs */
4461 ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size);
4462 if (ring_size < rx_ring_size)
4463 goto alloc_mem_err;
4464 }
4465
4466 return 0;
4467
4468/* handles low memory cases */
4469alloc_mem_err:
4470 BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n",
4471 index, ring_size);
4472 /* FW will drop all packets if queue is not big enough,
4473 * In these cases we disable the queue
6383c0b3 4474 * Min size is different for OOO, TPA and non-TPA queues
b3b83c3f
DK		 4475 */
4476 if (ring_size < (fp->disable_tpa ?
eb722d7a 4477 MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) {
b3b83c3f
DK		 4478 /* release memory allocated for this queue */
4479 bnx2x_free_fp_mem_at(bp, index);
4480 return -ENOMEM;
4481 }
4482 return 0;
4483}
4484
a8f47eb7 4485static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
55c11941
MS		 4486{
4487 if (!NO_FCOE(bp))
4488 /* FCoE */
4489 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4490 /* we will fail load process instead of mark
4491 * NO_FCOE_FLAG
4492 */
4493 return -ENOMEM;
4494
4495 return 0;
4496}
4497
a8f47eb7 4498static int bnx2x_alloc_fp_mem(struct bnx2x *bp)
b3b83c3f
DK		 4499{
4500 int i;
4501
55c11941
MS		 4502 /* 1. Allocate FP for leading - fatal if error
4503 * 2. Allocate RSS - fix number of queues if error
b3b83c3f
DK		 4504 */
4505
4506 /* leading */
4507 if (bnx2x_alloc_fp_mem_at(bp, 0))
4508 return -ENOMEM;
6383c0b3 4509
b3b83c3f
DK		 4510 /* RSS */
4511 for_each_nondefault_eth_queue(bp, i)
4512 if (bnx2x_alloc_fp_mem_at(bp, i))
4513 break;
4514
4515 /* handle memory failures */
4516 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4517 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4518
4519 WARN_ON(delta < 0);
4864a16a 4520 bnx2x_shrink_eth_fp(bp, delta);
55c11941
MS		 4521 if (CNIC_SUPPORT(bp))
4522 /* move non eth FPs next to last eth FP
4523 * must be done in that order
4524 * FCOE_IDX < FWD_IDX < OOO_IDX
4525 */
b3b83c3f 4526
55c11941
MS		 4527 /* move FCoE fp even NO_FCOE_FLAG is on */
4528 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4529 bp->num_ethernet_queues -= delta;
4530 bp->num_queues = bp->num_ethernet_queues +
4531 bp->num_cnic_queues;
b3b83c3f
DK		 4532 BNX2X_ERR("Adjusted num of queues from %d to %d\n",
4533 bp->num_queues + delta, bp->num_queues);
4534 }
4535
4536 return 0;
4537}
d6214d7a 4538
523224a3
DK		 4539void bnx2x_free_mem_bp(struct bnx2x *bp)
4540{
c3146eb6
DK		 4541 int i;
4542
4543 for (i = 0; i < bp->fp_array_size; i++)
4544 kfree(bp->fp[i].tpa_info);
523224a3 4545 kfree(bp->fp);
15192a8c
BW		 4546 kfree(bp->sp_objs);
4547 kfree(bp->fp_stats);
65565884 4548 kfree(bp->bnx2x_txq);
523224a3
DK		 4549 kfree(bp->msix_table);
4550 kfree(bp->ilt);
4551}
4552
0329aba1 4553int bnx2x_alloc_mem_bp(struct bnx2x *bp)
523224a3
DK		 4554{
4555 struct bnx2x_fastpath *fp;
4556 struct msix_entry *tbl;
4557 struct bnx2x_ilt *ilt;
6383c0b3 4558 int msix_table_size = 0;
55c11941 4559 int fp_array_size, txq_array_size;
15192a8c 4560 int i;
6383c0b3
AE		 4561
4562 /*
4563 * The biggest MSI-X table we might need is as a maximum number of fast
2de67439 4564 * path IGU SBs plus default SB (for PF only).
6383c0b3 4565 */
1ab4434c
AE		 4566 msix_table_size = bp->igu_sb_cnt;
4567 if (IS_PF(bp))
4568 msix_table_size++;
4569 BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size);
523224a3 4570
6383c0b3 4571 /* fp array: RSS plus CNIC related L2 queues */
55c11941 4572 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
c3146eb6
DK		 4573 bp->fp_array_size = fp_array_size;
4574 BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size);
15192a8c 4575
c3146eb6 4576 fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL);
523224a3
DK		 4577 if (!fp)
4578 goto alloc_err;
c3146eb6 4579 for (i = 0; i < bp->fp_array_size; i++) {
15192a8c
BW		 4580 fp[i].tpa_info =
4581 kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2,
4582 sizeof(struct bnx2x_agg_info), GFP_KERNEL);
4583 if (!(fp[i].tpa_info))
4584 goto alloc_err;
4585 }
4586
523224a3
DK		 4587 bp->fp = fp;
4588
15192a8c 4589 /* allocate sp objs */
c3146eb6 4590 bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs),
15192a8c
BW		 4591 GFP_KERNEL);
4592 if (!bp->sp_objs)
4593 goto alloc_err;
4594
4595 /* allocate fp_stats */
c3146eb6 4596 bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats),
15192a8c
BW		 4597 GFP_KERNEL);
4598 if (!bp->fp_stats)
4599 goto alloc_err;
4600
65565884 4601 /* Allocate memory for the transmission queues array */
55c11941
MS		 4602 txq_array_size =
4603 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4604 BNX2X_DEV_INFO("txq_array_size %d", txq_array_size);
4605
4606 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4607 GFP_KERNEL);
65565884
MS		 4608 if (!bp->bnx2x_txq)
4609 goto alloc_err;
4610
523224a3 4611 /* msix table */
01e23742 4612 tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL);
523224a3
DK		 4613 if (!tbl)
4614 goto alloc_err;
4615 bp->msix_table = tbl;
4616
4617 /* ilt */
4618 ilt = kzalloc(sizeof(*ilt), GFP_KERNEL);
4619 if (!ilt)
4620 goto alloc_err;
4621 bp->ilt = ilt;
4622
4623 return 0;
4624alloc_err:
4625 bnx2x_free_mem_bp(bp);
4626 return -ENOMEM;
523224a3
DK		 4627}
4628
a9fccec7 4629int bnx2x_reload_if_running(struct net_device *dev)
66371c44
MM		 4630{
4631 struct bnx2x *bp = netdev_priv(dev);
4632
4633 if (unlikely(!netif_running(dev)))
4634 return 0;
4635
5d07d868 4636 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
66371c44
MM		 4637 return bnx2x_nic_load(bp, LOAD_NORMAL);
4638}
4639
1ac9e428
YR		 4640int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4641{
4642 u32 sel_phy_idx = 0;
4643 if (bp->link_params.num_phys <= 1)
4644 return INT_PHY;
4645
4646 if (bp->link_vars.link_up) {
4647 sel_phy_idx = EXT_PHY1;
4648 /* In case link is SERDES, check if the EXT_PHY2 is the one */
4649 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4650 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4651 sel_phy_idx = EXT_PHY2;
4652 } else {
4653
4654 switch (bnx2x_phy_selection(&bp->link_params)) {
4655 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4656 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
4657 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4658 sel_phy_idx = EXT_PHY1;
4659 break;
4660 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
4661 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4662 sel_phy_idx = EXT_PHY2;
4663 break;
4664 }
4665 }
4666
4667 return sel_phy_idx;
1ac9e428
YR		 4668}
4669int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4670{
4671 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4672 /*
2de67439 4673 * The selected activated PHY is always after swapping (in case PHY
1ac9e428
YR		 4674 * swapping is enabled). So when swapping is enabled, we need to reverse
4675 * the configuration
4676 */
4677
4678 if (bp->link_params.multi_phy_config &
4679 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
4680 if (sel_phy_idx == EXT_PHY1)
4681 sel_phy_idx = EXT_PHY2;
4682 else if (sel_phy_idx == EXT_PHY2)
4683 sel_phy_idx = EXT_PHY1;
4684 }
4685 return LINK_CONFIG_IDX(sel_phy_idx);
4686}
4687
55c11941 4688#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 4689int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
4690{
4691 struct bnx2x *bp = netdev_priv(dev);
4692 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4693
4694 switch (type) {
4695 case NETDEV_FCOE_WWNN:
4696 *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi,
4697 cp->fcoe_wwn_node_name_lo);
4698 break;
4699 case NETDEV_FCOE_WWPN:
4700 *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi,
4701 cp->fcoe_wwn_port_name_lo);
4702 break;
4703 default:
51c1a580 4704 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
bf61ee14
VZ		 4705 return -EINVAL;
4706 }
4707
4708 return 0;
4709}
4710#endif
4711
9f6c9258
DK		 4712/* called with rtnl_lock */
4713int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
4714{
4715 struct bnx2x *bp = netdev_priv(dev);
9f6c9258
DK		 4716
4717 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 4718 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
9f6c9258
DK		 4719 return -EAGAIN;
4720 }
4721
4722 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
51c1a580
MS		 4723 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) {
4724 BNX2X_ERR("Can't support requested MTU size\n");
9f6c9258 4725 return -EINVAL;
51c1a580 4726 }
9f6c9258
DK		 4727
4728 /* This does not race with packet allocation
4729 * because the actual alloc size is
4730 * only updated as part of load
4731 */
4732 dev->mtu = new_mtu;
4733
66371c44
MM		 4734 return bnx2x_reload_if_running(dev);
4735}
4736
c8f44aff 4737netdev_features_t bnx2x_fix_features(struct net_device *dev,
621b4d66 4738 netdev_features_t features)
66371c44
MM		 4739{
4740 struct bnx2x *bp = netdev_priv(dev);
4741
4742 /* TPA requires Rx CSUM offloading */
621b4d66 4743 if (!(features & NETIF_F_RXCSUM) || bp->disable_tpa) {
66371c44 4744 features &= ~NETIF_F_LRO;
621b4d66
DK		 4745 features &= ~NETIF_F_GRO;
4746 }
66371c44
MM		 4747
4748 return features;
4749}
4750
c8f44aff 4751int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
66371c44
MM		 4752{
4753 struct bnx2x *bp = netdev_priv(dev);
4754 u32 flags = bp->flags;
8802f579 4755 u32 changes;
538dd2e3 4756 bool bnx2x_reload = false;
66371c44
MM		 4757
4758 if (features & NETIF_F_LRO)
4759 flags |= TPA_ENABLE_FLAG;
4760 else
4761 flags &= ~TPA_ENABLE_FLAG;
4762
621b4d66
DK		 4763 if (features & NETIF_F_GRO)
4764 flags |= GRO_ENABLE_FLAG;
4765 else
4766 flags &= ~GRO_ENABLE_FLAG;
4767
538dd2e3
MB		 4768 if (features & NETIF_F_LOOPBACK) {
4769 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4770 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4771 bnx2x_reload = true;
4772 }
4773 } else {
4774 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4775 bp->link_params.loopback_mode = LOOPBACK_NONE;
4776 bnx2x_reload = true;
4777 }
4778 }
4779
8802f579
ED		 4780 changes = flags ^ bp->flags;
4781
16a5fd92 4782 /* if GRO is changed while LRO is enabled, don't force a reload */
8802f579
ED		 4783 if ((changes & GRO_ENABLE_FLAG) && (flags & TPA_ENABLE_FLAG))
4784 changes &= ~GRO_ENABLE_FLAG;
4785
4786 if (changes)
538dd2e3 4787 bnx2x_reload = true;
8802f579
ED		 4788
4789 bp->flags = flags;
66371c44 4790
538dd2e3 4791 if (bnx2x_reload) {
66371c44
MM		 4792 if (bp->recovery_state == BNX2X_RECOVERY_DONE)
4793 return bnx2x_reload_if_running(dev);
4794 /* else: bnx2x_nic_load() will be called at end of recovery */
9f6c9258
DK		 4795 }
4796
66371c44 4797 return 0;
9f6c9258
DK		 4798}
4799
4800void bnx2x_tx_timeout(struct net_device *dev)
4801{
4802 struct bnx2x *bp = netdev_priv(dev);
4803
4804#ifdef BNX2X_STOP_ON_ERROR
4805 if (!bp->panic)
4806 bnx2x_panic();
4807#endif
7be08a72 4808
9f6c9258 4809 /* This allows the netif to be shutdown gracefully before resetting */
230bb0f3 4810 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_TX_TIMEOUT, 0);
9f6c9258
DK		 4811}
4812
9f6c9258
DK		 4813int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
4814{
4815 struct net_device *dev = pci_get_drvdata(pdev);
4816 struct bnx2x *bp;
4817
4818 if (!dev) {
4819 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4820 return -ENODEV;
4821 }
4822 bp = netdev_priv(dev);
4823
4824 rtnl_lock();
4825
4826 pci_save_state(pdev);
4827
4828 if (!netif_running(dev)) {
4829 rtnl_unlock();
4830 return 0;
4831 }
4832
4833 netif_device_detach(dev);
4834
5d07d868 4835 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
9f6c9258
DK		 4836
4837 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
4838
4839 rtnl_unlock();
4840
4841 return 0;
4842}
4843
4844int bnx2x_resume(struct pci_dev *pdev)
4845{
4846 struct net_device *dev = pci_get_drvdata(pdev);
4847 struct bnx2x *bp;
4848 int rc;
4849
4850 if (!dev) {
4851 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4852 return -ENODEV;
4853 }
4854 bp = netdev_priv(dev);
4855
4856 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 4857 BNX2X_ERR("Handling parity error recovery. Try again later\n");
9f6c9258
DK		 4858 return -EAGAIN;
4859 }
4860
4861 rtnl_lock();
4862
4863 pci_restore_state(pdev);
4864
4865 if (!netif_running(dev)) {
4866 rtnl_unlock();
4867 return 0;
4868 }
4869
4870 bnx2x_set_power_state(bp, PCI_D0);
4871 netif_device_attach(dev);
4872
4873 rc = bnx2x_nic_load(bp, LOAD_OPEN);
4874
4875 rtnl_unlock();
4876
4877 return rc;
4878}
619c5cb6 4879
619c5cb6
VZ		 4880void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
4881 u32 cid)
4882{
b9871bcf
AE		 4883 if (!cxt) {
4884 BNX2X_ERR("bad context pointer %p\n", cxt);
4885 return;
4886 }
4887
619c5cb6
VZ		 4888 /* ustorm cxt validation */
4889 cxt->ustorm_ag_context.cdu_usage =
4890 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4891 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
4892 /* xcontext validation */
4893 cxt->xstorm_ag_context.cdu_reserved =
4894 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4895 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
4896}
4897
1191cb83
ED		 4898static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
4899 u8 fw_sb_id, u8 sb_index,
4900 u8 ticks)
619c5cb6 4901{
619c5cb6
VZ		 4902 u32 addr = BAR_CSTRORM_INTMEM +
4903 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
4904 REG_WR8(bp, addr, ticks);
51c1a580
MS		 4905 DP(NETIF_MSG_IFUP,
4906 "port %x fw_sb_id %d sb_index %d ticks %d\n",
4907 port, fw_sb_id, sb_index, ticks);
619c5cb6
VZ		 4908}
4909
1191cb83
ED		 4910static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
4911 u16 fw_sb_id, u8 sb_index,
4912 u8 disable)
619c5cb6
VZ		 4913{
4914 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
4915 u32 addr = BAR_CSTRORM_INTMEM +
4916 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
0c14e5ce 4917 u8 flags = REG_RD8(bp, addr);
619c5cb6
VZ		 4918 /* clear and set */
4919 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4920 flags |= enable_flag;
0c14e5ce 4921 REG_WR8(bp, addr, flags);
51c1a580
MS		 4922 DP(NETIF_MSG_IFUP,
4923 "port %x fw_sb_id %d sb_index %d disable %d\n",
4924 port, fw_sb_id, sb_index, disable);
619c5cb6
VZ		 4925}
4926
4927void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
4928 u8 sb_index, u8 disable, u16 usec)
4929{
4930 int port = BP_PORT(bp);
4931 u8 ticks = usec / BNX2X_BTR;
4932
4933 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4934
4935 disable = disable ? 1 : (usec ? 0 : 1);
4936 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4937}
230bb0f3
YM		 4938
4939void bnx2x_schedule_sp_rtnl(struct bnx2x *bp, enum sp_rtnl_flag flag,
4940 u32 verbose)
4941{
4e857c58 4942 smp_mb__before_atomic();
230bb0f3 4943 set_bit(flag, &bp->sp_rtnl_state);
4e857c58 4944 smp_mb__after_atomic();
230bb0f3
YM		 4945 DP((BNX2X_MSG_SP | verbose), "Scheduling sp_rtnl task [Flag: %d]\n",
4946 flag);
4947 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4948}
4949EXPORT_SYMBOL(bnx2x_schedule_sp_rtnl);
Linux kernel - Deliverables
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