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net: encx24j600: Fix mask to update LED configuration
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41#include <net/vxlan.h>
42#endif
43#ifdef CONFIG_NET_RX_BUSY_POLL
44#include <net/busy_poll.h>
45#endif
46#include <linux/workqueue.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/log2.h>
50#include <linux/aer.h>
51#include <linux/bitmap.h>
52#include <linux/cpu_rmap.h>
53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
56#include "bnxt_sriov.h"
57#include "bnxt_ethtool.h"
58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
72#define BNXT_TX_PUSH_THRESH 92
73
74enum board_idx {
75 BCM57302,
76 BCM57304,
77 BCM57404,
78 BCM57406,
79 BCM57304_VF,
80 BCM57404_VF,
81};
82
83/* indexed by enum above */
84static const struct {
85 char *name;
86} board_info[] = {
87 { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
88 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
89 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
90 { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
92 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
93};
94
95static const struct pci_device_id bnxt_pci_tbl[] = {
96 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
97 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
98 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
99 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
100#ifdef CONFIG_BNXT_SRIOV
101 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
102 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
103#endif
104 { 0 }
105};
106
107MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
108
109static const u16 bnxt_vf_req_snif[] = {
110 HWRM_FUNC_CFG,
111 HWRM_PORT_PHY_QCFG,
112 HWRM_CFA_L2_FILTER_ALLOC,
113};
114
115static bool bnxt_vf_pciid(enum board_idx idx)
116{
117 return (idx == BCM57304_VF || idx == BCM57404_VF);
118}
119
120#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
121#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
122#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
123
124#define BNXT_CP_DB_REARM(db, raw_cons) \
125 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
126
127#define BNXT_CP_DB(db, raw_cons) \
128 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
129
130#define BNXT_CP_DB_IRQ_DIS(db) \
131 writel(DB_CP_IRQ_DIS_FLAGS, db)
132
133static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
134{
135 /* Tell compiler to fetch tx indices from memory. */
136 barrier();
137
138 return bp->tx_ring_size -
139 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
140}
141
142static const u16 bnxt_lhint_arr[] = {
143 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
144 TX_BD_FLAGS_LHINT_512_TO_1023,
145 TX_BD_FLAGS_LHINT_1024_TO_2047,
146 TX_BD_FLAGS_LHINT_1024_TO_2047,
147 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
148 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
149 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
150 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
151 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
152 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162};
163
164static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
165{
166 struct bnxt *bp = netdev_priv(dev);
167 struct tx_bd *txbd;
168 struct tx_bd_ext *txbd1;
169 struct netdev_queue *txq;
170 int i;
171 dma_addr_t mapping;
172 unsigned int length, pad = 0;
173 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
174 u16 prod, last_frag;
175 struct pci_dev *pdev = bp->pdev;
176 struct bnxt_napi *bnapi;
177 struct bnxt_tx_ring_info *txr;
178 struct bnxt_sw_tx_bd *tx_buf;
179
180 i = skb_get_queue_mapping(skb);
181 if (unlikely(i >= bp->tx_nr_rings)) {
182 dev_kfree_skb_any(skb);
183 return NETDEV_TX_OK;
184 }
185
186 bnapi = bp->bnapi[i];
187 txr = &bnapi->tx_ring;
188 txq = netdev_get_tx_queue(dev, i);
189 prod = txr->tx_prod;
190
191 free_size = bnxt_tx_avail(bp, txr);
192 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
193 netif_tx_stop_queue(txq);
194 return NETDEV_TX_BUSY;
195 }
196
197 length = skb->len;
198 len = skb_headlen(skb);
199 last_frag = skb_shinfo(skb)->nr_frags;
200
201 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
202
203 txbd->tx_bd_opaque = prod;
204
205 tx_buf = &txr->tx_buf_ring[prod];
206 tx_buf->skb = skb;
207 tx_buf->nr_frags = last_frag;
208
209 vlan_tag_flags = 0;
210 cfa_action = 0;
211 if (skb_vlan_tag_present(skb)) {
212 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
213 skb_vlan_tag_get(skb);
214 /* Currently supports 8021Q, 8021AD vlan offloads
215 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
216 */
217 if (skb->vlan_proto == htons(ETH_P_8021Q))
218 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
219 }
220
221 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
222 struct tx_push_bd *push = txr->tx_push;
223 struct tx_bd *tx_push = &push->txbd1;
224 struct tx_bd_ext *tx_push1 = &push->txbd2;
225 void *pdata = tx_push1 + 1;
226 int j;
227
228 /* Set COAL_NOW to be ready quickly for the next push */
229 tx_push->tx_bd_len_flags_type =
230 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
231 TX_BD_TYPE_LONG_TX_BD |
232 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
233 TX_BD_FLAGS_COAL_NOW |
234 TX_BD_FLAGS_PACKET_END |
235 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
236
237 if (skb->ip_summed == CHECKSUM_PARTIAL)
238 tx_push1->tx_bd_hsize_lflags =
239 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
240 else
241 tx_push1->tx_bd_hsize_lflags = 0;
242
243 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
244 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
245
246 skb_copy_from_linear_data(skb, pdata, len);
247 pdata += len;
248 for (j = 0; j < last_frag; j++) {
249 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
250 void *fptr;
251
252 fptr = skb_frag_address_safe(frag);
253 if (!fptr)
254 goto normal_tx;
255
256 memcpy(pdata, fptr, skb_frag_size(frag));
257 pdata += skb_frag_size(frag);
258 }
259
260 memcpy(txbd, tx_push, sizeof(*txbd));
261 prod = NEXT_TX(prod);
262 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
263 memcpy(txbd, tx_push1, sizeof(*txbd));
264 prod = NEXT_TX(prod);
265 push->doorbell =
266 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
267 txr->tx_prod = prod;
268
269 netdev_tx_sent_queue(txq, skb->len);
270
271 __iowrite64_copy(txr->tx_doorbell, push,
272 (length + sizeof(*push) + 8) / 8);
273
274 tx_buf->is_push = 1;
275
276 goto tx_done;
277 }
278
279normal_tx:
280 if (length < BNXT_MIN_PKT_SIZE) {
281 pad = BNXT_MIN_PKT_SIZE - length;
282 if (skb_pad(skb, pad)) {
283 /* SKB already freed. */
284 tx_buf->skb = NULL;
285 return NETDEV_TX_OK;
286 }
287 length = BNXT_MIN_PKT_SIZE;
288 }
289
290 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
291
292 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
293 dev_kfree_skb_any(skb);
294 tx_buf->skb = NULL;
295 return NETDEV_TX_OK;
296 }
297
298 dma_unmap_addr_set(tx_buf, mapping, mapping);
299 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
300 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
301
302 txbd->tx_bd_haddr = cpu_to_le64(mapping);
303
304 prod = NEXT_TX(prod);
305 txbd1 = (struct tx_bd_ext *)
306 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
307
308 txbd1->tx_bd_hsize_lflags = 0;
309 if (skb_is_gso(skb)) {
310 u32 hdr_len;
311
312 if (skb->encapsulation)
313 hdr_len = skb_inner_network_offset(skb) +
314 skb_inner_network_header_len(skb) +
315 inner_tcp_hdrlen(skb);
316 else
317 hdr_len = skb_transport_offset(skb) +
318 tcp_hdrlen(skb);
319
320 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
321 TX_BD_FLAGS_T_IPID |
322 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
323 length = skb_shinfo(skb)->gso_size;
324 txbd1->tx_bd_mss = cpu_to_le32(length);
325 length += hdr_len;
326 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
327 txbd1->tx_bd_hsize_lflags =
328 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
329 txbd1->tx_bd_mss = 0;
330 }
331
332 length >>= 9;
333 flags |= bnxt_lhint_arr[length];
334 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
335
336 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
337 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
338 for (i = 0; i < last_frag; i++) {
339 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
340
341 prod = NEXT_TX(prod);
342 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
343
344 len = skb_frag_size(frag);
345 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
346 DMA_TO_DEVICE);
347
348 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
349 goto tx_dma_error;
350
351 tx_buf = &txr->tx_buf_ring[prod];
352 dma_unmap_addr_set(tx_buf, mapping, mapping);
353
354 txbd->tx_bd_haddr = cpu_to_le64(mapping);
355
356 flags = len << TX_BD_LEN_SHIFT;
357 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
358 }
359
360 flags &= ~TX_BD_LEN;
361 txbd->tx_bd_len_flags_type =
362 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
363 TX_BD_FLAGS_PACKET_END);
364
365 netdev_tx_sent_queue(txq, skb->len);
366
367 /* Sync BD data before updating doorbell */
368 wmb();
369
370 prod = NEXT_TX(prod);
371 txr->tx_prod = prod;
372
373 writel(DB_KEY_TX | prod, txr->tx_doorbell);
374 writel(DB_KEY_TX | prod, txr->tx_doorbell);
375
376tx_done:
377
378 mmiowb();
379
380 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
381 netif_tx_stop_queue(txq);
382
383 /* netif_tx_stop_queue() must be done before checking
384 * tx index in bnxt_tx_avail() below, because in
385 * bnxt_tx_int(), we update tx index before checking for
386 * netif_tx_queue_stopped().
387 */
388 smp_mb();
389 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
390 netif_tx_wake_queue(txq);
391 }
392 return NETDEV_TX_OK;
393
394tx_dma_error:
395 last_frag = i;
396
397 /* start back at beginning and unmap skb */
398 prod = txr->tx_prod;
399 tx_buf = &txr->tx_buf_ring[prod];
400 tx_buf->skb = NULL;
401 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
402 skb_headlen(skb), PCI_DMA_TODEVICE);
403 prod = NEXT_TX(prod);
404
405 /* unmap remaining mapped pages */
406 for (i = 0; i < last_frag; i++) {
407 prod = NEXT_TX(prod);
408 tx_buf = &txr->tx_buf_ring[prod];
409 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
410 skb_frag_size(&skb_shinfo(skb)->frags[i]),
411 PCI_DMA_TODEVICE);
412 }
413
414 dev_kfree_skb_any(skb);
415 return NETDEV_TX_OK;
416}
417
418static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
419{
420 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
421 int index = bnapi->index;
422 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
423 u16 cons = txr->tx_cons;
424 struct pci_dev *pdev = bp->pdev;
425 int i;
426 unsigned int tx_bytes = 0;
427
428 for (i = 0; i < nr_pkts; i++) {
429 struct bnxt_sw_tx_bd *tx_buf;
430 struct sk_buff *skb;
431 int j, last;
432
433 tx_buf = &txr->tx_buf_ring[cons];
434 cons = NEXT_TX(cons);
435 skb = tx_buf->skb;
436 tx_buf->skb = NULL;
437
438 if (tx_buf->is_push) {
439 tx_buf->is_push = 0;
440 goto next_tx_int;
441 }
442
443 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
444 skb_headlen(skb), PCI_DMA_TODEVICE);
445 last = tx_buf->nr_frags;
446
447 for (j = 0; j < last; j++) {
448 cons = NEXT_TX(cons);
449 tx_buf = &txr->tx_buf_ring[cons];
450 dma_unmap_page(
451 &pdev->dev,
452 dma_unmap_addr(tx_buf, mapping),
453 skb_frag_size(&skb_shinfo(skb)->frags[j]),
454 PCI_DMA_TODEVICE);
455 }
456
457next_tx_int:
458 cons = NEXT_TX(cons);
459
460 tx_bytes += skb->len;
461 dev_kfree_skb_any(skb);
462 }
463
464 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
465 txr->tx_cons = cons;
466
467 /* Need to make the tx_cons update visible to bnxt_start_xmit()
468 * before checking for netif_tx_queue_stopped(). Without the
469 * memory barrier, there is a small possibility that bnxt_start_xmit()
470 * will miss it and cause the queue to be stopped forever.
471 */
472 smp_mb();
473
474 if (unlikely(netif_tx_queue_stopped(txq)) &&
475 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
476 __netif_tx_lock(txq, smp_processor_id());
477 if (netif_tx_queue_stopped(txq) &&
478 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
479 txr->dev_state != BNXT_DEV_STATE_CLOSING)
480 netif_tx_wake_queue(txq);
481 __netif_tx_unlock(txq);
482 }
483}
484
485static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
486 gfp_t gfp)
487{
488 u8 *data;
489 struct pci_dev *pdev = bp->pdev;
490
491 data = kmalloc(bp->rx_buf_size, gfp);
492 if (!data)
493 return NULL;
494
495 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
496 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
497
498 if (dma_mapping_error(&pdev->dev, *mapping)) {
499 kfree(data);
500 data = NULL;
501 }
502 return data;
503}
504
505static inline int bnxt_alloc_rx_data(struct bnxt *bp,
506 struct bnxt_rx_ring_info *rxr,
507 u16 prod, gfp_t gfp)
508{
509 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
510 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
511 u8 *data;
512 dma_addr_t mapping;
513
514 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
515 if (!data)
516 return -ENOMEM;
517
518 rx_buf->data = data;
519 dma_unmap_addr_set(rx_buf, mapping, mapping);
520
521 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
522
523 return 0;
524}
525
526static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
527 u8 *data)
528{
529 u16 prod = rxr->rx_prod;
530 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
531 struct rx_bd *cons_bd, *prod_bd;
532
533 prod_rx_buf = &rxr->rx_buf_ring[prod];
534 cons_rx_buf = &rxr->rx_buf_ring[cons];
535
536 prod_rx_buf->data = data;
537
538 dma_unmap_addr_set(prod_rx_buf, mapping,
539 dma_unmap_addr(cons_rx_buf, mapping));
540
541 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
542 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
543
544 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
545}
546
547static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
548{
549 u16 next, max = rxr->rx_agg_bmap_size;
550
551 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
552 if (next >= max)
553 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
554 return next;
555}
556
557static inline int bnxt_alloc_rx_page(struct bnxt *bp,
558 struct bnxt_rx_ring_info *rxr,
559 u16 prod, gfp_t gfp)
560{
561 struct rx_bd *rxbd =
562 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
563 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
564 struct pci_dev *pdev = bp->pdev;
565 struct page *page;
566 dma_addr_t mapping;
567 u16 sw_prod = rxr->rx_sw_agg_prod;
568
569 page = alloc_page(gfp);
570 if (!page)
571 return -ENOMEM;
572
573 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
574 PCI_DMA_FROMDEVICE);
575 if (dma_mapping_error(&pdev->dev, mapping)) {
576 __free_page(page);
577 return -EIO;
578 }
579
580 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
581 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
582
583 __set_bit(sw_prod, rxr->rx_agg_bmap);
584 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
585 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
586
587 rx_agg_buf->page = page;
588 rx_agg_buf->mapping = mapping;
589 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
590 rxbd->rx_bd_opaque = sw_prod;
591 return 0;
592}
593
594static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
595 u32 agg_bufs)
596{
597 struct bnxt *bp = bnapi->bp;
598 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
599 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
600 u16 prod = rxr->rx_agg_prod;
601 u16 sw_prod = rxr->rx_sw_agg_prod;
602 u32 i;
603
604 for (i = 0; i < agg_bufs; i++) {
605 u16 cons;
606 struct rx_agg_cmp *agg;
607 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
608 struct rx_bd *prod_bd;
609 struct page *page;
610
611 agg = (struct rx_agg_cmp *)
612 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
613 cons = agg->rx_agg_cmp_opaque;
614 __clear_bit(cons, rxr->rx_agg_bmap);
615
616 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
617 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
618
619 __set_bit(sw_prod, rxr->rx_agg_bmap);
620 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
621 cons_rx_buf = &rxr->rx_agg_ring[cons];
622
623 /* It is possible for sw_prod to be equal to cons, so
624 * set cons_rx_buf->page to NULL first.
625 */
626 page = cons_rx_buf->page;
627 cons_rx_buf->page = NULL;
628 prod_rx_buf->page = page;
629
630 prod_rx_buf->mapping = cons_rx_buf->mapping;
631
632 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
633
634 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
635 prod_bd->rx_bd_opaque = sw_prod;
636
637 prod = NEXT_RX_AGG(prod);
638 sw_prod = NEXT_RX_AGG(sw_prod);
639 cp_cons = NEXT_CMP(cp_cons);
640 }
641 rxr->rx_agg_prod = prod;
642 rxr->rx_sw_agg_prod = sw_prod;
643}
644
645static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
646 struct bnxt_rx_ring_info *rxr, u16 cons,
647 u16 prod, u8 *data, dma_addr_t dma_addr,
648 unsigned int len)
649{
650 int err;
651 struct sk_buff *skb;
652
653 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
654 if (unlikely(err)) {
655 bnxt_reuse_rx_data(rxr, cons, data);
656 return NULL;
657 }
658
659 skb = build_skb(data, 0);
660 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
661 PCI_DMA_FROMDEVICE);
662 if (!skb) {
663 kfree(data);
664 return NULL;
665 }
666
667 skb_reserve(skb, BNXT_RX_OFFSET);
668 skb_put(skb, len);
669 return skb;
670}
671
672static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
673 struct sk_buff *skb, u16 cp_cons,
674 u32 agg_bufs)
675{
676 struct pci_dev *pdev = bp->pdev;
677 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
678 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
679 u16 prod = rxr->rx_agg_prod;
680 u32 i;
681
682 for (i = 0; i < agg_bufs; i++) {
683 u16 cons, frag_len;
684 struct rx_agg_cmp *agg;
685 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
686 struct page *page;
687 dma_addr_t mapping;
688
689 agg = (struct rx_agg_cmp *)
690 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
691 cons = agg->rx_agg_cmp_opaque;
692 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
693 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
694
695 cons_rx_buf = &rxr->rx_agg_ring[cons];
696 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
697 __clear_bit(cons, rxr->rx_agg_bmap);
698
699 /* It is possible for bnxt_alloc_rx_page() to allocate
700 * a sw_prod index that equals the cons index, so we
701 * need to clear the cons entry now.
702 */
703 mapping = dma_unmap_addr(cons_rx_buf, mapping);
704 page = cons_rx_buf->page;
705 cons_rx_buf->page = NULL;
706
707 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
708 struct skb_shared_info *shinfo;
709 unsigned int nr_frags;
710
711 shinfo = skb_shinfo(skb);
712 nr_frags = --shinfo->nr_frags;
713 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
714
715 dev_kfree_skb(skb);
716
717 cons_rx_buf->page = page;
718
719 /* Update prod since possibly some pages have been
720 * allocated already.
721 */
722 rxr->rx_agg_prod = prod;
723 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
724 return NULL;
725 }
726
727 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
728 PCI_DMA_FROMDEVICE);
729
730 skb->data_len += frag_len;
731 skb->len += frag_len;
732 skb->truesize += PAGE_SIZE;
733
734 prod = NEXT_RX_AGG(prod);
735 cp_cons = NEXT_CMP(cp_cons);
736 }
737 rxr->rx_agg_prod = prod;
738 return skb;
739}
740
741static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
742 u8 agg_bufs, u32 *raw_cons)
743{
744 u16 last;
745 struct rx_agg_cmp *agg;
746
747 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
748 last = RING_CMP(*raw_cons);
749 agg = (struct rx_agg_cmp *)
750 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
751 return RX_AGG_CMP_VALID(agg, *raw_cons);
752}
753
754static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
755 unsigned int len,
756 dma_addr_t mapping)
757{
758 struct bnxt *bp = bnapi->bp;
759 struct pci_dev *pdev = bp->pdev;
760 struct sk_buff *skb;
761
762 skb = napi_alloc_skb(&bnapi->napi, len);
763 if (!skb)
764 return NULL;
765
766 dma_sync_single_for_cpu(&pdev->dev, mapping,
767 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
768
769 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
770
771 dma_sync_single_for_device(&pdev->dev, mapping,
772 bp->rx_copy_thresh,
773 PCI_DMA_FROMDEVICE);
774
775 skb_put(skb, len);
776 return skb;
777}
778
779static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
780 struct rx_tpa_start_cmp *tpa_start,
781 struct rx_tpa_start_cmp_ext *tpa_start1)
782{
783 u8 agg_id = TPA_START_AGG_ID(tpa_start);
784 u16 cons, prod;
785 struct bnxt_tpa_info *tpa_info;
786 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
787 struct rx_bd *prod_bd;
788 dma_addr_t mapping;
789
790 cons = tpa_start->rx_tpa_start_cmp_opaque;
791 prod = rxr->rx_prod;
792 cons_rx_buf = &rxr->rx_buf_ring[cons];
793 prod_rx_buf = &rxr->rx_buf_ring[prod];
794 tpa_info = &rxr->rx_tpa[agg_id];
795
796 prod_rx_buf->data = tpa_info->data;
797
798 mapping = tpa_info->mapping;
799 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
800
801 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
802
803 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
804
805 tpa_info->data = cons_rx_buf->data;
806 cons_rx_buf->data = NULL;
807 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
808
809 tpa_info->len =
810 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
811 RX_TPA_START_CMP_LEN_SHIFT;
812 if (likely(TPA_START_HASH_VALID(tpa_start))) {
813 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
814
815 tpa_info->hash_type = PKT_HASH_TYPE_L4;
816 tpa_info->gso_type = SKB_GSO_TCPV4;
817 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
818 if (hash_type == 3)
819 tpa_info->gso_type = SKB_GSO_TCPV6;
820 tpa_info->rss_hash =
821 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
822 } else {
823 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
824 tpa_info->gso_type = 0;
825 if (netif_msg_rx_err(bp))
826 netdev_warn(bp->dev, "TPA packet without valid hash\n");
827 }
828 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
829 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
830
831 rxr->rx_prod = NEXT_RX(prod);
832 cons = NEXT_RX(cons);
833 cons_rx_buf = &rxr->rx_buf_ring[cons];
834
835 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
836 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
837 cons_rx_buf->data = NULL;
838}
839
840static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
841 u16 cp_cons, u32 agg_bufs)
842{
843 if (agg_bufs)
844 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
845}
846
847#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
848#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
849
850static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
851 struct rx_tpa_end_cmp *tpa_end,
852 struct rx_tpa_end_cmp_ext *tpa_end1,
853 struct sk_buff *skb)
854{
855 struct tcphdr *th;
856 int payload_off, tcp_opt_len = 0;
857 int len, nw_off;
858
859 NAPI_GRO_CB(skb)->count = TPA_END_TPA_SEGS(tpa_end);
860 skb_shinfo(skb)->gso_size =
861 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
862 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
863 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
864 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
865 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
866 if (TPA_END_GRO_TS(tpa_end))
867 tcp_opt_len = 12;
868
869#ifdef CONFIG_INET
870 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
871 struct iphdr *iph;
872
873 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
874 ETH_HLEN;
875 skb_set_network_header(skb, nw_off);
876 iph = ip_hdr(skb);
877 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
878 len = skb->len - skb_transport_offset(skb);
879 th = tcp_hdr(skb);
880 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
881 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
882 struct ipv6hdr *iph;
883
884 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
885 ETH_HLEN;
886 skb_set_network_header(skb, nw_off);
887 iph = ipv6_hdr(skb);
888 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
889 len = skb->len - skb_transport_offset(skb);
890 th = tcp_hdr(skb);
891 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
892 } else {
893 dev_kfree_skb_any(skb);
894 return NULL;
895 }
896 tcp_gro_complete(skb);
897
898 if (nw_off) { /* tunnel */
899 struct udphdr *uh = NULL;
900
901 if (skb->protocol == htons(ETH_P_IP)) {
902 struct iphdr *iph = (struct iphdr *)skb->data;
903
904 if (iph->protocol == IPPROTO_UDP)
905 uh = (struct udphdr *)(iph + 1);
906 } else {
907 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
908
909 if (iph->nexthdr == IPPROTO_UDP)
910 uh = (struct udphdr *)(iph + 1);
911 }
912 if (uh) {
913 if (uh->check)
914 skb_shinfo(skb)->gso_type |=
915 SKB_GSO_UDP_TUNNEL_CSUM;
916 else
917 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
918 }
919 }
920#endif
921 return skb;
922}
923
924static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
925 struct bnxt_napi *bnapi,
926 u32 *raw_cons,
927 struct rx_tpa_end_cmp *tpa_end,
928 struct rx_tpa_end_cmp_ext *tpa_end1,
929 bool *agg_event)
930{
931 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
932 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
933 u8 agg_id = TPA_END_AGG_ID(tpa_end);
934 u8 *data, agg_bufs;
935 u16 cp_cons = RING_CMP(*raw_cons);
936 unsigned int len;
937 struct bnxt_tpa_info *tpa_info;
938 dma_addr_t mapping;
939 struct sk_buff *skb;
940
941 tpa_info = &rxr->rx_tpa[agg_id];
942 data = tpa_info->data;
943 prefetch(data);
944 len = tpa_info->len;
945 mapping = tpa_info->mapping;
946
947 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
948 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
949
950 if (agg_bufs) {
951 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
952 return ERR_PTR(-EBUSY);
953
954 *agg_event = true;
955 cp_cons = NEXT_CMP(cp_cons);
956 }
957
958 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
959 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
960 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
961 agg_bufs, (int)MAX_SKB_FRAGS);
962 return NULL;
963 }
964
965 if (len <= bp->rx_copy_thresh) {
966 skb = bnxt_copy_skb(bnapi, data, len, mapping);
967 if (!skb) {
968 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
969 return NULL;
970 }
971 } else {
972 u8 *new_data;
973 dma_addr_t new_mapping;
974
975 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
976 if (!new_data) {
977 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
978 return NULL;
979 }
980
981 tpa_info->data = new_data;
982 tpa_info->mapping = new_mapping;
983
984 skb = build_skb(data, 0);
985 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
986 PCI_DMA_FROMDEVICE);
987
988 if (!skb) {
989 kfree(data);
990 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
991 return NULL;
992 }
993 skb_reserve(skb, BNXT_RX_OFFSET);
994 skb_put(skb, len);
995 }
996
997 if (agg_bufs) {
998 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
999 if (!skb) {
1000 /* Page reuse already handled by bnxt_rx_pages(). */
1001 return NULL;
1002 }
1003 }
1004 skb->protocol = eth_type_trans(skb, bp->dev);
1005
1006 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1007 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1008
1009 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1010 netdev_features_t features = skb->dev->features;
1011 u16 vlan_proto = tpa_info->metadata >>
1012 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1013
1014 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1015 vlan_proto == ETH_P_8021Q) ||
1016 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1017 vlan_proto == ETH_P_8021AD)) {
1018 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1019 tpa_info->metadata &
1020 RX_CMP_FLAGS2_METADATA_VID_MASK);
1021 }
1022 }
1023
1024 skb_checksum_none_assert(skb);
1025 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1026 skb->ip_summed = CHECKSUM_UNNECESSARY;
1027 skb->csum_level =
1028 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1029 }
1030
1031 if (TPA_END_GRO(tpa_end))
1032 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1033
1034 return skb;
1035}
1036
1037/* returns the following:
1038 * 1 - 1 packet successfully received
1039 * 0 - successful TPA_START, packet not completed yet
1040 * -EBUSY - completion ring does not have all the agg buffers yet
1041 * -ENOMEM - packet aborted due to out of memory
1042 * -EIO - packet aborted due to hw error indicated in BD
1043 */
1044static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1045 bool *agg_event)
1046{
1047 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1048 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1049 struct net_device *dev = bp->dev;
1050 struct rx_cmp *rxcmp;
1051 struct rx_cmp_ext *rxcmp1;
1052 u32 tmp_raw_cons = *raw_cons;
1053 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1054 struct bnxt_sw_rx_bd *rx_buf;
1055 unsigned int len;
1056 u8 *data, agg_bufs, cmp_type;
1057 dma_addr_t dma_addr;
1058 struct sk_buff *skb;
1059 int rc = 0;
1060
1061 rxcmp = (struct rx_cmp *)
1062 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1063
1064 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1065 cp_cons = RING_CMP(tmp_raw_cons);
1066 rxcmp1 = (struct rx_cmp_ext *)
1067 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1068
1069 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1070 return -EBUSY;
1071
1072 cmp_type = RX_CMP_TYPE(rxcmp);
1073
1074 prod = rxr->rx_prod;
1075
1076 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1077 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1078 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1079
1080 goto next_rx_no_prod;
1081
1082 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1083 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1084 (struct rx_tpa_end_cmp *)rxcmp,
1085 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1086 agg_event);
1087
1088 if (unlikely(IS_ERR(skb)))
1089 return -EBUSY;
1090
1091 rc = -ENOMEM;
1092 if (likely(skb)) {
1093 skb_record_rx_queue(skb, bnapi->index);
1094 skb_mark_napi_id(skb, &bnapi->napi);
1095 if (bnxt_busy_polling(bnapi))
1096 netif_receive_skb(skb);
1097 else
1098 napi_gro_receive(&bnapi->napi, skb);
1099 rc = 1;
1100 }
1101 goto next_rx_no_prod;
1102 }
1103
1104 cons = rxcmp->rx_cmp_opaque;
1105 rx_buf = &rxr->rx_buf_ring[cons];
1106 data = rx_buf->data;
1107 prefetch(data);
1108
1109 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1110 RX_CMP_AGG_BUFS_SHIFT;
1111
1112 if (agg_bufs) {
1113 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1114 return -EBUSY;
1115
1116 cp_cons = NEXT_CMP(cp_cons);
1117 *agg_event = true;
1118 }
1119
1120 rx_buf->data = NULL;
1121 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1122 bnxt_reuse_rx_data(rxr, cons, data);
1123 if (agg_bufs)
1124 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1125
1126 rc = -EIO;
1127 goto next_rx;
1128 }
1129
1130 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1131 dma_addr = dma_unmap_addr(rx_buf, mapping);
1132
1133 if (len <= bp->rx_copy_thresh) {
1134 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1135 bnxt_reuse_rx_data(rxr, cons, data);
1136 if (!skb) {
1137 rc = -ENOMEM;
1138 goto next_rx;
1139 }
1140 } else {
1141 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1142 if (!skb) {
1143 rc = -ENOMEM;
1144 goto next_rx;
1145 }
1146 }
1147
1148 if (agg_bufs) {
1149 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1150 if (!skb) {
1151 rc = -ENOMEM;
1152 goto next_rx;
1153 }
1154 }
1155
1156 if (RX_CMP_HASH_VALID(rxcmp)) {
1157 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1158 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1159
1160 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1161 if (hash_type != 1 && hash_type != 3)
1162 type = PKT_HASH_TYPE_L3;
1163 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1164 }
1165
1166 skb->protocol = eth_type_trans(skb, dev);
1167
1168 if (rxcmp1->rx_cmp_flags2 &
1169 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1170 netdev_features_t features = skb->dev->features;
1171 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1172 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1173
1174 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1175 vlan_proto == ETH_P_8021Q) ||
1176 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1177 vlan_proto == ETH_P_8021AD))
1178 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1179 meta_data &
1180 RX_CMP_FLAGS2_METADATA_VID_MASK);
1181 }
1182
1183 skb_checksum_none_assert(skb);
1184 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1185 if (dev->features & NETIF_F_RXCSUM) {
1186 skb->ip_summed = CHECKSUM_UNNECESSARY;
1187 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1188 }
1189 } else {
1190 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)
1191 cpr->rx_l4_csum_errors++;
1192 }
1193
1194 skb_record_rx_queue(skb, bnapi->index);
1195 skb_mark_napi_id(skb, &bnapi->napi);
1196 if (bnxt_busy_polling(bnapi))
1197 netif_receive_skb(skb);
1198 else
1199 napi_gro_receive(&bnapi->napi, skb);
1200 rc = 1;
1201
1202next_rx:
1203 rxr->rx_prod = NEXT_RX(prod);
1204
1205next_rx_no_prod:
1206 *raw_cons = tmp_raw_cons;
1207
1208 return rc;
1209}
1210
1211static int bnxt_async_event_process(struct bnxt *bp,
1212 struct hwrm_async_event_cmpl *cmpl)
1213{
1214 u16 event_id = le16_to_cpu(cmpl->event_id);
1215
1216 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1217 switch (event_id) {
1218 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1219 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1220 schedule_work(&bp->sp_task);
1221 break;
1222 default:
1223 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1224 event_id);
1225 break;
1226 }
1227 return 0;
1228}
1229
1230static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1231{
1232 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1233 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1234 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1235 (struct hwrm_fwd_req_cmpl *)txcmp;
1236
1237 switch (cmpl_type) {
1238 case CMPL_BASE_TYPE_HWRM_DONE:
1239 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1240 if (seq_id == bp->hwrm_intr_seq_id)
1241 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1242 else
1243 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1244 break;
1245
1246 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1247 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1248
1249 if ((vf_id < bp->pf.first_vf_id) ||
1250 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1251 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1252 vf_id);
1253 return -EINVAL;
1254 }
1255
1256 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1257 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1258 schedule_work(&bp->sp_task);
1259 break;
1260
1261 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1262 bnxt_async_event_process(bp,
1263 (struct hwrm_async_event_cmpl *)txcmp);
1264
1265 default:
1266 break;
1267 }
1268
1269 return 0;
1270}
1271
1272static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1273{
1274 struct bnxt_napi *bnapi = dev_instance;
1275 struct bnxt *bp = bnapi->bp;
1276 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1277 u32 cons = RING_CMP(cpr->cp_raw_cons);
1278
1279 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1280 napi_schedule(&bnapi->napi);
1281 return IRQ_HANDLED;
1282}
1283
1284static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1285{
1286 u32 raw_cons = cpr->cp_raw_cons;
1287 u16 cons = RING_CMP(raw_cons);
1288 struct tx_cmp *txcmp;
1289
1290 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1291
1292 return TX_CMP_VALID(txcmp, raw_cons);
1293}
1294
1295#define CAG_LEGACY_INT_STATUS 0x2014
1296
1297static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1298{
1299 struct bnxt_napi *bnapi = dev_instance;
1300 struct bnxt *bp = bnapi->bp;
1301 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1302 u32 cons = RING_CMP(cpr->cp_raw_cons);
1303 u32 int_status;
1304
1305 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1306
1307 if (!bnxt_has_work(bp, cpr)) {
1308 int_status = readl(bp->bar0 + CAG_LEGACY_INT_STATUS);
1309 /* return if erroneous interrupt */
1310 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1311 return IRQ_NONE;
1312 }
1313
1314 /* disable ring IRQ */
1315 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1316
1317 /* Return here if interrupt is shared and is disabled. */
1318 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1319 return IRQ_HANDLED;
1320
1321 napi_schedule(&bnapi->napi);
1322 return IRQ_HANDLED;
1323}
1324
1325static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1326{
1327 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1328 u32 raw_cons = cpr->cp_raw_cons;
1329 u32 cons;
1330 int tx_pkts = 0;
1331 int rx_pkts = 0;
1332 bool rx_event = false;
1333 bool agg_event = false;
1334 struct tx_cmp *txcmp;
1335
1336 while (1) {
1337 int rc;
1338
1339 cons = RING_CMP(raw_cons);
1340 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1341
1342 if (!TX_CMP_VALID(txcmp, raw_cons))
1343 break;
1344
1345 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1346 tx_pkts++;
1347 /* return full budget so NAPI will complete. */
1348 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1349 rx_pkts = budget;
1350 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1351 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1352 if (likely(rc >= 0))
1353 rx_pkts += rc;
1354 else if (rc == -EBUSY) /* partial completion */
1355 break;
1356 rx_event = true;
1357 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1358 CMPL_BASE_TYPE_HWRM_DONE) ||
1359 (TX_CMP_TYPE(txcmp) ==
1360 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1361 (TX_CMP_TYPE(txcmp) ==
1362 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1363 bnxt_hwrm_handler(bp, txcmp);
1364 }
1365 raw_cons = NEXT_RAW_CMP(raw_cons);
1366
1367 if (rx_pkts == budget)
1368 break;
1369 }
1370
1371 cpr->cp_raw_cons = raw_cons;
1372 /* ACK completion ring before freeing tx ring and producing new
1373 * buffers in rx/agg rings to prevent overflowing the completion
1374 * ring.
1375 */
1376 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1377
1378 if (tx_pkts)
1379 bnxt_tx_int(bp, bnapi, tx_pkts);
1380
1381 if (rx_event) {
1382 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1383
1384 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1385 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1386 if (agg_event) {
1387 writel(DB_KEY_RX | rxr->rx_agg_prod,
1388 rxr->rx_agg_doorbell);
1389 writel(DB_KEY_RX | rxr->rx_agg_prod,
1390 rxr->rx_agg_doorbell);
1391 }
1392 }
1393 return rx_pkts;
1394}
1395
1396static int bnxt_poll(struct napi_struct *napi, int budget)
1397{
1398 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1399 struct bnxt *bp = bnapi->bp;
1400 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1401 int work_done = 0;
1402
1403 if (!bnxt_lock_napi(bnapi))
1404 return budget;
1405
1406 while (1) {
1407 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1408
1409 if (work_done >= budget)
1410 break;
1411
1412 if (!bnxt_has_work(bp, cpr)) {
1413 napi_complete(napi);
1414 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1415 break;
1416 }
1417 }
1418 mmiowb();
1419 bnxt_unlock_napi(bnapi);
1420 return work_done;
1421}
1422
1423#ifdef CONFIG_NET_RX_BUSY_POLL
1424static int bnxt_busy_poll(struct napi_struct *napi)
1425{
1426 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1427 struct bnxt *bp = bnapi->bp;
1428 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1429 int rx_work, budget = 4;
1430
1431 if (atomic_read(&bp->intr_sem) != 0)
1432 return LL_FLUSH_FAILED;
1433
1434 if (!bnxt_lock_poll(bnapi))
1435 return LL_FLUSH_BUSY;
1436
1437 rx_work = bnxt_poll_work(bp, bnapi, budget);
1438
1439 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1440
1441 bnxt_unlock_poll(bnapi);
1442 return rx_work;
1443}
1444#endif
1445
1446static void bnxt_free_tx_skbs(struct bnxt *bp)
1447{
1448 int i, max_idx;
1449 struct pci_dev *pdev = bp->pdev;
1450
1451 if (!bp->bnapi)
1452 return;
1453
1454 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1455 for (i = 0; i < bp->tx_nr_rings; i++) {
1456 struct bnxt_napi *bnapi = bp->bnapi[i];
1457 struct bnxt_tx_ring_info *txr;
1458 int j;
1459
1460 if (!bnapi)
1461 continue;
1462
1463 txr = &bnapi->tx_ring;
1464 for (j = 0; j < max_idx;) {
1465 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1466 struct sk_buff *skb = tx_buf->skb;
1467 int k, last;
1468
1469 if (!skb) {
1470 j++;
1471 continue;
1472 }
1473
1474 tx_buf->skb = NULL;
1475
1476 if (tx_buf->is_push) {
1477 dev_kfree_skb(skb);
1478 j += 2;
1479 continue;
1480 }
1481
1482 dma_unmap_single(&pdev->dev,
1483 dma_unmap_addr(tx_buf, mapping),
1484 skb_headlen(skb),
1485 PCI_DMA_TODEVICE);
1486
1487 last = tx_buf->nr_frags;
1488 j += 2;
1489 for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1490 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1491
1492 tx_buf = &txr->tx_buf_ring[j];
1493 dma_unmap_page(
1494 &pdev->dev,
1495 dma_unmap_addr(tx_buf, mapping),
1496 skb_frag_size(frag), PCI_DMA_TODEVICE);
1497 }
1498 dev_kfree_skb(skb);
1499 }
1500 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1501 }
1502}
1503
1504static void bnxt_free_rx_skbs(struct bnxt *bp)
1505{
1506 int i, max_idx, max_agg_idx;
1507 struct pci_dev *pdev = bp->pdev;
1508
1509 if (!bp->bnapi)
1510 return;
1511
1512 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1513 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1514 for (i = 0; i < bp->rx_nr_rings; i++) {
1515 struct bnxt_napi *bnapi = bp->bnapi[i];
1516 struct bnxt_rx_ring_info *rxr;
1517 int j;
1518
1519 if (!bnapi)
1520 continue;
1521
1522 rxr = &bnapi->rx_ring;
1523
1524 if (rxr->rx_tpa) {
1525 for (j = 0; j < MAX_TPA; j++) {
1526 struct bnxt_tpa_info *tpa_info =
1527 &rxr->rx_tpa[j];
1528 u8 *data = tpa_info->data;
1529
1530 if (!data)
1531 continue;
1532
1533 dma_unmap_single(
1534 &pdev->dev,
1535 dma_unmap_addr(tpa_info, mapping),
1536 bp->rx_buf_use_size,
1537 PCI_DMA_FROMDEVICE);
1538
1539 tpa_info->data = NULL;
1540
1541 kfree(data);
1542 }
1543 }
1544
1545 for (j = 0; j < max_idx; j++) {
1546 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1547 u8 *data = rx_buf->data;
1548
1549 if (!data)
1550 continue;
1551
1552 dma_unmap_single(&pdev->dev,
1553 dma_unmap_addr(rx_buf, mapping),
1554 bp->rx_buf_use_size,
1555 PCI_DMA_FROMDEVICE);
1556
1557 rx_buf->data = NULL;
1558
1559 kfree(data);
1560 }
1561
1562 for (j = 0; j < max_agg_idx; j++) {
1563 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1564 &rxr->rx_agg_ring[j];
1565 struct page *page = rx_agg_buf->page;
1566
1567 if (!page)
1568 continue;
1569
1570 dma_unmap_page(&pdev->dev,
1571 dma_unmap_addr(rx_agg_buf, mapping),
1572 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1573
1574 rx_agg_buf->page = NULL;
1575 __clear_bit(j, rxr->rx_agg_bmap);
1576
1577 __free_page(page);
1578 }
1579 }
1580}
1581
1582static void bnxt_free_skbs(struct bnxt *bp)
1583{
1584 bnxt_free_tx_skbs(bp);
1585 bnxt_free_rx_skbs(bp);
1586}
1587
1588static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1589{
1590 struct pci_dev *pdev = bp->pdev;
1591 int i;
1592
1593 for (i = 0; i < ring->nr_pages; i++) {
1594 if (!ring->pg_arr[i])
1595 continue;
1596
1597 dma_free_coherent(&pdev->dev, ring->page_size,
1598 ring->pg_arr[i], ring->dma_arr[i]);
1599
1600 ring->pg_arr[i] = NULL;
1601 }
1602 if (ring->pg_tbl) {
1603 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1604 ring->pg_tbl, ring->pg_tbl_map);
1605 ring->pg_tbl = NULL;
1606 }
1607 if (ring->vmem_size && *ring->vmem) {
1608 vfree(*ring->vmem);
1609 *ring->vmem = NULL;
1610 }
1611}
1612
1613static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1614{
1615 int i;
1616 struct pci_dev *pdev = bp->pdev;
1617
1618 if (ring->nr_pages > 1) {
1619 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1620 ring->nr_pages * 8,
1621 &ring->pg_tbl_map,
1622 GFP_KERNEL);
1623 if (!ring->pg_tbl)
1624 return -ENOMEM;
1625 }
1626
1627 for (i = 0; i < ring->nr_pages; i++) {
1628 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1629 ring->page_size,
1630 &ring->dma_arr[i],
1631 GFP_KERNEL);
1632 if (!ring->pg_arr[i])
1633 return -ENOMEM;
1634
1635 if (ring->nr_pages > 1)
1636 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1637 }
1638
1639 if (ring->vmem_size) {
1640 *ring->vmem = vzalloc(ring->vmem_size);
1641 if (!(*ring->vmem))
1642 return -ENOMEM;
1643 }
1644 return 0;
1645}
1646
1647static void bnxt_free_rx_rings(struct bnxt *bp)
1648{
1649 int i;
1650
1651 if (!bp->bnapi)
1652 return;
1653
1654 for (i = 0; i < bp->rx_nr_rings; i++) {
1655 struct bnxt_napi *bnapi = bp->bnapi[i];
1656 struct bnxt_rx_ring_info *rxr;
1657 struct bnxt_ring_struct *ring;
1658
1659 if (!bnapi)
1660 continue;
1661
1662 rxr = &bnapi->rx_ring;
1663
1664 kfree(rxr->rx_tpa);
1665 rxr->rx_tpa = NULL;
1666
1667 kfree(rxr->rx_agg_bmap);
1668 rxr->rx_agg_bmap = NULL;
1669
1670 ring = &rxr->rx_ring_struct;
1671 bnxt_free_ring(bp, ring);
1672
1673 ring = &rxr->rx_agg_ring_struct;
1674 bnxt_free_ring(bp, ring);
1675 }
1676}
1677
1678static int bnxt_alloc_rx_rings(struct bnxt *bp)
1679{
1680 int i, rc, agg_rings = 0, tpa_rings = 0;
1681
1682 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1683 agg_rings = 1;
1684
1685 if (bp->flags & BNXT_FLAG_TPA)
1686 tpa_rings = 1;
1687
1688 for (i = 0; i < bp->rx_nr_rings; i++) {
1689 struct bnxt_napi *bnapi = bp->bnapi[i];
1690 struct bnxt_rx_ring_info *rxr;
1691 struct bnxt_ring_struct *ring;
1692
1693 if (!bnapi)
1694 continue;
1695
1696 rxr = &bnapi->rx_ring;
1697 ring = &rxr->rx_ring_struct;
1698
1699 rc = bnxt_alloc_ring(bp, ring);
1700 if (rc)
1701 return rc;
1702
1703 if (agg_rings) {
1704 u16 mem_size;
1705
1706 ring = &rxr->rx_agg_ring_struct;
1707 rc = bnxt_alloc_ring(bp, ring);
1708 if (rc)
1709 return rc;
1710
1711 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1712 mem_size = rxr->rx_agg_bmap_size / 8;
1713 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1714 if (!rxr->rx_agg_bmap)
1715 return -ENOMEM;
1716
1717 if (tpa_rings) {
1718 rxr->rx_tpa = kcalloc(MAX_TPA,
1719 sizeof(struct bnxt_tpa_info),
1720 GFP_KERNEL);
1721 if (!rxr->rx_tpa)
1722 return -ENOMEM;
1723 }
1724 }
1725 }
1726 return 0;
1727}
1728
1729static void bnxt_free_tx_rings(struct bnxt *bp)
1730{
1731 int i;
1732 struct pci_dev *pdev = bp->pdev;
1733
1734 if (!bp->bnapi)
1735 return;
1736
1737 for (i = 0; i < bp->tx_nr_rings; i++) {
1738 struct bnxt_napi *bnapi = bp->bnapi[i];
1739 struct bnxt_tx_ring_info *txr;
1740 struct bnxt_ring_struct *ring;
1741
1742 if (!bnapi)
1743 continue;
1744
1745 txr = &bnapi->tx_ring;
1746
1747 if (txr->tx_push) {
1748 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1749 txr->tx_push, txr->tx_push_mapping);
1750 txr->tx_push = NULL;
1751 }
1752
1753 ring = &txr->tx_ring_struct;
1754
1755 bnxt_free_ring(bp, ring);
1756 }
1757}
1758
1759static int bnxt_alloc_tx_rings(struct bnxt *bp)
1760{
1761 int i, j, rc;
1762 struct pci_dev *pdev = bp->pdev;
1763
1764 bp->tx_push_size = 0;
1765 if (bp->tx_push_thresh) {
1766 int push_size;
1767
1768 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1769 bp->tx_push_thresh);
1770
1771 if (push_size > 128) {
1772 push_size = 0;
1773 bp->tx_push_thresh = 0;
1774 }
1775
1776 bp->tx_push_size = push_size;
1777 }
1778
1779 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1780 struct bnxt_napi *bnapi = bp->bnapi[i];
1781 struct bnxt_tx_ring_info *txr;
1782 struct bnxt_ring_struct *ring;
1783
1784 if (!bnapi)
1785 continue;
1786
1787 txr = &bnapi->tx_ring;
1788 ring = &txr->tx_ring_struct;
1789
1790 rc = bnxt_alloc_ring(bp, ring);
1791 if (rc)
1792 return rc;
1793
1794 if (bp->tx_push_size) {
1795 struct tx_bd *txbd;
1796 dma_addr_t mapping;
1797
1798 /* One pre-allocated DMA buffer to backup
1799 * TX push operation
1800 */
1801 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1802 bp->tx_push_size,
1803 &txr->tx_push_mapping,
1804 GFP_KERNEL);
1805
1806 if (!txr->tx_push)
1807 return -ENOMEM;
1808
1809 txbd = &txr->tx_push->txbd1;
1810
1811 mapping = txr->tx_push_mapping +
1812 sizeof(struct tx_push_bd);
1813 txbd->tx_bd_haddr = cpu_to_le64(mapping);
1814
1815 memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1816 }
1817 ring->queue_id = bp->q_info[j].queue_id;
1818 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1819 j++;
1820 }
1821 return 0;
1822}
1823
1824static void bnxt_free_cp_rings(struct bnxt *bp)
1825{
1826 int i;
1827
1828 if (!bp->bnapi)
1829 return;
1830
1831 for (i = 0; i < bp->cp_nr_rings; i++) {
1832 struct bnxt_napi *bnapi = bp->bnapi[i];
1833 struct bnxt_cp_ring_info *cpr;
1834 struct bnxt_ring_struct *ring;
1835
1836 if (!bnapi)
1837 continue;
1838
1839 cpr = &bnapi->cp_ring;
1840 ring = &cpr->cp_ring_struct;
1841
1842 bnxt_free_ring(bp, ring);
1843 }
1844}
1845
1846static int bnxt_alloc_cp_rings(struct bnxt *bp)
1847{
1848 int i, rc;
1849
1850 for (i = 0; i < bp->cp_nr_rings; i++) {
1851 struct bnxt_napi *bnapi = bp->bnapi[i];
1852 struct bnxt_cp_ring_info *cpr;
1853 struct bnxt_ring_struct *ring;
1854
1855 if (!bnapi)
1856 continue;
1857
1858 cpr = &bnapi->cp_ring;
1859 ring = &cpr->cp_ring_struct;
1860
1861 rc = bnxt_alloc_ring(bp, ring);
1862 if (rc)
1863 return rc;
1864 }
1865 return 0;
1866}
1867
1868static void bnxt_init_ring_struct(struct bnxt *bp)
1869{
1870 int i;
1871
1872 for (i = 0; i < bp->cp_nr_rings; i++) {
1873 struct bnxt_napi *bnapi = bp->bnapi[i];
1874 struct bnxt_cp_ring_info *cpr;
1875 struct bnxt_rx_ring_info *rxr;
1876 struct bnxt_tx_ring_info *txr;
1877 struct bnxt_ring_struct *ring;
1878
1879 if (!bnapi)
1880 continue;
1881
1882 cpr = &bnapi->cp_ring;
1883 ring = &cpr->cp_ring_struct;
1884 ring->nr_pages = bp->cp_nr_pages;
1885 ring->page_size = HW_CMPD_RING_SIZE;
1886 ring->pg_arr = (void **)cpr->cp_desc_ring;
1887 ring->dma_arr = cpr->cp_desc_mapping;
1888 ring->vmem_size = 0;
1889
1890 rxr = &bnapi->rx_ring;
1891 ring = &rxr->rx_ring_struct;
1892 ring->nr_pages = bp->rx_nr_pages;
1893 ring->page_size = HW_RXBD_RING_SIZE;
1894 ring->pg_arr = (void **)rxr->rx_desc_ring;
1895 ring->dma_arr = rxr->rx_desc_mapping;
1896 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1897 ring->vmem = (void **)&rxr->rx_buf_ring;
1898
1899 ring = &rxr->rx_agg_ring_struct;
1900 ring->nr_pages = bp->rx_agg_nr_pages;
1901 ring->page_size = HW_RXBD_RING_SIZE;
1902 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1903 ring->dma_arr = rxr->rx_agg_desc_mapping;
1904 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1905 ring->vmem = (void **)&rxr->rx_agg_ring;
1906
1907 txr = &bnapi->tx_ring;
1908 ring = &txr->tx_ring_struct;
1909 ring->nr_pages = bp->tx_nr_pages;
1910 ring->page_size = HW_RXBD_RING_SIZE;
1911 ring->pg_arr = (void **)txr->tx_desc_ring;
1912 ring->dma_arr = txr->tx_desc_mapping;
1913 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1914 ring->vmem = (void **)&txr->tx_buf_ring;
1915 }
1916}
1917
1918static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1919{
1920 int i;
1921 u32 prod;
1922 struct rx_bd **rx_buf_ring;
1923
1924 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1925 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1926 int j;
1927 struct rx_bd *rxbd;
1928
1929 rxbd = rx_buf_ring[i];
1930 if (!rxbd)
1931 continue;
1932
1933 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1934 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1935 rxbd->rx_bd_opaque = prod;
1936 }
1937 }
1938}
1939
1940static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1941{
1942 struct net_device *dev = bp->dev;
1943 struct bnxt_napi *bnapi = bp->bnapi[ring_nr];
1944 struct bnxt_rx_ring_info *rxr;
1945 struct bnxt_ring_struct *ring;
1946 u32 prod, type;
1947 int i;
1948
1949 if (!bnapi)
1950 return -EINVAL;
1951
1952 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1953 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1954
1955 if (NET_IP_ALIGN == 2)
1956 type |= RX_BD_FLAGS_SOP;
1957
1958 rxr = &bnapi->rx_ring;
1959 ring = &rxr->rx_ring_struct;
1960 bnxt_init_rxbd_pages(ring, type);
1961
1962 prod = rxr->rx_prod;
1963 for (i = 0; i < bp->rx_ring_size; i++) {
1964 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1965 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1966 ring_nr, i, bp->rx_ring_size);
1967 break;
1968 }
1969 prod = NEXT_RX(prod);
1970 }
1971 rxr->rx_prod = prod;
1972 ring->fw_ring_id = INVALID_HW_RING_ID;
1973
1974 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1975 return 0;
1976
1977 ring = &rxr->rx_agg_ring_struct;
1978
1979 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1980 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1981
1982 bnxt_init_rxbd_pages(ring, type);
1983
1984 prod = rxr->rx_agg_prod;
1985 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1986 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1987 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1988 ring_nr, i, bp->rx_ring_size);
1989 break;
1990 }
1991 prod = NEXT_RX_AGG(prod);
1992 }
1993 rxr->rx_agg_prod = prod;
1994 ring->fw_ring_id = INVALID_HW_RING_ID;
1995
1996 if (bp->flags & BNXT_FLAG_TPA) {
1997 if (rxr->rx_tpa) {
1998 u8 *data;
1999 dma_addr_t mapping;
2000
2001 for (i = 0; i < MAX_TPA; i++) {
2002 data = __bnxt_alloc_rx_data(bp, &mapping,
2003 GFP_KERNEL);
2004 if (!data)
2005 return -ENOMEM;
2006
2007 rxr->rx_tpa[i].data = data;
2008 rxr->rx_tpa[i].mapping = mapping;
2009 }
2010 } else {
2011 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2012 return -ENOMEM;
2013 }
2014 }
2015
2016 return 0;
2017}
2018
2019static int bnxt_init_rx_rings(struct bnxt *bp)
2020{
2021 int i, rc = 0;
2022
2023 for (i = 0; i < bp->rx_nr_rings; i++) {
2024 rc = bnxt_init_one_rx_ring(bp, i);
2025 if (rc)
2026 break;
2027 }
2028
2029 return rc;
2030}
2031
2032static int bnxt_init_tx_rings(struct bnxt *bp)
2033{
2034 u16 i;
2035
2036 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2037 MAX_SKB_FRAGS + 1);
2038
2039 for (i = 0; i < bp->tx_nr_rings; i++) {
2040 struct bnxt_napi *bnapi = bp->bnapi[i];
2041 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
2042 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2043
2044 ring->fw_ring_id = INVALID_HW_RING_ID;
2045 }
2046
2047 return 0;
2048}
2049
2050static void bnxt_free_ring_grps(struct bnxt *bp)
2051{
2052 kfree(bp->grp_info);
2053 bp->grp_info = NULL;
2054}
2055
2056static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2057{
2058 int i;
2059
2060 if (irq_re_init) {
2061 bp->grp_info = kcalloc(bp->cp_nr_rings,
2062 sizeof(struct bnxt_ring_grp_info),
2063 GFP_KERNEL);
2064 if (!bp->grp_info)
2065 return -ENOMEM;
2066 }
2067 for (i = 0; i < bp->cp_nr_rings; i++) {
2068 if (irq_re_init)
2069 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2070 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2071 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2072 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2073 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2074 }
2075 return 0;
2076}
2077
2078static void bnxt_free_vnics(struct bnxt *bp)
2079{
2080 kfree(bp->vnic_info);
2081 bp->vnic_info = NULL;
2082 bp->nr_vnics = 0;
2083}
2084
2085static int bnxt_alloc_vnics(struct bnxt *bp)
2086{
2087 int num_vnics = 1;
2088
2089#ifdef CONFIG_RFS_ACCEL
2090 if (bp->flags & BNXT_FLAG_RFS)
2091 num_vnics += bp->rx_nr_rings;
2092#endif
2093
2094 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2095 GFP_KERNEL);
2096 if (!bp->vnic_info)
2097 return -ENOMEM;
2098
2099 bp->nr_vnics = num_vnics;
2100 return 0;
2101}
2102
2103static void bnxt_init_vnics(struct bnxt *bp)
2104{
2105 int i;
2106
2107 for (i = 0; i < bp->nr_vnics; i++) {
2108 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2109
2110 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2111 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2112 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2113
2114 if (bp->vnic_info[i].rss_hash_key) {
2115 if (i == 0)
2116 prandom_bytes(vnic->rss_hash_key,
2117 HW_HASH_KEY_SIZE);
2118 else
2119 memcpy(vnic->rss_hash_key,
2120 bp->vnic_info[0].rss_hash_key,
2121 HW_HASH_KEY_SIZE);
2122 }
2123 }
2124}
2125
2126static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2127{
2128 int pages;
2129
2130 pages = ring_size / desc_per_pg;
2131
2132 if (!pages)
2133 return 1;
2134
2135 pages++;
2136
2137 while (pages & (pages - 1))
2138 pages++;
2139
2140 return pages;
2141}
2142
2143static void bnxt_set_tpa_flags(struct bnxt *bp)
2144{
2145 bp->flags &= ~BNXT_FLAG_TPA;
2146 if (bp->dev->features & NETIF_F_LRO)
2147 bp->flags |= BNXT_FLAG_LRO;
2148 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2149 bp->flags |= BNXT_FLAG_GRO;
2150}
2151
2152/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2153 * be set on entry.
2154 */
2155void bnxt_set_ring_params(struct bnxt *bp)
2156{
2157 u32 ring_size, rx_size, rx_space;
2158 u32 agg_factor = 0, agg_ring_size = 0;
2159
2160 /* 8 for CRC and VLAN */
2161 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2162
2163 rx_space = rx_size + NET_SKB_PAD +
2164 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2165
2166 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2167 ring_size = bp->rx_ring_size;
2168 bp->rx_agg_ring_size = 0;
2169 bp->rx_agg_nr_pages = 0;
2170
2171 if (bp->flags & BNXT_FLAG_TPA)
2172 agg_factor = 4;
2173
2174 bp->flags &= ~BNXT_FLAG_JUMBO;
2175 if (rx_space > PAGE_SIZE) {
2176 u32 jumbo_factor;
2177
2178 bp->flags |= BNXT_FLAG_JUMBO;
2179 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2180 if (jumbo_factor > agg_factor)
2181 agg_factor = jumbo_factor;
2182 }
2183 agg_ring_size = ring_size * agg_factor;
2184
2185 if (agg_ring_size) {
2186 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2187 RX_DESC_CNT);
2188 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2189 u32 tmp = agg_ring_size;
2190
2191 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2192 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2193 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2194 tmp, agg_ring_size);
2195 }
2196 bp->rx_agg_ring_size = agg_ring_size;
2197 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2198 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2199 rx_space = rx_size + NET_SKB_PAD +
2200 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2201 }
2202
2203 bp->rx_buf_use_size = rx_size;
2204 bp->rx_buf_size = rx_space;
2205
2206 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2207 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2208
2209 ring_size = bp->tx_ring_size;
2210 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2211 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2212
2213 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2214 bp->cp_ring_size = ring_size;
2215
2216 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2217 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2218 bp->cp_nr_pages = MAX_CP_PAGES;
2219 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2220 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2221 ring_size, bp->cp_ring_size);
2222 }
2223 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2224 bp->cp_ring_mask = bp->cp_bit - 1;
2225}
2226
2227static void bnxt_free_vnic_attributes(struct bnxt *bp)
2228{
2229 int i;
2230 struct bnxt_vnic_info *vnic;
2231 struct pci_dev *pdev = bp->pdev;
2232
2233 if (!bp->vnic_info)
2234 return;
2235
2236 for (i = 0; i < bp->nr_vnics; i++) {
2237 vnic = &bp->vnic_info[i];
2238
2239 kfree(vnic->fw_grp_ids);
2240 vnic->fw_grp_ids = NULL;
2241
2242 kfree(vnic->uc_list);
2243 vnic->uc_list = NULL;
2244
2245 if (vnic->mc_list) {
2246 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2247 vnic->mc_list, vnic->mc_list_mapping);
2248 vnic->mc_list = NULL;
2249 }
2250
2251 if (vnic->rss_table) {
2252 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2253 vnic->rss_table,
2254 vnic->rss_table_dma_addr);
2255 vnic->rss_table = NULL;
2256 }
2257
2258 vnic->rss_hash_key = NULL;
2259 vnic->flags = 0;
2260 }
2261}
2262
2263static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2264{
2265 int i, rc = 0, size;
2266 struct bnxt_vnic_info *vnic;
2267 struct pci_dev *pdev = bp->pdev;
2268 int max_rings;
2269
2270 for (i = 0; i < bp->nr_vnics; i++) {
2271 vnic = &bp->vnic_info[i];
2272
2273 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2274 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2275
2276 if (mem_size > 0) {
2277 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2278 if (!vnic->uc_list) {
2279 rc = -ENOMEM;
2280 goto out;
2281 }
2282 }
2283 }
2284
2285 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2286 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2287 vnic->mc_list =
2288 dma_alloc_coherent(&pdev->dev,
2289 vnic->mc_list_size,
2290 &vnic->mc_list_mapping,
2291 GFP_KERNEL);
2292 if (!vnic->mc_list) {
2293 rc = -ENOMEM;
2294 goto out;
2295 }
2296 }
2297
2298 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2299 max_rings = bp->rx_nr_rings;
2300 else
2301 max_rings = 1;
2302
2303 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2304 if (!vnic->fw_grp_ids) {
2305 rc = -ENOMEM;
2306 goto out;
2307 }
2308
2309 /* Allocate rss table and hash key */
2310 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2311 &vnic->rss_table_dma_addr,
2312 GFP_KERNEL);
2313 if (!vnic->rss_table) {
2314 rc = -ENOMEM;
2315 goto out;
2316 }
2317
2318 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2319
2320 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2321 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2322 }
2323 return 0;
2324
2325out:
2326 return rc;
2327}
2328
2329static void bnxt_free_hwrm_resources(struct bnxt *bp)
2330{
2331 struct pci_dev *pdev = bp->pdev;
2332
2333 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2334 bp->hwrm_cmd_resp_dma_addr);
2335
2336 bp->hwrm_cmd_resp_addr = NULL;
2337 if (bp->hwrm_dbg_resp_addr) {
2338 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2339 bp->hwrm_dbg_resp_addr,
2340 bp->hwrm_dbg_resp_dma_addr);
2341
2342 bp->hwrm_dbg_resp_addr = NULL;
2343 }
2344}
2345
2346static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2347{
2348 struct pci_dev *pdev = bp->pdev;
2349
2350 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2351 &bp->hwrm_cmd_resp_dma_addr,
2352 GFP_KERNEL);
2353 if (!bp->hwrm_cmd_resp_addr)
2354 return -ENOMEM;
2355 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2356 HWRM_DBG_REG_BUF_SIZE,
2357 &bp->hwrm_dbg_resp_dma_addr,
2358 GFP_KERNEL);
2359 if (!bp->hwrm_dbg_resp_addr)
2360 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2361
2362 return 0;
2363}
2364
2365static void bnxt_free_stats(struct bnxt *bp)
2366{
2367 u32 size, i;
2368 struct pci_dev *pdev = bp->pdev;
2369
2370 if (!bp->bnapi)
2371 return;
2372
2373 size = sizeof(struct ctx_hw_stats);
2374
2375 for (i = 0; i < bp->cp_nr_rings; i++) {
2376 struct bnxt_napi *bnapi = bp->bnapi[i];
2377 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2378
2379 if (cpr->hw_stats) {
2380 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2381 cpr->hw_stats_map);
2382 cpr->hw_stats = NULL;
2383 }
2384 }
2385}
2386
2387static int bnxt_alloc_stats(struct bnxt *bp)
2388{
2389 u32 size, i;
2390 struct pci_dev *pdev = bp->pdev;
2391
2392 size = sizeof(struct ctx_hw_stats);
2393
2394 for (i = 0; i < bp->cp_nr_rings; i++) {
2395 struct bnxt_napi *bnapi = bp->bnapi[i];
2396 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2397
2398 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2399 &cpr->hw_stats_map,
2400 GFP_KERNEL);
2401 if (!cpr->hw_stats)
2402 return -ENOMEM;
2403
2404 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2405 }
2406 return 0;
2407}
2408
2409static void bnxt_clear_ring_indices(struct bnxt *bp)
2410{
2411 int i;
2412
2413 if (!bp->bnapi)
2414 return;
2415
2416 for (i = 0; i < bp->cp_nr_rings; i++) {
2417 struct bnxt_napi *bnapi = bp->bnapi[i];
2418 struct bnxt_cp_ring_info *cpr;
2419 struct bnxt_rx_ring_info *rxr;
2420 struct bnxt_tx_ring_info *txr;
2421
2422 if (!bnapi)
2423 continue;
2424
2425 cpr = &bnapi->cp_ring;
2426 cpr->cp_raw_cons = 0;
2427
2428 txr = &bnapi->tx_ring;
2429 txr->tx_prod = 0;
2430 txr->tx_cons = 0;
2431
2432 rxr = &bnapi->rx_ring;
2433 rxr->rx_prod = 0;
2434 rxr->rx_agg_prod = 0;
2435 rxr->rx_sw_agg_prod = 0;
2436 }
2437}
2438
2439static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2440{
2441#ifdef CONFIG_RFS_ACCEL
2442 int i;
2443
2444 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2445 * safe to delete the hash table.
2446 */
2447 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2448 struct hlist_head *head;
2449 struct hlist_node *tmp;
2450 struct bnxt_ntuple_filter *fltr;
2451
2452 head = &bp->ntp_fltr_hash_tbl[i];
2453 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2454 hlist_del(&fltr->hash);
2455 kfree(fltr);
2456 }
2457 }
2458 if (irq_reinit) {
2459 kfree(bp->ntp_fltr_bmap);
2460 bp->ntp_fltr_bmap = NULL;
2461 }
2462 bp->ntp_fltr_count = 0;
2463#endif
2464}
2465
2466static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2467{
2468#ifdef CONFIG_RFS_ACCEL
2469 int i, rc = 0;
2470
2471 if (!(bp->flags & BNXT_FLAG_RFS))
2472 return 0;
2473
2474 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2475 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2476
2477 bp->ntp_fltr_count = 0;
2478 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2479 GFP_KERNEL);
2480
2481 if (!bp->ntp_fltr_bmap)
2482 rc = -ENOMEM;
2483
2484 return rc;
2485#else
2486 return 0;
2487#endif
2488}
2489
2490static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2491{
2492 bnxt_free_vnic_attributes(bp);
2493 bnxt_free_tx_rings(bp);
2494 bnxt_free_rx_rings(bp);
2495 bnxt_free_cp_rings(bp);
2496 bnxt_free_ntp_fltrs(bp, irq_re_init);
2497 if (irq_re_init) {
2498 bnxt_free_stats(bp);
2499 bnxt_free_ring_grps(bp);
2500 bnxt_free_vnics(bp);
2501 kfree(bp->bnapi);
2502 bp->bnapi = NULL;
2503 } else {
2504 bnxt_clear_ring_indices(bp);
2505 }
2506}
2507
2508static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2509{
2510 int i, rc, size, arr_size;
2511 void *bnapi;
2512
2513 if (irq_re_init) {
2514 /* Allocate bnapi mem pointer array and mem block for
2515 * all queues
2516 */
2517 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2518 bp->cp_nr_rings);
2519 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2520 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2521 if (!bnapi)
2522 return -ENOMEM;
2523
2524 bp->bnapi = bnapi;
2525 bnapi += arr_size;
2526 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2527 bp->bnapi[i] = bnapi;
2528 bp->bnapi[i]->index = i;
2529 bp->bnapi[i]->bp = bp;
2530 }
2531
2532 rc = bnxt_alloc_stats(bp);
2533 if (rc)
2534 goto alloc_mem_err;
2535
2536 rc = bnxt_alloc_ntp_fltrs(bp);
2537 if (rc)
2538 goto alloc_mem_err;
2539
2540 rc = bnxt_alloc_vnics(bp);
2541 if (rc)
2542 goto alloc_mem_err;
2543 }
2544
2545 bnxt_init_ring_struct(bp);
2546
2547 rc = bnxt_alloc_rx_rings(bp);
2548 if (rc)
2549 goto alloc_mem_err;
2550
2551 rc = bnxt_alloc_tx_rings(bp);
2552 if (rc)
2553 goto alloc_mem_err;
2554
2555 rc = bnxt_alloc_cp_rings(bp);
2556 if (rc)
2557 goto alloc_mem_err;
2558
2559 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2560 BNXT_VNIC_UCAST_FLAG;
2561 rc = bnxt_alloc_vnic_attributes(bp);
2562 if (rc)
2563 goto alloc_mem_err;
2564 return 0;
2565
2566alloc_mem_err:
2567 bnxt_free_mem(bp, true);
2568 return rc;
2569}
2570
2571void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2572 u16 cmpl_ring, u16 target_id)
2573{
2574 struct hwrm_cmd_req_hdr *req = request;
2575
2576 req->cmpl_ring_req_type =
2577 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2578 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2579 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2580}
2581
2582int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2583{
2584 int i, intr_process, rc;
2585 struct hwrm_cmd_req_hdr *req = msg;
2586 u32 *data = msg;
2587 __le32 *resp_len, *valid;
2588 u16 cp_ring_id, len = 0;
2589 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2590
2591 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2592 memset(resp, 0, PAGE_SIZE);
2593 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2594 HWRM_CMPL_RING_MASK) >>
2595 HWRM_CMPL_RING_SFT;
2596 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2597
2598 /* Write request msg to hwrm channel */
2599 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2600
2601 /* currently supports only one outstanding message */
2602 if (intr_process)
2603 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2604 HWRM_SEQ_ID_MASK;
2605
2606 /* Ring channel doorbell */
2607 writel(1, bp->bar0 + 0x100);
2608
2609 i = 0;
2610 if (intr_process) {
2611 /* Wait until hwrm response cmpl interrupt is processed */
2612 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2613 i++ < timeout) {
2614 usleep_range(600, 800);
2615 }
2616
2617 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2618 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2619 req->cmpl_ring_req_type);
2620 return -1;
2621 }
2622 } else {
2623 /* Check if response len is updated */
2624 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2625 for (i = 0; i < timeout; i++) {
2626 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2627 HWRM_RESP_LEN_SFT;
2628 if (len)
2629 break;
2630 usleep_range(600, 800);
2631 }
2632
2633 if (i >= timeout) {
2634 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2635 timeout, req->cmpl_ring_req_type,
2636 req->target_id_seq_id, *resp_len);
2637 return -1;
2638 }
2639
2640 /* Last word of resp contains valid bit */
2641 valid = bp->hwrm_cmd_resp_addr + len - 4;
2642 for (i = 0; i < timeout; i++) {
2643 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2644 break;
2645 usleep_range(600, 800);
2646 }
2647
2648 if (i >= timeout) {
2649 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2650 timeout, req->cmpl_ring_req_type,
2651 req->target_id_seq_id, len, *valid);
2652 return -1;
2653 }
2654 }
2655
2656 rc = le16_to_cpu(resp->error_code);
2657 if (rc) {
2658 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2659 le16_to_cpu(resp->req_type),
2660 le16_to_cpu(resp->seq_id), rc);
2661 return rc;
2662 }
2663 return 0;
2664}
2665
2666int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2667{
2668 int rc;
2669
2670 mutex_lock(&bp->hwrm_cmd_lock);
2671 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2672 mutex_unlock(&bp->hwrm_cmd_lock);
2673 return rc;
2674}
2675
2676static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2677{
2678 struct hwrm_func_drv_rgtr_input req = {0};
2679 int i;
2680
2681 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2682
2683 req.enables =
2684 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2685 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2686 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2687
2688 /* TODO: current async event fwd bits are not defined and the firmware
2689 * only checks if it is non-zero to enable async event forwarding
2690 */
2691 req.async_event_fwd[0] |= cpu_to_le32(1);
2692 req.os_type = cpu_to_le16(1);
2693 req.ver_maj = DRV_VER_MAJ;
2694 req.ver_min = DRV_VER_MIN;
2695 req.ver_upd = DRV_VER_UPD;
2696
2697 if (BNXT_PF(bp)) {
2698 unsigned long vf_req_snif_bmap[4];
2699 u32 *data = (u32 *)vf_req_snif_bmap;
2700
2701 memset(vf_req_snif_bmap, 0, 32);
2702 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2703 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2704
2705 for (i = 0; i < 8; i++) {
2706 req.vf_req_fwd[i] = cpu_to_le32(*data);
2707 data++;
2708 }
2709 req.enables |=
2710 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2711 }
2712
2713 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2714}
2715
2716static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2717{
2718 u32 rc = 0;
2719 struct hwrm_tunnel_dst_port_free_input req = {0};
2720
2721 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2722 req.tunnel_type = tunnel_type;
2723
2724 switch (tunnel_type) {
2725 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2726 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2727 break;
2728 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2729 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2730 break;
2731 default:
2732 break;
2733 }
2734
2735 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2736 if (rc)
2737 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2738 rc);
2739 return rc;
2740}
2741
2742static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2743 u8 tunnel_type)
2744{
2745 u32 rc = 0;
2746 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2747 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2748
2749 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2750
2751 req.tunnel_type = tunnel_type;
2752 req.tunnel_dst_port_val = port;
2753
2754 mutex_lock(&bp->hwrm_cmd_lock);
2755 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2756 if (rc) {
2757 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2758 rc);
2759 goto err_out;
2760 }
2761
2762 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2763 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2764
2765 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2766 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2767err_out:
2768 mutex_unlock(&bp->hwrm_cmd_lock);
2769 return rc;
2770}
2771
2772static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2773{
2774 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2775 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2776
2777 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2778 req.dflt_vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2779
2780 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2781 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2782 req.mask = cpu_to_le32(vnic->rx_mask);
2783 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2784}
2785
2786#ifdef CONFIG_RFS_ACCEL
2787static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2788 struct bnxt_ntuple_filter *fltr)
2789{
2790 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2791
2792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2793 req.ntuple_filter_id = fltr->filter_id;
2794 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2795}
2796
2797#define BNXT_NTP_FLTR_FLAGS \
2798 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2799 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2800 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2801 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2802 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2804 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2805 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2806 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2807 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2808 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2809 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2810 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2811 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID)
2812
2813static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2814 struct bnxt_ntuple_filter *fltr)
2815{
2816 int rc = 0;
2817 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2818 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2819 bp->hwrm_cmd_resp_addr;
2820 struct flow_keys *keys = &fltr->fkeys;
2821 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2822
2823 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2824 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2825
2826 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2827
2828 req.ethertype = htons(ETH_P_IP);
2829 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2830 req.ipaddr_type = 4;
2831 req.ip_protocol = keys->basic.ip_proto;
2832
2833 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2834 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2835 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2836 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2837
2838 req.src_port = keys->ports.src;
2839 req.src_port_mask = cpu_to_be16(0xffff);
2840 req.dst_port = keys->ports.dst;
2841 req.dst_port_mask = cpu_to_be16(0xffff);
2842
2843 req.dst_vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2844 mutex_lock(&bp->hwrm_cmd_lock);
2845 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2846 if (!rc)
2847 fltr->filter_id = resp->ntuple_filter_id;
2848 mutex_unlock(&bp->hwrm_cmd_lock);
2849 return rc;
2850}
2851#endif
2852
2853static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2854 u8 *mac_addr)
2855{
2856 u32 rc = 0;
2857 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2858 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2859
2860 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2861 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2862 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2863 req.dst_vnic_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2864 req.enables =
2865 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2866 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID |
2867 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2868 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2869 req.l2_addr_mask[0] = 0xff;
2870 req.l2_addr_mask[1] = 0xff;
2871 req.l2_addr_mask[2] = 0xff;
2872 req.l2_addr_mask[3] = 0xff;
2873 req.l2_addr_mask[4] = 0xff;
2874 req.l2_addr_mask[5] = 0xff;
2875
2876 mutex_lock(&bp->hwrm_cmd_lock);
2877 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2878 if (!rc)
2879 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2880 resp->l2_filter_id;
2881 mutex_unlock(&bp->hwrm_cmd_lock);
2882 return rc;
2883}
2884
2885static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2886{
2887 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2888 int rc = 0;
2889
2890 /* Any associated ntuple filters will also be cleared by firmware. */
2891 mutex_lock(&bp->hwrm_cmd_lock);
2892 for (i = 0; i < num_of_vnics; i++) {
2893 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2894
2895 for (j = 0; j < vnic->uc_filter_count; j++) {
2896 struct hwrm_cfa_l2_filter_free_input req = {0};
2897
2898 bnxt_hwrm_cmd_hdr_init(bp, &req,
2899 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2900
2901 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2902
2903 rc = _hwrm_send_message(bp, &req, sizeof(req),
2904 HWRM_CMD_TIMEOUT);
2905 }
2906 vnic->uc_filter_count = 0;
2907 }
2908 mutex_unlock(&bp->hwrm_cmd_lock);
2909
2910 return rc;
2911}
2912
2913static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2914{
2915 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2916 struct hwrm_vnic_tpa_cfg_input req = {0};
2917
2918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2919
2920 if (tpa_flags) {
2921 u16 mss = bp->dev->mtu - 40;
2922 u32 nsegs, n, segs = 0, flags;
2923
2924 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2925 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2926 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2927 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2928 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2929 if (tpa_flags & BNXT_FLAG_GRO)
2930 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2931
2932 req.flags = cpu_to_le32(flags);
2933
2934 req.enables =
2935 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2936 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS);
2937
2938 /* Number of segs are log2 units, and first packet is not
2939 * included as part of this units.
2940 */
2941 if (mss <= PAGE_SIZE) {
2942 n = PAGE_SIZE / mss;
2943 nsegs = (MAX_SKB_FRAGS - 1) * n;
2944 } else {
2945 n = mss / PAGE_SIZE;
2946 if (mss & (PAGE_SIZE - 1))
2947 n++;
2948 nsegs = (MAX_SKB_FRAGS - n) / n;
2949 }
2950
2951 segs = ilog2(nsegs);
2952 req.max_agg_segs = cpu_to_le16(segs);
2953 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2954 }
2955 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2956
2957 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2958}
2959
2960static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2961{
2962 u32 i, j, max_rings;
2963 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2964 struct hwrm_vnic_rss_cfg_input req = {0};
2965
2966 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2967 return 0;
2968
2969 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2970 if (set_rss) {
2971 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
2972 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
2973 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
2974 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
2975
2976 req.hash_type = cpu_to_le32(vnic->hash_type);
2977
2978 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2979 max_rings = bp->rx_nr_rings;
2980 else
2981 max_rings = 1;
2982
2983 /* Fill the RSS indirection table with ring group ids */
2984 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
2985 if (j == max_rings)
2986 j = 0;
2987 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
2988 }
2989
2990 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
2991 req.hash_key_tbl_addr =
2992 cpu_to_le64(vnic->rss_hash_key_dma_addr);
2993 }
2994 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
2995 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2996}
2997
2998static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
2999{
3000 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3001 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3002
3003 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3004 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3005 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3006 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3007 req.enables =
3008 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3009 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3010 /* thresholds not implemented in firmware yet */
3011 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3012 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3013 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3014 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3015}
3016
3017static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3018{
3019 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3020
3021 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3022 req.rss_cos_lb_ctx_id =
3023 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3024
3025 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3026 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3027}
3028
3029static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3030{
3031 int i;
3032
3033 for (i = 0; i < bp->nr_vnics; i++) {
3034 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3035
3036 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3037 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3038 }
3039 bp->rsscos_nr_ctxs = 0;
3040}
3041
3042static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3043{
3044 int rc;
3045 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3046 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3047 bp->hwrm_cmd_resp_addr;
3048
3049 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3050 -1);
3051
3052 mutex_lock(&bp->hwrm_cmd_lock);
3053 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3054 if (!rc)
3055 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3056 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3057 mutex_unlock(&bp->hwrm_cmd_lock);
3058
3059 return rc;
3060}
3061
3062static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3063{
3064 int grp_idx = 0;
3065 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3066 struct hwrm_vnic_cfg_input req = {0};
3067
3068 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3069 /* Only RSS support for now TBD: COS & LB */
3070 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3071 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3072 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3073 req.cos_rule = cpu_to_le16(0xffff);
3074 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3075 grp_idx = 0;
3076 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3077 grp_idx = vnic_id - 1;
3078
3079 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3080 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3081
3082 req.lb_rule = cpu_to_le16(0xffff);
3083 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3084 VLAN_HLEN);
3085
3086 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3087 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3088
3089 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3090}
3091
3092static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3093{
3094 u32 rc = 0;
3095
3096 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3097 struct hwrm_vnic_free_input req = {0};
3098
3099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3100 req.vnic_id =
3101 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3102
3103 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3104 if (rc)
3105 return rc;
3106 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3107 }
3108 return rc;
3109}
3110
3111static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3112{
3113 u16 i;
3114
3115 for (i = 0; i < bp->nr_vnics; i++)
3116 bnxt_hwrm_vnic_free_one(bp, i);
3117}
3118
3119static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, u16 start_grp_id,
3120 u16 end_grp_id)
3121{
3122 u32 rc = 0, i, j;
3123 struct hwrm_vnic_alloc_input req = {0};
3124 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3125
3126 /* map ring groups to this vnic */
3127 for (i = start_grp_id, j = 0; i < end_grp_id; i++, j++) {
3128 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) {
3129 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3130 j, (end_grp_id - start_grp_id));
3131 break;
3132 }
3133 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3134 bp->grp_info[i].fw_grp_id;
3135 }
3136
3137 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3138 if (vnic_id == 0)
3139 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3140
3141 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3142
3143 mutex_lock(&bp->hwrm_cmd_lock);
3144 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3145 if (!rc)
3146 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3147 mutex_unlock(&bp->hwrm_cmd_lock);
3148 return rc;
3149}
3150
3151static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3152{
3153 u16 i;
3154 u32 rc = 0;
3155
3156 mutex_lock(&bp->hwrm_cmd_lock);
3157 for (i = 0; i < bp->rx_nr_rings; i++) {
3158 struct hwrm_ring_grp_alloc_input req = {0};
3159 struct hwrm_ring_grp_alloc_output *resp =
3160 bp->hwrm_cmd_resp_addr;
3161
3162 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3163
3164 req.cr = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3165 req.rr = cpu_to_le16(bp->grp_info[i].rx_fw_ring_id);
3166 req.ar = cpu_to_le16(bp->grp_info[i].agg_fw_ring_id);
3167 req.sc = cpu_to_le16(bp->grp_info[i].fw_stats_ctx);
3168
3169 rc = _hwrm_send_message(bp, &req, sizeof(req),
3170 HWRM_CMD_TIMEOUT);
3171 if (rc)
3172 break;
3173
3174 bp->grp_info[i].fw_grp_id = le32_to_cpu(resp->ring_group_id);
3175 }
3176 mutex_unlock(&bp->hwrm_cmd_lock);
3177 return rc;
3178}
3179
3180static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3181{
3182 u16 i;
3183 u32 rc = 0;
3184 struct hwrm_ring_grp_free_input req = {0};
3185
3186 if (!bp->grp_info)
3187 return 0;
3188
3189 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3190
3191 mutex_lock(&bp->hwrm_cmd_lock);
3192 for (i = 0; i < bp->cp_nr_rings; i++) {
3193 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3194 continue;
3195 req.ring_group_id =
3196 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3197
3198 rc = _hwrm_send_message(bp, &req, sizeof(req),
3199 HWRM_CMD_TIMEOUT);
3200 if (rc)
3201 break;
3202 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3203 }
3204 mutex_unlock(&bp->hwrm_cmd_lock);
3205 return rc;
3206}
3207
3208static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3209 struct bnxt_ring_struct *ring,
3210 u32 ring_type, u32 map_index,
3211 u32 stats_ctx_id)
3212{
3213 int rc = 0, err = 0;
3214 struct hwrm_ring_alloc_input req = {0};
3215 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3216 u16 ring_id;
3217
3218 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3219
3220 req.enables = 0;
3221 if (ring->nr_pages > 1) {
3222 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3223 /* Page size is in log2 units */
3224 req.page_size = BNXT_PAGE_SHIFT;
3225 req.page_tbl_depth = 1;
3226 } else {
3227 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3228 }
3229 req.fbo = 0;
3230 /* Association of ring index with doorbell index and MSIX number */
3231 req.logical_id = cpu_to_le16(map_index);
3232
3233 switch (ring_type) {
3234 case HWRM_RING_ALLOC_TX:
3235 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3236 /* Association of transmit ring with completion ring */
3237 req.cmpl_ring_id =
3238 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3239 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3240 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3241 req.queue_id = cpu_to_le16(ring->queue_id);
3242 break;
3243 case HWRM_RING_ALLOC_RX:
3244 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3245 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3246 break;
3247 case HWRM_RING_ALLOC_AGG:
3248 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3249 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3250 break;
3251 case HWRM_RING_ALLOC_CMPL:
3252 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3253 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3254 if (bp->flags & BNXT_FLAG_USING_MSIX)
3255 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3256 break;
3257 default:
3258 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3259 ring_type);
3260 return -1;
3261 }
3262
3263 mutex_lock(&bp->hwrm_cmd_lock);
3264 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3265 err = le16_to_cpu(resp->error_code);
3266 ring_id = le16_to_cpu(resp->ring_id);
3267 mutex_unlock(&bp->hwrm_cmd_lock);
3268
3269 if (rc || err) {
3270 switch (ring_type) {
3271 case RING_FREE_REQ_RING_TYPE_CMPL:
3272 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3273 rc, err);
3274 return -1;
3275
3276 case RING_FREE_REQ_RING_TYPE_RX:
3277 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3278 rc, err);
3279 return -1;
3280
3281 case RING_FREE_REQ_RING_TYPE_TX:
3282 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3283 rc, err);
3284 return -1;
3285
3286 default:
3287 netdev_err(bp->dev, "Invalid ring\n");
3288 return -1;
3289 }
3290 }
3291 ring->fw_ring_id = ring_id;
3292 return rc;
3293}
3294
3295static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3296{
3297 int i, rc = 0;
3298
3299 if (bp->cp_nr_rings) {
3300 for (i = 0; i < bp->cp_nr_rings; i++) {
3301 struct bnxt_napi *bnapi = bp->bnapi[i];
3302 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3303 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3304
3305 rc = hwrm_ring_alloc_send_msg(bp, ring,
3306 HWRM_RING_ALLOC_CMPL, i,
3307 INVALID_STATS_CTX_ID);
3308 if (rc)
3309 goto err_out;
3310 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3311 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3312 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3313 }
3314 }
3315
3316 if (bp->tx_nr_rings) {
3317 for (i = 0; i < bp->tx_nr_rings; i++) {
3318 struct bnxt_napi *bnapi = bp->bnapi[i];
3319 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3320 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3321 u16 fw_stats_ctx = bp->grp_info[i].fw_stats_ctx;
3322
3323 rc = hwrm_ring_alloc_send_msg(bp, ring,
3324 HWRM_RING_ALLOC_TX, i,
3325 fw_stats_ctx);
3326 if (rc)
3327 goto err_out;
3328 txr->tx_doorbell = bp->bar1 + i * 0x80;
3329 }
3330 }
3331
3332 if (bp->rx_nr_rings) {
3333 for (i = 0; i < bp->rx_nr_rings; i++) {
3334 struct bnxt_napi *bnapi = bp->bnapi[i];
3335 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3336 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3337
3338 rc = hwrm_ring_alloc_send_msg(bp, ring,
3339 HWRM_RING_ALLOC_RX, i,
3340 INVALID_STATS_CTX_ID);
3341 if (rc)
3342 goto err_out;
3343 rxr->rx_doorbell = bp->bar1 + i * 0x80;
3344 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3345 bp->grp_info[i].rx_fw_ring_id = ring->fw_ring_id;
3346 }
3347 }
3348
3349 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3350 for (i = 0; i < bp->rx_nr_rings; i++) {
3351 struct bnxt_napi *bnapi = bp->bnapi[i];
3352 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3353 struct bnxt_ring_struct *ring =
3354 &rxr->rx_agg_ring_struct;
3355
3356 rc = hwrm_ring_alloc_send_msg(bp, ring,
3357 HWRM_RING_ALLOC_AGG,
3358 bp->rx_nr_rings + i,
3359 INVALID_STATS_CTX_ID);
3360 if (rc)
3361 goto err_out;
3362
3363 rxr->rx_agg_doorbell =
3364 bp->bar1 + (bp->rx_nr_rings + i) * 0x80;
3365 writel(DB_KEY_RX | rxr->rx_agg_prod,
3366 rxr->rx_agg_doorbell);
3367 bp->grp_info[i].agg_fw_ring_id = ring->fw_ring_id;
3368 }
3369 }
3370err_out:
3371 return rc;
3372}
3373
3374static int hwrm_ring_free_send_msg(struct bnxt *bp,
3375 struct bnxt_ring_struct *ring,
3376 u32 ring_type, int cmpl_ring_id)
3377{
3378 int rc;
3379 struct hwrm_ring_free_input req = {0};
3380 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3381 u16 error_code;
3382
3383 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3384 req.ring_type = ring_type;
3385 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3386
3387 mutex_lock(&bp->hwrm_cmd_lock);
3388 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3389 error_code = le16_to_cpu(resp->error_code);
3390 mutex_unlock(&bp->hwrm_cmd_lock);
3391
3392 if (rc || error_code) {
3393 switch (ring_type) {
3394 case RING_FREE_REQ_RING_TYPE_CMPL:
3395 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3396 rc);
3397 return rc;
3398 case RING_FREE_REQ_RING_TYPE_RX:
3399 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3400 rc);
3401 return rc;
3402 case RING_FREE_REQ_RING_TYPE_TX:
3403 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3404 rc);
3405 return rc;
3406 default:
3407 netdev_err(bp->dev, "Invalid ring\n");
3408 return -1;
3409 }
3410 }
3411 return 0;
3412}
3413
3414static int bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3415{
3416 int i, rc = 0;
3417
3418 if (!bp->bnapi)
3419 return 0;
3420
3421 if (bp->tx_nr_rings) {
3422 for (i = 0; i < bp->tx_nr_rings; i++) {
3423 struct bnxt_napi *bnapi = bp->bnapi[i];
3424 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3425 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3426 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3427
3428 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3429 hwrm_ring_free_send_msg(
3430 bp, ring,
3431 RING_FREE_REQ_RING_TYPE_TX,
3432 close_path ? cmpl_ring_id :
3433 INVALID_HW_RING_ID);
3434 ring->fw_ring_id = INVALID_HW_RING_ID;
3435 }
3436 }
3437 }
3438
3439 if (bp->rx_nr_rings) {
3440 for (i = 0; i < bp->rx_nr_rings; i++) {
3441 struct bnxt_napi *bnapi = bp->bnapi[i];
3442 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3443 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3444 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3445
3446 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3447 hwrm_ring_free_send_msg(
3448 bp, ring,
3449 RING_FREE_REQ_RING_TYPE_RX,
3450 close_path ? cmpl_ring_id :
3451 INVALID_HW_RING_ID);
3452 ring->fw_ring_id = INVALID_HW_RING_ID;
3453 bp->grp_info[i].rx_fw_ring_id =
3454 INVALID_HW_RING_ID;
3455 }
3456 }
3457 }
3458
3459 if (bp->rx_agg_nr_pages) {
3460 for (i = 0; i < bp->rx_nr_rings; i++) {
3461 struct bnxt_napi *bnapi = bp->bnapi[i];
3462 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3463 struct bnxt_ring_struct *ring =
3464 &rxr->rx_agg_ring_struct;
3465 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3466
3467 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3468 hwrm_ring_free_send_msg(
3469 bp, ring,
3470 RING_FREE_REQ_RING_TYPE_RX,
3471 close_path ? cmpl_ring_id :
3472 INVALID_HW_RING_ID);
3473 ring->fw_ring_id = INVALID_HW_RING_ID;
3474 bp->grp_info[i].agg_fw_ring_id =
3475 INVALID_HW_RING_ID;
3476 }
3477 }
3478 }
3479
3480 if (bp->cp_nr_rings) {
3481 for (i = 0; i < bp->cp_nr_rings; i++) {
3482 struct bnxt_napi *bnapi = bp->bnapi[i];
3483 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3484 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3485
3486 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3487 hwrm_ring_free_send_msg(
3488 bp, ring,
3489 RING_FREE_REQ_RING_TYPE_CMPL,
3490 INVALID_HW_RING_ID);
3491 ring->fw_ring_id = INVALID_HW_RING_ID;
3492 bp->grp_info[i].cp_fw_ring_id =
3493 INVALID_HW_RING_ID;
3494 }
3495 }
3496 }
3497
3498 return rc;
3499}
3500
3501int bnxt_hwrm_set_coal(struct bnxt *bp)
3502{
3503 int i, rc = 0;
3504 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3505 u16 max_buf, max_buf_irq;
3506 u16 buf_tmr, buf_tmr_irq;
3507 u32 flags;
3508
3509 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3510 -1, -1);
3511
3512 /* Each rx completion (2 records) should be DMAed immediately */
3513 max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3514 /* max_buf must not be zero */
3515 max_buf = clamp_t(u16, max_buf, 1, 63);
3516 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3517 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3518 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3519
3520 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3521
3522 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3523 * if coal_ticks is less than 25 us.
3524 */
3525 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3526 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3527
3528 req.flags = cpu_to_le16(flags);
3529 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3530 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3531 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3532 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3533 req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3534 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3535 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3536
3537 mutex_lock(&bp->hwrm_cmd_lock);
3538 for (i = 0; i < bp->cp_nr_rings; i++) {
3539 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3540
3541 rc = _hwrm_send_message(bp, &req, sizeof(req),
3542 HWRM_CMD_TIMEOUT);
3543 if (rc)
3544 break;
3545 }
3546 mutex_unlock(&bp->hwrm_cmd_lock);
3547 return rc;
3548}
3549
3550static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3551{
3552 int rc = 0, i;
3553 struct hwrm_stat_ctx_free_input req = {0};
3554
3555 if (!bp->bnapi)
3556 return 0;
3557
3558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3559
3560 mutex_lock(&bp->hwrm_cmd_lock);
3561 for (i = 0; i < bp->cp_nr_rings; i++) {
3562 struct bnxt_napi *bnapi = bp->bnapi[i];
3563 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3564
3565 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3566 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3567
3568 rc = _hwrm_send_message(bp, &req, sizeof(req),
3569 HWRM_CMD_TIMEOUT);
3570 if (rc)
3571 break;
3572
3573 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3574 }
3575 }
3576 mutex_unlock(&bp->hwrm_cmd_lock);
3577 return rc;
3578}
3579
3580static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3581{
3582 int rc = 0, i;
3583 struct hwrm_stat_ctx_alloc_input req = {0};
3584 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3585
3586 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3587
3588 req.update_period_ms = cpu_to_le32(1000);
3589
3590 mutex_lock(&bp->hwrm_cmd_lock);
3591 for (i = 0; i < bp->cp_nr_rings; i++) {
3592 struct bnxt_napi *bnapi = bp->bnapi[i];
3593 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3594
3595 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3596
3597 rc = _hwrm_send_message(bp, &req, sizeof(req),
3598 HWRM_CMD_TIMEOUT);
3599 if (rc)
3600 break;
3601
3602 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3603
3604 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3605 }
3606 mutex_unlock(&bp->hwrm_cmd_lock);
3607 return 0;
3608}
3609
3610static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3611{
3612 int rc = 0;
3613 struct hwrm_func_qcaps_input req = {0};
3614 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3615
3616 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3617 req.fid = cpu_to_le16(0xffff);
3618
3619 mutex_lock(&bp->hwrm_cmd_lock);
3620 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3621 if (rc)
3622 goto hwrm_func_qcaps_exit;
3623
3624 if (BNXT_PF(bp)) {
3625 struct bnxt_pf_info *pf = &bp->pf;
3626
3627 pf->fw_fid = le16_to_cpu(resp->fid);
3628 pf->port_id = le16_to_cpu(resp->port_id);
3629 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3630 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3631 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3632 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3633 pf->max_pf_tx_rings = pf->max_tx_rings;
3634 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3635 pf->max_pf_rx_rings = pf->max_rx_rings;
3636 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3637 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3638 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3639 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3640 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3641 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3642 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3643 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3644 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3645 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3646 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3647 } else {
379a80a1 3648#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 3649 struct bnxt_vf_info *vf = &bp->vf;
3650
3651 vf->fw_fid = le16_to_cpu(resp->fid);
3652 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3653 if (!is_valid_ether_addr(vf->mac_addr))
3654 random_ether_addr(vf->mac_addr);
3655
3656 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3657 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3658 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3659 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3660 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3661 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3662 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 3663#endif
c0c050c5
MC		 3664 }
3665
3666 bp->tx_push_thresh = 0;
3667 if (resp->flags &
3668 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3669 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3670
3671hwrm_func_qcaps_exit:
3672 mutex_unlock(&bp->hwrm_cmd_lock);
3673 return rc;
3674}
3675
3676static int bnxt_hwrm_func_reset(struct bnxt *bp)
3677{
3678 struct hwrm_func_reset_input req = {0};
3679
3680 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3681 req.enables = 0;
3682
3683 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3684}
3685
3686static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3687{
3688 int rc = 0;
3689 struct hwrm_queue_qportcfg_input req = {0};
3690 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3691 u8 i, *qptr;
3692
3693 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3694
3695 mutex_lock(&bp->hwrm_cmd_lock);
3696 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3697 if (rc)
3698 goto qportcfg_exit;
3699
3700 if (!resp->max_configurable_queues) {
3701 rc = -EINVAL;
3702 goto qportcfg_exit;
3703 }
3704 bp->max_tc = resp->max_configurable_queues;
3705 if (bp->max_tc > BNXT_MAX_QUEUE)
3706 bp->max_tc = BNXT_MAX_QUEUE;
3707
3708 qptr = &resp->queue_id0;
3709 for (i = 0; i < bp->max_tc; i++) {
3710 bp->q_info[i].queue_id = *qptr++;
3711 bp->q_info[i].queue_profile = *qptr++;
3712 }
3713
3714qportcfg_exit:
3715 mutex_unlock(&bp->hwrm_cmd_lock);
3716 return rc;
3717}
3718
3719static int bnxt_hwrm_ver_get(struct bnxt *bp)
3720{
3721 int rc;
3722 struct hwrm_ver_get_input req = {0};
3723 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3724
3725 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3726 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3727 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3728 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3729 mutex_lock(&bp->hwrm_cmd_lock);
3730 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3731 if (rc)
3732 goto hwrm_ver_get_exit;
3733
3734 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3735
3736 if (req.hwrm_intf_maj != resp->hwrm_intf_maj ||
3737 req.hwrm_intf_min != resp->hwrm_intf_min ||
3738 req.hwrm_intf_upd != resp->hwrm_intf_upd) {
3739 netdev_warn(bp->dev, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n",
3740 resp->hwrm_intf_maj, resp->hwrm_intf_min,
3741 resp->hwrm_intf_upd, req.hwrm_intf_maj,
3742 req.hwrm_intf_min, req.hwrm_intf_upd);
3743 netdev_warn(bp->dev, "Please update driver or firmware with matching interface versions.\n");
3744 }
3745 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3746 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3747 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3748
3749hwrm_ver_get_exit:
3750 mutex_unlock(&bp->hwrm_cmd_lock);
3751 return rc;
3752}
3753
3754static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3755{
3756 if (bp->vxlan_port_cnt) {
3757 bnxt_hwrm_tunnel_dst_port_free(
3758 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3759 }
3760 bp->vxlan_port_cnt = 0;
3761 if (bp->nge_port_cnt) {
3762 bnxt_hwrm_tunnel_dst_port_free(
3763 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3764 }
3765 bp->nge_port_cnt = 0;
3766}
3767
3768static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3769{
3770 int rc, i;
3771 u32 tpa_flags = 0;
3772
3773 if (set_tpa)
3774 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3775 for (i = 0; i < bp->nr_vnics; i++) {
3776 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3777 if (rc) {
3778 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3779 rc, i);
3780 return rc;
3781 }
3782 }
3783 return 0;
3784}
3785
3786static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3787{
3788 int i;
3789
3790 for (i = 0; i < bp->nr_vnics; i++)
3791 bnxt_hwrm_vnic_set_rss(bp, i, false);
3792}
3793
3794static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3795 bool irq_re_init)
3796{
3797 if (bp->vnic_info) {
3798 bnxt_hwrm_clear_vnic_filter(bp);
3799 /* clear all RSS setting before free vnic ctx */
3800 bnxt_hwrm_clear_vnic_rss(bp);
3801 bnxt_hwrm_vnic_ctx_free(bp);
3802 /* before free the vnic, undo the vnic tpa settings */
3803 if (bp->flags & BNXT_FLAG_TPA)
3804 bnxt_set_tpa(bp, false);
3805 bnxt_hwrm_vnic_free(bp);
3806 }
3807 bnxt_hwrm_ring_free(bp, close_path);
3808 bnxt_hwrm_ring_grp_free(bp);
3809 if (irq_re_init) {
3810 bnxt_hwrm_stat_ctx_free(bp);
3811 bnxt_hwrm_free_tunnel_ports(bp);
3812 }
3813}
3814
3815static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3816{
3817 int rc;
3818
3819 /* allocate context for vnic */
3820 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3821 if (rc) {
3822 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3823 vnic_id, rc);
3824 goto vnic_setup_err;
3825 }
3826 bp->rsscos_nr_ctxs++;
3827
3828 /* configure default vnic, ring grp */
3829 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3830 if (rc) {
3831 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3832 vnic_id, rc);
3833 goto vnic_setup_err;
3834 }
3835
3836 /* Enable RSS hashing on vnic */
3837 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3838 if (rc) {
3839 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3840 vnic_id, rc);
3841 goto vnic_setup_err;
3842 }
3843
3844 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3845 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3846 if (rc) {
3847 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3848 vnic_id, rc);
3849 }
3850 }
3851
3852vnic_setup_err:
3853 return rc;
3854}
3855
3856static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3857{
3858#ifdef CONFIG_RFS_ACCEL
3859 int i, rc = 0;
3860
3861 for (i = 0; i < bp->rx_nr_rings; i++) {
3862 u16 vnic_id = i + 1;
3863 u16 ring_id = i;
3864
3865 if (vnic_id >= bp->nr_vnics)
3866 break;
3867
3868 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3869 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, ring_id + 1);
3870 if (rc) {
3871 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3872 vnic_id, rc);
3873 break;
3874 }
3875 rc = bnxt_setup_vnic(bp, vnic_id);
3876 if (rc)
3877 break;
3878 }
3879 return rc;
3880#else
3881 return 0;
3882#endif
3883}
3884
c0c050c5
MC		 3885static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3886{
3887 int rc = 0;
3888
3889 if (irq_re_init) {
3890 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3891 if (rc) {
3892 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3893 rc);
3894 goto err_out;
3895 }
3896 }
3897
3898 rc = bnxt_hwrm_ring_alloc(bp);
3899 if (rc) {
3900 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3901 goto err_out;
3902 }
3903
3904 rc = bnxt_hwrm_ring_grp_alloc(bp);
3905 if (rc) {
3906 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3907 goto err_out;
3908 }
3909
3910 /* default vnic 0 */
3911 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3912 if (rc) {
3913 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3914 goto err_out;
3915 }
3916
3917 rc = bnxt_setup_vnic(bp, 0);
3918 if (rc)
3919 goto err_out;
3920
3921 if (bp->flags & BNXT_FLAG_RFS) {
3922 rc = bnxt_alloc_rfs_vnics(bp);
3923 if (rc)
3924 goto err_out;
3925 }
3926
3927 if (bp->flags & BNXT_FLAG_TPA) {
3928 rc = bnxt_set_tpa(bp, true);
3929 if (rc)
3930 goto err_out;
3931 }
3932
3933 if (BNXT_VF(bp))
3934 bnxt_update_vf_mac(bp);
3935
3936 /* Filter for default vnic 0 */
3937 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3938 if (rc) {
3939 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3940 goto err_out;
3941 }
3942 bp->vnic_info[0].uc_filter_count = 1;
3943
3944 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST |
3945 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3946
3947 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3948 bp->vnic_info[0].rx_mask |=
3949 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3950
3951 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
3952 if (rc) {
3953 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", rc);
3954 goto err_out;
3955 }
3956
3957 rc = bnxt_hwrm_set_coal(bp);
3958 if (rc)
3959 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3960 rc);
3961
3962 return 0;
3963
3964err_out:
3965 bnxt_hwrm_resource_free(bp, 0, true);
3966
3967 return rc;
3968}
3969
3970static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3971{
3972 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3973 return 0;
3974}
3975
3976static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3977{
3978 bnxt_init_rx_rings(bp);
3979 bnxt_init_tx_rings(bp);
3980 bnxt_init_ring_grps(bp, irq_re_init);
3981 bnxt_init_vnics(bp);
3982
3983 return bnxt_init_chip(bp, irq_re_init);
3984}
3985
3986static void bnxt_disable_int(struct bnxt *bp)
3987{
3988 int i;
3989
3990 if (!bp->bnapi)
3991 return;
3992
3993 for (i = 0; i < bp->cp_nr_rings; i++) {
3994 struct bnxt_napi *bnapi = bp->bnapi[i];
3995 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3996
3997 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3998 }
3999}
4000
4001static void bnxt_enable_int(struct bnxt *bp)
4002{
4003 int i;
4004
4005 atomic_set(&bp->intr_sem, 0);
4006 for (i = 0; i < bp->cp_nr_rings; i++) {
4007 struct bnxt_napi *bnapi = bp->bnapi[i];
4008 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4009
4010 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4011 }
4012}
4013
4014static int bnxt_set_real_num_queues(struct bnxt *bp)
4015{
4016 int rc;
4017 struct net_device *dev = bp->dev;
4018
4019 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4020 if (rc)
4021 return rc;
4022
4023 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4024 if (rc)
4025 return rc;
4026
4027#ifdef CONFIG_RFS_ACCEL
4028 if (bp->rx_nr_rings)
4029 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4030 if (!dev->rx_cpu_rmap)
4031 rc = -ENOMEM;
4032#endif
4033
4034 return rc;
4035}
4036
4037static int bnxt_setup_msix(struct bnxt *bp)
4038{
4039 struct msix_entry *msix_ent;
4040 struct net_device *dev = bp->dev;
4041 int i, total_vecs, rc = 0;
4042 const int len = sizeof(bp->irq_tbl[0].name);
4043
4044 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4045 total_vecs = bp->cp_nr_rings;
4046
4047 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4048 if (!msix_ent)
4049 return -ENOMEM;
4050
4051 for (i = 0; i < total_vecs; i++) {
4052 msix_ent[i].entry = i;
4053 msix_ent[i].vector = 0;
4054 }
4055
4056 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs);
4057 if (total_vecs < 0) {
4058 rc = -ENODEV;
4059 goto msix_setup_exit;
4060 }
4061
4062 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4063 if (bp->irq_tbl) {
4064 int tcs;
4065
4066 /* Trim rings based upon num of vectors allocated */
4067 bp->rx_nr_rings = min_t(int, total_vecs, bp->rx_nr_rings);
4068 bp->tx_nr_rings = min_t(int, total_vecs, bp->tx_nr_rings);
4069 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4070 tcs = netdev_get_num_tc(dev);
4071 if (tcs > 1) {
4072 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4073 if (bp->tx_nr_rings_per_tc == 0) {
4074 netdev_reset_tc(dev);
4075 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4076 } else {
4077 int i, off, count;
4078
4079 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4080 for (i = 0; i < tcs; i++) {
4081 count = bp->tx_nr_rings_per_tc;
4082 off = i * count;
4083 netdev_set_tc_queue(dev, i, count, off);
4084 }
4085 }
4086 }
4087 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
4088
4089 for (i = 0; i < bp->cp_nr_rings; i++) {
4090 bp->irq_tbl[i].vector = msix_ent[i].vector;
4091 snprintf(bp->irq_tbl[i].name, len,
4092 "%s-%s-%d", dev->name, "TxRx", i);
4093 bp->irq_tbl[i].handler = bnxt_msix;
4094 }
4095 rc = bnxt_set_real_num_queues(bp);
4096 if (rc)
4097 goto msix_setup_exit;
4098 } else {
4099 rc = -ENOMEM;
4100 goto msix_setup_exit;
4101 }
4102 bp->flags |= BNXT_FLAG_USING_MSIX;
4103 kfree(msix_ent);
4104 return 0;
4105
4106msix_setup_exit:
4107 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4108 pci_disable_msix(bp->pdev);
4109 kfree(msix_ent);
4110 return rc;
4111}
4112
4113static int bnxt_setup_inta(struct bnxt *bp)
4114{
4115 int rc;
4116 const int len = sizeof(bp->irq_tbl[0].name);
4117
4118 if (netdev_get_num_tc(bp->dev))
4119 netdev_reset_tc(bp->dev);
4120
4121 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4122 if (!bp->irq_tbl) {
4123 rc = -ENOMEM;
4124 return rc;
4125 }
4126 bp->rx_nr_rings = 1;
4127 bp->tx_nr_rings = 1;
4128 bp->cp_nr_rings = 1;
4129 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4130 bp->irq_tbl[0].vector = bp->pdev->irq;
4131 snprintf(bp->irq_tbl[0].name, len,
4132 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4133 bp->irq_tbl[0].handler = bnxt_inta;
4134 rc = bnxt_set_real_num_queues(bp);
4135 return rc;
4136}
4137
4138static int bnxt_setup_int_mode(struct bnxt *bp)
4139{
4140 int rc = 0;
4141
4142 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4143 rc = bnxt_setup_msix(bp);
4144
4145 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4146 /* fallback to INTA */
4147 rc = bnxt_setup_inta(bp);
4148 }
4149 return rc;
4150}
4151
4152static void bnxt_free_irq(struct bnxt *bp)
4153{
4154 struct bnxt_irq *irq;
4155 int i;
4156
4157#ifdef CONFIG_RFS_ACCEL
4158 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4159 bp->dev->rx_cpu_rmap = NULL;
4160#endif
4161 if (!bp->irq_tbl)
4162 return;
4163
4164 for (i = 0; i < bp->cp_nr_rings; i++) {
4165 irq = &bp->irq_tbl[i];
4166 if (irq->requested)
4167 free_irq(irq->vector, bp->bnapi[i]);
4168 irq->requested = 0;
4169 }
4170 if (bp->flags & BNXT_FLAG_USING_MSIX)
4171 pci_disable_msix(bp->pdev);
4172 kfree(bp->irq_tbl);
4173 bp->irq_tbl = NULL;
4174}
4175
4176static int bnxt_request_irq(struct bnxt *bp)
4177{
4178 int i, rc = 0;
4179 unsigned long flags = 0;
4180#ifdef CONFIG_RFS_ACCEL
4181 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4182#endif
4183
4184 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4185 flags = IRQF_SHARED;
4186
4187 for (i = 0; i < bp->cp_nr_rings; i++) {
4188 struct bnxt_irq *irq = &bp->irq_tbl[i];
4189#ifdef CONFIG_RFS_ACCEL
4190 if (rmap && (i < bp->rx_nr_rings)) {
4191 rc = irq_cpu_rmap_add(rmap, irq->vector);
4192 if (rc)
4193 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4194 i);
4195 }
4196#endif
4197 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4198 bp->bnapi[i]);
4199 if (rc)
4200 break;
4201
4202 irq->requested = 1;
4203 }
4204 return rc;
4205}
4206
4207static void bnxt_del_napi(struct bnxt *bp)
4208{
4209 int i;
4210
4211 if (!bp->bnapi)
4212 return;
4213
4214 for (i = 0; i < bp->cp_nr_rings; i++) {
4215 struct bnxt_napi *bnapi = bp->bnapi[i];
4216
4217 napi_hash_del(&bnapi->napi);
4218 netif_napi_del(&bnapi->napi);
4219 }
4220}
4221
4222static void bnxt_init_napi(struct bnxt *bp)
4223{
4224 int i;
4225 struct bnxt_napi *bnapi;
4226
4227 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4228 for (i = 0; i < bp->cp_nr_rings; i++) {
4229 bnapi = bp->bnapi[i];
4230 netif_napi_add(bp->dev, &bnapi->napi,
4231 bnxt_poll, 64);
4232 napi_hash_add(&bnapi->napi);
4233 }
4234 } else {
4235 bnapi = bp->bnapi[0];
4236 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4237 napi_hash_add(&bnapi->napi);
4238 }
4239}
4240
4241static void bnxt_disable_napi(struct bnxt *bp)
4242{
4243 int i;
4244
4245 if (!bp->bnapi)
4246 return;
4247
4248 for (i = 0; i < bp->cp_nr_rings; i++) {
4249 napi_disable(&bp->bnapi[i]->napi);
4250 bnxt_disable_poll(bp->bnapi[i]);
4251 }
4252}
4253
4254static void bnxt_enable_napi(struct bnxt *bp)
4255{
4256 int i;
4257
4258 for (i = 0; i < bp->cp_nr_rings; i++) {
4259 bnxt_enable_poll(bp->bnapi[i]);
4260 napi_enable(&bp->bnapi[i]->napi);
4261 }
4262}
4263
4264static void bnxt_tx_disable(struct bnxt *bp)
4265{
4266 int i;
4267 struct bnxt_napi *bnapi;
4268 struct bnxt_tx_ring_info *txr;
4269 struct netdev_queue *txq;
4270
4271 if (bp->bnapi) {
4272 for (i = 0; i < bp->tx_nr_rings; i++) {
4273 bnapi = bp->bnapi[i];
4274 txr = &bnapi->tx_ring;
4275 txq = netdev_get_tx_queue(bp->dev, i);
4276 __netif_tx_lock(txq, smp_processor_id());
4277 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4278 __netif_tx_unlock(txq);
4279 }
4280 }
4281 /* Stop all TX queues */
4282 netif_tx_disable(bp->dev);
4283 netif_carrier_off(bp->dev);
4284}
4285
4286static void bnxt_tx_enable(struct bnxt *bp)
4287{
4288 int i;
4289 struct bnxt_napi *bnapi;
4290 struct bnxt_tx_ring_info *txr;
4291 struct netdev_queue *txq;
4292
4293 for (i = 0; i < bp->tx_nr_rings; i++) {
4294 bnapi = bp->bnapi[i];
4295 txr = &bnapi->tx_ring;
4296 txq = netdev_get_tx_queue(bp->dev, i);
4297 txr->dev_state = 0;
4298 }
4299 netif_tx_wake_all_queues(bp->dev);
4300 if (bp->link_info.link_up)
4301 netif_carrier_on(bp->dev);
4302}
4303
4304static void bnxt_report_link(struct bnxt *bp)
4305{
4306 if (bp->link_info.link_up) {
4307 const char *duplex;
4308 const char *flow_ctrl;
4309 u16 speed;
4310
4311 netif_carrier_on(bp->dev);
4312 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4313 duplex = "full";
4314 else
4315 duplex = "half";
4316 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4317 flow_ctrl = "ON - receive & transmit";
4318 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4319 flow_ctrl = "ON - transmit";
4320 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4321 flow_ctrl = "ON - receive";
4322 else
4323 flow_ctrl = "none";
4324 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4325 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4326 speed, duplex, flow_ctrl);
4327 } else {
4328 netif_carrier_off(bp->dev);
4329 netdev_err(bp->dev, "NIC Link is Down\n");
4330 }
4331}
4332
4333static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4334{
4335 int rc = 0;
4336 struct bnxt_link_info *link_info = &bp->link_info;
4337 struct hwrm_port_phy_qcfg_input req = {0};
4338 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4339 u8 link_up = link_info->link_up;
4340
4341 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4342
4343 mutex_lock(&bp->hwrm_cmd_lock);
4344 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4345 if (rc) {
4346 mutex_unlock(&bp->hwrm_cmd_lock);
4347 return rc;
4348 }
4349
4350 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4351 link_info->phy_link_status = resp->link;
4352 link_info->duplex = resp->duplex;
4353 link_info->pause = resp->pause;
4354 link_info->auto_mode = resp->auto_mode;
4355 link_info->auto_pause_setting = resp->auto_pause;
4356 link_info->force_pause_setting = resp->force_pause;
4357 link_info->duplex_setting = resp->duplex_setting;
4358 if (link_info->phy_link_status == BNXT_LINK_LINK)
4359 link_info->link_speed = le16_to_cpu(resp->link_speed);
4360 else
4361 link_info->link_speed = 0;
4362 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4363 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4364 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4365 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4366 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4367 link_info->phy_ver[0] = resp->phy_maj;
4368 link_info->phy_ver[1] = resp->phy_min;
4369 link_info->phy_ver[2] = resp->phy_bld;
4370 link_info->media_type = resp->media_type;
4371 link_info->transceiver = resp->transceiver_type;
4372 link_info->phy_addr = resp->phy_addr;
4373
4374 /* TODO: need to add more logic to report VF link */
4375 if (chng_link_state) {
4376 if (link_info->phy_link_status == BNXT_LINK_LINK)
4377 link_info->link_up = 1;
4378 else
4379 link_info->link_up = 0;
4380 if (link_up != link_info->link_up)
4381 bnxt_report_link(bp);
4382 } else {
4383 /* alwasy link down if not require to update link state */
4384 link_info->link_up = 0;
4385 }
4386 mutex_unlock(&bp->hwrm_cmd_lock);
4387 return 0;
4388}
4389
4390static void
4391bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4392{
4393 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4394 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4395 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4396 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4397 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4398 req->enables |=
4399 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4400 } else {
4401 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4402 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4403 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4404 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4405 req->enables |=
4406 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4407 }
4408}
4409
4410static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4411 struct hwrm_port_phy_cfg_input *req)
4412{
4413 u8 autoneg = bp->link_info.autoneg;
4414 u16 fw_link_speed = bp->link_info.req_link_speed;
4415 u32 advertising = bp->link_info.advertising;
4416
4417 if (autoneg & BNXT_AUTONEG_SPEED) {
4418 req->auto_mode |=
4419 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4420
4421 req->enables |= cpu_to_le32(
4422 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4423 req->auto_link_speed_mask = cpu_to_le16(advertising);
4424
4425 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4426 req->flags |=
4427 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4428 } else {
4429 req->force_link_speed = cpu_to_le16(fw_link_speed);
4430 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4431 }
4432
4433 /* currently don't support half duplex */
4434 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4435 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4436 /* tell chimp that the setting takes effect immediately */
4437 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4438}
4439
4440int bnxt_hwrm_set_pause(struct bnxt *bp)
4441{
4442 struct hwrm_port_phy_cfg_input req = {0};
4443 int rc;
4444
4445 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4446 bnxt_hwrm_set_pause_common(bp, &req);
4447
4448 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4449 bp->link_info.force_link_chng)
4450 bnxt_hwrm_set_link_common(bp, &req);
4451
4452 mutex_lock(&bp->hwrm_cmd_lock);
4453 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4454 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4455 /* since changing of pause setting doesn't trigger any link
4456 * change event, the driver needs to update the current pause
4457 * result upon successfully return of the phy_cfg command
4458 */
4459 bp->link_info.pause =
4460 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4461 bp->link_info.auto_pause_setting = 0;
4462 if (!bp->link_info.force_link_chng)
4463 bnxt_report_link(bp);
4464 }
4465 bp->link_info.force_link_chng = false;
4466 mutex_unlock(&bp->hwrm_cmd_lock);
4467 return rc;
4468}
4469
4470int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4471{
4472 struct hwrm_port_phy_cfg_input req = {0};
4473
4474 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4475 if (set_pause)
4476 bnxt_hwrm_set_pause_common(bp, &req);
4477
4478 bnxt_hwrm_set_link_common(bp, &req);
4479 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4480}
4481
4482static int bnxt_update_phy_setting(struct bnxt *bp)
4483{
4484 int rc;
4485 bool update_link = false;
4486 bool update_pause = false;
4487 struct bnxt_link_info *link_info = &bp->link_info;
4488
4489 rc = bnxt_update_link(bp, true);
4490 if (rc) {
4491 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4492 rc);
4493 return rc;
4494 }
4495 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4496 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4497 update_pause = true;
4498 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4499 link_info->force_pause_setting != link_info->req_flow_ctrl)
4500 update_pause = true;
4501 if (link_info->req_duplex != link_info->duplex_setting)
4502 update_link = true;
4503 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4504 if (BNXT_AUTO_MODE(link_info->auto_mode))
4505 update_link = true;
4506 if (link_info->req_link_speed != link_info->force_link_speed)
4507 update_link = true;
4508 } else {
4509 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4510 update_link = true;
4511 if (link_info->advertising != link_info->auto_link_speeds)
4512 update_link = true;
4513 if (link_info->req_link_speed != link_info->auto_link_speed)
4514 update_link = true;
4515 }
4516
4517 if (update_link)
4518 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4519 else if (update_pause)
4520 rc = bnxt_hwrm_set_pause(bp);
4521 if (rc) {
4522 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4523 rc);
4524 return rc;
4525 }
4526
4527 return rc;
4528}
4529
4530static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4531{
4532 int rc = 0;
4533
4534 netif_carrier_off(bp->dev);
4535 if (irq_re_init) {
4536 rc = bnxt_setup_int_mode(bp);
4537 if (rc) {
4538 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4539 rc);
4540 return rc;
4541 }
4542 }
4543 if ((bp->flags & BNXT_FLAG_RFS) &&
4544 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4545 /* disable RFS if falling back to INTA */
4546 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4547 bp->flags &= ~BNXT_FLAG_RFS;
4548 }
4549
4550 rc = bnxt_alloc_mem(bp, irq_re_init);
4551 if (rc) {
4552 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4553 goto open_err_free_mem;
4554 }
4555
4556 if (irq_re_init) {
4557 bnxt_init_napi(bp);
4558 rc = bnxt_request_irq(bp);
4559 if (rc) {
4560 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4561 goto open_err;
4562 }
4563 }
4564
4565 bnxt_enable_napi(bp);
4566
4567 rc = bnxt_init_nic(bp, irq_re_init);
4568 if (rc) {
4569 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4570 goto open_err;
4571 }
4572
4573 if (link_re_init) {
4574 rc = bnxt_update_phy_setting(bp);
4575 if (rc)
4576 goto open_err;
4577 }
4578
4579 if (irq_re_init) {
4580#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4581 vxlan_get_rx_port(bp->dev);
4582#endif
4583 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4584 bp, htons(0x17c1),
4585 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4586 bp->nge_port_cnt = 1;
4587 }
4588
4589 bp->state = BNXT_STATE_OPEN;
4590 bnxt_enable_int(bp);
4591 /* Enable TX queues */
4592 bnxt_tx_enable(bp);
4593 mod_timer(&bp->timer, jiffies + bp->current_interval);
4594
4595 return 0;
4596
4597open_err:
4598 bnxt_disable_napi(bp);
4599 bnxt_del_napi(bp);
4600
4601open_err_free_mem:
4602 bnxt_free_skbs(bp);
4603 bnxt_free_irq(bp);
4604 bnxt_free_mem(bp, true);
4605 return rc;
4606}
4607
4608/* rtnl_lock held */
4609int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4610{
4611 int rc = 0;
4612
4613 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4614 if (rc) {
4615 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4616 dev_close(bp->dev);
4617 }
4618 return rc;
4619}
4620
4621static int bnxt_open(struct net_device *dev)
4622{
4623 struct bnxt *bp = netdev_priv(dev);
4624 int rc = 0;
4625
4626 rc = bnxt_hwrm_func_reset(bp);
4627 if (rc) {
4628 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4629 rc);
4630 rc = -1;
4631 return rc;
4632 }
4633 return __bnxt_open_nic(bp, true, true);
4634}
4635
4636static void bnxt_disable_int_sync(struct bnxt *bp)
4637{
4638 int i;
4639
4640 atomic_inc(&bp->intr_sem);
4641 if (!netif_running(bp->dev))
4642 return;
4643
4644 bnxt_disable_int(bp);
4645 for (i = 0; i < bp->cp_nr_rings; i++)
4646 synchronize_irq(bp->irq_tbl[i].vector);
4647}
4648
4649int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4650{
4651 int rc = 0;
4652
4653#ifdef CONFIG_BNXT_SRIOV
4654 if (bp->sriov_cfg) {
4655 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4656 !bp->sriov_cfg,
4657 BNXT_SRIOV_CFG_WAIT_TMO);
4658 if (rc)
4659 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4660 }
4661#endif
4662 /* Change device state to avoid TX queue wake up's */
4663 bnxt_tx_disable(bp);
4664
4665 bp->state = BNXT_STATE_CLOSED;
4666 cancel_work_sync(&bp->sp_task);
4667
4668 /* Flush rings before disabling interrupts */
4669 bnxt_shutdown_nic(bp, irq_re_init);
4670
4671 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4672
4673 bnxt_disable_napi(bp);
4674 bnxt_disable_int_sync(bp);
4675 del_timer_sync(&bp->timer);
4676 bnxt_free_skbs(bp);
4677
4678 if (irq_re_init) {
4679 bnxt_free_irq(bp);
4680 bnxt_del_napi(bp);
4681 }
4682 bnxt_free_mem(bp, irq_re_init);
4683 return rc;
4684}
4685
4686static int bnxt_close(struct net_device *dev)
4687{
4688 struct bnxt *bp = netdev_priv(dev);
4689
4690 bnxt_close_nic(bp, true, true);
4691 return 0;
4692}
4693
4694/* rtnl_lock held */
4695static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4696{
4697 switch (cmd) {
4698 case SIOCGMIIPHY:
4699 /* fallthru */
4700 case SIOCGMIIREG: {
4701 if (!netif_running(dev))
4702 return -EAGAIN;
4703
4704 return 0;
4705 }
4706
4707 case SIOCSMIIREG:
4708 if (!netif_running(dev))
4709 return -EAGAIN;
4710
4711 return 0;
4712
4713 default:
4714 /* do nothing */
4715 break;
4716 }
4717 return -EOPNOTSUPP;
4718}
4719
4720static struct rtnl_link_stats64 *
4721bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4722{
4723 u32 i;
4724 struct bnxt *bp = netdev_priv(dev);
4725
4726 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4727
4728 if (!bp->bnapi)
4729 return stats;
4730
4731 /* TODO check if we need to synchronize with bnxt_close path */
4732 for (i = 0; i < bp->cp_nr_rings; i++) {
4733 struct bnxt_napi *bnapi = bp->bnapi[i];
4734 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4735 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4736
4737 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4738 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4739 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4740
4741 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4742 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4743 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4744
4745 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4746 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4747 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4748
4749 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4750 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4751 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4752
4753 stats->rx_missed_errors +=
4754 le64_to_cpu(hw_stats->rx_discard_pkts);
4755
4756 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4757
4758 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4759
4760 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4761 }
4762
4763 return stats;
4764}
4765
4766static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4767{
4768 struct net_device *dev = bp->dev;
4769 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4770 struct netdev_hw_addr *ha;
4771 u8 *haddr;
4772 int mc_count = 0;
4773 bool update = false;
4774 int off = 0;
4775
4776 netdev_for_each_mc_addr(ha, dev) {
4777 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4778 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4779 vnic->mc_list_count = 0;
4780 return false;
4781 }
4782 haddr = ha->addr;
4783 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4784 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4785 update = true;
4786 }
4787 off += ETH_ALEN;
4788 mc_count++;
4789 }
4790 if (mc_count)
4791 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4792
4793 if (mc_count != vnic->mc_list_count) {
4794 vnic->mc_list_count = mc_count;
4795 update = true;
4796 }
4797 return update;
4798}
4799
4800static bool bnxt_uc_list_updated(struct bnxt *bp)
4801{
4802 struct net_device *dev = bp->dev;
4803 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4804 struct netdev_hw_addr *ha;
4805 int off = 0;
4806
4807 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4808 return true;
4809
4810 netdev_for_each_uc_addr(ha, dev) {
4811 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4812 return true;
4813
4814 off += ETH_ALEN;
4815 }
4816 return false;
4817}
4818
4819static void bnxt_set_rx_mode(struct net_device *dev)
4820{
4821 struct bnxt *bp = netdev_priv(dev);
4822 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4823 u32 mask = vnic->rx_mask;
4824 bool mc_update = false;
4825 bool uc_update;
4826
4827 if (!netif_running(dev))
4828 return;
4829
4830 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4831 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4832 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4833
4834 /* Only allow PF to be in promiscuous mode */
4835 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4836 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4837
4838 uc_update = bnxt_uc_list_updated(bp);
4839
4840 if (dev->flags & IFF_ALLMULTI) {
4841 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4842 vnic->mc_list_count = 0;
4843 } else {
4844 mc_update = bnxt_mc_list_updated(bp, &mask);
4845 }
4846
4847 if (mask != vnic->rx_mask || uc_update || mc_update) {
4848 vnic->rx_mask = mask;
4849
4850 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4851 schedule_work(&bp->sp_task);
4852 }
4853}
4854
4855static void bnxt_cfg_rx_mode(struct bnxt *bp)
4856{
4857 struct net_device *dev = bp->dev;
4858 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4859 struct netdev_hw_addr *ha;
4860 int i, off = 0, rc;
4861 bool uc_update;
4862
4863 netif_addr_lock_bh(dev);
4864 uc_update = bnxt_uc_list_updated(bp);
4865 netif_addr_unlock_bh(dev);
4866
4867 if (!uc_update)
4868 goto skip_uc;
4869
4870 mutex_lock(&bp->hwrm_cmd_lock);
4871 for (i = 1; i < vnic->uc_filter_count; i++) {
4872 struct hwrm_cfa_l2_filter_free_input req = {0};
4873
4874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4875 -1);
4876
4877 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4878
4879 rc = _hwrm_send_message(bp, &req, sizeof(req),
4880 HWRM_CMD_TIMEOUT);
4881 }
4882 mutex_unlock(&bp->hwrm_cmd_lock);
4883
4884 vnic->uc_filter_count = 1;
4885
4886 netif_addr_lock_bh(dev);
4887 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4888 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4889 } else {
4890 netdev_for_each_uc_addr(ha, dev) {
4891 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4892 off += ETH_ALEN;
4893 vnic->uc_filter_count++;
4894 }
4895 }
4896 netif_addr_unlock_bh(dev);
4897
4898 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4899 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4900 if (rc) {
4901 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4902 rc);
4903 vnic->uc_filter_count = i;
4904 }
4905 }
4906
4907skip_uc:
4908 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4909 if (rc)
4910 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4911 rc);
4912}
4913
4914static netdev_features_t bnxt_fix_features(struct net_device *dev,
4915 netdev_features_t features)
4916{
4917 return features;
4918}
4919
4920static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
4921{
4922 struct bnxt *bp = netdev_priv(dev);
4923 u32 flags = bp->flags;
4924 u32 changes;
4925 int rc = 0;
4926 bool re_init = false;
4927 bool update_tpa = false;
4928
4929 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
4930 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
4931 flags |= BNXT_FLAG_GRO;
4932 if (features & NETIF_F_LRO)
4933 flags |= BNXT_FLAG_LRO;
4934
4935 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4936 flags |= BNXT_FLAG_STRIP_VLAN;
4937
4938 if (features & NETIF_F_NTUPLE)
4939 flags |= BNXT_FLAG_RFS;
4940
4941 changes = flags ^ bp->flags;
4942 if (changes & BNXT_FLAG_TPA) {
4943 update_tpa = true;
4944 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
4945 (flags & BNXT_FLAG_TPA) == 0)
4946 re_init = true;
4947 }
4948
4949 if (changes & ~BNXT_FLAG_TPA)
4950 re_init = true;
4951
4952 if (flags != bp->flags) {
4953 u32 old_flags = bp->flags;
4954
4955 bp->flags = flags;
4956
4957 if (!netif_running(dev)) {
4958 if (update_tpa)
4959 bnxt_set_ring_params(bp);
4960 return rc;
4961 }
4962
4963 if (re_init) {
4964 bnxt_close_nic(bp, false, false);
4965 if (update_tpa)
4966 bnxt_set_ring_params(bp);
4967
4968 return bnxt_open_nic(bp, false, false);
4969 }
4970 if (update_tpa) {
4971 rc = bnxt_set_tpa(bp,
4972 (flags & BNXT_FLAG_TPA) ?
4973 true : false);
4974 if (rc)
4975 bp->flags = old_flags;
4976 }
4977 }
4978 return rc;
4979}
4980
4981static void bnxt_dbg_dump_states(struct bnxt *bp)
4982{
4983 int i;
4984 struct bnxt_napi *bnapi;
4985 struct bnxt_tx_ring_info *txr;
4986 struct bnxt_rx_ring_info *rxr;
4987 struct bnxt_cp_ring_info *cpr;
4988
4989 for (i = 0; i < bp->cp_nr_rings; i++) {
4990 bnapi = bp->bnapi[i];
4991 txr = &bnapi->tx_ring;
4992 rxr = &bnapi->rx_ring;
4993 cpr = &bnapi->cp_ring;
4994 if (netif_msg_drv(bp)) {
4995 netdev_info(bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
4996 i, txr->tx_ring_struct.fw_ring_id,
4997 txr->tx_prod, txr->tx_cons);
4998 netdev_info(bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
4999 i, rxr->rx_ring_struct.fw_ring_id,
5000 rxr->rx_prod,
5001 rxr->rx_agg_ring_struct.fw_ring_id,
5002 rxr->rx_agg_prod, rxr->rx_sw_agg_prod);
5003 netdev_info(bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5004 i, cpr->cp_ring_struct.fw_ring_id,
5005 cpr->cp_raw_cons);
5006 }
5007 }
5008}
5009
5010static void bnxt_reset_task(struct bnxt *bp)
5011{
5012 bnxt_dbg_dump_states(bp);
5013 if (netif_running(bp->dev))
5014 bnxt_tx_disable(bp); /* prevent tx timout again */
5015}
5016
5017static void bnxt_tx_timeout(struct net_device *dev)
5018{
5019 struct bnxt *bp = netdev_priv(dev);
5020
5021 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5022 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5023 schedule_work(&bp->sp_task);
5024}
5025
5026#ifdef CONFIG_NET_POLL_CONTROLLER
5027static void bnxt_poll_controller(struct net_device *dev)
5028{
5029 struct bnxt *bp = netdev_priv(dev);
5030 int i;
5031
5032 for (i = 0; i < bp->cp_nr_rings; i++) {
5033 struct bnxt_irq *irq = &bp->irq_tbl[i];
5034
5035 disable_irq(irq->vector);
5036 irq->handler(irq->vector, bp->bnapi[i]);
5037 enable_irq(irq->vector);
5038 }
5039}
5040#endif
5041
5042static void bnxt_timer(unsigned long data)
5043{
5044 struct bnxt *bp = (struct bnxt *)data;
5045 struct net_device *dev = bp->dev;
5046
5047 if (!netif_running(dev))
5048 return;
5049
5050 if (atomic_read(&bp->intr_sem) != 0)
5051 goto bnxt_restart_timer;
5052
5053bnxt_restart_timer:
5054 mod_timer(&bp->timer, jiffies + bp->current_interval);
5055}
5056
5057static void bnxt_cfg_ntp_filters(struct bnxt *);
5058
5059static void bnxt_sp_task(struct work_struct *work)
5060{
5061 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5062 int rc;
5063
5064 if (bp->state != BNXT_STATE_OPEN)
5065 return;
5066
5067 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5068 bnxt_cfg_rx_mode(bp);
5069
5070 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5071 bnxt_cfg_ntp_filters(bp);
5072 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5073 rc = bnxt_update_link(bp, true);
5074 if (rc)
5075 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5076 rc);
5077 }
5078 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5079 bnxt_hwrm_exec_fwd_req(bp);
5080 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5081 bnxt_hwrm_tunnel_dst_port_alloc(
5082 bp, bp->vxlan_port,
5083 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5084 }
5085 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5086 bnxt_hwrm_tunnel_dst_port_free(
5087 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5088 }
5089 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5090 bnxt_reset_task(bp);
5091}
5092
5093static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5094{
5095 int rc;
5096 struct bnxt *bp = netdev_priv(dev);
5097
5098 SET_NETDEV_DEV(dev, &pdev->dev);
5099
5100 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5101 rc = pci_enable_device(pdev);
5102 if (rc) {
5103 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5104 goto init_err;
5105 }
5106
5107 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5108 dev_err(&pdev->dev,
5109 "Cannot find PCI device base address, aborting\n");
5110 rc = -ENODEV;
5111 goto init_err_disable;
5112 }
5113
5114 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5115 if (rc) {
5116 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5117 goto init_err_disable;
5118 }
5119
5120 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5121 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5122 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5123 goto init_err_disable;
5124 }
5125
5126 pci_set_master(pdev);
5127
5128 bp->dev = dev;
5129 bp->pdev = pdev;
5130
5131 bp->bar0 = pci_ioremap_bar(pdev, 0);
5132 if (!bp->bar0) {
5133 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5134 rc = -ENOMEM;
5135 goto init_err_release;
5136 }
5137
5138 bp->bar1 = pci_ioremap_bar(pdev, 2);
5139 if (!bp->bar1) {
5140 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5141 rc = -ENOMEM;
5142 goto init_err_release;
5143 }
5144
5145 bp->bar2 = pci_ioremap_bar(pdev, 4);
5146 if (!bp->bar2) {
5147 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5148 rc = -ENOMEM;
5149 goto init_err_release;
5150 }
5151
5152 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5153
5154 spin_lock_init(&bp->ntp_fltr_lock);
5155
5156 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5157 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5158
5159 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5160 bp->coal_bufs = 20;
5161 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5162 bp->coal_bufs_irq = 2;
5163
5164 init_timer(&bp->timer);
5165 bp->timer.data = (unsigned long)bp;
5166 bp->timer.function = bnxt_timer;
5167 bp->current_interval = BNXT_TIMER_INTERVAL;
5168
5169 bp->state = BNXT_STATE_CLOSED;
5170
5171 return 0;
5172
5173init_err_release:
5174 if (bp->bar2) {
5175 pci_iounmap(pdev, bp->bar2);
5176 bp->bar2 = NULL;
5177 }
5178
5179 if (bp->bar1) {
5180 pci_iounmap(pdev, bp->bar1);
5181 bp->bar1 = NULL;
5182 }
5183
5184 if (bp->bar0) {
5185 pci_iounmap(pdev, bp->bar0);
5186 bp->bar0 = NULL;
5187 }
5188
5189 pci_release_regions(pdev);
5190
5191init_err_disable:
5192 pci_disable_device(pdev);
5193
5194init_err:
5195 return rc;
5196}
5197
5198/* rtnl_lock held */
5199static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5200{
5201 struct sockaddr *addr = p;
5202
5203 if (!is_valid_ether_addr(addr->sa_data))
5204 return -EADDRNOTAVAIL;
5205
5206 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5207
5208 return 0;
5209}
5210
5211/* rtnl_lock held */
5212static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5213{
5214 struct bnxt *bp = netdev_priv(dev);
5215
5216 if (new_mtu < 60 || new_mtu > 9000)
5217 return -EINVAL;
5218
5219 if (netif_running(dev))
5220 bnxt_close_nic(bp, false, false);
5221
5222 dev->mtu = new_mtu;
5223 bnxt_set_ring_params(bp);
5224
5225 if (netif_running(dev))
5226 return bnxt_open_nic(bp, false, false);
5227
5228 return 0;
5229}
5230
5231static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5232{
5233 struct bnxt *bp = netdev_priv(dev);
5234
5235 if (tc > bp->max_tc) {
5236 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5237 tc, bp->max_tc);
5238 return -EINVAL;
5239 }
5240
5241 if (netdev_get_num_tc(dev) == tc)
5242 return 0;
5243
5244 if (tc) {
5245 int max_rx_rings, max_tx_rings;
5246
5247 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5248 if (bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5249 return -ENOMEM;
5250 }
5251
5252 /* Needs to close the device and do hw resource re-allocations */
5253 if (netif_running(bp->dev))
5254 bnxt_close_nic(bp, true, false);
5255
5256 if (tc) {
5257 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5258 netdev_set_num_tc(dev, tc);
5259 } else {
5260 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5261 netdev_reset_tc(dev);
5262 }
5263 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5264 bp->num_stat_ctxs = bp->cp_nr_rings;
5265
5266 if (netif_running(bp->dev))
5267 return bnxt_open_nic(bp, true, false);
5268
5269 return 0;
5270}
5271
5272#ifdef CONFIG_RFS_ACCEL
5273static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5274 struct bnxt_ntuple_filter *f2)
5275{
5276 struct flow_keys *keys1 = &f1->fkeys;
5277 struct flow_keys *keys2 = &f2->fkeys;
5278
5279 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5280 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5281 keys1->ports.ports == keys2->ports.ports &&
5282 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5283 keys1->basic.n_proto == keys2->basic.n_proto &&
5284 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5285 return true;
5286
5287 return false;
5288}
5289
5290static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5291 u16 rxq_index, u32 flow_id)
5292{
5293 struct bnxt *bp = netdev_priv(dev);
5294 struct bnxt_ntuple_filter *fltr, *new_fltr;
5295 struct flow_keys *fkeys;
5296 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5297 int rc = 0, idx;
5298 struct hlist_head *head;
5299
5300 if (skb->encapsulation)
5301 return -EPROTONOSUPPORT;
5302
5303 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5304 if (!new_fltr)
5305 return -ENOMEM;
5306
5307 fkeys = &new_fltr->fkeys;
5308 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5309 rc = -EPROTONOSUPPORT;
5310 goto err_free;
5311 }
5312
5313 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5314 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5315 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5316 rc = -EPROTONOSUPPORT;
5317 goto err_free;
5318 }
5319
5320 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5321
5322 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5323 head = &bp->ntp_fltr_hash_tbl[idx];
5324 rcu_read_lock();
5325 hlist_for_each_entry_rcu(fltr, head, hash) {
5326 if (bnxt_fltr_match(fltr, new_fltr)) {
5327 rcu_read_unlock();
5328 rc = 0;
5329 goto err_free;
5330 }
5331 }
5332 rcu_read_unlock();
5333
5334 spin_lock_bh(&bp->ntp_fltr_lock);
5335 new_fltr->sw_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5336 BNXT_NTP_FLTR_MAX_FLTR, 0);
5337 if (new_fltr->sw_id < 0) {
5338 spin_unlock_bh(&bp->ntp_fltr_lock);
5339 rc = -ENOMEM;
5340 goto err_free;
5341 }
5342
5343 new_fltr->flow_id = flow_id;
5344 new_fltr->rxq = rxq_index;
5345 hlist_add_head_rcu(&new_fltr->hash, head);
5346 bp->ntp_fltr_count++;
5347 spin_unlock_bh(&bp->ntp_fltr_lock);
5348
5349 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5350 schedule_work(&bp->sp_task);
5351
5352 return new_fltr->sw_id;
5353
5354err_free:
5355 kfree(new_fltr);
5356 return rc;
5357}
5358
5359static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5360{
5361 int i;
5362
5363 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5364 struct hlist_head *head;
5365 struct hlist_node *tmp;
5366 struct bnxt_ntuple_filter *fltr;
5367 int rc;
5368
5369 head = &bp->ntp_fltr_hash_tbl[i];
5370 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5371 bool del = false;
5372
5373 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5374 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5375 fltr->flow_id,
5376 fltr->sw_id)) {
5377 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5378 fltr);
5379 del = true;
5380 }
5381 } else {
5382 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5383 fltr);
5384 if (rc)
5385 del = true;
5386 else
5387 set_bit(BNXT_FLTR_VALID, &fltr->state);
5388 }
5389
5390 if (del) {
5391 spin_lock_bh(&bp->ntp_fltr_lock);
5392 hlist_del_rcu(&fltr->hash);
5393 bp->ntp_fltr_count--;
5394 spin_unlock_bh(&bp->ntp_fltr_lock);
5395 synchronize_rcu();
5396 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5397 kfree(fltr);
5398 }
5399 }
5400 }
5401}
5402
5403#else
5404
5405static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5406{
5407}
5408
5409#endif /* CONFIG_RFS_ACCEL */
5410
5411static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5412 __be16 port)
5413{
5414 struct bnxt *bp = netdev_priv(dev);
5415
5416 if (!netif_running(dev))
5417 return;
5418
5419 if (sa_family != AF_INET6 && sa_family != AF_INET)
5420 return;
5421
5422 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5423 return;
5424
5425 bp->vxlan_port_cnt++;
5426 if (bp->vxlan_port_cnt == 1) {
5427 bp->vxlan_port = port;
5428 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5429 schedule_work(&bp->sp_task);
5430 }
5431}
5432
5433static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5434 __be16 port)
5435{
5436 struct bnxt *bp = netdev_priv(dev);
5437
5438 if (!netif_running(dev))
5439 return;
5440
5441 if (sa_family != AF_INET6 && sa_family != AF_INET)
5442 return;
5443
5444 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5445 bp->vxlan_port_cnt--;
5446
5447 if (bp->vxlan_port_cnt == 0) {
5448 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5449 schedule_work(&bp->sp_task);
5450 }
5451 }
5452}
5453
5454static const struct net_device_ops bnxt_netdev_ops = {
5455 .ndo_open = bnxt_open,
5456 .ndo_start_xmit = bnxt_start_xmit,
5457 .ndo_stop = bnxt_close,
5458 .ndo_get_stats64 = bnxt_get_stats64,
5459 .ndo_set_rx_mode = bnxt_set_rx_mode,
5460 .ndo_do_ioctl = bnxt_ioctl,
5461 .ndo_validate_addr = eth_validate_addr,
5462 .ndo_set_mac_address = bnxt_change_mac_addr,
5463 .ndo_change_mtu = bnxt_change_mtu,
5464 .ndo_fix_features = bnxt_fix_features,
5465 .ndo_set_features = bnxt_set_features,
5466 .ndo_tx_timeout = bnxt_tx_timeout,
5467#ifdef CONFIG_BNXT_SRIOV
5468 .ndo_get_vf_config = bnxt_get_vf_config,
5469 .ndo_set_vf_mac = bnxt_set_vf_mac,
5470 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5471 .ndo_set_vf_rate = bnxt_set_vf_bw,
5472 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5473 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5474#endif
5475#ifdef CONFIG_NET_POLL_CONTROLLER
5476 .ndo_poll_controller = bnxt_poll_controller,
5477#endif
5478 .ndo_setup_tc = bnxt_setup_tc,
5479#ifdef CONFIG_RFS_ACCEL
5480 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5481#endif
5482 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5483 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5484#ifdef CONFIG_NET_RX_BUSY_POLL
5485 .ndo_busy_poll = bnxt_busy_poll,
5486#endif
5487};
5488
5489static void bnxt_remove_one(struct pci_dev *pdev)
5490{
5491 struct net_device *dev = pci_get_drvdata(pdev);
5492 struct bnxt *bp = netdev_priv(dev);
5493
5494 if (BNXT_PF(bp))
5495 bnxt_sriov_disable(bp);
5496
5497 unregister_netdev(dev);
5498 cancel_work_sync(&bp->sp_task);
5499 bp->sp_event = 0;
5500
5501 bnxt_free_hwrm_resources(bp);
5502 pci_iounmap(pdev, bp->bar2);
5503 pci_iounmap(pdev, bp->bar1);
5504 pci_iounmap(pdev, bp->bar0);
5505 free_netdev(dev);
5506
5507 pci_release_regions(pdev);
5508 pci_disable_device(pdev);
5509}
5510
5511static int bnxt_probe_phy(struct bnxt *bp)
5512{
5513 int rc = 0;
5514 struct bnxt_link_info *link_info = &bp->link_info;
5515 char phy_ver[PHY_VER_STR_LEN];
5516
5517 rc = bnxt_update_link(bp, false);
5518 if (rc) {
5519 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5520 rc);
5521 return rc;
5522 }
5523
5524 /*initialize the ethool setting copy with NVM settings */
5525 if (BNXT_AUTO_MODE(link_info->auto_mode))
5526 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5527
5528 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5529 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5530 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5531 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5532 } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5533 link_info->req_flow_ctrl = link_info->force_pause_setting;
5534 }
5535 link_info->req_duplex = link_info->duplex_setting;
5536 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5537 link_info->req_link_speed = link_info->auto_link_speed;
5538 else
5539 link_info->req_link_speed = link_info->force_link_speed;
5540 link_info->advertising = link_info->auto_link_speeds;
5541 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5542 link_info->phy_ver[0],
5543 link_info->phy_ver[1],
5544 link_info->phy_ver[2]);
5545 strcat(bp->fw_ver_str, phy_ver);
5546 return rc;
5547}
5548
5549static int bnxt_get_max_irq(struct pci_dev *pdev)
5550{
5551 u16 ctrl;
5552
5553 if (!pdev->msix_cap)
5554 return 1;
5555
5556 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5557 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5558}
5559
5560void bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx)
5561{
379a80a1 5562 int max_rings = 0;
c0c050c5
MC		 5563
5564 if (BNXT_PF(bp)) {
5565 *max_tx = bp->pf.max_pf_tx_rings;
5566 *max_rx = bp->pf.max_pf_rx_rings;
5567 max_rings = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5568 max_rings = min_t(int, max_rings, bp->pf.max_stat_ctxs);
5569 } else {
379a80a1 5570#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 5571 *max_tx = bp->vf.max_tx_rings;
5572 *max_rx = bp->vf.max_rx_rings;
5573 max_rings = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5574 max_rings = min_t(int, max_rings, bp->vf.max_stat_ctxs);
379a80a1 5575#endif
c0c050c5
MC		 5576 }
5577 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5578 *max_rx >>= 1;
5579
5580 *max_rx = min_t(int, *max_rx, max_rings);
5581 *max_tx = min_t(int, *max_tx, max_rings);
5582}
5583
5584static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5585{
5586 static int version_printed;
5587 struct net_device *dev;
5588 struct bnxt *bp;
5589 int rc, max_rx_rings, max_tx_rings, max_irqs, dflt_rings;
5590
5591 if (version_printed++ == 0)
5592 pr_info("%s", version);
5593
5594 max_irqs = bnxt_get_max_irq(pdev);
5595 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5596 if (!dev)
5597 return -ENOMEM;
5598
5599 bp = netdev_priv(dev);
5600
5601 if (bnxt_vf_pciid(ent->driver_data))
5602 bp->flags |= BNXT_FLAG_VF;
5603
5604 if (pdev->msix_cap) {
5605 bp->flags |= BNXT_FLAG_MSIX_CAP;
5606 if (BNXT_PF(bp))
5607 bp->flags |= BNXT_FLAG_RFS;
5608 }
5609
5610 rc = bnxt_init_board(pdev, dev);
5611 if (rc < 0)
5612 goto init_err_free;
5613
5614 dev->netdev_ops = &bnxt_netdev_ops;
5615 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5616 dev->ethtool_ops = &bnxt_ethtool_ops;
5617
5618 pci_set_drvdata(pdev, dev);
5619
5620 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5621 NETIF_F_TSO | NETIF_F_TSO6 |
5622 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5623 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5624 NETIF_F_RXHASH |
5625 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5626
5627 if (bp->flags & BNXT_FLAG_RFS)
5628 dev->hw_features |= NETIF_F_NTUPLE;
5629
5630 dev->hw_enc_features =
5631 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5632 NETIF_F_TSO | NETIF_F_TSO6 |
5633 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5634 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5635 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5636 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5637 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5638 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5639 dev->priv_flags |= IFF_UNICAST_FLT;
5640
5641#ifdef CONFIG_BNXT_SRIOV
5642 init_waitqueue_head(&bp->sriov_cfg_wait);
5643#endif
5644 rc = bnxt_alloc_hwrm_resources(bp);
5645 if (rc)
5646 goto init_err;
5647
5648 mutex_init(&bp->hwrm_cmd_lock);
5649 bnxt_hwrm_ver_get(bp);
5650
5651 rc = bnxt_hwrm_func_drv_rgtr(bp);
5652 if (rc)
5653 goto init_err;
5654
5655 /* Get the MAX capabilities for this function */
5656 rc = bnxt_hwrm_func_qcaps(bp);
5657 if (rc) {
5658 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5659 rc);
5660 rc = -1;
5661 goto init_err;
5662 }
5663
5664 rc = bnxt_hwrm_queue_qportcfg(bp);
5665 if (rc) {
5666 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5667 rc);
5668 rc = -1;
5669 goto init_err;
5670 }
5671
5672 bnxt_set_tpa_flags(bp);
5673 bnxt_set_ring_params(bp);
5674 dflt_rings = netif_get_num_default_rss_queues();
5675 if (BNXT_PF(bp)) {
5676 memcpy(dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
5677 bp->pf.max_irqs = max_irqs;
5678 } else {
379a80a1 5679#if defined(CONFIG_BNXT_SRIOV)
c0c050c5
MC		 5680 memcpy(dev->dev_addr, bp->vf.mac_addr, ETH_ALEN);
5681 bp->vf.max_irqs = max_irqs;
379a80a1 5682#endif
c0c050c5
MC		 5683 }
5684 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5685 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5686 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5687 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5688 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
5689 bp->num_stat_ctxs = bp->cp_nr_rings;
5690
5691 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5692 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5693
5694 rc = bnxt_probe_phy(bp);
5695 if (rc)
5696 goto init_err;
5697
5698 rc = register_netdev(dev);
5699 if (rc)
5700 goto init_err;
5701
5702 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5703 board_info[ent->driver_data].name,
5704 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5705
5706 return 0;
5707
5708init_err:
5709 pci_iounmap(pdev, bp->bar0);
5710 pci_release_regions(pdev);
5711 pci_disable_device(pdev);
5712
5713init_err_free:
5714 free_netdev(dev);
5715 return rc;
5716}
5717
5718static struct pci_driver bnxt_pci_driver = {
5719 .name = DRV_MODULE_NAME,
5720 .id_table = bnxt_pci_tbl,
5721 .probe = bnxt_init_one,
5722 .remove = bnxt_remove_one,
5723#if defined(CONFIG_BNXT_SRIOV)
5724 .sriov_configure = bnxt_sriov_configure,
5725#endif
5726};
5727
5728module_pci_driver(bnxt_pci_driver);
Linux kernel - Deliverables
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