Commit | Line | Data |
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8b230ed8 | 1 | /* |
2732ba56 | 2 | * Linux network driver for QLogic BR-series Converged Network Adapter. |
8b230ed8 RM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
2732ba56 RM |
14 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
15 | * Copyright (c) 2014-2015 QLogic Corporation | |
8b230ed8 | 16 | * All rights reserved |
2732ba56 | 17 | * www.qlogic.com |
8b230ed8 RM |
18 | */ |
19 | #ifndef __BNA_TYPES_H__ | |
20 | #define __BNA_TYPES_H__ | |
21 | ||
22 | #include "cna.h" | |
078086f3 | 23 | #include "bna_hw_defs.h" |
8b230ed8 | 24 | #include "bfa_cee.h" |
078086f3 | 25 | #include "bfa_msgq.h" |
8b230ed8 | 26 | |
1aa8b471 | 27 | /* Forward declarations */ |
8b230ed8 | 28 | |
078086f3 | 29 | struct bna_mcam_handle; |
8b230ed8 RM |
30 | struct bna_txq; |
31 | struct bna_tx; | |
32 | struct bna_rxq; | |
33 | struct bna_cq; | |
34 | struct bna_rx; | |
35 | struct bna_rxf; | |
078086f3 | 36 | struct bna_enet; |
8b230ed8 RM |
37 | struct bna; |
38 | struct bnad; | |
39 | ||
1aa8b471 | 40 | /* Enums, primitive data types */ |
8b230ed8 RM |
41 | |
42 | enum bna_status { | |
43 | BNA_STATUS_T_DISABLED = 0, | |
44 | BNA_STATUS_T_ENABLED = 1 | |
45 | }; | |
46 | ||
47 | enum bna_cleanup_type { | |
0120b99c RM |
48 | BNA_HARD_CLEANUP = 0, |
49 | BNA_SOFT_CLEANUP = 1 | |
8b230ed8 RM |
50 | }; |
51 | ||
52 | enum bna_cb_status { | |
0120b99c | 53 | BNA_CB_SUCCESS = 0, |
8b230ed8 RM |
54 | BNA_CB_FAIL = 1, |
55 | BNA_CB_INTERRUPT = 2, | |
56 | BNA_CB_BUSY = 3, | |
57 | BNA_CB_INVALID_MAC = 4, | |
58 | BNA_CB_MCAST_LIST_FULL = 5, | |
59 | BNA_CB_UCAST_CAM_FULL = 6, | |
60 | BNA_CB_WAITING = 7, | |
61 | BNA_CB_NOT_EXEC = 8 | |
62 | }; | |
63 | ||
64 | enum bna_res_type { | |
65 | BNA_RES_T_MEM = 1, | |
66 | BNA_RES_T_INTR = 2 | |
67 | }; | |
68 | ||
69 | enum bna_mem_type { | |
0120b99c RM |
70 | BNA_MEM_T_KVA = 1, |
71 | BNA_MEM_T_DMA = 2 | |
8b230ed8 RM |
72 | }; |
73 | ||
74 | enum bna_intr_type { | |
75 | BNA_INTR_T_INTX = 1, | |
76 | BNA_INTR_T_MSIX = 2 | |
77 | }; | |
78 | ||
79 | enum bna_res_req_type { | |
0120b99c RM |
80 | BNA_RES_MEM_T_COM = 0, |
81 | BNA_RES_MEM_T_ATTR = 1, | |
82 | BNA_RES_MEM_T_FWTRC = 2, | |
83 | BNA_RES_MEM_T_STATS = 3, | |
8b230ed8 RM |
84 | BNA_RES_T_MAX |
85 | }; | |
86 | ||
078086f3 RM |
87 | enum bna_mod_res_req_type { |
88 | BNA_MOD_RES_MEM_T_TX_ARRAY = 0, | |
89 | BNA_MOD_RES_MEM_T_TXQ_ARRAY = 1, | |
90 | BNA_MOD_RES_MEM_T_RX_ARRAY = 2, | |
91 | BNA_MOD_RES_MEM_T_RXP_ARRAY = 3, | |
92 | BNA_MOD_RES_MEM_T_RXQ_ARRAY = 4, | |
93 | BNA_MOD_RES_MEM_T_UCMAC_ARRAY = 5, | |
94 | BNA_MOD_RES_MEM_T_MCMAC_ARRAY = 6, | |
95 | BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY = 7, | |
96 | BNA_MOD_RES_T_MAX | |
97 | }; | |
98 | ||
8b230ed8 RM |
99 | enum bna_tx_res_req_type { |
100 | BNA_TX_RES_MEM_T_TCB = 0, | |
101 | BNA_TX_RES_MEM_T_UNMAPQ = 1, | |
0120b99c | 102 | BNA_TX_RES_MEM_T_QPT = 2, |
8b230ed8 | 103 | BNA_TX_RES_MEM_T_SWQPT = 3, |
0120b99c | 104 | BNA_TX_RES_MEM_T_PAGE = 4, |
078086f3 RM |
105 | BNA_TX_RES_MEM_T_IBIDX = 5, |
106 | BNA_TX_RES_INTR_T_TXCMPL = 6, | |
8b230ed8 RM |
107 | BNA_TX_RES_T_MAX, |
108 | }; | |
109 | ||
110 | enum bna_rx_mem_type { | |
111 | BNA_RX_RES_MEM_T_CCB = 0, /* CQ context */ | |
112 | BNA_RX_RES_MEM_T_RCB = 1, /* CQ context */ | |
e29aa339 RM |
113 | BNA_RX_RES_MEM_T_UNMAPHQ = 2, |
114 | BNA_RX_RES_MEM_T_UNMAPDQ = 3, | |
115 | BNA_RX_RES_MEM_T_CQPT = 4, | |
116 | BNA_RX_RES_MEM_T_CSWQPT = 5, | |
117 | BNA_RX_RES_MEM_T_CQPT_PAGE = 6, | |
118 | BNA_RX_RES_MEM_T_HQPT = 7, | |
119 | BNA_RX_RES_MEM_T_DQPT = 8, | |
120 | BNA_RX_RES_MEM_T_HSWQPT = 9, | |
121 | BNA_RX_RES_MEM_T_DSWQPT = 10, | |
122 | BNA_RX_RES_MEM_T_DPAGE = 11, | |
123 | BNA_RX_RES_MEM_T_HPAGE = 12, | |
124 | BNA_RX_RES_MEM_T_IBIDX = 13, | |
125 | BNA_RX_RES_MEM_T_RIT = 14, | |
126 | BNA_RX_RES_T_INTR = 15, | |
127 | BNA_RX_RES_T_MAX = 16 | |
8b230ed8 RM |
128 | }; |
129 | ||
8b230ed8 RM |
130 | enum bna_tx_type { |
131 | BNA_TX_T_REGULAR = 0, | |
132 | BNA_TX_T_LOOPBACK = 1, | |
133 | }; | |
134 | ||
135 | enum bna_tx_flags { | |
078086f3 | 136 | BNA_TX_F_ENET_STARTED = 1, |
8b230ed8 | 137 | BNA_TX_F_ENABLED = 2, |
078086f3 | 138 | BNA_TX_F_BW_UPDATED = 8, |
8b230ed8 RM |
139 | }; |
140 | ||
141 | enum bna_tx_mod_flags { | |
078086f3 RM |
142 | BNA_TX_MOD_F_ENET_STARTED = 1, |
143 | BNA_TX_MOD_F_ENET_LOOPBACK = 2, | |
8b230ed8 RM |
144 | }; |
145 | ||
146 | enum bna_rx_type { | |
147 | BNA_RX_T_REGULAR = 0, | |
148 | BNA_RX_T_LOOPBACK = 1, | |
149 | }; | |
150 | ||
151 | enum bna_rxp_type { | |
0120b99c RM |
152 | BNA_RXP_SINGLE = 1, |
153 | BNA_RXP_SLR = 2, | |
154 | BNA_RXP_HDS = 3 | |
8b230ed8 RM |
155 | }; |
156 | ||
157 | enum bna_rxmode { | |
0120b99c | 158 | BNA_RXMODE_PROMISC = 1, |
078086f3 RM |
159 | BNA_RXMODE_DEFAULT = 2, |
160 | BNA_RXMODE_ALLMULTI = 4 | |
8b230ed8 RM |
161 | }; |
162 | ||
163 | enum bna_rx_event { | |
164 | RX_E_START = 1, | |
165 | RX_E_STOP = 2, | |
166 | RX_E_FAIL = 3, | |
078086f3 RM |
167 | RX_E_STARTED = 4, |
168 | RX_E_STOPPED = 5, | |
169 | RX_E_RXF_STARTED = 6, | |
170 | RX_E_RXF_STOPPED = 7, | |
171 | RX_E_CLEANUP_DONE = 8, | |
8b230ed8 RM |
172 | }; |
173 | ||
8b230ed8 | 174 | enum bna_rx_flags { |
078086f3 RM |
175 | BNA_RX_F_ENET_STARTED = 1, |
176 | BNA_RX_F_ENABLED = 2, | |
8b230ed8 RM |
177 | }; |
178 | ||
179 | enum bna_rx_mod_flags { | |
078086f3 RM |
180 | BNA_RX_MOD_F_ENET_STARTED = 1, |
181 | BNA_RX_MOD_F_ENET_LOOPBACK = 2, | |
8b230ed8 RM |
182 | }; |
183 | ||
8b230ed8 RM |
184 | enum bna_rxf_event { |
185 | RXF_E_START = 1, | |
186 | RXF_E_STOP = 2, | |
187 | RXF_E_FAIL = 3, | |
078086f3 | 188 | RXF_E_CONFIG = 4, |
078086f3 | 189 | RXF_E_FW_RESP = 7, |
8b230ed8 RM |
190 | }; |
191 | ||
078086f3 RM |
192 | enum bna_enet_type { |
193 | BNA_ENET_T_REGULAR = 0, | |
194 | BNA_ENET_T_LOOPBACK_INTERNAL = 1, | |
195 | BNA_ENET_T_LOOPBACK_EXTERNAL = 2, | |
196 | }; | |
197 | ||
8b230ed8 RM |
198 | enum bna_link_status { |
199 | BNA_LINK_DOWN = 0, | |
200 | BNA_LINK_UP = 1, | |
0120b99c | 201 | BNA_CEE_UP = 2 |
8b230ed8 RM |
202 | }; |
203 | ||
078086f3 RM |
204 | enum bna_ethport_flags { |
205 | BNA_ETHPORT_F_ADMIN_UP = 1, | |
206 | BNA_ETHPORT_F_PORT_ENABLED = 2, | |
207 | BNA_ETHPORT_F_RX_STARTED = 4, | |
208 | }; | |
209 | ||
078086f3 RM |
210 | enum bna_enet_flags { |
211 | BNA_ENET_F_IOCETH_READY = 1, | |
212 | BNA_ENET_F_ENABLED = 2, | |
213 | BNA_ENET_F_PAUSE_CHANGED = 4, | |
214 | BNA_ENET_F_MTU_CHANGED = 8 | |
215 | }; | |
216 | ||
217 | enum bna_rss_flags { | |
218 | BNA_RSS_F_RIT_PENDING = 1, | |
219 | BNA_RSS_F_CFG_PENDING = 2, | |
220 | BNA_RSS_F_STATUS_PENDING = 4, | |
221 | }; | |
222 | ||
223 | enum bna_mod_flags { | |
224 | BNA_MOD_F_INIT_DONE = 1, | |
225 | }; | |
226 | ||
8b230ed8 RM |
227 | enum bna_pkt_rates { |
228 | BNA_PKT_RATE_10K = 10000, | |
229 | BNA_PKT_RATE_20K = 20000, | |
230 | BNA_PKT_RATE_30K = 30000, | |
231 | BNA_PKT_RATE_40K = 40000, | |
232 | BNA_PKT_RATE_50K = 50000, | |
233 | BNA_PKT_RATE_60K = 60000, | |
234 | BNA_PKT_RATE_70K = 70000, | |
235 | BNA_PKT_RATE_80K = 80000, | |
236 | }; | |
237 | ||
238 | enum bna_dim_load_types { | |
239 | BNA_LOAD_T_HIGH_4 = 0, /* 80K <= r */ | |
240 | BNA_LOAD_T_HIGH_3 = 1, /* 60K <= r < 80K */ | |
241 | BNA_LOAD_T_HIGH_2 = 2, /* 50K <= r < 60K */ | |
242 | BNA_LOAD_T_HIGH_1 = 3, /* 40K <= r < 50K */ | |
243 | BNA_LOAD_T_LOW_1 = 4, /* 30K <= r < 40K */ | |
244 | BNA_LOAD_T_LOW_2 = 5, /* 20K <= r < 30K */ | |
245 | BNA_LOAD_T_LOW_3 = 6, /* 10K <= r < 20K */ | |
246 | BNA_LOAD_T_LOW_4 = 7, /* r < 10K */ | |
247 | BNA_LOAD_T_MAX = 8 | |
248 | }; | |
249 | ||
250 | enum bna_dim_bias_types { | |
251 | BNA_BIAS_T_SMALL = 0, /* small pkts > (large pkts * 2) */ | |
252 | BNA_BIAS_T_LARGE = 1, /* Not BNA_BIAS_T_SMALL */ | |
253 | BNA_BIAS_T_MAX = 2 | |
254 | }; | |
255 | ||
078086f3 RM |
256 | #define BNA_MAX_NAME_SIZE 64 |
257 | struct bna_ident { | |
258 | int id; | |
259 | char name[BNA_MAX_NAME_SIZE]; | |
260 | }; | |
261 | ||
8b230ed8 RM |
262 | struct bna_mac { |
263 | /* This should be the first one */ | |
264 | struct list_head qe; | |
265 | u8 addr[ETH_ALEN]; | |
078086f3 | 266 | struct bna_mcam_handle *handle; |
8b230ed8 RM |
267 | }; |
268 | ||
269 | struct bna_mem_descr { | |
270 | u32 len; | |
271 | void *kva; | |
272 | struct bna_dma_addr dma; | |
273 | }; | |
274 | ||
275 | struct bna_mem_info { | |
276 | enum bna_mem_type mem_type; | |
277 | u32 len; | |
0120b99c | 278 | u32 num; |
8b230ed8 RM |
279 | u32 align_sz; /* 0/1 = no alignment */ |
280 | struct bna_mem_descr *mdl; | |
281 | void *cookie; /* For bnad to unmap dma later */ | |
282 | }; | |
283 | ||
284 | struct bna_intr_descr { | |
285 | int vector; | |
286 | }; | |
287 | ||
288 | struct bna_intr_info { | |
289 | enum bna_intr_type intr_type; | |
290 | int num; | |
291 | struct bna_intr_descr *idl; | |
292 | }; | |
293 | ||
294 | union bna_res_u { | |
295 | struct bna_mem_info mem_info; | |
296 | struct bna_intr_info intr_info; | |
297 | }; | |
298 | ||
299 | struct bna_res_info { | |
300 | enum bna_res_type res_type; | |
301 | union bna_res_u res_u; | |
302 | }; | |
303 | ||
304 | /* HW QPT */ | |
305 | struct bna_qpt { | |
306 | struct bna_dma_addr hw_qpt_ptr; | |
307 | void *kv_qpt_ptr; | |
308 | u32 page_count; | |
309 | u32 page_size; | |
310 | }; | |
311 | ||
078086f3 | 312 | struct bna_attr { |
761fab37 | 313 | bool fw_query_complete; |
078086f3 RM |
314 | int num_txq; |
315 | int num_rxp; | |
316 | int num_ucmac; | |
317 | int num_mcmac; | |
318 | int max_rit_size; | |
319 | }; | |
320 | ||
1aa8b471 | 321 | /* IOCEth */ |
8b230ed8 | 322 | |
078086f3 | 323 | struct bna_ioceth { |
8b230ed8 RM |
324 | bfa_fsm_t fsm; |
325 | struct bfa_ioc ioc; | |
326 | ||
078086f3 RM |
327 | struct bna_attr attr; |
328 | struct bfa_msgq_cmd_entry msgq_cmd; | |
329 | struct bfi_enet_attr_req attr_req; | |
8b230ed8 | 330 | |
078086f3 | 331 | void (*stop_cbfn)(struct bnad *bnad); |
8b230ed8 RM |
332 | struct bnad *stop_cbarg; |
333 | ||
334 | struct bna *bna; | |
335 | }; | |
336 | ||
1aa8b471 | 337 | /* Enet */ |
8b230ed8 RM |
338 | |
339 | /* Pause configuration */ | |
340 | struct bna_pause_config { | |
341 | enum bna_status tx_pause; | |
342 | enum bna_status rx_pause; | |
343 | }; | |
344 | ||
078086f3 RM |
345 | struct bna_enet { |
346 | bfa_fsm_t fsm; | |
347 | enum bna_enet_flags flags; | |
348 | ||
349 | enum bna_enet_type type; | |
350 | ||
351 | struct bna_pause_config pause_config; | |
352 | int mtu; | |
353 | ||
354 | /* Callback for bna_enet_disable(), enet_stop() */ | |
355 | void (*stop_cbfn)(void *); | |
356 | void *stop_cbarg; | |
357 | ||
078086f3 RM |
358 | /* Callback for bna_enet_mtu_set() */ |
359 | void (*mtu_cbfn)(struct bnad *); | |
360 | ||
361 | struct bfa_wc chld_stop_wc; | |
362 | ||
363 | struct bfa_msgq_cmd_entry msgq_cmd; | |
364 | struct bfi_enet_set_pause_req pause_req; | |
365 | ||
366 | struct bna *bna; | |
367 | }; | |
368 | ||
1aa8b471 | 369 | /* Ethport */ |
078086f3 RM |
370 | |
371 | struct bna_ethport { | |
372 | bfa_fsm_t fsm; | |
373 | enum bna_ethport_flags flags; | |
374 | ||
375 | enum bna_link_status link_status; | |
376 | ||
377 | int rx_started_count; | |
378 | ||
379 | void (*stop_cbfn)(struct bna_enet *); | |
380 | ||
381 | void (*adminup_cbfn)(struct bnad *, enum bna_cb_status); | |
382 | ||
383 | void (*link_cbfn)(struct bnad *, enum bna_link_status); | |
384 | ||
385 | struct bfa_msgq_cmd_entry msgq_cmd; | |
386 | union { | |
387 | struct bfi_enet_enable_req admin_req; | |
388 | struct bfi_enet_diag_lb_req lpbk_req; | |
389 | } bfi_enet_cmd; | |
390 | ||
391 | struct bna *bna; | |
392 | }; | |
393 | ||
1aa8b471 | 394 | /* Interrupt Block */ |
8b230ed8 | 395 | |
8b230ed8 RM |
396 | /* Doorbell structure */ |
397 | struct bna_ib_dbell { | |
e1e0918f | 398 | void __iomem *doorbell_addr; |
8b230ed8 RM |
399 | u32 doorbell_ack; |
400 | }; | |
401 | ||
8b230ed8 RM |
402 | /* IB structure */ |
403 | struct bna_ib { | |
8b230ed8 RM |
404 | struct bna_dma_addr ib_seg_host_addr; |
405 | void *ib_seg_host_addr_kva; | |
8b230ed8 RM |
406 | |
407 | struct bna_ib_dbell door_bell; | |
408 | ||
078086f3 RM |
409 | enum bna_intr_type intr_type; |
410 | int intr_vector; | |
8b230ed8 | 411 | |
078086f3 | 412 | u8 coalescing_timeo; /* Unit is 5usec. */ |
8b230ed8 | 413 | |
078086f3 RM |
414 | int interpkt_count; |
415 | int interpkt_timeo; | |
8b230ed8 RM |
416 | }; |
417 | ||
1aa8b471 | 418 | /* Tx object */ |
8b230ed8 RM |
419 | |
420 | /* Tx datapath control structure */ | |
421 | #define BNA_Q_NAME_SIZE 16 | |
422 | struct bna_tcb { | |
423 | /* Fast path */ | |
424 | void **sw_qpt; | |
5216562a | 425 | void *sw_q; |
8b230ed8 RM |
426 | void *unmap_q; |
427 | u32 producer_index; | |
428 | u32 consumer_index; | |
429 | volatile u32 *hw_consumer_index; | |
430 | u32 q_depth; | |
e1e0918f | 431 | void __iomem *q_dbell; |
8b230ed8 | 432 | struct bna_ib_dbell *i_dbell; |
8b230ed8 RM |
433 | /* Control path */ |
434 | struct bna_txq *txq; | |
435 | struct bnad *bnad; | |
078086f3 | 436 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
437 | enum bna_intr_type intr_type; |
438 | int intr_vector; | |
439 | u8 priority; /* Current priority */ | |
440 | unsigned long flags; /* Used by bnad as required */ | |
441 | int id; | |
442 | char name[BNA_Q_NAME_SIZE]; | |
443 | }; | |
444 | ||
445 | /* TxQ QPT and configuration */ | |
446 | struct bna_txq { | |
447 | /* This should be the first one */ | |
448 | struct list_head qe; | |
449 | ||
8b230ed8 RM |
450 | u8 priority; |
451 | ||
452 | struct bna_qpt qpt; | |
453 | struct bna_tcb *tcb; | |
078086f3 | 454 | struct bna_ib ib; |
8b230ed8 RM |
455 | |
456 | struct bna_tx *tx; | |
457 | ||
078086f3 RM |
458 | int hw_id; |
459 | ||
0120b99c RM |
460 | u64 tx_packets; |
461 | u64 tx_bytes; | |
8b230ed8 RM |
462 | }; |
463 | ||
8b230ed8 RM |
464 | /* Tx object */ |
465 | struct bna_tx { | |
466 | /* This should be the first one */ | |
467 | struct list_head qe; | |
078086f3 RM |
468 | int rid; |
469 | int hw_id; | |
8b230ed8 RM |
470 | |
471 | bfa_fsm_t fsm; | |
472 | enum bna_tx_flags flags; | |
473 | ||
474 | enum bna_tx_type type; | |
078086f3 | 475 | int num_txq; |
8b230ed8 RM |
476 | |
477 | struct list_head txq_q; | |
078086f3 | 478 | u16 txf_vlan_id; |
8b230ed8 RM |
479 | |
480 | /* Tx event handlers */ | |
481 | void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *); | |
482 | void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *); | |
078086f3 RM |
483 | void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *); |
484 | void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *); | |
485 | void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *); | |
8b230ed8 RM |
486 | |
487 | /* callback for bna_tx_disable(), bna_tx_stop() */ | |
078086f3 | 488 | void (*stop_cbfn)(void *arg, struct bna_tx *tx); |
8b230ed8 RM |
489 | void *stop_cbarg; |
490 | ||
078086f3 RM |
491 | struct bfa_msgq_cmd_entry msgq_cmd; |
492 | union { | |
493 | struct bfi_enet_tx_cfg_req cfg_req; | |
494 | struct bfi_enet_req req; | |
495 | struct bfi_enet_tx_cfg_rsp cfg_rsp; | |
496 | } bfi_enet_cmd; | |
8b230ed8 RM |
497 | |
498 | struct bna *bna; | |
499 | void *priv; /* bnad's cookie */ | |
500 | }; | |
501 | ||
078086f3 | 502 | /* Tx object configuration used during creation */ |
8b230ed8 RM |
503 | struct bna_tx_config { |
504 | int num_txq; | |
505 | int txq_depth; | |
078086f3 | 506 | int coalescing_timeo; |
8b230ed8 RM |
507 | enum bna_tx_type tx_type; |
508 | }; | |
509 | ||
510 | struct bna_tx_event_cbfn { | |
511 | /* Optional */ | |
512 | void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *); | |
513 | void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *); | |
514 | /* Mandatory */ | |
078086f3 RM |
515 | void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *); |
516 | void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *); | |
517 | void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *); | |
8b230ed8 RM |
518 | }; |
519 | ||
520 | /* Tx module - keeps track of free, active tx objects */ | |
521 | struct bna_tx_mod { | |
522 | struct bna_tx *tx; /* BFI_MAX_TXQ entries */ | |
523 | struct bna_txq *txq; /* BFI_MAX_TXQ entries */ | |
524 | ||
525 | struct list_head tx_free_q; | |
526 | struct list_head tx_active_q; | |
527 | ||
528 | struct list_head txq_free_q; | |
529 | ||
530 | /* callback for bna_tx_mod_stop() */ | |
078086f3 | 531 | void (*stop_cbfn)(struct bna_enet *enet); |
8b230ed8 RM |
532 | |
533 | struct bfa_wc tx_stop_wc; | |
534 | ||
535 | enum bna_tx_mod_flags flags; | |
536 | ||
078086f3 RM |
537 | u8 prio_map; |
538 | int default_prio; | |
539 | int iscsi_over_cee; | |
540 | int iscsi_prio; | |
541 | int prio_reconfigured; | |
8b230ed8 | 542 | |
078086f3 | 543 | u32 rid_mask; |
8b230ed8 RM |
544 | |
545 | struct bna *bna; | |
546 | }; | |
547 | ||
1aa8b471 | 548 | /* Rx object */ |
8b230ed8 RM |
549 | |
550 | /* Rx datapath control structure */ | |
551 | struct bna_rcb { | |
552 | /* Fast path */ | |
553 | void **sw_qpt; | |
5216562a | 554 | void *sw_q; |
8b230ed8 RM |
555 | void *unmap_q; |
556 | u32 producer_index; | |
557 | u32 consumer_index; | |
558 | u32 q_depth; | |
e1e0918f | 559 | void __iomem *q_dbell; |
8b230ed8 RM |
560 | /* Control path */ |
561 | struct bna_rxq *rxq; | |
078086f3 | 562 | struct bna_ccb *ccb; |
8b230ed8 | 563 | struct bnad *bnad; |
078086f3 | 564 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
565 | unsigned long flags; |
566 | int id; | |
567 | }; | |
568 | ||
569 | /* RxQ structure - QPT, configuration */ | |
570 | struct bna_rxq { | |
571 | struct list_head qe; | |
8b230ed8 RM |
572 | |
573 | int buffer_size; | |
574 | int q_depth; | |
e29aa339 RM |
575 | u32 num_vecs; |
576 | enum bna_status multi_buffer; | |
8b230ed8 RM |
577 | |
578 | struct bna_qpt qpt; | |
579 | struct bna_rcb *rcb; | |
580 | ||
581 | struct bna_rxp *rxp; | |
582 | struct bna_rx *rx; | |
583 | ||
078086f3 RM |
584 | int hw_id; |
585 | ||
0120b99c | 586 | u64 rx_packets; |
8b230ed8 | 587 | u64 rx_bytes; |
0120b99c RM |
588 | u64 rx_packets_with_error; |
589 | u64 rxbuf_alloc_failed; | |
8b230ed8 RM |
590 | }; |
591 | ||
592 | /* RxQ pair */ | |
593 | union bna_rxq_u { | |
594 | struct { | |
595 | struct bna_rxq *hdr; | |
596 | struct bna_rxq *data; | |
597 | } hds; | |
598 | struct { | |
599 | struct bna_rxq *small; | |
600 | struct bna_rxq *large; | |
601 | } slr; | |
602 | struct { | |
603 | struct bna_rxq *only; | |
604 | struct bna_rxq *reserved; | |
605 | } single; | |
606 | }; | |
607 | ||
608 | /* Packet rate for Dynamic Interrupt Moderation */ | |
609 | struct bna_pkt_rate { | |
610 | u32 small_pkt_cnt; | |
611 | u32 large_pkt_cnt; | |
612 | }; | |
613 | ||
614 | /* Completion control structure */ | |
615 | struct bna_ccb { | |
616 | /* Fast path */ | |
617 | void **sw_qpt; | |
5216562a | 618 | void *sw_q; |
8b230ed8 RM |
619 | u32 producer_index; |
620 | volatile u32 *hw_producer_index; | |
621 | u32 q_depth; | |
622 | struct bna_ib_dbell *i_dbell; | |
623 | struct bna_rcb *rcb[2]; | |
624 | void *ctrl; /* For bnad */ | |
625 | struct bna_pkt_rate pkt_rate; | |
e29aa339 RM |
626 | u32 pkts_una; |
627 | u32 bytes_per_intr; | |
8b230ed8 RM |
628 | |
629 | /* Control path */ | |
630 | struct bna_cq *cq; | |
631 | struct bnad *bnad; | |
078086f3 | 632 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
633 | enum bna_intr_type intr_type; |
634 | int intr_vector; | |
635 | u8 rx_coalescing_timeo; /* For NAPI */ | |
636 | int id; | |
637 | char name[BNA_Q_NAME_SIZE]; | |
638 | }; | |
639 | ||
640 | /* CQ QPT, configuration */ | |
641 | struct bna_cq { | |
8b230ed8 RM |
642 | struct bna_qpt qpt; |
643 | struct bna_ccb *ccb; | |
644 | ||
078086f3 | 645 | struct bna_ib ib; |
8b230ed8 RM |
646 | |
647 | struct bna_rx *rx; | |
648 | }; | |
649 | ||
650 | struct bna_rss_config { | |
078086f3 | 651 | enum bfi_enet_rss_type hash_type; |
8b230ed8 | 652 | u8 hash_mask; |
078086f3 | 653 | u32 toeplitz_hash_key[BFI_ENET_RSS_KEY_LEN]; |
8b230ed8 RM |
654 | }; |
655 | ||
656 | struct bna_hds_config { | |
078086f3 RM |
657 | enum bfi_enet_hds_type hdr_type; |
658 | int forced_offset; | |
8b230ed8 RM |
659 | }; |
660 | ||
078086f3 | 661 | /* Rx object configuration used during creation */ |
8b230ed8 RM |
662 | struct bna_rx_config { |
663 | enum bna_rx_type rx_type; | |
664 | int num_paths; | |
665 | enum bna_rxp_type rxp_type; | |
078086f3 | 666 | int coalescing_timeo; |
8b230ed8 RM |
667 | /* |
668 | * Small/Large (or Header/Data) buffer size to be configured | |
e29aa339 | 669 | * for SLR and HDS queue type. |
8b230ed8 | 670 | */ |
e29aa339 RM |
671 | u32 frame_size; |
672 | ||
673 | /* header or small queue */ | |
674 | u32 q1_depth; | |
675 | u32 q1_buf_size; | |
676 | ||
677 | /* data or large queue */ | |
678 | u32 q0_depth; | |
679 | u32 q0_buf_size; | |
680 | u32 q0_num_vecs; | |
681 | enum bna_status q0_multi_buf; | |
8b230ed8 RM |
682 | |
683 | enum bna_status rss_status; | |
684 | struct bna_rss_config rss_config; | |
685 | ||
8b230ed8 RM |
686 | struct bna_hds_config hds_config; |
687 | ||
688 | enum bna_status vlan_strip_status; | |
689 | }; | |
690 | ||
691 | /* Rx Path structure - one per MSIX vector/CPU */ | |
692 | struct bna_rxp { | |
693 | /* This should be the first one */ | |
694 | struct list_head qe; | |
695 | ||
696 | enum bna_rxp_type type; | |
697 | union bna_rxq_u rxq; | |
698 | struct bna_cq cq; | |
699 | ||
700 | struct bna_rx *rx; | |
701 | ||
702 | /* MSI-x vector number for configuring RSS */ | |
703 | int vector; | |
078086f3 | 704 | int hw_id; |
8b230ed8 RM |
705 | }; |
706 | ||
707 | /* RxF structure (hardware Rx Function) */ | |
708 | struct bna_rxf { | |
709 | bfa_fsm_t fsm; | |
078086f3 RM |
710 | |
711 | struct bfa_msgq_cmd_entry msgq_cmd; | |
712 | union { | |
713 | struct bfi_enet_enable_req req; | |
714 | struct bfi_enet_rss_cfg_req rss_req; | |
715 | struct bfi_enet_rit_req rit_req; | |
716 | struct bfi_enet_rx_vlan_req vlan_req; | |
717 | struct bfi_enet_mcast_add_req mcast_add_req; | |
718 | struct bfi_enet_mcast_del_req mcast_del_req; | |
719 | struct bfi_enet_ucast_req ucast_req; | |
720 | } bfi_enet_cmd; | |
8b230ed8 RM |
721 | |
722 | /* callback for bna_rxf_start() */ | |
078086f3 | 723 | void (*start_cbfn) (struct bna_rx *rx); |
8b230ed8 RM |
724 | struct bna_rx *start_cbarg; |
725 | ||
726 | /* callback for bna_rxf_stop() */ | |
078086f3 | 727 | void (*stop_cbfn) (struct bna_rx *rx); |
8b230ed8 RM |
728 | struct bna_rx *stop_cbarg; |
729 | ||
8b230ed8 RM |
730 | /** |
731 | * callback for: | |
732 | * bna_rxf_ucast_set() | |
733 | * bna_rxf_{ucast/mcast}_add(), | |
0120b99c | 734 | * bna_rxf_{ucast/mcast}_del(), |
8b230ed8 RM |
735 | * bna_rxf_mode_set() |
736 | */ | |
078086f3 | 737 | void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx); |
8b230ed8 RM |
738 | struct bnad *cam_fltr_cbarg; |
739 | ||
8b230ed8 RM |
740 | /* List of unicast addresses yet to be applied to h/w */ |
741 | struct list_head ucast_pending_add_q; | |
742 | struct list_head ucast_pending_del_q; | |
078086f3 | 743 | struct bna_mac *ucast_pending_mac; |
8b230ed8 RM |
744 | int ucast_pending_set; |
745 | /* ucast addresses applied to the h/w */ | |
746 | struct list_head ucast_active_q; | |
078086f3 RM |
747 | struct bna_mac ucast_active_mac; |
748 | int ucast_active_set; | |
8b230ed8 RM |
749 | |
750 | /* List of multicast addresses yet to be applied to h/w */ | |
751 | struct list_head mcast_pending_add_q; | |
752 | struct list_head mcast_pending_del_q; | |
753 | /* multicast addresses applied to the h/w */ | |
754 | struct list_head mcast_active_q; | |
078086f3 | 755 | struct list_head mcast_handle_q; |
8b230ed8 RM |
756 | |
757 | /* Rx modes yet to be applied to h/w */ | |
758 | enum bna_rxmode rxmode_pending; | |
759 | enum bna_rxmode rxmode_pending_bitmask; | |
760 | /* Rx modes applied to h/w */ | |
761 | enum bna_rxmode rxmode_active; | |
762 | ||
078086f3 | 763 | u8 vlan_pending_bitmask; |
8b230ed8 | 764 | enum bna_status vlan_filter_status; |
078086f3 RM |
765 | u32 vlan_filter_table[(BFI_ENET_VLAN_ID_MAX) / 32]; |
766 | bool vlan_strip_pending; | |
767 | enum bna_status vlan_strip_status; | |
768 | ||
769 | enum bna_rss_flags rss_pending; | |
770 | enum bna_status rss_status; | |
771 | struct bna_rss_config rss_cfg; | |
772 | u8 *rit; | |
773 | int rit_size; | |
774 | ||
775 | struct bna_rx *rx; | |
8b230ed8 RM |
776 | }; |
777 | ||
778 | /* Rx object */ | |
779 | struct bna_rx { | |
780 | /* This should be the first one */ | |
781 | struct list_head qe; | |
078086f3 RM |
782 | int rid; |
783 | int hw_id; | |
8b230ed8 RM |
784 | |
785 | bfa_fsm_t fsm; | |
786 | ||
787 | enum bna_rx_type type; | |
788 | ||
078086f3 | 789 | int num_paths; |
8b230ed8 RM |
790 | struct list_head rxp_q; |
791 | ||
078086f3 RM |
792 | struct bna_hds_config hds_cfg; |
793 | ||
8b230ed8 RM |
794 | struct bna_rxf rxf; |
795 | ||
796 | enum bna_rx_flags rx_flags; | |
797 | ||
078086f3 RM |
798 | struct bfa_msgq_cmd_entry msgq_cmd; |
799 | union { | |
800 | struct bfi_enet_rx_cfg_req cfg_req; | |
801 | struct bfi_enet_req req; | |
802 | struct bfi_enet_rx_cfg_rsp cfg_rsp; | |
803 | } bfi_enet_cmd; | |
8b230ed8 RM |
804 | |
805 | /* Rx event handlers */ | |
806 | void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *); | |
807 | void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *); | |
808 | void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *); | |
809 | void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *); | |
5bcf6ac0 | 810 | void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *); |
078086f3 RM |
811 | void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *); |
812 | void (*rx_post_cbfn)(struct bnad *, struct bna_rx *); | |
8b230ed8 RM |
813 | |
814 | /* callback for bna_rx_disable(), bna_rx_stop() */ | |
078086f3 | 815 | void (*stop_cbfn)(void *arg, struct bna_rx *rx); |
8b230ed8 RM |
816 | void *stop_cbarg; |
817 | ||
818 | struct bna *bna; | |
819 | void *priv; /* bnad's cookie */ | |
820 | }; | |
821 | ||
822 | struct bna_rx_event_cbfn { | |
823 | /* Optional */ | |
824 | void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *); | |
825 | void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *); | |
826 | void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *); | |
827 | void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *); | |
5bcf6ac0 | 828 | void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *); |
8b230ed8 | 829 | /* Mandatory */ |
078086f3 RM |
830 | void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *); |
831 | void (*rx_post_cbfn)(struct bnad *, struct bna_rx *); | |
8b230ed8 RM |
832 | }; |
833 | ||
834 | /* Rx module - keeps track of free, active rx objects */ | |
835 | struct bna_rx_mod { | |
836 | struct bna *bna; /* back pointer to parent */ | |
837 | struct bna_rx *rx; /* BFI_MAX_RXQ entries */ | |
838 | struct bna_rxp *rxp; /* BFI_MAX_RXQ entries */ | |
839 | struct bna_rxq *rxq; /* BFI_MAX_RXQ entries */ | |
840 | ||
841 | struct list_head rx_free_q; | |
842 | struct list_head rx_active_q; | |
843 | int rx_free_count; | |
844 | ||
845 | struct list_head rxp_free_q; | |
846 | int rxp_free_count; | |
847 | ||
848 | struct list_head rxq_free_q; | |
849 | int rxq_free_count; | |
850 | ||
851 | enum bna_rx_mod_flags flags; | |
852 | ||
853 | /* callback for bna_rx_mod_stop() */ | |
078086f3 | 854 | void (*stop_cbfn)(struct bna_enet *enet); |
8b230ed8 RM |
855 | |
856 | struct bfa_wc rx_stop_wc; | |
857 | u32 dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX]; | |
078086f3 | 858 | u32 rid_mask; |
8b230ed8 RM |
859 | }; |
860 | ||
1aa8b471 | 861 | /* CAM */ |
8b230ed8 RM |
862 | |
863 | struct bna_ucam_mod { | |
20b298f5 | 864 | struct bna_mac *ucmac; /* num_ucmac * 2 entries */ |
8b230ed8 | 865 | struct list_head free_q; |
20b298f5 | 866 | struct list_head del_q; |
8b230ed8 RM |
867 | |
868 | struct bna *bna; | |
869 | }; | |
870 | ||
078086f3 RM |
871 | struct bna_mcam_handle { |
872 | /* This should be the first one */ | |
873 | struct list_head qe; | |
874 | int handle; | |
875 | int refcnt; | |
876 | }; | |
877 | ||
8b230ed8 | 878 | struct bna_mcam_mod { |
20b298f5 RM |
879 | struct bna_mac *mcmac; /* num_mcmac * 2 entries */ |
880 | struct bna_mcam_handle *mchandle; /* num_mcmac entries */ | |
8b230ed8 | 881 | struct list_head free_q; |
20b298f5 | 882 | struct list_head del_q; |
078086f3 | 883 | struct list_head free_handle_q; |
8b230ed8 RM |
884 | |
885 | struct bna *bna; | |
886 | }; | |
887 | ||
1aa8b471 | 888 | /* Statistics */ |
8b230ed8 | 889 | |
8b230ed8 | 890 | struct bna_stats { |
078086f3 RM |
891 | struct bna_dma_addr hw_stats_dma; |
892 | struct bfi_enet_stats *hw_stats_kva; | |
893 | struct bfi_enet_stats hw_stats; | |
894 | }; | |
895 | ||
896 | struct bna_stats_mod { | |
897 | bool ioc_ready; | |
898 | bool stats_get_busy; | |
899 | bool stats_clr_busy; | |
900 | struct bfa_msgq_cmd_entry stats_get_cmd; | |
901 | struct bfa_msgq_cmd_entry stats_clr_cmd; | |
902 | struct bfi_enet_stats_req stats_get; | |
903 | struct bfi_enet_stats_req stats_clr; | |
8b230ed8 RM |
904 | }; |
905 | ||
1aa8b471 | 906 | /* BNA */ |
8b230ed8 RM |
907 | |
908 | struct bna { | |
078086f3 | 909 | struct bna_ident ident; |
8b230ed8 RM |
910 | struct bfa_pcidev pcidev; |
911 | ||
078086f3 RM |
912 | struct bna_reg regs; |
913 | struct bna_bit_defn bits; | |
8b230ed8 | 914 | |
8b230ed8 RM |
915 | struct bna_stats stats; |
916 | ||
078086f3 | 917 | struct bna_ioceth ioceth; |
8b230ed8 | 918 | struct bfa_cee cee; |
72a9730b | 919 | struct bfa_flash flash; |
078086f3 | 920 | struct bfa_msgq msgq; |
8b230ed8 | 921 | |
078086f3 RM |
922 | struct bna_ethport ethport; |
923 | struct bna_enet enet; | |
924 | struct bna_stats_mod stats_mod; | |
8b230ed8 RM |
925 | |
926 | struct bna_tx_mod tx_mod; | |
8b230ed8 | 927 | struct bna_rx_mod rx_mod; |
8b230ed8 RM |
928 | struct bna_ucam_mod ucam_mod; |
929 | struct bna_mcam_mod mcam_mod; | |
930 | ||
078086f3 | 931 | enum bna_mod_flags mod_flags; |
8b230ed8 | 932 | |
078086f3 RM |
933 | int default_mode_rid; |
934 | int promisc_rid; | |
8b230ed8 RM |
935 | |
936 | struct bnad *bnad; | |
937 | }; | |
8b230ed8 | 938 | #endif /* __BNA_TYPES_H__ */ |