Commit | Line | Data |
---|---|---|
89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
909a8583 | 17 | #include <linux/circ_buf.h> |
89e5785f HS |
18 | #include <linux/slab.h> |
19 | #include <linux/init.h> | |
2dbfdbb9 | 20 | #include <linux/gpio.h> |
a6b7a407 | 21 | #include <linux/interrupt.h> |
89e5785f HS |
22 | #include <linux/netdevice.h> |
23 | #include <linux/etherdevice.h> | |
89e5785f | 24 | #include <linux/dma-mapping.h> |
84e0cdb0 | 25 | #include <linux/platform_data/macb.h> |
89e5785f | 26 | #include <linux/platform_device.h> |
6c36a707 | 27 | #include <linux/phy.h> |
b17471f5 | 28 | #include <linux/of.h> |
fb97a846 JCPV |
29 | #include <linux/of_device.h> |
30 | #include <linux/of_net.h> | |
8ef29f8a | 31 | #include <linux/pinctrl/consumer.h> |
89e5785f | 32 | |
89e5785f HS |
33 | #include "macb.h" |
34 | ||
89e5785f | 35 | #define RX_BUFFER_SIZE 128 |
55054a16 HS |
36 | #define RX_RING_SIZE 512 /* must be power of 2 */ |
37 | #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) | |
89e5785f | 38 | |
55054a16 HS |
39 | #define TX_RING_SIZE 128 /* must be power of 2 */ |
40 | #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) | |
89e5785f | 41 | |
909a8583 NF |
42 | /* level of occupied TX descriptors under which we wake up TX process */ |
43 | #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4) | |
89e5785f HS |
44 | |
45 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
46 | | MACB_BIT(ISR_ROVR)) | |
e86cd53a NF |
47 | #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ |
48 | | MACB_BIT(ISR_RLE) \ | |
49 | | MACB_BIT(TXERR)) | |
50 | #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) | |
51 | ||
52 | /* | |
53 | * Graceful stop timeouts in us. We should allow up to | |
54 | * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) | |
55 | */ | |
56 | #define MACB_HALT_TIMEOUT 1230 | |
89e5785f | 57 | |
55054a16 HS |
58 | /* Ring buffer accessors */ |
59 | static unsigned int macb_tx_ring_wrap(unsigned int index) | |
60 | { | |
61 | return index & (TX_RING_SIZE - 1); | |
62 | } | |
63 | ||
55054a16 HS |
64 | static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index) |
65 | { | |
66 | return &bp->tx_ring[macb_tx_ring_wrap(index)]; | |
67 | } | |
68 | ||
69 | static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index) | |
70 | { | |
71 | return &bp->tx_skb[macb_tx_ring_wrap(index)]; | |
72 | } | |
73 | ||
74 | static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index) | |
75 | { | |
76 | dma_addr_t offset; | |
77 | ||
78 | offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); | |
79 | ||
80 | return bp->tx_ring_dma + offset; | |
81 | } | |
82 | ||
83 | static unsigned int macb_rx_ring_wrap(unsigned int index) | |
84 | { | |
85 | return index & (RX_RING_SIZE - 1); | |
86 | } | |
87 | ||
88 | static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) | |
89 | { | |
90 | return &bp->rx_ring[macb_rx_ring_wrap(index)]; | |
91 | } | |
92 | ||
93 | static void *macb_rx_buffer(struct macb *bp, unsigned int index) | |
94 | { | |
95 | return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index); | |
96 | } | |
97 | ||
314bccc4 | 98 | void macb_set_hwaddr(struct macb *bp) |
89e5785f HS |
99 | { |
100 | u32 bottom; | |
101 | u16 top; | |
102 | ||
103 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 104 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 105 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 106 | macb_or_gem_writel(bp, SA1T, top); |
3629a6ce JE |
107 | |
108 | /* Clear unused address register sets */ | |
109 | macb_or_gem_writel(bp, SA2B, 0); | |
110 | macb_or_gem_writel(bp, SA2T, 0); | |
111 | macb_or_gem_writel(bp, SA3B, 0); | |
112 | macb_or_gem_writel(bp, SA3T, 0); | |
113 | macb_or_gem_writel(bp, SA4B, 0); | |
114 | macb_or_gem_writel(bp, SA4T, 0); | |
89e5785f | 115 | } |
314bccc4 | 116 | EXPORT_SYMBOL_GPL(macb_set_hwaddr); |
89e5785f | 117 | |
314bccc4 | 118 | void macb_get_hwaddr(struct macb *bp) |
89e5785f | 119 | { |
d25e78aa | 120 | struct macb_platform_data *pdata; |
89e5785f HS |
121 | u32 bottom; |
122 | u16 top; | |
123 | u8 addr[6]; | |
17b8bb3e JE |
124 | int i; |
125 | ||
d25e78aa JE |
126 | pdata = bp->pdev->dev.platform_data; |
127 | ||
17b8bb3e JE |
128 | /* Check all 4 address register for vaild address */ |
129 | for (i = 0; i < 4; i++) { | |
130 | bottom = macb_or_gem_readl(bp, SA1B + i * 8); | |
131 | top = macb_or_gem_readl(bp, SA1T + i * 8); | |
132 | ||
d25e78aa JE |
133 | if (pdata && pdata->rev_eth_addr) { |
134 | addr[5] = bottom & 0xff; | |
135 | addr[4] = (bottom >> 8) & 0xff; | |
136 | addr[3] = (bottom >> 16) & 0xff; | |
137 | addr[2] = (bottom >> 24) & 0xff; | |
138 | addr[1] = top & 0xff; | |
139 | addr[0] = (top & 0xff00) >> 8; | |
140 | } else { | |
141 | addr[0] = bottom & 0xff; | |
142 | addr[1] = (bottom >> 8) & 0xff; | |
143 | addr[2] = (bottom >> 16) & 0xff; | |
144 | addr[3] = (bottom >> 24) & 0xff; | |
145 | addr[4] = top & 0xff; | |
146 | addr[5] = (top >> 8) & 0xff; | |
147 | } | |
17b8bb3e JE |
148 | |
149 | if (is_valid_ether_addr(addr)) { | |
150 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | |
151 | return; | |
152 | } | |
d1d5741d | 153 | } |
17b8bb3e JE |
154 | |
155 | netdev_info(bp->dev, "invalid hw address, using random\n"); | |
156 | eth_hw_addr_random(bp->dev); | |
89e5785f | 157 | } |
314bccc4 | 158 | EXPORT_SYMBOL_GPL(macb_get_hwaddr); |
89e5785f | 159 | |
6c36a707 | 160 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 161 | { |
6c36a707 | 162 | struct macb *bp = bus->priv; |
89e5785f HS |
163 | int value; |
164 | ||
89e5785f HS |
165 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
166 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
167 | | MACB_BF(PHYA, mii_id) |
168 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
169 | | MACB_BF(CODE, MACB_MAN_CODE))); |
170 | ||
6c36a707 R |
171 | /* wait for end of transfer */ |
172 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
173 | cpu_relax(); | |
89e5785f HS |
174 | |
175 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
176 | |
177 | return value; | |
178 | } | |
179 | ||
6c36a707 R |
180 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
181 | u16 value) | |
89e5785f | 182 | { |
6c36a707 | 183 | struct macb *bp = bus->priv; |
89e5785f HS |
184 | |
185 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
186 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
187 | | MACB_BF(PHYA, mii_id) |
188 | | MACB_BF(REGA, regnum) | |
89e5785f | 189 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 190 | | MACB_BF(DATA, value))); |
89e5785f | 191 | |
6c36a707 R |
192 | /* wait for end of transfer */ |
193 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
194 | cpu_relax(); | |
195 | ||
196 | return 0; | |
197 | } | |
89e5785f | 198 | |
6c36a707 R |
199 | static int macb_mdio_reset(struct mii_bus *bus) |
200 | { | |
201 | return 0; | |
89e5785f HS |
202 | } |
203 | ||
6c36a707 | 204 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 205 | { |
6c36a707 R |
206 | struct macb *bp = netdev_priv(dev); |
207 | struct phy_device *phydev = bp->phy_dev; | |
208 | unsigned long flags; | |
89e5785f | 209 | |
6c36a707 | 210 | int status_change = 0; |
89e5785f | 211 | |
6c36a707 R |
212 | spin_lock_irqsave(&bp->lock, flags); |
213 | ||
214 | if (phydev->link) { | |
215 | if ((bp->speed != phydev->speed) || | |
216 | (bp->duplex != phydev->duplex)) { | |
217 | u32 reg; | |
218 | ||
219 | reg = macb_readl(bp, NCFGR); | |
220 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
140b7552 PV |
221 | if (macb_is_gem(bp)) |
222 | reg &= ~GEM_BIT(GBE); | |
6c36a707 R |
223 | |
224 | if (phydev->duplex) | |
225 | reg |= MACB_BIT(FD); | |
179956f4 | 226 | if (phydev->speed == SPEED_100) |
6c36a707 | 227 | reg |= MACB_BIT(SPD); |
140b7552 PV |
228 | if (phydev->speed == SPEED_1000) |
229 | reg |= GEM_BIT(GBE); | |
6c36a707 | 230 | |
140b7552 | 231 | macb_or_gem_writel(bp, NCFGR, reg); |
6c36a707 R |
232 | |
233 | bp->speed = phydev->speed; | |
234 | bp->duplex = phydev->duplex; | |
235 | status_change = 1; | |
236 | } | |
89e5785f HS |
237 | } |
238 | ||
6c36a707 | 239 | if (phydev->link != bp->link) { |
c8f15686 | 240 | if (!phydev->link) { |
6c36a707 R |
241 | bp->speed = 0; |
242 | bp->duplex = -1; | |
243 | } | |
244 | bp->link = phydev->link; | |
89e5785f | 245 | |
6c36a707 R |
246 | status_change = 1; |
247 | } | |
89e5785f | 248 | |
6c36a707 R |
249 | spin_unlock_irqrestore(&bp->lock, flags); |
250 | ||
251 | if (status_change) { | |
03fc4721 NF |
252 | if (phydev->link) { |
253 | netif_carrier_on(dev); | |
c220f8cd JI |
254 | netdev_info(dev, "link up (%d/%s)\n", |
255 | phydev->speed, | |
256 | phydev->duplex == DUPLEX_FULL ? | |
257 | "Full" : "Half"); | |
03fc4721 NF |
258 | } else { |
259 | netif_carrier_off(dev); | |
c220f8cd | 260 | netdev_info(dev, "link down\n"); |
03fc4721 | 261 | } |
6c36a707 | 262 | } |
89e5785f HS |
263 | } |
264 | ||
6c36a707 R |
265 | /* based on au1000_eth. c*/ |
266 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 267 | { |
6c36a707 | 268 | struct macb *bp = netdev_priv(dev); |
2dbfdbb9 | 269 | struct macb_platform_data *pdata; |
7455a76f | 270 | struct phy_device *phydev; |
2dbfdbb9 | 271 | int phy_irq; |
7455a76f | 272 | int ret; |
6c36a707 | 273 | |
7455a76f | 274 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 275 | if (!phydev) { |
c220f8cd | 276 | netdev_err(dev, "no PHY found\n"); |
6c36a707 R |
277 | return -1; |
278 | } | |
279 | ||
2dbfdbb9 JE |
280 | pdata = dev_get_platdata(&bp->pdev->dev); |
281 | if (pdata && gpio_is_valid(pdata->phy_irq_pin)) { | |
282 | ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int"); | |
283 | if (!ret) { | |
284 | phy_irq = gpio_to_irq(pdata->phy_irq_pin); | |
285 | phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq; | |
286 | } | |
287 | } | |
6c36a707 R |
288 | |
289 | /* attach the mac to the phy */ | |
7455a76f | 290 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, |
fb97a846 | 291 | bp->phy_interface); |
7455a76f | 292 | if (ret) { |
c220f8cd | 293 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 294 | return ret; |
6c36a707 R |
295 | } |
296 | ||
297 | /* mask with MAC supported features */ | |
140b7552 PV |
298 | if (macb_is_gem(bp)) |
299 | phydev->supported &= PHY_GBIT_FEATURES; | |
300 | else | |
301 | phydev->supported &= PHY_BASIC_FEATURES; | |
6c36a707 R |
302 | |
303 | phydev->advertising = phydev->supported; | |
304 | ||
305 | bp->link = 0; | |
306 | bp->speed = 0; | |
307 | bp->duplex = -1; | |
308 | bp->phy_dev = phydev; | |
309 | ||
310 | return 0; | |
89e5785f HS |
311 | } |
312 | ||
0005f541 | 313 | int macb_mii_init(struct macb *bp) |
89e5785f | 314 | { |
84e0cdb0 | 315 | struct macb_platform_data *pdata; |
6c36a707 | 316 | int err = -ENXIO, i; |
89e5785f | 317 | |
3dbda77e | 318 | /* Enable management port */ |
6c36a707 | 319 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 320 | |
298cf9be LB |
321 | bp->mii_bus = mdiobus_alloc(); |
322 | if (bp->mii_bus == NULL) { | |
323 | err = -ENOMEM; | |
324 | goto err_out; | |
325 | } | |
326 | ||
327 | bp->mii_bus->name = "MACB_mii_bus"; | |
328 | bp->mii_bus->read = &macb_mdio_read; | |
329 | bp->mii_bus->write = &macb_mdio_write; | |
330 | bp->mii_bus->reset = &macb_mdio_reset; | |
98d5e57e FF |
331 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
332 | bp->pdev->name, bp->pdev->id); | |
298cf9be LB |
333 | bp->mii_bus->priv = bp; |
334 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 335 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 336 | |
6c36a707 | 337 | if (pdata) |
298cf9be | 338 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 339 | |
298cf9be LB |
340 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
341 | if (!bp->mii_bus->irq) { | |
6c36a707 | 342 | err = -ENOMEM; |
298cf9be | 343 | goto err_out_free_mdiobus; |
89e5785f HS |
344 | } |
345 | ||
6c36a707 | 346 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 347 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 348 | |
91523947 | 349 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 350 | |
298cf9be | 351 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 352 | goto err_out_free_mdio_irq; |
89e5785f | 353 | |
6c36a707 R |
354 | if (macb_mii_probe(bp->dev) != 0) { |
355 | goto err_out_unregister_bus; | |
356 | } | |
89e5785f | 357 | |
6c36a707 | 358 | return 0; |
89e5785f | 359 | |
6c36a707 | 360 | err_out_unregister_bus: |
298cf9be | 361 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 362 | err_out_free_mdio_irq: |
298cf9be LB |
363 | kfree(bp->mii_bus->irq); |
364 | err_out_free_mdiobus: | |
365 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
366 | err_out: |
367 | return err; | |
89e5785f | 368 | } |
0005f541 | 369 | EXPORT_SYMBOL_GPL(macb_mii_init); |
89e5785f HS |
370 | |
371 | static void macb_update_stats(struct macb *bp) | |
372 | { | |
373 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
a494ed8e JI |
374 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
375 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
89e5785f HS |
376 | |
377 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
378 | ||
379 | for(; p < end; p++, reg++) | |
0f0d84e5 | 380 | *p += __raw_readl(reg); |
89e5785f HS |
381 | } |
382 | ||
e86cd53a | 383 | static int macb_halt_tx(struct macb *bp) |
89e5785f | 384 | { |
e86cd53a NF |
385 | unsigned long halt_time, timeout; |
386 | u32 status; | |
89e5785f | 387 | |
e86cd53a | 388 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); |
89e5785f | 389 | |
e86cd53a NF |
390 | timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); |
391 | do { | |
392 | halt_time = jiffies; | |
393 | status = macb_readl(bp, TSR); | |
394 | if (!(status & MACB_BIT(TGO))) | |
395 | return 0; | |
89e5785f | 396 | |
e86cd53a NF |
397 | usleep_range(10, 250); |
398 | } while (time_before(halt_time, timeout)); | |
bdcba151 | 399 | |
e86cd53a NF |
400 | return -ETIMEDOUT; |
401 | } | |
39eddb4c | 402 | |
e86cd53a NF |
403 | static void macb_tx_error_task(struct work_struct *work) |
404 | { | |
405 | struct macb *bp = container_of(work, struct macb, tx_error_task); | |
406 | struct macb_tx_skb *tx_skb; | |
407 | struct sk_buff *skb; | |
408 | unsigned int tail; | |
bdcba151 | 409 | |
e86cd53a NF |
410 | netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n", |
411 | bp->tx_tail, bp->tx_head); | |
bdcba151 | 412 | |
e86cd53a NF |
413 | /* Make sure nobody is trying to queue up new packets */ |
414 | netif_stop_queue(bp->dev); | |
d3e61457 | 415 | |
e86cd53a NF |
416 | /* |
417 | * Stop transmission now | |
418 | * (in case we have just queued new packets) | |
419 | */ | |
420 | if (macb_halt_tx(bp)) | |
421 | /* Just complain for now, reinitializing TX path can be good */ | |
422 | netdev_err(bp->dev, "BUG: halt tx timed out\n"); | |
bdcba151 | 423 | |
e86cd53a | 424 | /* No need for the lock here as nobody will interrupt us anymore */ |
bdcba151 | 425 | |
e86cd53a NF |
426 | /* |
427 | * Treat frames in TX queue including the ones that caused the error. | |
428 | * Free transmit buffers in upper layer. | |
429 | */ | |
430 | for (tail = bp->tx_tail; tail != bp->tx_head; tail++) { | |
431 | struct macb_dma_desc *desc; | |
432 | u32 ctrl; | |
55054a16 | 433 | |
e86cd53a NF |
434 | desc = macb_tx_desc(bp, tail); |
435 | ctrl = desc->ctrl; | |
436 | tx_skb = macb_tx_skb(bp, tail); | |
437 | skb = tx_skb->skb; | |
bdcba151 | 438 | |
e86cd53a NF |
439 | if (ctrl & MACB_BIT(TX_USED)) { |
440 | netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", | |
441 | macb_tx_ring_wrap(tail), skb->data); | |
442 | bp->stats.tx_packets++; | |
443 | bp->stats.tx_bytes += skb->len; | |
444 | } else { | |
445 | /* | |
446 | * "Buffers exhausted mid-frame" errors may only happen | |
447 | * if the driver is buggy, so complain loudly about those. | |
448 | * Statistics are updated by hardware. | |
449 | */ | |
450 | if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) | |
451 | netdev_err(bp->dev, | |
452 | "BUG: TX buffers exhausted mid-frame\n"); | |
39eddb4c | 453 | |
e86cd53a NF |
454 | desc->ctrl = ctrl | MACB_BIT(TX_USED); |
455 | } | |
456 | ||
457 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, | |
458 | DMA_TO_DEVICE); | |
459 | tx_skb->skb = NULL; | |
460 | dev_kfree_skb(skb); | |
89e5785f HS |
461 | } |
462 | ||
e86cd53a NF |
463 | /* Make descriptor updates visible to hardware */ |
464 | wmb(); | |
465 | ||
466 | /* Reinitialize the TX desc queue */ | |
467 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
468 | /* Make TX ring reflect state of hardware */ | |
469 | bp->tx_head = bp->tx_tail = 0; | |
470 | ||
471 | /* Now we are ready to start transmission again */ | |
472 | netif_wake_queue(bp->dev); | |
473 | ||
474 | /* Housework before enabling TX IRQ */ | |
475 | macb_writel(bp, TSR, macb_readl(bp, TSR)); | |
476 | macb_writel(bp, IER, MACB_TX_INT_FLAGS); | |
477 | } | |
478 | ||
479 | static void macb_tx_interrupt(struct macb *bp) | |
480 | { | |
481 | unsigned int tail; | |
482 | unsigned int head; | |
483 | u32 status; | |
484 | ||
485 | status = macb_readl(bp, TSR); | |
486 | macb_writel(bp, TSR, status); | |
487 | ||
488 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", | |
489 | (unsigned long)status); | |
89e5785f HS |
490 | |
491 | head = bp->tx_head; | |
55054a16 HS |
492 | for (tail = bp->tx_tail; tail != head; tail++) { |
493 | struct macb_tx_skb *tx_skb; | |
494 | struct sk_buff *skb; | |
495 | struct macb_dma_desc *desc; | |
496 | u32 ctrl; | |
89e5785f | 497 | |
55054a16 | 498 | desc = macb_tx_desc(bp, tail); |
89e5785f | 499 | |
03dbe05f | 500 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 501 | rmb(); |
03dbe05f | 502 | |
55054a16 | 503 | ctrl = desc->ctrl; |
89e5785f | 504 | |
55054a16 | 505 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
506 | break; |
507 | ||
55054a16 HS |
508 | tx_skb = macb_tx_skb(bp, tail); |
509 | skb = tx_skb->skb; | |
510 | ||
a268adb1 | 511 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", |
55054a16 HS |
512 | macb_tx_ring_wrap(tail), skb->data); |
513 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, | |
89e5785f HS |
514 | DMA_TO_DEVICE); |
515 | bp->stats.tx_packets++; | |
516 | bp->stats.tx_bytes += skb->len; | |
55054a16 | 517 | tx_skb->skb = NULL; |
89e5785f HS |
518 | dev_kfree_skb_irq(skb); |
519 | } | |
520 | ||
521 | bp->tx_tail = tail; | |
55054a16 | 522 | if (netif_queue_stopped(bp->dev) |
909a8583 NF |
523 | && CIRC_CNT(bp->tx_head, bp->tx_tail, |
524 | TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH) | |
89e5785f HS |
525 | netif_wake_queue(bp->dev); |
526 | } | |
527 | ||
528 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
529 | unsigned int last_frag) | |
530 | { | |
531 | unsigned int len; | |
532 | unsigned int frag; | |
29bc2e1e | 533 | unsigned int offset; |
89e5785f | 534 | struct sk_buff *skb; |
55054a16 | 535 | struct macb_dma_desc *desc; |
89e5785f | 536 | |
55054a16 HS |
537 | desc = macb_rx_desc(bp, last_frag); |
538 | len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); | |
89e5785f | 539 | |
a268adb1 | 540 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
55054a16 HS |
541 | macb_rx_ring_wrap(first_frag), |
542 | macb_rx_ring_wrap(last_frag), len); | |
89e5785f | 543 | |
29bc2e1e HS |
544 | /* |
545 | * The ethernet header starts NET_IP_ALIGN bytes into the | |
546 | * first buffer. Since the header is 14 bytes, this makes the | |
547 | * payload word-aligned. | |
548 | * | |
549 | * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy | |
550 | * the two padding bytes into the skb so that we avoid hitting | |
551 | * the slowpath in memcpy(), and pull them off afterwards. | |
552 | */ | |
553 | skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); | |
89e5785f HS |
554 | if (!skb) { |
555 | bp->stats.rx_dropped++; | |
55054a16 HS |
556 | for (frag = first_frag; ; frag++) { |
557 | desc = macb_rx_desc(bp, frag); | |
558 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
559 | if (frag == last_frag) |
560 | break; | |
561 | } | |
03dbe05f HS |
562 | |
563 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 564 | wmb(); |
03dbe05f | 565 | |
89e5785f HS |
566 | return 1; |
567 | } | |
568 | ||
29bc2e1e HS |
569 | offset = 0; |
570 | len += NET_IP_ALIGN; | |
bc8acf2c | 571 | skb_checksum_none_assert(skb); |
89e5785f HS |
572 | skb_put(skb, len); |
573 | ||
55054a16 | 574 | for (frag = first_frag; ; frag++) { |
89e5785f HS |
575 | unsigned int frag_len = RX_BUFFER_SIZE; |
576 | ||
577 | if (offset + frag_len > len) { | |
578 | BUG_ON(frag != last_frag); | |
579 | frag_len = len - offset; | |
580 | } | |
27d7ff46 | 581 | skb_copy_to_linear_data_offset(skb, offset, |
55054a16 | 582 | macb_rx_buffer(bp, frag), frag_len); |
89e5785f | 583 | offset += RX_BUFFER_SIZE; |
55054a16 HS |
584 | desc = macb_rx_desc(bp, frag); |
585 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
586 | |
587 | if (frag == last_frag) | |
588 | break; | |
589 | } | |
590 | ||
03dbe05f HS |
591 | /* Make descriptor updates visible to hardware */ |
592 | wmb(); | |
593 | ||
29bc2e1e | 594 | __skb_pull(skb, NET_IP_ALIGN); |
89e5785f HS |
595 | skb->protocol = eth_type_trans(skb, bp->dev); |
596 | ||
597 | bp->stats.rx_packets++; | |
29bc2e1e | 598 | bp->stats.rx_bytes += skb->len; |
a268adb1 | 599 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
c220f8cd | 600 | skb->len, skb->csum); |
89e5785f HS |
601 | netif_receive_skb(skb); |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
607 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
608 | unsigned int end) | |
609 | { | |
610 | unsigned int frag; | |
611 | ||
55054a16 HS |
612 | for (frag = begin; frag != end; frag++) { |
613 | struct macb_dma_desc *desc = macb_rx_desc(bp, frag); | |
614 | desc->addr &= ~MACB_BIT(RX_USED); | |
615 | } | |
03dbe05f HS |
616 | |
617 | /* Make descriptor updates visible to hardware */ | |
89e5785f HS |
618 | wmb(); |
619 | ||
620 | /* | |
621 | * When this happens, the hardware stats registers for | |
622 | * whatever caused this is updated, so we don't have to record | |
623 | * anything. | |
624 | */ | |
625 | } | |
626 | ||
627 | static int macb_rx(struct macb *bp, int budget) | |
628 | { | |
629 | int received = 0; | |
55054a16 | 630 | unsigned int tail; |
89e5785f HS |
631 | int first_frag = -1; |
632 | ||
55054a16 HS |
633 | for (tail = bp->rx_tail; budget > 0; tail++) { |
634 | struct macb_dma_desc *desc = macb_rx_desc(bp, tail); | |
89e5785f HS |
635 | u32 addr, ctrl; |
636 | ||
03dbe05f | 637 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 638 | rmb(); |
03dbe05f | 639 | |
55054a16 HS |
640 | addr = desc->addr; |
641 | ctrl = desc->ctrl; | |
89e5785f HS |
642 | |
643 | if (!(addr & MACB_BIT(RX_USED))) | |
644 | break; | |
645 | ||
646 | if (ctrl & MACB_BIT(RX_SOF)) { | |
647 | if (first_frag != -1) | |
648 | discard_partial_frame(bp, first_frag, tail); | |
649 | first_frag = tail; | |
650 | } | |
651 | ||
652 | if (ctrl & MACB_BIT(RX_EOF)) { | |
653 | int dropped; | |
654 | BUG_ON(first_frag == -1); | |
655 | ||
656 | dropped = macb_rx_frame(bp, first_frag, tail); | |
657 | first_frag = -1; | |
658 | if (!dropped) { | |
659 | received++; | |
660 | budget--; | |
661 | } | |
662 | } | |
663 | } | |
664 | ||
665 | if (first_frag != -1) | |
666 | bp->rx_tail = first_frag; | |
667 | else | |
668 | bp->rx_tail = tail; | |
669 | ||
670 | return received; | |
671 | } | |
672 | ||
bea3348e | 673 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 674 | { |
bea3348e | 675 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 676 | int work_done; |
89e5785f HS |
677 | u32 status; |
678 | ||
679 | status = macb_readl(bp, RSR); | |
680 | macb_writel(bp, RSR, status); | |
681 | ||
bea3348e | 682 | work_done = 0; |
89e5785f | 683 | |
a268adb1 | 684 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
c220f8cd | 685 | (unsigned long)status, budget); |
89e5785f | 686 | |
bea3348e | 687 | work_done = macb_rx(bp, budget); |
b336369c | 688 | if (work_done < budget) { |
288379f0 | 689 | napi_complete(napi); |
89e5785f | 690 | |
b336369c JH |
691 | /* |
692 | * We've done what we can to clean the buffers. Make sure we | |
693 | * get notified when new packets arrive. | |
694 | */ | |
695 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
696 | } | |
89e5785f HS |
697 | |
698 | /* TODO: Handle errors */ | |
699 | ||
bea3348e | 700 | return work_done; |
89e5785f HS |
701 | } |
702 | ||
703 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
704 | { | |
705 | struct net_device *dev = dev_id; | |
706 | struct macb *bp = netdev_priv(dev); | |
707 | u32 status; | |
708 | ||
709 | status = macb_readl(bp, ISR); | |
710 | ||
711 | if (unlikely(!status)) | |
712 | return IRQ_NONE; | |
713 | ||
714 | spin_lock(&bp->lock); | |
715 | ||
716 | while (status) { | |
89e5785f HS |
717 | /* close possible race with dev_close */ |
718 | if (unlikely(!netif_running(dev))) { | |
95ebcea6 | 719 | macb_writel(bp, IDR, -1); |
89e5785f HS |
720 | break; |
721 | } | |
722 | ||
a268adb1 HS |
723 | netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status); |
724 | ||
89e5785f | 725 | if (status & MACB_RX_INT_FLAGS) { |
b336369c JH |
726 | /* |
727 | * There's no point taking any more interrupts | |
728 | * until we have processed the buffers. The | |
729 | * scheduling call may fail if the poll routine | |
730 | * is already scheduled, so disable interrupts | |
731 | * now. | |
732 | */ | |
733 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
734 | ||
288379f0 | 735 | if (napi_schedule_prep(&bp->napi)) { |
a268adb1 | 736 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 737 | __napi_schedule(&bp->napi); |
89e5785f HS |
738 | } |
739 | } | |
740 | ||
e86cd53a NF |
741 | if (unlikely(status & (MACB_TX_ERR_FLAGS))) { |
742 | macb_writel(bp, IDR, MACB_TX_INT_FLAGS); | |
743 | schedule_work(&bp->tx_error_task); | |
744 | break; | |
745 | } | |
746 | ||
747 | if (status & MACB_BIT(TCOMP)) | |
748 | macb_tx_interrupt(bp); | |
89e5785f HS |
749 | |
750 | /* | |
751 | * Link change detection isn't possible with RMII, so we'll | |
752 | * add that if/when we get our hands on a full-blown MII PHY. | |
753 | */ | |
754 | ||
b19f7f71 AS |
755 | if (status & MACB_BIT(ISR_ROVR)) { |
756 | /* We missed at least one packet */ | |
f75ba50b JI |
757 | if (macb_is_gem(bp)) |
758 | bp->hw_stats.gem.rx_overruns++; | |
759 | else | |
760 | bp->hw_stats.macb.rx_overruns++; | |
b19f7f71 AS |
761 | } |
762 | ||
89e5785f HS |
763 | if (status & MACB_BIT(HRESP)) { |
764 | /* | |
c220f8cd JI |
765 | * TODO: Reset the hardware, and maybe move the |
766 | * netdev_err to a lower-priority context as well | |
767 | * (work queue?) | |
89e5785f | 768 | */ |
c220f8cd | 769 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
89e5785f HS |
770 | } |
771 | ||
772 | status = macb_readl(bp, ISR); | |
773 | } | |
774 | ||
775 | spin_unlock(&bp->lock); | |
776 | ||
777 | return IRQ_HANDLED; | |
778 | } | |
779 | ||
6e8cf5c0 TP |
780 | #ifdef CONFIG_NET_POLL_CONTROLLER |
781 | /* | |
782 | * Polling receive - used by netconsole and other diagnostic tools | |
783 | * to allow network i/o with interrupts disabled. | |
784 | */ | |
785 | static void macb_poll_controller(struct net_device *dev) | |
786 | { | |
787 | unsigned long flags; | |
788 | ||
789 | local_irq_save(flags); | |
790 | macb_interrupt(dev->irq, dev); | |
791 | local_irq_restore(flags); | |
792 | } | |
793 | #endif | |
794 | ||
89e5785f HS |
795 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
796 | { | |
797 | struct macb *bp = netdev_priv(dev); | |
798 | dma_addr_t mapping; | |
799 | unsigned int len, entry; | |
55054a16 HS |
800 | struct macb_dma_desc *desc; |
801 | struct macb_tx_skb *tx_skb; | |
89e5785f | 802 | u32 ctrl; |
4871953c | 803 | unsigned long flags; |
89e5785f | 804 | |
a268adb1 HS |
805 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
806 | netdev_vdbg(bp->dev, | |
c220f8cd JI |
807 | "start_xmit: len %u head %p data %p tail %p end %p\n", |
808 | skb->len, skb->head, skb->data, | |
809 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
810 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
811 | skb->data, 16, true); | |
89e5785f HS |
812 | #endif |
813 | ||
814 | len = skb->len; | |
4871953c | 815 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
816 | |
817 | /* This is a hard error, log it. */ | |
909a8583 | 818 | if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) { |
89e5785f | 819 | netif_stop_queue(dev); |
4871953c | 820 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd JI |
821 | netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); |
822 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", | |
823 | bp->tx_head, bp->tx_tail); | |
5b548140 | 824 | return NETDEV_TX_BUSY; |
89e5785f HS |
825 | } |
826 | ||
55054a16 HS |
827 | entry = macb_tx_ring_wrap(bp->tx_head); |
828 | bp->tx_head++; | |
a268adb1 | 829 | netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry); |
89e5785f HS |
830 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
831 | len, DMA_TO_DEVICE); | |
55054a16 HS |
832 | |
833 | tx_skb = &bp->tx_skb[entry]; | |
834 | tx_skb->skb = skb; | |
835 | tx_skb->mapping = mapping; | |
a268adb1 | 836 | netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", |
c220f8cd | 837 | skb->data, (unsigned long)mapping); |
89e5785f HS |
838 | |
839 | ctrl = MACB_BF(TX_FRMLEN, len); | |
840 | ctrl |= MACB_BIT(TX_LAST); | |
841 | if (entry == (TX_RING_SIZE - 1)) | |
842 | ctrl |= MACB_BIT(TX_WRAP); | |
843 | ||
55054a16 HS |
844 | desc = &bp->tx_ring[entry]; |
845 | desc->addr = mapping; | |
846 | desc->ctrl = ctrl; | |
03dbe05f HS |
847 | |
848 | /* Make newly initialized descriptor visible to hardware */ | |
89e5785f HS |
849 | wmb(); |
850 | ||
e072092f RC |
851 | skb_tx_timestamp(skb); |
852 | ||
89e5785f HS |
853 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
854 | ||
909a8583 | 855 | if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) |
89e5785f HS |
856 | netif_stop_queue(dev); |
857 | ||
4871953c | 858 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 859 | |
6ed10654 | 860 | return NETDEV_TX_OK; |
89e5785f HS |
861 | } |
862 | ||
863 | static void macb_free_consistent(struct macb *bp) | |
864 | { | |
865 | if (bp->tx_skb) { | |
866 | kfree(bp->tx_skb); | |
867 | bp->tx_skb = NULL; | |
868 | } | |
869 | if (bp->rx_ring) { | |
870 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
871 | bp->rx_ring, bp->rx_ring_dma); | |
872 | bp->rx_ring = NULL; | |
873 | } | |
874 | if (bp->tx_ring) { | |
875 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
876 | bp->tx_ring, bp->tx_ring_dma); | |
877 | bp->tx_ring = NULL; | |
878 | } | |
879 | if (bp->rx_buffers) { | |
880 | dma_free_coherent(&bp->pdev->dev, | |
881 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
882 | bp->rx_buffers, bp->rx_buffers_dma); | |
883 | bp->rx_buffers = NULL; | |
884 | } | |
885 | } | |
886 | ||
887 | static int macb_alloc_consistent(struct macb *bp) | |
888 | { | |
889 | int size; | |
890 | ||
55054a16 | 891 | size = TX_RING_SIZE * sizeof(struct macb_tx_skb); |
89e5785f HS |
892 | bp->tx_skb = kmalloc(size, GFP_KERNEL); |
893 | if (!bp->tx_skb) | |
894 | goto out_err; | |
895 | ||
896 | size = RX_RING_BYTES; | |
897 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
898 | &bp->rx_ring_dma, GFP_KERNEL); | |
899 | if (!bp->rx_ring) | |
900 | goto out_err; | |
c220f8cd JI |
901 | netdev_dbg(bp->dev, |
902 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
903 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f HS |
904 | |
905 | size = TX_RING_BYTES; | |
906 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
907 | &bp->tx_ring_dma, GFP_KERNEL); | |
908 | if (!bp->tx_ring) | |
909 | goto out_err; | |
c220f8cd JI |
910 | netdev_dbg(bp->dev, |
911 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
912 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
89e5785f HS |
913 | |
914 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
915 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
916 | &bp->rx_buffers_dma, GFP_KERNEL); | |
917 | if (!bp->rx_buffers) | |
918 | goto out_err; | |
c220f8cd JI |
919 | netdev_dbg(bp->dev, |
920 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
921 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
89e5785f HS |
922 | |
923 | return 0; | |
924 | ||
925 | out_err: | |
926 | macb_free_consistent(bp); | |
927 | return -ENOMEM; | |
928 | } | |
929 | ||
930 | static void macb_init_rings(struct macb *bp) | |
931 | { | |
932 | int i; | |
933 | dma_addr_t addr; | |
934 | ||
935 | addr = bp->rx_buffers_dma; | |
936 | for (i = 0; i < RX_RING_SIZE; i++) { | |
937 | bp->rx_ring[i].addr = addr; | |
938 | bp->rx_ring[i].ctrl = 0; | |
939 | addr += RX_BUFFER_SIZE; | |
940 | } | |
941 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
942 | ||
943 | for (i = 0; i < TX_RING_SIZE; i++) { | |
944 | bp->tx_ring[i].addr = 0; | |
945 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
946 | } | |
947 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
948 | ||
949 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
950 | } | |
951 | ||
952 | static void macb_reset_hw(struct macb *bp) | |
953 | { | |
89e5785f HS |
954 | /* |
955 | * Disable RX and TX (XXX: Should we halt the transmission | |
956 | * more gracefully?) | |
957 | */ | |
958 | macb_writel(bp, NCR, 0); | |
959 | ||
960 | /* Clear the stats registers (XXX: Update stats first?) */ | |
961 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
962 | ||
963 | /* Clear all status flags */ | |
95ebcea6 JE |
964 | macb_writel(bp, TSR, -1); |
965 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
966 | |
967 | /* Disable all interrupts */ | |
95ebcea6 | 968 | macb_writel(bp, IDR, -1); |
89e5785f HS |
969 | macb_readl(bp, ISR); |
970 | } | |
971 | ||
70c9f3d4 JI |
972 | static u32 gem_mdc_clk_div(struct macb *bp) |
973 | { | |
974 | u32 config; | |
975 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
976 | ||
977 | if (pclk_hz <= 20000000) | |
978 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
979 | else if (pclk_hz <= 40000000) | |
980 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
981 | else if (pclk_hz <= 80000000) | |
982 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
983 | else if (pclk_hz <= 120000000) | |
984 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
985 | else if (pclk_hz <= 160000000) | |
986 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
987 | else | |
988 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
989 | ||
990 | return config; | |
991 | } | |
992 | ||
993 | static u32 macb_mdc_clk_div(struct macb *bp) | |
994 | { | |
995 | u32 config; | |
996 | unsigned long pclk_hz; | |
997 | ||
998 | if (macb_is_gem(bp)) | |
999 | return gem_mdc_clk_div(bp); | |
1000 | ||
1001 | pclk_hz = clk_get_rate(bp->pclk); | |
1002 | if (pclk_hz <= 20000000) | |
1003 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1004 | else if (pclk_hz <= 40000000) | |
1005 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1006 | else if (pclk_hz <= 80000000) | |
1007 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1008 | else | |
1009 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1010 | ||
1011 | return config; | |
1012 | } | |
1013 | ||
757a03c6 JI |
1014 | /* |
1015 | * Get the DMA bus width field of the network configuration register that we | |
1016 | * should program. We find the width from decoding the design configuration | |
1017 | * register to find the maximum supported data bus width. | |
1018 | */ | |
1019 | static u32 macb_dbw(struct macb *bp) | |
1020 | { | |
1021 | if (!macb_is_gem(bp)) | |
1022 | return 0; | |
1023 | ||
1024 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
1025 | case 4: | |
1026 | return GEM_BF(DBW, GEM_DBW128); | |
1027 | case 2: | |
1028 | return GEM_BF(DBW, GEM_DBW64); | |
1029 | case 1: | |
1030 | default: | |
1031 | return GEM_BF(DBW, GEM_DBW32); | |
1032 | } | |
1033 | } | |
1034 | ||
0116da4f JI |
1035 | /* |
1036 | * Configure the receive DMA engine to use the correct receive buffer size. | |
1037 | * This is a configurable parameter for GEM. | |
1038 | */ | |
1039 | static void macb_configure_dma(struct macb *bp) | |
1040 | { | |
1041 | u32 dmacfg; | |
1042 | ||
1043 | if (macb_is_gem(bp)) { | |
1044 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
1045 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); | |
1046 | gem_writel(bp, DMACFG, dmacfg); | |
1047 | } | |
1048 | } | |
1049 | ||
89e5785f HS |
1050 | static void macb_init_hw(struct macb *bp) |
1051 | { | |
1052 | u32 config; | |
1053 | ||
1054 | macb_reset_hw(bp); | |
314bccc4 | 1055 | macb_set_hwaddr(bp); |
89e5785f | 1056 | |
70c9f3d4 | 1057 | config = macb_mdc_clk_div(bp); |
29bc2e1e | 1058 | config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ |
89e5785f HS |
1059 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
1060 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 1061 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
1062 | if (bp->dev->flags & IFF_PROMISC) |
1063 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
1064 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
1065 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 1066 | config |= macb_dbw(bp); |
89e5785f | 1067 | macb_writel(bp, NCFGR, config); |
26cdfb49 VD |
1068 | bp->speed = SPEED_10; |
1069 | bp->duplex = DUPLEX_HALF; | |
89e5785f | 1070 | |
0116da4f JI |
1071 | macb_configure_dma(bp); |
1072 | ||
89e5785f HS |
1073 | /* Initialize TX and RX buffers */ |
1074 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
1075 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
1076 | ||
1077 | /* Enable TX and RX */ | |
6c36a707 | 1078 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
1079 | |
1080 | /* Enable interrupts */ | |
e86cd53a NF |
1081 | macb_writel(bp, IER, (MACB_RX_INT_FLAGS |
1082 | | MACB_TX_INT_FLAGS | |
89e5785f | 1083 | | MACB_BIT(HRESP))); |
89e5785f | 1084 | |
89e5785f HS |
1085 | } |
1086 | ||
446ebd01 PV |
1087 | /* |
1088 | * The hash address register is 64 bits long and takes up two | |
1089 | * locations in the memory map. The least significant bits are stored | |
1090 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
1091 | * | |
1092 | * The unicast hash enable and the multicast hash enable bits in the | |
1093 | * network configuration register enable the reception of hash matched | |
1094 | * frames. The destination address is reduced to a 6 bit index into | |
1095 | * the 64 bit hash register using the following hash function. The | |
1096 | * hash function is an exclusive or of every sixth bit of the | |
1097 | * destination address. | |
1098 | * | |
1099 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
1100 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
1101 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
1102 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
1103 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
1104 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
1105 | * | |
1106 | * da[0] represents the least significant bit of the first byte | |
1107 | * received, that is, the multicast/unicast indicator, and da[47] | |
1108 | * represents the most significant bit of the last byte received. If | |
1109 | * the hash index, hi[n], points to a bit that is set in the hash | |
1110 | * register then the frame will be matched according to whether the | |
1111 | * frame is multicast or unicast. A multicast match will be signalled | |
1112 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
1113 | * index points to a bit set in the hash register. A unicast match | |
1114 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
1115 | * and the hash index points to a bit set in the hash register. To | |
1116 | * receive all multicast frames, the hash register should be set with | |
1117 | * all ones and the multicast hash enable bit should be set in the | |
1118 | * network configuration register. | |
1119 | */ | |
1120 | ||
1121 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
1122 | { | |
1123 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
1124 | return 1; | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Return the hash index value for the specified address. | |
1130 | */ | |
1131 | static int hash_get_index(__u8 *addr) | |
1132 | { | |
1133 | int i, j, bitval; | |
1134 | int hash_index = 0; | |
1135 | ||
1136 | for (j = 0; j < 6; j++) { | |
1137 | for (i = 0, bitval = 0; i < 8; i++) | |
1138 | bitval ^= hash_bit_value(i*6 + j, addr); | |
1139 | ||
1140 | hash_index |= (bitval << j); | |
1141 | } | |
1142 | ||
1143 | return hash_index; | |
1144 | } | |
1145 | ||
1146 | /* | |
1147 | * Add multicast addresses to the internal multicast-hash table. | |
1148 | */ | |
1149 | static void macb_sethashtable(struct net_device *dev) | |
1150 | { | |
22bedad3 | 1151 | struct netdev_hw_addr *ha; |
446ebd01 | 1152 | unsigned long mc_filter[2]; |
f9dcbcc9 | 1153 | unsigned int bitnr; |
446ebd01 PV |
1154 | struct macb *bp = netdev_priv(dev); |
1155 | ||
1156 | mc_filter[0] = mc_filter[1] = 0; | |
1157 | ||
22bedad3 JP |
1158 | netdev_for_each_mc_addr(ha, dev) { |
1159 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
1160 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
1161 | } | |
1162 | ||
f75ba50b JI |
1163 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
1164 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
1165 | } |
1166 | ||
1167 | /* | |
1168 | * Enable/Disable promiscuous and multicast modes. | |
1169 | */ | |
e0da1f14 | 1170 | void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
1171 | { |
1172 | unsigned long cfg; | |
1173 | struct macb *bp = netdev_priv(dev); | |
1174 | ||
1175 | cfg = macb_readl(bp, NCFGR); | |
1176 | ||
1177 | if (dev->flags & IFF_PROMISC) | |
1178 | /* Enable promiscuous mode */ | |
1179 | cfg |= MACB_BIT(CAF); | |
1180 | else if (dev->flags & (~IFF_PROMISC)) | |
1181 | /* Disable promiscuous mode */ | |
1182 | cfg &= ~MACB_BIT(CAF); | |
1183 | ||
1184 | if (dev->flags & IFF_ALLMULTI) { | |
1185 | /* Enable all multicast mode */ | |
f75ba50b JI |
1186 | macb_or_gem_writel(bp, HRB, -1); |
1187 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1188 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1189 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1190 | /* Enable specific multicasts */ |
1191 | macb_sethashtable(dev); | |
1192 | cfg |= MACB_BIT(NCFGR_MTI); | |
1193 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1194 | /* Disable all multicast mode */ | |
f75ba50b JI |
1195 | macb_or_gem_writel(bp, HRB, 0); |
1196 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1197 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1198 | } | |
1199 | ||
1200 | macb_writel(bp, NCFGR, cfg); | |
1201 | } | |
e0da1f14 | 1202 | EXPORT_SYMBOL_GPL(macb_set_rx_mode); |
446ebd01 | 1203 | |
89e5785f HS |
1204 | static int macb_open(struct net_device *dev) |
1205 | { | |
1206 | struct macb *bp = netdev_priv(dev); | |
1207 | int err; | |
1208 | ||
c220f8cd | 1209 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1210 | |
03fc4721 NF |
1211 | /* carrier starts down */ |
1212 | netif_carrier_off(dev); | |
1213 | ||
6c36a707 R |
1214 | /* if the phy is not yet register, retry later*/ |
1215 | if (!bp->phy_dev) | |
1216 | return -EAGAIN; | |
1217 | ||
89e5785f HS |
1218 | if (!is_valid_ether_addr(dev->dev_addr)) |
1219 | return -EADDRNOTAVAIL; | |
1220 | ||
1221 | err = macb_alloc_consistent(bp); | |
1222 | if (err) { | |
c220f8cd JI |
1223 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1224 | err); | |
89e5785f HS |
1225 | return err; |
1226 | } | |
1227 | ||
bea3348e SH |
1228 | napi_enable(&bp->napi); |
1229 | ||
89e5785f HS |
1230 | macb_init_rings(bp); |
1231 | macb_init_hw(bp); | |
89e5785f | 1232 | |
6c36a707 R |
1233 | /* schedule a link state check */ |
1234 | phy_start(bp->phy_dev); | |
89e5785f | 1235 | |
6c36a707 | 1236 | netif_start_queue(dev); |
89e5785f HS |
1237 | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | static int macb_close(struct net_device *dev) | |
1242 | { | |
1243 | struct macb *bp = netdev_priv(dev); | |
1244 | unsigned long flags; | |
1245 | ||
89e5785f | 1246 | netif_stop_queue(dev); |
bea3348e | 1247 | napi_disable(&bp->napi); |
89e5785f | 1248 | |
6c36a707 R |
1249 | if (bp->phy_dev) |
1250 | phy_stop(bp->phy_dev); | |
1251 | ||
89e5785f HS |
1252 | spin_lock_irqsave(&bp->lock, flags); |
1253 | macb_reset_hw(bp); | |
1254 | netif_carrier_off(dev); | |
1255 | spin_unlock_irqrestore(&bp->lock, flags); | |
1256 | ||
1257 | macb_free_consistent(bp); | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
a494ed8e JI |
1262 | static void gem_update_stats(struct macb *bp) |
1263 | { | |
1264 | u32 __iomem *reg = bp->regs + GEM_OTX; | |
1265 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; | |
1266 | u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; | |
1267 | ||
1268 | for (; p < end; p++, reg++) | |
1269 | *p += __raw_readl(reg); | |
1270 | } | |
1271 | ||
1272 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
1273 | { | |
1274 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
1275 | struct net_device_stats *nstat = &bp->stats; | |
1276 | ||
1277 | gem_update_stats(bp); | |
1278 | ||
1279 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
1280 | hwstat->rx_alignment_errors + | |
1281 | hwstat->rx_resource_errors + | |
1282 | hwstat->rx_overruns + | |
1283 | hwstat->rx_oversize_frames + | |
1284 | hwstat->rx_jabbers + | |
1285 | hwstat->rx_undersized_frames + | |
1286 | hwstat->rx_length_field_frame_errors); | |
1287 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
1288 | hwstat->tx_excessive_collisions + | |
1289 | hwstat->tx_underrun + | |
1290 | hwstat->tx_carrier_sense_errors); | |
1291 | nstat->multicast = hwstat->rx_multicast_frames; | |
1292 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
1293 | hwstat->tx_multiple_collision_frames + | |
1294 | hwstat->tx_excessive_collisions); | |
1295 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
1296 | hwstat->rx_jabbers + | |
1297 | hwstat->rx_undersized_frames + | |
1298 | hwstat->rx_length_field_frame_errors); | |
1299 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1300 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
1301 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
1302 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1303 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
1304 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
1305 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
1306 | ||
1307 | return nstat; | |
1308 | } | |
1309 | ||
2ea32eed | 1310 | struct net_device_stats *macb_get_stats(struct net_device *dev) |
89e5785f HS |
1311 | { |
1312 | struct macb *bp = netdev_priv(dev); | |
1313 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
1314 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
1315 | ||
1316 | if (macb_is_gem(bp)) | |
1317 | return gem_get_stats(bp); | |
89e5785f | 1318 | |
6c36a707 R |
1319 | /* read stats from hardware */ |
1320 | macb_update_stats(bp); | |
1321 | ||
89e5785f HS |
1322 | /* Convert HW stats into netdevice stats */ |
1323 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1324 | hwstat->rx_align_errors + | |
1325 | hwstat->rx_resource_errors + | |
1326 | hwstat->rx_overruns + | |
1327 | hwstat->rx_oversize_pkts + | |
1328 | hwstat->rx_jabbers + | |
1329 | hwstat->rx_undersize_pkts + | |
1330 | hwstat->sqe_test_errors + | |
1331 | hwstat->rx_length_mismatch); | |
1332 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1333 | hwstat->tx_excessive_cols + | |
1334 | hwstat->tx_underruns + | |
1335 | hwstat->tx_carrier_errors); | |
1336 | nstat->collisions = (hwstat->tx_single_cols + | |
1337 | hwstat->tx_multiple_cols + | |
1338 | hwstat->tx_excessive_cols); | |
1339 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1340 | hwstat->rx_jabbers + | |
1341 | hwstat->rx_undersize_pkts + | |
1342 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1343 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1344 | hwstat->rx_overruns; | |
89e5785f HS |
1345 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1346 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1347 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1348 | /* XXX: What does "missed" mean? */ | |
1349 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1350 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1351 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1352 | /* Don't know about heartbeat or window errors... */ | |
1353 | ||
1354 | return nstat; | |
1355 | } | |
2ea32eed | 1356 | EXPORT_SYMBOL_GPL(macb_get_stats); |
89e5785f HS |
1357 | |
1358 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1359 | { | |
1360 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1361 | struct phy_device *phydev = bp->phy_dev; |
1362 | ||
1363 | if (!phydev) | |
1364 | return -ENODEV; | |
89e5785f | 1365 | |
6c36a707 | 1366 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1367 | } |
1368 | ||
1369 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1370 | { | |
1371 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1372 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1373 | |
6c36a707 R |
1374 | if (!phydev) |
1375 | return -ENODEV; | |
1376 | ||
1377 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1378 | } |
1379 | ||
d1d1b53d NF |
1380 | static int macb_get_regs_len(struct net_device *netdev) |
1381 | { | |
1382 | return MACB_GREGS_NBR * sizeof(u32); | |
1383 | } | |
1384 | ||
1385 | static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1386 | void *p) | |
1387 | { | |
1388 | struct macb *bp = netdev_priv(dev); | |
1389 | unsigned int tail, head; | |
1390 | u32 *regs_buff = p; | |
1391 | ||
1392 | regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) | |
1393 | | MACB_GREGS_VERSION; | |
1394 | ||
1395 | tail = macb_tx_ring_wrap(bp->tx_tail); | |
1396 | head = macb_tx_ring_wrap(bp->tx_head); | |
1397 | ||
1398 | regs_buff[0] = macb_readl(bp, NCR); | |
1399 | regs_buff[1] = macb_or_gem_readl(bp, NCFGR); | |
1400 | regs_buff[2] = macb_readl(bp, NSR); | |
1401 | regs_buff[3] = macb_readl(bp, TSR); | |
1402 | regs_buff[4] = macb_readl(bp, RBQP); | |
1403 | regs_buff[5] = macb_readl(bp, TBQP); | |
1404 | regs_buff[6] = macb_readl(bp, RSR); | |
1405 | regs_buff[7] = macb_readl(bp, IMR); | |
1406 | ||
1407 | regs_buff[8] = tail; | |
1408 | regs_buff[9] = head; | |
1409 | regs_buff[10] = macb_tx_dma(bp, tail); | |
1410 | regs_buff[11] = macb_tx_dma(bp, head); | |
1411 | ||
1412 | if (macb_is_gem(bp)) { | |
1413 | regs_buff[12] = gem_readl(bp, USRIO); | |
1414 | regs_buff[13] = gem_readl(bp, DMACFG); | |
1415 | } | |
1416 | } | |
1417 | ||
0005f541 | 1418 | const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
1419 | .get_settings = macb_get_settings, |
1420 | .set_settings = macb_set_settings, | |
d1d1b53d NF |
1421 | .get_regs_len = macb_get_regs_len, |
1422 | .get_regs = macb_get_regs, | |
89e5785f | 1423 | .get_link = ethtool_op_get_link, |
17f393e8 | 1424 | .get_ts_info = ethtool_op_get_ts_info, |
89e5785f | 1425 | }; |
0005f541 | 1426 | EXPORT_SYMBOL_GPL(macb_ethtool_ops); |
89e5785f | 1427 | |
0005f541 | 1428 | int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f HS |
1429 | { |
1430 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1431 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1432 | |
1433 | if (!netif_running(dev)) | |
1434 | return -EINVAL; | |
1435 | ||
6c36a707 R |
1436 | if (!phydev) |
1437 | return -ENODEV; | |
89e5785f | 1438 | |
28b04113 | 1439 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f | 1440 | } |
0005f541 | 1441 | EXPORT_SYMBOL_GPL(macb_ioctl); |
89e5785f | 1442 | |
5f1fa992 AB |
1443 | static const struct net_device_ops macb_netdev_ops = { |
1444 | .ndo_open = macb_open, | |
1445 | .ndo_stop = macb_close, | |
1446 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 1447 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
1448 | .ndo_get_stats = macb_get_stats, |
1449 | .ndo_do_ioctl = macb_ioctl, | |
1450 | .ndo_validate_addr = eth_validate_addr, | |
1451 | .ndo_change_mtu = eth_change_mtu, | |
1452 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
1453 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1454 | .ndo_poll_controller = macb_poll_controller, | |
1455 | #endif | |
5f1fa992 AB |
1456 | }; |
1457 | ||
fb97a846 JCPV |
1458 | #if defined(CONFIG_OF) |
1459 | static const struct of_device_id macb_dt_ids[] = { | |
1460 | { .compatible = "cdns,at32ap7000-macb" }, | |
1461 | { .compatible = "cdns,at91sam9260-macb" }, | |
1462 | { .compatible = "cdns,macb" }, | |
1463 | { .compatible = "cdns,pc302-gem" }, | |
1464 | { .compatible = "cdns,gem" }, | |
1465 | { /* sentinel */ } | |
1466 | }; | |
1467 | ||
1468 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
1469 | ||
1470 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1471 | { | |
1472 | struct device_node *np = pdev->dev.of_node; | |
1473 | ||
1474 | if (np) | |
1475 | return of_get_phy_mode(np); | |
1476 | ||
1477 | return -ENODEV; | |
1478 | } | |
1479 | ||
1480 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1481 | { | |
1482 | struct device_node *np = bp->pdev->dev.of_node; | |
1483 | if (np) { | |
1484 | const char *mac = of_get_mac_address(np); | |
1485 | if (mac) { | |
1486 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | |
1487 | return 0; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | return -ENODEV; | |
1492 | } | |
1493 | #else | |
1494 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1495 | { | |
1496 | return -ENODEV; | |
1497 | } | |
1498 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1499 | { | |
1500 | return -ENODEV; | |
1501 | } | |
1502 | #endif | |
1503 | ||
06c3fd6a | 1504 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f | 1505 | { |
84e0cdb0 | 1506 | struct macb_platform_data *pdata; |
89e5785f HS |
1507 | struct resource *regs; |
1508 | struct net_device *dev; | |
1509 | struct macb *bp; | |
6c36a707 | 1510 | struct phy_device *phydev; |
89e5785f HS |
1511 | u32 config; |
1512 | int err = -ENXIO; | |
8ef29f8a | 1513 | struct pinctrl *pinctrl; |
89e5785f HS |
1514 | |
1515 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1516 | if (!regs) { | |
1517 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1518 | goto err_out; | |
1519 | } | |
1520 | ||
8ef29f8a JCPV |
1521 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1522 | if (IS_ERR(pinctrl)) { | |
1523 | err = PTR_ERR(pinctrl); | |
1524 | if (err == -EPROBE_DEFER) | |
1525 | goto err_out; | |
1526 | ||
1527 | dev_warn(&pdev->dev, "No pinctrl provided\n"); | |
1528 | } | |
1529 | ||
89e5785f HS |
1530 | err = -ENOMEM; |
1531 | dev = alloc_etherdev(sizeof(*bp)); | |
41de8d4c | 1532 | if (!dev) |
89e5785f | 1533 | goto err_out; |
89e5785f | 1534 | |
89e5785f HS |
1535 | SET_NETDEV_DEV(dev, &pdev->dev); |
1536 | ||
1537 | /* TODO: Actually, we have some interesting features... */ | |
1538 | dev->features |= 0; | |
1539 | ||
1540 | bp = netdev_priv(dev); | |
1541 | bp->pdev = pdev; | |
1542 | bp->dev = dev; | |
1543 | ||
1544 | spin_lock_init(&bp->lock); | |
e86cd53a | 1545 | INIT_WORK(&bp->tx_error_task, macb_tx_error_task); |
89e5785f | 1546 | |
461845db | 1547 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
0cc8674f AV |
1548 | if (IS_ERR(bp->pclk)) { |
1549 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1550 | goto err_out_free_dev; | |
1551 | } | |
1552 | clk_enable(bp->pclk); | |
461845db | 1553 | |
89e5785f HS |
1554 | bp->hclk = clk_get(&pdev->dev, "hclk"); |
1555 | if (IS_ERR(bp->hclk)) { | |
1556 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1557 | goto err_out_put_pclk; | |
1558 | } | |
89e5785f HS |
1559 | clk_enable(bp->hclk); |
1560 | ||
28f65c11 | 1561 | bp->regs = ioremap(regs->start, resource_size(regs)); |
89e5785f HS |
1562 | if (!bp->regs) { |
1563 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1564 | err = -ENOMEM; | |
1565 | goto err_out_disable_clocks; | |
1566 | } | |
1567 | ||
1568 | dev->irq = platform_get_irq(pdev, 0); | |
ab392d2d | 1569 | err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); |
89e5785f | 1570 | if (err) { |
c220f8cd JI |
1571 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", |
1572 | dev->irq, err); | |
89e5785f HS |
1573 | goto err_out_iounmap; |
1574 | } | |
1575 | ||
5f1fa992 | 1576 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 1577 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1578 | dev->ethtool_ops = &macb_ethtool_ops; |
1579 | ||
1580 | dev->base_addr = regs->start; | |
1581 | ||
89e5785f | 1582 | /* Set MII management clock divider */ |
70c9f3d4 | 1583 | config = macb_mdc_clk_div(bp); |
757a03c6 | 1584 | config |= macb_dbw(bp); |
89e5785f HS |
1585 | macb_writel(bp, NCFGR, config); |
1586 | ||
fb97a846 JCPV |
1587 | err = macb_get_hwaddr_dt(bp); |
1588 | if (err < 0) | |
1589 | macb_get_hwaddr(bp); | |
1590 | ||
1591 | err = macb_get_phy_mode_dt(pdev); | |
1592 | if (err < 0) { | |
1593 | pdata = pdev->dev.platform_data; | |
1594 | if (pdata && pdata->is_rmii) | |
1595 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
1596 | else | |
1597 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
1598 | } else { | |
1599 | bp->phy_interface = err; | |
1600 | } | |
6c36a707 | 1601 | |
140b7552 PV |
1602 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) |
1603 | macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); | |
1604 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
0cc8674f | 1605 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b JI |
1606 | macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | |
1607 | MACB_BIT(CLKEN))); | |
0cc8674f | 1608 | #else |
f75ba50b | 1609 | macb_or_gem_writel(bp, USRIO, 0); |
0cc8674f | 1610 | #endif |
89e5785f | 1611 | else |
0cc8674f | 1612 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b | 1613 | macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); |
0cc8674f | 1614 | #else |
f75ba50b | 1615 | macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1616 | #endif |
89e5785f | 1617 | |
89e5785f HS |
1618 | err = register_netdev(dev); |
1619 | if (err) { | |
1620 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1621 | goto err_out_free_irq; | |
1622 | } | |
1623 | ||
6c36a707 R |
1624 | if (macb_mii_init(bp) != 0) { |
1625 | goto err_out_unregister_netdev; | |
1626 | } | |
89e5785f | 1627 | |
6c36a707 | 1628 | platform_set_drvdata(pdev, dev); |
89e5785f | 1629 | |
03fc4721 NF |
1630 | netif_carrier_off(dev); |
1631 | ||
f75ba50b JI |
1632 | netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", |
1633 | macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, | |
1634 | dev->irq, dev->dev_addr); | |
89e5785f | 1635 | |
6c36a707 | 1636 | phydev = bp->phy_dev; |
c220f8cd JI |
1637 | netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1638 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 1639 | |
89e5785f HS |
1640 | return 0; |
1641 | ||
6c36a707 R |
1642 | err_out_unregister_netdev: |
1643 | unregister_netdev(dev); | |
89e5785f HS |
1644 | err_out_free_irq: |
1645 | free_irq(dev->irq, dev); | |
1646 | err_out_iounmap: | |
1647 | iounmap(bp->regs); | |
1648 | err_out_disable_clocks: | |
1649 | clk_disable(bp->hclk); | |
89e5785f | 1650 | clk_put(bp->hclk); |
0cc8674f | 1651 | clk_disable(bp->pclk); |
89e5785f HS |
1652 | err_out_put_pclk: |
1653 | clk_put(bp->pclk); | |
1654 | err_out_free_dev: | |
1655 | free_netdev(dev); | |
1656 | err_out: | |
1657 | platform_set_drvdata(pdev, NULL); | |
1658 | return err; | |
1659 | } | |
1660 | ||
06c3fd6a | 1661 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1662 | { |
1663 | struct net_device *dev; | |
1664 | struct macb *bp; | |
1665 | ||
1666 | dev = platform_get_drvdata(pdev); | |
1667 | ||
1668 | if (dev) { | |
1669 | bp = netdev_priv(dev); | |
84b7901f AN |
1670 | if (bp->phy_dev) |
1671 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1672 | mdiobus_unregister(bp->mii_bus); |
1673 | kfree(bp->mii_bus->irq); | |
1674 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1675 | unregister_netdev(dev); |
1676 | free_irq(dev->irq, dev); | |
1677 | iounmap(bp->regs); | |
1678 | clk_disable(bp->hclk); | |
89e5785f | 1679 | clk_put(bp->hclk); |
0cc8674f | 1680 | clk_disable(bp->pclk); |
89e5785f HS |
1681 | clk_put(bp->pclk); |
1682 | free_netdev(dev); | |
1683 | platform_set_drvdata(pdev, NULL); | |
1684 | } | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
c1f598fd HS |
1689 | #ifdef CONFIG_PM |
1690 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1691 | { | |
1692 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1693 | struct macb *bp = netdev_priv(netdev); | |
1694 | ||
03fc4721 | 1695 | netif_carrier_off(netdev); |
c1f598fd HS |
1696 | netif_device_detach(netdev); |
1697 | ||
c1f598fd | 1698 | clk_disable(bp->hclk); |
c1f598fd HS |
1699 | clk_disable(bp->pclk); |
1700 | ||
1701 | return 0; | |
1702 | } | |
1703 | ||
1704 | static int macb_resume(struct platform_device *pdev) | |
1705 | { | |
1706 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1707 | struct macb *bp = netdev_priv(netdev); | |
1708 | ||
1709 | clk_enable(bp->pclk); | |
c1f598fd | 1710 | clk_enable(bp->hclk); |
c1f598fd HS |
1711 | |
1712 | netif_device_attach(netdev); | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | #else | |
1717 | #define macb_suspend NULL | |
1718 | #define macb_resume NULL | |
1719 | #endif | |
1720 | ||
89e5785f | 1721 | static struct platform_driver macb_driver = { |
06c3fd6a | 1722 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1723 | .suspend = macb_suspend, |
1724 | .resume = macb_resume, | |
89e5785f HS |
1725 | .driver = { |
1726 | .name = "macb", | |
72abb461 | 1727 | .owner = THIS_MODULE, |
fb97a846 | 1728 | .of_match_table = of_match_ptr(macb_dt_ids), |
89e5785f HS |
1729 | }, |
1730 | }; | |
1731 | ||
1732 | static int __init macb_init(void) | |
1733 | { | |
06c3fd6a | 1734 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1735 | } |
1736 | ||
1737 | static void __exit macb_exit(void) | |
1738 | { | |
1739 | platform_driver_unregister(&macb_driver); | |
1740 | } | |
1741 | ||
1742 | module_init(macb_init); | |
1743 | module_exit(macb_exit); | |
1744 | ||
1745 | MODULE_LICENSE("GPL"); | |
f75ba50b | 1746 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 1747 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 1748 | MODULE_ALIAS("platform:macb"); |