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f21fb3ed RV |
1 | /********************************************************************** |
2 | * Author: Cavium, Inc. | |
3 | * | |
4 | * Contact: support@cavium.com | |
5 | * Please include "LiquidIO" in the subject. | |
6 | * | |
7 | * Copyright (c) 2003-2015 Cavium, Inc. | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * This file may also be available under a different license from Cavium. | |
20 | * Contact Cavium, Inc. for more information | |
21 | **********************************************************************/ | |
22 | ||
23 | /*! \file octeon_device.h | |
24 | * \brief Host Driver: This file defines the octeon device structure. | |
25 | */ | |
26 | ||
27 | #ifndef _OCTEON_DEVICE_H_ | |
28 | #define _OCTEON_DEVICE_H_ | |
29 | ||
30 | /** PCI VendorId Device Id */ | |
31 | #define OCTEON_CN68XX_PCIID 0x91177d | |
32 | #define OCTEON_CN66XX_PCIID 0x92177d | |
e86b1ab6 | 33 | #define OCTEON_CN23XX_PCIID_PF 0x9702177d |
f21fb3ed RV |
34 | /** Driver identifies chips by these Ids, created by clubbing together |
35 | * DeviceId+RevisionId; Where Revision Id is not used to distinguish | |
36 | * between chips, a value of 0 is used for revision id. | |
37 | */ | |
38 | #define OCTEON_CN68XX 0x0091 | |
39 | #define OCTEON_CN66XX 0x0092 | |
e86b1ab6 RV |
40 | #define OCTEON_CN23XX_PF_VID 0x9702 |
41 | ||
42 | /**RevisionId for the chips */ | |
43 | #define OCTEON_CN23XX_REV_1_0 0x00 | |
44 | #define OCTEON_CN23XX_REV_1_1 0x01 | |
45 | #define OCTEON_CN23XX_REV_2_0 0x80 | |
f21fb3ed RV |
46 | |
47 | /** Endian-swap modes supported by Octeon. */ | |
48 | enum octeon_pci_swap_mode { | |
49 | OCTEON_PCI_PASSTHROUGH = 0, | |
50 | OCTEON_PCI_64BIT_SWAP = 1, | |
51 | OCTEON_PCI_32BIT_BYTE_SWAP = 2, | |
52 | OCTEON_PCI_32BIT_LW_SWAP = 3 | |
53 | }; | |
54 | ||
55 | /*--------------- PCI BAR1 index registers -------------*/ | |
56 | ||
57 | /* BAR1 Mask */ | |
58 | #define PCI_BAR1_ENABLE_CA 1 | |
59 | #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP | |
60 | #define PCI_BAR1_ENTRY_VALID 1 | |
61 | #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ | |
62 | | (PCI_BAR1_ENDIAN_MODE << 1) \ | |
63 | | PCI_BAR1_ENTRY_VALID) | |
64 | ||
65 | /** Octeon Device state. | |
66 | * Each octeon device goes through each of these states | |
67 | * as it is initialized. | |
68 | */ | |
69 | #define OCT_DEV_BEGIN_STATE 0x0 | |
70 | #define OCT_DEV_PCI_MAP_DONE 0x1 | |
71 | #define OCT_DEV_DISPATCH_INIT_DONE 0x2 | |
72 | #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x3 | |
73 | #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4 | |
74 | #define OCT_DEV_RESP_LIST_INIT_DONE 0x5 | |
75 | #define OCT_DEV_DROQ_INIT_DONE 0x6 | |
76 | #define OCT_DEV_IO_QUEUES_DONE 0x7 | |
77 | #define OCT_DEV_CONSOLE_INIT_DONE 0x8 | |
78 | #define OCT_DEV_HOST_OK 0x9 | |
79 | #define OCT_DEV_CORE_OK 0xa | |
80 | #define OCT_DEV_RUNNING 0xb | |
81 | #define OCT_DEV_IN_RESET 0xc | |
82 | #define OCT_DEV_STATE_INVALID 0xd | |
83 | ||
84 | #define OCT_DEV_STATES OCT_DEV_STATE_INVALID | |
85 | ||
86 | /** Octeon Device interrupts | |
87 | * These interrupt bits are set in int_status filed of | |
88 | * octeon_device structure | |
89 | */ | |
90 | #define OCT_DEV_INTR_DMA0_FORCE 0x01 | |
91 | #define OCT_DEV_INTR_DMA1_FORCE 0x02 | |
92 | #define OCT_DEV_INTR_PKT_DATA 0x04 | |
93 | ||
94 | #define LIO_RESET_SECS (3) | |
95 | ||
96 | /*---------------------------DISPATCH LIST-------------------------------*/ | |
97 | ||
98 | /** The dispatch list entry. | |
99 | * The driver keeps a record of functions registered for each | |
100 | * response header opcode in this structure. Since the opcode is | |
101 | * hashed to index into the driver's list, more than one opcode | |
102 | * can hash to the same entry, in which case the list field points | |
103 | * to a linked list with the other entries. | |
104 | */ | |
105 | struct octeon_dispatch { | |
106 | /** List head for this entry */ | |
107 | struct list_head list; | |
108 | ||
109 | /** The opcode for which the dispatch function & arg should be used */ | |
110 | u16 opcode; | |
111 | ||
112 | /** The function to be called for a packet received by the driver */ | |
113 | octeon_dispatch_fn_t dispatch_fn; | |
114 | ||
115 | /* The application specified argument to be passed to the above | |
116 | * function along with the received packet | |
117 | */ | |
118 | void *arg; | |
119 | }; | |
120 | ||
121 | /** The dispatch list structure. */ | |
122 | struct octeon_dispatch_list { | |
123 | /** access to dispatch list must be atomic */ | |
124 | spinlock_t lock; | |
125 | ||
126 | /** Count of dispatch functions currently registered */ | |
127 | u32 count; | |
128 | ||
129 | /** The list of dispatch functions */ | |
130 | struct octeon_dispatch *dlist; | |
131 | }; | |
132 | ||
133 | /*----------------------- THE OCTEON DEVICE ---------------------------*/ | |
134 | ||
135 | #define OCT_MEM_REGIONS 3 | |
136 | /** PCI address space mapping information. | |
137 | * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of | |
138 | * Octeon gets mapped to different physical address spaces in | |
139 | * the kernel. | |
140 | */ | |
141 | struct octeon_mmio { | |
142 | /** PCI address to which the BAR is mapped. */ | |
143 | u64 start; | |
144 | ||
145 | /** Length of this PCI address space. */ | |
146 | u32 len; | |
147 | ||
148 | /** Length that has been mapped to phys. address space. */ | |
149 | u32 mapped_len; | |
150 | ||
151 | /** The physical address to which the PCI address space is mapped. */ | |
152 | u8 __iomem *hw_addr; | |
153 | ||
154 | /** Flag indicating the mapping was successful. */ | |
155 | u32 done; | |
156 | }; | |
157 | ||
158 | #define MAX_OCTEON_MAPS 32 | |
159 | ||
160 | struct octeon_io_enable { | |
63da8404 RV |
161 | u64 iq; |
162 | u64 oq; | |
163 | u64 iq64B; | |
f21fb3ed RV |
164 | }; |
165 | ||
166 | struct octeon_reg_list { | |
167 | u32 __iomem *pci_win_wr_addr_hi; | |
168 | u32 __iomem *pci_win_wr_addr_lo; | |
169 | u64 __iomem *pci_win_wr_addr; | |
170 | ||
171 | u32 __iomem *pci_win_rd_addr_hi; | |
172 | u32 __iomem *pci_win_rd_addr_lo; | |
173 | u64 __iomem *pci_win_rd_addr; | |
174 | ||
175 | u32 __iomem *pci_win_wr_data_hi; | |
176 | u32 __iomem *pci_win_wr_data_lo; | |
177 | u64 __iomem *pci_win_wr_data; | |
178 | ||
179 | u32 __iomem *pci_win_rd_data_hi; | |
180 | u32 __iomem *pci_win_rd_data_lo; | |
181 | u64 __iomem *pci_win_rd_data; | |
182 | }; | |
183 | ||
184 | #define OCTEON_CONSOLE_MAX_READ_BYTES 512 | |
185 | struct octeon_console { | |
186 | u32 active; | |
187 | u32 waiting; | |
188 | u64 addr; | |
189 | u32 buffer_size; | |
190 | u64 input_base_addr; | |
191 | u64 output_base_addr; | |
192 | char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; | |
193 | }; | |
194 | ||
195 | struct octeon_board_info { | |
196 | char name[OCT_BOARD_NAME]; | |
197 | char serial_number[OCT_SERIAL_LEN]; | |
198 | u64 major; | |
199 | u64 minor; | |
200 | }; | |
201 | ||
202 | struct octeon_fn_list { | |
203 | void (*setup_iq_regs)(struct octeon_device *, u32); | |
204 | void (*setup_oq_regs)(struct octeon_device *, u32); | |
205 | ||
206 | irqreturn_t (*process_interrupt_regs)(void *); | |
207 | int (*soft_reset)(struct octeon_device *); | |
208 | int (*setup_device_regs)(struct octeon_device *); | |
f21fb3ed RV |
209 | void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); |
210 | void (*bar1_idx_write)(struct octeon_device *, u32, u32); | |
211 | u32 (*bar1_idx_read)(struct octeon_device *, u32); | |
9a96bde4 | 212 | u32 (*update_iq_read_idx)(struct octeon_instr_queue *); |
f21fb3ed RV |
213 | |
214 | void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); | |
215 | void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); | |
216 | ||
217 | void (*enable_interrupt)(void *); | |
218 | void (*disable_interrupt)(void *); | |
219 | ||
220 | void (*enable_io_queues)(struct octeon_device *); | |
221 | void (*disable_io_queues)(struct octeon_device *); | |
222 | }; | |
223 | ||
224 | /* Must be multiple of 8, changing breaks ABI */ | |
225 | #define CVMX_BOOTMEM_NAME_LEN 128 | |
226 | ||
227 | /* Structure for named memory blocks | |
228 | * Number of descriptors | |
a2c64b67 | 229 | * available can be changed without affecting compatibility, |
f21fb3ed RV |
230 | * but name length changes require a bump in the bootmem |
231 | * descriptor version | |
232 | * Note: This structure must be naturally 64 bit aligned, as a single | |
233 | * memory image will be used by both 32 and 64 bit programs. | |
234 | */ | |
235 | struct cvmx_bootmem_named_block_desc { | |
236 | /** Base address of named block */ | |
237 | u64 base_addr; | |
238 | ||
239 | /** Size actually allocated for named block */ | |
240 | u64 size; | |
241 | ||
242 | /** name of named block */ | |
243 | char name[CVMX_BOOTMEM_NAME_LEN]; | |
244 | }; | |
245 | ||
246 | struct oct_fw_info { | |
247 | u32 max_nic_ports; /** max nic ports for the device */ | |
248 | u32 num_gmx_ports; /** num gmx ports */ | |
249 | u64 app_cap_flags; /** firmware cap flags */ | |
250 | ||
251 | /** The core application is running in this mode. | |
252 | * See octeon-drv-opcodes.h for values. | |
253 | */ | |
254 | u32 app_mode; | |
255 | char liquidio_firmware_version[32]; | |
256 | }; | |
257 | ||
258 | /* wrappers around work structs */ | |
259 | struct cavium_wk { | |
260 | struct delayed_work work; | |
261 | void *ctxptr; | |
a2c64b67 | 262 | u64 ctxul; |
f21fb3ed RV |
263 | }; |
264 | ||
265 | struct cavium_wq { | |
266 | struct workqueue_struct *wq; | |
267 | struct cavium_wk wk; | |
268 | }; | |
269 | ||
270 | struct octdev_props { | |
271 | /* Each interface in the Octeon device has a network | |
272 | * device pointer (used for OS specific calls). | |
273 | */ | |
9a96bde4 | 274 | int napi_enabled; |
0cece6c5 | 275 | int gmxport; |
f21fb3ed RV |
276 | struct net_device *netdev; |
277 | }; | |
278 | ||
3451b97c RV |
279 | struct octeon_pf_vf_hs_word { |
280 | #ifdef __LITTLE_ENDIAN_BITFIELD | |
281 | /** PKIND value assigned for the DPI interface */ | |
282 | u64 pkind : 8; | |
283 | ||
284 | /** OCTEON core clock multiplier */ | |
285 | u64 core_tics_per_us : 16; | |
286 | ||
287 | /** OCTEON coprocessor clock multiplier */ | |
288 | u64 coproc_tics_per_us : 16; | |
289 | ||
290 | /** app that currently running on OCTEON */ | |
291 | u64 app_mode : 8; | |
292 | ||
293 | /** RESERVED */ | |
294 | u64 reserved : 16; | |
295 | ||
296 | #else | |
297 | ||
298 | /** RESERVED */ | |
299 | u64 reserved : 16; | |
300 | ||
301 | /** app that currently running on OCTEON */ | |
302 | u64 app_mode : 8; | |
303 | ||
304 | /** OCTEON coprocessor clock multiplier */ | |
305 | u64 coproc_tics_per_us : 16; | |
306 | ||
307 | /** OCTEON core clock multiplier */ | |
308 | u64 core_tics_per_us : 16; | |
309 | ||
310 | /** PKIND value assigned for the DPI interface */ | |
311 | u64 pkind : 8; | |
312 | #endif | |
313 | }; | |
314 | ||
e86b1ab6 RV |
315 | struct octeon_sriov_info { |
316 | /* Actual rings left for PF device */ | |
317 | u32 num_pf_rings; | |
318 | ||
319 | /* SRN of PF usable IO queues */ | |
320 | u32 pf_srn; | |
321 | /* total pf rings */ | |
322 | u32 trs; | |
323 | ||
324 | }; | |
325 | ||
f21fb3ed RV |
326 | /** The Octeon device. |
327 | * Each Octeon device has this structure to represent all its | |
328 | * components. | |
329 | */ | |
330 | struct octeon_device { | |
331 | /** Lock for PCI window configuration accesses */ | |
332 | spinlock_t pci_win_lock; | |
333 | ||
334 | /** Lock for memory accesses */ | |
335 | spinlock_t mem_access_lock; | |
336 | ||
337 | /** PCI device pointer */ | |
338 | struct pci_dev *pci_dev; | |
339 | ||
340 | /** Chip specific information. */ | |
341 | void *chip; | |
342 | ||
343 | /** Number of interfaces detected in this octeon device. */ | |
344 | u32 ifcount; | |
345 | ||
346 | struct octdev_props props[MAX_OCTEON_LINKS]; | |
347 | ||
348 | /** Octeon Chip type. */ | |
349 | u16 chip_id; | |
350 | u16 rev_id; | |
e86b1ab6 | 351 | u16 pf_num; |
f21fb3ed RV |
352 | /** This device's id - set by the driver. */ |
353 | u32 octeon_id; | |
354 | ||
355 | /** This device's PCIe port used for traffic. */ | |
356 | u16 pcie_port; | |
357 | ||
358 | u16 flags; | |
359 | #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) | |
360 | #define LIO_FLAG_MSIX_ENABLED (u32)(1 << 2) | |
361 | ||
362 | /** The state of this device */ | |
363 | atomic_t status; | |
364 | ||
365 | /** memory mapped io range */ | |
366 | struct octeon_mmio mmio[OCT_MEM_REGIONS]; | |
367 | ||
368 | struct octeon_reg_list reg_list; | |
369 | ||
370 | struct octeon_fn_list fn_list; | |
371 | ||
372 | struct octeon_board_info boardinfo; | |
373 | ||
374 | u32 num_iqs; | |
375 | ||
376 | /* The pool containing pre allocated buffers used for soft commands */ | |
377 | struct octeon_sc_buffer_pool sc_buf_pool; | |
378 | ||
379 | /** The input instruction queues */ | |
63da8404 RV |
380 | struct octeon_instr_queue *instr_queue |
381 | [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; | |
f21fb3ed RV |
382 | |
383 | /** The doubly-linked list of instruction response */ | |
384 | struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; | |
385 | ||
386 | u32 num_oqs; | |
387 | ||
388 | /** The DROQ output queues */ | |
63da8404 | 389 | struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; |
f21fb3ed RV |
390 | |
391 | struct octeon_io_enable io_qmask; | |
392 | ||
393 | /** List of dispatch functions */ | |
394 | struct octeon_dispatch_list dispatch; | |
395 | ||
396 | /* Interrupt Moderation */ | |
397 | struct oct_intrmod_cfg intrmod; | |
398 | ||
399 | u32 int_status; | |
400 | ||
401 | u64 droq_intr; | |
402 | ||
403 | /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ | |
404 | u64 bootmem_desc_addr; | |
405 | ||
406 | /** Placeholder memory for named blocks. | |
407 | * Assumes single-threaded access | |
408 | */ | |
409 | struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; | |
410 | ||
411 | /** Address of consoles descriptor */ | |
412 | u64 console_desc_addr; | |
413 | ||
414 | /** Number of consoles available. 0 means they are inaccessible */ | |
415 | u32 num_consoles; | |
416 | ||
417 | /* Console caches */ | |
418 | struct octeon_console console[MAX_OCTEON_MAPS]; | |
419 | ||
420 | /* Coprocessor clock rate. */ | |
421 | u64 coproc_clock_rate; | |
422 | ||
423 | /** The core application is running in this mode. See liquidio_common.h | |
424 | * for values. | |
425 | */ | |
426 | u32 app_mode; | |
427 | ||
428 | struct oct_fw_info fw_info; | |
429 | ||
430 | /** The name given to this device. */ | |
431 | char device_name[32]; | |
432 | ||
433 | /** Application Context */ | |
434 | void *app_ctx; | |
435 | ||
436 | struct cavium_wq dma_comp_wq; | |
437 | ||
60441888 RV |
438 | /** Lock for dma response list */ |
439 | spinlock_t cmd_resp_wqlock; | |
440 | u32 cmd_resp_state; | |
441 | ||
63da8404 | 442 | struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; |
f21fb3ed RV |
443 | |
444 | struct cavium_wk nic_poll_work; | |
445 | ||
446 | struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; | |
447 | ||
448 | void *priv; | |
1f164717 | 449 | |
e86b1ab6 RV |
450 | struct octeon_sriov_info sriov_info; |
451 | ||
3451b97c RV |
452 | struct octeon_pf_vf_hs_word pfvf_hsword; |
453 | ||
1f164717 RV |
454 | int rx_pause; |
455 | int tx_pause; | |
456 | ||
457 | struct oct_link_stats link_stats; /*stastics from firmware*/ | |
458 | ||
f5a20472 RV |
459 | /* private flags to control driver-specific features through ethtool */ |
460 | u32 priv_flags; | |
f21fb3ed RV |
461 | }; |
462 | ||
60441888 RV |
463 | #define OCT_DRV_ONLINE 1 |
464 | #define OCT_DRV_OFFLINE 2 | |
f21fb3ed RV |
465 | #define OCTEON_CN6XXX(oct) ((oct->chip_id == OCTEON_CN66XX) || \ |
466 | (oct->chip_id == OCTEON_CN68XX)) | |
e86b1ab6 | 467 | #define OCTEON_CN23XX_PF(oct) (oct->chip_id == OCTEON_CN23XX_PF_VID) |
f21fb3ed RV |
468 | #define CHIP_FIELD(oct, TYPE, field) \ |
469 | (((struct octeon_ ## TYPE *)(oct->chip))->field) | |
470 | ||
471 | struct oct_intrmod_cmd { | |
472 | struct octeon_device *oct_dev; | |
473 | struct octeon_soft_command *sc; | |
474 | struct oct_intrmod_cfg *cfg; | |
475 | }; | |
476 | ||
477 | /*------------------ Function Prototypes ----------------------*/ | |
478 | ||
479 | /** Initialize device list memory */ | |
480 | void octeon_init_device_list(int conf_type); | |
481 | ||
482 | /** Free memory for Input and Output queue structures for a octeon device */ | |
483 | void octeon_free_device_mem(struct octeon_device *); | |
484 | ||
485 | /* Look up a free entry in the octeon_device table and allocate resources | |
486 | * for the octeon_device structure for an octeon device. Called at init | |
487 | * time. | |
488 | */ | |
489 | struct octeon_device *octeon_allocate_device(u32 pci_id, | |
490 | u32 priv_size); | |
491 | ||
492 | /** Initialize the driver's dispatch list which is a mix of a hash table | |
493 | * and a linked list. This is done at driver load time. | |
494 | * @param octeon_dev - pointer to the octeon device structure. | |
495 | * @return 0 on success, else -ve error value | |
496 | */ | |
497 | int octeon_init_dispatch_list(struct octeon_device *octeon_dev); | |
498 | ||
499 | /** Delete the driver's dispatch list and all registered entries. | |
500 | * This is done at driver unload time. | |
501 | * @param octeon_dev - pointer to the octeon device structure. | |
502 | */ | |
503 | void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); | |
504 | ||
505 | /** Initialize the core device fields with the info returned by the FW. | |
506 | * @param recv_info - Receive info structure | |
507 | * @param buf - Receive buffer | |
508 | */ | |
509 | int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); | |
510 | ||
511 | /** Gets the dispatch function registered to receive packets with a | |
512 | * given opcode/subcode. | |
513 | * @param octeon_dev - the octeon device pointer. | |
514 | * @param opcode - the opcode for which the dispatch function | |
515 | * is to checked. | |
516 | * @param subcode - the subcode for which the dispatch function | |
517 | * is to checked. | |
518 | * | |
519 | * @return Success: octeon_dispatch_fn_t (dispatch function pointer) | |
520 | * @return Failure: NULL | |
521 | * | |
522 | * Looks up the dispatch list to get the dispatch function for a | |
523 | * given opcode. | |
524 | */ | |
525 | octeon_dispatch_fn_t | |
526 | octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, | |
527 | u16 subcode); | |
528 | ||
529 | /** Get the octeon device pointer. | |
530 | * @param octeon_id - The id for which the octeon device pointer is required. | |
531 | * @return Success: Octeon device pointer. | |
532 | * @return Failure: NULL. | |
533 | */ | |
534 | struct octeon_device *lio_get_device(u32 octeon_id); | |
535 | ||
536 | /** Get the octeon id assigned to the octeon device passed as argument. | |
537 | * This function is exported to other modules. | |
538 | * @param dev - octeon device pointer passed as a void *. | |
539 | * @return octeon device id | |
540 | */ | |
541 | int lio_get_device_id(void *dev); | |
542 | ||
543 | static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) | |
544 | { | |
545 | u16 rev = (oct->rev_id & 0xC) >> 2; | |
546 | ||
547 | return (rev == 0) ? 1 : rev; | |
548 | } | |
549 | ||
550 | static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) | |
551 | { | |
552 | return oct->rev_id & 0x3; | |
553 | } | |
554 | ||
555 | /** Read windowed register. | |
556 | * @param oct - pointer to the Octeon device. | |
557 | * @param addr - Address of the register to read. | |
558 | * | |
559 | * This routine is called to read from the indirectly accessed | |
560 | * Octeon registers that are visible through a PCI BAR0 mapped window | |
561 | * register. | |
562 | * @return - 64 bit value read from the register. | |
563 | */ | |
564 | ||
565 | u64 lio_pci_readq(struct octeon_device *oct, u64 addr); | |
566 | ||
567 | /** Write windowed register. | |
568 | * @param oct - pointer to the Octeon device. | |
569 | * @param val - Value to write | |
570 | * @param addr - Address of the register to write | |
571 | * | |
572 | * This routine is called to write to the indirectly accessed | |
573 | * Octeon registers that are visible through a PCI BAR0 mapped window | |
574 | * register. | |
575 | * @return Nothing. | |
576 | */ | |
577 | void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); | |
578 | ||
579 | /* Routines for reading and writing CSRs */ | |
580 | #define octeon_write_csr(oct_dev, reg_off, value) \ | |
581 | writel(value, oct_dev->mmio[0].hw_addr + reg_off) | |
582 | ||
583 | #define octeon_write_csr64(oct_dev, reg_off, val64) \ | |
584 | writeq(val64, oct_dev->mmio[0].hw_addr + reg_off) | |
585 | ||
586 | #define octeon_read_csr(oct_dev, reg_off) \ | |
587 | readl(oct_dev->mmio[0].hw_addr + reg_off) | |
588 | ||
589 | #define octeon_read_csr64(oct_dev, reg_off) \ | |
590 | readq(oct_dev->mmio[0].hw_addr + reg_off) | |
591 | ||
592 | /** | |
593 | * Checks if memory access is okay | |
594 | * | |
595 | * @param oct which octeon to send to | |
596 | * @return Zero on success, negative on failure. | |
597 | */ | |
598 | int octeon_mem_access_ok(struct octeon_device *oct); | |
599 | ||
600 | /** | |
601 | * Waits for DDR initialization. | |
602 | * | |
603 | * @param oct which octeon to send to | |
604 | * @param timeout_in_ms pointer to how long to wait until DDR is initialized | |
605 | * in ms. | |
606 | * If contents are 0, it waits until contents are non-zero | |
607 | * before starting to check. | |
608 | * @return Zero on success, negative on failure. | |
609 | */ | |
610 | int octeon_wait_for_ddr_init(struct octeon_device *oct, | |
611 | u32 *timeout_in_ms); | |
612 | ||
613 | /** | |
614 | * Wait for u-boot to boot and be waiting for a command. | |
615 | * | |
616 | * @param wait_time_hundredths | |
617 | * Maximum time to wait | |
618 | * | |
619 | * @return Zero on success, negative on failure. | |
620 | */ | |
621 | int octeon_wait_for_bootloader(struct octeon_device *oct, | |
622 | u32 wait_time_hundredths); | |
623 | ||
624 | /** | |
625 | * Initialize console access | |
626 | * | |
627 | * @param oct which octeon initialize | |
628 | * @return Zero on success, negative on failure. | |
629 | */ | |
630 | int octeon_init_consoles(struct octeon_device *oct); | |
631 | ||
632 | /** | |
633 | * Adds access to a console to the device. | |
634 | * | |
635 | * @param oct which octeon to add to | |
636 | * @param console_num which console | |
637 | * @return Zero on success, negative on failure. | |
638 | */ | |
639 | int octeon_add_console(struct octeon_device *oct, u32 console_num); | |
640 | ||
641 | /** write or read from a console */ | |
642 | int octeon_console_write(struct octeon_device *oct, u32 console_num, | |
643 | char *buffer, u32 write_request_size, u32 flags); | |
644 | int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); | |
a7d5a3dc | 645 | |
f21fb3ed RV |
646 | int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); |
647 | ||
648 | /** Removes all attached consoles. */ | |
649 | void octeon_remove_consoles(struct octeon_device *oct); | |
650 | ||
651 | /** | |
652 | * Send a string to u-boot on console 0 as a command. | |
653 | * | |
654 | * @param oct which octeon to send to | |
655 | * @param cmd_str String to send | |
656 | * @param wait_hundredths Time to wait for u-boot to accept the command. | |
657 | * | |
658 | * @return Zero on success, negative on failure. | |
659 | */ | |
660 | int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, | |
661 | u32 wait_hundredths); | |
662 | ||
663 | /** Parses, validates, and downloads firmware, then boots associated cores. | |
664 | * @param oct which octeon to download firmware to | |
665 | * @param data - The complete firmware file image | |
666 | * @param size - The size of the data | |
667 | * | |
668 | * @return 0 if success. | |
669 | * -EINVAL if file is incompatible or badly formatted. | |
670 | * -ENODEV if no handler was found for the application type or an | |
671 | * invalid octeon id was passed. | |
672 | */ | |
673 | int octeon_download_firmware(struct octeon_device *oct, const u8 *data, | |
674 | size_t size); | |
675 | ||
676 | char *lio_get_state_string(atomic_t *state_ptr); | |
677 | ||
678 | /** Sets up instruction queues for the device | |
679 | * @param oct which octeon to setup | |
680 | * | |
681 | * @return 0 if success. 1 if fails | |
682 | */ | |
683 | int octeon_setup_instr_queues(struct octeon_device *oct); | |
684 | ||
685 | /** Sets up output queues for the device | |
686 | * @param oct which octeon to setup | |
687 | * | |
688 | * @return 0 if success. 1 if fails | |
689 | */ | |
690 | int octeon_setup_output_queues(struct octeon_device *oct); | |
691 | ||
692 | int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); | |
693 | ||
694 | int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); | |
695 | ||
696 | /** Turns off the input and output queues for the device | |
697 | * @param oct which octeon to disable | |
698 | */ | |
699 | void octeon_set_io_queues_off(struct octeon_device *oct); | |
700 | ||
701 | /** Turns on or off the given output queue for the device | |
702 | * @param oct which octeon to change | |
703 | * @param q_no which queue | |
704 | * @param enable 1 to enable, 0 to disable | |
705 | */ | |
706 | void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); | |
707 | ||
708 | /** Retrieve the config for the device | |
709 | * @param oct which octeon | |
710 | * @param card_type type of card | |
711 | * | |
712 | * @returns pointer to configuration | |
713 | */ | |
714 | void *oct_get_config_info(struct octeon_device *oct, u16 card_type); | |
715 | ||
716 | /** Gets the octeon device configuration | |
717 | * @return - pointer to the octeon configuration struture | |
718 | */ | |
719 | struct octeon_config *octeon_get_conf(struct octeon_device *oct); | |
720 | ||
cd8b1eb4 RV |
721 | void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); |
722 | ||
f5a20472 RV |
723 | /* LiquidIO driver pivate flags */ |
724 | enum { | |
725 | OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ | |
726 | }; | |
727 | ||
728 | static inline void lio_set_priv_flag(struct octeon_device *octdev, u32 flag, | |
729 | u32 val) | |
730 | { | |
731 | if (val) | |
732 | octdev->priv_flags |= (0x1 << flag); | |
733 | else | |
734 | octdev->priv_flags &= ~(0x1 << flag); | |
735 | } | |
f21fb3ed | 736 | #endif |