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vxlan: tun_id is 64bit, not 32bit
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
b5a02f50 65#include <net/addrconf.h>
b8ff05a9
DM		 66#include <asm/uaccess.h>
67
68#include "cxgb4.h"
69#include "t4_regs.h"
f612b815 70#include "t4_values.h"
b8ff05a9
DM		 71#include "t4_msg.h"
72#include "t4fw_api.h"
cd6c2f12 73#include "t4fw_version.h"
688848b1 74#include "cxgb4_dcb.h"
fd88b31a 75#include "cxgb4_debugfs.h"
b5a02f50 76#include "clip_tbl.h"
b8ff05a9
DM		 77#include "l2t.h"
78
812034f1
HS		 79char cxgb4_driver_name[] = KBUILD_MODNAME;
80
01bcca68
VP		 81#ifdef DRV_VERSION
82#undef DRV_VERSION
83#endif
3a7f8554 84#define DRV_VERSION "2.0.0-ko"
812034f1 85const char cxgb4_driver_version[] = DRV_VERSION;
52a5f846 86#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
b8ff05a9 87
f2b7e78d
VP		 88/* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
93 */
94struct filter_entry {
95 /* Administrative fields for filter.
96 */
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
99
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
103
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
108 */
109 struct ch_filter_specification fs;
110};
111
b8ff05a9
DM		 112#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
115
3fedeab1
HS		 116/* Macros needed to support the PCI Device ID Table ...
117 */
118#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 119 static const struct pci_device_id cxgb4_pci_tbl[] = {
3fedeab1 120#define CH_PCI_DEVICE_ID_FUNCTION 0x4
b8ff05a9 121
3fedeab1
HS		 122/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
123 * called for both.
124 */
125#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
126
127#define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
129
130#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
131 { 0, } \
132 }
133
134#include "t4_pci_id_tbl.h"
b8ff05a9 135
16e47624 136#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 137#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 138#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 139#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 140#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 141#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 142#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144#define PHY_AQ1202_DEVICEID 0x4409
145#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 146
147MODULE_DESCRIPTION(DRV_DESC);
148MODULE_AUTHOR("Chelsio Communications");
149MODULE_LICENSE("Dual BSD/GPL");
150MODULE_VERSION(DRV_VERSION);
151MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 152MODULE_FIRMWARE(FW4_FNAME);
0a57a536 153MODULE_FIRMWARE(FW5_FNAME);
52a5f846 154MODULE_FIRMWARE(FW6_FNAME);
b8ff05a9 155
636f9d37
VP		 156/*
157 * Normally we're willing to become the firmware's Master PF but will be happy
158 * if another PF has already become the Master and initialized the adapter.
159 * Setting "force_init" will cause this driver to forcibly establish itself as
160 * the Master PF and initialize the adapter.
161 */
162static uint force_init;
163
164module_param(force_init, uint, 0644);
d7d3e25f
HS		 165MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter,"
166 "deprecated parameter");
13ee15d3 167
b8ff05a9
DM		 168static int dflt_msg_enable = DFLT_MSG_ENABLE;
169
170module_param(dflt_msg_enable, int, 0644);
171MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
172
173/*
174 * The driver uses the best interrupt scheme available on a platform in the
175 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
176 * of these schemes the driver may consider as follows:
177 *
178 * msi = 2: choose from among all three options
179 * msi = 1: only consider MSI and INTx interrupts
180 * msi = 0: force INTx interrupts
181 */
182static int msi = 2;
183
184module_param(msi, int, 0644);
185MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
186
636f9d37
VP		 187/*
188 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
189 * offset by 2 bytes in order to have the IP headers line up on 4-byte
190 * boundaries. This is a requirement for many architectures which will throw
191 * a machine check fault if an attempt is made to access one of the 4-byte IP
192 * header fields on a non-4-byte boundary. And it's a major performance issue
193 * even on some architectures which allow it like some implementations of the
194 * x86 ISA. However, some architectures don't mind this and for some very
195 * edge-case performance sensitive applications (like forwarding large volumes
196 * of small packets), setting this DMA offset to 0 will decrease the number of
197 * PCI-E Bus transfers enough to measurably affect performance.
198 */
199static int rx_dma_offset = 2;
200
b8ff05a9 201#ifdef CONFIG_PCI_IOV
7d6727cf
SR		 202/* Configure the number of PCI-E Virtual Function which are to be instantiated
203 * on SR-IOV Capable Physical Functions.
0a57a536 204 */
7d6727cf 205static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 206
207module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 208MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 209#endif
210
688848b1
AB		 211/* TX Queue select used to determine what algorithm to use for selecting TX
212 * queue. Select between the kernel provided function (select_queue=0) or user
213 * cxgb_select_queue function (select_queue=1)
214 *
215 * Default: select_queue=0
216 */
217static int select_queue;
218module_param(select_queue, int, 0644);
219MODULE_PARM_DESC(select_queue,
220 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
221
b8ff05a9
DM		 222static struct dentry *cxgb4_debugfs_root;
223
224static LIST_HEAD(adapter_list);
225static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 226/* Adapter list to be accessed from atomic context */
227static LIST_HEAD(adap_rcu_list);
228static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 229static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
230static const char *uld_str[] = { "RDMA", "iSCSI" };
231
232static void link_report(struct net_device *dev)
233{
234 if (!netif_carrier_ok(dev))
235 netdev_info(dev, "link down\n");
236 else {
237 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
238
85412255 239 const char *s;
b8ff05a9
DM		 240 const struct port_info *p = netdev_priv(dev);
241
242 switch (p->link_cfg.speed) {
e8b39015 243 case 10000:
b8ff05a9
DM		 244 s = "10Gbps";
245 break;
e8b39015 246 case 1000:
b8ff05a9
DM		 247 s = "1000Mbps";
248 break;
e8b39015 249 case 100:
b8ff05a9
DM		 250 s = "100Mbps";
251 break;
e8b39015 252 case 40000:
72aca4bf
KS		 253 s = "40Gbps";
254 break;
85412255
HS		 255 default:
256 pr_info("%s: unsupported speed: %d\n",
257 dev->name, p->link_cfg.speed);
258 return;
b8ff05a9
DM		 259 }
260
261 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
262 fc[p->link_cfg.fc]);
263 }
264}
265
688848b1
AB		 266#ifdef CONFIG_CHELSIO_T4_DCB
267/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
268static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
269{
270 struct port_info *pi = netdev_priv(dev);
271 struct adapter *adap = pi->adapter;
272 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
273 int i;
274
275 /* We use a simple mapping of Port TX Queue Index to DCB
276 * Priority when we're enabling DCB.
277 */
278 for (i = 0; i < pi->nqsets; i++, txq++) {
279 u32 name, value;
280 int err;
281
5167865a
HS		 282 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
283 FW_PARAMS_PARAM_X_V(
284 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
285 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 286 value = enable ? i : 0xffffffff;
287
288 /* Since we can be called while atomic (from "interrupt
289 * level") we need to issue the Set Parameters Commannd
290 * without sleeping (timeout < 0).
291 */
b2612722 292 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 293 &name, &value,
294 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 295
296 if (err)
297 dev_err(adap->pdev_dev,
298 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
299 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 300 else
301 txq->dcb_prio = value;
688848b1
AB		 302 }
303}
304#endif /* CONFIG_CHELSIO_T4_DCB */
305
b8ff05a9
DM		 306void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
307{
308 struct net_device *dev = adapter->port[port_id];
309
310 /* Skip changes from disabled ports. */
311 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
312 if (link_stat)
313 netif_carrier_on(dev);
688848b1
AB		 314 else {
315#ifdef CONFIG_CHELSIO_T4_DCB
316 cxgb4_dcb_state_init(dev);
317 dcb_tx_queue_prio_enable(dev, false);
318#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 319 netif_carrier_off(dev);
688848b1 320 }
b8ff05a9
DM		 321
322 link_report(dev);
323 }
324}
325
326void t4_os_portmod_changed(const struct adapter *adap, int port_id)
327{
328 static const char *mod_str[] = {
a0881cab 329 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 330 };
331
332 const struct net_device *dev = adap->port[port_id];
333 const struct port_info *pi = netdev_priv(dev);
334
335 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
336 netdev_info(dev, "port module unplugged\n");
a0881cab 337 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 338 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
339}
340
341/*
342 * Configure the exact and hash address filters to handle a port's multicast
343 * and secondary unicast MAC addresses.
344 */
345static int set_addr_filters(const struct net_device *dev, bool sleep)
346{
347 u64 mhash = 0;
348 u64 uhash = 0;
349 bool free = true;
350 u16 filt_idx[7];
351 const u8 *addr[7];
352 int ret, naddr = 0;
b8ff05a9
DM		 353 const struct netdev_hw_addr *ha;
354 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 355 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 356 const struct port_info *pi = netdev_priv(dev);
b2612722 357 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 358
359 /* first do the secondary unicast addresses */
360 netdev_for_each_uc_addr(ha, dev) {
361 addr[naddr++] = ha->addr;
362 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 363 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 364 naddr, addr, filt_idx, &uhash, sleep);
365 if (ret < 0)
366 return ret;
367
368 free = false;
369 naddr = 0;
370 }
371 }
372
373 /* next set up the multicast addresses */
4a35ecf8
DM		 374 netdev_for_each_mc_addr(ha, dev) {
375 addr[naddr++] = ha->addr;
376 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 377 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 378 naddr, addr, filt_idx, &mhash, sleep);
379 if (ret < 0)
380 return ret;
381
382 free = false;
383 naddr = 0;
384 }
385 }
386
060e0c75 387 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 388 uhash | mhash, sleep);
389}
390
3069ee9b
VP		 391int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
392module_param(dbfifo_int_thresh, int, 0644);
393MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
394
404d9e3f
VP		 395/*
396 * usecs to sleep while draining the dbfifo
397 */
398static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 399module_param(dbfifo_drain_delay, int, 0644);
400MODULE_PARM_DESC(dbfifo_drain_delay,
401 "usecs to sleep while draining the dbfifo");
402
b8ff05a9
DM		 403/*
404 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
405 * If @mtu is -1 it is left unchanged.
406 */
407static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
408{
409 int ret;
410 struct port_info *pi = netdev_priv(dev);
411
412 ret = set_addr_filters(dev, sleep_ok);
413 if (ret == 0)
b2612722 414 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
b8ff05a9 415 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 416 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 417 sleep_ok);
418 return ret;
419}
420
421/**
422 * link_start - enable a port
423 * @dev: the port to enable
424 *
425 * Performs the MAC and PHY actions needed to enable a port.
426 */
427static int link_start(struct net_device *dev)
428{
429 int ret;
430 struct port_info *pi = netdev_priv(dev);
b2612722 431 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 432
433 /*
434 * We do not set address filters and promiscuity here, the stack does
435 * that step explicitly.
436 */
060e0c75 437 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 438 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 439 if (ret == 0) {
060e0c75 440 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 441 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 442 true);
b8ff05a9
DM		 443 if (ret >= 0) {
444 pi->xact_addr_filt = ret;
445 ret = 0;
446 }
447 }
448 if (ret == 0)
4036da90 449 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 450 &pi->link_cfg);
30f00847
AB		 451 if (ret == 0) {
452 local_bh_disable();
688848b1
AB		 453 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
454 true, CXGB4_DCB_ENABLED);
30f00847
AB		 455 local_bh_enable();
456 }
688848b1 457
b8ff05a9
DM		 458 return ret;
459}
460
688848b1
AB		 461int cxgb4_dcb_enabled(const struct net_device *dev)
462{
463#ifdef CONFIG_CHELSIO_T4_DCB
464 struct port_info *pi = netdev_priv(dev);
465
3bb06261
AB		 466 if (!pi->dcb.enabled)
467 return 0;
468
469 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
470 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
688848b1
AB		 471#else
472 return 0;
473#endif
474}
475EXPORT_SYMBOL(cxgb4_dcb_enabled);
476
477#ifdef CONFIG_CHELSIO_T4_DCB
478/* Handle a Data Center Bridging update message from the firmware. */
479static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
480{
2b5fb1f2 481 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
688848b1
AB		 482 struct net_device *dev = adap->port[port];
483 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
484 int new_dcb_enabled;
485
486 cxgb4_dcb_handle_fw_update(adap, pcmd);
487 new_dcb_enabled = cxgb4_dcb_enabled(dev);
488
489 /* If the DCB has become enabled or disabled on the port then we're
490 * going to need to set up/tear down DCB Priority parameters for the
491 * TX Queues associated with the port.
492 */
493 if (new_dcb_enabled != old_dcb_enabled)
494 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
495}
496#endif /* CONFIG_CHELSIO_T4_DCB */
497
f2b7e78d
VP		 498/* Clear a filter and release any of its resources that we own. This also
499 * clears the filter's "pending" status.
500 */
501static void clear_filter(struct adapter *adap, struct filter_entry *f)
502{
503 /* If the new or old filter have loopback rewriteing rules then we'll
504 * need to free any existing Layer Two Table (L2T) entries of the old
505 * filter rule. The firmware will handle freeing up any Source MAC
506 * Table (SMT) entries used for rewriting Source MAC Addresses in
507 * loopback rules.
508 */
509 if (f->l2t)
510 cxgb4_l2t_release(f->l2t);
511
512 /* The zeroing of the filter rule below clears the filter valid,
513 * pending, locked flags, l2t pointer, etc. so it's all we need for
514 * this operation.
515 */
516 memset(f, 0, sizeof(*f));
517}
518
519/* Handle a filter write/deletion reply.
520 */
521static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
522{
523 unsigned int idx = GET_TID(rpl);
524 unsigned int nidx = idx - adap->tids.ftid_base;
525 unsigned int ret;
526 struct filter_entry *f;
527
528 if (idx >= adap->tids.ftid_base && nidx <
529 (adap->tids.nftids + adap->tids.nsftids)) {
530 idx = nidx;
bdc590b9 531 ret = TCB_COOKIE_G(rpl->cookie);
f2b7e78d
VP		 532 f = &adap->tids.ftid_tab[idx];
533
534 if (ret == FW_FILTER_WR_FLT_DELETED) {
535 /* Clear the filter when we get confirmation from the
536 * hardware that the filter has been deleted.
537 */
538 clear_filter(adap, f);
539 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
540 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
541 idx);
542 clear_filter(adap, f);
543 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
544 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
545 f->pending = 0; /* asynchronous setup completed */
546 f->valid = 1;
547 } else {
548 /* Something went wrong. Issue a warning about the
549 * problem and clear everything out.
550 */
551 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
552 idx, ret);
553 clear_filter(adap, f);
554 }
555 }
556}
557
558/* Response queue handler for the FW event queue.
b8ff05a9
DM		 559 */
560static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
561 const struct pkt_gl *gl)
562{
563 u8 opcode = ((const struct rss_header *)rsp)->opcode;
564
565 rsp++; /* skip RSS header */
b407a4a9
VP		 566
567 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
568 */
569 if (unlikely(opcode == CPL_FW4_MSG &&
570 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
571 rsp++;
572 opcode = ((const struct rss_header *)rsp)->opcode;
573 rsp++;
574 if (opcode != CPL_SGE_EGR_UPDATE) {
575 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
576 , opcode);
577 goto out;
578 }
579 }
580
b8ff05a9
DM		 581 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
582 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 583 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 584 struct sge_txq *txq;
b8ff05a9 585
e46dab4d 586 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 587 txq->restarts++;
e46dab4d 588 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 589 struct sge_eth_txq *eq;
590
591 eq = container_of(txq, struct sge_eth_txq, q);
592 netif_tx_wake_queue(eq->txq);
593 } else {
594 struct sge_ofld_txq *oq;
595
596 oq = container_of(txq, struct sge_ofld_txq, q);
597 tasklet_schedule(&oq->qresume_tsk);
598 }
599 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
600 const struct cpl_fw6_msg *p = (void *)rsp;
601
688848b1
AB		 602#ifdef CONFIG_CHELSIO_T4_DCB
603 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 604 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 605 unsigned int action =
2b5fb1f2 606 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 607
608 if (cmd == FW_PORT_CMD &&
609 action == FW_PORT_ACTION_GET_PORT_INFO) {
2b5fb1f2 610 int port = FW_PORT_CMD_PORTID_G(
688848b1
AB		 611 be32_to_cpu(pcmd->op_to_portid));
612 struct net_device *dev = q->adap->port[port];
613 int state_input = ((pcmd->u.info.dcbxdis_pkd &
2b5fb1f2 614 FW_PORT_CMD_DCBXDIS_F)
688848b1
AB		 615 ? CXGB4_DCB_INPUT_FW_DISABLED
616 : CXGB4_DCB_INPUT_FW_ENABLED);
617
618 cxgb4_dcb_state_fsm(dev, state_input);
619 }
620
621 if (cmd == FW_PORT_CMD &&
622 action == FW_PORT_ACTION_L2_DCB_CFG)
623 dcb_rpl(q->adap, pcmd);
624 else
625#endif
626 if (p->type == 0)
627 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 628 } else if (opcode == CPL_L2T_WRITE_RPL) {
629 const struct cpl_l2t_write_rpl *p = (void *)rsp;
630
631 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 632 } else if (opcode == CPL_SET_TCB_RPL) {
633 const struct cpl_set_tcb_rpl *p = (void *)rsp;
634
635 filter_rpl(q->adap, p);
b8ff05a9
DM		 636 } else
637 dev_err(q->adap->pdev_dev,
638 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 639out:
b8ff05a9
DM		 640 return 0;
641}
642
643/**
644 * uldrx_handler - response queue handler for ULD queues
645 * @q: the response queue that received the packet
646 * @rsp: the response queue descriptor holding the offload message
647 * @gl: the gather list of packet fragments
648 *
649 * Deliver an ingress offload packet to a ULD. All processing is done by
650 * the ULD, we just maintain statistics.
651 */
652static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
653 const struct pkt_gl *gl)
654{
655 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
656
b407a4a9
VP		 657 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
658 */
659 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
660 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
661 rsp += 2;
662
b8ff05a9
DM		 663 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
664 rxq->stats.nomem++;
665 return -1;
666 }
667 if (gl == NULL)
668 rxq->stats.imm++;
669 else if (gl == CXGB4_MSG_AN)
670 rxq->stats.an++;
671 else
672 rxq->stats.pkts++;
673 return 0;
674}
675
676static void disable_msi(struct adapter *adapter)
677{
678 if (adapter->flags & USING_MSIX) {
679 pci_disable_msix(adapter->pdev);
680 adapter->flags &= ~USING_MSIX;
681 } else if (adapter->flags & USING_MSI) {
682 pci_disable_msi(adapter->pdev);
683 adapter->flags &= ~USING_MSI;
684 }
685}
686
687/*
688 * Interrupt handler for non-data events used with MSI-X.
689 */
690static irqreturn_t t4_nondata_intr(int irq, void *cookie)
691{
692 struct adapter *adap = cookie;
0d804338 693 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 694
0d804338 695 if (v & PFSW_F) {
b8ff05a9 696 adap->swintr = 1;
0d804338 697 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 698 }
c3c7b121
HS		 699 if (adap->flags & MASTER_PF)
700 t4_slow_intr_handler(adap);
b8ff05a9
DM		 701 return IRQ_HANDLED;
702}
703
704/*
705 * Name the MSI-X interrupts.
706 */
707static void name_msix_vecs(struct adapter *adap)
708{
ba27816c 709 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 710
711 /* non-data interrupts */
b1a3c2b6 712 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 713
714 /* FW events */
b1a3c2b6
DM		 715 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
716 adap->port[0]->name);
b8ff05a9
DM		 717
718 /* Ethernet queues */
719 for_each_port(adap, j) {
720 struct net_device *d = adap->port[j];
721 const struct port_info *pi = netdev_priv(d);
722
ba27816c 723 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 724 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
725 d->name, i);
b8ff05a9
DM		 726 }
727
728 /* offload queues */
f90ce561
HS		 729 for_each_iscsirxq(&adap->sge, i)
730 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d",
b1a3c2b6 731 adap->port[0]->name, i);
ba27816c
DM		 732
733 for_each_rdmarxq(&adap->sge, i)
734 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 735 adap->port[0]->name, i);
cf38be6d
HS		 736
737 for_each_rdmaciq(&adap->sge, i)
738 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
739 adap->port[0]->name, i);
b8ff05a9
DM		 740}
741
742static int request_msix_queue_irqs(struct adapter *adap)
743{
744 struct sge *s = &adap->sge;
f90ce561 745 int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
cf38be6d 746 int msi_index = 2;
b8ff05a9
DM		 747
748 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
749 adap->msix_info[1].desc, &s->fw_evtq);
750 if (err)
751 return err;
752
753 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 754 err = request_irq(adap->msix_info[msi_index].vec,
755 t4_sge_intr_msix, 0,
756 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 757 &s->ethrxq[ethqidx].rspq);
758 if (err)
759 goto unwind;
404d9e3f 760 msi_index++;
b8ff05a9 761 }
f90ce561 762 for_each_iscsirxq(s, iscsiqidx) {
404d9e3f
VP		 763 err = request_irq(adap->msix_info[msi_index].vec,
764 t4_sge_intr_msix, 0,
765 adap->msix_info[msi_index].desc,
f90ce561 766 &s->iscsirxq[iscsiqidx].rspq);
b8ff05a9
DM		 767 if (err)
768 goto unwind;
404d9e3f 769 msi_index++;
b8ff05a9
DM		 770 }
771 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 772 err = request_irq(adap->msix_info[msi_index].vec,
773 t4_sge_intr_msix, 0,
774 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 775 &s->rdmarxq[rdmaqidx].rspq);
776 if (err)
777 goto unwind;
404d9e3f 778 msi_index++;
b8ff05a9 779 }
cf38be6d
HS		 780 for_each_rdmaciq(s, rdmaciqqidx) {
781 err = request_irq(adap->msix_info[msi_index].vec,
782 t4_sge_intr_msix, 0,
783 adap->msix_info[msi_index].desc,
784 &s->rdmaciq[rdmaciqqidx].rspq);
785 if (err)
786 goto unwind;
787 msi_index++;
788 }
b8ff05a9
DM		 789 return 0;
790
791unwind:
cf38be6d
HS		 792 while (--rdmaciqqidx >= 0)
793 free_irq(adap->msix_info[--msi_index].vec,
794 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 795 while (--rdmaqidx >= 0)
404d9e3f 796 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9 797 &s->rdmarxq[rdmaqidx].rspq);
f90ce561 798 while (--iscsiqidx >= 0)
404d9e3f 799 free_irq(adap->msix_info[--msi_index].vec,
f90ce561 800 &s->iscsirxq[iscsiqidx].rspq);
b8ff05a9 801 while (--ethqidx >= 0)
404d9e3f
VP		 802 free_irq(adap->msix_info[--msi_index].vec,
803 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 804 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
805 return err;
806}
807
808static void free_msix_queue_irqs(struct adapter *adap)
809{
404d9e3f 810 int i, msi_index = 2;
b8ff05a9
DM		 811 struct sge *s = &adap->sge;
812
813 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
814 for_each_ethrxq(s, i)
404d9e3f 815 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
f90ce561
HS		 816 for_each_iscsirxq(s, i)
817 free_irq(adap->msix_info[msi_index++].vec,
818 &s->iscsirxq[i].rspq);
b8ff05a9 819 for_each_rdmarxq(s, i)
404d9e3f 820 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 821 for_each_rdmaciq(s, i)
822 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 823}
824
671b0060 825/**
812034f1 826 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 827 * @pi: the port
828 * @queues: array of queue indices for RSS
829 *
830 * Sets up the portion of the HW RSS table for the port's VI to distribute
831 * packets to the Rx queues in @queues.
c035e183 832 * Should never be called before setting up sge eth rx queues
671b0060 833 */
812034f1 834int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 835{
836 u16 *rss;
837 int i, err;
c035e183
HS		 838 struct adapter *adapter = pi->adapter;
839 const struct sge_eth_rxq *rxq;
671b0060 840
c035e183 841 rxq = &adapter->sge.ethrxq[pi->first_qset];
671b0060
DM		 842 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
843 if (!rss)
844 return -ENOMEM;
845
846 /* map the queue indices to queue ids */
847 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 848 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 849
b2612722 850 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 851 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 852 /* If Tunnel All Lookup isn't specified in the global RSS
853 * Configuration, then we need to specify a default Ingress
854 * Queue for any ingress packets which aren't hashed. We'll
855 * use our first ingress queue ...
856 */
857 if (!err)
858 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
859 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
860 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
861 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
862 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
863 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
864 rss[0]);
671b0060
DM		 865 kfree(rss);
866 return err;
867}
868
b8ff05a9
DM		 869/**
870 * setup_rss - configure RSS
871 * @adap: the adapter
872 *
671b0060 873 * Sets up RSS for each port.
b8ff05a9
DM		 874 */
875static int setup_rss(struct adapter *adap)
876{
c035e183 877 int i, j, err;
b8ff05a9
DM		 878
879 for_each_port(adap, i) {
880 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 881
c035e183
HS		 882 /* Fill default values with equal distribution */
883 for (j = 0; j < pi->rss_size; j++)
884 pi->rss[j] = j % pi->nqsets;
885
812034f1 886 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 887 if (err)
888 return err;
889 }
890 return 0;
891}
892
e46dab4d
DM		 893/*
894 * Return the channel of the ingress queue with the given qid.
895 */
896static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
897{
898 qid -= p->ingr_start;
899 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
900}
901
b8ff05a9
DM		 902/*
903 * Wait until all NAPI handlers are descheduled.
904 */
905static void quiesce_rx(struct adapter *adap)
906{
907 int i;
908
4b8e27a8 909 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 910 struct sge_rspq *q = adap->sge.ingr_map[i];
911
3a336cb1 912 if (q && q->handler) {
b8ff05a9 913 napi_disable(&q->napi);
3a336cb1
HS		 914 local_bh_disable();
915 while (!cxgb_poll_lock_napi(q))
916 mdelay(1);
917 local_bh_enable();
918 }
919
b8ff05a9
DM		 920 }
921}
922
b37987e8
HS		 923/* Disable interrupt and napi handler */
924static void disable_interrupts(struct adapter *adap)
925{
926 if (adap->flags & FULL_INIT_DONE) {
927 t4_intr_disable(adap);
928 if (adap->flags & USING_MSIX) {
929 free_msix_queue_irqs(adap);
930 free_irq(adap->msix_info[0].vec, adap);
931 } else {
932 free_irq(adap->pdev->irq, adap);
933 }
934 quiesce_rx(adap);
935 }
936}
937
b8ff05a9
DM		 938/*
939 * Enable NAPI scheduling and interrupt generation for all Rx queues.
940 */
941static void enable_rx(struct adapter *adap)
942{
943 int i;
944
4b8e27a8 945 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 946 struct sge_rspq *q = adap->sge.ingr_map[i];
947
948 if (!q)
949 continue;
3a336cb1
HS		 950 if (q->handler) {
951 cxgb_busy_poll_init_lock(q);
b8ff05a9 952 napi_enable(&q->napi);
3a336cb1 953 }
b8ff05a9 954 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 955 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
956 SEINTARM_V(q->intr_params) |
957 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 958 }
959}
960
1c6a5b0e
HS		 961static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
962 unsigned int nq, unsigned int per_chan, int msi_idx,
963 u16 *ids)
964{
965 int i, err;
966
967 for (i = 0; i < nq; i++, q++) {
968 if (msi_idx > 0)
969 msi_idx++;
970 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
971 adap->port[i / per_chan],
972 msi_idx, q->fl.size ? &q->fl : NULL,
145ef8a5 973 uldrx_handler, 0);
1c6a5b0e
HS		 974 if (err)
975 return err;
976 memset(&q->stats, 0, sizeof(q->stats));
977 if (ids)
978 ids[i] = q->rspq.abs_id;
979 }
980 return 0;
981}
982
b8ff05a9
DM		 983/**
984 * setup_sge_queues - configure SGE Tx/Rx/response queues
985 * @adap: the adapter
986 *
987 * Determines how many sets of SGE queues to use and initializes them.
988 * We support multiple queue sets per port if we have MSI-X, otherwise
989 * just one queue set per port.
990 */
991static int setup_sge_queues(struct adapter *adap)
992{
993 int err, msi_idx, i, j;
994 struct sge *s = &adap->sge;
995
4b8e27a8
HS		 996 bitmap_zero(s->starving_fl, s->egr_sz);
997 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 998
999 if (adap->flags & USING_MSIX)
1000 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1001 else {
1002 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
145ef8a5 1003 NULL, NULL, -1);
b8ff05a9
DM		 1004 if (err)
1005 return err;
1006 msi_idx = -((int)s->intrq.abs_id + 1);
1007 }
1008
4b8e27a8
HS		 1009 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1010 * don't forget to update the following which need to be
1011 * synchronized to and changes here.
1012 *
1013 * 1. The calculations of MAX_INGQ in cxgb4.h.
1014 *
1015 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1016 * to accommodate any new/deleted Ingress Queues
1017 * which need MSI-X Vectors.
1018 *
1019 * 3. Update sge_qinfo_show() to include information on the
1020 * new/deleted queues.
1021 */
b8ff05a9 1022 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
145ef8a5 1023 msi_idx, NULL, fwevtq_handler, -1);
b8ff05a9
DM		 1024 if (err) {
1025freeout: t4_free_sge_resources(adap);
1026 return err;
1027 }
1028
1029 for_each_port(adap, i) {
1030 struct net_device *dev = adap->port[i];
1031 struct port_info *pi = netdev_priv(dev);
1032 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1033 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1034
1035 for (j = 0; j < pi->nqsets; j++, q++) {
1036 if (msi_idx > 0)
1037 msi_idx++;
1038 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1039 msi_idx, &q->fl,
145ef8a5
HS		 1040 t4_ethrx_handler,
1041 t4_get_mps_bg_map(adap,
1042 pi->tx_chan));
b8ff05a9
DM		 1043 if (err)
1044 goto freeout;
1045 q->rspq.idx = j;
1046 memset(&q->stats, 0, sizeof(q->stats));
1047 }
1048 for (j = 0; j < pi->nqsets; j++, t++) {
1049 err = t4_sge_alloc_eth_txq(adap, t, dev,
1050 netdev_get_tx_queue(dev, j),
1051 s->fw_evtq.cntxt_id);
1052 if (err)
1053 goto freeout;
1054 }
1055 }
1056
f90ce561
HS		 1057 j = s->iscsiqsets / adap->params.nports; /* iscsi queues per channel */
1058 for_each_iscsirxq(s, i) {
1c6a5b0e
HS		 1059 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1060 adap->port[i / j],
b8ff05a9
DM		 1061 s->fw_evtq.cntxt_id);
1062 if (err)
1063 goto freeout;
1064 }
1065
1c6a5b0e
HS		 1066#define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1067 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1068 if (err) \
1069 goto freeout; \
1070 if (msi_idx > 0) \
1071 msi_idx += nq; \
1072} while (0)
b8ff05a9 1073
f90ce561 1074 ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq);
1c6a5b0e 1075 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
f36e58e5
HS		 1076 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1077 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
b8ff05a9 1078
1c6a5b0e 1079#undef ALLOC_OFLD_RXQS
cf38be6d 1080
b8ff05a9
DM		 1081 for_each_port(adap, i) {
1082 /*
1083 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1084 * have RDMA queues, and that's the right value.
1085 */
1086 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1087 s->fw_evtq.cntxt_id,
1088 s->rdmarxq[i].rspq.cntxt_id);
1089 if (err)
1090 goto freeout;
1091 }
1092
9bb59b96 1093 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 1094 MPS_TRC_RSS_CONTROL_A :
1095 MPS_T5_TRC_RSS_CONTROL_A,
1096 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1097 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9
DM		 1098 return 0;
1099}
1100
b8ff05a9
DM		 1101/*
1102 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1103 * The allocated memory is cleared.
1104 */
1105void *t4_alloc_mem(size_t size)
1106{
8be04b93 1107 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1108
1109 if (!p)
89bf67f1 1110 p = vzalloc(size);
b8ff05a9
DM		 1111 return p;
1112}
1113
1114/*
1115 * Free memory allocated through alloc_mem().
1116 */
fd88b31a 1117void t4_free_mem(void *addr)
b8ff05a9 1118{
d2fcb548 1119 kvfree(addr);
b8ff05a9
DM		 1120}
1121
f2b7e78d
VP		 1122/* Send a Work Request to write the filter at a specified index. We construct
1123 * a Firmware Filter Work Request to have the work done and put the indicated
1124 * filter into "pending" mode which will prevent any further actions against
1125 * it till we get a reply from the firmware on the completion status of the
1126 * request.
1127 */
1128static int set_filter_wr(struct adapter *adapter, int fidx)
1129{
1130 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1131 struct sk_buff *skb;
1132 struct fw_filter_wr *fwr;
1133 unsigned int ftid;
1134
f72f116a
MH		 1135 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1136 if (!skb)
1137 return -ENOMEM;
1138
f2b7e78d
VP		 1139 /* If the new filter requires loopback Destination MAC and/or VLAN
1140 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1141 * the filter.
1142 */
1143 if (f->fs.newdmac || f->fs.newvlan) {
1144 /* allocate L2T entry for new filter */
f7502659
HS		 1145 f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan,
1146 f->fs.eport, f->fs.dmac);
f72f116a 1147 if (f->l2t == NULL) {
f72f116a 1148 kfree_skb(skb);
f2b7e78d
VP		 1149 return -ENOMEM;
1150 }
1151 }
1152
1153 ftid = adapter->tids.ftid_base + fidx;
1154
f2b7e78d
VP		 1155 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1156 memset(fwr, 0, sizeof(*fwr));
1157
1158 /* It would be nice to put most of the following in t4_hw.c but most
1159 * of the work is translating the cxgbtool ch_filter_specification
1160 * into the Work Request and the definition of that structure is
1161 * currently in cxgbtool.h which isn't appropriate to pull into the
1162 * common code. We may eventually try to come up with a more neutral
1163 * filter specification structure but for now it's easiest to simply
1164 * put this fairly direct code in line ...
1165 */
e2ac9628
HS		 1166 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1167 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
f2b7e78d 1168 fwr->tid_to_iq =
77a80e23
HS		 1169 htonl(FW_FILTER_WR_TID_V(ftid) |
1170 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1171 FW_FILTER_WR_NOREPLY_V(0) |
1172 FW_FILTER_WR_IQ_V(f->fs.iq));
f2b7e78d 1173 fwr->del_filter_to_l2tix =
77a80e23
HS		 1174 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1175 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1176 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1177 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1178 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1179 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1180 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1181 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1182 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f2b7e78d 1183 f->fs.newvlan == VLAN_REWRITE) |
77a80e23 1184 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
f2b7e78d 1185 f->fs.newvlan == VLAN_REWRITE) |
77a80e23
HS		 1186 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1187 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1188 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1189 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
f2b7e78d
VP		 1190 fwr->ethtype = htons(f->fs.val.ethtype);
1191 fwr->ethtypem = htons(f->fs.mask.ethtype);
1192 fwr->frag_to_ovlan_vldm =
77a80e23
HS		 1193 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1194 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1195 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1196 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1197 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1198 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
f2b7e78d
VP		 1199 fwr->smac_sel = 0;
1200 fwr->rx_chan_rx_rpl_iq =
77a80e23
HS		 1201 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1202 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
f2b7e78d 1203 fwr->maci_to_matchtypem =
77a80e23
HS		 1204 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1205 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1206 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1207 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1208 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1209 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1210 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1211 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
f2b7e78d
VP		 1212 fwr->ptcl = f->fs.val.proto;
1213 fwr->ptclm = f->fs.mask.proto;
1214 fwr->ttyp = f->fs.val.tos;
1215 fwr->ttypm = f->fs.mask.tos;
1216 fwr->ivlan = htons(f->fs.val.ivlan);
1217 fwr->ivlanm = htons(f->fs.mask.ivlan);
1218 fwr->ovlan = htons(f->fs.val.ovlan);
1219 fwr->ovlanm = htons(f->fs.mask.ovlan);
1220 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1221 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1222 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1223 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1224 fwr->lp = htons(f->fs.val.lport);
1225 fwr->lpm = htons(f->fs.mask.lport);
1226 fwr->fp = htons(f->fs.val.fport);
1227 fwr->fpm = htons(f->fs.mask.fport);
1228 if (f->fs.newsmac)
1229 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1230
1231 /* Mark the filter as "pending" and ship off the Filter Work Request.
1232 * When we get the Work Request Reply we'll clear the pending status.
1233 */
1234 f->pending = 1;
1235 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1236 t4_ofld_send(adapter, skb);
1237 return 0;
1238}
1239
1240/* Delete the filter at a specified index.
1241 */
1242static int del_filter_wr(struct adapter *adapter, int fidx)
1243{
1244 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1245 struct sk_buff *skb;
1246 struct fw_filter_wr *fwr;
1247 unsigned int len, ftid;
1248
1249 len = sizeof(*fwr);
1250 ftid = adapter->tids.ftid_base + fidx;
1251
f72f116a
MH		 1252 skb = alloc_skb(len, GFP_KERNEL);
1253 if (!skb)
1254 return -ENOMEM;
1255
f2b7e78d
VP		 1256 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1257 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1258
1259 /* Mark the filter as "pending" and ship off the Filter Work Request.
1260 * When we get the Work Request Reply we'll clear the pending status.
1261 */
1262 f->pending = 1;
1263 t4_mgmt_tx(adapter, skb);
1264 return 0;
1265}
1266
688848b1
AB		 1267static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1268 void *accel_priv, select_queue_fallback_t fallback)
1269{
1270 int txq;
1271
1272#ifdef CONFIG_CHELSIO_T4_DCB
1273 /* If a Data Center Bridging has been successfully negotiated on this
1274 * link then we'll use the skb's priority to map it to a TX Queue.
1275 * The skb's priority is determined via the VLAN Tag Priority Code
1276 * Point field.
1277 */
1278 if (cxgb4_dcb_enabled(dev)) {
1279 u16 vlan_tci;
1280 int err;
1281
1282 err = vlan_get_tag(skb, &vlan_tci);
1283 if (unlikely(err)) {
1284 if (net_ratelimit())
1285 netdev_warn(dev,
1286 "TX Packet without VLAN Tag on DCB Link\n");
1287 txq = 0;
1288 } else {
1289 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 1290#ifdef CONFIG_CHELSIO_T4_FCOE
1291 if (skb->protocol == htons(ETH_P_FCOE))
1292 txq = skb->priority & 0x7;
1293#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 1294 }
1295 return txq;
1296 }
1297#endif /* CONFIG_CHELSIO_T4_DCB */
1298
1299 if (select_queue) {
1300 txq = (skb_rx_queue_recorded(skb)
1301 ? skb_get_rx_queue(skb)
1302 : smp_processor_id());
1303
1304 while (unlikely(txq >= dev->real_num_tx_queues))
1305 txq -= dev->real_num_tx_queues;
1306
1307 return txq;
1308 }
1309
1310 return fallback(dev, skb) % dev->real_num_tx_queues;
1311}
1312
b8ff05a9
DM		 1313static int closest_timer(const struct sge *s, int time)
1314{
1315 int i, delta, match = 0, min_delta = INT_MAX;
1316
1317 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1318 delta = time - s->timer_val[i];
1319 if (delta < 0)
1320 delta = -delta;
1321 if (delta < min_delta) {
1322 min_delta = delta;
1323 match = i;
1324 }
1325 }
1326 return match;
1327}
1328
1329static int closest_thres(const struct sge *s, int thres)
1330{
1331 int i, delta, match = 0, min_delta = INT_MAX;
1332
1333 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1334 delta = thres - s->counter_val[i];
1335 if (delta < 0)
1336 delta = -delta;
1337 if (delta < min_delta) {
1338 min_delta = delta;
1339 match = i;
1340 }
1341 }
1342 return match;
1343}
1344
b8ff05a9 1345/**
812034f1 1346 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1347 * @q: the Rx queue
1348 * @us: the hold-off time in us, or 0 to disable timer
1349 * @cnt: the hold-off packet count, or 0 to disable counter
1350 *
1351 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1352 * one of the two needs to be enabled for the queue to generate interrupts.
1353 */
812034f1
HS		 1354int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1355 unsigned int us, unsigned int cnt)
b8ff05a9 1356{
c887ad0e
HS		 1357 struct adapter *adap = q->adap;
1358
b8ff05a9
DM		 1359 if ((us | cnt) == 0)
1360 cnt = 1;
1361
1362 if (cnt) {
1363 int err;
1364 u32 v, new_idx;
1365
1366 new_idx = closest_thres(&adap->sge, cnt);
1367 if (q->desc && q->pktcnt_idx != new_idx) {
1368 /* the queue has already been created, update it */
5167865a
HS		 1369 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1370 FW_PARAMS_PARAM_X_V(
1371 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1372 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1373 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1374 &v, &new_idx);
b8ff05a9
DM		 1375 if (err)
1376 return err;
1377 }
1378 q->pktcnt_idx = new_idx;
1379 }
1380
1381 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1382 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1383 return 0;
1384}
1385
c8f44aff 1386static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1387{
2ed28baa 1388 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1389 netdev_features_t changed = dev->features ^ features;
19ecae2c 1390 int err;
19ecae2c 1391
f646968f 1392 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1393 return 0;
19ecae2c 1394
b2612722 1395 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1396 -1, -1, -1,
f646968f 1397 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1398 if (unlikely(err))
f646968f 1399 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1400 return err;
87b6cf51
DM		 1401}
1402
91744948 1403static int setup_debugfs(struct adapter *adap)
b8ff05a9 1404{
b8ff05a9
DM		 1405 if (IS_ERR_OR_NULL(adap->debugfs_root))
1406 return -1;
1407
fd88b31a
HS		 1408#ifdef CONFIG_DEBUG_FS
1409 t4_setup_debugfs(adap);
1410#endif
b8ff05a9
DM		 1411 return 0;
1412}
1413
1414/*
1415 * upper-layer driver support
1416 */
1417
1418/*
1419 * Allocate an active-open TID and set it to the supplied value.
1420 */
1421int cxgb4_alloc_atid(struct tid_info *t, void *data)
1422{
1423 int atid = -1;
1424
1425 spin_lock_bh(&t->atid_lock);
1426 if (t->afree) {
1427 union aopen_entry *p = t->afree;
1428
f2b7e78d 1429 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1430 t->afree = p->next;
1431 p->data = data;
1432 t->atids_in_use++;
1433 }
1434 spin_unlock_bh(&t->atid_lock);
1435 return atid;
1436}
1437EXPORT_SYMBOL(cxgb4_alloc_atid);
1438
1439/*
1440 * Release an active-open TID.
1441 */
1442void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1443{
f2b7e78d 1444 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1445
1446 spin_lock_bh(&t->atid_lock);
1447 p->next = t->afree;
1448 t->afree = p;
1449 t->atids_in_use--;
1450 spin_unlock_bh(&t->atid_lock);
1451}
1452EXPORT_SYMBOL(cxgb4_free_atid);
1453
1454/*
1455 * Allocate a server TID and set it to the supplied value.
1456 */
1457int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1458{
1459 int stid;
1460
1461 spin_lock_bh(&t->stid_lock);
1462 if (family == PF_INET) {
1463 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1464 if (stid < t->nstids)
1465 __set_bit(stid, t->stid_bmap);
1466 else
1467 stid = -1;
1468 } else {
a99c683e 1469 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
b8ff05a9
DM		 1470 if (stid < 0)
1471 stid = -1;
1472 }
1473 if (stid >= 0) {
1474 t->stid_tab[stid].data = data;
1475 stid += t->stid_base;
15f63b74
KS		 1476 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1477 * This is equivalent to 4 TIDs. With CLIP enabled it
1478 * needs 2 TIDs.
1479 */
1480 if (family == PF_INET)
1481 t->stids_in_use++;
1482 else
a99c683e 1483 t->stids_in_use += 2;
b8ff05a9
DM		 1484 }
1485 spin_unlock_bh(&t->stid_lock);
1486 return stid;
1487}
1488EXPORT_SYMBOL(cxgb4_alloc_stid);
1489
dca4faeb
VP		 1490/* Allocate a server filter TID and set it to the supplied value.
1491 */
1492int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1493{
1494 int stid;
1495
1496 spin_lock_bh(&t->stid_lock);
1497 if (family == PF_INET) {
1498 stid = find_next_zero_bit(t->stid_bmap,
1499 t->nstids + t->nsftids, t->nstids);
1500 if (stid < (t->nstids + t->nsftids))
1501 __set_bit(stid, t->stid_bmap);
1502 else
1503 stid = -1;
1504 } else {
1505 stid = -1;
1506 }
1507 if (stid >= 0) {
1508 t->stid_tab[stid].data = data;
470c60c4
KS		 1509 stid -= t->nstids;
1510 stid += t->sftid_base;
2248b293 1511 t->sftids_in_use++;
dca4faeb
VP		 1512 }
1513 spin_unlock_bh(&t->stid_lock);
1514 return stid;
1515}
1516EXPORT_SYMBOL(cxgb4_alloc_sftid);
1517
1518/* Release a server TID.
b8ff05a9
DM		 1519 */
1520void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1521{
470c60c4
KS		 1522 /* Is it a server filter TID? */
1523 if (t->nsftids && (stid >= t->sftid_base)) {
1524 stid -= t->sftid_base;
1525 stid += t->nstids;
1526 } else {
1527 stid -= t->stid_base;
1528 }
1529
b8ff05a9
DM		 1530 spin_lock_bh(&t->stid_lock);
1531 if (family == PF_INET)
1532 __clear_bit(stid, t->stid_bmap);
1533 else
a99c683e 1534 bitmap_release_region(t->stid_bmap, stid, 1);
b8ff05a9 1535 t->stid_tab[stid].data = NULL;
2248b293
HS		 1536 if (stid < t->nstids) {
1537 if (family == PF_INET)
1538 t->stids_in_use--;
1539 else
a99c683e 1540 t->stids_in_use -= 2;
2248b293
HS		 1541 } else {
1542 t->sftids_in_use--;
1543 }
b8ff05a9
DM		 1544 spin_unlock_bh(&t->stid_lock);
1545}
1546EXPORT_SYMBOL(cxgb4_free_stid);
1547
1548/*
1549 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1550 */
1551static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1552 unsigned int tid)
1553{
1554 struct cpl_tid_release *req;
1555
1556 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1557 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1558 INIT_TP_WR(req, tid);
1559 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1560}
1561
1562/*
1563 * Queue a TID release request and if necessary schedule a work queue to
1564 * process it.
1565 */
31b9c19b 1566static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1567 unsigned int tid)
b8ff05a9
DM		 1568{
1569 void **p = &t->tid_tab[tid];
1570 struct adapter *adap = container_of(t, struct adapter, tids);
1571
1572 spin_lock_bh(&adap->tid_release_lock);
1573 *p = adap->tid_release_head;
1574 /* Low 2 bits encode the Tx channel number */
1575 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1576 if (!adap->tid_release_task_busy) {
1577 adap->tid_release_task_busy = true;
29aaee65 1578 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1579 }
1580 spin_unlock_bh(&adap->tid_release_lock);
1581}
b8ff05a9
DM		 1582
1583/*
1584 * Process the list of pending TID release requests.
1585 */
1586static void process_tid_release_list(struct work_struct *work)
1587{
1588 struct sk_buff *skb;
1589 struct adapter *adap;
1590
1591 adap = container_of(work, struct adapter, tid_release_task);
1592
1593 spin_lock_bh(&adap->tid_release_lock);
1594 while (adap->tid_release_head) {
1595 void **p = adap->tid_release_head;
1596 unsigned int chan = (uintptr_t)p & 3;
1597 p = (void *)p - chan;
1598
1599 adap->tid_release_head = *p;
1600 *p = NULL;
1601 spin_unlock_bh(&adap->tid_release_lock);
1602
1603 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1604 GFP_KERNEL)))
1605 schedule_timeout_uninterruptible(1);
1606
1607 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1608 t4_ofld_send(adap, skb);
1609 spin_lock_bh(&adap->tid_release_lock);
1610 }
1611 adap->tid_release_task_busy = false;
1612 spin_unlock_bh(&adap->tid_release_lock);
1613}
1614
1615/*
1616 * Release a TID and inform HW. If we are unable to allocate the release
1617 * message we defer to a work queue.
1618 */
1619void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1620{
b8ff05a9
DM		 1621 struct sk_buff *skb;
1622 struct adapter *adap = container_of(t, struct adapter, tids);
1623
9a1bb9f6
HS		 1624 WARN_ON(tid >= t->ntids);
1625
1626 if (t->tid_tab[tid]) {
1627 t->tid_tab[tid] = NULL;
1628 if (t->hash_base && (tid >= t->hash_base))
1629 atomic_dec(&t->hash_tids_in_use);
1630 else
1631 atomic_dec(&t->tids_in_use);
1632 }
1633
b8ff05a9
DM		 1634 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1635 if (likely(skb)) {
b8ff05a9
DM		 1636 mk_tid_release(skb, chan, tid);
1637 t4_ofld_send(adap, skb);
1638 } else
1639 cxgb4_queue_tid_release(t, chan, tid);
b8ff05a9
DM		 1640}
1641EXPORT_SYMBOL(cxgb4_remove_tid);
1642
1643/*
1644 * Allocate and initialize the TID tables. Returns 0 on success.
1645 */
1646static int tid_init(struct tid_info *t)
1647{
1648 size_t size;
f2b7e78d 1649 unsigned int stid_bmap_size;
b8ff05a9 1650 unsigned int natids = t->natids;
b6f8eaec 1651 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 1652
dca4faeb 1653 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 1654 size = t->ntids * sizeof(*t->tid_tab) +
1655 natids * sizeof(*t->atid_tab) +
b8ff05a9 1656 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1657 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1658 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 1659 t->nftids * sizeof(*t->ftid_tab) +
1660 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 1661
b8ff05a9
DM		 1662 t->tid_tab = t4_alloc_mem(size);
1663 if (!t->tid_tab)
1664 return -ENOMEM;
1665
1666 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1667 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1668 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1669 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 1670 spin_lock_init(&t->stid_lock);
1671 spin_lock_init(&t->atid_lock);
1672
1673 t->stids_in_use = 0;
2248b293 1674 t->sftids_in_use = 0;
b8ff05a9
DM		 1675 t->afree = NULL;
1676 t->atids_in_use = 0;
1677 atomic_set(&t->tids_in_use, 0);
9a1bb9f6 1678 atomic_set(&t->hash_tids_in_use, 0);
b8ff05a9
DM		 1679
1680 /* Setup the free list for atid_tab and clear the stid bitmap. */
1681 if (natids) {
1682 while (--natids)
1683 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1684 t->afree = t->atid_tab;
1685 }
dca4faeb 1686 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 1687 /* Reserve stid 0 for T4/T5 adapters */
1688 if (!t->stid_base &&
3ccc6cf7 1689 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
b6f8eaec
KS		 1690 __set_bit(0, t->stid_bmap);
1691
b8ff05a9
DM		 1692 return 0;
1693}
1694
1695/**
1696 * cxgb4_create_server - create an IP server
1697 * @dev: the device
1698 * @stid: the server TID
1699 * @sip: local IP address to bind server to
1700 * @sport: the server's TCP port
1701 * @queue: queue to direct messages from this server to
1702 *
1703 * Create an IP server for the given port and address.
1704 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1705 */
1706int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1707 __be32 sip, __be16 sport, __be16 vlan,
1708 unsigned int queue)
b8ff05a9
DM		 1709{
1710 unsigned int chan;
1711 struct sk_buff *skb;
1712 struct adapter *adap;
1713 struct cpl_pass_open_req *req;
80f40c1f 1714 int ret;
b8ff05a9
DM		 1715
1716 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1717 if (!skb)
1718 return -ENOMEM;
1719
1720 adap = netdev2adap(dev);
1721 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1722 INIT_TP_WR(req, 0);
1723 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1724 req->local_port = sport;
1725 req->peer_port = htons(0);
1726 req->local_ip = sip;
1727 req->peer_ip = htonl(0);
e46dab4d 1728 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1729 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1730 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1731 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1732 ret = t4_mgmt_tx(adap, skb);
1733 return net_xmit_eval(ret);
b8ff05a9
DM		 1734}
1735EXPORT_SYMBOL(cxgb4_create_server);
1736
80f40c1f
VP		 1737/* cxgb4_create_server6 - create an IPv6 server
1738 * @dev: the device
1739 * @stid: the server TID
1740 * @sip: local IPv6 address to bind server to
1741 * @sport: the server's TCP port
1742 * @queue: queue to direct messages from this server to
1743 *
1744 * Create an IPv6 server for the given port and address.
1745 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1746 */
1747int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1748 const struct in6_addr *sip, __be16 sport,
1749 unsigned int queue)
1750{
1751 unsigned int chan;
1752 struct sk_buff *skb;
1753 struct adapter *adap;
1754 struct cpl_pass_open_req6 *req;
1755 int ret;
1756
1757 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1758 if (!skb)
1759 return -ENOMEM;
1760
1761 adap = netdev2adap(dev);
1762 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1763 INIT_TP_WR(req, 0);
1764 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1765 req->local_port = sport;
1766 req->peer_port = htons(0);
1767 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1768 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1769 req->peer_ip_hi = cpu_to_be64(0);
1770 req->peer_ip_lo = cpu_to_be64(0);
1771 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1772 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1773 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1774 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1775 ret = t4_mgmt_tx(adap, skb);
1776 return net_xmit_eval(ret);
1777}
1778EXPORT_SYMBOL(cxgb4_create_server6);
1779
1780int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1781 unsigned int queue, bool ipv6)
1782{
1783 struct sk_buff *skb;
1784 struct adapter *adap;
1785 struct cpl_close_listsvr_req *req;
1786 int ret;
1787
1788 adap = netdev2adap(dev);
1789
1790 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1791 if (!skb)
1792 return -ENOMEM;
1793
1794 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1795 INIT_TP_WR(req, 0);
1796 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1797 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1798 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1799 ret = t4_mgmt_tx(adap, skb);
1800 return net_xmit_eval(ret);
1801}
1802EXPORT_SYMBOL(cxgb4_remove_server);
1803
b8ff05a9
DM		 1804/**
1805 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1806 * @mtus: the HW MTU table
1807 * @mtu: the target MTU
1808 * @idx: index of selected entry in the MTU table
1809 *
1810 * Returns the index and the value in the HW MTU table that is closest to
1811 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1812 * table, in which case that smallest available value is selected.
1813 */
1814unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1815 unsigned int *idx)
1816{
1817 unsigned int i = 0;
1818
1819 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1820 ++i;
1821 if (idx)
1822 *idx = i;
1823 return mtus[i];
1824}
1825EXPORT_SYMBOL(cxgb4_best_mtu);
1826
92e7ae71
HS		 1827/**
1828 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1829 * @mtus: the HW MTU table
1830 * @header_size: Header Size
1831 * @data_size_max: maximum Data Segment Size
1832 * @data_size_align: desired Data Segment Size Alignment (2^N)
1833 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1834 *
1835 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1836 * MTU Table based solely on a Maximum MTU parameter, we break that
1837 * parameter up into a Header Size and Maximum Data Segment Size, and
1838 * provide a desired Data Segment Size Alignment. If we find an MTU in
1839 * the Hardware MTU Table which will result in a Data Segment Size with
1840 * the requested alignment _and_ that MTU isn't "too far" from the
1841 * closest MTU, then we'll return that rather than the closest MTU.
1842 */
1843unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1844 unsigned short header_size,
1845 unsigned short data_size_max,
1846 unsigned short data_size_align,
1847 unsigned int *mtu_idxp)
1848{
1849 unsigned short max_mtu = header_size + data_size_max;
1850 unsigned short data_size_align_mask = data_size_align - 1;
1851 int mtu_idx, aligned_mtu_idx;
1852
1853 /* Scan the MTU Table till we find an MTU which is larger than our
1854 * Maximum MTU or we reach the end of the table. Along the way,
1855 * record the last MTU found, if any, which will result in a Data
1856 * Segment Length matching the requested alignment.
1857 */
1858 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1859 unsigned short data_size = mtus[mtu_idx] - header_size;
1860
1861 /* If this MTU minus the Header Size would result in a
1862 * Data Segment Size of the desired alignment, remember it.
1863 */
1864 if ((data_size & data_size_align_mask) == 0)
1865 aligned_mtu_idx = mtu_idx;
1866
1867 /* If we're not at the end of the Hardware MTU Table and the
1868 * next element is larger than our Maximum MTU, drop out of
1869 * the loop.
1870 */
1871 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1872 break;
1873 }
1874
1875 /* If we fell out of the loop because we ran to the end of the table,
1876 * then we just have to use the last [largest] entry.
1877 */
1878 if (mtu_idx == NMTUS)
1879 mtu_idx--;
1880
1881 /* If we found an MTU which resulted in the requested Data Segment
1882 * Length alignment and that's "not far" from the largest MTU which is
1883 * less than or equal to the maximum MTU, then use that.
1884 */
1885 if (aligned_mtu_idx >= 0 &&
1886 mtu_idx - aligned_mtu_idx <= 1)
1887 mtu_idx = aligned_mtu_idx;
1888
1889 /* If the caller has passed in an MTU Index pointer, pass the
1890 * MTU Index back. Return the MTU value.
1891 */
1892 if (mtu_idxp)
1893 *mtu_idxp = mtu_idx;
1894 return mtus[mtu_idx];
1895}
1896EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1897
27999805
H		 1898/**
1899 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1900 * @chip: chip type
1901 * @viid: VI id of the given port
1902 *
1903 * Return the SMT index for this VI.
1904 */
1905unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1906{
1907 /* In T4/T5, SMT contains 256 SMAC entries organized in
1908 * 128 rows of 2 entries each.
1909 * In T6, SMT contains 256 SMAC entries in 256 rows.
1910 * TODO: The below code needs to be updated when we add support
1911 * for 256 VFs.
1912 */
1913 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1914 return ((viid & 0x7f) << 1);
1915 else
1916 return (viid & 0x7f);
1917}
1918EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1919
b8ff05a9
DM		 1920/**
1921 * cxgb4_port_chan - get the HW channel of a port
1922 * @dev: the net device for the port
1923 *
1924 * Return the HW Tx channel of the given port.
1925 */
1926unsigned int cxgb4_port_chan(const struct net_device *dev)
1927{
1928 return netdev2pinfo(dev)->tx_chan;
1929}
1930EXPORT_SYMBOL(cxgb4_port_chan);
1931
881806bc
VP		 1932unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1933{
1934 struct adapter *adap = netdev2adap(dev);
2cc301d2 1935 u32 v1, v2, lp_count, hp_count;
881806bc 1936
f061de42
HS		 1937 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1938 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1939 if (is_t4(adap->params.chip)) {
f061de42
HS		 1940 lp_count = LP_COUNT_G(v1);
1941 hp_count = HP_COUNT_G(v1);
2cc301d2 1942 } else {
f061de42
HS		 1943 lp_count = LP_COUNT_T5_G(v1);
1944 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1945 }
1946 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1947}
1948EXPORT_SYMBOL(cxgb4_dbfifo_count);
1949
b8ff05a9
DM		 1950/**
1951 * cxgb4_port_viid - get the VI id of a port
1952 * @dev: the net device for the port
1953 *
1954 * Return the VI id of the given port.
1955 */
1956unsigned int cxgb4_port_viid(const struct net_device *dev)
1957{
1958 return netdev2pinfo(dev)->viid;
1959}
1960EXPORT_SYMBOL(cxgb4_port_viid);
1961
1962/**
1963 * cxgb4_port_idx - get the index of a port
1964 * @dev: the net device for the port
1965 *
1966 * Return the index of the given port.
1967 */
1968unsigned int cxgb4_port_idx(const struct net_device *dev)
1969{
1970 return netdev2pinfo(dev)->port_id;
1971}
1972EXPORT_SYMBOL(cxgb4_port_idx);
1973
b8ff05a9
DM		 1974void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1975 struct tp_tcp_stats *v6)
1976{
1977 struct adapter *adap = pci_get_drvdata(pdev);
1978
1979 spin_lock(&adap->stats_lock);
1980 t4_tp_get_tcp_stats(adap, v4, v6);
1981 spin_unlock(&adap->stats_lock);
1982}
1983EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1984
1985void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1986 const unsigned int *pgsz_order)
1987{
1988 struct adapter *adap = netdev2adap(dev);
1989
0d804338
HS		 1990 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1991 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1992 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1993 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 1994}
1995EXPORT_SYMBOL(cxgb4_iscsi_init);
1996
3069ee9b
VP		 1997int cxgb4_flush_eq_cache(struct net_device *dev)
1998{
1999 struct adapter *adap = netdev2adap(dev);
3069ee9b 2000
5d700ecb 2001 return t4_sge_ctxt_flush(adap, adap->mbox);
3069ee9b
VP		 2002}
2003EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2004
2005static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2006{
f061de42 2007 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 2008 __be64 indices;
2009 int ret;
2010
fc5ab020
HS		 2011 spin_lock(&adap->win0_lock);
2012 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2013 sizeof(indices), (__be32 *)&indices,
2014 T4_MEMORY_READ);
2015 spin_unlock(&adap->win0_lock);
3069ee9b 2016 if (!ret) {
404d9e3f
VP		 2017 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2018 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 2019 }
2020 return ret;
2021}
2022
2023int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2024 u16 size)
2025{
2026 struct adapter *adap = netdev2adap(dev);
2027 u16 hw_pidx, hw_cidx;
2028 int ret;
2029
2030 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2031 if (ret)
2032 goto out;
2033
2034 if (pidx != hw_pidx) {
2035 u16 delta;
f612b815 2036 u32 val;
3069ee9b
VP		 2037
2038 if (pidx >= hw_pidx)
2039 delta = pidx - hw_pidx;
2040 else
2041 delta = size - hw_pidx + pidx;
f612b815
HS		 2042
2043 if (is_t4(adap->params.chip))
2044 val = PIDX_V(delta);
2045 else
2046 val = PIDX_T5_V(delta);
3069ee9b 2047 wmb();
f612b815
HS		 2048 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2049 QID_V(qid) | val);
3069ee9b
VP		 2050 }
2051out:
2052 return ret;
2053}
2054EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2055
031cf476
HS		 2056int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2057{
2058 struct adapter *adap;
2059 u32 offset, memtype, memaddr;
6559a7e8 2060 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476
HS		 2061 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2062 int ret;
2063
2064 adap = netdev2adap(dev);
2065
2066 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2067
2068 /* Figure out where the offset lands in the Memory Type/Address scheme.
2069 * This code assumes that the memory is laid out starting at offset 0
2070 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2071 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2072 * MC0, and some have both MC0 and MC1.
2073 */
6559a7e8
HS		 2074 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2075 edc0_size = EDRAM0_SIZE_G(size) << 20;
2076 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2077 edc1_size = EDRAM1_SIZE_G(size) << 20;
2078 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2079 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476
HS		 2080
2081 edc0_end = edc0_size;
2082 edc1_end = edc0_end + edc1_size;
2083 mc0_end = edc1_end + mc0_size;
2084
2085 if (offset < edc0_end) {
2086 memtype = MEM_EDC0;
2087 memaddr = offset;
2088 } else if (offset < edc1_end) {
2089 memtype = MEM_EDC1;
2090 memaddr = offset - edc0_end;
2091 } else {
2092 if (offset < mc0_end) {
2093 memtype = MEM_MC0;
2094 memaddr = offset - edc1_end;
3ccc6cf7 2095 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 2096 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2097 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 2098 mc1_end = mc0_end + mc1_size;
2099 if (offset < mc1_end) {
2100 memtype = MEM_MC1;
2101 memaddr = offset - mc0_end;
2102 } else {
2103 /* offset beyond the end of any memory */
2104 goto err;
2105 }
3ccc6cf7
HS		 2106 } else {
2107 /* T4/T6 only has a single memory channel */
2108 goto err;
031cf476
HS		 2109 }
2110 }
2111
2112 spin_lock(&adap->win0_lock);
2113 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2114 spin_unlock(&adap->win0_lock);
2115 return ret;
2116
2117err:
2118 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2119 stag, offset);
2120 return -EINVAL;
2121}
2122EXPORT_SYMBOL(cxgb4_read_tpte);
2123
7730b4c7
HS		 2124u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2125{
2126 u32 hi, lo;
2127 struct adapter *adap;
2128
2129 adap = netdev2adap(dev);
f612b815
HS		 2130 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2131 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 2132
2133 return ((u64)hi << 32) | (u64)lo;
2134}
2135EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2136
df64e4d3
HS		 2137int cxgb4_bar2_sge_qregs(struct net_device *dev,
2138 unsigned int qid,
2139 enum cxgb4_bar2_qtype qtype,
66cf188e 2140 int user,
df64e4d3
HS		 2141 u64 *pbar2_qoffset,
2142 unsigned int *pbar2_qid)
2143{
b2612722 2144 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 2145 qid,
2146 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2147 ? T4_BAR2_QTYPE_EGRESS
2148 : T4_BAR2_QTYPE_INGRESS),
66cf188e 2149 user,
df64e4d3
HS		 2150 pbar2_qoffset,
2151 pbar2_qid);
2152}
2153EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2154
b8ff05a9
DM		 2155static struct pci_driver cxgb4_driver;
2156
2157static void check_neigh_update(struct neighbour *neigh)
2158{
2159 const struct device *parent;
2160 const struct net_device *netdev = neigh->dev;
2161
2162 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2163 netdev = vlan_dev_real_dev(netdev);
2164 parent = netdev->dev.parent;
2165 if (parent && parent->driver == &cxgb4_driver.driver)
2166 t4_l2t_update(dev_get_drvdata(parent), neigh);
2167}
2168
2169static int netevent_cb(struct notifier_block *nb, unsigned long event,
2170 void *data)
2171{
2172 switch (event) {
2173 case NETEVENT_NEIGH_UPDATE:
2174 check_neigh_update(data);
2175 break;
b8ff05a9
DM		 2176 case NETEVENT_REDIRECT:
2177 default:
2178 break;
2179 }
2180 return 0;
2181}
2182
2183static bool netevent_registered;
2184static struct notifier_block cxgb4_netevent_nb = {
2185 .notifier_call = netevent_cb
2186};
2187
3069ee9b
VP		 2188static void drain_db_fifo(struct adapter *adap, int usecs)
2189{
2cc301d2 2190 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 2191
2192 do {
f061de42
HS		 2193 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2194 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 2195 if (is_t4(adap->params.chip)) {
f061de42
HS		 2196 lp_count = LP_COUNT_G(v1);
2197 hp_count = HP_COUNT_G(v1);
2cc301d2 2198 } else {
f061de42
HS		 2199 lp_count = LP_COUNT_T5_G(v1);
2200 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 2201 }
2202
2203 if (lp_count == 0 && hp_count == 0)
2204 break;
3069ee9b
VP		 2205 set_current_state(TASK_UNINTERRUPTIBLE);
2206 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 2207 } while (1);
2208}
2209
2210static void disable_txq_db(struct sge_txq *q)
2211{
05eb2389
SW		 2212 unsigned long flags;
2213
2214 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 2215 q->db_disabled = 1;
05eb2389 2216 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 2217}
2218
05eb2389 2219static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 2220{
2221 spin_lock_irq(&q->db_lock);
05eb2389
SW		 2222 if (q->db_pidx_inc) {
2223 /* Make sure that all writes to the TX descriptors
2224 * are committed before we tell HW about them.
2225 */
2226 wmb();
f612b815
HS		 2227 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2228 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 2229 q->db_pidx_inc = 0;
2230 }
3069ee9b
VP		 2231 q->db_disabled = 0;
2232 spin_unlock_irq(&q->db_lock);
2233}
2234
2235static void disable_dbs(struct adapter *adap)
2236{
2237 int i;
2238
2239 for_each_ethrxq(&adap->sge, i)
2240 disable_txq_db(&adap->sge.ethtxq[i].q);
f90ce561 2241 for_each_iscsirxq(&adap->sge, i)
3069ee9b
VP		 2242 disable_txq_db(&adap->sge.ofldtxq[i].q);
2243 for_each_port(adap, i)
2244 disable_txq_db(&adap->sge.ctrlq[i].q);
2245}
2246
2247static void enable_dbs(struct adapter *adap)
2248{
2249 int i;
2250
2251 for_each_ethrxq(&adap->sge, i)
05eb2389 2252 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
f90ce561 2253 for_each_iscsirxq(&adap->sge, i)
05eb2389 2254 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 2255 for_each_port(adap, i)
05eb2389
SW		 2256 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2257}
2258
2259static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2260{
2261 if (adap->uld_handle[CXGB4_ULD_RDMA])
2262 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2263 cmd);
2264}
2265
2266static void process_db_full(struct work_struct *work)
2267{
2268 struct adapter *adap;
2269
2270 adap = container_of(work, struct adapter, db_full_task);
2271
2272 drain_db_fifo(adap, dbfifo_drain_delay);
2273 enable_dbs(adap);
2274 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 2275 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2276 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2277 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2278 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2279 else
2280 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2281 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 2282}
2283
2284static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2285{
2286 u16 hw_pidx, hw_cidx;
2287 int ret;
2288
05eb2389 2289 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 2290 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2291 if (ret)
2292 goto out;
2293 if (q->db_pidx != hw_pidx) {
2294 u16 delta;
f612b815 2295 u32 val;
3069ee9b
VP		 2296
2297 if (q->db_pidx >= hw_pidx)
2298 delta = q->db_pidx - hw_pidx;
2299 else
2300 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 2301
2302 if (is_t4(adap->params.chip))
2303 val = PIDX_V(delta);
2304 else
2305 val = PIDX_T5_V(delta);
3069ee9b 2306 wmb();
f612b815
HS		 2307 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2308 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2309 }
2310out:
2311 q->db_disabled = 0;
05eb2389
SW		 2312 q->db_pidx_inc = 0;
2313 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2314 if (ret)
2315 CH_WARN(adap, "DB drop recovery failed.\n");
2316}
2317static void recover_all_queues(struct adapter *adap)
2318{
2319 int i;
2320
2321 for_each_ethrxq(&adap->sge, i)
2322 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
f90ce561 2323 for_each_iscsirxq(&adap->sge, i)
3069ee9b
VP		 2324 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2325 for_each_port(adap, i)
2326 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2327}
2328
881806bc
VP		 2329static void process_db_drop(struct work_struct *work)
2330{
2331 struct adapter *adap;
881806bc 2332
3069ee9b 2333 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2334
d14807dd 2335 if (is_t4(adap->params.chip)) {
05eb2389 2336 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2337 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2338 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2339 recover_all_queues(adap);
05eb2389 2340 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2341 enable_dbs(adap);
05eb2389 2342 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2343 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2344 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2345 u16 qid = (dropped_db >> 15) & 0x1ffff;
2346 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2347 u64 bar2_qoffset;
2348 unsigned int bar2_qid;
2349 int ret;
2cc301d2 2350
b2612722 2351 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
e0456717 2352 0, &bar2_qoffset, &bar2_qid);
df64e4d3
HS		 2353 if (ret)
2354 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2355 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2356 else
f612b815 2357 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2358 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2359
2360 /* Re-enable BAR2 WC */
2361 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2362 }
2363
3ccc6cf7
HS		 2364 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2365 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2366}
2367
2368void t4_db_full(struct adapter *adap)
2369{
d14807dd 2370 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2371 disable_dbs(adap);
2372 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2373 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2374 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2375 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2376 }
881806bc
VP		 2377}
2378
2379void t4_db_dropped(struct adapter *adap)
2380{
05eb2389
SW		 2381 if (is_t4(adap->params.chip)) {
2382 disable_dbs(adap);
2383 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2384 }
29aaee65 2385 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2386}
2387
b8ff05a9
DM		 2388static void uld_attach(struct adapter *adap, unsigned int uld)
2389{
2390 void *handle;
2391 struct cxgb4_lld_info lli;
dca4faeb 2392 unsigned short i;
b8ff05a9
DM		 2393
2394 lli.pdev = adap->pdev;
b2612722 2395 lli.pf = adap->pf;
b8ff05a9
DM		 2396 lli.l2t = adap->l2t;
2397 lli.tids = &adap->tids;
2398 lli.ports = adap->port;
2399 lli.vr = &adap->vres;
2400 lli.mtus = adap->params.mtus;
2401 if (uld == CXGB4_ULD_RDMA) {
2402 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 2403 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 2404 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 2405 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9 2406 } else if (uld == CXGB4_ULD_ISCSI) {
f90ce561
HS		 2407 lli.rxq_ids = adap->sge.iscsi_rxq;
2408 lli.nrxq = adap->sge.iscsiqsets;
b8ff05a9 2409 }
f90ce561 2410 lli.ntxq = adap->sge.iscsiqsets;
b8ff05a9
DM		 2411 lli.nchan = adap->params.nports;
2412 lli.nports = adap->params.nports;
2413 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 2414 lli.adapter_type = adap->params.chip;
837e4a42 2415 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
7730b4c7 2416 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
df64e4d3
HS		 2417 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2418 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
dcf7b6f5 2419 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 2420 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2421 for (i = 0; i < NCHAN; i++)
2422 lli.tx_modq[i] = i;
f612b815
HS		 2423 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2424 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
b8ff05a9 2425 lli.fw_vers = adap->params.fw_vers;
3069ee9b 2426 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS		 2427 lli.sge_ingpadboundary = adap->sge.fl_align;
2428 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP		 2429 lli.sge_pktshift = adap->sge.pktshift;
2430 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS		 2431 lli.max_ordird_qp = adap->params.max_ordird_qp;
2432 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 2433 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
982b81eb 2434 lli.nodeid = dev_to_node(adap->pdev_dev);
b8ff05a9
DM		 2435
2436 handle = ulds[uld].add(&lli);
2437 if (IS_ERR(handle)) {
2438 dev_warn(adap->pdev_dev,
2439 "could not attach to the %s driver, error %ld\n",
2440 uld_str[uld], PTR_ERR(handle));
2441 return;
2442 }
2443
2444 adap->uld_handle[uld] = handle;
2445
2446 if (!netevent_registered) {
2447 register_netevent_notifier(&cxgb4_netevent_nb);
2448 netevent_registered = true;
2449 }
e29f5dbc
DM		 2450
2451 if (adap->flags & FULL_INIT_DONE)
2452 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 2453}
2454
2455static void attach_ulds(struct adapter *adap)
2456{
2457 unsigned int i;
2458
01bcca68
VP		 2459 spin_lock(&adap_rcu_lock);
2460 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2461 spin_unlock(&adap_rcu_lock);
2462
b8ff05a9
DM		 2463 mutex_lock(&uld_mutex);
2464 list_add_tail(&adap->list_node, &adapter_list);
2465 for (i = 0; i < CXGB4_ULD_MAX; i++)
2466 if (ulds[i].add)
2467 uld_attach(adap, i);
2468 mutex_unlock(&uld_mutex);
2469}
2470
2471static void detach_ulds(struct adapter *adap)
2472{
2473 unsigned int i;
2474
2475 mutex_lock(&uld_mutex);
2476 list_del(&adap->list_node);
2477 for (i = 0; i < CXGB4_ULD_MAX; i++)
2478 if (adap->uld_handle[i]) {
2479 ulds[i].state_change(adap->uld_handle[i],
2480 CXGB4_STATE_DETACH);
2481 adap->uld_handle[i] = NULL;
2482 }
2483 if (netevent_registered && list_empty(&adapter_list)) {
2484 unregister_netevent_notifier(&cxgb4_netevent_nb);
2485 netevent_registered = false;
2486 }
2487 mutex_unlock(&uld_mutex);
01bcca68
VP		 2488
2489 spin_lock(&adap_rcu_lock);
2490 list_del_rcu(&adap->rcu_node);
2491 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 2492}
2493
2494static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2495{
2496 unsigned int i;
2497
2498 mutex_lock(&uld_mutex);
2499 for (i = 0; i < CXGB4_ULD_MAX; i++)
2500 if (adap->uld_handle[i])
2501 ulds[i].state_change(adap->uld_handle[i], new_state);
2502 mutex_unlock(&uld_mutex);
2503}
2504
2505/**
2506 * cxgb4_register_uld - register an upper-layer driver
2507 * @type: the ULD type
2508 * @p: the ULD methods
2509 *
2510 * Registers an upper-layer driver with this driver and notifies the ULD
2511 * about any presently available devices that support its type. Returns
2512 * %-EBUSY if a ULD of the same type is already registered.
2513 */
2514int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2515{
2516 int ret = 0;
2517 struct adapter *adap;
2518
2519 if (type >= CXGB4_ULD_MAX)
2520 return -EINVAL;
2521 mutex_lock(&uld_mutex);
2522 if (ulds[type].add) {
2523 ret = -EBUSY;
2524 goto out;
2525 }
2526 ulds[type] = *p;
2527 list_for_each_entry(adap, &adapter_list, list_node)
2528 uld_attach(adap, type);
2529out: mutex_unlock(&uld_mutex);
2530 return ret;
2531}
2532EXPORT_SYMBOL(cxgb4_register_uld);
2533
2534/**
2535 * cxgb4_unregister_uld - unregister an upper-layer driver
2536 * @type: the ULD type
2537 *
2538 * Unregisters an existing upper-layer driver.
2539 */
2540int cxgb4_unregister_uld(enum cxgb4_uld type)
2541{
2542 struct adapter *adap;
2543
2544 if (type >= CXGB4_ULD_MAX)
2545 return -EINVAL;
2546 mutex_lock(&uld_mutex);
2547 list_for_each_entry(adap, &adapter_list, list_node)
2548 adap->uld_handle[type] = NULL;
2549 ulds[type].add = NULL;
2550 mutex_unlock(&uld_mutex);
2551 return 0;
2552}
2553EXPORT_SYMBOL(cxgb4_unregister_uld);
2554
1bb60376 2555#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2556static int cxgb4_inet6addr_handler(struct notifier_block *this,
2557 unsigned long event, void *data)
01bcca68 2558{
b5a02f50
AB		 2559 struct inet6_ifaddr *ifa = data;
2560 struct net_device *event_dev = ifa->idev->dev;
2561 const struct device *parent = NULL;
2562#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2563 struct adapter *adap;
b5a02f50
AB		 2564#endif
2565 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2566 event_dev = vlan_dev_real_dev(event_dev);
2567#if IS_ENABLED(CONFIG_BONDING)
2568 if (event_dev->flags & IFF_MASTER) {
2569 list_for_each_entry(adap, &adapter_list, list_node) {
2570 switch (event) {
2571 case NETDEV_UP:
2572 cxgb4_clip_get(adap->port[0],
2573 (const u32 *)ifa, 1);
2574 break;
2575 case NETDEV_DOWN:
2576 cxgb4_clip_release(adap->port[0],
2577 (const u32 *)ifa, 1);
2578 break;
2579 default:
2580 break;
2581 }
2582 }
2583 return NOTIFY_OK;
2584 }
2585#endif
01bcca68 2586
b5a02f50
AB		 2587 if (event_dev)
2588 parent = event_dev->dev.parent;
01bcca68 2589
b5a02f50 2590 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2591 switch (event) {
2592 case NETDEV_UP:
b5a02f50 2593 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2594 break;
2595 case NETDEV_DOWN:
b5a02f50 2596 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2597 break;
2598 default:
2599 break;
2600 }
2601 }
b5a02f50 2602 return NOTIFY_OK;
01bcca68
VP		 2603}
2604
b5a02f50 2605static bool inet6addr_registered;
01bcca68
VP		 2606static struct notifier_block cxgb4_inet6addr_notifier = {
2607 .notifier_call = cxgb4_inet6addr_handler
2608};
2609
01bcca68
VP		 2610static void update_clip(const struct adapter *adap)
2611{
2612 int i;
2613 struct net_device *dev;
2614 int ret;
2615
2616 rcu_read_lock();
2617
2618 for (i = 0; i < MAX_NPORTS; i++) {
2619 dev = adap->port[i];
2620 ret = 0;
2621
2622 if (dev)
b5a02f50 2623 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2624
2625 if (ret < 0)
2626 break;
2627 }
2628 rcu_read_unlock();
2629}
1bb60376 2630#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2631
b8ff05a9
DM		 2632/**
2633 * cxgb_up - enable the adapter
2634 * @adap: adapter being enabled
2635 *
2636 * Called when the first port is enabled, this function performs the
2637 * actions necessary to make an adapter operational, such as completing
2638 * the initialization of HW modules, and enabling interrupts.
2639 *
2640 * Must be called with the rtnl lock held.
2641 */
2642static int cxgb_up(struct adapter *adap)
2643{
aaefae9b 2644 int err;
b8ff05a9 2645
aaefae9b
DM		 2646 err = setup_sge_queues(adap);
2647 if (err)
2648 goto out;
2649 err = setup_rss(adap);
2650 if (err)
2651 goto freeq;
b8ff05a9
DM		 2652
2653 if (adap->flags & USING_MSIX) {
aaefae9b 2654 name_msix_vecs(adap);
b8ff05a9
DM		 2655 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2656 adap->msix_info[0].desc, adap);
2657 if (err)
2658 goto irq_err;
2659
2660 err = request_msix_queue_irqs(adap);
2661 if (err) {
2662 free_irq(adap->msix_info[0].vec, adap);
2663 goto irq_err;
2664 }
2665 } else {
2666 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2667 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2668 adap->port[0]->name, adap);
b8ff05a9
DM		 2669 if (err)
2670 goto irq_err;
2671 }
2672 enable_rx(adap);
2673 t4_sge_start(adap);
2674 t4_intr_enable(adap);
aaefae9b 2675 adap->flags |= FULL_INIT_DONE;
b8ff05a9 2676 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2677#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2678 update_clip(adap);
1bb60376 2679#endif
b8ff05a9
DM		 2680 out:
2681 return err;
2682 irq_err:
2683 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2684 freeq:
2685 t4_free_sge_resources(adap);
b8ff05a9
DM		 2686 goto out;
2687}
2688
2689static void cxgb_down(struct adapter *adapter)
2690{
b8ff05a9 2691 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2692 cancel_work_sync(&adapter->db_full_task);
2693 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2694 adapter->tid_release_task_busy = false;
204dc3c0 2695 adapter->tid_release_head = NULL;
b8ff05a9 2696
aaefae9b
DM		 2697 t4_sge_stop(adapter);
2698 t4_free_sge_resources(adapter);
2699 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2700}
2701
2702/*
2703 * net_device operations
2704 */
2705static int cxgb_open(struct net_device *dev)
2706{
2707 int err;
2708 struct port_info *pi = netdev_priv(dev);
2709 struct adapter *adapter = pi->adapter;
2710
6a3c869a
DM		 2711 netif_carrier_off(dev);
2712
aaefae9b
DM		 2713 if (!(adapter->flags & FULL_INIT_DONE)) {
2714 err = cxgb_up(adapter);
2715 if (err < 0)
2716 return err;
2717 }
b8ff05a9 2718
f68707b8
DM		 2719 err = link_start(dev);
2720 if (!err)
2721 netif_tx_start_all_queues(dev);
2722 return err;
b8ff05a9
DM		 2723}
2724
2725static int cxgb_close(struct net_device *dev)
2726{
b8ff05a9
DM		 2727 struct port_info *pi = netdev_priv(dev);
2728 struct adapter *adapter = pi->adapter;
2729
2730 netif_tx_stop_all_queues(dev);
2731 netif_carrier_off(dev);
b2612722 2732 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
b8ff05a9
DM		 2733}
2734
f2b7e78d
VP		 2735/* Return an error number if the indicated filter isn't writable ...
2736 */
2737static int writable_filter(struct filter_entry *f)
2738{
2739 if (f->locked)
2740 return -EPERM;
2741 if (f->pending)
2742 return -EBUSY;
2743
2744 return 0;
2745}
2746
2747/* Delete the filter at the specified index (if valid). The checks for all
2748 * the common problems with doing this like the filter being locked, currently
2749 * pending in another operation, etc.
2750 */
2751static int delete_filter(struct adapter *adapter, unsigned int fidx)
2752{
2753 struct filter_entry *f;
2754 int ret;
2755
dca4faeb 2756 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 2757 return -EINVAL;
2758
2759 f = &adapter->tids.ftid_tab[fidx];
2760 ret = writable_filter(f);
2761 if (ret)
2762 return ret;
2763 if (f->valid)
2764 return del_filter_wr(adapter, fidx);
2765
2766 return 0;
2767}
2768
dca4faeb 2769int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2770 __be32 sip, __be16 sport, __be16 vlan,
2771 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2772{
2773 int ret;
2774 struct filter_entry *f;
2775 struct adapter *adap;
2776 int i;
2777 u8 *val;
2778
2779 adap = netdev2adap(dev);
2780
1cab775c 2781 /* Adjust stid to correct filter index */
470c60c4 2782 stid -= adap->tids.sftid_base;
1cab775c
VP		 2783 stid += adap->tids.nftids;
2784
dca4faeb
VP		 2785 /* Check to make sure the filter requested is writable ...
2786 */
2787 f = &adap->tids.ftid_tab[stid];
2788 ret = writable_filter(f);
2789 if (ret)
2790 return ret;
2791
2792 /* Clear out any old resources being used by the filter before
2793 * we start constructing the new filter.
2794 */
2795 if (f->valid)
2796 clear_filter(adap, f);
2797
2798 /* Clear out filter specifications */
2799 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2800 f->fs.val.lport = cpu_to_be16(sport);
2801 f->fs.mask.lport = ~0;
2802 val = (u8 *)&sip;
793dad94 2803 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2804 for (i = 0; i < 4; i++) {
2805 f->fs.val.lip[i] = val[i];
2806 f->fs.mask.lip[i] = ~0;
2807 }
0d804338 2808 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2809 f->fs.val.iport = port;
2810 f->fs.mask.iport = mask;
2811 }
2812 }
dca4faeb 2813
0d804338 2814 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2815 f->fs.val.proto = IPPROTO_TCP;
2816 f->fs.mask.proto = ~0;
2817 }
2818
dca4faeb
VP		 2819 f->fs.dirsteer = 1;
2820 f->fs.iq = queue;
2821 /* Mark filter as locked */
2822 f->locked = 1;
2823 f->fs.rpttid = 1;
2824
2825 ret = set_filter_wr(adap, stid);
2826 if (ret) {
2827 clear_filter(adap, f);
2828 return ret;
2829 }
2830
2831 return 0;
2832}
2833EXPORT_SYMBOL(cxgb4_create_server_filter);
2834
2835int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2836 unsigned int queue, bool ipv6)
2837{
2838 int ret;
2839 struct filter_entry *f;
2840 struct adapter *adap;
2841
2842 adap = netdev2adap(dev);
1cab775c
VP		 2843
2844 /* Adjust stid to correct filter index */
470c60c4 2845 stid -= adap->tids.sftid_base;
1cab775c
VP		 2846 stid += adap->tids.nftids;
2847
dca4faeb
VP		 2848 f = &adap->tids.ftid_tab[stid];
2849 /* Unlock the filter */
2850 f->locked = 0;
2851
2852 ret = delete_filter(adap, stid);
2853 if (ret)
2854 return ret;
2855
2856 return 0;
2857}
2858EXPORT_SYMBOL(cxgb4_remove_server_filter);
2859
f5152c90
DM		 2860static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2861 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2862{
2863 struct port_stats stats;
2864 struct port_info *p = netdev_priv(dev);
2865 struct adapter *adapter = p->adapter;
b8ff05a9 2866
9fe6cb58
GS		 2867 /* Block retrieving statistics during EEH error
2868 * recovery. Otherwise, the recovery might fail
2869 * and the PCI device will be removed permanently
2870 */
b8ff05a9 2871 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2872 if (!netif_device_present(dev)) {
2873 spin_unlock(&adapter->stats_lock);
2874 return ns;
2875 }
a4cfd929
HS		 2876 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2877 &p->stats_base);
b8ff05a9
DM		 2878 spin_unlock(&adapter->stats_lock);
2879
2880 ns->tx_bytes = stats.tx_octets;
2881 ns->tx_packets = stats.tx_frames;
2882 ns->rx_bytes = stats.rx_octets;
2883 ns->rx_packets = stats.rx_frames;
2884 ns->multicast = stats.rx_mcast_frames;
2885
2886 /* detailed rx_errors */
2887 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2888 stats.rx_runt;
2889 ns->rx_over_errors = 0;
2890 ns->rx_crc_errors = stats.rx_fcs_err;
2891 ns->rx_frame_errors = stats.rx_symbol_err;
2892 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2893 stats.rx_ovflow2 + stats.rx_ovflow3 +
2894 stats.rx_trunc0 + stats.rx_trunc1 +
2895 stats.rx_trunc2 + stats.rx_trunc3;
2896 ns->rx_missed_errors = 0;
2897
2898 /* detailed tx_errors */
2899 ns->tx_aborted_errors = 0;
2900 ns->tx_carrier_errors = 0;
2901 ns->tx_fifo_errors = 0;
2902 ns->tx_heartbeat_errors = 0;
2903 ns->tx_window_errors = 0;
2904
2905 ns->tx_errors = stats.tx_error_frames;
2906 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2907 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2908 return ns;
2909}
2910
2911static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2912{
060e0c75 2913 unsigned int mbox;
b8ff05a9
DM		 2914 int ret = 0, prtad, devad;
2915 struct port_info *pi = netdev_priv(dev);
2916 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2917
2918 switch (cmd) {
2919 case SIOCGMIIPHY:
2920 if (pi->mdio_addr < 0)
2921 return -EOPNOTSUPP;
2922 data->phy_id = pi->mdio_addr;
2923 break;
2924 case SIOCGMIIREG:
2925 case SIOCSMIIREG:
2926 if (mdio_phy_id_is_c45(data->phy_id)) {
2927 prtad = mdio_phy_id_prtad(data->phy_id);
2928 devad = mdio_phy_id_devad(data->phy_id);
2929 } else if (data->phy_id < 32) {
2930 prtad = data->phy_id;
2931 devad = 0;
2932 data->reg_num &= 0x1f;
2933 } else
2934 return -EINVAL;
2935
b2612722 2936 mbox = pi->adapter->pf;
b8ff05a9 2937 if (cmd == SIOCGMIIREG)
060e0c75 2938 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2939 data->reg_num, &data->val_out);
2940 else
060e0c75 2941 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2942 data->reg_num, data->val_in);
2943 break;
5e2a5ebc
HS		 2944 case SIOCGHWTSTAMP:
2945 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2946 sizeof(pi->tstamp_config)) ?
2947 -EFAULT : 0;
2948 case SIOCSHWTSTAMP:
2949 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2950 sizeof(pi->tstamp_config)))
2951 return -EFAULT;
2952
2953 switch (pi->tstamp_config.rx_filter) {
2954 case HWTSTAMP_FILTER_NONE:
2955 pi->rxtstamp = false;
2956 break;
2957 case HWTSTAMP_FILTER_ALL:
2958 pi->rxtstamp = true;
2959 break;
2960 default:
2961 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2962 return -ERANGE;
2963 }
2964
2965 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2966 sizeof(pi->tstamp_config)) ?
2967 -EFAULT : 0;
b8ff05a9
DM		 2968 default:
2969 return -EOPNOTSUPP;
2970 }
2971 return ret;
2972}
2973
2974static void cxgb_set_rxmode(struct net_device *dev)
2975{
2976 /* unfortunately we can't return errors to the stack */
2977 set_rxmode(dev, -1, false);
2978}
2979
2980static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2981{
2982 int ret;
2983 struct port_info *pi = netdev_priv(dev);
2984
2985 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2986 return -EINVAL;
b2612722 2987 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2988 -1, -1, -1, true);
b8ff05a9
DM		 2989 if (!ret)
2990 dev->mtu = new_mtu;
2991 return ret;
2992}
2993
2994static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2995{
2996 int ret;
2997 struct sockaddr *addr = p;
2998 struct port_info *pi = netdev_priv(dev);
2999
3000 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 3001 return -EADDRNOTAVAIL;
b8ff05a9 3002
b2612722 3003 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
060e0c75 3004 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 3005 if (ret < 0)
3006 return ret;
3007
3008 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3009 pi->xact_addr_filt = ret;
3010 return 0;
3011}
3012
b8ff05a9
DM		 3013#ifdef CONFIG_NET_POLL_CONTROLLER
3014static void cxgb_netpoll(struct net_device *dev)
3015{
3016 struct port_info *pi = netdev_priv(dev);
3017 struct adapter *adap = pi->adapter;
3018
3019 if (adap->flags & USING_MSIX) {
3020 int i;
3021 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3022
3023 for (i = pi->nqsets; i; i--, rx++)
3024 t4_sge_intr_msix(0, &rx->rspq);
3025 } else
3026 t4_intr_handler(adap)(0, adap);
3027}
3028#endif
3029
3030static const struct net_device_ops cxgb4_netdev_ops = {
3031 .ndo_open = cxgb_open,
3032 .ndo_stop = cxgb_close,
3033 .ndo_start_xmit = t4_eth_xmit,
688848b1 3034 .ndo_select_queue = cxgb_select_queue,
9be793bf 3035 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3036 .ndo_set_rx_mode = cxgb_set_rxmode,
3037 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3038 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3039 .ndo_validate_addr = eth_validate_addr,
3040 .ndo_do_ioctl = cxgb_ioctl,
3041 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3042#ifdef CONFIG_NET_POLL_CONTROLLER
3043 .ndo_poll_controller = cxgb_netpoll,
3044#endif
84a200b3
VP		 3045#ifdef CONFIG_CHELSIO_T4_FCOE
3046 .ndo_fcoe_enable = cxgb_fcoe_enable,
3047 .ndo_fcoe_disable = cxgb_fcoe_disable,
3048#endif /* CONFIG_CHELSIO_T4_FCOE */
3a336cb1
HS		 3049#ifdef CONFIG_NET_RX_BUSY_POLL
3050 .ndo_busy_poll = cxgb_busy_poll,
3051#endif
3052
b8ff05a9
DM		 3053};
3054
3055void t4_fatal_err(struct adapter *adap)
3056{
f612b815 3057 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
b8ff05a9
DM		 3058 t4_intr_disable(adap);
3059 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3060}
3061
3062static void setup_memwin(struct adapter *adap)
3063{
b562fc37 3064 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3065
b562fc37 3066 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3067}
3068
3069static void setup_memwin_rdma(struct adapter *adap)
3070{
1ae970e0 3071 if (adap->vres.ocq.size) {
0abfd152
HS		 3072 u32 start;
3073 unsigned int sz_kb;
1ae970e0 3074
0abfd152
HS		 3075 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3076 start &= PCI_BASE_ADDRESS_MEM_MASK;
3077 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3078 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3079 t4_write_reg(adap,
f061de42
HS		 3080 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3081 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3082 t4_write_reg(adap,
f061de42 3083 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3084 adap->vres.ocq.start);
3085 t4_read_reg(adap,
f061de42 3086 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3087 }
b8ff05a9
DM		 3088}
3089
02b5fb8e
DM		 3090static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3091{
3092 u32 v;
3093 int ret;
3094
3095 /* get device capabilities */
3096 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3097 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3098 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3099 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3100 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3101 if (ret < 0)
3102 return ret;
3103
e2ac9628
HS		 3104 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3105 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3106 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3107 if (ret < 0)
3108 return ret;
3109
b2612722 3110 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3111 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3112 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3113 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3114 if (ret < 0)
3115 return ret;
3116
b2612722 3117 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3118 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3119 FW_CMD_CAP_PF);
02b5fb8e
DM		 3120 if (ret < 0)
3121 return ret;
3122
3123 t4_sge_init(adap);
3124
02b5fb8e 3125 /* tweak some settings */
837e4a42 3126 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3127 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3128 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3129 v = t4_read_reg(adap, TP_PIO_DATA_A);
3130 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3131
dca4faeb
VP		 3132 /* first 4 Tx modulation queues point to consecutive Tx channels */
3133 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3134 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3135 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3136
3137 /* associate each Tx modulation queue with consecutive Tx channels */
3138 v = 0x84218421;
837e4a42 3139 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3140 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3141 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3142 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3143 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3144 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3145
3146#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3147 if (is_offload(adap)) {
0d804338
HS		 3148 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3149 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3150 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3151 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3152 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3153 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3154 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3155 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3156 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3157 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3158 }
3159
060e0c75 3160 /* get basic stuff going */
b2612722 3161 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3162}
3163
b8ff05a9
DM		 3164/*
3165 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3166 */
3167#define MAX_ATIDS 8192U
3168
636f9d37
VP		 3169/*
3170 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3171 *
3172 * If the firmware we're dealing with has Configuration File support, then
3173 * we use that to perform all configuration
3174 */
3175
3176/*
3177 * Tweak configuration based on module parameters, etc. Most of these have
3178 * defaults assigned to them by Firmware Configuration Files (if we're using
3179 * them) but need to be explicitly set if we're using hard-coded
3180 * initialization. But even in the case of using Firmware Configuration
3181 * Files, we'd like to expose the ability to change these via module
3182 * parameters so these are essentially common tweaks/settings for
3183 * Configuration Files and hard-coded initialization ...
3184 */
3185static int adap_init0_tweaks(struct adapter *adapter)
3186{
3187 /*
3188 * Fix up various Host-Dependent Parameters like Page Size, Cache
3189 * Line Size, etc. The firmware default is for a 4KB Page Size and
3190 * 64B Cache Line Size ...
3191 */
3192 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3193
3194 /*
3195 * Process module parameters which affect early initialization.
3196 */
3197 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3198 dev_err(&adapter->pdev->dev,
3199 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3200 rx_dma_offset);
3201 rx_dma_offset = 2;
3202 }
f612b815
HS		 3203 t4_set_reg_field(adapter, SGE_CONTROL_A,
3204 PKTSHIFT_V(PKTSHIFT_M),
3205 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3206
3207 /*
3208 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3209 * adds the pseudo header itself.
3210 */
837e4a42
HS		 3211 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3212 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3213
3214 return 0;
3215}
3216
01b69614
HS		 3217/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3218 * unto themselves and they contain their own firmware to perform their
3219 * tasks ...
3220 */
3221static int phy_aq1202_version(const u8 *phy_fw_data,
3222 size_t phy_fw_size)
3223{
3224 int offset;
3225
3226 /* At offset 0x8 you're looking for the primary image's
3227 * starting offset which is 3 Bytes wide
3228 *
3229 * At offset 0xa of the primary image, you look for the offset
3230 * of the DRAM segment which is 3 Bytes wide.
3231 *
3232 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3233 * wide
3234 */
3235 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3236 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3237 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3238
3239 offset = le24(phy_fw_data + 0x8) << 12;
3240 offset = le24(phy_fw_data + offset + 0xa);
3241 return be16(phy_fw_data + offset + 0x27e);
3242
3243 #undef be16
3244 #undef le16
3245 #undef le24
3246}
3247
3248static struct info_10gbt_phy_fw {
3249 unsigned int phy_fw_id; /* PCI Device ID */
3250 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3251 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3252 int phy_flash; /* Has FLASH for PHY Firmware */
3253} phy_info_array[] = {
3254 {
3255 PHY_AQ1202_DEVICEID,
3256 PHY_AQ1202_FIRMWARE,
3257 phy_aq1202_version,
3258 1,
3259 },
3260 {
3261 PHY_BCM84834_DEVICEID,
3262 PHY_BCM84834_FIRMWARE,
3263 NULL,
3264 0,
3265 },
3266 { 0, NULL, NULL },
3267};
3268
3269static struct info_10gbt_phy_fw *find_phy_info(int devid)
3270{
3271 int i;
3272
3273 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3274 if (phy_info_array[i].phy_fw_id == devid)
3275 return &phy_info_array[i];
3276 }
3277 return NULL;
3278}
3279
3280/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3281 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3282 * we return a negative error number. If we transfer new firmware we return 1
3283 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3284 */
3285static int adap_init0_phy(struct adapter *adap)
3286{
3287 const struct firmware *phyf;
3288 int ret;
3289 struct info_10gbt_phy_fw *phy_info;
3290
3291 /* Use the device ID to determine which PHY file to flash.
3292 */
3293 phy_info = find_phy_info(adap->pdev->device);
3294 if (!phy_info) {
3295 dev_warn(adap->pdev_dev,
3296 "No PHY Firmware file found for this PHY\n");
3297 return -EOPNOTSUPP;
3298 }
3299
3300 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3301 * use that. The adapter firmware provides us with a memory buffer
3302 * where we can load a PHY firmware file from the host if we want to
3303 * override the PHY firmware File in flash.
3304 */
3305 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3306 adap->pdev_dev);
3307 if (ret < 0) {
3308 /* For adapters without FLASH attached to PHY for their
3309 * firmware, it's obviously a fatal error if we can't get the
3310 * firmware to the adapter. For adapters with PHY firmware
3311 * FLASH storage, it's worth a warning if we can't find the
3312 * PHY Firmware but we'll neuter the error ...
3313 */
3314 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3315 "/lib/firmware/%s, error %d\n",
3316 phy_info->phy_fw_file, -ret);
3317 if (phy_info->phy_flash) {
3318 int cur_phy_fw_ver = 0;
3319
3320 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3321 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3322 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3323 ret = 0;
3324 }
3325
3326 return ret;
3327 }
3328
3329 /* Load PHY Firmware onto adapter.
3330 */
3331 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3332 phy_info->phy_fw_version,
3333 (u8 *)phyf->data, phyf->size);
3334 if (ret < 0)
3335 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3336 -ret);
3337 else if (ret > 0) {
3338 int new_phy_fw_ver = 0;
3339
3340 if (phy_info->phy_fw_version)
3341 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3342 phyf->size);
3343 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3344 "Firmware /lib/firmware/%s, version %#x\n",
3345 phy_info->phy_fw_file, new_phy_fw_ver);
3346 }
3347
3348 release_firmware(phyf);
3349
3350 return ret;
3351}
3352
636f9d37
VP		 3353/*
3354 * Attempt to initialize the adapter via a Firmware Configuration File.
3355 */
3356static int adap_init0_config(struct adapter *adapter, int reset)
3357{
3358 struct fw_caps_config_cmd caps_cmd;
3359 const struct firmware *cf;
3360 unsigned long mtype = 0, maddr = 0;
3361 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3362 int ret;
3363 int config_issued = 0;
0a57a536 3364 char *fw_config_file, fw_config_file_path[256];
16e47624 3365 char *config_name = NULL;
636f9d37
VP		 3366
3367 /*
3368 * Reset device if necessary.
3369 */
3370 if (reset) {
3371 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3372 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3373 if (ret < 0)
3374 goto bye;
3375 }
3376
01b69614
HS		 3377 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3378 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3379 * to be performed after any global adapter RESET above since some
3380 * PHYs only have local RAM copies of the PHY firmware.
3381 */
3382 if (is_10gbt_device(adapter->pdev->device)) {
3383 ret = adap_init0_phy(adapter);
3384 if (ret < 0)
3385 goto bye;
3386 }
636f9d37
VP		 3387 /*
3388 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3389 * then use that. Otherwise, use the configuration file stored
3390 * in the adapter flash ...
3391 */
d14807dd 3392 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3393 case CHELSIO_T4:
16e47624 3394 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3395 break;
3396 case CHELSIO_T5:
3397 fw_config_file = FW5_CFNAME;
3398 break;
3ccc6cf7
HS		 3399 case CHELSIO_T6:
3400 fw_config_file = FW6_CFNAME;
3401 break;
0a57a536
SR		 3402 default:
3403 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3404 adapter->pdev->device);
3405 ret = -EINVAL;
3406 goto bye;
3407 }
3408
3409 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3410 if (ret < 0) {
16e47624 3411 config_name = "On FLASH";
636f9d37
VP		 3412 mtype = FW_MEMTYPE_CF_FLASH;
3413 maddr = t4_flash_cfg_addr(adapter);
3414 } else {
3415 u32 params[7], val[7];
3416
16e47624
HS		 3417 sprintf(fw_config_file_path,
3418 "/lib/firmware/%s", fw_config_file);
3419 config_name = fw_config_file_path;
3420
636f9d37
VP		 3421 if (cf->size >= FLASH_CFG_MAX_SIZE)
3422 ret = -ENOMEM;
3423 else {
5167865a
HS		 3424 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3425 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 3426 ret = t4_query_params(adapter, adapter->mbox,
b2612722 3427 adapter->pf, 0, 1, params, val);
636f9d37
VP		 3428 if (ret == 0) {
3429 /*
fc5ab020 3430 * For t4_memory_rw() below addresses and
636f9d37
VP		 3431 * sizes have to be in terms of multiples of 4
3432 * bytes. So, if the Configuration File isn't
3433 * a multiple of 4 bytes in length we'll have
3434 * to write that out separately since we can't
3435 * guarantee that the bytes following the
3436 * residual byte in the buffer returned by
3437 * request_firmware() are zeroed out ...
3438 */
3439 size_t resid = cf->size & 0x3;
3440 size_t size = cf->size & ~0x3;
3441 __be32 *data = (__be32 *)cf->data;
3442
5167865a
HS		 3443 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3444 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3445
fc5ab020
HS		 3446 spin_lock(&adapter->win0_lock);
3447 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3448 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3449 if (ret == 0 && resid != 0) {
3450 union {
3451 __be32 word;
3452 char buf[4];
3453 } last;
3454 int i;
3455
3456 last.word = data[size >> 2];
3457 for (i = resid; i < 4; i++)
3458 last.buf[i] = 0;
fc5ab020
HS		 3459 ret = t4_memory_rw(adapter, 0, mtype,
3460 maddr + size,
3461 4, &last.word,
3462 T4_MEMORY_WRITE);
636f9d37 3463 }
fc5ab020 3464 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3465 }
3466 }
3467
3468 release_firmware(cf);
3469 if (ret)
3470 goto bye;
3471 }
3472
3473 /*
3474 * Issue a Capability Configuration command to the firmware to get it
3475 * to parse the Configuration File. We don't use t4_fw_config_file()
3476 * because we want the ability to modify various features after we've
3477 * processed the configuration file ...
3478 */
3479 memset(&caps_cmd, 0, sizeof(caps_cmd));
3480 caps_cmd.op_to_write =
e2ac9628
HS		 3481 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3482 FW_CMD_REQUEST_F |
3483 FW_CMD_READ_F);
ce91a923 3484 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3485 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3486 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3487 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3488 FW_LEN16(caps_cmd));
3489 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3490 &caps_cmd);
16e47624
HS		 3491
3492 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3493 * Configuration File in FLASH), our last gasp effort is to use the
3494 * Firmware Configuration File which is embedded in the firmware. A
3495 * very few early versions of the firmware didn't have one embedded
3496 * but we can ignore those.
3497 */
3498 if (ret == -ENOENT) {
3499 memset(&caps_cmd, 0, sizeof(caps_cmd));
3500 caps_cmd.op_to_write =
e2ac9628
HS		 3501 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3502 FW_CMD_REQUEST_F |
3503 FW_CMD_READ_F);
16e47624
HS		 3504 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3505 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3506 sizeof(caps_cmd), &caps_cmd);
3507 config_name = "Firmware Default";
3508 }
3509
3510 config_issued = 1;
636f9d37
VP		 3511 if (ret < 0)
3512 goto bye;
3513
3514 finiver = ntohl(caps_cmd.finiver);
3515 finicsum = ntohl(caps_cmd.finicsum);
3516 cfcsum = ntohl(caps_cmd.cfcsum);
3517 if (finicsum != cfcsum)
3518 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3519 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3520 finicsum, cfcsum);
3521
636f9d37
VP		 3522 /*
3523 * And now tell the firmware to use the configuration we just loaded.
3524 */
3525 caps_cmd.op_to_write =
e2ac9628
HS		 3526 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3527 FW_CMD_REQUEST_F |
3528 FW_CMD_WRITE_F);
ce91a923 3529 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3530 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3531 NULL);
3532 if (ret < 0)
3533 goto bye;
3534
3535 /*
3536 * Tweak configuration based on system architecture, module
3537 * parameters, etc.
3538 */
3539 ret = adap_init0_tweaks(adapter);
3540 if (ret < 0)
3541 goto bye;
3542
3543 /*
3544 * And finally tell the firmware to initialize itself using the
3545 * parameters from the Configuration File.
3546 */
3547 ret = t4_fw_initialize(adapter, adapter->mbox);
3548 if (ret < 0)
3549 goto bye;
3550
06640310
HS		 3551 /* Emit Firmware Configuration File information and return
3552 * successfully.
636f9d37 3553 */
636f9d37 3554 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 3555 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3556 config_name, finiver, cfcsum);
636f9d37
VP		 3557 return 0;
3558
3559 /*
3560 * Something bad happened. Return the error ... (If the "error"
3561 * is that there's no Configuration File on the adapter we don't
3562 * want to issue a warning since this is fairly common.)
3563 */
3564bye:
16e47624
HS		 3565 if (config_issued && ret != -ENOENT)
3566 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3567 config_name, -ret);
636f9d37
VP		 3568 return ret;
3569}
3570
16e47624
HS		 3571static struct fw_info fw_info_array[] = {
3572 {
3573 .chip = CHELSIO_T4,
3574 .fs_name = FW4_CFNAME,
3575 .fw_mod_name = FW4_FNAME,
3576 .fw_hdr = {
3577 .chip = FW_HDR_CHIP_T4,
3578 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3579 .intfver_nic = FW_INTFVER(T4, NIC),
3580 .intfver_vnic = FW_INTFVER(T4, VNIC),
3581 .intfver_ri = FW_INTFVER(T4, RI),
3582 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3583 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3584 },
3585 }, {
3586 .chip = CHELSIO_T5,
3587 .fs_name = FW5_CFNAME,
3588 .fw_mod_name = FW5_FNAME,
3589 .fw_hdr = {
3590 .chip = FW_HDR_CHIP_T5,
3591 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3592 .intfver_nic = FW_INTFVER(T5, NIC),
3593 .intfver_vnic = FW_INTFVER(T5, VNIC),
3594 .intfver_ri = FW_INTFVER(T5, RI),
3595 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3596 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3597 },
3ccc6cf7
HS		 3598 }, {
3599 .chip = CHELSIO_T6,
3600 .fs_name = FW6_CFNAME,
3601 .fw_mod_name = FW6_FNAME,
3602 .fw_hdr = {
3603 .chip = FW_HDR_CHIP_T6,
3604 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3605 .intfver_nic = FW_INTFVER(T6, NIC),
3606 .intfver_vnic = FW_INTFVER(T6, VNIC),
3607 .intfver_ofld = FW_INTFVER(T6, OFLD),
3608 .intfver_ri = FW_INTFVER(T6, RI),
3609 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3610 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3611 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3612 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3613 },
16e47624 3614 }
3ccc6cf7 3615
16e47624
HS		 3616};
3617
3618static struct fw_info *find_fw_info(int chip)
3619{
3620 int i;
3621
3622 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3623 if (fw_info_array[i].chip == chip)
3624 return &fw_info_array[i];
3625 }
3626 return NULL;
3627}
3628
b8ff05a9
DM		 3629/*
3630 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3631 */
3632static int adap_init0(struct adapter *adap)
3633{
3634 int ret;
3635 u32 v, port_vec;
3636 enum dev_state state;
3637 u32 params[7], val[7];
9a4da2cd 3638 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 3639 int reset = 1;
b8ff05a9 3640
ae469b68
HS		 3641 /* Grab Firmware Device Log parameters as early as possible so we have
3642 * access to it for debugging, etc.
3643 */
3644 ret = t4_init_devlog_params(adap);
3645 if (ret < 0)
3646 return ret;
3647
666224d4
HS		 3648 /* Contact FW, advertising Master capability */
3649 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
b8ff05a9
DM		 3650 if (ret < 0) {
3651 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3652 ret);
3653 return ret;
3654 }
636f9d37
VP		 3655 if (ret == adap->mbox)
3656 adap->flags |= MASTER_PF;
b8ff05a9 3657
636f9d37
VP		 3658 /*
3659 * If we're the Master PF Driver and the device is uninitialized,
3660 * then let's consider upgrading the firmware ... (We always want
3661 * to check the firmware version number in order to A. get it for
3662 * later reporting and B. to warn if the currently loaded firmware
3663 * is excessively mismatched relative to the driver.)
3664 */
16e47624
HS		 3665 t4_get_fw_version(adap, &adap->params.fw_vers);
3666 t4_get_tp_version(adap, &adap->params.tp_vers);
a69265e9
HS		 3667 ret = t4_check_fw_version(adap);
3668 /* If firmware is too old (not supported by driver) force an update. */
21d11bd6 3669 if (ret)
a69265e9 3670 state = DEV_STATE_UNINIT;
636f9d37 3671 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 3672 struct fw_info *fw_info;
3673 struct fw_hdr *card_fw;
3674 const struct firmware *fw;
3675 const u8 *fw_data = NULL;
3676 unsigned int fw_size = 0;
3677
3678 /* This is the firmware whose headers the driver was compiled
3679 * against
3680 */
3681 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3682 if (fw_info == NULL) {
3683 dev_err(adap->pdev_dev,
3684 "unable to get firmware info for chip %d.\n",
3685 CHELSIO_CHIP_VERSION(adap->params.chip));
3686 return -EINVAL;
636f9d37 3687 }
16e47624
HS		 3688
3689 /* allocate memory to read the header of the firmware on the
3690 * card
3691 */
3692 card_fw = t4_alloc_mem(sizeof(*card_fw));
3693
3694 /* Get FW from from /lib/firmware/ */
3695 ret = request_firmware(&fw, fw_info->fw_mod_name,
3696 adap->pdev_dev);
3697 if (ret < 0) {
3698 dev_err(adap->pdev_dev,
3699 "unable to load firmware image %s, error %d\n",
3700 fw_info->fw_mod_name, ret);
3701 } else {
3702 fw_data = fw->data;
3703 fw_size = fw->size;
3704 }
3705
3706 /* upgrade FW logic */
3707 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3708 state, &reset);
3709
3710 /* Cleaning up */
0b5b6bee 3711 release_firmware(fw);
16e47624
HS		 3712 t4_free_mem(card_fw);
3713
636f9d37 3714 if (ret < 0)
16e47624 3715 goto bye;
636f9d37 3716 }
b8ff05a9 3717
636f9d37
VP		 3718 /*
3719 * Grab VPD parameters. This should be done after we establish a
3720 * connection to the firmware since some of the VPD parameters
3721 * (notably the Core Clock frequency) are retrieved via requests to
3722 * the firmware. On the other hand, we need these fairly early on
3723 * so we do this right after getting ahold of the firmware.
3724 */
098ef6c2 3725 ret = t4_get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 3726 if (ret < 0)
3727 goto bye;
a0881cab 3728
636f9d37 3729 /*
13ee15d3
VP		 3730 * Find out what ports are available to us. Note that we need to do
3731 * this before calling adap_init0_no_config() since it needs nports
3732 * and portvec ...
636f9d37
VP		 3733 */
3734 v =
5167865a
HS		 3735 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3736 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
b2612722 3737 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
a0881cab
DM		 3738 if (ret < 0)
3739 goto bye;
3740
636f9d37
VP		 3741 adap->params.nports = hweight32(port_vec);
3742 adap->params.portvec = port_vec;
3743
06640310
HS		 3744 /* If the firmware is initialized already, emit a simply note to that
3745 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 3746 */
3747 if (state == DEV_STATE_INIT) {
3748 dev_info(adap->pdev_dev, "Coming up as %s: "\
3749 "Adapter already initialized\n",
3750 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 3751 } else {
3752 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3753 "Initializing adapter\n");
06640310
HS		 3754
3755 /* Find out whether we're dealing with a version of the
3756 * firmware which has configuration file support.
636f9d37 3757 */
06640310
HS		 3758 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3759 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 3760 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 3761 params, val);
13ee15d3 3762
06640310
HS		 3763 /* If the firmware doesn't support Configuration Files,
3764 * return an error.
3765 */
3766 if (ret < 0) {
3767 dev_err(adap->pdev_dev, "firmware doesn't support "
3768 "Firmware Configuration Files\n");
3769 goto bye;
3770 }
3771
3772 /* The firmware provides us with a memory buffer where we can
3773 * load a Configuration File from the host if we want to
3774 * override the Configuration File in flash.
3775 */
3776 ret = adap_init0_config(adap, reset);
3777 if (ret == -ENOENT) {
3778 dev_err(adap->pdev_dev, "no Configuration File "
3779 "present on adapter.\n");
3780 goto bye;
636f9d37
VP		 3781 }
3782 if (ret < 0) {
06640310
HS		 3783 dev_err(adap->pdev_dev, "could not initialize "
3784 "adapter, error %d\n", -ret);
636f9d37
VP		 3785 goto bye;
3786 }
3787 }
3788
06640310
HS		 3789 /* Give the SGE code a chance to pull in anything that it needs ...
3790 * Note that this must be called after we retrieve our VPD parameters
3791 * in order to know how to convert core ticks to seconds, etc.
636f9d37 3792 */
06640310
HS		 3793 ret = t4_sge_init(adap);
3794 if (ret < 0)
3795 goto bye;
636f9d37 3796
9a4da2cd
VP		 3797 if (is_bypass_device(adap->pdev->device))
3798 adap->params.bypass = 1;
3799
636f9d37
VP		 3800 /*
3801 * Grab some of our basic fundamental operating parameters.
3802 */
3803#define FW_PARAM_DEV(param) \
5167865a
HS		 3804 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3805 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 3806
b8ff05a9 3807#define FW_PARAM_PFVF(param) \
5167865a
HS		 3808 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3809 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3810 FW_PARAMS_PARAM_Y_V(0) | \
3811 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 3812
636f9d37 3813 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 3814 params[1] = FW_PARAM_PFVF(L2T_START);
3815 params[2] = FW_PARAM_PFVF(L2T_END);
3816 params[3] = FW_PARAM_PFVF(FILTER_START);
3817 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 3818 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 3819 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 3820 if (ret < 0)
3821 goto bye;
636f9d37
VP		 3822 adap->sge.egr_start = val[0];
3823 adap->l2t_start = val[1];
3824 adap->l2t_end = val[2];
b8ff05a9
DM		 3825 adap->tids.ftid_base = val[3];
3826 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 3827 adap->sge.ingr_start = val[5];
b8ff05a9 3828
4b8e27a8
HS		 3829 /* qids (ingress/egress) returned from firmware can be anywhere
3830 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3831 * Hence driver needs to allocate memory for this range to
3832 * store the queue info. Get the highest IQFLINT/EQ index returned
3833 * in FW_EQ_*_CMD.alloc command.
3834 */
3835 params[0] = FW_PARAM_PFVF(EQ_END);
3836 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 3837 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 3838 if (ret < 0)
3839 goto bye;
3840 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3841 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3842
3843 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3844 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3845 if (!adap->sge.egr_map) {
3846 ret = -ENOMEM;
3847 goto bye;
3848 }
3849
3850 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3851 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3852 if (!adap->sge.ingr_map) {
3853 ret = -ENOMEM;
3854 goto bye;
3855 }
3856
3857 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 3858 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 3859 */
3860 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3861 sizeof(long), GFP_KERNEL);
3862 if (!adap->sge.starving_fl) {
3863 ret = -ENOMEM;
3864 goto bye;
3865 }
3866
3867 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3868 sizeof(long), GFP_KERNEL);
3869 if (!adap->sge.txq_maperr) {
3870 ret = -ENOMEM;
3871 goto bye;
3872 }
3873
5b377d11
HS		 3874#ifdef CONFIG_DEBUG_FS
3875 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3876 sizeof(long), GFP_KERNEL);
3877 if (!adap->sge.blocked_fl) {
3878 ret = -ENOMEM;
3879 goto bye;
3880 }
3881#endif
3882
b5a02f50
AB		 3883 params[0] = FW_PARAM_PFVF(CLIP_START);
3884 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 3885 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 3886 if (ret < 0)
3887 goto bye;
3888 adap->clipt_start = val[0];
3889 adap->clipt_end = val[1];
3890
636f9d37
VP		 3891 /* query params related to active filter region */
3892 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3893 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 3894 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 3895 /* If Active filter size is set we enable establishing
3896 * offload connection through firmware work request
3897 */
3898 if ((val[0] != val[1]) && (ret >= 0)) {
3899 adap->flags |= FW_OFLD_CONN;
3900 adap->tids.aftid_base = val[0];
3901 adap->tids.aftid_end = val[1];
3902 }
3903
b407a4a9
VP		 3904 /* If we're running on newer firmware, let it know that we're
3905 * prepared to deal with encapsulated CPL messages. Older
3906 * firmware won't understand this and we'll just get
3907 * unencapsulated messages ...
3908 */
3909 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3910 val[0] = 1;
b2612722 3911 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 3912
1ac0f095
KS		 3913 /*
3914 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3915 * capability. Earlier versions of the firmware didn't have the
3916 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3917 * permission to use ULPTX MEMWRITE DSGL.
3918 */
3919 if (is_t4(adap->params.chip)) {
3920 adap->params.ulptx_memwrite_dsgl = false;
3921 } else {
3922 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 3923 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 3924 1, params, val);
3925 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3926 }
3927
636f9d37
VP		 3928 /*
3929 * Get device capabilities so we can determine what resources we need
3930 * to manage.
3931 */
3932 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 3933 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3934 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3935 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3936 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3937 &caps_cmd);
3938 if (ret < 0)
3939 goto bye;
3940
13ee15d3 3941 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 3942 /* query offload-related parameters */
3943 params[0] = FW_PARAM_DEV(NTID);
3944 params[1] = FW_PARAM_PFVF(SERVER_START);
3945 params[2] = FW_PARAM_PFVF(SERVER_END);
3946 params[3] = FW_PARAM_PFVF(TDDP_START);
3947 params[4] = FW_PARAM_PFVF(TDDP_END);
3948 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 3949 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3950 params, val);
b8ff05a9
DM		 3951 if (ret < 0)
3952 goto bye;
3953 adap->tids.ntids = val[0];
3954 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3955 adap->tids.stid_base = val[1];
3956 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 3957 /*
dbedd44e 3958 * Setup server filter region. Divide the available filter
636f9d37
VP		 3959 * region into two parts. Regular filters get 1/3rd and server
3960 * filters get 2/3rd part. This is only enabled if workarond
3961 * path is enabled.
3962 * 1. For regular filters.
3963 * 2. Server filter: This are special filters which are used
3964 * to redirect SYN packets to offload queue.
3965 */
3966 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3967 adap->tids.sftid_base = adap->tids.ftid_base +
3968 DIV_ROUND_UP(adap->tids.nftids, 3);
3969 adap->tids.nsftids = adap->tids.nftids -
3970 DIV_ROUND_UP(adap->tids.nftids, 3);
3971 adap->tids.nftids = adap->tids.sftid_base -
3972 adap->tids.ftid_base;
3973 }
b8ff05a9
DM		 3974 adap->vres.ddp.start = val[3];
3975 adap->vres.ddp.size = val[4] - val[3] + 1;
3976 adap->params.ofldq_wr_cred = val[5];
636f9d37 3977
b8ff05a9
DM		 3978 adap->params.offload = 1;
3979 }
636f9d37 3980 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 3981 params[0] = FW_PARAM_PFVF(STAG_START);
3982 params[1] = FW_PARAM_PFVF(STAG_END);
3983 params[2] = FW_PARAM_PFVF(RQ_START);
3984 params[3] = FW_PARAM_PFVF(RQ_END);
3985 params[4] = FW_PARAM_PFVF(PBL_START);
3986 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 3987 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3988 params, val);
b8ff05a9
DM		 3989 if (ret < 0)
3990 goto bye;
3991 adap->vres.stag.start = val[0];
3992 adap->vres.stag.size = val[1] - val[0] + 1;
3993 adap->vres.rq.start = val[2];
3994 adap->vres.rq.size = val[3] - val[2] + 1;
3995 adap->vres.pbl.start = val[4];
3996 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 3997
3998 params[0] = FW_PARAM_PFVF(SQRQ_START);
3999 params[1] = FW_PARAM_PFVF(SQRQ_END);
4000 params[2] = FW_PARAM_PFVF(CQ_START);
4001 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 4002 params[4] = FW_PARAM_PFVF(OCQ_START);
4003 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 4004 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 4005 val);
a0881cab
DM		 4006 if (ret < 0)
4007 goto bye;
4008 adap->vres.qp.start = val[0];
4009 adap->vres.qp.size = val[1] - val[0] + 1;
4010 adap->vres.cq.start = val[2];
4011 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 4012 adap->vres.ocq.start = val[4];
4013 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 4014
4015 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4016 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 4017 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 4018 val);
4c2c5763
HS		 4019 if (ret < 0) {
4020 adap->params.max_ordird_qp = 8;
4021 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4022 ret = 0;
4023 } else {
4024 adap->params.max_ordird_qp = val[0];
4025 adap->params.max_ird_adapter = val[1];
4026 }
4027 dev_info(adap->pdev_dev,
4028 "max_ordird_qp %d max_ird_adapter %d\n",
4029 adap->params.max_ordird_qp,
4030 adap->params.max_ird_adapter);
b8ff05a9 4031 }
636f9d37 4032 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4033 params[0] = FW_PARAM_PFVF(ISCSI_START);
4034 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4035 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4036 params, val);
b8ff05a9
DM		 4037 if (ret < 0)
4038 goto bye;
4039 adap->vres.iscsi.start = val[0];
4040 adap->vres.iscsi.size = val[1] - val[0] + 1;
4041 }
4042#undef FW_PARAM_PFVF
4043#undef FW_PARAM_DEV
4044
92e7ae71
HS		 4045 /* The MTU/MSS Table is initialized by now, so load their values. If
4046 * we're initializing the adapter, then we'll make any modifications
4047 * we want to the MTU/MSS Table and also initialize the congestion
4048 * parameters.
636f9d37 4049 */
b8ff05a9 4050 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4051 if (state != DEV_STATE_INIT) {
4052 int i;
4053
4054 /* The default MTU Table contains values 1492 and 1500.
4055 * However, for TCP, it's better to have two values which are
4056 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4057 * This allows us to have a TCP Data Payload which is a
4058 * multiple of 8 regardless of what combination of TCP Options
4059 * are in use (always a multiple of 4 bytes) which is
4060 * important for performance reasons. For instance, if no
4061 * options are in use, then we have a 20-byte IP header and a
4062 * 20-byte TCP header. In this case, a 1500-byte MSS would
4063 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4064 * which is not a multiple of 8. So using an MSS of 1488 in
4065 * this case results in a TCP Data Payload of 1448 bytes which
4066 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4067 * Stamps have been negotiated, then an MTU of 1500 bytes
4068 * results in a TCP Data Payload of 1448 bytes which, as
4069 * above, is a multiple of 8 bytes ...
4070 */
4071 for (i = 0; i < NMTUS; i++)
4072 if (adap->params.mtus[i] == 1492) {
4073 adap->params.mtus[i] = 1488;
4074 break;
4075 }
7ee9ff94 4076
92e7ae71
HS		 4077 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4078 adap->params.b_wnd);
4079 }
df64e4d3 4080 t4_init_sge_params(adap);
636f9d37 4081 adap->flags |= FW_OK;
c1e9af0c 4082 t4_init_tp_params(adap);
b8ff05a9
DM		 4083 return 0;
4084
4085 /*
636f9d37
VP		 4086 * Something bad happened. If a command timed out or failed with EIO
4087 * FW does not operate within its spec or something catastrophic
4088 * happened to HW/FW, stop issuing commands.
b8ff05a9 4089 */
636f9d37 4090bye:
4b8e27a8
HS		 4091 kfree(adap->sge.egr_map);
4092 kfree(adap->sge.ingr_map);
4093 kfree(adap->sge.starving_fl);
4094 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4095#ifdef CONFIG_DEBUG_FS
4096 kfree(adap->sge.blocked_fl);
4097#endif
636f9d37
VP		 4098 if (ret != -ETIMEDOUT && ret != -EIO)
4099 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4100 return ret;
4101}
4102
204dc3c0
DM		 4103/* EEH callbacks */
4104
4105static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4106 pci_channel_state_t state)
4107{
4108 int i;
4109 struct adapter *adap = pci_get_drvdata(pdev);
4110
4111 if (!adap)
4112 goto out;
4113
4114 rtnl_lock();
4115 adap->flags &= ~FW_OK;
4116 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4117 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4118 for_each_port(adap, i) {
4119 struct net_device *dev = adap->port[i];
4120
4121 netif_device_detach(dev);
4122 netif_carrier_off(dev);
4123 }
9fe6cb58 4124 spin_unlock(&adap->stats_lock);
b37987e8 4125 disable_interrupts(adap);
204dc3c0
DM		 4126 if (adap->flags & FULL_INIT_DONE)
4127 cxgb_down(adap);
4128 rtnl_unlock();
144be3d9
GS		 4129 if ((adap->flags & DEV_ENABLED)) {
4130 pci_disable_device(pdev);
4131 adap->flags &= ~DEV_ENABLED;
4132 }
204dc3c0
DM		 4133out: return state == pci_channel_io_perm_failure ?
4134 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4135}
4136
4137static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4138{
4139 int i, ret;
4140 struct fw_caps_config_cmd c;
4141 struct adapter *adap = pci_get_drvdata(pdev);
4142
4143 if (!adap) {
4144 pci_restore_state(pdev);
4145 pci_save_state(pdev);
4146 return PCI_ERS_RESULT_RECOVERED;
4147 }
4148
144be3d9
GS		 4149 if (!(adap->flags & DEV_ENABLED)) {
4150 if (pci_enable_device(pdev)) {
4151 dev_err(&pdev->dev, "Cannot reenable PCI "
4152 "device after reset\n");
4153 return PCI_ERS_RESULT_DISCONNECT;
4154 }
4155 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4156 }
4157
4158 pci_set_master(pdev);
4159 pci_restore_state(pdev);
4160 pci_save_state(pdev);
4161 pci_cleanup_aer_uncorrect_error_status(pdev);
4162
8203b509 4163 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4164 return PCI_ERS_RESULT_DISCONNECT;
b2612722 4165 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4166 return PCI_ERS_RESULT_DISCONNECT;
4167 adap->flags |= FW_OK;
4168 if (adap_init1(adap, &c))
4169 return PCI_ERS_RESULT_DISCONNECT;
4170
4171 for_each_port(adap, i) {
4172 struct port_info *p = adap2pinfo(adap, i);
4173
b2612722 4174 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
060e0c75 4175 NULL, NULL);
204dc3c0
DM		 4176 if (ret < 0)
4177 return PCI_ERS_RESULT_DISCONNECT;
4178 p->viid = ret;
4179 p->xact_addr_filt = -1;
4180 }
4181
4182 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4183 adap->params.b_wnd);
1ae970e0 4184 setup_memwin(adap);
204dc3c0
DM		 4185 if (cxgb_up(adap))
4186 return PCI_ERS_RESULT_DISCONNECT;
4187 return PCI_ERS_RESULT_RECOVERED;
4188}
4189
4190static void eeh_resume(struct pci_dev *pdev)
4191{
4192 int i;
4193 struct adapter *adap = pci_get_drvdata(pdev);
4194
4195 if (!adap)
4196 return;
4197
4198 rtnl_lock();
4199 for_each_port(adap, i) {
4200 struct net_device *dev = adap->port[i];
4201
4202 if (netif_running(dev)) {
4203 link_start(dev);
4204 cxgb_set_rxmode(dev);
4205 }
4206 netif_device_attach(dev);
4207 }
4208 rtnl_unlock();
4209}
4210
3646f0e5 4211static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4212 .error_detected = eeh_err_detected,
4213 .slot_reset = eeh_slot_reset,
4214 .resume = eeh_resume,
4215};
4216
57d8b764 4217static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4218{
57d8b764
KS		 4219 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4220 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 4221}
4222
c887ad0e
HS		 4223static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4224 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 4225 unsigned int size, unsigned int iqe_size)
4226{
c887ad0e 4227 q->adap = adap;
812034f1 4228 cxgb4_set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 4229 q->iqe_len = iqe_size;
4230 q->size = size;
4231}
4232
4233/*
4234 * Perform default configuration of DMA queues depending on the number and type
4235 * of ports we found and the number of available CPUs. Most settings can be
4236 * modified by the admin prior to actual use.
4237 */
91744948 4238static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4239{
4240 struct sge *s = &adap->sge;
688848b1
AB		 4241 int i, n10g = 0, qidx = 0;
4242#ifndef CONFIG_CHELSIO_T4_DCB
4243 int q10g = 0;
4244#endif
cf38be6d 4245 int ciq_size;
b8ff05a9
DM		 4246
4247 for_each_port(adap, i)
57d8b764 4248 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 4249#ifdef CONFIG_CHELSIO_T4_DCB
4250 /* For Data Center Bridging support we need to be able to support up
4251 * to 8 Traffic Priorities; each of which will be assigned to its
4252 * own TX Queue in order to prevent Head-Of-Line Blocking.
4253 */
4254 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4255 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4256 MAX_ETH_QSETS, adap->params.nports * 8);
4257 BUG_ON(1);
4258 }
b8ff05a9 4259
688848b1
AB		 4260 for_each_port(adap, i) {
4261 struct port_info *pi = adap2pinfo(adap, i);
4262
4263 pi->first_qset = qidx;
4264 pi->nqsets = 8;
4265 qidx += pi->nqsets;
4266 }
4267#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4268 /*
4269 * We default to 1 queue per non-10G port and up to # of cores queues
4270 * per 10G port.
4271 */
4272 if (n10g)
4273 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4274 if (q10g > netif_get_num_default_rss_queues())
4275 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 4276
4277 for_each_port(adap, i) {
4278 struct port_info *pi = adap2pinfo(adap, i);
4279
4280 pi->first_qset = qidx;
57d8b764 4281 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4282 qidx += pi->nqsets;
4283 }
688848b1 4284#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4285
4286 s->ethqsets = qidx;
4287 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4288
4289 if (is_offload(adap)) {
4290 /*
4291 * For offload we use 1 queue/channel if all ports are up to 1G,
4292 * otherwise we divide all available queues amongst the channels
4293 * capped by the number of available cores.
4294 */
4295 if (n10g) {
f90ce561 4296 i = min_t(int, ARRAY_SIZE(s->iscsirxq),
b8ff05a9 4297 num_online_cpus());
f90ce561 4298 s->iscsiqsets = roundup(i, adap->params.nports);
b8ff05a9 4299 } else
f90ce561 4300 s->iscsiqsets = adap->params.nports;
b8ff05a9
DM		 4301 /* For RDMA one Rx queue per channel suffices */
4302 s->rdmaqs = adap->params.nports;
f36e58e5
HS		 4303 /* Try and allow at least 1 CIQ per cpu rounding down
4304 * to the number of ports, with a minimum of 1 per port.
4305 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4306 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4307 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4308 */
4309 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4310 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4311 adap->params.nports;
4312 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
b8ff05a9
DM		 4313 }
4314
4315 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4316 struct sge_eth_rxq *r = &s->ethrxq[i];
4317
c887ad0e 4318 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4319 r->fl.size = 72;
4320 }
4321
4322 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4323 s->ethtxq[i].q.size = 1024;
4324
4325 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4326 s->ctrlq[i].q.size = 512;
4327
4328 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4329 s->ofldtxq[i].q.size = 1024;
4330
f90ce561
HS		 4331 for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) {
4332 struct sge_ofld_rxq *r = &s->iscsirxq[i];
b8ff05a9 4333
c887ad0e 4334 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 4335 r->rspq.uld = CXGB4_ULD_ISCSI;
4336 r->fl.size = 72;
4337 }
4338
4339 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4340 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4341
c887ad0e 4342 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 4343 r->rspq.uld = CXGB4_ULD_RDMA;
4344 r->fl.size = 72;
4345 }
4346
cf38be6d
HS		 4347 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4348 if (ciq_size > SGE_MAX_IQ_SIZE) {
4349 CH_WARN(adap, "CIQ size too small for available IQs\n");
4350 ciq_size = SGE_MAX_IQ_SIZE;
4351 }
4352
4353 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4354 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4355
c887ad0e 4356 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 4357 r->rspq.uld = CXGB4_ULD_RDMA;
4358 }
4359
c887ad0e
HS		 4360 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4361 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 4362}
4363
4364/*
4365 * Reduce the number of Ethernet queues across all ports to at most n.
4366 * n provides at least one queue per port.
4367 */
91744948 4368static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4369{
4370 int i;
4371 struct port_info *pi;
4372
4373 while (n < adap->sge.ethqsets)
4374 for_each_port(adap, i) {
4375 pi = adap2pinfo(adap, i);
4376 if (pi->nqsets > 1) {
4377 pi->nqsets--;
4378 adap->sge.ethqsets--;
4379 if (adap->sge.ethqsets <= n)
4380 break;
4381 }
4382 }
4383
4384 n = 0;
4385 for_each_port(adap, i) {
4386 pi = adap2pinfo(adap, i);
4387 pi->first_qset = n;
4388 n += pi->nqsets;
4389 }
4390}
4391
4392/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4393#define EXTRA_VECS 2
4394
91744948 4395static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 4396{
4397 int ofld_need = 0;
f36e58e5 4398 int i, want, need, allocated;
b8ff05a9
DM		 4399 struct sge *s = &adap->sge;
4400 unsigned int nchan = adap->params.nports;
f36e58e5
HS		 4401 struct msix_entry *entries;
4402
4403 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4404 GFP_KERNEL);
4405 if (!entries)
4406 return -ENOMEM;
b8ff05a9 4407
f36e58e5 4408 for (i = 0; i < MAX_INGQ + 1; ++i)
b8ff05a9
DM		 4409 entries[i].entry = i;
4410
4411 want = s->max_ethqsets + EXTRA_VECS;
4412 if (is_offload(adap)) {
f90ce561 4413 want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets;
b8ff05a9 4414 /* need nchan for each possible ULD */
cf38be6d 4415 ofld_need = 3 * nchan;
b8ff05a9 4416 }
688848b1
AB		 4417#ifdef CONFIG_CHELSIO_T4_DCB
4418 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4419 * each port.
4420 */
4421 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4422#else
b8ff05a9 4423 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 4424#endif
f36e58e5
HS		 4425 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4426 if (allocated < 0) {
4427 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4428 " not using MSI-X\n");
4429 kfree(entries);
4430 return allocated;
4431 }
b8ff05a9 4432
f36e58e5 4433 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 4434 * Every group gets its minimum requirement and NIC gets top
4435 * priority for leftovers.
4436 */
f36e58e5 4437 i = allocated - EXTRA_VECS - ofld_need;
c32ad224
AG		 4438 if (i < s->max_ethqsets) {
4439 s->max_ethqsets = i;
4440 if (i < s->ethqsets)
4441 reduce_ethqs(adap, i);
4442 }
4443 if (is_offload(adap)) {
f36e58e5
HS		 4444 if (allocated < want) {
4445 s->rdmaqs = nchan;
4446 s->rdmaciqs = nchan;
4447 }
4448
4449 /* leftovers go to OFLD */
4450 i = allocated - EXTRA_VECS - s->max_ethqsets -
4451 s->rdmaqs - s->rdmaciqs;
f90ce561 4452 s->iscsiqsets = (i / nchan) * nchan; /* round down */
c32ad224 4453 }
f36e58e5 4454 for (i = 0; i < allocated; ++i)
c32ad224 4455 adap->msix_info[i].vec = entries[i].vector;
43eb4e82
HS		 4456 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4457 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
f90ce561 4458 allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs,
43eb4e82 4459 s->rdmaciqs);
c32ad224 4460
f36e58e5 4461 kfree(entries);
c32ad224 4462 return 0;
b8ff05a9
DM		 4463}
4464
4465#undef EXTRA_VECS
4466
91744948 4467static int init_rss(struct adapter *adap)
671b0060 4468{
c035e183
HS		 4469 unsigned int i;
4470 int err;
4471
4472 err = t4_init_rss_mode(adap, adap->mbox);
4473 if (err)
4474 return err;
671b0060
DM		 4475
4476 for_each_port(adap, i) {
4477 struct port_info *pi = adap2pinfo(adap, i);
4478
4479 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4480 if (!pi->rss)
4481 return -ENOMEM;
671b0060
DM		 4482 }
4483 return 0;
4484}
4485
547fd272
HS		 4486static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4487 enum pci_bus_speed *speed,
4488 enum pcie_link_width *width)
4489{
4490 u32 lnkcap1, lnkcap2;
4491 int err1, err2;
4492
4493#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
4494
4495 *speed = PCI_SPEED_UNKNOWN;
4496 *width = PCIE_LNK_WIDTH_UNKNOWN;
4497
4498 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4499 &lnkcap1);
4500 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4501 &lnkcap2);
4502 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4503 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4504 *speed = PCIE_SPEED_8_0GT;
4505 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4506 *speed = PCIE_SPEED_5_0GT;
4507 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4508 *speed = PCIE_SPEED_2_5GT;
4509 }
4510 if (!err1) {
4511 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4512 if (!lnkcap2) { /* pre-r3.0 */
4513 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4514 *speed = PCIE_SPEED_5_0GT;
4515 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4516 *speed = PCIE_SPEED_2_5GT;
4517 }
4518 }
4519
4520 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4521 return err1 ? err1 : err2 ? err2 : -EINVAL;
4522 return 0;
4523}
4524
4525static void cxgb4_check_pcie_caps(struct adapter *adap)
4526{
4527 enum pcie_link_width width, width_cap;
4528 enum pci_bus_speed speed, speed_cap;
4529
4530#define PCIE_SPEED_STR(speed) \
4531 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4532 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4533 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4534 "Unknown")
4535
4536 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4537 dev_warn(adap->pdev_dev,
4538 "Unable to determine PCIe device BW capabilities\n");
4539 return;
4540 }
4541
4542 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4543 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4544 dev_warn(adap->pdev_dev,
4545 "Unable to determine PCI Express bandwidth.\n");
4546 return;
4547 }
4548
4549 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4550 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4551 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4552 width, width_cap);
4553 if (speed < speed_cap || width < width_cap)
4554 dev_info(adap->pdev_dev,
4555 "A slot with more lanes and/or higher speed is "
4556 "suggested for optimal performance.\n");
4557}
4558
91744948 4559static void print_port_info(const struct net_device *dev)
b8ff05a9 4560{
b8ff05a9 4561 char buf[80];
118969ed 4562 char *bufp = buf;
f1a051b9 4563 const char *spd = "";
118969ed
DM		 4564 const struct port_info *pi = netdev_priv(dev);
4565 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 4566
4567 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4568 spd = " 2.5 GT/s";
4569 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4570 spd = " 5 GT/s";
d2e752db
RD		 4571 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4572 spd = " 8 GT/s";
b8ff05a9 4573
118969ed
DM		 4574 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4575 bufp += sprintf(bufp, "100/");
4576 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4577 bufp += sprintf(bufp, "1000/");
4578 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4579 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 4580 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4581 bufp += sprintf(bufp, "40G/");
118969ed
DM		 4582 if (bufp != buf)
4583 --bufp;
72aca4bf 4584 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed 4585
547fd272 4586 netdev_info(dev, "Chelsio %s rev %d %s %sNIC %s\n",
0a57a536 4587 adap->params.vpd.id,
d14807dd 4588 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
547fd272 4589 is_offload(adap) ? "R" : "",
118969ed
DM		 4590 (adap->flags & USING_MSIX) ? " MSI-X" :
4591 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 4592 netdev_info(dev, "S/N: %s, P/N: %s\n",
4593 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 4594}
4595
91744948 4596static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 4597{
e5c8ae5f 4598 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 4599}
4600
06546391
DM		 4601/*
4602 * Free the following resources:
4603 * - memory used for tables
4604 * - MSI/MSI-X
4605 * - net devices
4606 * - resources FW is holding for us
4607 */
4608static void free_some_resources(struct adapter *adapter)
4609{
4610 unsigned int i;
4611
4612 t4_free_mem(adapter->l2t);
4613 t4_free_mem(adapter->tids.tid_tab);
4b8e27a8
HS		 4614 kfree(adapter->sge.egr_map);
4615 kfree(adapter->sge.ingr_map);
4616 kfree(adapter->sge.starving_fl);
4617 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 4618#ifdef CONFIG_DEBUG_FS
4619 kfree(adapter->sge.blocked_fl);
4620#endif
06546391
DM		 4621 disable_msi(adapter);
4622
4623 for_each_port(adapter, i)
671b0060 4624 if (adapter->port[i]) {
4f3a0fcf
HS		 4625 struct port_info *pi = adap2pinfo(adapter, i);
4626
4627 if (pi->viid != 0)
4628 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4629 0, pi->viid);
671b0060 4630 kfree(adap2pinfo(adapter, i)->rss);
06546391 4631 free_netdev(adapter->port[i]);
671b0060 4632 }
06546391 4633 if (adapter->flags & FW_OK)
b2612722 4634 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 4635}
4636
2ed28baa 4637#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 4638#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 4639 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 4640#define SEGMENT_SIZE 128
b8ff05a9 4641
d86bd29e
HS		 4642static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4643{
d86bd29e
HS		 4644 u16 device_id;
4645
4646 /* Retrieve adapter's device ID */
4647 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
46cdc9be 4648
4649 switch (device_id >> 12) {
d86bd29e 4650 case CHELSIO_T4:
46cdc9be 4651 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
d86bd29e 4652 case CHELSIO_T5:
46cdc9be 4653 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
d86bd29e 4654 case CHELSIO_T6:
46cdc9be 4655 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
d86bd29e
HS		 4656 default:
4657 dev_err(&pdev->dev, "Device %d is not supported\n",
4658 device_id);
d86bd29e 4659 }
46cdc9be 4660 return -EINVAL;
d86bd29e
HS		 4661}
4662
1dd06ae8 4663static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 4664{
22adfe0a 4665 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 4666 struct port_info *pi;
c8f44aff 4667 bool highdma = false;
b8ff05a9 4668 struct adapter *adapter = NULL;
d6ce2628 4669 void __iomem *regs;
d86bd29e
HS		 4670 u32 whoami, pl_rev;
4671 enum chip_type chip;
b8ff05a9
DM		 4672
4673 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4674
4675 err = pci_request_regions(pdev, KBUILD_MODNAME);
4676 if (err) {
4677 /* Just info, some other driver may have claimed the device. */
4678 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4679 return err;
4680 }
4681
b8ff05a9
DM		 4682 err = pci_enable_device(pdev);
4683 if (err) {
4684 dev_err(&pdev->dev, "cannot enable PCI device\n");
4685 goto out_release_regions;
4686 }
4687
d6ce2628
HS		 4688 regs = pci_ioremap_bar(pdev, 0);
4689 if (!regs) {
4690 dev_err(&pdev->dev, "cannot map device registers\n");
4691 err = -ENOMEM;
4692 goto out_disable_device;
4693 }
4694
8203b509
HS		 4695 err = t4_wait_dev_ready(regs);
4696 if (err < 0)
4697 goto out_unmap_bar0;
4698
d6ce2628 4699 /* We control everything through one PF */
d86bd29e
HS		 4700 whoami = readl(regs + PL_WHOAMI_A);
4701 pl_rev = REV_G(readl(regs + PL_REV_A));
4702 chip = get_chip_type(pdev, pl_rev);
4703 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4704 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
d6ce2628
HS		 4705 if (func != ent->driver_data) {
4706 iounmap(regs);
4707 pci_disable_device(pdev);
4708 pci_save_state(pdev); /* to restore SR-IOV later */
4709 goto sriov;
4710 }
4711
b8ff05a9 4712 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 4713 highdma = true;
b8ff05a9
DM		 4714 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4715 if (err) {
4716 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4717 "coherent allocations\n");
d6ce2628 4718 goto out_unmap_bar0;
b8ff05a9
DM		 4719 }
4720 } else {
4721 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4722 if (err) {
4723 dev_err(&pdev->dev, "no usable DMA configuration\n");
d6ce2628 4724 goto out_unmap_bar0;
b8ff05a9
DM		 4725 }
4726 }
4727
4728 pci_enable_pcie_error_reporting(pdev);
ef306b50 4729 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 4730 pci_set_master(pdev);
4731 pci_save_state(pdev);
4732
4733 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4734 if (!adapter) {
4735 err = -ENOMEM;
d6ce2628 4736 goto out_unmap_bar0;
b8ff05a9
DM		 4737 }
4738
29aaee65
AB		 4739 adapter->workq = create_singlethread_workqueue("cxgb4");
4740 if (!adapter->workq) {
4741 err = -ENOMEM;
4742 goto out_free_adapter;
4743 }
4744
144be3d9
GS		 4745 /* PCI device has been enabled */
4746 adapter->flags |= DEV_ENABLED;
4747
d6ce2628 4748 adapter->regs = regs;
b8ff05a9
DM		 4749 adapter->pdev = pdev;
4750 adapter->pdev_dev = &pdev->dev;
3069ee9b 4751 adapter->mbox = func;
b2612722 4752 adapter->pf = func;
b8ff05a9
DM		 4753 adapter->msg_enable = dflt_msg_enable;
4754 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4755
4756 spin_lock_init(&adapter->stats_lock);
4757 spin_lock_init(&adapter->tid_release_lock);
e327c225 4758 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 4759
4760 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 4761 INIT_WORK(&adapter->db_full_task, process_db_full);
4762 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 4763
4764 err = t4_prep_adapter(adapter);
4765 if (err)
d6ce2628
HS		 4766 goto out_free_adapter;
4767
22adfe0a 4768
d14807dd 4769 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 4770 s_qpp = (QUEUESPERPAGEPF0_S +
4771 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 4772 adapter->pf);
f612b815
HS		 4773 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4774 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 4775 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4776
4777 /* Each segment size is 128B. Write coalescing is enabled only
4778 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4779 * queue is less no of segments that can be accommodated in
4780 * a page size.
4781 */
4782 if (qpp > num_seg) {
4783 dev_err(&pdev->dev,
4784 "Incorrect number of egress queues per page\n");
4785 err = -EINVAL;
d6ce2628 4786 goto out_free_adapter;
22adfe0a
SR		 4787 }
4788 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4789 pci_resource_len(pdev, 2));
4790 if (!adapter->bar2) {
4791 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4792 err = -ENOMEM;
d6ce2628 4793 goto out_free_adapter;
22adfe0a
SR		 4794 }
4795 }
4796
636f9d37 4797 setup_memwin(adapter);
b8ff05a9 4798 err = adap_init0(adapter);
5b377d11
HS		 4799#ifdef CONFIG_DEBUG_FS
4800 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4801#endif
636f9d37 4802 setup_memwin_rdma(adapter);
b8ff05a9
DM		 4803 if (err)
4804 goto out_unmap_bar;
4805
2a485cf7
HS		 4806 /* configure SGE_STAT_CFG_A to read WC stats */
4807 if (!is_t4(adapter->params.chip))
676d6a75
HS		 4808 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4809 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4810 T6_STATMODE_V(0)));
2a485cf7 4811
b8ff05a9
DM		 4812 for_each_port(adapter, i) {
4813 struct net_device *netdev;
4814
4815 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4816 MAX_ETH_QSETS);
4817 if (!netdev) {
4818 err = -ENOMEM;
4819 goto out_free_dev;
4820 }
4821
4822 SET_NETDEV_DEV(netdev, &pdev->dev);
4823
4824 adapter->port[i] = netdev;
4825 pi = netdev_priv(netdev);
4826 pi->adapter = adapter;
4827 pi->xact_addr_filt = -1;
b8ff05a9 4828 pi->port_id = i;
b8ff05a9
DM		 4829 netdev->irq = pdev->irq;
4830
2ed28baa
MM		 4831 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4832 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4833 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 4834 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 4835 if (highdma)
4836 netdev->hw_features |= NETIF_F_HIGHDMA;
4837 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 4838 netdev->vlan_features = netdev->features & VLAN_FEAT;
4839
01789349
JP		 4840 netdev->priv_flags |= IFF_UNICAST_FLT;
4841
b8ff05a9 4842 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 4843#ifdef CONFIG_CHELSIO_T4_DCB
4844 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4845 cxgb4_dcb_state_init(netdev);
4846#endif
812034f1 4847 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 4848 }
4849
4850 pci_set_drvdata(pdev, adapter);
4851
4852 if (adapter->flags & FW_OK) {
060e0c75 4853 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 4854 if (err)
4855 goto out_free_dev;
098ef6c2
HS		 4856 } else if (adapter->params.nports == 1) {
4857 /* If we don't have a connection to the firmware -- possibly
4858 * because of an error -- grab the raw VPD parameters so we
4859 * can set the proper MAC Address on the debug network
4860 * interface that we've created.
4861 */
4862 u8 hw_addr[ETH_ALEN];
4863 u8 *na = adapter->params.vpd.na;
4864
4865 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4866 if (!err) {
4867 for (i = 0; i < ETH_ALEN; i++)
4868 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4869 hex2val(na[2 * i + 1]));
4870 t4_set_hw_addr(adapter, 0, hw_addr);
4871 }
b8ff05a9
DM		 4872 }
4873
098ef6c2 4874 /* Configure queues and allocate tables now, they can be needed as
b8ff05a9
DM		 4875 * soon as the first register_netdev completes.
4876 */
4877 cfg_queues(adapter);
4878
5be9ed8d 4879 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
b8ff05a9
DM		 4880 if (!adapter->l2t) {
4881 /* We tolerate a lack of L2T, giving up some functionality */
4882 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4883 adapter->params.offload = 0;
4884 }
4885
b5a02f50 4886#if IS_ENABLED(CONFIG_IPV6)
eb72f74f
HS		 4887 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
4888 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
4889 /* CLIP functionality is not present in hardware,
4890 * hence disable all offload features
b5a02f50
AB		 4891 */
4892 dev_warn(&pdev->dev,
eb72f74f 4893 "CLIP not enabled in hardware, continuing\n");
b5a02f50 4894 adapter->params.offload = 0;
eb72f74f
HS		 4895 } else {
4896 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4897 adapter->clipt_end);
4898 if (!adapter->clipt) {
4899 /* We tolerate a lack of clip_table, giving up
4900 * some functionality
4901 */
4902 dev_warn(&pdev->dev,
4903 "could not allocate Clip table, continuing\n");
4904 adapter->params.offload = 0;
4905 }
b5a02f50
AB		 4906 }
4907#endif
b8ff05a9
DM		 4908 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4909 dev_warn(&pdev->dev, "could not allocate TID table, "
4910 "continuing\n");
4911 adapter->params.offload = 0;
4912 }
4913
9a1bb9f6
HS		 4914 if (is_offload(adapter)) {
4915 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4916 u32 hash_base, hash_reg;
4917
4918 if (chip <= CHELSIO_T5) {
4919 hash_reg = LE_DB_TID_HASHBASE_A;
4920 hash_base = t4_read_reg(adapter, hash_reg);
4921 adapter->tids.hash_base = hash_base / 4;
4922 } else {
4923 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4924 hash_base = t4_read_reg(adapter, hash_reg);
4925 adapter->tids.hash_base = hash_base;
4926 }
4927 }
4928 }
4929
f7cabcdd
DM		 4930 /* See what interrupts we'll be using */
4931 if (msi > 1 && enable_msix(adapter) == 0)
4932 adapter->flags |= USING_MSIX;
4933 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4934 adapter->flags |= USING_MSI;
4935
547fd272
HS		 4936 /* check for PCI Express bandwidth capabiltites */
4937 cxgb4_check_pcie_caps(adapter);
4938
671b0060
DM		 4939 err = init_rss(adapter);
4940 if (err)
4941 goto out_free_dev;
4942
b8ff05a9
DM		 4943 /*
4944 * The card is now ready to go. If any errors occur during device
4945 * registration we do not fail the whole card but rather proceed only
4946 * with the ports we manage to register successfully. However we must
4947 * register at least one net device.
4948 */
4949 for_each_port(adapter, i) {
a57cabe0
DM		 4950 pi = adap2pinfo(adapter, i);
4951 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4952 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4953
b8ff05a9
DM		 4954 err = register_netdev(adapter->port[i]);
4955 if (err)
b1a3c2b6 4956 break;
b1a3c2b6
DM		 4957 adapter->chan_map[pi->tx_chan] = i;
4958 print_port_info(adapter->port[i]);
b8ff05a9 4959 }
b1a3c2b6 4960 if (i == 0) {
b8ff05a9
DM		 4961 dev_err(&pdev->dev, "could not register any net devices\n");
4962 goto out_free_dev;
4963 }
b1a3c2b6
DM		 4964 if (err) {
4965 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4966 err = 0;
6403eab1 4967 }
b8ff05a9
DM		 4968
4969 if (cxgb4_debugfs_root) {
4970 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4971 cxgb4_debugfs_root);
4972 setup_debugfs(adapter);
4973 }
4974
6482aa7c
DLR		 4975 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4976 pdev->needs_freset = 1;
4977
b8ff05a9
DM		 4978 if (is_offload(adapter))
4979 attach_ulds(adapter);
4980
8e1e6059 4981sriov:
b8ff05a9 4982#ifdef CONFIG_PCI_IOV
7d6727cf 4983 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 4984 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4985 dev_info(&pdev->dev,
4986 "instantiated %u virtual functions\n",
4987 num_vf[func]);
4988#endif
4989 return 0;
4990
4991 out_free_dev:
06546391 4992 free_some_resources(adapter);
b8ff05a9 4993 out_unmap_bar:
d14807dd 4994 if (!is_t4(adapter->params.chip))
22adfe0a 4995 iounmap(adapter->bar2);
b8ff05a9 4996 out_free_adapter:
29aaee65
AB		 4997 if (adapter->workq)
4998 destroy_workqueue(adapter->workq);
4999
b8ff05a9 5000 kfree(adapter);
d6ce2628
HS		 5001 out_unmap_bar0:
5002 iounmap(regs);
b8ff05a9
DM		 5003 out_disable_device:
5004 pci_disable_pcie_error_reporting(pdev);
5005 pci_disable_device(pdev);
5006 out_release_regions:
5007 pci_release_regions(pdev);
b8ff05a9
DM		 5008 return err;
5009}
5010
91744948 5011static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 5012{
5013 struct adapter *adapter = pci_get_drvdata(pdev);
5014
636f9d37 5015#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 5016 pci_disable_sriov(pdev);
5017
636f9d37
VP		 5018#endif
5019
b8ff05a9
DM		 5020 if (adapter) {
5021 int i;
5022
29aaee65
AB		 5023 /* Tear down per-adapter Work Queue first since it can contain
5024 * references to our adapter data structure.
5025 */
5026 destroy_workqueue(adapter->workq);
5027
b8ff05a9
DM		 5028 if (is_offload(adapter))
5029 detach_ulds(adapter);
5030
b37987e8
HS		 5031 disable_interrupts(adapter);
5032
b8ff05a9 5033 for_each_port(adapter, i)
8f3a7676 5034 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 5035 unregister_netdev(adapter->port[i]);
5036
9f16dc2e 5037 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 5038
f2b7e78d
VP		 5039 /* If we allocated filters, free up state associated with any
5040 * valid filters ...
5041 */
5042 if (adapter->tids.ftid_tab) {
5043 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 5044 for (i = 0; i < (adapter->tids.nftids +
5045 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 5046 if (f->valid)
5047 clear_filter(adapter, f);
5048 }
5049
aaefae9b
DM		 5050 if (adapter->flags & FULL_INIT_DONE)
5051 cxgb_down(adapter);
b8ff05a9 5052
06546391 5053 free_some_resources(adapter);
b5a02f50
AB		 5054#if IS_ENABLED(CONFIG_IPV6)
5055 t4_cleanup_clip_tbl(adapter);
5056#endif
b8ff05a9 5057 iounmap(adapter->regs);
d14807dd 5058 if (!is_t4(adapter->params.chip))
22adfe0a 5059 iounmap(adapter->bar2);
b8ff05a9 5060 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 5061 if ((adapter->flags & DEV_ENABLED)) {
5062 pci_disable_device(pdev);
5063 adapter->flags &= ~DEV_ENABLED;
5064 }
b8ff05a9 5065 pci_release_regions(pdev);
ee9a33b2 5066 synchronize_rcu();
8b662fe7 5067 kfree(adapter);
a069ec91 5068 } else
b8ff05a9
DM		 5069 pci_release_regions(pdev);
5070}
5071
5072static struct pci_driver cxgb4_driver = {
5073 .name = KBUILD_MODNAME,
5074 .id_table = cxgb4_pci_tbl,
5075 .probe = init_one,
91744948 5076 .remove = remove_one,
687d705c 5077 .shutdown = remove_one,
204dc3c0 5078 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 5079};
5080
5081static int __init cxgb4_init_module(void)
5082{
5083 int ret;
5084
5085 /* Debugfs support is optional, just warn if this fails */
5086 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5087 if (!cxgb4_debugfs_root)
428ac43f 5088 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 5089
5090 ret = pci_register_driver(&cxgb4_driver);
29aaee65 5091 if (ret < 0)
b8ff05a9 5092 debugfs_remove(cxgb4_debugfs_root);
01bcca68 5093
1bb60376 5094#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 5095 if (!inet6addr_registered) {
5096 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5097 inet6addr_registered = true;
5098 }
1bb60376 5099#endif
01bcca68 5100
b8ff05a9
DM		 5101 return ret;
5102}
5103
5104static void __exit cxgb4_cleanup_module(void)
5105{
1bb60376 5106#if IS_ENABLED(CONFIG_IPV6)
1793c798 5107 if (inet6addr_registered) {
b5a02f50
AB		 5108 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5109 inet6addr_registered = false;
5110 }
1bb60376 5111#endif
b8ff05a9
DM		 5112 pci_unregister_driver(&cxgb4_driver);
5113 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5114}
5115
5116module_init(cxgb4_init_module);
5117module_exit(cxgb4_cleanup_module);
Linux kernel - Deliverables
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