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cxgb4: Rename t4_link_start() to t4_link_l1cfg
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
b5a02f50 65#include <net/addrconf.h>
b8ff05a9
DM		 66#include <asm/uaccess.h>
67
68#include "cxgb4.h"
69#include "t4_regs.h"
f612b815 70#include "t4_values.h"
b8ff05a9
DM		 71#include "t4_msg.h"
72#include "t4fw_api.h"
cd6c2f12 73#include "t4fw_version.h"
688848b1 74#include "cxgb4_dcb.h"
fd88b31a 75#include "cxgb4_debugfs.h"
b5a02f50 76#include "clip_tbl.h"
b8ff05a9
DM		 77#include "l2t.h"
78
812034f1
HS		 79char cxgb4_driver_name[] = KBUILD_MODNAME;
80
01bcca68
VP		 81#ifdef DRV_VERSION
82#undef DRV_VERSION
83#endif
3a7f8554 84#define DRV_VERSION "2.0.0-ko"
812034f1 85const char cxgb4_driver_version[] = DRV_VERSION;
3a7f8554 86#define DRV_DESC "Chelsio T4/T5 Network Driver"
b8ff05a9 87
f2b7e78d
VP		 88/* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
93 */
94struct filter_entry {
95 /* Administrative fields for filter.
96 */
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
99
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
103
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
108 */
109 struct ch_filter_specification fs;
110};
111
b8ff05a9
DM		 112#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
115
3fedeab1
HS		 116/* Macros needed to support the PCI Device ID Table ...
117 */
118#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 119 static const struct pci_device_id cxgb4_pci_tbl[] = {
3fedeab1 120#define CH_PCI_DEVICE_ID_FUNCTION 0x4
b8ff05a9 121
3fedeab1
HS		 122/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
123 * called for both.
124 */
125#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
126
127#define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
129
130#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
131 { 0, } \
132 }
133
134#include "t4_pci_id_tbl.h"
b8ff05a9 135
16e47624 136#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 137#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 138#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 139#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 140#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 141#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 142#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144#define PHY_AQ1202_DEVICEID 0x4409
145#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 146
147MODULE_DESCRIPTION(DRV_DESC);
148MODULE_AUTHOR("Chelsio Communications");
149MODULE_LICENSE("Dual BSD/GPL");
150MODULE_VERSION(DRV_VERSION);
151MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 152MODULE_FIRMWARE(FW4_FNAME);
0a57a536 153MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 154
636f9d37
VP		 155/*
156 * Normally we're willing to become the firmware's Master PF but will be happy
157 * if another PF has already become the Master and initialized the adapter.
158 * Setting "force_init" will cause this driver to forcibly establish itself as
159 * the Master PF and initialize the adapter.
160 */
161static uint force_init;
162
163module_param(force_init, uint, 0644);
164MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
165
13ee15d3
VP		 166/*
167 * Normally if the firmware we connect to has Configuration File support, we
168 * use that and only fall back to the old Driver-based initialization if the
169 * Configuration File fails for some reason. If force_old_init is set, then
170 * we'll always use the old Driver-based initialization sequence.
171 */
172static uint force_old_init;
173
174module_param(force_old_init, uint, 0644);
06640310
HS		 175MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
176 " parameter");
13ee15d3 177
b8ff05a9
DM		 178static int dflt_msg_enable = DFLT_MSG_ENABLE;
179
180module_param(dflt_msg_enable, int, 0644);
181MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
182
183/*
184 * The driver uses the best interrupt scheme available on a platform in the
185 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
186 * of these schemes the driver may consider as follows:
187 *
188 * msi = 2: choose from among all three options
189 * msi = 1: only consider MSI and INTx interrupts
190 * msi = 0: force INTx interrupts
191 */
192static int msi = 2;
193
194module_param(msi, int, 0644);
195MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
196
197/*
198 * Queue interrupt hold-off timer values. Queues default to the first of these
199 * upon creation.
200 */
201static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
202
203module_param_array(intr_holdoff, uint, NULL, 0644);
204MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
06640310 205 "0..4 in microseconds, deprecated parameter");
b8ff05a9
DM		 206
207static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
208
209module_param_array(intr_cnt, uint, NULL, 0644);
210MODULE_PARM_DESC(intr_cnt,
06640310
HS		 211 "thresholds 1..3 for queue interrupt packet counters, "
212 "deprecated parameter");
b8ff05a9 213
636f9d37
VP		 214/*
215 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
216 * offset by 2 bytes in order to have the IP headers line up on 4-byte
217 * boundaries. This is a requirement for many architectures which will throw
218 * a machine check fault if an attempt is made to access one of the 4-byte IP
219 * header fields on a non-4-byte boundary. And it's a major performance issue
220 * even on some architectures which allow it like some implementations of the
221 * x86 ISA. However, some architectures don't mind this and for some very
222 * edge-case performance sensitive applications (like forwarding large volumes
223 * of small packets), setting this DMA offset to 0 will decrease the number of
224 * PCI-E Bus transfers enough to measurably affect performance.
225 */
226static int rx_dma_offset = 2;
227
eb939922 228static bool vf_acls;
b8ff05a9
DM		 229
230#ifdef CONFIG_PCI_IOV
231module_param(vf_acls, bool, 0644);
06640310
HS		 232MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
233 "deprecated parameter");
b8ff05a9 234
7d6727cf
SR		 235/* Configure the number of PCI-E Virtual Function which are to be instantiated
236 * on SR-IOV Capable Physical Functions.
0a57a536 237 */
7d6727cf 238static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 239
240module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 241MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 242#endif
243
688848b1
AB		 244/* TX Queue select used to determine what algorithm to use for selecting TX
245 * queue. Select between the kernel provided function (select_queue=0) or user
246 * cxgb_select_queue function (select_queue=1)
247 *
248 * Default: select_queue=0
249 */
250static int select_queue;
251module_param(select_queue, int, 0644);
252MODULE_PARM_DESC(select_queue,
253 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
254
06640310 255static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
13ee15d3 256
f2b7e78d 257module_param(tp_vlan_pri_map, uint, 0644);
06640310
HS		 258MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
259 "deprecated parameter");
f2b7e78d 260
b8ff05a9
DM		 261static struct dentry *cxgb4_debugfs_root;
262
263static LIST_HEAD(adapter_list);
264static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 265/* Adapter list to be accessed from atomic context */
266static LIST_HEAD(adap_rcu_list);
267static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 268static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
269static const char *uld_str[] = { "RDMA", "iSCSI" };
270
271static void link_report(struct net_device *dev)
272{
273 if (!netif_carrier_ok(dev))
274 netdev_info(dev, "link down\n");
275 else {
276 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
277
278 const char *s = "10Mbps";
279 const struct port_info *p = netdev_priv(dev);
280
281 switch (p->link_cfg.speed) {
e8b39015 282 case 10000:
b8ff05a9
DM		 283 s = "10Gbps";
284 break;
e8b39015 285 case 1000:
b8ff05a9
DM		 286 s = "1000Mbps";
287 break;
e8b39015 288 case 100:
b8ff05a9
DM		 289 s = "100Mbps";
290 break;
e8b39015 291 case 40000:
72aca4bf
KS		 292 s = "40Gbps";
293 break;
b8ff05a9
DM		 294 }
295
296 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
297 fc[p->link_cfg.fc]);
298 }
299}
300
688848b1
AB		 301#ifdef CONFIG_CHELSIO_T4_DCB
302/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
303static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
304{
305 struct port_info *pi = netdev_priv(dev);
306 struct adapter *adap = pi->adapter;
307 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
308 int i;
309
310 /* We use a simple mapping of Port TX Queue Index to DCB
311 * Priority when we're enabling DCB.
312 */
313 for (i = 0; i < pi->nqsets; i++, txq++) {
314 u32 name, value;
315 int err;
316
5167865a
HS		 317 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
318 FW_PARAMS_PARAM_X_V(
319 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
320 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 321 value = enable ? i : 0xffffffff;
322
323 /* Since we can be called while atomic (from "interrupt
324 * level") we need to issue the Set Parameters Commannd
325 * without sleeping (timeout < 0).
326 */
b2612722 327 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 328 &name, &value,
329 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 330
331 if (err)
332 dev_err(adap->pdev_dev,
333 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
334 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 335 else
336 txq->dcb_prio = value;
688848b1
AB		 337 }
338}
339#endif /* CONFIG_CHELSIO_T4_DCB */
340
b8ff05a9
DM		 341void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
342{
343 struct net_device *dev = adapter->port[port_id];
344
345 /* Skip changes from disabled ports. */
346 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
347 if (link_stat)
348 netif_carrier_on(dev);
688848b1
AB		 349 else {
350#ifdef CONFIG_CHELSIO_T4_DCB
351 cxgb4_dcb_state_init(dev);
352 dcb_tx_queue_prio_enable(dev, false);
353#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 354 netif_carrier_off(dev);
688848b1 355 }
b8ff05a9
DM		 356
357 link_report(dev);
358 }
359}
360
361void t4_os_portmod_changed(const struct adapter *adap, int port_id)
362{
363 static const char *mod_str[] = {
a0881cab 364 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 365 };
366
367 const struct net_device *dev = adap->port[port_id];
368 const struct port_info *pi = netdev_priv(dev);
369
370 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
371 netdev_info(dev, "port module unplugged\n");
a0881cab 372 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 373 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
374}
375
376/*
377 * Configure the exact and hash address filters to handle a port's multicast
378 * and secondary unicast MAC addresses.
379 */
380static int set_addr_filters(const struct net_device *dev, bool sleep)
381{
382 u64 mhash = 0;
383 u64 uhash = 0;
384 bool free = true;
385 u16 filt_idx[7];
386 const u8 *addr[7];
387 int ret, naddr = 0;
b8ff05a9
DM		 388 const struct netdev_hw_addr *ha;
389 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 390 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 391 const struct port_info *pi = netdev_priv(dev);
b2612722 392 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 393
394 /* first do the secondary unicast addresses */
395 netdev_for_each_uc_addr(ha, dev) {
396 addr[naddr++] = ha->addr;
397 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 398 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 399 naddr, addr, filt_idx, &uhash, sleep);
400 if (ret < 0)
401 return ret;
402
403 free = false;
404 naddr = 0;
405 }
406 }
407
408 /* next set up the multicast addresses */
4a35ecf8
DM		 409 netdev_for_each_mc_addr(ha, dev) {
410 addr[naddr++] = ha->addr;
411 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 412 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 413 naddr, addr, filt_idx, &mhash, sleep);
414 if (ret < 0)
415 return ret;
416
417 free = false;
418 naddr = 0;
419 }
420 }
421
060e0c75 422 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 423 uhash | mhash, sleep);
424}
425
3069ee9b
VP		 426int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
427module_param(dbfifo_int_thresh, int, 0644);
428MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
429
404d9e3f
VP		 430/*
431 * usecs to sleep while draining the dbfifo
432 */
433static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 434module_param(dbfifo_drain_delay, int, 0644);
435MODULE_PARM_DESC(dbfifo_drain_delay,
436 "usecs to sleep while draining the dbfifo");
437
b8ff05a9
DM		 438/*
439 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
440 * If @mtu is -1 it is left unchanged.
441 */
442static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
443{
444 int ret;
445 struct port_info *pi = netdev_priv(dev);
446
447 ret = set_addr_filters(dev, sleep_ok);
448 if (ret == 0)
b2612722 449 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
b8ff05a9 450 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 451 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 452 sleep_ok);
453 return ret;
454}
455
456/**
457 * link_start - enable a port
458 * @dev: the port to enable
459 *
460 * Performs the MAC and PHY actions needed to enable a port.
461 */
462static int link_start(struct net_device *dev)
463{
464 int ret;
465 struct port_info *pi = netdev_priv(dev);
b2612722 466 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 467
468 /*
469 * We do not set address filters and promiscuity here, the stack does
470 * that step explicitly.
471 */
060e0c75 472 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 473 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 474 if (ret == 0) {
060e0c75 475 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 476 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 477 true);
b8ff05a9
DM		 478 if (ret >= 0) {
479 pi->xact_addr_filt = ret;
480 ret = 0;
481 }
482 }
483 if (ret == 0)
4036da90 484 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 485 &pi->link_cfg);
30f00847
AB		 486 if (ret == 0) {
487 local_bh_disable();
688848b1
AB		 488 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
489 true, CXGB4_DCB_ENABLED);
30f00847
AB		 490 local_bh_enable();
491 }
688848b1 492
b8ff05a9
DM		 493 return ret;
494}
495
688848b1
AB		 496int cxgb4_dcb_enabled(const struct net_device *dev)
497{
498#ifdef CONFIG_CHELSIO_T4_DCB
499 struct port_info *pi = netdev_priv(dev);
500
3bb06261
AB		 501 if (!pi->dcb.enabled)
502 return 0;
503
504 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
505 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
688848b1
AB		 506#else
507 return 0;
508#endif
509}
510EXPORT_SYMBOL(cxgb4_dcb_enabled);
511
512#ifdef CONFIG_CHELSIO_T4_DCB
513/* Handle a Data Center Bridging update message from the firmware. */
514static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
515{
2b5fb1f2 516 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
688848b1
AB		 517 struct net_device *dev = adap->port[port];
518 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
519 int new_dcb_enabled;
520
521 cxgb4_dcb_handle_fw_update(adap, pcmd);
522 new_dcb_enabled = cxgb4_dcb_enabled(dev);
523
524 /* If the DCB has become enabled or disabled on the port then we're
525 * going to need to set up/tear down DCB Priority parameters for the
526 * TX Queues associated with the port.
527 */
528 if (new_dcb_enabled != old_dcb_enabled)
529 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
530}
531#endif /* CONFIG_CHELSIO_T4_DCB */
532
f2b7e78d
VP		 533/* Clear a filter and release any of its resources that we own. This also
534 * clears the filter's "pending" status.
535 */
536static void clear_filter(struct adapter *adap, struct filter_entry *f)
537{
538 /* If the new or old filter have loopback rewriteing rules then we'll
539 * need to free any existing Layer Two Table (L2T) entries of the old
540 * filter rule. The firmware will handle freeing up any Source MAC
541 * Table (SMT) entries used for rewriting Source MAC Addresses in
542 * loopback rules.
543 */
544 if (f->l2t)
545 cxgb4_l2t_release(f->l2t);
546
547 /* The zeroing of the filter rule below clears the filter valid,
548 * pending, locked flags, l2t pointer, etc. so it's all we need for
549 * this operation.
550 */
551 memset(f, 0, sizeof(*f));
552}
553
554/* Handle a filter write/deletion reply.
555 */
556static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
557{
558 unsigned int idx = GET_TID(rpl);
559 unsigned int nidx = idx - adap->tids.ftid_base;
560 unsigned int ret;
561 struct filter_entry *f;
562
563 if (idx >= adap->tids.ftid_base && nidx <
564 (adap->tids.nftids + adap->tids.nsftids)) {
565 idx = nidx;
bdc590b9 566 ret = TCB_COOKIE_G(rpl->cookie);
f2b7e78d
VP		 567 f = &adap->tids.ftid_tab[idx];
568
569 if (ret == FW_FILTER_WR_FLT_DELETED) {
570 /* Clear the filter when we get confirmation from the
571 * hardware that the filter has been deleted.
572 */
573 clear_filter(adap, f);
574 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
575 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
576 idx);
577 clear_filter(adap, f);
578 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
579 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
580 f->pending = 0; /* asynchronous setup completed */
581 f->valid = 1;
582 } else {
583 /* Something went wrong. Issue a warning about the
584 * problem and clear everything out.
585 */
586 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
587 idx, ret);
588 clear_filter(adap, f);
589 }
590 }
591}
592
593/* Response queue handler for the FW event queue.
b8ff05a9
DM		 594 */
595static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
596 const struct pkt_gl *gl)
597{
598 u8 opcode = ((const struct rss_header *)rsp)->opcode;
599
600 rsp++; /* skip RSS header */
b407a4a9
VP		 601
602 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
603 */
604 if (unlikely(opcode == CPL_FW4_MSG &&
605 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
606 rsp++;
607 opcode = ((const struct rss_header *)rsp)->opcode;
608 rsp++;
609 if (opcode != CPL_SGE_EGR_UPDATE) {
610 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
611 , opcode);
612 goto out;
613 }
614 }
615
b8ff05a9
DM		 616 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
617 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 618 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 619 struct sge_txq *txq;
b8ff05a9 620
e46dab4d 621 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 622 txq->restarts++;
e46dab4d 623 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 624 struct sge_eth_txq *eq;
625
626 eq = container_of(txq, struct sge_eth_txq, q);
627 netif_tx_wake_queue(eq->txq);
628 } else {
629 struct sge_ofld_txq *oq;
630
631 oq = container_of(txq, struct sge_ofld_txq, q);
632 tasklet_schedule(&oq->qresume_tsk);
633 }
634 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
635 const struct cpl_fw6_msg *p = (void *)rsp;
636
688848b1
AB		 637#ifdef CONFIG_CHELSIO_T4_DCB
638 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 639 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 640 unsigned int action =
2b5fb1f2 641 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 642
643 if (cmd == FW_PORT_CMD &&
644 action == FW_PORT_ACTION_GET_PORT_INFO) {
2b5fb1f2 645 int port = FW_PORT_CMD_PORTID_G(
688848b1
AB		 646 be32_to_cpu(pcmd->op_to_portid));
647 struct net_device *dev = q->adap->port[port];
648 int state_input = ((pcmd->u.info.dcbxdis_pkd &
2b5fb1f2 649 FW_PORT_CMD_DCBXDIS_F)
688848b1
AB		 650 ? CXGB4_DCB_INPUT_FW_DISABLED
651 : CXGB4_DCB_INPUT_FW_ENABLED);
652
653 cxgb4_dcb_state_fsm(dev, state_input);
654 }
655
656 if (cmd == FW_PORT_CMD &&
657 action == FW_PORT_ACTION_L2_DCB_CFG)
658 dcb_rpl(q->adap, pcmd);
659 else
660#endif
661 if (p->type == 0)
662 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 663 } else if (opcode == CPL_L2T_WRITE_RPL) {
664 const struct cpl_l2t_write_rpl *p = (void *)rsp;
665
666 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 667 } else if (opcode == CPL_SET_TCB_RPL) {
668 const struct cpl_set_tcb_rpl *p = (void *)rsp;
669
670 filter_rpl(q->adap, p);
b8ff05a9
DM		 671 } else
672 dev_err(q->adap->pdev_dev,
673 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 674out:
b8ff05a9
DM		 675 return 0;
676}
677
678/**
679 * uldrx_handler - response queue handler for ULD queues
680 * @q: the response queue that received the packet
681 * @rsp: the response queue descriptor holding the offload message
682 * @gl: the gather list of packet fragments
683 *
684 * Deliver an ingress offload packet to a ULD. All processing is done by
685 * the ULD, we just maintain statistics.
686 */
687static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
688 const struct pkt_gl *gl)
689{
690 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
691
b407a4a9
VP		 692 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
693 */
694 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
695 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
696 rsp += 2;
697
b8ff05a9
DM		 698 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
699 rxq->stats.nomem++;
700 return -1;
701 }
702 if (gl == NULL)
703 rxq->stats.imm++;
704 else if (gl == CXGB4_MSG_AN)
705 rxq->stats.an++;
706 else
707 rxq->stats.pkts++;
708 return 0;
709}
710
711static void disable_msi(struct adapter *adapter)
712{
713 if (adapter->flags & USING_MSIX) {
714 pci_disable_msix(adapter->pdev);
715 adapter->flags &= ~USING_MSIX;
716 } else if (adapter->flags & USING_MSI) {
717 pci_disable_msi(adapter->pdev);
718 adapter->flags &= ~USING_MSI;
719 }
720}
721
722/*
723 * Interrupt handler for non-data events used with MSI-X.
724 */
725static irqreturn_t t4_nondata_intr(int irq, void *cookie)
726{
727 struct adapter *adap = cookie;
0d804338 728 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 729
0d804338 730 if (v & PFSW_F) {
b8ff05a9 731 adap->swintr = 1;
0d804338 732 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 733 }
c3c7b121
HS		 734 if (adap->flags & MASTER_PF)
735 t4_slow_intr_handler(adap);
b8ff05a9
DM		 736 return IRQ_HANDLED;
737}
738
739/*
740 * Name the MSI-X interrupts.
741 */
742static void name_msix_vecs(struct adapter *adap)
743{
ba27816c 744 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 745
746 /* non-data interrupts */
b1a3c2b6 747 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 748
749 /* FW events */
b1a3c2b6
DM		 750 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
751 adap->port[0]->name);
b8ff05a9
DM		 752
753 /* Ethernet queues */
754 for_each_port(adap, j) {
755 struct net_device *d = adap->port[j];
756 const struct port_info *pi = netdev_priv(d);
757
ba27816c 758 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 759 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
760 d->name, i);
b8ff05a9
DM		 761 }
762
763 /* offload queues */
ba27816c
DM		 764 for_each_ofldrxq(&adap->sge, i)
765 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 766 adap->port[0]->name, i);
ba27816c
DM		 767
768 for_each_rdmarxq(&adap->sge, i)
769 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 770 adap->port[0]->name, i);
cf38be6d
HS		 771
772 for_each_rdmaciq(&adap->sge, i)
773 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
774 adap->port[0]->name, i);
b8ff05a9
DM		 775}
776
777static int request_msix_queue_irqs(struct adapter *adap)
778{
779 struct sge *s = &adap->sge;
cf38be6d
HS		 780 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
781 int msi_index = 2;
b8ff05a9
DM		 782
783 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
784 adap->msix_info[1].desc, &s->fw_evtq);
785 if (err)
786 return err;
787
788 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 789 err = request_irq(adap->msix_info[msi_index].vec,
790 t4_sge_intr_msix, 0,
791 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 792 &s->ethrxq[ethqidx].rspq);
793 if (err)
794 goto unwind;
404d9e3f 795 msi_index++;
b8ff05a9
DM		 796 }
797 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP		 798 err = request_irq(adap->msix_info[msi_index].vec,
799 t4_sge_intr_msix, 0,
800 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 801 &s->ofldrxq[ofldqidx].rspq);
802 if (err)
803 goto unwind;
404d9e3f 804 msi_index++;
b8ff05a9
DM		 805 }
806 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 807 err = request_irq(adap->msix_info[msi_index].vec,
808 t4_sge_intr_msix, 0,
809 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 810 &s->rdmarxq[rdmaqidx].rspq);
811 if (err)
812 goto unwind;
404d9e3f 813 msi_index++;
b8ff05a9 814 }
cf38be6d
HS		 815 for_each_rdmaciq(s, rdmaciqqidx) {
816 err = request_irq(adap->msix_info[msi_index].vec,
817 t4_sge_intr_msix, 0,
818 adap->msix_info[msi_index].desc,
819 &s->rdmaciq[rdmaciqqidx].rspq);
820 if (err)
821 goto unwind;
822 msi_index++;
823 }
b8ff05a9
DM		 824 return 0;
825
826unwind:
cf38be6d
HS		 827 while (--rdmaciqqidx >= 0)
828 free_irq(adap->msix_info[--msi_index].vec,
829 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 830 while (--rdmaqidx >= 0)
404d9e3f 831 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 832 &s->rdmarxq[rdmaqidx].rspq);
833 while (--ofldqidx >= 0)
404d9e3f 834 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 835 &s->ofldrxq[ofldqidx].rspq);
836 while (--ethqidx >= 0)
404d9e3f
VP		 837 free_irq(adap->msix_info[--msi_index].vec,
838 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 839 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
840 return err;
841}
842
843static void free_msix_queue_irqs(struct adapter *adap)
844{
404d9e3f 845 int i, msi_index = 2;
b8ff05a9
DM		 846 struct sge *s = &adap->sge;
847
848 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
849 for_each_ethrxq(s, i)
404d9e3f 850 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 851 for_each_ofldrxq(s, i)
404d9e3f 852 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 853 for_each_rdmarxq(s, i)
404d9e3f 854 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 855 for_each_rdmaciq(s, i)
856 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 857}
858
671b0060 859/**
812034f1 860 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 861 * @pi: the port
862 * @queues: array of queue indices for RSS
863 *
864 * Sets up the portion of the HW RSS table for the port's VI to distribute
865 * packets to the Rx queues in @queues.
c035e183 866 * Should never be called before setting up sge eth rx queues
671b0060 867 */
812034f1 868int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 869{
870 u16 *rss;
871 int i, err;
c035e183
HS		 872 struct adapter *adapter = pi->adapter;
873 const struct sge_eth_rxq *rxq;
671b0060 874
c035e183 875 rxq = &adapter->sge.ethrxq[pi->first_qset];
671b0060
DM		 876 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
877 if (!rss)
878 return -ENOMEM;
879
880 /* map the queue indices to queue ids */
881 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 882 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 883
b2612722 884 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 885 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 886 /* If Tunnel All Lookup isn't specified in the global RSS
887 * Configuration, then we need to specify a default Ingress
888 * Queue for any ingress packets which aren't hashed. We'll
889 * use our first ingress queue ...
890 */
891 if (!err)
892 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
893 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
894 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
895 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
896 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
897 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
898 rss[0]);
671b0060
DM		 899 kfree(rss);
900 return err;
901}
902
b8ff05a9
DM		 903/**
904 * setup_rss - configure RSS
905 * @adap: the adapter
906 *
671b0060 907 * Sets up RSS for each port.
b8ff05a9
DM		 908 */
909static int setup_rss(struct adapter *adap)
910{
c035e183 911 int i, j, err;
b8ff05a9
DM		 912
913 for_each_port(adap, i) {
914 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 915
c035e183
HS		 916 /* Fill default values with equal distribution */
917 for (j = 0; j < pi->rss_size; j++)
918 pi->rss[j] = j % pi->nqsets;
919
812034f1 920 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 921 if (err)
922 return err;
923 }
924 return 0;
925}
926
e46dab4d
DM		 927/*
928 * Return the channel of the ingress queue with the given qid.
929 */
930static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
931{
932 qid -= p->ingr_start;
933 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
934}
935
b8ff05a9
DM		 936/*
937 * Wait until all NAPI handlers are descheduled.
938 */
939static void quiesce_rx(struct adapter *adap)
940{
941 int i;
942
4b8e27a8 943 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 944 struct sge_rspq *q = adap->sge.ingr_map[i];
945
3a336cb1 946 if (q && q->handler) {
b8ff05a9 947 napi_disable(&q->napi);
3a336cb1
HS		 948 local_bh_disable();
949 while (!cxgb_poll_lock_napi(q))
950 mdelay(1);
951 local_bh_enable();
952 }
953
b8ff05a9
DM		 954 }
955}
956
b37987e8
HS		 957/* Disable interrupt and napi handler */
958static void disable_interrupts(struct adapter *adap)
959{
960 if (adap->flags & FULL_INIT_DONE) {
961 t4_intr_disable(adap);
962 if (adap->flags & USING_MSIX) {
963 free_msix_queue_irqs(adap);
964 free_irq(adap->msix_info[0].vec, adap);
965 } else {
966 free_irq(adap->pdev->irq, adap);
967 }
968 quiesce_rx(adap);
969 }
970}
971
b8ff05a9
DM		 972/*
973 * Enable NAPI scheduling and interrupt generation for all Rx queues.
974 */
975static void enable_rx(struct adapter *adap)
976{
977 int i;
978
4b8e27a8 979 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 980 struct sge_rspq *q = adap->sge.ingr_map[i];
981
982 if (!q)
983 continue;
3a336cb1
HS		 984 if (q->handler) {
985 cxgb_busy_poll_init_lock(q);
b8ff05a9 986 napi_enable(&q->napi);
3a336cb1 987 }
b8ff05a9 988 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 989 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
990 SEINTARM_V(q->intr_params) |
991 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 992 }
993}
994
1c6a5b0e
HS		 995static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
996 unsigned int nq, unsigned int per_chan, int msi_idx,
997 u16 *ids)
998{
999 int i, err;
1000
1001 for (i = 0; i < nq; i++, q++) {
1002 if (msi_idx > 0)
1003 msi_idx++;
1004 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1005 adap->port[i / per_chan],
1006 msi_idx, q->fl.size ? &q->fl : NULL,
145ef8a5 1007 uldrx_handler, 0);
1c6a5b0e
HS		 1008 if (err)
1009 return err;
1010 memset(&q->stats, 0, sizeof(q->stats));
1011 if (ids)
1012 ids[i] = q->rspq.abs_id;
1013 }
1014 return 0;
1015}
1016
b8ff05a9
DM		 1017/**
1018 * setup_sge_queues - configure SGE Tx/Rx/response queues
1019 * @adap: the adapter
1020 *
1021 * Determines how many sets of SGE queues to use and initializes them.
1022 * We support multiple queue sets per port if we have MSI-X, otherwise
1023 * just one queue set per port.
1024 */
1025static int setup_sge_queues(struct adapter *adap)
1026{
1027 int err, msi_idx, i, j;
1028 struct sge *s = &adap->sge;
1029
4b8e27a8
HS		 1030 bitmap_zero(s->starving_fl, s->egr_sz);
1031 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 1032
1033 if (adap->flags & USING_MSIX)
1034 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1035 else {
1036 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
145ef8a5 1037 NULL, NULL, -1);
b8ff05a9
DM		 1038 if (err)
1039 return err;
1040 msi_idx = -((int)s->intrq.abs_id + 1);
1041 }
1042
4b8e27a8
HS		 1043 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1044 * don't forget to update the following which need to be
1045 * synchronized to and changes here.
1046 *
1047 * 1. The calculations of MAX_INGQ in cxgb4.h.
1048 *
1049 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1050 * to accommodate any new/deleted Ingress Queues
1051 * which need MSI-X Vectors.
1052 *
1053 * 3. Update sge_qinfo_show() to include information on the
1054 * new/deleted queues.
1055 */
b8ff05a9 1056 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
145ef8a5 1057 msi_idx, NULL, fwevtq_handler, -1);
b8ff05a9
DM		 1058 if (err) {
1059freeout: t4_free_sge_resources(adap);
1060 return err;
1061 }
1062
1063 for_each_port(adap, i) {
1064 struct net_device *dev = adap->port[i];
1065 struct port_info *pi = netdev_priv(dev);
1066 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1067 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1068
1069 for (j = 0; j < pi->nqsets; j++, q++) {
1070 if (msi_idx > 0)
1071 msi_idx++;
1072 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1073 msi_idx, &q->fl,
145ef8a5
HS		 1074 t4_ethrx_handler,
1075 t4_get_mps_bg_map(adap,
1076 pi->tx_chan));
b8ff05a9
DM		 1077 if (err)
1078 goto freeout;
1079 q->rspq.idx = j;
1080 memset(&q->stats, 0, sizeof(q->stats));
1081 }
1082 for (j = 0; j < pi->nqsets; j++, t++) {
1083 err = t4_sge_alloc_eth_txq(adap, t, dev,
1084 netdev_get_tx_queue(dev, j),
1085 s->fw_evtq.cntxt_id);
1086 if (err)
1087 goto freeout;
1088 }
1089 }
1090
1091 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1092 for_each_ofldrxq(s, i) {
1c6a5b0e
HS		 1093 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1094 adap->port[i / j],
b8ff05a9
DM		 1095 s->fw_evtq.cntxt_id);
1096 if (err)
1097 goto freeout;
1098 }
1099
1c6a5b0e
HS		 1100#define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1101 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1102 if (err) \
1103 goto freeout; \
1104 if (msi_idx > 0) \
1105 msi_idx += nq; \
1106} while (0)
b8ff05a9 1107
1c6a5b0e
HS		 1108 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1109 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
f36e58e5
HS		 1110 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1111 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
b8ff05a9 1112
1c6a5b0e 1113#undef ALLOC_OFLD_RXQS
cf38be6d 1114
b8ff05a9
DM		 1115 for_each_port(adap, i) {
1116 /*
1117 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1118 * have RDMA queues, and that's the right value.
1119 */
1120 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1121 s->fw_evtq.cntxt_id,
1122 s->rdmarxq[i].rspq.cntxt_id);
1123 if (err)
1124 goto freeout;
1125 }
1126
9bb59b96 1127 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 1128 MPS_TRC_RSS_CONTROL_A :
1129 MPS_T5_TRC_RSS_CONTROL_A,
1130 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1131 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9
DM		 1132 return 0;
1133}
1134
b8ff05a9
DM		 1135/*
1136 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1137 * The allocated memory is cleared.
1138 */
1139void *t4_alloc_mem(size_t size)
1140{
8be04b93 1141 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1142
1143 if (!p)
89bf67f1 1144 p = vzalloc(size);
b8ff05a9
DM		 1145 return p;
1146}
1147
1148/*
1149 * Free memory allocated through alloc_mem().
1150 */
fd88b31a 1151void t4_free_mem(void *addr)
b8ff05a9
DM		 1152{
1153 if (is_vmalloc_addr(addr))
1154 vfree(addr);
1155 else
1156 kfree(addr);
1157}
1158
f2b7e78d
VP		 1159/* Send a Work Request to write the filter at a specified index. We construct
1160 * a Firmware Filter Work Request to have the work done and put the indicated
1161 * filter into "pending" mode which will prevent any further actions against
1162 * it till we get a reply from the firmware on the completion status of the
1163 * request.
1164 */
1165static int set_filter_wr(struct adapter *adapter, int fidx)
1166{
1167 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1168 struct sk_buff *skb;
1169 struct fw_filter_wr *fwr;
1170 unsigned int ftid;
1171
f72f116a
MH		 1172 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1173 if (!skb)
1174 return -ENOMEM;
1175
f2b7e78d
VP		 1176 /* If the new filter requires loopback Destination MAC and/or VLAN
1177 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1178 * the filter.
1179 */
1180 if (f->fs.newdmac || f->fs.newvlan) {
1181 /* allocate L2T entry for new filter */
1182 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
f72f116a
MH		 1183 if (f->l2t == NULL) {
1184 kfree_skb(skb);
f2b7e78d 1185 return -EAGAIN;
f72f116a 1186 }
f2b7e78d
VP		 1187 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1188 f->fs.eport, f->fs.dmac)) {
1189 cxgb4_l2t_release(f->l2t);
1190 f->l2t = NULL;
f72f116a 1191 kfree_skb(skb);
f2b7e78d
VP		 1192 return -ENOMEM;
1193 }
1194 }
1195
1196 ftid = adapter->tids.ftid_base + fidx;
1197
f2b7e78d
VP		 1198 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1199 memset(fwr, 0, sizeof(*fwr));
1200
1201 /* It would be nice to put most of the following in t4_hw.c but most
1202 * of the work is translating the cxgbtool ch_filter_specification
1203 * into the Work Request and the definition of that structure is
1204 * currently in cxgbtool.h which isn't appropriate to pull into the
1205 * common code. We may eventually try to come up with a more neutral
1206 * filter specification structure but for now it's easiest to simply
1207 * put this fairly direct code in line ...
1208 */
e2ac9628
HS		 1209 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1210 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
f2b7e78d 1211 fwr->tid_to_iq =
77a80e23
HS		 1212 htonl(FW_FILTER_WR_TID_V(ftid) |
1213 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1214 FW_FILTER_WR_NOREPLY_V(0) |
1215 FW_FILTER_WR_IQ_V(f->fs.iq));
f2b7e78d 1216 fwr->del_filter_to_l2tix =
77a80e23
HS		 1217 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1218 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1219 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1220 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1221 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1222 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1223 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1224 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1225 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f2b7e78d 1226 f->fs.newvlan == VLAN_REWRITE) |
77a80e23 1227 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
f2b7e78d 1228 f->fs.newvlan == VLAN_REWRITE) |
77a80e23
HS		 1229 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1230 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1231 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1232 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
f2b7e78d
VP		 1233 fwr->ethtype = htons(f->fs.val.ethtype);
1234 fwr->ethtypem = htons(f->fs.mask.ethtype);
1235 fwr->frag_to_ovlan_vldm =
77a80e23
HS		 1236 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1237 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1238 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1239 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1240 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1241 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
f2b7e78d
VP		 1242 fwr->smac_sel = 0;
1243 fwr->rx_chan_rx_rpl_iq =
77a80e23
HS		 1244 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1245 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
f2b7e78d 1246 fwr->maci_to_matchtypem =
77a80e23
HS		 1247 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1248 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1249 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1250 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1251 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1252 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1253 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1254 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
f2b7e78d
VP		 1255 fwr->ptcl = f->fs.val.proto;
1256 fwr->ptclm = f->fs.mask.proto;
1257 fwr->ttyp = f->fs.val.tos;
1258 fwr->ttypm = f->fs.mask.tos;
1259 fwr->ivlan = htons(f->fs.val.ivlan);
1260 fwr->ivlanm = htons(f->fs.mask.ivlan);
1261 fwr->ovlan = htons(f->fs.val.ovlan);
1262 fwr->ovlanm = htons(f->fs.mask.ovlan);
1263 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1264 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1265 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1266 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1267 fwr->lp = htons(f->fs.val.lport);
1268 fwr->lpm = htons(f->fs.mask.lport);
1269 fwr->fp = htons(f->fs.val.fport);
1270 fwr->fpm = htons(f->fs.mask.fport);
1271 if (f->fs.newsmac)
1272 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1273
1274 /* Mark the filter as "pending" and ship off the Filter Work Request.
1275 * When we get the Work Request Reply we'll clear the pending status.
1276 */
1277 f->pending = 1;
1278 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1279 t4_ofld_send(adapter, skb);
1280 return 0;
1281}
1282
1283/* Delete the filter at a specified index.
1284 */
1285static int del_filter_wr(struct adapter *adapter, int fidx)
1286{
1287 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1288 struct sk_buff *skb;
1289 struct fw_filter_wr *fwr;
1290 unsigned int len, ftid;
1291
1292 len = sizeof(*fwr);
1293 ftid = adapter->tids.ftid_base + fidx;
1294
f72f116a
MH		 1295 skb = alloc_skb(len, GFP_KERNEL);
1296 if (!skb)
1297 return -ENOMEM;
1298
f2b7e78d
VP		 1299 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1300 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1301
1302 /* Mark the filter as "pending" and ship off the Filter Work Request.
1303 * When we get the Work Request Reply we'll clear the pending status.
1304 */
1305 f->pending = 1;
1306 t4_mgmt_tx(adapter, skb);
1307 return 0;
1308}
1309
688848b1
AB		 1310static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1311 void *accel_priv, select_queue_fallback_t fallback)
1312{
1313 int txq;
1314
1315#ifdef CONFIG_CHELSIO_T4_DCB
1316 /* If a Data Center Bridging has been successfully negotiated on this
1317 * link then we'll use the skb's priority to map it to a TX Queue.
1318 * The skb's priority is determined via the VLAN Tag Priority Code
1319 * Point field.
1320 */
1321 if (cxgb4_dcb_enabled(dev)) {
1322 u16 vlan_tci;
1323 int err;
1324
1325 err = vlan_get_tag(skb, &vlan_tci);
1326 if (unlikely(err)) {
1327 if (net_ratelimit())
1328 netdev_warn(dev,
1329 "TX Packet without VLAN Tag on DCB Link\n");
1330 txq = 0;
1331 } else {
1332 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 1333#ifdef CONFIG_CHELSIO_T4_FCOE
1334 if (skb->protocol == htons(ETH_P_FCOE))
1335 txq = skb->priority & 0x7;
1336#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 1337 }
1338 return txq;
1339 }
1340#endif /* CONFIG_CHELSIO_T4_DCB */
1341
1342 if (select_queue) {
1343 txq = (skb_rx_queue_recorded(skb)
1344 ? skb_get_rx_queue(skb)
1345 : smp_processor_id());
1346
1347 while (unlikely(txq >= dev->real_num_tx_queues))
1348 txq -= dev->real_num_tx_queues;
1349
1350 return txq;
1351 }
1352
1353 return fallback(dev, skb) % dev->real_num_tx_queues;
1354}
1355
b8ff05a9
DM		 1356static int closest_timer(const struct sge *s, int time)
1357{
1358 int i, delta, match = 0, min_delta = INT_MAX;
1359
1360 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1361 delta = time - s->timer_val[i];
1362 if (delta < 0)
1363 delta = -delta;
1364 if (delta < min_delta) {
1365 min_delta = delta;
1366 match = i;
1367 }
1368 }
1369 return match;
1370}
1371
1372static int closest_thres(const struct sge *s, int thres)
1373{
1374 int i, delta, match = 0, min_delta = INT_MAX;
1375
1376 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1377 delta = thres - s->counter_val[i];
1378 if (delta < 0)
1379 delta = -delta;
1380 if (delta < min_delta) {
1381 min_delta = delta;
1382 match = i;
1383 }
1384 }
1385 return match;
1386}
1387
b8ff05a9 1388/**
812034f1 1389 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1390 * @q: the Rx queue
1391 * @us: the hold-off time in us, or 0 to disable timer
1392 * @cnt: the hold-off packet count, or 0 to disable counter
1393 *
1394 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1395 * one of the two needs to be enabled for the queue to generate interrupts.
1396 */
812034f1
HS		 1397int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1398 unsigned int us, unsigned int cnt)
b8ff05a9 1399{
c887ad0e
HS		 1400 struct adapter *adap = q->adap;
1401
b8ff05a9
DM		 1402 if ((us | cnt) == 0)
1403 cnt = 1;
1404
1405 if (cnt) {
1406 int err;
1407 u32 v, new_idx;
1408
1409 new_idx = closest_thres(&adap->sge, cnt);
1410 if (q->desc && q->pktcnt_idx != new_idx) {
1411 /* the queue has already been created, update it */
5167865a
HS		 1412 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1413 FW_PARAMS_PARAM_X_V(
1414 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1415 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1416 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1417 &v, &new_idx);
b8ff05a9
DM		 1418 if (err)
1419 return err;
1420 }
1421 q->pktcnt_idx = new_idx;
1422 }
1423
1424 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1425 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1426 return 0;
1427}
1428
c8f44aff 1429static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1430{
2ed28baa 1431 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1432 netdev_features_t changed = dev->features ^ features;
19ecae2c 1433 int err;
19ecae2c 1434
f646968f 1435 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1436 return 0;
19ecae2c 1437
b2612722 1438 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1439 -1, -1, -1,
f646968f 1440 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1441 if (unlikely(err))
f646968f 1442 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1443 return err;
87b6cf51
DM		 1444}
1445
91744948 1446static int setup_debugfs(struct adapter *adap)
b8ff05a9 1447{
b8ff05a9
DM		 1448 if (IS_ERR_OR_NULL(adap->debugfs_root))
1449 return -1;
1450
fd88b31a
HS		 1451#ifdef CONFIG_DEBUG_FS
1452 t4_setup_debugfs(adap);
1453#endif
b8ff05a9
DM		 1454 return 0;
1455}
1456
1457/*
1458 * upper-layer driver support
1459 */
1460
1461/*
1462 * Allocate an active-open TID and set it to the supplied value.
1463 */
1464int cxgb4_alloc_atid(struct tid_info *t, void *data)
1465{
1466 int atid = -1;
1467
1468 spin_lock_bh(&t->atid_lock);
1469 if (t->afree) {
1470 union aopen_entry *p = t->afree;
1471
f2b7e78d 1472 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1473 t->afree = p->next;
1474 p->data = data;
1475 t->atids_in_use++;
1476 }
1477 spin_unlock_bh(&t->atid_lock);
1478 return atid;
1479}
1480EXPORT_SYMBOL(cxgb4_alloc_atid);
1481
1482/*
1483 * Release an active-open TID.
1484 */
1485void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1486{
f2b7e78d 1487 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1488
1489 spin_lock_bh(&t->atid_lock);
1490 p->next = t->afree;
1491 t->afree = p;
1492 t->atids_in_use--;
1493 spin_unlock_bh(&t->atid_lock);
1494}
1495EXPORT_SYMBOL(cxgb4_free_atid);
1496
1497/*
1498 * Allocate a server TID and set it to the supplied value.
1499 */
1500int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1501{
1502 int stid;
1503
1504 spin_lock_bh(&t->stid_lock);
1505 if (family == PF_INET) {
1506 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1507 if (stid < t->nstids)
1508 __set_bit(stid, t->stid_bmap);
1509 else
1510 stid = -1;
1511 } else {
1512 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1513 if (stid < 0)
1514 stid = -1;
1515 }
1516 if (stid >= 0) {
1517 t->stid_tab[stid].data = data;
1518 stid += t->stid_base;
15f63b74
KS		 1519 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1520 * This is equivalent to 4 TIDs. With CLIP enabled it
1521 * needs 2 TIDs.
1522 */
1523 if (family == PF_INET)
1524 t->stids_in_use++;
1525 else
1526 t->stids_in_use += 4;
b8ff05a9
DM		 1527 }
1528 spin_unlock_bh(&t->stid_lock);
1529 return stid;
1530}
1531EXPORT_SYMBOL(cxgb4_alloc_stid);
1532
dca4faeb
VP		 1533/* Allocate a server filter TID and set it to the supplied value.
1534 */
1535int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1536{
1537 int stid;
1538
1539 spin_lock_bh(&t->stid_lock);
1540 if (family == PF_INET) {
1541 stid = find_next_zero_bit(t->stid_bmap,
1542 t->nstids + t->nsftids, t->nstids);
1543 if (stid < (t->nstids + t->nsftids))
1544 __set_bit(stid, t->stid_bmap);
1545 else
1546 stid = -1;
1547 } else {
1548 stid = -1;
1549 }
1550 if (stid >= 0) {
1551 t->stid_tab[stid].data = data;
470c60c4
KS		 1552 stid -= t->nstids;
1553 stid += t->sftid_base;
dca4faeb
VP		 1554 t->stids_in_use++;
1555 }
1556 spin_unlock_bh(&t->stid_lock);
1557 return stid;
1558}
1559EXPORT_SYMBOL(cxgb4_alloc_sftid);
1560
1561/* Release a server TID.
b8ff05a9
DM		 1562 */
1563void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1564{
470c60c4
KS		 1565 /* Is it a server filter TID? */
1566 if (t->nsftids && (stid >= t->sftid_base)) {
1567 stid -= t->sftid_base;
1568 stid += t->nstids;
1569 } else {
1570 stid -= t->stid_base;
1571 }
1572
b8ff05a9
DM		 1573 spin_lock_bh(&t->stid_lock);
1574 if (family == PF_INET)
1575 __clear_bit(stid, t->stid_bmap);
1576 else
1577 bitmap_release_region(t->stid_bmap, stid, 2);
1578 t->stid_tab[stid].data = NULL;
15f63b74
KS		 1579 if (family == PF_INET)
1580 t->stids_in_use--;
1581 else
1582 t->stids_in_use -= 4;
b8ff05a9
DM		 1583 spin_unlock_bh(&t->stid_lock);
1584}
1585EXPORT_SYMBOL(cxgb4_free_stid);
1586
1587/*
1588 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1589 */
1590static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1591 unsigned int tid)
1592{
1593 struct cpl_tid_release *req;
1594
1595 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1596 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1597 INIT_TP_WR(req, tid);
1598 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1599}
1600
1601/*
1602 * Queue a TID release request and if necessary schedule a work queue to
1603 * process it.
1604 */
31b9c19b 1605static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1606 unsigned int tid)
b8ff05a9
DM		 1607{
1608 void **p = &t->tid_tab[tid];
1609 struct adapter *adap = container_of(t, struct adapter, tids);
1610
1611 spin_lock_bh(&adap->tid_release_lock);
1612 *p = adap->tid_release_head;
1613 /* Low 2 bits encode the Tx channel number */
1614 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1615 if (!adap->tid_release_task_busy) {
1616 adap->tid_release_task_busy = true;
29aaee65 1617 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1618 }
1619 spin_unlock_bh(&adap->tid_release_lock);
1620}
b8ff05a9
DM		 1621
1622/*
1623 * Process the list of pending TID release requests.
1624 */
1625static void process_tid_release_list(struct work_struct *work)
1626{
1627 struct sk_buff *skb;
1628 struct adapter *adap;
1629
1630 adap = container_of(work, struct adapter, tid_release_task);
1631
1632 spin_lock_bh(&adap->tid_release_lock);
1633 while (adap->tid_release_head) {
1634 void **p = adap->tid_release_head;
1635 unsigned int chan = (uintptr_t)p & 3;
1636 p = (void *)p - chan;
1637
1638 adap->tid_release_head = *p;
1639 *p = NULL;
1640 spin_unlock_bh(&adap->tid_release_lock);
1641
1642 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1643 GFP_KERNEL)))
1644 schedule_timeout_uninterruptible(1);
1645
1646 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1647 t4_ofld_send(adap, skb);
1648 spin_lock_bh(&adap->tid_release_lock);
1649 }
1650 adap->tid_release_task_busy = false;
1651 spin_unlock_bh(&adap->tid_release_lock);
1652}
1653
1654/*
1655 * Release a TID and inform HW. If we are unable to allocate the release
1656 * message we defer to a work queue.
1657 */
1658void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1659{
1660 void *old;
1661 struct sk_buff *skb;
1662 struct adapter *adap = container_of(t, struct adapter, tids);
1663
1664 old = t->tid_tab[tid];
1665 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1666 if (likely(skb)) {
1667 t->tid_tab[tid] = NULL;
1668 mk_tid_release(skb, chan, tid);
1669 t4_ofld_send(adap, skb);
1670 } else
1671 cxgb4_queue_tid_release(t, chan, tid);
1672 if (old)
1673 atomic_dec(&t->tids_in_use);
1674}
1675EXPORT_SYMBOL(cxgb4_remove_tid);
1676
1677/*
1678 * Allocate and initialize the TID tables. Returns 0 on success.
1679 */
1680static int tid_init(struct tid_info *t)
1681{
1682 size_t size;
f2b7e78d 1683 unsigned int stid_bmap_size;
b8ff05a9 1684 unsigned int natids = t->natids;
b6f8eaec 1685 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 1686
dca4faeb 1687 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 1688 size = t->ntids * sizeof(*t->tid_tab) +
1689 natids * sizeof(*t->atid_tab) +
b8ff05a9 1690 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1691 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1692 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 1693 t->nftids * sizeof(*t->ftid_tab) +
1694 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 1695
b8ff05a9
DM		 1696 t->tid_tab = t4_alloc_mem(size);
1697 if (!t->tid_tab)
1698 return -ENOMEM;
1699
1700 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1701 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1702 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1703 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 1704 spin_lock_init(&t->stid_lock);
1705 spin_lock_init(&t->atid_lock);
1706
1707 t->stids_in_use = 0;
1708 t->afree = NULL;
1709 t->atids_in_use = 0;
1710 atomic_set(&t->tids_in_use, 0);
1711
1712 /* Setup the free list for atid_tab and clear the stid bitmap. */
1713 if (natids) {
1714 while (--natids)
1715 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1716 t->afree = t->atid_tab;
1717 }
dca4faeb 1718 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 1719 /* Reserve stid 0 for T4/T5 adapters */
1720 if (!t->stid_base &&
3ccc6cf7 1721 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
b6f8eaec
KS		 1722 __set_bit(0, t->stid_bmap);
1723
b8ff05a9
DM		 1724 return 0;
1725}
1726
1727/**
1728 * cxgb4_create_server - create an IP server
1729 * @dev: the device
1730 * @stid: the server TID
1731 * @sip: local IP address to bind server to
1732 * @sport: the server's TCP port
1733 * @queue: queue to direct messages from this server to
1734 *
1735 * Create an IP server for the given port and address.
1736 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1737 */
1738int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1739 __be32 sip, __be16 sport, __be16 vlan,
1740 unsigned int queue)
b8ff05a9
DM		 1741{
1742 unsigned int chan;
1743 struct sk_buff *skb;
1744 struct adapter *adap;
1745 struct cpl_pass_open_req *req;
80f40c1f 1746 int ret;
b8ff05a9
DM		 1747
1748 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1749 if (!skb)
1750 return -ENOMEM;
1751
1752 adap = netdev2adap(dev);
1753 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1754 INIT_TP_WR(req, 0);
1755 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1756 req->local_port = sport;
1757 req->peer_port = htons(0);
1758 req->local_ip = sip;
1759 req->peer_ip = htonl(0);
e46dab4d 1760 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1761 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1762 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1763 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1764 ret = t4_mgmt_tx(adap, skb);
1765 return net_xmit_eval(ret);
b8ff05a9
DM		 1766}
1767EXPORT_SYMBOL(cxgb4_create_server);
1768
80f40c1f
VP		 1769/* cxgb4_create_server6 - create an IPv6 server
1770 * @dev: the device
1771 * @stid: the server TID
1772 * @sip: local IPv6 address to bind server to
1773 * @sport: the server's TCP port
1774 * @queue: queue to direct messages from this server to
1775 *
1776 * Create an IPv6 server for the given port and address.
1777 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1778 */
1779int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1780 const struct in6_addr *sip, __be16 sport,
1781 unsigned int queue)
1782{
1783 unsigned int chan;
1784 struct sk_buff *skb;
1785 struct adapter *adap;
1786 struct cpl_pass_open_req6 *req;
1787 int ret;
1788
1789 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1790 if (!skb)
1791 return -ENOMEM;
1792
1793 adap = netdev2adap(dev);
1794 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1795 INIT_TP_WR(req, 0);
1796 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1797 req->local_port = sport;
1798 req->peer_port = htons(0);
1799 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1800 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1801 req->peer_ip_hi = cpu_to_be64(0);
1802 req->peer_ip_lo = cpu_to_be64(0);
1803 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1804 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1805 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1806 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1807 ret = t4_mgmt_tx(adap, skb);
1808 return net_xmit_eval(ret);
1809}
1810EXPORT_SYMBOL(cxgb4_create_server6);
1811
1812int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1813 unsigned int queue, bool ipv6)
1814{
1815 struct sk_buff *skb;
1816 struct adapter *adap;
1817 struct cpl_close_listsvr_req *req;
1818 int ret;
1819
1820 adap = netdev2adap(dev);
1821
1822 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1823 if (!skb)
1824 return -ENOMEM;
1825
1826 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1827 INIT_TP_WR(req, 0);
1828 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1829 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1830 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1831 ret = t4_mgmt_tx(adap, skb);
1832 return net_xmit_eval(ret);
1833}
1834EXPORT_SYMBOL(cxgb4_remove_server);
1835
b8ff05a9
DM		 1836/**
1837 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1838 * @mtus: the HW MTU table
1839 * @mtu: the target MTU
1840 * @idx: index of selected entry in the MTU table
1841 *
1842 * Returns the index and the value in the HW MTU table that is closest to
1843 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1844 * table, in which case that smallest available value is selected.
1845 */
1846unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1847 unsigned int *idx)
1848{
1849 unsigned int i = 0;
1850
1851 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1852 ++i;
1853 if (idx)
1854 *idx = i;
1855 return mtus[i];
1856}
1857EXPORT_SYMBOL(cxgb4_best_mtu);
1858
92e7ae71
HS		 1859/**
1860 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1861 * @mtus: the HW MTU table
1862 * @header_size: Header Size
1863 * @data_size_max: maximum Data Segment Size
1864 * @data_size_align: desired Data Segment Size Alignment (2^N)
1865 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1866 *
1867 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1868 * MTU Table based solely on a Maximum MTU parameter, we break that
1869 * parameter up into a Header Size and Maximum Data Segment Size, and
1870 * provide a desired Data Segment Size Alignment. If we find an MTU in
1871 * the Hardware MTU Table which will result in a Data Segment Size with
1872 * the requested alignment _and_ that MTU isn't "too far" from the
1873 * closest MTU, then we'll return that rather than the closest MTU.
1874 */
1875unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1876 unsigned short header_size,
1877 unsigned short data_size_max,
1878 unsigned short data_size_align,
1879 unsigned int *mtu_idxp)
1880{
1881 unsigned short max_mtu = header_size + data_size_max;
1882 unsigned short data_size_align_mask = data_size_align - 1;
1883 int mtu_idx, aligned_mtu_idx;
1884
1885 /* Scan the MTU Table till we find an MTU which is larger than our
1886 * Maximum MTU or we reach the end of the table. Along the way,
1887 * record the last MTU found, if any, which will result in a Data
1888 * Segment Length matching the requested alignment.
1889 */
1890 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1891 unsigned short data_size = mtus[mtu_idx] - header_size;
1892
1893 /* If this MTU minus the Header Size would result in a
1894 * Data Segment Size of the desired alignment, remember it.
1895 */
1896 if ((data_size & data_size_align_mask) == 0)
1897 aligned_mtu_idx = mtu_idx;
1898
1899 /* If we're not at the end of the Hardware MTU Table and the
1900 * next element is larger than our Maximum MTU, drop out of
1901 * the loop.
1902 */
1903 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1904 break;
1905 }
1906
1907 /* If we fell out of the loop because we ran to the end of the table,
1908 * then we just have to use the last [largest] entry.
1909 */
1910 if (mtu_idx == NMTUS)
1911 mtu_idx--;
1912
1913 /* If we found an MTU which resulted in the requested Data Segment
1914 * Length alignment and that's "not far" from the largest MTU which is
1915 * less than or equal to the maximum MTU, then use that.
1916 */
1917 if (aligned_mtu_idx >= 0 &&
1918 mtu_idx - aligned_mtu_idx <= 1)
1919 mtu_idx = aligned_mtu_idx;
1920
1921 /* If the caller has passed in an MTU Index pointer, pass the
1922 * MTU Index back. Return the MTU value.
1923 */
1924 if (mtu_idxp)
1925 *mtu_idxp = mtu_idx;
1926 return mtus[mtu_idx];
1927}
1928EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1929
b8ff05a9
DM		 1930/**
1931 * cxgb4_port_chan - get the HW channel of a port
1932 * @dev: the net device for the port
1933 *
1934 * Return the HW Tx channel of the given port.
1935 */
1936unsigned int cxgb4_port_chan(const struct net_device *dev)
1937{
1938 return netdev2pinfo(dev)->tx_chan;
1939}
1940EXPORT_SYMBOL(cxgb4_port_chan);
1941
881806bc
VP		 1942unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1943{
1944 struct adapter *adap = netdev2adap(dev);
2cc301d2 1945 u32 v1, v2, lp_count, hp_count;
881806bc 1946
f061de42
HS		 1947 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1948 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1949 if (is_t4(adap->params.chip)) {
f061de42
HS		 1950 lp_count = LP_COUNT_G(v1);
1951 hp_count = HP_COUNT_G(v1);
2cc301d2 1952 } else {
f061de42
HS		 1953 lp_count = LP_COUNT_T5_G(v1);
1954 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1955 }
1956 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1957}
1958EXPORT_SYMBOL(cxgb4_dbfifo_count);
1959
b8ff05a9
DM		 1960/**
1961 * cxgb4_port_viid - get the VI id of a port
1962 * @dev: the net device for the port
1963 *
1964 * Return the VI id of the given port.
1965 */
1966unsigned int cxgb4_port_viid(const struct net_device *dev)
1967{
1968 return netdev2pinfo(dev)->viid;
1969}
1970EXPORT_SYMBOL(cxgb4_port_viid);
1971
1972/**
1973 * cxgb4_port_idx - get the index of a port
1974 * @dev: the net device for the port
1975 *
1976 * Return the index of the given port.
1977 */
1978unsigned int cxgb4_port_idx(const struct net_device *dev)
1979{
1980 return netdev2pinfo(dev)->port_id;
1981}
1982EXPORT_SYMBOL(cxgb4_port_idx);
1983
b8ff05a9
DM		 1984void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1985 struct tp_tcp_stats *v6)
1986{
1987 struct adapter *adap = pci_get_drvdata(pdev);
1988
1989 spin_lock(&adap->stats_lock);
1990 t4_tp_get_tcp_stats(adap, v4, v6);
1991 spin_unlock(&adap->stats_lock);
1992}
1993EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1994
1995void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1996 const unsigned int *pgsz_order)
1997{
1998 struct adapter *adap = netdev2adap(dev);
1999
0d804338
HS		 2000 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2001 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2002 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2003 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 2004}
2005EXPORT_SYMBOL(cxgb4_iscsi_init);
2006
3069ee9b
VP		 2007int cxgb4_flush_eq_cache(struct net_device *dev)
2008{
2009 struct adapter *adap = netdev2adap(dev);
3069ee9b 2010
5d700ecb 2011 return t4_sge_ctxt_flush(adap, adap->mbox);
3069ee9b
VP		 2012}
2013EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2014
2015static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2016{
f061de42 2017 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 2018 __be64 indices;
2019 int ret;
2020
fc5ab020
HS		 2021 spin_lock(&adap->win0_lock);
2022 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2023 sizeof(indices), (__be32 *)&indices,
2024 T4_MEMORY_READ);
2025 spin_unlock(&adap->win0_lock);
3069ee9b 2026 if (!ret) {
404d9e3f
VP		 2027 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2028 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 2029 }
2030 return ret;
2031}
2032
2033int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2034 u16 size)
2035{
2036 struct adapter *adap = netdev2adap(dev);
2037 u16 hw_pidx, hw_cidx;
2038 int ret;
2039
2040 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2041 if (ret)
2042 goto out;
2043
2044 if (pidx != hw_pidx) {
2045 u16 delta;
f612b815 2046 u32 val;
3069ee9b
VP		 2047
2048 if (pidx >= hw_pidx)
2049 delta = pidx - hw_pidx;
2050 else
2051 delta = size - hw_pidx + pidx;
f612b815
HS		 2052
2053 if (is_t4(adap->params.chip))
2054 val = PIDX_V(delta);
2055 else
2056 val = PIDX_T5_V(delta);
3069ee9b 2057 wmb();
f612b815
HS		 2058 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2059 QID_V(qid) | val);
3069ee9b
VP		 2060 }
2061out:
2062 return ret;
2063}
2064EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2065
031cf476
HS		 2066int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2067{
2068 struct adapter *adap;
2069 u32 offset, memtype, memaddr;
6559a7e8 2070 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476
HS		 2071 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2072 int ret;
2073
2074 adap = netdev2adap(dev);
2075
2076 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2077
2078 /* Figure out where the offset lands in the Memory Type/Address scheme.
2079 * This code assumes that the memory is laid out starting at offset 0
2080 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2081 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2082 * MC0, and some have both MC0 and MC1.
2083 */
6559a7e8
HS		 2084 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2085 edc0_size = EDRAM0_SIZE_G(size) << 20;
2086 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2087 edc1_size = EDRAM1_SIZE_G(size) << 20;
2088 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2089 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476
HS		 2090
2091 edc0_end = edc0_size;
2092 edc1_end = edc0_end + edc1_size;
2093 mc0_end = edc1_end + mc0_size;
2094
2095 if (offset < edc0_end) {
2096 memtype = MEM_EDC0;
2097 memaddr = offset;
2098 } else if (offset < edc1_end) {
2099 memtype = MEM_EDC1;
2100 memaddr = offset - edc0_end;
2101 } else {
2102 if (offset < mc0_end) {
2103 memtype = MEM_MC0;
2104 memaddr = offset - edc1_end;
3ccc6cf7 2105 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 2106 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2107 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 2108 mc1_end = mc0_end + mc1_size;
2109 if (offset < mc1_end) {
2110 memtype = MEM_MC1;
2111 memaddr = offset - mc0_end;
2112 } else {
2113 /* offset beyond the end of any memory */
2114 goto err;
2115 }
3ccc6cf7
HS		 2116 } else {
2117 /* T4/T6 only has a single memory channel */
2118 goto err;
031cf476
HS		 2119 }
2120 }
2121
2122 spin_lock(&adap->win0_lock);
2123 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2124 spin_unlock(&adap->win0_lock);
2125 return ret;
2126
2127err:
2128 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2129 stag, offset);
2130 return -EINVAL;
2131}
2132EXPORT_SYMBOL(cxgb4_read_tpte);
2133
7730b4c7
HS		 2134u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2135{
2136 u32 hi, lo;
2137 struct adapter *adap;
2138
2139 adap = netdev2adap(dev);
f612b815
HS		 2140 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2141 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 2142
2143 return ((u64)hi << 32) | (u64)lo;
2144}
2145EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2146
df64e4d3
HS		 2147int cxgb4_bar2_sge_qregs(struct net_device *dev,
2148 unsigned int qid,
2149 enum cxgb4_bar2_qtype qtype,
2150 u64 *pbar2_qoffset,
2151 unsigned int *pbar2_qid)
2152{
b2612722 2153 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 2154 qid,
2155 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2156 ? T4_BAR2_QTYPE_EGRESS
2157 : T4_BAR2_QTYPE_INGRESS),
2158 pbar2_qoffset,
2159 pbar2_qid);
2160}
2161EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2162
b8ff05a9
DM		 2163static struct pci_driver cxgb4_driver;
2164
2165static void check_neigh_update(struct neighbour *neigh)
2166{
2167 const struct device *parent;
2168 const struct net_device *netdev = neigh->dev;
2169
2170 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2171 netdev = vlan_dev_real_dev(netdev);
2172 parent = netdev->dev.parent;
2173 if (parent && parent->driver == &cxgb4_driver.driver)
2174 t4_l2t_update(dev_get_drvdata(parent), neigh);
2175}
2176
2177static int netevent_cb(struct notifier_block *nb, unsigned long event,
2178 void *data)
2179{
2180 switch (event) {
2181 case NETEVENT_NEIGH_UPDATE:
2182 check_neigh_update(data);
2183 break;
b8ff05a9
DM		 2184 case NETEVENT_REDIRECT:
2185 default:
2186 break;
2187 }
2188 return 0;
2189}
2190
2191static bool netevent_registered;
2192static struct notifier_block cxgb4_netevent_nb = {
2193 .notifier_call = netevent_cb
2194};
2195
3069ee9b
VP		 2196static void drain_db_fifo(struct adapter *adap, int usecs)
2197{
2cc301d2 2198 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 2199
2200 do {
f061de42
HS		 2201 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2202 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 2203 if (is_t4(adap->params.chip)) {
f061de42
HS		 2204 lp_count = LP_COUNT_G(v1);
2205 hp_count = HP_COUNT_G(v1);
2cc301d2 2206 } else {
f061de42
HS		 2207 lp_count = LP_COUNT_T5_G(v1);
2208 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 2209 }
2210
2211 if (lp_count == 0 && hp_count == 0)
2212 break;
3069ee9b
VP		 2213 set_current_state(TASK_UNINTERRUPTIBLE);
2214 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 2215 } while (1);
2216}
2217
2218static void disable_txq_db(struct sge_txq *q)
2219{
05eb2389
SW		 2220 unsigned long flags;
2221
2222 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 2223 q->db_disabled = 1;
05eb2389 2224 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 2225}
2226
05eb2389 2227static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 2228{
2229 spin_lock_irq(&q->db_lock);
05eb2389
SW		 2230 if (q->db_pidx_inc) {
2231 /* Make sure that all writes to the TX descriptors
2232 * are committed before we tell HW about them.
2233 */
2234 wmb();
f612b815
HS		 2235 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2236 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 2237 q->db_pidx_inc = 0;
2238 }
3069ee9b
VP		 2239 q->db_disabled = 0;
2240 spin_unlock_irq(&q->db_lock);
2241}
2242
2243static void disable_dbs(struct adapter *adap)
2244{
2245 int i;
2246
2247 for_each_ethrxq(&adap->sge, i)
2248 disable_txq_db(&adap->sge.ethtxq[i].q);
2249 for_each_ofldrxq(&adap->sge, i)
2250 disable_txq_db(&adap->sge.ofldtxq[i].q);
2251 for_each_port(adap, i)
2252 disable_txq_db(&adap->sge.ctrlq[i].q);
2253}
2254
2255static void enable_dbs(struct adapter *adap)
2256{
2257 int i;
2258
2259 for_each_ethrxq(&adap->sge, i)
05eb2389 2260 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 2261 for_each_ofldrxq(&adap->sge, i)
05eb2389 2262 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 2263 for_each_port(adap, i)
05eb2389
SW		 2264 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2265}
2266
2267static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2268{
2269 if (adap->uld_handle[CXGB4_ULD_RDMA])
2270 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2271 cmd);
2272}
2273
2274static void process_db_full(struct work_struct *work)
2275{
2276 struct adapter *adap;
2277
2278 adap = container_of(work, struct adapter, db_full_task);
2279
2280 drain_db_fifo(adap, dbfifo_drain_delay);
2281 enable_dbs(adap);
2282 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 2283 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2284 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2285 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2286 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2287 else
2288 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2289 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 2290}
2291
2292static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2293{
2294 u16 hw_pidx, hw_cidx;
2295 int ret;
2296
05eb2389 2297 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 2298 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2299 if (ret)
2300 goto out;
2301 if (q->db_pidx != hw_pidx) {
2302 u16 delta;
f612b815 2303 u32 val;
3069ee9b
VP		 2304
2305 if (q->db_pidx >= hw_pidx)
2306 delta = q->db_pidx - hw_pidx;
2307 else
2308 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 2309
2310 if (is_t4(adap->params.chip))
2311 val = PIDX_V(delta);
2312 else
2313 val = PIDX_T5_V(delta);
3069ee9b 2314 wmb();
f612b815
HS		 2315 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2316 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2317 }
2318out:
2319 q->db_disabled = 0;
05eb2389
SW		 2320 q->db_pidx_inc = 0;
2321 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2322 if (ret)
2323 CH_WARN(adap, "DB drop recovery failed.\n");
2324}
2325static void recover_all_queues(struct adapter *adap)
2326{
2327 int i;
2328
2329 for_each_ethrxq(&adap->sge, i)
2330 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2331 for_each_ofldrxq(&adap->sge, i)
2332 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2333 for_each_port(adap, i)
2334 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2335}
2336
881806bc
VP		 2337static void process_db_drop(struct work_struct *work)
2338{
2339 struct adapter *adap;
881806bc 2340
3069ee9b 2341 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2342
d14807dd 2343 if (is_t4(adap->params.chip)) {
05eb2389 2344 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2345 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2346 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2347 recover_all_queues(adap);
05eb2389 2348 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2349 enable_dbs(adap);
05eb2389 2350 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2351 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2352 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2353 u16 qid = (dropped_db >> 15) & 0x1ffff;
2354 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2355 u64 bar2_qoffset;
2356 unsigned int bar2_qid;
2357 int ret;
2cc301d2 2358
b2612722 2359 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
df64e4d3
HS		 2360 &bar2_qoffset, &bar2_qid);
2361 if (ret)
2362 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2363 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2364 else
f612b815 2365 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2366 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2367
2368 /* Re-enable BAR2 WC */
2369 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2370 }
2371
3ccc6cf7
HS		 2372 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2373 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2374}
2375
2376void t4_db_full(struct adapter *adap)
2377{
d14807dd 2378 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2379 disable_dbs(adap);
2380 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2381 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2382 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2383 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2384 }
881806bc
VP		 2385}
2386
2387void t4_db_dropped(struct adapter *adap)
2388{
05eb2389
SW		 2389 if (is_t4(adap->params.chip)) {
2390 disable_dbs(adap);
2391 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2392 }
29aaee65 2393 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2394}
2395
b8ff05a9
DM		 2396static void uld_attach(struct adapter *adap, unsigned int uld)
2397{
2398 void *handle;
2399 struct cxgb4_lld_info lli;
dca4faeb 2400 unsigned short i;
b8ff05a9
DM		 2401
2402 lli.pdev = adap->pdev;
b2612722 2403 lli.pf = adap->pf;
b8ff05a9
DM		 2404 lli.l2t = adap->l2t;
2405 lli.tids = &adap->tids;
2406 lli.ports = adap->port;
2407 lli.vr = &adap->vres;
2408 lli.mtus = adap->params.mtus;
2409 if (uld == CXGB4_ULD_RDMA) {
2410 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 2411 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 2412 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 2413 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM		 2414 } else if (uld == CXGB4_ULD_ISCSI) {
2415 lli.rxq_ids = adap->sge.ofld_rxq;
2416 lli.nrxq = adap->sge.ofldqsets;
2417 }
2418 lli.ntxq = adap->sge.ofldqsets;
2419 lli.nchan = adap->params.nports;
2420 lli.nports = adap->params.nports;
2421 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 2422 lli.adapter_type = adap->params.chip;
837e4a42 2423 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
7730b4c7 2424 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
df64e4d3
HS		 2425 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2426 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
dcf7b6f5 2427 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 2428 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2429 for (i = 0; i < NCHAN; i++)
2430 lli.tx_modq[i] = i;
f612b815
HS		 2431 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2432 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
b8ff05a9 2433 lli.fw_vers = adap->params.fw_vers;
3069ee9b 2434 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS		 2435 lli.sge_ingpadboundary = adap->sge.fl_align;
2436 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP		 2437 lli.sge_pktshift = adap->sge.pktshift;
2438 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS		 2439 lli.max_ordird_qp = adap->params.max_ordird_qp;
2440 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 2441 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
982b81eb 2442 lli.nodeid = dev_to_node(adap->pdev_dev);
b8ff05a9
DM		 2443
2444 handle = ulds[uld].add(&lli);
2445 if (IS_ERR(handle)) {
2446 dev_warn(adap->pdev_dev,
2447 "could not attach to the %s driver, error %ld\n",
2448 uld_str[uld], PTR_ERR(handle));
2449 return;
2450 }
2451
2452 adap->uld_handle[uld] = handle;
2453
2454 if (!netevent_registered) {
2455 register_netevent_notifier(&cxgb4_netevent_nb);
2456 netevent_registered = true;
2457 }
e29f5dbc
DM		 2458
2459 if (adap->flags & FULL_INIT_DONE)
2460 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 2461}
2462
2463static void attach_ulds(struct adapter *adap)
2464{
2465 unsigned int i;
2466
01bcca68
VP		 2467 spin_lock(&adap_rcu_lock);
2468 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2469 spin_unlock(&adap_rcu_lock);
2470
b8ff05a9
DM		 2471 mutex_lock(&uld_mutex);
2472 list_add_tail(&adap->list_node, &adapter_list);
2473 for (i = 0; i < CXGB4_ULD_MAX; i++)
2474 if (ulds[i].add)
2475 uld_attach(adap, i);
2476 mutex_unlock(&uld_mutex);
2477}
2478
2479static void detach_ulds(struct adapter *adap)
2480{
2481 unsigned int i;
2482
2483 mutex_lock(&uld_mutex);
2484 list_del(&adap->list_node);
2485 for (i = 0; i < CXGB4_ULD_MAX; i++)
2486 if (adap->uld_handle[i]) {
2487 ulds[i].state_change(adap->uld_handle[i],
2488 CXGB4_STATE_DETACH);
2489 adap->uld_handle[i] = NULL;
2490 }
2491 if (netevent_registered && list_empty(&adapter_list)) {
2492 unregister_netevent_notifier(&cxgb4_netevent_nb);
2493 netevent_registered = false;
2494 }
2495 mutex_unlock(&uld_mutex);
01bcca68
VP		 2496
2497 spin_lock(&adap_rcu_lock);
2498 list_del_rcu(&adap->rcu_node);
2499 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 2500}
2501
2502static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2503{
2504 unsigned int i;
2505
2506 mutex_lock(&uld_mutex);
2507 for (i = 0; i < CXGB4_ULD_MAX; i++)
2508 if (adap->uld_handle[i])
2509 ulds[i].state_change(adap->uld_handle[i], new_state);
2510 mutex_unlock(&uld_mutex);
2511}
2512
2513/**
2514 * cxgb4_register_uld - register an upper-layer driver
2515 * @type: the ULD type
2516 * @p: the ULD methods
2517 *
2518 * Registers an upper-layer driver with this driver and notifies the ULD
2519 * about any presently available devices that support its type. Returns
2520 * %-EBUSY if a ULD of the same type is already registered.
2521 */
2522int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2523{
2524 int ret = 0;
2525 struct adapter *adap;
2526
2527 if (type >= CXGB4_ULD_MAX)
2528 return -EINVAL;
2529 mutex_lock(&uld_mutex);
2530 if (ulds[type].add) {
2531 ret = -EBUSY;
2532 goto out;
2533 }
2534 ulds[type] = *p;
2535 list_for_each_entry(adap, &adapter_list, list_node)
2536 uld_attach(adap, type);
2537out: mutex_unlock(&uld_mutex);
2538 return ret;
2539}
2540EXPORT_SYMBOL(cxgb4_register_uld);
2541
2542/**
2543 * cxgb4_unregister_uld - unregister an upper-layer driver
2544 * @type: the ULD type
2545 *
2546 * Unregisters an existing upper-layer driver.
2547 */
2548int cxgb4_unregister_uld(enum cxgb4_uld type)
2549{
2550 struct adapter *adap;
2551
2552 if (type >= CXGB4_ULD_MAX)
2553 return -EINVAL;
2554 mutex_lock(&uld_mutex);
2555 list_for_each_entry(adap, &adapter_list, list_node)
2556 adap->uld_handle[type] = NULL;
2557 ulds[type].add = NULL;
2558 mutex_unlock(&uld_mutex);
2559 return 0;
2560}
2561EXPORT_SYMBOL(cxgb4_unregister_uld);
2562
1bb60376 2563#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2564static int cxgb4_inet6addr_handler(struct notifier_block *this,
2565 unsigned long event, void *data)
01bcca68 2566{
b5a02f50
AB		 2567 struct inet6_ifaddr *ifa = data;
2568 struct net_device *event_dev = ifa->idev->dev;
2569 const struct device *parent = NULL;
2570#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2571 struct adapter *adap;
b5a02f50
AB		 2572#endif
2573 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2574 event_dev = vlan_dev_real_dev(event_dev);
2575#if IS_ENABLED(CONFIG_BONDING)
2576 if (event_dev->flags & IFF_MASTER) {
2577 list_for_each_entry(adap, &adapter_list, list_node) {
2578 switch (event) {
2579 case NETDEV_UP:
2580 cxgb4_clip_get(adap->port[0],
2581 (const u32 *)ifa, 1);
2582 break;
2583 case NETDEV_DOWN:
2584 cxgb4_clip_release(adap->port[0],
2585 (const u32 *)ifa, 1);
2586 break;
2587 default:
2588 break;
2589 }
2590 }
2591 return NOTIFY_OK;
2592 }
2593#endif
01bcca68 2594
b5a02f50
AB		 2595 if (event_dev)
2596 parent = event_dev->dev.parent;
01bcca68 2597
b5a02f50 2598 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2599 switch (event) {
2600 case NETDEV_UP:
b5a02f50 2601 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2602 break;
2603 case NETDEV_DOWN:
b5a02f50 2604 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2605 break;
2606 default:
2607 break;
2608 }
2609 }
b5a02f50 2610 return NOTIFY_OK;
01bcca68
VP		 2611}
2612
b5a02f50 2613static bool inet6addr_registered;
01bcca68
VP		 2614static struct notifier_block cxgb4_inet6addr_notifier = {
2615 .notifier_call = cxgb4_inet6addr_handler
2616};
2617
01bcca68
VP		 2618static void update_clip(const struct adapter *adap)
2619{
2620 int i;
2621 struct net_device *dev;
2622 int ret;
2623
2624 rcu_read_lock();
2625
2626 for (i = 0; i < MAX_NPORTS; i++) {
2627 dev = adap->port[i];
2628 ret = 0;
2629
2630 if (dev)
b5a02f50 2631 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2632
2633 if (ret < 0)
2634 break;
2635 }
2636 rcu_read_unlock();
2637}
1bb60376 2638#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2639
b8ff05a9
DM		 2640/**
2641 * cxgb_up - enable the adapter
2642 * @adap: adapter being enabled
2643 *
2644 * Called when the first port is enabled, this function performs the
2645 * actions necessary to make an adapter operational, such as completing
2646 * the initialization of HW modules, and enabling interrupts.
2647 *
2648 * Must be called with the rtnl lock held.
2649 */
2650static int cxgb_up(struct adapter *adap)
2651{
aaefae9b 2652 int err;
b8ff05a9 2653
aaefae9b
DM		 2654 err = setup_sge_queues(adap);
2655 if (err)
2656 goto out;
2657 err = setup_rss(adap);
2658 if (err)
2659 goto freeq;
b8ff05a9
DM		 2660
2661 if (adap->flags & USING_MSIX) {
aaefae9b 2662 name_msix_vecs(adap);
b8ff05a9
DM		 2663 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2664 adap->msix_info[0].desc, adap);
2665 if (err)
2666 goto irq_err;
2667
2668 err = request_msix_queue_irqs(adap);
2669 if (err) {
2670 free_irq(adap->msix_info[0].vec, adap);
2671 goto irq_err;
2672 }
2673 } else {
2674 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2675 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2676 adap->port[0]->name, adap);
b8ff05a9
DM		 2677 if (err)
2678 goto irq_err;
2679 }
2680 enable_rx(adap);
2681 t4_sge_start(adap);
2682 t4_intr_enable(adap);
aaefae9b 2683 adap->flags |= FULL_INIT_DONE;
b8ff05a9 2684 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2685#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2686 update_clip(adap);
1bb60376 2687#endif
b8ff05a9
DM		 2688 out:
2689 return err;
2690 irq_err:
2691 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2692 freeq:
2693 t4_free_sge_resources(adap);
b8ff05a9
DM		 2694 goto out;
2695}
2696
2697static void cxgb_down(struct adapter *adapter)
2698{
b8ff05a9 2699 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2700 cancel_work_sync(&adapter->db_full_task);
2701 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2702 adapter->tid_release_task_busy = false;
204dc3c0 2703 adapter->tid_release_head = NULL;
b8ff05a9 2704
aaefae9b
DM		 2705 t4_sge_stop(adapter);
2706 t4_free_sge_resources(adapter);
2707 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2708}
2709
2710/*
2711 * net_device operations
2712 */
2713static int cxgb_open(struct net_device *dev)
2714{
2715 int err;
2716 struct port_info *pi = netdev_priv(dev);
2717 struct adapter *adapter = pi->adapter;
2718
6a3c869a
DM		 2719 netif_carrier_off(dev);
2720
aaefae9b
DM		 2721 if (!(adapter->flags & FULL_INIT_DONE)) {
2722 err = cxgb_up(adapter);
2723 if (err < 0)
2724 return err;
2725 }
b8ff05a9 2726
f68707b8
DM		 2727 err = link_start(dev);
2728 if (!err)
2729 netif_tx_start_all_queues(dev);
2730 return err;
b8ff05a9
DM		 2731}
2732
2733static int cxgb_close(struct net_device *dev)
2734{
b8ff05a9
DM		 2735 struct port_info *pi = netdev_priv(dev);
2736 struct adapter *adapter = pi->adapter;
2737
2738 netif_tx_stop_all_queues(dev);
2739 netif_carrier_off(dev);
b2612722 2740 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
b8ff05a9
DM		 2741}
2742
f2b7e78d
VP		 2743/* Return an error number if the indicated filter isn't writable ...
2744 */
2745static int writable_filter(struct filter_entry *f)
2746{
2747 if (f->locked)
2748 return -EPERM;
2749 if (f->pending)
2750 return -EBUSY;
2751
2752 return 0;
2753}
2754
2755/* Delete the filter at the specified index (if valid). The checks for all
2756 * the common problems with doing this like the filter being locked, currently
2757 * pending in another operation, etc.
2758 */
2759static int delete_filter(struct adapter *adapter, unsigned int fidx)
2760{
2761 struct filter_entry *f;
2762 int ret;
2763
dca4faeb 2764 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 2765 return -EINVAL;
2766
2767 f = &adapter->tids.ftid_tab[fidx];
2768 ret = writable_filter(f);
2769 if (ret)
2770 return ret;
2771 if (f->valid)
2772 return del_filter_wr(adapter, fidx);
2773
2774 return 0;
2775}
2776
dca4faeb 2777int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2778 __be32 sip, __be16 sport, __be16 vlan,
2779 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2780{
2781 int ret;
2782 struct filter_entry *f;
2783 struct adapter *adap;
2784 int i;
2785 u8 *val;
2786
2787 adap = netdev2adap(dev);
2788
1cab775c 2789 /* Adjust stid to correct filter index */
470c60c4 2790 stid -= adap->tids.sftid_base;
1cab775c
VP		 2791 stid += adap->tids.nftids;
2792
dca4faeb
VP		 2793 /* Check to make sure the filter requested is writable ...
2794 */
2795 f = &adap->tids.ftid_tab[stid];
2796 ret = writable_filter(f);
2797 if (ret)
2798 return ret;
2799
2800 /* Clear out any old resources being used by the filter before
2801 * we start constructing the new filter.
2802 */
2803 if (f->valid)
2804 clear_filter(adap, f);
2805
2806 /* Clear out filter specifications */
2807 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2808 f->fs.val.lport = cpu_to_be16(sport);
2809 f->fs.mask.lport = ~0;
2810 val = (u8 *)&sip;
793dad94 2811 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2812 for (i = 0; i < 4; i++) {
2813 f->fs.val.lip[i] = val[i];
2814 f->fs.mask.lip[i] = ~0;
2815 }
0d804338 2816 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2817 f->fs.val.iport = port;
2818 f->fs.mask.iport = mask;
2819 }
2820 }
dca4faeb 2821
0d804338 2822 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2823 f->fs.val.proto = IPPROTO_TCP;
2824 f->fs.mask.proto = ~0;
2825 }
2826
dca4faeb
VP		 2827 f->fs.dirsteer = 1;
2828 f->fs.iq = queue;
2829 /* Mark filter as locked */
2830 f->locked = 1;
2831 f->fs.rpttid = 1;
2832
2833 ret = set_filter_wr(adap, stid);
2834 if (ret) {
2835 clear_filter(adap, f);
2836 return ret;
2837 }
2838
2839 return 0;
2840}
2841EXPORT_SYMBOL(cxgb4_create_server_filter);
2842
2843int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2844 unsigned int queue, bool ipv6)
2845{
2846 int ret;
2847 struct filter_entry *f;
2848 struct adapter *adap;
2849
2850 adap = netdev2adap(dev);
1cab775c
VP		 2851
2852 /* Adjust stid to correct filter index */
470c60c4 2853 stid -= adap->tids.sftid_base;
1cab775c
VP		 2854 stid += adap->tids.nftids;
2855
dca4faeb
VP		 2856 f = &adap->tids.ftid_tab[stid];
2857 /* Unlock the filter */
2858 f->locked = 0;
2859
2860 ret = delete_filter(adap, stid);
2861 if (ret)
2862 return ret;
2863
2864 return 0;
2865}
2866EXPORT_SYMBOL(cxgb4_remove_server_filter);
2867
f5152c90
DM		 2868static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2869 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2870{
2871 struct port_stats stats;
2872 struct port_info *p = netdev_priv(dev);
2873 struct adapter *adapter = p->adapter;
b8ff05a9 2874
9fe6cb58
GS		 2875 /* Block retrieving statistics during EEH error
2876 * recovery. Otherwise, the recovery might fail
2877 * and the PCI device will be removed permanently
2878 */
b8ff05a9 2879 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2880 if (!netif_device_present(dev)) {
2881 spin_unlock(&adapter->stats_lock);
2882 return ns;
2883 }
a4cfd929
HS		 2884 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2885 &p->stats_base);
b8ff05a9
DM		 2886 spin_unlock(&adapter->stats_lock);
2887
2888 ns->tx_bytes = stats.tx_octets;
2889 ns->tx_packets = stats.tx_frames;
2890 ns->rx_bytes = stats.rx_octets;
2891 ns->rx_packets = stats.rx_frames;
2892 ns->multicast = stats.rx_mcast_frames;
2893
2894 /* detailed rx_errors */
2895 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2896 stats.rx_runt;
2897 ns->rx_over_errors = 0;
2898 ns->rx_crc_errors = stats.rx_fcs_err;
2899 ns->rx_frame_errors = stats.rx_symbol_err;
2900 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2901 stats.rx_ovflow2 + stats.rx_ovflow3 +
2902 stats.rx_trunc0 + stats.rx_trunc1 +
2903 stats.rx_trunc2 + stats.rx_trunc3;
2904 ns->rx_missed_errors = 0;
2905
2906 /* detailed tx_errors */
2907 ns->tx_aborted_errors = 0;
2908 ns->tx_carrier_errors = 0;
2909 ns->tx_fifo_errors = 0;
2910 ns->tx_heartbeat_errors = 0;
2911 ns->tx_window_errors = 0;
2912
2913 ns->tx_errors = stats.tx_error_frames;
2914 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2915 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2916 return ns;
2917}
2918
2919static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2920{
060e0c75 2921 unsigned int mbox;
b8ff05a9
DM		 2922 int ret = 0, prtad, devad;
2923 struct port_info *pi = netdev_priv(dev);
2924 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2925
2926 switch (cmd) {
2927 case SIOCGMIIPHY:
2928 if (pi->mdio_addr < 0)
2929 return -EOPNOTSUPP;
2930 data->phy_id = pi->mdio_addr;
2931 break;
2932 case SIOCGMIIREG:
2933 case SIOCSMIIREG:
2934 if (mdio_phy_id_is_c45(data->phy_id)) {
2935 prtad = mdio_phy_id_prtad(data->phy_id);
2936 devad = mdio_phy_id_devad(data->phy_id);
2937 } else if (data->phy_id < 32) {
2938 prtad = data->phy_id;
2939 devad = 0;
2940 data->reg_num &= 0x1f;
2941 } else
2942 return -EINVAL;
2943
b2612722 2944 mbox = pi->adapter->pf;
b8ff05a9 2945 if (cmd == SIOCGMIIREG)
060e0c75 2946 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2947 data->reg_num, &data->val_out);
2948 else
060e0c75 2949 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2950 data->reg_num, data->val_in);
2951 break;
2952 default:
2953 return -EOPNOTSUPP;
2954 }
2955 return ret;
2956}
2957
2958static void cxgb_set_rxmode(struct net_device *dev)
2959{
2960 /* unfortunately we can't return errors to the stack */
2961 set_rxmode(dev, -1, false);
2962}
2963
2964static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2965{
2966 int ret;
2967 struct port_info *pi = netdev_priv(dev);
2968
2969 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2970 return -EINVAL;
b2612722 2971 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2972 -1, -1, -1, true);
b8ff05a9
DM		 2973 if (!ret)
2974 dev->mtu = new_mtu;
2975 return ret;
2976}
2977
2978static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2979{
2980 int ret;
2981 struct sockaddr *addr = p;
2982 struct port_info *pi = netdev_priv(dev);
2983
2984 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2985 return -EADDRNOTAVAIL;
b8ff05a9 2986
b2612722 2987 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
060e0c75 2988 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 2989 if (ret < 0)
2990 return ret;
2991
2992 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2993 pi->xact_addr_filt = ret;
2994 return 0;
2995}
2996
b8ff05a9
DM		 2997#ifdef CONFIG_NET_POLL_CONTROLLER
2998static void cxgb_netpoll(struct net_device *dev)
2999{
3000 struct port_info *pi = netdev_priv(dev);
3001 struct adapter *adap = pi->adapter;
3002
3003 if (adap->flags & USING_MSIX) {
3004 int i;
3005 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3006
3007 for (i = pi->nqsets; i; i--, rx++)
3008 t4_sge_intr_msix(0, &rx->rspq);
3009 } else
3010 t4_intr_handler(adap)(0, adap);
3011}
3012#endif
3013
3014static const struct net_device_ops cxgb4_netdev_ops = {
3015 .ndo_open = cxgb_open,
3016 .ndo_stop = cxgb_close,
3017 .ndo_start_xmit = t4_eth_xmit,
688848b1 3018 .ndo_select_queue = cxgb_select_queue,
9be793bf 3019 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3020 .ndo_set_rx_mode = cxgb_set_rxmode,
3021 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3022 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3023 .ndo_validate_addr = eth_validate_addr,
3024 .ndo_do_ioctl = cxgb_ioctl,
3025 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3026#ifdef CONFIG_NET_POLL_CONTROLLER
3027 .ndo_poll_controller = cxgb_netpoll,
3028#endif
84a200b3
VP		 3029#ifdef CONFIG_CHELSIO_T4_FCOE
3030 .ndo_fcoe_enable = cxgb_fcoe_enable,
3031 .ndo_fcoe_disable = cxgb_fcoe_disable,
3032#endif /* CONFIG_CHELSIO_T4_FCOE */
3a336cb1
HS		 3033#ifdef CONFIG_NET_RX_BUSY_POLL
3034 .ndo_busy_poll = cxgb_busy_poll,
3035#endif
3036
b8ff05a9
DM		 3037};
3038
3039void t4_fatal_err(struct adapter *adap)
3040{
f612b815 3041 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
b8ff05a9
DM		 3042 t4_intr_disable(adap);
3043 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3044}
3045
3046static void setup_memwin(struct adapter *adap)
3047{
b562fc37 3048 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3049
b562fc37 3050 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3051}
3052
3053static void setup_memwin_rdma(struct adapter *adap)
3054{
1ae970e0 3055 if (adap->vres.ocq.size) {
0abfd152
HS		 3056 u32 start;
3057 unsigned int sz_kb;
1ae970e0 3058
0abfd152
HS		 3059 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3060 start &= PCI_BASE_ADDRESS_MEM_MASK;
3061 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3062 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3063 t4_write_reg(adap,
f061de42
HS		 3064 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3065 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3066 t4_write_reg(adap,
f061de42 3067 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3068 adap->vres.ocq.start);
3069 t4_read_reg(adap,
f061de42 3070 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3071 }
b8ff05a9
DM		 3072}
3073
02b5fb8e
DM		 3074static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3075{
3076 u32 v;
3077 int ret;
3078
3079 /* get device capabilities */
3080 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3081 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3082 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3083 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3084 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3085 if (ret < 0)
3086 return ret;
3087
3088 /* select capabilities we'll be using */
3089 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3090 if (!vf_acls)
3091 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3092 else
3093 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3094 } else if (vf_acls) {
3095 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3096 return ret;
3097 }
e2ac9628
HS		 3098 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3099 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3100 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3101 if (ret < 0)
3102 return ret;
3103
b2612722 3104 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3105 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3106 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3107 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3108 if (ret < 0)
3109 return ret;
3110
b2612722 3111 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3112 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3113 FW_CMD_CAP_PF);
02b5fb8e
DM		 3114 if (ret < 0)
3115 return ret;
3116
3117 t4_sge_init(adap);
3118
02b5fb8e 3119 /* tweak some settings */
837e4a42 3120 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3121 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3122 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3123 v = t4_read_reg(adap, TP_PIO_DATA_A);
3124 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3125
dca4faeb
VP		 3126 /* first 4 Tx modulation queues point to consecutive Tx channels */
3127 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3128 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3129 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3130
3131 /* associate each Tx modulation queue with consecutive Tx channels */
3132 v = 0x84218421;
837e4a42 3133 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3134 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3135 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3136 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3137 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3138 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3139
3140#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3141 if (is_offload(adap)) {
0d804338
HS		 3142 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3143 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3144 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3145 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3146 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3147 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3148 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3149 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3150 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3151 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3152 }
3153
060e0c75 3154 /* get basic stuff going */
b2612722 3155 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3156}
3157
b8ff05a9
DM		 3158/*
3159 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3160 */
3161#define MAX_ATIDS 8192U
3162
636f9d37
VP		 3163/*
3164 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3165 *
3166 * If the firmware we're dealing with has Configuration File support, then
3167 * we use that to perform all configuration
3168 */
3169
3170/*
3171 * Tweak configuration based on module parameters, etc. Most of these have
3172 * defaults assigned to them by Firmware Configuration Files (if we're using
3173 * them) but need to be explicitly set if we're using hard-coded
3174 * initialization. But even in the case of using Firmware Configuration
3175 * Files, we'd like to expose the ability to change these via module
3176 * parameters so these are essentially common tweaks/settings for
3177 * Configuration Files and hard-coded initialization ...
3178 */
3179static int adap_init0_tweaks(struct adapter *adapter)
3180{
3181 /*
3182 * Fix up various Host-Dependent Parameters like Page Size, Cache
3183 * Line Size, etc. The firmware default is for a 4KB Page Size and
3184 * 64B Cache Line Size ...
3185 */
3186 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3187
3188 /*
3189 * Process module parameters which affect early initialization.
3190 */
3191 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3192 dev_err(&adapter->pdev->dev,
3193 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3194 rx_dma_offset);
3195 rx_dma_offset = 2;
3196 }
f612b815
HS		 3197 t4_set_reg_field(adapter, SGE_CONTROL_A,
3198 PKTSHIFT_V(PKTSHIFT_M),
3199 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3200
3201 /*
3202 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3203 * adds the pseudo header itself.
3204 */
837e4a42
HS		 3205 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3206 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3207
3208 return 0;
3209}
3210
01b69614
HS		 3211/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3212 * unto themselves and they contain their own firmware to perform their
3213 * tasks ...
3214 */
3215static int phy_aq1202_version(const u8 *phy_fw_data,
3216 size_t phy_fw_size)
3217{
3218 int offset;
3219
3220 /* At offset 0x8 you're looking for the primary image's
3221 * starting offset which is 3 Bytes wide
3222 *
3223 * At offset 0xa of the primary image, you look for the offset
3224 * of the DRAM segment which is 3 Bytes wide.
3225 *
3226 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3227 * wide
3228 */
3229 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3230 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3231 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3232
3233 offset = le24(phy_fw_data + 0x8) << 12;
3234 offset = le24(phy_fw_data + offset + 0xa);
3235 return be16(phy_fw_data + offset + 0x27e);
3236
3237 #undef be16
3238 #undef le16
3239 #undef le24
3240}
3241
3242static struct info_10gbt_phy_fw {
3243 unsigned int phy_fw_id; /* PCI Device ID */
3244 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3245 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3246 int phy_flash; /* Has FLASH for PHY Firmware */
3247} phy_info_array[] = {
3248 {
3249 PHY_AQ1202_DEVICEID,
3250 PHY_AQ1202_FIRMWARE,
3251 phy_aq1202_version,
3252 1,
3253 },
3254 {
3255 PHY_BCM84834_DEVICEID,
3256 PHY_BCM84834_FIRMWARE,
3257 NULL,
3258 0,
3259 },
3260 { 0, NULL, NULL },
3261};
3262
3263static struct info_10gbt_phy_fw *find_phy_info(int devid)
3264{
3265 int i;
3266
3267 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3268 if (phy_info_array[i].phy_fw_id == devid)
3269 return &phy_info_array[i];
3270 }
3271 return NULL;
3272}
3273
3274/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3275 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3276 * we return a negative error number. If we transfer new firmware we return 1
3277 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3278 */
3279static int adap_init0_phy(struct adapter *adap)
3280{
3281 const struct firmware *phyf;
3282 int ret;
3283 struct info_10gbt_phy_fw *phy_info;
3284
3285 /* Use the device ID to determine which PHY file to flash.
3286 */
3287 phy_info = find_phy_info(adap->pdev->device);
3288 if (!phy_info) {
3289 dev_warn(adap->pdev_dev,
3290 "No PHY Firmware file found for this PHY\n");
3291 return -EOPNOTSUPP;
3292 }
3293
3294 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3295 * use that. The adapter firmware provides us with a memory buffer
3296 * where we can load a PHY firmware file from the host if we want to
3297 * override the PHY firmware File in flash.
3298 */
3299 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3300 adap->pdev_dev);
3301 if (ret < 0) {
3302 /* For adapters without FLASH attached to PHY for their
3303 * firmware, it's obviously a fatal error if we can't get the
3304 * firmware to the adapter. For adapters with PHY firmware
3305 * FLASH storage, it's worth a warning if we can't find the
3306 * PHY Firmware but we'll neuter the error ...
3307 */
3308 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3309 "/lib/firmware/%s, error %d\n",
3310 phy_info->phy_fw_file, -ret);
3311 if (phy_info->phy_flash) {
3312 int cur_phy_fw_ver = 0;
3313
3314 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3315 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3316 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3317 ret = 0;
3318 }
3319
3320 return ret;
3321 }
3322
3323 /* Load PHY Firmware onto adapter.
3324 */
3325 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3326 phy_info->phy_fw_version,
3327 (u8 *)phyf->data, phyf->size);
3328 if (ret < 0)
3329 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3330 -ret);
3331 else if (ret > 0) {
3332 int new_phy_fw_ver = 0;
3333
3334 if (phy_info->phy_fw_version)
3335 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3336 phyf->size);
3337 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3338 "Firmware /lib/firmware/%s, version %#x\n",
3339 phy_info->phy_fw_file, new_phy_fw_ver);
3340 }
3341
3342 release_firmware(phyf);
3343
3344 return ret;
3345}
3346
636f9d37
VP		 3347/*
3348 * Attempt to initialize the adapter via a Firmware Configuration File.
3349 */
3350static int adap_init0_config(struct adapter *adapter, int reset)
3351{
3352 struct fw_caps_config_cmd caps_cmd;
3353 const struct firmware *cf;
3354 unsigned long mtype = 0, maddr = 0;
3355 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3356 int ret;
3357 int config_issued = 0;
0a57a536 3358 char *fw_config_file, fw_config_file_path[256];
16e47624 3359 char *config_name = NULL;
636f9d37
VP		 3360
3361 /*
3362 * Reset device if necessary.
3363 */
3364 if (reset) {
3365 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3366 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3367 if (ret < 0)
3368 goto bye;
3369 }
3370
01b69614
HS		 3371 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3372 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3373 * to be performed after any global adapter RESET above since some
3374 * PHYs only have local RAM copies of the PHY firmware.
3375 */
3376 if (is_10gbt_device(adapter->pdev->device)) {
3377 ret = adap_init0_phy(adapter);
3378 if (ret < 0)
3379 goto bye;
3380 }
636f9d37
VP		 3381 /*
3382 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3383 * then use that. Otherwise, use the configuration file stored
3384 * in the adapter flash ...
3385 */
d14807dd 3386 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3387 case CHELSIO_T4:
16e47624 3388 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3389 break;
3390 case CHELSIO_T5:
3391 fw_config_file = FW5_CFNAME;
3392 break;
3ccc6cf7
HS		 3393 case CHELSIO_T6:
3394 fw_config_file = FW6_CFNAME;
3395 break;
0a57a536
SR		 3396 default:
3397 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3398 adapter->pdev->device);
3399 ret = -EINVAL;
3400 goto bye;
3401 }
3402
3403 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3404 if (ret < 0) {
16e47624 3405 config_name = "On FLASH";
636f9d37
VP		 3406 mtype = FW_MEMTYPE_CF_FLASH;
3407 maddr = t4_flash_cfg_addr(adapter);
3408 } else {
3409 u32 params[7], val[7];
3410
16e47624
HS		 3411 sprintf(fw_config_file_path,
3412 "/lib/firmware/%s", fw_config_file);
3413 config_name = fw_config_file_path;
3414
636f9d37
VP		 3415 if (cf->size >= FLASH_CFG_MAX_SIZE)
3416 ret = -ENOMEM;
3417 else {
5167865a
HS		 3418 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3419 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 3420 ret = t4_query_params(adapter, adapter->mbox,
b2612722 3421 adapter->pf, 0, 1, params, val);
636f9d37
VP		 3422 if (ret == 0) {
3423 /*
fc5ab020 3424 * For t4_memory_rw() below addresses and
636f9d37
VP		 3425 * sizes have to be in terms of multiples of 4
3426 * bytes. So, if the Configuration File isn't
3427 * a multiple of 4 bytes in length we'll have
3428 * to write that out separately since we can't
3429 * guarantee that the bytes following the
3430 * residual byte in the buffer returned by
3431 * request_firmware() are zeroed out ...
3432 */
3433 size_t resid = cf->size & 0x3;
3434 size_t size = cf->size & ~0x3;
3435 __be32 *data = (__be32 *)cf->data;
3436
5167865a
HS		 3437 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3438 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3439
fc5ab020
HS		 3440 spin_lock(&adapter->win0_lock);
3441 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3442 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3443 if (ret == 0 && resid != 0) {
3444 union {
3445 __be32 word;
3446 char buf[4];
3447 } last;
3448 int i;
3449
3450 last.word = data[size >> 2];
3451 for (i = resid; i < 4; i++)
3452 last.buf[i] = 0;
fc5ab020
HS		 3453 ret = t4_memory_rw(adapter, 0, mtype,
3454 maddr + size,
3455 4, &last.word,
3456 T4_MEMORY_WRITE);
636f9d37 3457 }
fc5ab020 3458 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3459 }
3460 }
3461
3462 release_firmware(cf);
3463 if (ret)
3464 goto bye;
3465 }
3466
3467 /*
3468 * Issue a Capability Configuration command to the firmware to get it
3469 * to parse the Configuration File. We don't use t4_fw_config_file()
3470 * because we want the ability to modify various features after we've
3471 * processed the configuration file ...
3472 */
3473 memset(&caps_cmd, 0, sizeof(caps_cmd));
3474 caps_cmd.op_to_write =
e2ac9628
HS		 3475 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3476 FW_CMD_REQUEST_F |
3477 FW_CMD_READ_F);
ce91a923 3478 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3479 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3480 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3481 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3482 FW_LEN16(caps_cmd));
3483 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3484 &caps_cmd);
16e47624
HS		 3485
3486 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3487 * Configuration File in FLASH), our last gasp effort is to use the
3488 * Firmware Configuration File which is embedded in the firmware. A
3489 * very few early versions of the firmware didn't have one embedded
3490 * but we can ignore those.
3491 */
3492 if (ret == -ENOENT) {
3493 memset(&caps_cmd, 0, sizeof(caps_cmd));
3494 caps_cmd.op_to_write =
e2ac9628
HS		 3495 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3496 FW_CMD_REQUEST_F |
3497 FW_CMD_READ_F);
16e47624
HS		 3498 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3499 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3500 sizeof(caps_cmd), &caps_cmd);
3501 config_name = "Firmware Default";
3502 }
3503
3504 config_issued = 1;
636f9d37
VP		 3505 if (ret < 0)
3506 goto bye;
3507
3508 finiver = ntohl(caps_cmd.finiver);
3509 finicsum = ntohl(caps_cmd.finicsum);
3510 cfcsum = ntohl(caps_cmd.cfcsum);
3511 if (finicsum != cfcsum)
3512 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3513 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3514 finicsum, cfcsum);
3515
636f9d37
VP		 3516 /*
3517 * And now tell the firmware to use the configuration we just loaded.
3518 */
3519 caps_cmd.op_to_write =
e2ac9628
HS		 3520 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3521 FW_CMD_REQUEST_F |
3522 FW_CMD_WRITE_F);
ce91a923 3523 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3524 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3525 NULL);
3526 if (ret < 0)
3527 goto bye;
3528
3529 /*
3530 * Tweak configuration based on system architecture, module
3531 * parameters, etc.
3532 */
3533 ret = adap_init0_tweaks(adapter);
3534 if (ret < 0)
3535 goto bye;
3536
3537 /*
3538 * And finally tell the firmware to initialize itself using the
3539 * parameters from the Configuration File.
3540 */
3541 ret = t4_fw_initialize(adapter, adapter->mbox);
3542 if (ret < 0)
3543 goto bye;
3544
06640310
HS		 3545 /* Emit Firmware Configuration File information and return
3546 * successfully.
636f9d37 3547 */
636f9d37 3548 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 3549 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3550 config_name, finiver, cfcsum);
636f9d37
VP		 3551 return 0;
3552
3553 /*
3554 * Something bad happened. Return the error ... (If the "error"
3555 * is that there's no Configuration File on the adapter we don't
3556 * want to issue a warning since this is fairly common.)
3557 */
3558bye:
16e47624
HS		 3559 if (config_issued && ret != -ENOENT)
3560 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3561 config_name, -ret);
636f9d37
VP		 3562 return ret;
3563}
3564
16e47624
HS		 3565static struct fw_info fw_info_array[] = {
3566 {
3567 .chip = CHELSIO_T4,
3568 .fs_name = FW4_CFNAME,
3569 .fw_mod_name = FW4_FNAME,
3570 .fw_hdr = {
3571 .chip = FW_HDR_CHIP_T4,
3572 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3573 .intfver_nic = FW_INTFVER(T4, NIC),
3574 .intfver_vnic = FW_INTFVER(T4, VNIC),
3575 .intfver_ri = FW_INTFVER(T4, RI),
3576 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3577 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3578 },
3579 }, {
3580 .chip = CHELSIO_T5,
3581 .fs_name = FW5_CFNAME,
3582 .fw_mod_name = FW5_FNAME,
3583 .fw_hdr = {
3584 .chip = FW_HDR_CHIP_T5,
3585 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3586 .intfver_nic = FW_INTFVER(T5, NIC),
3587 .intfver_vnic = FW_INTFVER(T5, VNIC),
3588 .intfver_ri = FW_INTFVER(T5, RI),
3589 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3590 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3591 },
3ccc6cf7
HS		 3592 }, {
3593 .chip = CHELSIO_T6,
3594 .fs_name = FW6_CFNAME,
3595 .fw_mod_name = FW6_FNAME,
3596 .fw_hdr = {
3597 .chip = FW_HDR_CHIP_T6,
3598 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3599 .intfver_nic = FW_INTFVER(T6, NIC),
3600 .intfver_vnic = FW_INTFVER(T6, VNIC),
3601 .intfver_ofld = FW_INTFVER(T6, OFLD),
3602 .intfver_ri = FW_INTFVER(T6, RI),
3603 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3604 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3605 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3606 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3607 },
16e47624 3608 }
3ccc6cf7 3609
16e47624
HS		 3610};
3611
3612static struct fw_info *find_fw_info(int chip)
3613{
3614 int i;
3615
3616 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3617 if (fw_info_array[i].chip == chip)
3618 return &fw_info_array[i];
3619 }
3620 return NULL;
3621}
3622
b8ff05a9
DM		 3623/*
3624 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3625 */
3626static int adap_init0(struct adapter *adap)
3627{
3628 int ret;
3629 u32 v, port_vec;
3630 enum dev_state state;
3631 u32 params[7], val[7];
9a4da2cd 3632 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 3633 int reset = 1;
b8ff05a9 3634
ae469b68
HS		 3635 /* Grab Firmware Device Log parameters as early as possible so we have
3636 * access to it for debugging, etc.
3637 */
3638 ret = t4_init_devlog_params(adap);
3639 if (ret < 0)
3640 return ret;
3641
666224d4
HS		 3642 /* Contact FW, advertising Master capability */
3643 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
b8ff05a9
DM		 3644 if (ret < 0) {
3645 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3646 ret);
3647 return ret;
3648 }
636f9d37
VP		 3649 if (ret == adap->mbox)
3650 adap->flags |= MASTER_PF;
b8ff05a9 3651
636f9d37
VP		 3652 /*
3653 * If we're the Master PF Driver and the device is uninitialized,
3654 * then let's consider upgrading the firmware ... (We always want
3655 * to check the firmware version number in order to A. get it for
3656 * later reporting and B. to warn if the currently loaded firmware
3657 * is excessively mismatched relative to the driver.)
3658 */
16e47624
HS		 3659 t4_get_fw_version(adap, &adap->params.fw_vers);
3660 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 3661 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 3662 struct fw_info *fw_info;
3663 struct fw_hdr *card_fw;
3664 const struct firmware *fw;
3665 const u8 *fw_data = NULL;
3666 unsigned int fw_size = 0;
3667
3668 /* This is the firmware whose headers the driver was compiled
3669 * against
3670 */
3671 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3672 if (fw_info == NULL) {
3673 dev_err(adap->pdev_dev,
3674 "unable to get firmware info for chip %d.\n",
3675 CHELSIO_CHIP_VERSION(adap->params.chip));
3676 return -EINVAL;
636f9d37 3677 }
16e47624
HS		 3678
3679 /* allocate memory to read the header of the firmware on the
3680 * card
3681 */
3682 card_fw = t4_alloc_mem(sizeof(*card_fw));
3683
3684 /* Get FW from from /lib/firmware/ */
3685 ret = request_firmware(&fw, fw_info->fw_mod_name,
3686 adap->pdev_dev);
3687 if (ret < 0) {
3688 dev_err(adap->pdev_dev,
3689 "unable to load firmware image %s, error %d\n",
3690 fw_info->fw_mod_name, ret);
3691 } else {
3692 fw_data = fw->data;
3693 fw_size = fw->size;
3694 }
3695
3696 /* upgrade FW logic */
3697 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3698 state, &reset);
3699
3700 /* Cleaning up */
0b5b6bee 3701 release_firmware(fw);
16e47624
HS		 3702 t4_free_mem(card_fw);
3703
636f9d37 3704 if (ret < 0)
16e47624 3705 goto bye;
636f9d37 3706 }
b8ff05a9 3707
636f9d37
VP		 3708 /*
3709 * Grab VPD parameters. This should be done after we establish a
3710 * connection to the firmware since some of the VPD parameters
3711 * (notably the Core Clock frequency) are retrieved via requests to
3712 * the firmware. On the other hand, we need these fairly early on
3713 * so we do this right after getting ahold of the firmware.
3714 */
3715 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 3716 if (ret < 0)
3717 goto bye;
a0881cab 3718
636f9d37 3719 /*
13ee15d3
VP		 3720 * Find out what ports are available to us. Note that we need to do
3721 * this before calling adap_init0_no_config() since it needs nports
3722 * and portvec ...
636f9d37
VP		 3723 */
3724 v =
5167865a
HS		 3725 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3726 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
b2612722 3727 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
a0881cab
DM		 3728 if (ret < 0)
3729 goto bye;
3730
636f9d37
VP		 3731 adap->params.nports = hweight32(port_vec);
3732 adap->params.portvec = port_vec;
3733
06640310
HS		 3734 /* If the firmware is initialized already, emit a simply note to that
3735 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 3736 */
3737 if (state == DEV_STATE_INIT) {
3738 dev_info(adap->pdev_dev, "Coming up as %s: "\
3739 "Adapter already initialized\n",
3740 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 3741 } else {
3742 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3743 "Initializing adapter\n");
06640310
HS		 3744
3745 /* Find out whether we're dealing with a version of the
3746 * firmware which has configuration file support.
636f9d37 3747 */
06640310
HS		 3748 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3749 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 3750 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 3751 params, val);
13ee15d3 3752
06640310
HS		 3753 /* If the firmware doesn't support Configuration Files,
3754 * return an error.
3755 */
3756 if (ret < 0) {
3757 dev_err(adap->pdev_dev, "firmware doesn't support "
3758 "Firmware Configuration Files\n");
3759 goto bye;
3760 }
3761
3762 /* The firmware provides us with a memory buffer where we can
3763 * load a Configuration File from the host if we want to
3764 * override the Configuration File in flash.
3765 */
3766 ret = adap_init0_config(adap, reset);
3767 if (ret == -ENOENT) {
3768 dev_err(adap->pdev_dev, "no Configuration File "
3769 "present on adapter.\n");
3770 goto bye;
636f9d37
VP		 3771 }
3772 if (ret < 0) {
06640310
HS		 3773 dev_err(adap->pdev_dev, "could not initialize "
3774 "adapter, error %d\n", -ret);
636f9d37
VP		 3775 goto bye;
3776 }
3777 }
3778
06640310
HS		 3779 /* Give the SGE code a chance to pull in anything that it needs ...
3780 * Note that this must be called after we retrieve our VPD parameters
3781 * in order to know how to convert core ticks to seconds, etc.
636f9d37 3782 */
06640310
HS		 3783 ret = t4_sge_init(adap);
3784 if (ret < 0)
3785 goto bye;
636f9d37 3786
9a4da2cd
VP		 3787 if (is_bypass_device(adap->pdev->device))
3788 adap->params.bypass = 1;
3789
636f9d37
VP		 3790 /*
3791 * Grab some of our basic fundamental operating parameters.
3792 */
3793#define FW_PARAM_DEV(param) \
5167865a
HS		 3794 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3795 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 3796
b8ff05a9 3797#define FW_PARAM_PFVF(param) \
5167865a
HS		 3798 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3799 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3800 FW_PARAMS_PARAM_Y_V(0) | \
3801 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 3802
636f9d37 3803 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 3804 params[1] = FW_PARAM_PFVF(L2T_START);
3805 params[2] = FW_PARAM_PFVF(L2T_END);
3806 params[3] = FW_PARAM_PFVF(FILTER_START);
3807 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 3808 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 3809 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 3810 if (ret < 0)
3811 goto bye;
636f9d37
VP		 3812 adap->sge.egr_start = val[0];
3813 adap->l2t_start = val[1];
3814 adap->l2t_end = val[2];
b8ff05a9
DM		 3815 adap->tids.ftid_base = val[3];
3816 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 3817 adap->sge.ingr_start = val[5];
b8ff05a9 3818
4b8e27a8
HS		 3819 /* qids (ingress/egress) returned from firmware can be anywhere
3820 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3821 * Hence driver needs to allocate memory for this range to
3822 * store the queue info. Get the highest IQFLINT/EQ index returned
3823 * in FW_EQ_*_CMD.alloc command.
3824 */
3825 params[0] = FW_PARAM_PFVF(EQ_END);
3826 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 3827 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 3828 if (ret < 0)
3829 goto bye;
3830 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3831 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3832
3833 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3834 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3835 if (!adap->sge.egr_map) {
3836 ret = -ENOMEM;
3837 goto bye;
3838 }
3839
3840 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3841 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3842 if (!adap->sge.ingr_map) {
3843 ret = -ENOMEM;
3844 goto bye;
3845 }
3846
3847 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 3848 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 3849 */
3850 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3851 sizeof(long), GFP_KERNEL);
3852 if (!adap->sge.starving_fl) {
3853 ret = -ENOMEM;
3854 goto bye;
3855 }
3856
3857 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3858 sizeof(long), GFP_KERNEL);
3859 if (!adap->sge.txq_maperr) {
3860 ret = -ENOMEM;
3861 goto bye;
3862 }
3863
5b377d11
HS		 3864#ifdef CONFIG_DEBUG_FS
3865 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3866 sizeof(long), GFP_KERNEL);
3867 if (!adap->sge.blocked_fl) {
3868 ret = -ENOMEM;
3869 goto bye;
3870 }
3871#endif
3872
b5a02f50
AB		 3873 params[0] = FW_PARAM_PFVF(CLIP_START);
3874 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 3875 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 3876 if (ret < 0)
3877 goto bye;
3878 adap->clipt_start = val[0];
3879 adap->clipt_end = val[1];
3880
636f9d37
VP		 3881 /* query params related to active filter region */
3882 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3883 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 3884 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 3885 /* If Active filter size is set we enable establishing
3886 * offload connection through firmware work request
3887 */
3888 if ((val[0] != val[1]) && (ret >= 0)) {
3889 adap->flags |= FW_OFLD_CONN;
3890 adap->tids.aftid_base = val[0];
3891 adap->tids.aftid_end = val[1];
3892 }
3893
b407a4a9
VP		 3894 /* If we're running on newer firmware, let it know that we're
3895 * prepared to deal with encapsulated CPL messages. Older
3896 * firmware won't understand this and we'll just get
3897 * unencapsulated messages ...
3898 */
3899 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3900 val[0] = 1;
b2612722 3901 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 3902
1ac0f095
KS		 3903 /*
3904 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3905 * capability. Earlier versions of the firmware didn't have the
3906 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3907 * permission to use ULPTX MEMWRITE DSGL.
3908 */
3909 if (is_t4(adap->params.chip)) {
3910 adap->params.ulptx_memwrite_dsgl = false;
3911 } else {
3912 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 3913 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 3914 1, params, val);
3915 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3916 }
3917
636f9d37
VP		 3918 /*
3919 * Get device capabilities so we can determine what resources we need
3920 * to manage.
3921 */
3922 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 3923 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3924 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3925 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3926 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3927 &caps_cmd);
3928 if (ret < 0)
3929 goto bye;
3930
13ee15d3 3931 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 3932 /* query offload-related parameters */
3933 params[0] = FW_PARAM_DEV(NTID);
3934 params[1] = FW_PARAM_PFVF(SERVER_START);
3935 params[2] = FW_PARAM_PFVF(SERVER_END);
3936 params[3] = FW_PARAM_PFVF(TDDP_START);
3937 params[4] = FW_PARAM_PFVF(TDDP_END);
3938 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 3939 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3940 params, val);
b8ff05a9
DM		 3941 if (ret < 0)
3942 goto bye;
3943 adap->tids.ntids = val[0];
3944 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3945 adap->tids.stid_base = val[1];
3946 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 3947 /*
dbedd44e 3948 * Setup server filter region. Divide the available filter
636f9d37
VP		 3949 * region into two parts. Regular filters get 1/3rd and server
3950 * filters get 2/3rd part. This is only enabled if workarond
3951 * path is enabled.
3952 * 1. For regular filters.
3953 * 2. Server filter: This are special filters which are used
3954 * to redirect SYN packets to offload queue.
3955 */
3956 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3957 adap->tids.sftid_base = adap->tids.ftid_base +
3958 DIV_ROUND_UP(adap->tids.nftids, 3);
3959 adap->tids.nsftids = adap->tids.nftids -
3960 DIV_ROUND_UP(adap->tids.nftids, 3);
3961 adap->tids.nftids = adap->tids.sftid_base -
3962 adap->tids.ftid_base;
3963 }
b8ff05a9
DM		 3964 adap->vres.ddp.start = val[3];
3965 adap->vres.ddp.size = val[4] - val[3] + 1;
3966 adap->params.ofldq_wr_cred = val[5];
636f9d37 3967
b8ff05a9
DM		 3968 adap->params.offload = 1;
3969 }
636f9d37 3970 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 3971 params[0] = FW_PARAM_PFVF(STAG_START);
3972 params[1] = FW_PARAM_PFVF(STAG_END);
3973 params[2] = FW_PARAM_PFVF(RQ_START);
3974 params[3] = FW_PARAM_PFVF(RQ_END);
3975 params[4] = FW_PARAM_PFVF(PBL_START);
3976 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 3977 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3978 params, val);
b8ff05a9
DM		 3979 if (ret < 0)
3980 goto bye;
3981 adap->vres.stag.start = val[0];
3982 adap->vres.stag.size = val[1] - val[0] + 1;
3983 adap->vres.rq.start = val[2];
3984 adap->vres.rq.size = val[3] - val[2] + 1;
3985 adap->vres.pbl.start = val[4];
3986 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 3987
3988 params[0] = FW_PARAM_PFVF(SQRQ_START);
3989 params[1] = FW_PARAM_PFVF(SQRQ_END);
3990 params[2] = FW_PARAM_PFVF(CQ_START);
3991 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 3992 params[4] = FW_PARAM_PFVF(OCQ_START);
3993 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 3994 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 3995 val);
a0881cab
DM		 3996 if (ret < 0)
3997 goto bye;
3998 adap->vres.qp.start = val[0];
3999 adap->vres.qp.size = val[1] - val[0] + 1;
4000 adap->vres.cq.start = val[2];
4001 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 4002 adap->vres.ocq.start = val[4];
4003 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 4004
4005 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4006 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 4007 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 4008 val);
4c2c5763
HS		 4009 if (ret < 0) {
4010 adap->params.max_ordird_qp = 8;
4011 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4012 ret = 0;
4013 } else {
4014 adap->params.max_ordird_qp = val[0];
4015 adap->params.max_ird_adapter = val[1];
4016 }
4017 dev_info(adap->pdev_dev,
4018 "max_ordird_qp %d max_ird_adapter %d\n",
4019 adap->params.max_ordird_qp,
4020 adap->params.max_ird_adapter);
b8ff05a9 4021 }
636f9d37 4022 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4023 params[0] = FW_PARAM_PFVF(ISCSI_START);
4024 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4025 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4026 params, val);
b8ff05a9
DM		 4027 if (ret < 0)
4028 goto bye;
4029 adap->vres.iscsi.start = val[0];
4030 adap->vres.iscsi.size = val[1] - val[0] + 1;
4031 }
4032#undef FW_PARAM_PFVF
4033#undef FW_PARAM_DEV
4034
92e7ae71
HS		 4035 /* The MTU/MSS Table is initialized by now, so load their values. If
4036 * we're initializing the adapter, then we'll make any modifications
4037 * we want to the MTU/MSS Table and also initialize the congestion
4038 * parameters.
636f9d37 4039 */
b8ff05a9 4040 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4041 if (state != DEV_STATE_INIT) {
4042 int i;
4043
4044 /* The default MTU Table contains values 1492 and 1500.
4045 * However, for TCP, it's better to have two values which are
4046 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4047 * This allows us to have a TCP Data Payload which is a
4048 * multiple of 8 regardless of what combination of TCP Options
4049 * are in use (always a multiple of 4 bytes) which is
4050 * important for performance reasons. For instance, if no
4051 * options are in use, then we have a 20-byte IP header and a
4052 * 20-byte TCP header. In this case, a 1500-byte MSS would
4053 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4054 * which is not a multiple of 8. So using an MSS of 1488 in
4055 * this case results in a TCP Data Payload of 1448 bytes which
4056 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4057 * Stamps have been negotiated, then an MTU of 1500 bytes
4058 * results in a TCP Data Payload of 1448 bytes which, as
4059 * above, is a multiple of 8 bytes ...
4060 */
4061 for (i = 0; i < NMTUS; i++)
4062 if (adap->params.mtus[i] == 1492) {
4063 adap->params.mtus[i] = 1488;
4064 break;
4065 }
7ee9ff94 4066
92e7ae71
HS		 4067 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4068 adap->params.b_wnd);
4069 }
df64e4d3 4070 t4_init_sge_params(adap);
dcf7b6f5 4071 t4_init_tp_params(adap);
636f9d37 4072 adap->flags |= FW_OK;
b8ff05a9
DM		 4073 return 0;
4074
4075 /*
636f9d37
VP		 4076 * Something bad happened. If a command timed out or failed with EIO
4077 * FW does not operate within its spec or something catastrophic
4078 * happened to HW/FW, stop issuing commands.
b8ff05a9 4079 */
636f9d37 4080bye:
4b8e27a8
HS		 4081 kfree(adap->sge.egr_map);
4082 kfree(adap->sge.ingr_map);
4083 kfree(adap->sge.starving_fl);
4084 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4085#ifdef CONFIG_DEBUG_FS
4086 kfree(adap->sge.blocked_fl);
4087#endif
636f9d37
VP		 4088 if (ret != -ETIMEDOUT && ret != -EIO)
4089 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4090 return ret;
4091}
4092
204dc3c0
DM		 4093/* EEH callbacks */
4094
4095static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4096 pci_channel_state_t state)
4097{
4098 int i;
4099 struct adapter *adap = pci_get_drvdata(pdev);
4100
4101 if (!adap)
4102 goto out;
4103
4104 rtnl_lock();
4105 adap->flags &= ~FW_OK;
4106 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4107 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4108 for_each_port(adap, i) {
4109 struct net_device *dev = adap->port[i];
4110
4111 netif_device_detach(dev);
4112 netif_carrier_off(dev);
4113 }
9fe6cb58 4114 spin_unlock(&adap->stats_lock);
b37987e8 4115 disable_interrupts(adap);
204dc3c0
DM		 4116 if (adap->flags & FULL_INIT_DONE)
4117 cxgb_down(adap);
4118 rtnl_unlock();
144be3d9
GS		 4119 if ((adap->flags & DEV_ENABLED)) {
4120 pci_disable_device(pdev);
4121 adap->flags &= ~DEV_ENABLED;
4122 }
204dc3c0
DM		 4123out: return state == pci_channel_io_perm_failure ?
4124 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4125}
4126
4127static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4128{
4129 int i, ret;
4130 struct fw_caps_config_cmd c;
4131 struct adapter *adap = pci_get_drvdata(pdev);
4132
4133 if (!adap) {
4134 pci_restore_state(pdev);
4135 pci_save_state(pdev);
4136 return PCI_ERS_RESULT_RECOVERED;
4137 }
4138
144be3d9
GS		 4139 if (!(adap->flags & DEV_ENABLED)) {
4140 if (pci_enable_device(pdev)) {
4141 dev_err(&pdev->dev, "Cannot reenable PCI "
4142 "device after reset\n");
4143 return PCI_ERS_RESULT_DISCONNECT;
4144 }
4145 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4146 }
4147
4148 pci_set_master(pdev);
4149 pci_restore_state(pdev);
4150 pci_save_state(pdev);
4151 pci_cleanup_aer_uncorrect_error_status(pdev);
4152
8203b509 4153 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4154 return PCI_ERS_RESULT_DISCONNECT;
b2612722 4155 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4156 return PCI_ERS_RESULT_DISCONNECT;
4157 adap->flags |= FW_OK;
4158 if (adap_init1(adap, &c))
4159 return PCI_ERS_RESULT_DISCONNECT;
4160
4161 for_each_port(adap, i) {
4162 struct port_info *p = adap2pinfo(adap, i);
4163
b2612722 4164 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
060e0c75 4165 NULL, NULL);
204dc3c0
DM		 4166 if (ret < 0)
4167 return PCI_ERS_RESULT_DISCONNECT;
4168 p->viid = ret;
4169 p->xact_addr_filt = -1;
4170 }
4171
4172 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4173 adap->params.b_wnd);
1ae970e0 4174 setup_memwin(adap);
204dc3c0
DM		 4175 if (cxgb_up(adap))
4176 return PCI_ERS_RESULT_DISCONNECT;
4177 return PCI_ERS_RESULT_RECOVERED;
4178}
4179
4180static void eeh_resume(struct pci_dev *pdev)
4181{
4182 int i;
4183 struct adapter *adap = pci_get_drvdata(pdev);
4184
4185 if (!adap)
4186 return;
4187
4188 rtnl_lock();
4189 for_each_port(adap, i) {
4190 struct net_device *dev = adap->port[i];
4191
4192 if (netif_running(dev)) {
4193 link_start(dev);
4194 cxgb_set_rxmode(dev);
4195 }
4196 netif_device_attach(dev);
4197 }
4198 rtnl_unlock();
4199}
4200
3646f0e5 4201static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4202 .error_detected = eeh_err_detected,
4203 .slot_reset = eeh_slot_reset,
4204 .resume = eeh_resume,
4205};
4206
57d8b764 4207static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4208{
57d8b764
KS		 4209 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4210 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 4211}
4212
c887ad0e
HS		 4213static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4214 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 4215 unsigned int size, unsigned int iqe_size)
4216{
c887ad0e 4217 q->adap = adap;
812034f1 4218 cxgb4_set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 4219 q->iqe_len = iqe_size;
4220 q->size = size;
4221}
4222
4223/*
4224 * Perform default configuration of DMA queues depending on the number and type
4225 * of ports we found and the number of available CPUs. Most settings can be
4226 * modified by the admin prior to actual use.
4227 */
91744948 4228static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4229{
4230 struct sge *s = &adap->sge;
688848b1
AB		 4231 int i, n10g = 0, qidx = 0;
4232#ifndef CONFIG_CHELSIO_T4_DCB
4233 int q10g = 0;
4234#endif
cf38be6d 4235 int ciq_size;
b8ff05a9
DM		 4236
4237 for_each_port(adap, i)
57d8b764 4238 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 4239#ifdef CONFIG_CHELSIO_T4_DCB
4240 /* For Data Center Bridging support we need to be able to support up
4241 * to 8 Traffic Priorities; each of which will be assigned to its
4242 * own TX Queue in order to prevent Head-Of-Line Blocking.
4243 */
4244 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4245 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4246 MAX_ETH_QSETS, adap->params.nports * 8);
4247 BUG_ON(1);
4248 }
b8ff05a9 4249
688848b1
AB		 4250 for_each_port(adap, i) {
4251 struct port_info *pi = adap2pinfo(adap, i);
4252
4253 pi->first_qset = qidx;
4254 pi->nqsets = 8;
4255 qidx += pi->nqsets;
4256 }
4257#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4258 /*
4259 * We default to 1 queue per non-10G port and up to # of cores queues
4260 * per 10G port.
4261 */
4262 if (n10g)
4263 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4264 if (q10g > netif_get_num_default_rss_queues())
4265 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 4266
4267 for_each_port(adap, i) {
4268 struct port_info *pi = adap2pinfo(adap, i);
4269
4270 pi->first_qset = qidx;
57d8b764 4271 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4272 qidx += pi->nqsets;
4273 }
688848b1 4274#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4275
4276 s->ethqsets = qidx;
4277 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4278
4279 if (is_offload(adap)) {
4280 /*
4281 * For offload we use 1 queue/channel if all ports are up to 1G,
4282 * otherwise we divide all available queues amongst the channels
4283 * capped by the number of available cores.
4284 */
4285 if (n10g) {
4286 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4287 num_online_cpus());
4288 s->ofldqsets = roundup(i, adap->params.nports);
4289 } else
4290 s->ofldqsets = adap->params.nports;
4291 /* For RDMA one Rx queue per channel suffices */
4292 s->rdmaqs = adap->params.nports;
f36e58e5
HS		 4293 /* Try and allow at least 1 CIQ per cpu rounding down
4294 * to the number of ports, with a minimum of 1 per port.
4295 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4296 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4297 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4298 */
4299 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4300 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4301 adap->params.nports;
4302 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
b8ff05a9
DM		 4303 }
4304
4305 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4306 struct sge_eth_rxq *r = &s->ethrxq[i];
4307
c887ad0e 4308 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4309 r->fl.size = 72;
4310 }
4311
4312 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4313 s->ethtxq[i].q.size = 1024;
4314
4315 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4316 s->ctrlq[i].q.size = 512;
4317
4318 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4319 s->ofldtxq[i].q.size = 1024;
4320
4321 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4322 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4323
c887ad0e 4324 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 4325 r->rspq.uld = CXGB4_ULD_ISCSI;
4326 r->fl.size = 72;
4327 }
4328
4329 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4330 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4331
c887ad0e 4332 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 4333 r->rspq.uld = CXGB4_ULD_RDMA;
4334 r->fl.size = 72;
4335 }
4336
cf38be6d
HS		 4337 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4338 if (ciq_size > SGE_MAX_IQ_SIZE) {
4339 CH_WARN(adap, "CIQ size too small for available IQs\n");
4340 ciq_size = SGE_MAX_IQ_SIZE;
4341 }
4342
4343 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4344 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4345
c887ad0e 4346 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 4347 r->rspq.uld = CXGB4_ULD_RDMA;
4348 }
4349
c887ad0e
HS		 4350 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4351 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 4352}
4353
4354/*
4355 * Reduce the number of Ethernet queues across all ports to at most n.
4356 * n provides at least one queue per port.
4357 */
91744948 4358static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4359{
4360 int i;
4361 struct port_info *pi;
4362
4363 while (n < adap->sge.ethqsets)
4364 for_each_port(adap, i) {
4365 pi = adap2pinfo(adap, i);
4366 if (pi->nqsets > 1) {
4367 pi->nqsets--;
4368 adap->sge.ethqsets--;
4369 if (adap->sge.ethqsets <= n)
4370 break;
4371 }
4372 }
4373
4374 n = 0;
4375 for_each_port(adap, i) {
4376 pi = adap2pinfo(adap, i);
4377 pi->first_qset = n;
4378 n += pi->nqsets;
4379 }
4380}
4381
4382/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4383#define EXTRA_VECS 2
4384
91744948 4385static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 4386{
4387 int ofld_need = 0;
f36e58e5 4388 int i, want, need, allocated;
b8ff05a9
DM		 4389 struct sge *s = &adap->sge;
4390 unsigned int nchan = adap->params.nports;
f36e58e5
HS		 4391 struct msix_entry *entries;
4392
4393 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4394 GFP_KERNEL);
4395 if (!entries)
4396 return -ENOMEM;
b8ff05a9 4397
f36e58e5 4398 for (i = 0; i < MAX_INGQ + 1; ++i)
b8ff05a9
DM		 4399 entries[i].entry = i;
4400
4401 want = s->max_ethqsets + EXTRA_VECS;
4402 if (is_offload(adap)) {
cf38be6d 4403 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 4404 /* need nchan for each possible ULD */
cf38be6d 4405 ofld_need = 3 * nchan;
b8ff05a9 4406 }
688848b1
AB		 4407#ifdef CONFIG_CHELSIO_T4_DCB
4408 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4409 * each port.
4410 */
4411 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4412#else
b8ff05a9 4413 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 4414#endif
f36e58e5
HS		 4415 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4416 if (allocated < 0) {
4417 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4418 " not using MSI-X\n");
4419 kfree(entries);
4420 return allocated;
4421 }
b8ff05a9 4422
f36e58e5 4423 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 4424 * Every group gets its minimum requirement and NIC gets top
4425 * priority for leftovers.
4426 */
f36e58e5 4427 i = allocated - EXTRA_VECS - ofld_need;
c32ad224
AG		 4428 if (i < s->max_ethqsets) {
4429 s->max_ethqsets = i;
4430 if (i < s->ethqsets)
4431 reduce_ethqs(adap, i);
4432 }
4433 if (is_offload(adap)) {
f36e58e5
HS		 4434 if (allocated < want) {
4435 s->rdmaqs = nchan;
4436 s->rdmaciqs = nchan;
4437 }
4438
4439 /* leftovers go to OFLD */
4440 i = allocated - EXTRA_VECS - s->max_ethqsets -
4441 s->rdmaqs - s->rdmaciqs;
c32ad224
AG		 4442 s->ofldqsets = (i / nchan) * nchan; /* round down */
4443 }
f36e58e5 4444 for (i = 0; i < allocated; ++i)
c32ad224
AG		 4445 adap->msix_info[i].vec = entries[i].vector;
4446
f36e58e5 4447 kfree(entries);
c32ad224 4448 return 0;
b8ff05a9
DM		 4449}
4450
4451#undef EXTRA_VECS
4452
91744948 4453static int init_rss(struct adapter *adap)
671b0060 4454{
c035e183
HS		 4455 unsigned int i;
4456 int err;
4457
4458 err = t4_init_rss_mode(adap, adap->mbox);
4459 if (err)
4460 return err;
671b0060
DM		 4461
4462 for_each_port(adap, i) {
4463 struct port_info *pi = adap2pinfo(adap, i);
4464
4465 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4466 if (!pi->rss)
4467 return -ENOMEM;
671b0060
DM		 4468 }
4469 return 0;
4470}
4471
91744948 4472static void print_port_info(const struct net_device *dev)
b8ff05a9 4473{
b8ff05a9 4474 char buf[80];
118969ed 4475 char *bufp = buf;
f1a051b9 4476 const char *spd = "";
118969ed
DM		 4477 const struct port_info *pi = netdev_priv(dev);
4478 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 4479
4480 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4481 spd = " 2.5 GT/s";
4482 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4483 spd = " 5 GT/s";
d2e752db
RD		 4484 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4485 spd = " 8 GT/s";
b8ff05a9 4486
118969ed
DM		 4487 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4488 bufp += sprintf(bufp, "100/");
4489 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4490 bufp += sprintf(bufp, "1000/");
4491 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4492 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 4493 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4494 bufp += sprintf(bufp, "40G/");
118969ed
DM		 4495 if (bufp != buf)
4496 --bufp;
72aca4bf 4497 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM		 4498
4499 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 4500 adap->params.vpd.id,
d14807dd 4501 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM		 4502 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4503 (adap->flags & USING_MSIX) ? " MSI-X" :
4504 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 4505 netdev_info(dev, "S/N: %s, P/N: %s\n",
4506 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 4507}
4508
91744948 4509static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 4510{
e5c8ae5f 4511 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 4512}
4513
06546391
DM		 4514/*
4515 * Free the following resources:
4516 * - memory used for tables
4517 * - MSI/MSI-X
4518 * - net devices
4519 * - resources FW is holding for us
4520 */
4521static void free_some_resources(struct adapter *adapter)
4522{
4523 unsigned int i;
4524
4525 t4_free_mem(adapter->l2t);
4526 t4_free_mem(adapter->tids.tid_tab);
4b8e27a8
HS		 4527 kfree(adapter->sge.egr_map);
4528 kfree(adapter->sge.ingr_map);
4529 kfree(adapter->sge.starving_fl);
4530 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 4531#ifdef CONFIG_DEBUG_FS
4532 kfree(adapter->sge.blocked_fl);
4533#endif
06546391
DM		 4534 disable_msi(adapter);
4535
4536 for_each_port(adapter, i)
671b0060 4537 if (adapter->port[i]) {
4f3a0fcf
HS		 4538 struct port_info *pi = adap2pinfo(adapter, i);
4539
4540 if (pi->viid != 0)
4541 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4542 0, pi->viid);
671b0060 4543 kfree(adap2pinfo(adapter, i)->rss);
06546391 4544 free_netdev(adapter->port[i]);
671b0060 4545 }
06546391 4546 if (adapter->flags & FW_OK)
b2612722 4547 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 4548}
4549
2ed28baa 4550#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 4551#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 4552 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 4553#define SEGMENT_SIZE 128
b8ff05a9 4554
1dd06ae8 4555static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 4556{
22adfe0a 4557 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 4558 struct port_info *pi;
c8f44aff 4559 bool highdma = false;
b8ff05a9 4560 struct adapter *adapter = NULL;
d6ce2628 4561 void __iomem *regs;
b8ff05a9
DM		 4562
4563 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4564
4565 err = pci_request_regions(pdev, KBUILD_MODNAME);
4566 if (err) {
4567 /* Just info, some other driver may have claimed the device. */
4568 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4569 return err;
4570 }
4571
b8ff05a9
DM		 4572 err = pci_enable_device(pdev);
4573 if (err) {
4574 dev_err(&pdev->dev, "cannot enable PCI device\n");
4575 goto out_release_regions;
4576 }
4577
d6ce2628
HS		 4578 regs = pci_ioremap_bar(pdev, 0);
4579 if (!regs) {
4580 dev_err(&pdev->dev, "cannot map device registers\n");
4581 err = -ENOMEM;
4582 goto out_disable_device;
4583 }
4584
8203b509
HS		 4585 err = t4_wait_dev_ready(regs);
4586 if (err < 0)
4587 goto out_unmap_bar0;
4588
d6ce2628 4589 /* We control everything through one PF */
0d804338 4590 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
d6ce2628
HS		 4591 if (func != ent->driver_data) {
4592 iounmap(regs);
4593 pci_disable_device(pdev);
4594 pci_save_state(pdev); /* to restore SR-IOV later */
4595 goto sriov;
4596 }
4597
b8ff05a9 4598 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 4599 highdma = true;
b8ff05a9
DM		 4600 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4601 if (err) {
4602 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4603 "coherent allocations\n");
d6ce2628 4604 goto out_unmap_bar0;
b8ff05a9
DM		 4605 }
4606 } else {
4607 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4608 if (err) {
4609 dev_err(&pdev->dev, "no usable DMA configuration\n");
d6ce2628 4610 goto out_unmap_bar0;
b8ff05a9
DM		 4611 }
4612 }
4613
4614 pci_enable_pcie_error_reporting(pdev);
ef306b50 4615 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 4616 pci_set_master(pdev);
4617 pci_save_state(pdev);
4618
4619 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4620 if (!adapter) {
4621 err = -ENOMEM;
d6ce2628 4622 goto out_unmap_bar0;
b8ff05a9
DM		 4623 }
4624
29aaee65
AB		 4625 adapter->workq = create_singlethread_workqueue("cxgb4");
4626 if (!adapter->workq) {
4627 err = -ENOMEM;
4628 goto out_free_adapter;
4629 }
4630
144be3d9
GS		 4631 /* PCI device has been enabled */
4632 adapter->flags |= DEV_ENABLED;
4633
d6ce2628 4634 adapter->regs = regs;
b8ff05a9
DM		 4635 adapter->pdev = pdev;
4636 adapter->pdev_dev = &pdev->dev;
3069ee9b 4637 adapter->mbox = func;
b2612722 4638 adapter->pf = func;
b8ff05a9
DM		 4639 adapter->msg_enable = dflt_msg_enable;
4640 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4641
4642 spin_lock_init(&adapter->stats_lock);
4643 spin_lock_init(&adapter->tid_release_lock);
e327c225 4644 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 4645
4646 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 4647 INIT_WORK(&adapter->db_full_task, process_db_full);
4648 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 4649
4650 err = t4_prep_adapter(adapter);
4651 if (err)
d6ce2628
HS		 4652 goto out_free_adapter;
4653
22adfe0a 4654
d14807dd 4655 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 4656 s_qpp = (QUEUESPERPAGEPF0_S +
4657 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 4658 adapter->pf);
f612b815
HS		 4659 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4660 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 4661 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4662
4663 /* Each segment size is 128B. Write coalescing is enabled only
4664 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4665 * queue is less no of segments that can be accommodated in
4666 * a page size.
4667 */
4668 if (qpp > num_seg) {
4669 dev_err(&pdev->dev,
4670 "Incorrect number of egress queues per page\n");
4671 err = -EINVAL;
d6ce2628 4672 goto out_free_adapter;
22adfe0a
SR		 4673 }
4674 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4675 pci_resource_len(pdev, 2));
4676 if (!adapter->bar2) {
4677 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4678 err = -ENOMEM;
d6ce2628 4679 goto out_free_adapter;
22adfe0a 4680 }
a4cfd929
HS		 4681 t4_write_reg(adapter, SGE_STAT_CFG_A,
4682 STATSOURCE_T5_V(7) | STATMODE_V(0));
22adfe0a
SR		 4683 }
4684
636f9d37 4685 setup_memwin(adapter);
b8ff05a9 4686 err = adap_init0(adapter);
5b377d11
HS		 4687#ifdef CONFIG_DEBUG_FS
4688 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4689#endif
636f9d37 4690 setup_memwin_rdma(adapter);
b8ff05a9
DM		 4691 if (err)
4692 goto out_unmap_bar;
4693
4694 for_each_port(adapter, i) {
4695 struct net_device *netdev;
4696
4697 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4698 MAX_ETH_QSETS);
4699 if (!netdev) {
4700 err = -ENOMEM;
4701 goto out_free_dev;
4702 }
4703
4704 SET_NETDEV_DEV(netdev, &pdev->dev);
4705
4706 adapter->port[i] = netdev;
4707 pi = netdev_priv(netdev);
4708 pi->adapter = adapter;
4709 pi->xact_addr_filt = -1;
b8ff05a9 4710 pi->port_id = i;
b8ff05a9
DM		 4711 netdev->irq = pdev->irq;
4712
2ed28baa
MM		 4713 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4714 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4715 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 4716 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 4717 if (highdma)
4718 netdev->hw_features |= NETIF_F_HIGHDMA;
4719 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 4720 netdev->vlan_features = netdev->features & VLAN_FEAT;
4721
01789349
JP		 4722 netdev->priv_flags |= IFF_UNICAST_FLT;
4723
b8ff05a9 4724 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 4725#ifdef CONFIG_CHELSIO_T4_DCB
4726 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4727 cxgb4_dcb_state_init(netdev);
4728#endif
812034f1 4729 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 4730 }
4731
4732 pci_set_drvdata(pdev, adapter);
4733
4734 if (adapter->flags & FW_OK) {
060e0c75 4735 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 4736 if (err)
4737 goto out_free_dev;
4738 }
4739
4740 /*
4741 * Configure queues and allocate tables now, they can be needed as
4742 * soon as the first register_netdev completes.
4743 */
4744 cfg_queues(adapter);
4745
4746 adapter->l2t = t4_init_l2t();
4747 if (!adapter->l2t) {
4748 /* We tolerate a lack of L2T, giving up some functionality */
4749 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4750 adapter->params.offload = 0;
4751 }
4752
b5a02f50
AB		 4753#if IS_ENABLED(CONFIG_IPV6)
4754 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4755 adapter->clipt_end);
4756 if (!adapter->clipt) {
4757 /* We tolerate a lack of clip_table, giving up
4758 * some functionality
4759 */
4760 dev_warn(&pdev->dev,
4761 "could not allocate Clip table, continuing\n");
4762 adapter->params.offload = 0;
4763 }
4764#endif
b8ff05a9
DM		 4765 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4766 dev_warn(&pdev->dev, "could not allocate TID table, "
4767 "continuing\n");
4768 adapter->params.offload = 0;
4769 }
4770
f7cabcdd
DM		 4771 /* See what interrupts we'll be using */
4772 if (msi > 1 && enable_msix(adapter) == 0)
4773 adapter->flags |= USING_MSIX;
4774 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4775 adapter->flags |= USING_MSI;
4776
671b0060
DM		 4777 err = init_rss(adapter);
4778 if (err)
4779 goto out_free_dev;
4780
b8ff05a9
DM		 4781 /*
4782 * The card is now ready to go. If any errors occur during device
4783 * registration we do not fail the whole card but rather proceed only
4784 * with the ports we manage to register successfully. However we must
4785 * register at least one net device.
4786 */
4787 for_each_port(adapter, i) {
a57cabe0
DM		 4788 pi = adap2pinfo(adapter, i);
4789 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4790 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4791
b8ff05a9
DM		 4792 err = register_netdev(adapter->port[i]);
4793 if (err)
b1a3c2b6 4794 break;
b1a3c2b6
DM		 4795 adapter->chan_map[pi->tx_chan] = i;
4796 print_port_info(adapter->port[i]);
b8ff05a9 4797 }
b1a3c2b6 4798 if (i == 0) {
b8ff05a9
DM		 4799 dev_err(&pdev->dev, "could not register any net devices\n");
4800 goto out_free_dev;
4801 }
b1a3c2b6
DM		 4802 if (err) {
4803 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4804 err = 0;
6403eab1 4805 }
b8ff05a9
DM		 4806
4807 if (cxgb4_debugfs_root) {
4808 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4809 cxgb4_debugfs_root);
4810 setup_debugfs(adapter);
4811 }
4812
6482aa7c
DLR		 4813 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4814 pdev->needs_freset = 1;
4815
b8ff05a9
DM		 4816 if (is_offload(adapter))
4817 attach_ulds(adapter);
4818
8e1e6059 4819sriov:
b8ff05a9 4820#ifdef CONFIG_PCI_IOV
7d6727cf 4821 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 4822 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4823 dev_info(&pdev->dev,
4824 "instantiated %u virtual functions\n",
4825 num_vf[func]);
4826#endif
4827 return 0;
4828
4829 out_free_dev:
06546391 4830 free_some_resources(adapter);
b8ff05a9 4831 out_unmap_bar:
d14807dd 4832 if (!is_t4(adapter->params.chip))
22adfe0a 4833 iounmap(adapter->bar2);
b8ff05a9 4834 out_free_adapter:
29aaee65
AB		 4835 if (adapter->workq)
4836 destroy_workqueue(adapter->workq);
4837
b8ff05a9 4838 kfree(adapter);
d6ce2628
HS		 4839 out_unmap_bar0:
4840 iounmap(regs);
b8ff05a9
DM		 4841 out_disable_device:
4842 pci_disable_pcie_error_reporting(pdev);
4843 pci_disable_device(pdev);
4844 out_release_regions:
4845 pci_release_regions(pdev);
b8ff05a9
DM		 4846 return err;
4847}
4848
91744948 4849static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 4850{
4851 struct adapter *adapter = pci_get_drvdata(pdev);
4852
636f9d37 4853#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 4854 pci_disable_sriov(pdev);
4855
636f9d37
VP		 4856#endif
4857
b8ff05a9
DM		 4858 if (adapter) {
4859 int i;
4860
29aaee65
AB		 4861 /* Tear down per-adapter Work Queue first since it can contain
4862 * references to our adapter data structure.
4863 */
4864 destroy_workqueue(adapter->workq);
4865
b8ff05a9
DM		 4866 if (is_offload(adapter))
4867 detach_ulds(adapter);
4868
b37987e8
HS		 4869 disable_interrupts(adapter);
4870
b8ff05a9 4871 for_each_port(adapter, i)
8f3a7676 4872 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 4873 unregister_netdev(adapter->port[i]);
4874
9f16dc2e 4875 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 4876
f2b7e78d
VP		 4877 /* If we allocated filters, free up state associated with any
4878 * valid filters ...
4879 */
4880 if (adapter->tids.ftid_tab) {
4881 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 4882 for (i = 0; i < (adapter->tids.nftids +
4883 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 4884 if (f->valid)
4885 clear_filter(adapter, f);
4886 }
4887
aaefae9b
DM		 4888 if (adapter->flags & FULL_INIT_DONE)
4889 cxgb_down(adapter);
b8ff05a9 4890
06546391 4891 free_some_resources(adapter);
b5a02f50
AB		 4892#if IS_ENABLED(CONFIG_IPV6)
4893 t4_cleanup_clip_tbl(adapter);
4894#endif
b8ff05a9 4895 iounmap(adapter->regs);
d14807dd 4896 if (!is_t4(adapter->params.chip))
22adfe0a 4897 iounmap(adapter->bar2);
b8ff05a9 4898 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 4899 if ((adapter->flags & DEV_ENABLED)) {
4900 pci_disable_device(pdev);
4901 adapter->flags &= ~DEV_ENABLED;
4902 }
b8ff05a9 4903 pci_release_regions(pdev);
ee9a33b2 4904 synchronize_rcu();
8b662fe7 4905 kfree(adapter);
a069ec91 4906 } else
b8ff05a9
DM		 4907 pci_release_regions(pdev);
4908}
4909
4910static struct pci_driver cxgb4_driver = {
4911 .name = KBUILD_MODNAME,
4912 .id_table = cxgb4_pci_tbl,
4913 .probe = init_one,
91744948 4914 .remove = remove_one,
687d705c 4915 .shutdown = remove_one,
204dc3c0 4916 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 4917};
4918
4919static int __init cxgb4_init_module(void)
4920{
4921 int ret;
4922
4923 /* Debugfs support is optional, just warn if this fails */
4924 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
4925 if (!cxgb4_debugfs_root)
428ac43f 4926 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 4927
4928 ret = pci_register_driver(&cxgb4_driver);
29aaee65 4929 if (ret < 0)
b8ff05a9 4930 debugfs_remove(cxgb4_debugfs_root);
01bcca68 4931
1bb60376 4932#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 4933 if (!inet6addr_registered) {
4934 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4935 inet6addr_registered = true;
4936 }
1bb60376 4937#endif
01bcca68 4938
b8ff05a9
DM		 4939 return ret;
4940}
4941
4942static void __exit cxgb4_cleanup_module(void)
4943{
1bb60376 4944#if IS_ENABLED(CONFIG_IPV6)
1793c798 4945 if (inet6addr_registered) {
b5a02f50
AB		 4946 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4947 inet6addr_registered = false;
4948 }
1bb60376 4949#endif
b8ff05a9
DM		 4950 pci_unregister_driver(&cxgb4_driver);
4951 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
4952}
4953
4954module_init(cxgb4_init_module);
4955module_exit(cxgb4_cleanup_module);
Linux kernel - Deliverables
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