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hv_netvsc: Use the xmit_more skb flag to optimize signaling the host
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
b5a02f50 65#include <net/addrconf.h>
b8ff05a9
DM		 66#include <asm/uaccess.h>
67
68#include "cxgb4.h"
69#include "t4_regs.h"
f612b815 70#include "t4_values.h"
b8ff05a9
DM		 71#include "t4_msg.h"
72#include "t4fw_api.h"
cd6c2f12 73#include "t4fw_version.h"
688848b1 74#include "cxgb4_dcb.h"
fd88b31a 75#include "cxgb4_debugfs.h"
b5a02f50 76#include "clip_tbl.h"
b8ff05a9
DM		 77#include "l2t.h"
78
812034f1
HS		 79char cxgb4_driver_name[] = KBUILD_MODNAME;
80
01bcca68
VP		 81#ifdef DRV_VERSION
82#undef DRV_VERSION
83#endif
3a7f8554 84#define DRV_VERSION "2.0.0-ko"
812034f1 85const char cxgb4_driver_version[] = DRV_VERSION;
3a7f8554 86#define DRV_DESC "Chelsio T4/T5 Network Driver"
b8ff05a9 87
f2b7e78d
VP		 88/* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
93 */
94struct filter_entry {
95 /* Administrative fields for filter.
96 */
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
99
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
103
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
108 */
109 struct ch_filter_specification fs;
110};
111
b8ff05a9
DM		 112#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
115
3fedeab1
HS		 116/* Macros needed to support the PCI Device ID Table ...
117 */
118#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 119 static const struct pci_device_id cxgb4_pci_tbl[] = {
3fedeab1 120#define CH_PCI_DEVICE_ID_FUNCTION 0x4
b8ff05a9 121
3fedeab1
HS		 122/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
123 * called for both.
124 */
125#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
126
127#define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
129
130#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
131 { 0, } \
132 }
133
134#include "t4_pci_id_tbl.h"
b8ff05a9 135
16e47624 136#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 137#define FW5_FNAME "cxgb4/t5fw.bin"
16e47624 138#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 139#define FW5_CFNAME "cxgb4/t5-config.txt"
b8ff05a9
DM		 140
141MODULE_DESCRIPTION(DRV_DESC);
142MODULE_AUTHOR("Chelsio Communications");
143MODULE_LICENSE("Dual BSD/GPL");
144MODULE_VERSION(DRV_VERSION);
145MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 146MODULE_FIRMWARE(FW4_FNAME);
0a57a536 147MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 148
636f9d37
VP		 149/*
150 * Normally we're willing to become the firmware's Master PF but will be happy
151 * if another PF has already become the Master and initialized the adapter.
152 * Setting "force_init" will cause this driver to forcibly establish itself as
153 * the Master PF and initialize the adapter.
154 */
155static uint force_init;
156
157module_param(force_init, uint, 0644);
158MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
159
13ee15d3
VP		 160/*
161 * Normally if the firmware we connect to has Configuration File support, we
162 * use that and only fall back to the old Driver-based initialization if the
163 * Configuration File fails for some reason. If force_old_init is set, then
164 * we'll always use the old Driver-based initialization sequence.
165 */
166static uint force_old_init;
167
168module_param(force_old_init, uint, 0644);
06640310
HS		 169MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
170 " parameter");
13ee15d3 171
b8ff05a9
DM		 172static int dflt_msg_enable = DFLT_MSG_ENABLE;
173
174module_param(dflt_msg_enable, int, 0644);
175MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
176
177/*
178 * The driver uses the best interrupt scheme available on a platform in the
179 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
180 * of these schemes the driver may consider as follows:
181 *
182 * msi = 2: choose from among all three options
183 * msi = 1: only consider MSI and INTx interrupts
184 * msi = 0: force INTx interrupts
185 */
186static int msi = 2;
187
188module_param(msi, int, 0644);
189MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
190
191/*
192 * Queue interrupt hold-off timer values. Queues default to the first of these
193 * upon creation.
194 */
195static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
196
197module_param_array(intr_holdoff, uint, NULL, 0644);
198MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
06640310 199 "0..4 in microseconds, deprecated parameter");
b8ff05a9
DM		 200
201static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
202
203module_param_array(intr_cnt, uint, NULL, 0644);
204MODULE_PARM_DESC(intr_cnt,
06640310
HS		 205 "thresholds 1..3 for queue interrupt packet counters, "
206 "deprecated parameter");
b8ff05a9 207
636f9d37
VP		 208/*
209 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
210 * offset by 2 bytes in order to have the IP headers line up on 4-byte
211 * boundaries. This is a requirement for many architectures which will throw
212 * a machine check fault if an attempt is made to access one of the 4-byte IP
213 * header fields on a non-4-byte boundary. And it's a major performance issue
214 * even on some architectures which allow it like some implementations of the
215 * x86 ISA. However, some architectures don't mind this and for some very
216 * edge-case performance sensitive applications (like forwarding large volumes
217 * of small packets), setting this DMA offset to 0 will decrease the number of
218 * PCI-E Bus transfers enough to measurably affect performance.
219 */
220static int rx_dma_offset = 2;
221
eb939922 222static bool vf_acls;
b8ff05a9
DM		 223
224#ifdef CONFIG_PCI_IOV
225module_param(vf_acls, bool, 0644);
06640310
HS		 226MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
227 "deprecated parameter");
b8ff05a9 228
7d6727cf
SR		 229/* Configure the number of PCI-E Virtual Function which are to be instantiated
230 * on SR-IOV Capable Physical Functions.
0a57a536 231 */
7d6727cf 232static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 233
234module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 235MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 236#endif
237
688848b1
AB		 238/* TX Queue select used to determine what algorithm to use for selecting TX
239 * queue. Select between the kernel provided function (select_queue=0) or user
240 * cxgb_select_queue function (select_queue=1)
241 *
242 * Default: select_queue=0
243 */
244static int select_queue;
245module_param(select_queue, int, 0644);
246MODULE_PARM_DESC(select_queue,
247 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
248
06640310 249static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
13ee15d3 250
f2b7e78d 251module_param(tp_vlan_pri_map, uint, 0644);
06640310
HS		 252MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
253 "deprecated parameter");
f2b7e78d 254
b8ff05a9
DM		 255static struct dentry *cxgb4_debugfs_root;
256
257static LIST_HEAD(adapter_list);
258static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 259/* Adapter list to be accessed from atomic context */
260static LIST_HEAD(adap_rcu_list);
261static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 262static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
263static const char *uld_str[] = { "RDMA", "iSCSI" };
264
265static void link_report(struct net_device *dev)
266{
267 if (!netif_carrier_ok(dev))
268 netdev_info(dev, "link down\n");
269 else {
270 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
271
272 const char *s = "10Mbps";
273 const struct port_info *p = netdev_priv(dev);
274
275 switch (p->link_cfg.speed) {
e8b39015 276 case 10000:
b8ff05a9
DM		 277 s = "10Gbps";
278 break;
e8b39015 279 case 1000:
b8ff05a9
DM		 280 s = "1000Mbps";
281 break;
e8b39015 282 case 100:
b8ff05a9
DM		 283 s = "100Mbps";
284 break;
e8b39015 285 case 40000:
72aca4bf
KS		 286 s = "40Gbps";
287 break;
b8ff05a9
DM		 288 }
289
290 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
291 fc[p->link_cfg.fc]);
292 }
293}
294
688848b1
AB		 295#ifdef CONFIG_CHELSIO_T4_DCB
296/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
297static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
298{
299 struct port_info *pi = netdev_priv(dev);
300 struct adapter *adap = pi->adapter;
301 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
302 int i;
303
304 /* We use a simple mapping of Port TX Queue Index to DCB
305 * Priority when we're enabling DCB.
306 */
307 for (i = 0; i < pi->nqsets; i++, txq++) {
308 u32 name, value;
309 int err;
310
5167865a
HS		 311 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
312 FW_PARAMS_PARAM_X_V(
313 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
314 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 315 value = enable ? i : 0xffffffff;
316
317 /* Since we can be called while atomic (from "interrupt
318 * level") we need to issue the Set Parameters Commannd
319 * without sleeping (timeout < 0).
320 */
321 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
322 &name, &value);
323
324 if (err)
325 dev_err(adap->pdev_dev,
326 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
327 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 328 else
329 txq->dcb_prio = value;
688848b1
AB		 330 }
331}
332#endif /* CONFIG_CHELSIO_T4_DCB */
333
b8ff05a9
DM		 334void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
335{
336 struct net_device *dev = adapter->port[port_id];
337
338 /* Skip changes from disabled ports. */
339 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
340 if (link_stat)
341 netif_carrier_on(dev);
688848b1
AB		 342 else {
343#ifdef CONFIG_CHELSIO_T4_DCB
344 cxgb4_dcb_state_init(dev);
345 dcb_tx_queue_prio_enable(dev, false);
346#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 347 netif_carrier_off(dev);
688848b1 348 }
b8ff05a9
DM		 349
350 link_report(dev);
351 }
352}
353
354void t4_os_portmod_changed(const struct adapter *adap, int port_id)
355{
356 static const char *mod_str[] = {
a0881cab 357 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 358 };
359
360 const struct net_device *dev = adap->port[port_id];
361 const struct port_info *pi = netdev_priv(dev);
362
363 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
364 netdev_info(dev, "port module unplugged\n");
a0881cab 365 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 366 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
367}
368
369/*
370 * Configure the exact and hash address filters to handle a port's multicast
371 * and secondary unicast MAC addresses.
372 */
373static int set_addr_filters(const struct net_device *dev, bool sleep)
374{
375 u64 mhash = 0;
376 u64 uhash = 0;
377 bool free = true;
378 u16 filt_idx[7];
379 const u8 *addr[7];
380 int ret, naddr = 0;
b8ff05a9
DM		 381 const struct netdev_hw_addr *ha;
382 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 383 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 384 const struct port_info *pi = netdev_priv(dev);
060e0c75 385 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 386
387 /* first do the secondary unicast addresses */
388 netdev_for_each_uc_addr(ha, dev) {
389 addr[naddr++] = ha->addr;
390 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 391 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 392 naddr, addr, filt_idx, &uhash, sleep);
393 if (ret < 0)
394 return ret;
395
396 free = false;
397 naddr = 0;
398 }
399 }
400
401 /* next set up the multicast addresses */
4a35ecf8
DM		 402 netdev_for_each_mc_addr(ha, dev) {
403 addr[naddr++] = ha->addr;
404 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 405 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 406 naddr, addr, filt_idx, &mhash, sleep);
407 if (ret < 0)
408 return ret;
409
410 free = false;
411 naddr = 0;
412 }
413 }
414
060e0c75 415 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 416 uhash | mhash, sleep);
417}
418
3069ee9b
VP		 419int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
420module_param(dbfifo_int_thresh, int, 0644);
421MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
422
404d9e3f
VP		 423/*
424 * usecs to sleep while draining the dbfifo
425 */
426static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 427module_param(dbfifo_drain_delay, int, 0644);
428MODULE_PARM_DESC(dbfifo_drain_delay,
429 "usecs to sleep while draining the dbfifo");
430
b8ff05a9
DM		 431/*
432 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
433 * If @mtu is -1 it is left unchanged.
434 */
435static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
436{
437 int ret;
438 struct port_info *pi = netdev_priv(dev);
439
440 ret = set_addr_filters(dev, sleep_ok);
441 if (ret == 0)
060e0c75 442 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
b8ff05a9 443 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 444 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 445 sleep_ok);
446 return ret;
447}
448
449/**
450 * link_start - enable a port
451 * @dev: the port to enable
452 *
453 * Performs the MAC and PHY actions needed to enable a port.
454 */
455static int link_start(struct net_device *dev)
456{
457 int ret;
458 struct port_info *pi = netdev_priv(dev);
060e0c75 459 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 460
461 /*
462 * We do not set address filters and promiscuity here, the stack does
463 * that step explicitly.
464 */
060e0c75 465 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 466 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 467 if (ret == 0) {
060e0c75 468 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 469 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 470 true);
b8ff05a9
DM		 471 if (ret >= 0) {
472 pi->xact_addr_filt = ret;
473 ret = 0;
474 }
475 }
476 if (ret == 0)
060e0c75
DM		 477 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
478 &pi->link_cfg);
30f00847
AB		 479 if (ret == 0) {
480 local_bh_disable();
688848b1
AB		 481 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
482 true, CXGB4_DCB_ENABLED);
30f00847
AB		 483 local_bh_enable();
484 }
688848b1 485
b8ff05a9
DM		 486 return ret;
487}
488
688848b1
AB		 489int cxgb4_dcb_enabled(const struct net_device *dev)
490{
491#ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_info *pi = netdev_priv(dev);
493
3bb06261
AB		 494 if (!pi->dcb.enabled)
495 return 0;
496
497 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
498 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
688848b1
AB		 499#else
500 return 0;
501#endif
502}
503EXPORT_SYMBOL(cxgb4_dcb_enabled);
504
505#ifdef CONFIG_CHELSIO_T4_DCB
506/* Handle a Data Center Bridging update message from the firmware. */
507static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
508{
2b5fb1f2 509 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
688848b1
AB		 510 struct net_device *dev = adap->port[port];
511 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
512 int new_dcb_enabled;
513
514 cxgb4_dcb_handle_fw_update(adap, pcmd);
515 new_dcb_enabled = cxgb4_dcb_enabled(dev);
516
517 /* If the DCB has become enabled or disabled on the port then we're
518 * going to need to set up/tear down DCB Priority parameters for the
519 * TX Queues associated with the port.
520 */
521 if (new_dcb_enabled != old_dcb_enabled)
522 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
523}
524#endif /* CONFIG_CHELSIO_T4_DCB */
525
f2b7e78d
VP		 526/* Clear a filter and release any of its resources that we own. This also
527 * clears the filter's "pending" status.
528 */
529static void clear_filter(struct adapter *adap, struct filter_entry *f)
530{
531 /* If the new or old filter have loopback rewriteing rules then we'll
532 * need to free any existing Layer Two Table (L2T) entries of the old
533 * filter rule. The firmware will handle freeing up any Source MAC
534 * Table (SMT) entries used for rewriting Source MAC Addresses in
535 * loopback rules.
536 */
537 if (f->l2t)
538 cxgb4_l2t_release(f->l2t);
539
540 /* The zeroing of the filter rule below clears the filter valid,
541 * pending, locked flags, l2t pointer, etc. so it's all we need for
542 * this operation.
543 */
544 memset(f, 0, sizeof(*f));
545}
546
547/* Handle a filter write/deletion reply.
548 */
549static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
550{
551 unsigned int idx = GET_TID(rpl);
552 unsigned int nidx = idx - adap->tids.ftid_base;
553 unsigned int ret;
554 struct filter_entry *f;
555
556 if (idx >= adap->tids.ftid_base && nidx <
557 (adap->tids.nftids + adap->tids.nsftids)) {
558 idx = nidx;
bdc590b9 559 ret = TCB_COOKIE_G(rpl->cookie);
f2b7e78d
VP		 560 f = &adap->tids.ftid_tab[idx];
561
562 if (ret == FW_FILTER_WR_FLT_DELETED) {
563 /* Clear the filter when we get confirmation from the
564 * hardware that the filter has been deleted.
565 */
566 clear_filter(adap, f);
567 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
568 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
569 idx);
570 clear_filter(adap, f);
571 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
572 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
573 f->pending = 0; /* asynchronous setup completed */
574 f->valid = 1;
575 } else {
576 /* Something went wrong. Issue a warning about the
577 * problem and clear everything out.
578 */
579 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
580 idx, ret);
581 clear_filter(adap, f);
582 }
583 }
584}
585
586/* Response queue handler for the FW event queue.
b8ff05a9
DM		 587 */
588static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
589 const struct pkt_gl *gl)
590{
591 u8 opcode = ((const struct rss_header *)rsp)->opcode;
592
593 rsp++; /* skip RSS header */
b407a4a9
VP		 594
595 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
596 */
597 if (unlikely(opcode == CPL_FW4_MSG &&
598 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
599 rsp++;
600 opcode = ((const struct rss_header *)rsp)->opcode;
601 rsp++;
602 if (opcode != CPL_SGE_EGR_UPDATE) {
603 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
604 , opcode);
605 goto out;
606 }
607 }
608
b8ff05a9
DM		 609 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
610 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 611 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 612 struct sge_txq *txq;
b8ff05a9 613
e46dab4d 614 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 615 txq->restarts++;
e46dab4d 616 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 617 struct sge_eth_txq *eq;
618
619 eq = container_of(txq, struct sge_eth_txq, q);
620 netif_tx_wake_queue(eq->txq);
621 } else {
622 struct sge_ofld_txq *oq;
623
624 oq = container_of(txq, struct sge_ofld_txq, q);
625 tasklet_schedule(&oq->qresume_tsk);
626 }
627 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
628 const struct cpl_fw6_msg *p = (void *)rsp;
629
688848b1
AB		 630#ifdef CONFIG_CHELSIO_T4_DCB
631 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 632 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 633 unsigned int action =
2b5fb1f2 634 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 635
636 if (cmd == FW_PORT_CMD &&
637 action == FW_PORT_ACTION_GET_PORT_INFO) {
2b5fb1f2 638 int port = FW_PORT_CMD_PORTID_G(
688848b1
AB		 639 be32_to_cpu(pcmd->op_to_portid));
640 struct net_device *dev = q->adap->port[port];
641 int state_input = ((pcmd->u.info.dcbxdis_pkd &
2b5fb1f2 642 FW_PORT_CMD_DCBXDIS_F)
688848b1
AB		 643 ? CXGB4_DCB_INPUT_FW_DISABLED
644 : CXGB4_DCB_INPUT_FW_ENABLED);
645
646 cxgb4_dcb_state_fsm(dev, state_input);
647 }
648
649 if (cmd == FW_PORT_CMD &&
650 action == FW_PORT_ACTION_L2_DCB_CFG)
651 dcb_rpl(q->adap, pcmd);
652 else
653#endif
654 if (p->type == 0)
655 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 656 } else if (opcode == CPL_L2T_WRITE_RPL) {
657 const struct cpl_l2t_write_rpl *p = (void *)rsp;
658
659 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 660 } else if (opcode == CPL_SET_TCB_RPL) {
661 const struct cpl_set_tcb_rpl *p = (void *)rsp;
662
663 filter_rpl(q->adap, p);
b8ff05a9
DM		 664 } else
665 dev_err(q->adap->pdev_dev,
666 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 667out:
b8ff05a9
DM		 668 return 0;
669}
670
671/**
672 * uldrx_handler - response queue handler for ULD queues
673 * @q: the response queue that received the packet
674 * @rsp: the response queue descriptor holding the offload message
675 * @gl: the gather list of packet fragments
676 *
677 * Deliver an ingress offload packet to a ULD. All processing is done by
678 * the ULD, we just maintain statistics.
679 */
680static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
681 const struct pkt_gl *gl)
682{
683 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
684
b407a4a9
VP		 685 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
686 */
687 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
688 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
689 rsp += 2;
690
b8ff05a9
DM		 691 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
692 rxq->stats.nomem++;
693 return -1;
694 }
695 if (gl == NULL)
696 rxq->stats.imm++;
697 else if (gl == CXGB4_MSG_AN)
698 rxq->stats.an++;
699 else
700 rxq->stats.pkts++;
701 return 0;
702}
703
704static void disable_msi(struct adapter *adapter)
705{
706 if (adapter->flags & USING_MSIX) {
707 pci_disable_msix(adapter->pdev);
708 adapter->flags &= ~USING_MSIX;
709 } else if (adapter->flags & USING_MSI) {
710 pci_disable_msi(adapter->pdev);
711 adapter->flags &= ~USING_MSI;
712 }
713}
714
715/*
716 * Interrupt handler for non-data events used with MSI-X.
717 */
718static irqreturn_t t4_nondata_intr(int irq, void *cookie)
719{
720 struct adapter *adap = cookie;
0d804338 721 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 722
0d804338 723 if (v & PFSW_F) {
b8ff05a9 724 adap->swintr = 1;
0d804338 725 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 726 }
c3c7b121
HS		 727 if (adap->flags & MASTER_PF)
728 t4_slow_intr_handler(adap);
b8ff05a9
DM		 729 return IRQ_HANDLED;
730}
731
732/*
733 * Name the MSI-X interrupts.
734 */
735static void name_msix_vecs(struct adapter *adap)
736{
ba27816c 737 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 738
739 /* non-data interrupts */
b1a3c2b6 740 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 741
742 /* FW events */
b1a3c2b6
DM		 743 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
744 adap->port[0]->name);
b8ff05a9
DM		 745
746 /* Ethernet queues */
747 for_each_port(adap, j) {
748 struct net_device *d = adap->port[j];
749 const struct port_info *pi = netdev_priv(d);
750
ba27816c 751 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 752 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
753 d->name, i);
b8ff05a9
DM		 754 }
755
756 /* offload queues */
ba27816c
DM		 757 for_each_ofldrxq(&adap->sge, i)
758 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 759 adap->port[0]->name, i);
ba27816c
DM		 760
761 for_each_rdmarxq(&adap->sge, i)
762 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 763 adap->port[0]->name, i);
cf38be6d
HS		 764
765 for_each_rdmaciq(&adap->sge, i)
766 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
767 adap->port[0]->name, i);
b8ff05a9
DM		 768}
769
770static int request_msix_queue_irqs(struct adapter *adap)
771{
772 struct sge *s = &adap->sge;
cf38be6d
HS		 773 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
774 int msi_index = 2;
b8ff05a9
DM		 775
776 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
777 adap->msix_info[1].desc, &s->fw_evtq);
778 if (err)
779 return err;
780
781 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 782 err = request_irq(adap->msix_info[msi_index].vec,
783 t4_sge_intr_msix, 0,
784 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 785 &s->ethrxq[ethqidx].rspq);
786 if (err)
787 goto unwind;
404d9e3f 788 msi_index++;
b8ff05a9
DM		 789 }
790 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP		 791 err = request_irq(adap->msix_info[msi_index].vec,
792 t4_sge_intr_msix, 0,
793 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 794 &s->ofldrxq[ofldqidx].rspq);
795 if (err)
796 goto unwind;
404d9e3f 797 msi_index++;
b8ff05a9
DM		 798 }
799 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 800 err = request_irq(adap->msix_info[msi_index].vec,
801 t4_sge_intr_msix, 0,
802 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 803 &s->rdmarxq[rdmaqidx].rspq);
804 if (err)
805 goto unwind;
404d9e3f 806 msi_index++;
b8ff05a9 807 }
cf38be6d
HS		 808 for_each_rdmaciq(s, rdmaciqqidx) {
809 err = request_irq(adap->msix_info[msi_index].vec,
810 t4_sge_intr_msix, 0,
811 adap->msix_info[msi_index].desc,
812 &s->rdmaciq[rdmaciqqidx].rspq);
813 if (err)
814 goto unwind;
815 msi_index++;
816 }
b8ff05a9
DM		 817 return 0;
818
819unwind:
cf38be6d
HS		 820 while (--rdmaciqqidx >= 0)
821 free_irq(adap->msix_info[--msi_index].vec,
822 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 823 while (--rdmaqidx >= 0)
404d9e3f 824 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 825 &s->rdmarxq[rdmaqidx].rspq);
826 while (--ofldqidx >= 0)
404d9e3f 827 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 828 &s->ofldrxq[ofldqidx].rspq);
829 while (--ethqidx >= 0)
404d9e3f
VP		 830 free_irq(adap->msix_info[--msi_index].vec,
831 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 832 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
833 return err;
834}
835
836static void free_msix_queue_irqs(struct adapter *adap)
837{
404d9e3f 838 int i, msi_index = 2;
b8ff05a9
DM		 839 struct sge *s = &adap->sge;
840
841 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
842 for_each_ethrxq(s, i)
404d9e3f 843 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 844 for_each_ofldrxq(s, i)
404d9e3f 845 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 846 for_each_rdmarxq(s, i)
404d9e3f 847 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 848 for_each_rdmaciq(s, i)
849 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 850}
851
671b0060 852/**
812034f1 853 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 854 * @pi: the port
855 * @queues: array of queue indices for RSS
856 *
857 * Sets up the portion of the HW RSS table for the port's VI to distribute
858 * packets to the Rx queues in @queues.
c035e183 859 * Should never be called before setting up sge eth rx queues
671b0060 860 */
812034f1 861int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 862{
863 u16 *rss;
864 int i, err;
c035e183
HS		 865 struct adapter *adapter = pi->adapter;
866 const struct sge_eth_rxq *rxq;
671b0060 867
c035e183 868 rxq = &adapter->sge.ethrxq[pi->first_qset];
671b0060
DM		 869 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
870 if (!rss)
871 return -ENOMEM;
872
873 /* map the queue indices to queue ids */
874 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 875 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 876
c035e183 877 err = t4_config_rss_range(adapter, adapter->fn, pi->viid, 0,
060e0c75 878 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 879 /* If Tunnel All Lookup isn't specified in the global RSS
880 * Configuration, then we need to specify a default Ingress
881 * Queue for any ingress packets which aren't hashed. We'll
882 * use our first ingress queue ...
883 */
884 if (!err)
885 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
886 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
887 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
888 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
889 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
890 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
891 rss[0]);
671b0060
DM		 892 kfree(rss);
893 return err;
894}
895
b8ff05a9
DM		 896/**
897 * setup_rss - configure RSS
898 * @adap: the adapter
899 *
671b0060 900 * Sets up RSS for each port.
b8ff05a9
DM		 901 */
902static int setup_rss(struct adapter *adap)
903{
c035e183 904 int i, j, err;
b8ff05a9
DM		 905
906 for_each_port(adap, i) {
907 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 908
c035e183
HS		 909 /* Fill default values with equal distribution */
910 for (j = 0; j < pi->rss_size; j++)
911 pi->rss[j] = j % pi->nqsets;
912
812034f1 913 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 914 if (err)
915 return err;
916 }
917 return 0;
918}
919
e46dab4d
DM		 920/*
921 * Return the channel of the ingress queue with the given qid.
922 */
923static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
924{
925 qid -= p->ingr_start;
926 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
927}
928
b8ff05a9
DM		 929/*
930 * Wait until all NAPI handlers are descheduled.
931 */
932static void quiesce_rx(struct adapter *adap)
933{
934 int i;
935
4b8e27a8 936 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 937 struct sge_rspq *q = adap->sge.ingr_map[i];
938
3a336cb1 939 if (q && q->handler) {
b8ff05a9 940 napi_disable(&q->napi);
3a336cb1
HS		 941 local_bh_disable();
942 while (!cxgb_poll_lock_napi(q))
943 mdelay(1);
944 local_bh_enable();
945 }
946
b8ff05a9
DM		 947 }
948}
949
b37987e8
HS		 950/* Disable interrupt and napi handler */
951static void disable_interrupts(struct adapter *adap)
952{
953 if (adap->flags & FULL_INIT_DONE) {
954 t4_intr_disable(adap);
955 if (adap->flags & USING_MSIX) {
956 free_msix_queue_irqs(adap);
957 free_irq(adap->msix_info[0].vec, adap);
958 } else {
959 free_irq(adap->pdev->irq, adap);
960 }
961 quiesce_rx(adap);
962 }
963}
964
b8ff05a9
DM		 965/*
966 * Enable NAPI scheduling and interrupt generation for all Rx queues.
967 */
968static void enable_rx(struct adapter *adap)
969{
970 int i;
971
4b8e27a8 972 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 973 struct sge_rspq *q = adap->sge.ingr_map[i];
974
975 if (!q)
976 continue;
3a336cb1
HS		 977 if (q->handler) {
978 cxgb_busy_poll_init_lock(q);
b8ff05a9 979 napi_enable(&q->napi);
3a336cb1 980 }
b8ff05a9 981 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 982 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
983 SEINTARM_V(q->intr_params) |
984 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 985 }
986}
987
1c6a5b0e
HS		 988static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
989 unsigned int nq, unsigned int per_chan, int msi_idx,
990 u16 *ids)
991{
992 int i, err;
993
994 for (i = 0; i < nq; i++, q++) {
995 if (msi_idx > 0)
996 msi_idx++;
997 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
998 adap->port[i / per_chan],
999 msi_idx, q->fl.size ? &q->fl : NULL,
145ef8a5 1000 uldrx_handler, 0);
1c6a5b0e
HS		 1001 if (err)
1002 return err;
1003 memset(&q->stats, 0, sizeof(q->stats));
1004 if (ids)
1005 ids[i] = q->rspq.abs_id;
1006 }
1007 return 0;
1008}
1009
b8ff05a9
DM		 1010/**
1011 * setup_sge_queues - configure SGE Tx/Rx/response queues
1012 * @adap: the adapter
1013 *
1014 * Determines how many sets of SGE queues to use and initializes them.
1015 * We support multiple queue sets per port if we have MSI-X, otherwise
1016 * just one queue set per port.
1017 */
1018static int setup_sge_queues(struct adapter *adap)
1019{
1020 int err, msi_idx, i, j;
1021 struct sge *s = &adap->sge;
1022
4b8e27a8
HS		 1023 bitmap_zero(s->starving_fl, s->egr_sz);
1024 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 1025
1026 if (adap->flags & USING_MSIX)
1027 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1028 else {
1029 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
145ef8a5 1030 NULL, NULL, -1);
b8ff05a9
DM		 1031 if (err)
1032 return err;
1033 msi_idx = -((int)s->intrq.abs_id + 1);
1034 }
1035
4b8e27a8
HS		 1036 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1037 * don't forget to update the following which need to be
1038 * synchronized to and changes here.
1039 *
1040 * 1. The calculations of MAX_INGQ in cxgb4.h.
1041 *
1042 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1043 * to accommodate any new/deleted Ingress Queues
1044 * which need MSI-X Vectors.
1045 *
1046 * 3. Update sge_qinfo_show() to include information on the
1047 * new/deleted queues.
1048 */
b8ff05a9 1049 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
145ef8a5 1050 msi_idx, NULL, fwevtq_handler, -1);
b8ff05a9
DM		 1051 if (err) {
1052freeout: t4_free_sge_resources(adap);
1053 return err;
1054 }
1055
1056 for_each_port(adap, i) {
1057 struct net_device *dev = adap->port[i];
1058 struct port_info *pi = netdev_priv(dev);
1059 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1060 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1061
1062 for (j = 0; j < pi->nqsets; j++, q++) {
1063 if (msi_idx > 0)
1064 msi_idx++;
1065 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1066 msi_idx, &q->fl,
145ef8a5
HS		 1067 t4_ethrx_handler,
1068 t4_get_mps_bg_map(adap,
1069 pi->tx_chan));
b8ff05a9
DM		 1070 if (err)
1071 goto freeout;
1072 q->rspq.idx = j;
1073 memset(&q->stats, 0, sizeof(q->stats));
1074 }
1075 for (j = 0; j < pi->nqsets; j++, t++) {
1076 err = t4_sge_alloc_eth_txq(adap, t, dev,
1077 netdev_get_tx_queue(dev, j),
1078 s->fw_evtq.cntxt_id);
1079 if (err)
1080 goto freeout;
1081 }
1082 }
1083
1084 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1085 for_each_ofldrxq(s, i) {
1c6a5b0e
HS		 1086 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1087 adap->port[i / j],
b8ff05a9
DM		 1088 s->fw_evtq.cntxt_id);
1089 if (err)
1090 goto freeout;
1091 }
1092
1c6a5b0e
HS		 1093#define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1094 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1095 if (err) \
1096 goto freeout; \
1097 if (msi_idx > 0) \
1098 msi_idx += nq; \
1099} while (0)
b8ff05a9 1100
1c6a5b0e
HS		 1101 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1102 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
f36e58e5
HS		 1103 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1104 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
b8ff05a9 1105
1c6a5b0e 1106#undef ALLOC_OFLD_RXQS
cf38be6d 1107
b8ff05a9
DM		 1108 for_each_port(adap, i) {
1109 /*
1110 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1111 * have RDMA queues, and that's the right value.
1112 */
1113 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1114 s->fw_evtq.cntxt_id,
1115 s->rdmarxq[i].rspq.cntxt_id);
1116 if (err)
1117 goto freeout;
1118 }
1119
9bb59b96 1120 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 1121 MPS_TRC_RSS_CONTROL_A :
1122 MPS_T5_TRC_RSS_CONTROL_A,
1123 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1124 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9
DM		 1125 return 0;
1126}
1127
b8ff05a9
DM		 1128/*
1129 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1130 * The allocated memory is cleared.
1131 */
1132void *t4_alloc_mem(size_t size)
1133{
8be04b93 1134 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1135
1136 if (!p)
89bf67f1 1137 p = vzalloc(size);
b8ff05a9
DM		 1138 return p;
1139}
1140
1141/*
1142 * Free memory allocated through alloc_mem().
1143 */
fd88b31a 1144void t4_free_mem(void *addr)
b8ff05a9
DM		 1145{
1146 if (is_vmalloc_addr(addr))
1147 vfree(addr);
1148 else
1149 kfree(addr);
1150}
1151
f2b7e78d
VP		 1152/* Send a Work Request to write the filter at a specified index. We construct
1153 * a Firmware Filter Work Request to have the work done and put the indicated
1154 * filter into "pending" mode which will prevent any further actions against
1155 * it till we get a reply from the firmware on the completion status of the
1156 * request.
1157 */
1158static int set_filter_wr(struct adapter *adapter, int fidx)
1159{
1160 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1161 struct sk_buff *skb;
1162 struct fw_filter_wr *fwr;
1163 unsigned int ftid;
1164
f72f116a
MH		 1165 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1166 if (!skb)
1167 return -ENOMEM;
1168
f2b7e78d
VP		 1169 /* If the new filter requires loopback Destination MAC and/or VLAN
1170 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1171 * the filter.
1172 */
1173 if (f->fs.newdmac || f->fs.newvlan) {
1174 /* allocate L2T entry for new filter */
1175 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
f72f116a
MH		 1176 if (f->l2t == NULL) {
1177 kfree_skb(skb);
f2b7e78d 1178 return -EAGAIN;
f72f116a 1179 }
f2b7e78d
VP		 1180 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1181 f->fs.eport, f->fs.dmac)) {
1182 cxgb4_l2t_release(f->l2t);
1183 f->l2t = NULL;
f72f116a 1184 kfree_skb(skb);
f2b7e78d
VP		 1185 return -ENOMEM;
1186 }
1187 }
1188
1189 ftid = adapter->tids.ftid_base + fidx;
1190
f2b7e78d
VP		 1191 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1192 memset(fwr, 0, sizeof(*fwr));
1193
1194 /* It would be nice to put most of the following in t4_hw.c but most
1195 * of the work is translating the cxgbtool ch_filter_specification
1196 * into the Work Request and the definition of that structure is
1197 * currently in cxgbtool.h which isn't appropriate to pull into the
1198 * common code. We may eventually try to come up with a more neutral
1199 * filter specification structure but for now it's easiest to simply
1200 * put this fairly direct code in line ...
1201 */
e2ac9628
HS		 1202 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1203 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
f2b7e78d 1204 fwr->tid_to_iq =
77a80e23
HS		 1205 htonl(FW_FILTER_WR_TID_V(ftid) |
1206 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1207 FW_FILTER_WR_NOREPLY_V(0) |
1208 FW_FILTER_WR_IQ_V(f->fs.iq));
f2b7e78d 1209 fwr->del_filter_to_l2tix =
77a80e23
HS		 1210 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1211 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1212 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1213 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1214 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1215 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1216 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1217 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1218 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f2b7e78d 1219 f->fs.newvlan == VLAN_REWRITE) |
77a80e23 1220 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
f2b7e78d 1221 f->fs.newvlan == VLAN_REWRITE) |
77a80e23
HS		 1222 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1223 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1224 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1225 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
f2b7e78d
VP		 1226 fwr->ethtype = htons(f->fs.val.ethtype);
1227 fwr->ethtypem = htons(f->fs.mask.ethtype);
1228 fwr->frag_to_ovlan_vldm =
77a80e23
HS		 1229 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1230 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1231 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1232 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1233 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1234 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
f2b7e78d
VP		 1235 fwr->smac_sel = 0;
1236 fwr->rx_chan_rx_rpl_iq =
77a80e23
HS		 1237 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1238 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
f2b7e78d 1239 fwr->maci_to_matchtypem =
77a80e23
HS		 1240 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1241 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1242 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1243 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1244 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1245 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1246 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1247 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
f2b7e78d
VP		 1248 fwr->ptcl = f->fs.val.proto;
1249 fwr->ptclm = f->fs.mask.proto;
1250 fwr->ttyp = f->fs.val.tos;
1251 fwr->ttypm = f->fs.mask.tos;
1252 fwr->ivlan = htons(f->fs.val.ivlan);
1253 fwr->ivlanm = htons(f->fs.mask.ivlan);
1254 fwr->ovlan = htons(f->fs.val.ovlan);
1255 fwr->ovlanm = htons(f->fs.mask.ovlan);
1256 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1257 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1258 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1259 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1260 fwr->lp = htons(f->fs.val.lport);
1261 fwr->lpm = htons(f->fs.mask.lport);
1262 fwr->fp = htons(f->fs.val.fport);
1263 fwr->fpm = htons(f->fs.mask.fport);
1264 if (f->fs.newsmac)
1265 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1266
1267 /* Mark the filter as "pending" and ship off the Filter Work Request.
1268 * When we get the Work Request Reply we'll clear the pending status.
1269 */
1270 f->pending = 1;
1271 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1272 t4_ofld_send(adapter, skb);
1273 return 0;
1274}
1275
1276/* Delete the filter at a specified index.
1277 */
1278static int del_filter_wr(struct adapter *adapter, int fidx)
1279{
1280 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1281 struct sk_buff *skb;
1282 struct fw_filter_wr *fwr;
1283 unsigned int len, ftid;
1284
1285 len = sizeof(*fwr);
1286 ftid = adapter->tids.ftid_base + fidx;
1287
f72f116a
MH		 1288 skb = alloc_skb(len, GFP_KERNEL);
1289 if (!skb)
1290 return -ENOMEM;
1291
f2b7e78d
VP		 1292 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1293 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1294
1295 /* Mark the filter as "pending" and ship off the Filter Work Request.
1296 * When we get the Work Request Reply we'll clear the pending status.
1297 */
1298 f->pending = 1;
1299 t4_mgmt_tx(adapter, skb);
1300 return 0;
1301}
1302
688848b1
AB		 1303static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1304 void *accel_priv, select_queue_fallback_t fallback)
1305{
1306 int txq;
1307
1308#ifdef CONFIG_CHELSIO_T4_DCB
1309 /* If a Data Center Bridging has been successfully negotiated on this
1310 * link then we'll use the skb's priority to map it to a TX Queue.
1311 * The skb's priority is determined via the VLAN Tag Priority Code
1312 * Point field.
1313 */
1314 if (cxgb4_dcb_enabled(dev)) {
1315 u16 vlan_tci;
1316 int err;
1317
1318 err = vlan_get_tag(skb, &vlan_tci);
1319 if (unlikely(err)) {
1320 if (net_ratelimit())
1321 netdev_warn(dev,
1322 "TX Packet without VLAN Tag on DCB Link\n");
1323 txq = 0;
1324 } else {
1325 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 1326#ifdef CONFIG_CHELSIO_T4_FCOE
1327 if (skb->protocol == htons(ETH_P_FCOE))
1328 txq = skb->priority & 0x7;
1329#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 1330 }
1331 return txq;
1332 }
1333#endif /* CONFIG_CHELSIO_T4_DCB */
1334
1335 if (select_queue) {
1336 txq = (skb_rx_queue_recorded(skb)
1337 ? skb_get_rx_queue(skb)
1338 : smp_processor_id());
1339
1340 while (unlikely(txq >= dev->real_num_tx_queues))
1341 txq -= dev->real_num_tx_queues;
1342
1343 return txq;
1344 }
1345
1346 return fallback(dev, skb) % dev->real_num_tx_queues;
1347}
1348
b8ff05a9
DM		 1349static inline int is_offload(const struct adapter *adap)
1350{
1351 return adap->params.offload;
1352}
1353
b8ff05a9
DM		 1354static int closest_timer(const struct sge *s, int time)
1355{
1356 int i, delta, match = 0, min_delta = INT_MAX;
1357
1358 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1359 delta = time - s->timer_val[i];
1360 if (delta < 0)
1361 delta = -delta;
1362 if (delta < min_delta) {
1363 min_delta = delta;
1364 match = i;
1365 }
1366 }
1367 return match;
1368}
1369
1370static int closest_thres(const struct sge *s, int thres)
1371{
1372 int i, delta, match = 0, min_delta = INT_MAX;
1373
1374 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1375 delta = thres - s->counter_val[i];
1376 if (delta < 0)
1377 delta = -delta;
1378 if (delta < min_delta) {
1379 min_delta = delta;
1380 match = i;
1381 }
1382 }
1383 return match;
1384}
1385
b8ff05a9 1386/**
812034f1 1387 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1388 * @q: the Rx queue
1389 * @us: the hold-off time in us, or 0 to disable timer
1390 * @cnt: the hold-off packet count, or 0 to disable counter
1391 *
1392 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1393 * one of the two needs to be enabled for the queue to generate interrupts.
1394 */
812034f1
HS		 1395int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1396 unsigned int us, unsigned int cnt)
b8ff05a9 1397{
c887ad0e
HS		 1398 struct adapter *adap = q->adap;
1399
b8ff05a9
DM		 1400 if ((us | cnt) == 0)
1401 cnt = 1;
1402
1403 if (cnt) {
1404 int err;
1405 u32 v, new_idx;
1406
1407 new_idx = closest_thres(&adap->sge, cnt);
1408 if (q->desc && q->pktcnt_idx != new_idx) {
1409 /* the queue has already been created, update it */
5167865a
HS		 1410 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1411 FW_PARAMS_PARAM_X_V(
1412 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1413 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
060e0c75
DM		 1414 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
1415 &new_idx);
b8ff05a9
DM		 1416 if (err)
1417 return err;
1418 }
1419 q->pktcnt_idx = new_idx;
1420 }
1421
1422 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1423 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1424 return 0;
1425}
1426
c8f44aff 1427static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1428{
2ed28baa 1429 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1430 netdev_features_t changed = dev->features ^ features;
19ecae2c 1431 int err;
19ecae2c 1432
f646968f 1433 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1434 return 0;
19ecae2c 1435
2ed28baa
MM		 1436 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
1437 -1, -1, -1,
f646968f 1438 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1439 if (unlikely(err))
f646968f 1440 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1441 return err;
87b6cf51
DM		 1442}
1443
91744948 1444static int setup_debugfs(struct adapter *adap)
b8ff05a9 1445{
b8ff05a9
DM		 1446 if (IS_ERR_OR_NULL(adap->debugfs_root))
1447 return -1;
1448
fd88b31a
HS		 1449#ifdef CONFIG_DEBUG_FS
1450 t4_setup_debugfs(adap);
1451#endif
b8ff05a9
DM		 1452 return 0;
1453}
1454
1455/*
1456 * upper-layer driver support
1457 */
1458
1459/*
1460 * Allocate an active-open TID and set it to the supplied value.
1461 */
1462int cxgb4_alloc_atid(struct tid_info *t, void *data)
1463{
1464 int atid = -1;
1465
1466 spin_lock_bh(&t->atid_lock);
1467 if (t->afree) {
1468 union aopen_entry *p = t->afree;
1469
f2b7e78d 1470 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1471 t->afree = p->next;
1472 p->data = data;
1473 t->atids_in_use++;
1474 }
1475 spin_unlock_bh(&t->atid_lock);
1476 return atid;
1477}
1478EXPORT_SYMBOL(cxgb4_alloc_atid);
1479
1480/*
1481 * Release an active-open TID.
1482 */
1483void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1484{
f2b7e78d 1485 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1486
1487 spin_lock_bh(&t->atid_lock);
1488 p->next = t->afree;
1489 t->afree = p;
1490 t->atids_in_use--;
1491 spin_unlock_bh(&t->atid_lock);
1492}
1493EXPORT_SYMBOL(cxgb4_free_atid);
1494
1495/*
1496 * Allocate a server TID and set it to the supplied value.
1497 */
1498int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1499{
1500 int stid;
1501
1502 spin_lock_bh(&t->stid_lock);
1503 if (family == PF_INET) {
1504 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1505 if (stid < t->nstids)
1506 __set_bit(stid, t->stid_bmap);
1507 else
1508 stid = -1;
1509 } else {
1510 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1511 if (stid < 0)
1512 stid = -1;
1513 }
1514 if (stid >= 0) {
1515 t->stid_tab[stid].data = data;
1516 stid += t->stid_base;
15f63b74
KS		 1517 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1518 * This is equivalent to 4 TIDs. With CLIP enabled it
1519 * needs 2 TIDs.
1520 */
1521 if (family == PF_INET)
1522 t->stids_in_use++;
1523 else
1524 t->stids_in_use += 4;
b8ff05a9
DM		 1525 }
1526 spin_unlock_bh(&t->stid_lock);
1527 return stid;
1528}
1529EXPORT_SYMBOL(cxgb4_alloc_stid);
1530
dca4faeb
VP		 1531/* Allocate a server filter TID and set it to the supplied value.
1532 */
1533int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1534{
1535 int stid;
1536
1537 spin_lock_bh(&t->stid_lock);
1538 if (family == PF_INET) {
1539 stid = find_next_zero_bit(t->stid_bmap,
1540 t->nstids + t->nsftids, t->nstids);
1541 if (stid < (t->nstids + t->nsftids))
1542 __set_bit(stid, t->stid_bmap);
1543 else
1544 stid = -1;
1545 } else {
1546 stid = -1;
1547 }
1548 if (stid >= 0) {
1549 t->stid_tab[stid].data = data;
470c60c4
KS		 1550 stid -= t->nstids;
1551 stid += t->sftid_base;
dca4faeb
VP		 1552 t->stids_in_use++;
1553 }
1554 spin_unlock_bh(&t->stid_lock);
1555 return stid;
1556}
1557EXPORT_SYMBOL(cxgb4_alloc_sftid);
1558
1559/* Release a server TID.
b8ff05a9
DM		 1560 */
1561void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1562{
470c60c4
KS		 1563 /* Is it a server filter TID? */
1564 if (t->nsftids && (stid >= t->sftid_base)) {
1565 stid -= t->sftid_base;
1566 stid += t->nstids;
1567 } else {
1568 stid -= t->stid_base;
1569 }
1570
b8ff05a9
DM		 1571 spin_lock_bh(&t->stid_lock);
1572 if (family == PF_INET)
1573 __clear_bit(stid, t->stid_bmap);
1574 else
1575 bitmap_release_region(t->stid_bmap, stid, 2);
1576 t->stid_tab[stid].data = NULL;
15f63b74
KS		 1577 if (family == PF_INET)
1578 t->stids_in_use--;
1579 else
1580 t->stids_in_use -= 4;
b8ff05a9
DM		 1581 spin_unlock_bh(&t->stid_lock);
1582}
1583EXPORT_SYMBOL(cxgb4_free_stid);
1584
1585/*
1586 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1587 */
1588static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1589 unsigned int tid)
1590{
1591 struct cpl_tid_release *req;
1592
1593 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1594 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1595 INIT_TP_WR(req, tid);
1596 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1597}
1598
1599/*
1600 * Queue a TID release request and if necessary schedule a work queue to
1601 * process it.
1602 */
31b9c19b 1603static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1604 unsigned int tid)
b8ff05a9
DM		 1605{
1606 void **p = &t->tid_tab[tid];
1607 struct adapter *adap = container_of(t, struct adapter, tids);
1608
1609 spin_lock_bh(&adap->tid_release_lock);
1610 *p = adap->tid_release_head;
1611 /* Low 2 bits encode the Tx channel number */
1612 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1613 if (!adap->tid_release_task_busy) {
1614 adap->tid_release_task_busy = true;
29aaee65 1615 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1616 }
1617 spin_unlock_bh(&adap->tid_release_lock);
1618}
b8ff05a9
DM		 1619
1620/*
1621 * Process the list of pending TID release requests.
1622 */
1623static void process_tid_release_list(struct work_struct *work)
1624{
1625 struct sk_buff *skb;
1626 struct adapter *adap;
1627
1628 adap = container_of(work, struct adapter, tid_release_task);
1629
1630 spin_lock_bh(&adap->tid_release_lock);
1631 while (adap->tid_release_head) {
1632 void **p = adap->tid_release_head;
1633 unsigned int chan = (uintptr_t)p & 3;
1634 p = (void *)p - chan;
1635
1636 adap->tid_release_head = *p;
1637 *p = NULL;
1638 spin_unlock_bh(&adap->tid_release_lock);
1639
1640 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1641 GFP_KERNEL)))
1642 schedule_timeout_uninterruptible(1);
1643
1644 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1645 t4_ofld_send(adap, skb);
1646 spin_lock_bh(&adap->tid_release_lock);
1647 }
1648 adap->tid_release_task_busy = false;
1649 spin_unlock_bh(&adap->tid_release_lock);
1650}
1651
1652/*
1653 * Release a TID and inform HW. If we are unable to allocate the release
1654 * message we defer to a work queue.
1655 */
1656void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1657{
1658 void *old;
1659 struct sk_buff *skb;
1660 struct adapter *adap = container_of(t, struct adapter, tids);
1661
1662 old = t->tid_tab[tid];
1663 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1664 if (likely(skb)) {
1665 t->tid_tab[tid] = NULL;
1666 mk_tid_release(skb, chan, tid);
1667 t4_ofld_send(adap, skb);
1668 } else
1669 cxgb4_queue_tid_release(t, chan, tid);
1670 if (old)
1671 atomic_dec(&t->tids_in_use);
1672}
1673EXPORT_SYMBOL(cxgb4_remove_tid);
1674
1675/*
1676 * Allocate and initialize the TID tables. Returns 0 on success.
1677 */
1678static int tid_init(struct tid_info *t)
1679{
1680 size_t size;
f2b7e78d 1681 unsigned int stid_bmap_size;
b8ff05a9 1682 unsigned int natids = t->natids;
b6f8eaec 1683 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 1684
dca4faeb 1685 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 1686 size = t->ntids * sizeof(*t->tid_tab) +
1687 natids * sizeof(*t->atid_tab) +
b8ff05a9 1688 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1689 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1690 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 1691 t->nftids * sizeof(*t->ftid_tab) +
1692 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 1693
b8ff05a9
DM		 1694 t->tid_tab = t4_alloc_mem(size);
1695 if (!t->tid_tab)
1696 return -ENOMEM;
1697
1698 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1699 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1700 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1701 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 1702 spin_lock_init(&t->stid_lock);
1703 spin_lock_init(&t->atid_lock);
1704
1705 t->stids_in_use = 0;
1706 t->afree = NULL;
1707 t->atids_in_use = 0;
1708 atomic_set(&t->tids_in_use, 0);
1709
1710 /* Setup the free list for atid_tab and clear the stid bitmap. */
1711 if (natids) {
1712 while (--natids)
1713 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1714 t->afree = t->atid_tab;
1715 }
dca4faeb 1716 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 1717 /* Reserve stid 0 for T4/T5 adapters */
1718 if (!t->stid_base &&
1719 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
1720 __set_bit(0, t->stid_bmap);
1721
b8ff05a9
DM		 1722 return 0;
1723}
1724
1725/**
1726 * cxgb4_create_server - create an IP server
1727 * @dev: the device
1728 * @stid: the server TID
1729 * @sip: local IP address to bind server to
1730 * @sport: the server's TCP port
1731 * @queue: queue to direct messages from this server to
1732 *
1733 * Create an IP server for the given port and address.
1734 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1735 */
1736int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1737 __be32 sip, __be16 sport, __be16 vlan,
1738 unsigned int queue)
b8ff05a9
DM		 1739{
1740 unsigned int chan;
1741 struct sk_buff *skb;
1742 struct adapter *adap;
1743 struct cpl_pass_open_req *req;
80f40c1f 1744 int ret;
b8ff05a9
DM		 1745
1746 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1747 if (!skb)
1748 return -ENOMEM;
1749
1750 adap = netdev2adap(dev);
1751 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1752 INIT_TP_WR(req, 0);
1753 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1754 req->local_port = sport;
1755 req->peer_port = htons(0);
1756 req->local_ip = sip;
1757 req->peer_ip = htonl(0);
e46dab4d 1758 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1759 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1760 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1761 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1762 ret = t4_mgmt_tx(adap, skb);
1763 return net_xmit_eval(ret);
b8ff05a9
DM		 1764}
1765EXPORT_SYMBOL(cxgb4_create_server);
1766
80f40c1f
VP		 1767/* cxgb4_create_server6 - create an IPv6 server
1768 * @dev: the device
1769 * @stid: the server TID
1770 * @sip: local IPv6 address to bind server to
1771 * @sport: the server's TCP port
1772 * @queue: queue to direct messages from this server to
1773 *
1774 * Create an IPv6 server for the given port and address.
1775 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1776 */
1777int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1778 const struct in6_addr *sip, __be16 sport,
1779 unsigned int queue)
1780{
1781 unsigned int chan;
1782 struct sk_buff *skb;
1783 struct adapter *adap;
1784 struct cpl_pass_open_req6 *req;
1785 int ret;
1786
1787 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1788 if (!skb)
1789 return -ENOMEM;
1790
1791 adap = netdev2adap(dev);
1792 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1793 INIT_TP_WR(req, 0);
1794 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1795 req->local_port = sport;
1796 req->peer_port = htons(0);
1797 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1798 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1799 req->peer_ip_hi = cpu_to_be64(0);
1800 req->peer_ip_lo = cpu_to_be64(0);
1801 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1802 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1803 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1804 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1805 ret = t4_mgmt_tx(adap, skb);
1806 return net_xmit_eval(ret);
1807}
1808EXPORT_SYMBOL(cxgb4_create_server6);
1809
1810int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1811 unsigned int queue, bool ipv6)
1812{
1813 struct sk_buff *skb;
1814 struct adapter *adap;
1815 struct cpl_close_listsvr_req *req;
1816 int ret;
1817
1818 adap = netdev2adap(dev);
1819
1820 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1821 if (!skb)
1822 return -ENOMEM;
1823
1824 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1825 INIT_TP_WR(req, 0);
1826 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1827 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1828 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1829 ret = t4_mgmt_tx(adap, skb);
1830 return net_xmit_eval(ret);
1831}
1832EXPORT_SYMBOL(cxgb4_remove_server);
1833
b8ff05a9
DM		 1834/**
1835 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1836 * @mtus: the HW MTU table
1837 * @mtu: the target MTU
1838 * @idx: index of selected entry in the MTU table
1839 *
1840 * Returns the index and the value in the HW MTU table that is closest to
1841 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1842 * table, in which case that smallest available value is selected.
1843 */
1844unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1845 unsigned int *idx)
1846{
1847 unsigned int i = 0;
1848
1849 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1850 ++i;
1851 if (idx)
1852 *idx = i;
1853 return mtus[i];
1854}
1855EXPORT_SYMBOL(cxgb4_best_mtu);
1856
92e7ae71
HS		 1857/**
1858 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1859 * @mtus: the HW MTU table
1860 * @header_size: Header Size
1861 * @data_size_max: maximum Data Segment Size
1862 * @data_size_align: desired Data Segment Size Alignment (2^N)
1863 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1864 *
1865 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1866 * MTU Table based solely on a Maximum MTU parameter, we break that
1867 * parameter up into a Header Size and Maximum Data Segment Size, and
1868 * provide a desired Data Segment Size Alignment. If we find an MTU in
1869 * the Hardware MTU Table which will result in a Data Segment Size with
1870 * the requested alignment _and_ that MTU isn't "too far" from the
1871 * closest MTU, then we'll return that rather than the closest MTU.
1872 */
1873unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1874 unsigned short header_size,
1875 unsigned short data_size_max,
1876 unsigned short data_size_align,
1877 unsigned int *mtu_idxp)
1878{
1879 unsigned short max_mtu = header_size + data_size_max;
1880 unsigned short data_size_align_mask = data_size_align - 1;
1881 int mtu_idx, aligned_mtu_idx;
1882
1883 /* Scan the MTU Table till we find an MTU which is larger than our
1884 * Maximum MTU or we reach the end of the table. Along the way,
1885 * record the last MTU found, if any, which will result in a Data
1886 * Segment Length matching the requested alignment.
1887 */
1888 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1889 unsigned short data_size = mtus[mtu_idx] - header_size;
1890
1891 /* If this MTU minus the Header Size would result in a
1892 * Data Segment Size of the desired alignment, remember it.
1893 */
1894 if ((data_size & data_size_align_mask) == 0)
1895 aligned_mtu_idx = mtu_idx;
1896
1897 /* If we're not at the end of the Hardware MTU Table and the
1898 * next element is larger than our Maximum MTU, drop out of
1899 * the loop.
1900 */
1901 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1902 break;
1903 }
1904
1905 /* If we fell out of the loop because we ran to the end of the table,
1906 * then we just have to use the last [largest] entry.
1907 */
1908 if (mtu_idx == NMTUS)
1909 mtu_idx--;
1910
1911 /* If we found an MTU which resulted in the requested Data Segment
1912 * Length alignment and that's "not far" from the largest MTU which is
1913 * less than or equal to the maximum MTU, then use that.
1914 */
1915 if (aligned_mtu_idx >= 0 &&
1916 mtu_idx - aligned_mtu_idx <= 1)
1917 mtu_idx = aligned_mtu_idx;
1918
1919 /* If the caller has passed in an MTU Index pointer, pass the
1920 * MTU Index back. Return the MTU value.
1921 */
1922 if (mtu_idxp)
1923 *mtu_idxp = mtu_idx;
1924 return mtus[mtu_idx];
1925}
1926EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1927
b8ff05a9
DM		 1928/**
1929 * cxgb4_port_chan - get the HW channel of a port
1930 * @dev: the net device for the port
1931 *
1932 * Return the HW Tx channel of the given port.
1933 */
1934unsigned int cxgb4_port_chan(const struct net_device *dev)
1935{
1936 return netdev2pinfo(dev)->tx_chan;
1937}
1938EXPORT_SYMBOL(cxgb4_port_chan);
1939
881806bc
VP		 1940unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1941{
1942 struct adapter *adap = netdev2adap(dev);
2cc301d2 1943 u32 v1, v2, lp_count, hp_count;
881806bc 1944
f061de42
HS		 1945 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1946 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1947 if (is_t4(adap->params.chip)) {
f061de42
HS		 1948 lp_count = LP_COUNT_G(v1);
1949 hp_count = HP_COUNT_G(v1);
2cc301d2 1950 } else {
f061de42
HS		 1951 lp_count = LP_COUNT_T5_G(v1);
1952 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1953 }
1954 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1955}
1956EXPORT_SYMBOL(cxgb4_dbfifo_count);
1957
b8ff05a9
DM		 1958/**
1959 * cxgb4_port_viid - get the VI id of a port
1960 * @dev: the net device for the port
1961 *
1962 * Return the VI id of the given port.
1963 */
1964unsigned int cxgb4_port_viid(const struct net_device *dev)
1965{
1966 return netdev2pinfo(dev)->viid;
1967}
1968EXPORT_SYMBOL(cxgb4_port_viid);
1969
1970/**
1971 * cxgb4_port_idx - get the index of a port
1972 * @dev: the net device for the port
1973 *
1974 * Return the index of the given port.
1975 */
1976unsigned int cxgb4_port_idx(const struct net_device *dev)
1977{
1978 return netdev2pinfo(dev)->port_id;
1979}
1980EXPORT_SYMBOL(cxgb4_port_idx);
1981
b8ff05a9
DM		 1982void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1983 struct tp_tcp_stats *v6)
1984{
1985 struct adapter *adap = pci_get_drvdata(pdev);
1986
1987 spin_lock(&adap->stats_lock);
1988 t4_tp_get_tcp_stats(adap, v4, v6);
1989 spin_unlock(&adap->stats_lock);
1990}
1991EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1992
1993void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1994 const unsigned int *pgsz_order)
1995{
1996 struct adapter *adap = netdev2adap(dev);
1997
0d804338
HS		 1998 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1999 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2000 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2001 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 2002}
2003EXPORT_SYMBOL(cxgb4_iscsi_init);
2004
3069ee9b
VP		 2005int cxgb4_flush_eq_cache(struct net_device *dev)
2006{
2007 struct adapter *adap = netdev2adap(dev);
2008 int ret;
2009
2010 ret = t4_fwaddrspace_write(adap, adap->mbox,
f061de42 2011 0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
3069ee9b
VP		 2012 return ret;
2013}
2014EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2015
2016static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2017{
f061de42 2018 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 2019 __be64 indices;
2020 int ret;
2021
fc5ab020
HS		 2022 spin_lock(&adap->win0_lock);
2023 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2024 sizeof(indices), (__be32 *)&indices,
2025 T4_MEMORY_READ);
2026 spin_unlock(&adap->win0_lock);
3069ee9b 2027 if (!ret) {
404d9e3f
VP		 2028 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2029 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 2030 }
2031 return ret;
2032}
2033
2034int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2035 u16 size)
2036{
2037 struct adapter *adap = netdev2adap(dev);
2038 u16 hw_pidx, hw_cidx;
2039 int ret;
2040
2041 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2042 if (ret)
2043 goto out;
2044
2045 if (pidx != hw_pidx) {
2046 u16 delta;
f612b815 2047 u32 val;
3069ee9b
VP		 2048
2049 if (pidx >= hw_pidx)
2050 delta = pidx - hw_pidx;
2051 else
2052 delta = size - hw_pidx + pidx;
f612b815
HS		 2053
2054 if (is_t4(adap->params.chip))
2055 val = PIDX_V(delta);
2056 else
2057 val = PIDX_T5_V(delta);
3069ee9b 2058 wmb();
f612b815
HS		 2059 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2060 QID_V(qid) | val);
3069ee9b
VP		 2061 }
2062out:
2063 return ret;
2064}
2065EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2066
3cbdb928
VP		 2067void cxgb4_disable_db_coalescing(struct net_device *dev)
2068{
2069 struct adapter *adap;
2070
2071 adap = netdev2adap(dev);
f061de42 2072 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
f612b815 2073 NOCOALESCE_F);
3cbdb928
VP		 2074}
2075EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
2076
2077void cxgb4_enable_db_coalescing(struct net_device *dev)
2078{
2079 struct adapter *adap;
2080
2081 adap = netdev2adap(dev);
f061de42 2082 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
3cbdb928
VP		 2083}
2084EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
2085
031cf476
HS		 2086int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2087{
2088 struct adapter *adap;
2089 u32 offset, memtype, memaddr;
6559a7e8 2090 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476
HS		 2091 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2092 int ret;
2093
2094 adap = netdev2adap(dev);
2095
2096 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2097
2098 /* Figure out where the offset lands in the Memory Type/Address scheme.
2099 * This code assumes that the memory is laid out starting at offset 0
2100 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2101 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2102 * MC0, and some have both MC0 and MC1.
2103 */
6559a7e8
HS		 2104 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2105 edc0_size = EDRAM0_SIZE_G(size) << 20;
2106 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2107 edc1_size = EDRAM1_SIZE_G(size) << 20;
2108 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2109 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476
HS		 2110
2111 edc0_end = edc0_size;
2112 edc1_end = edc0_end + edc1_size;
2113 mc0_end = edc1_end + mc0_size;
2114
2115 if (offset < edc0_end) {
2116 memtype = MEM_EDC0;
2117 memaddr = offset;
2118 } else if (offset < edc1_end) {
2119 memtype = MEM_EDC1;
2120 memaddr = offset - edc0_end;
2121 } else {
2122 if (offset < mc0_end) {
2123 memtype = MEM_MC0;
2124 memaddr = offset - edc1_end;
2125 } else if (is_t4(adap->params.chip)) {
2126 /* T4 only has a single memory channel */
2127 goto err;
2128 } else {
6559a7e8
HS		 2129 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2130 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 2131 mc1_end = mc0_end + mc1_size;
2132 if (offset < mc1_end) {
2133 memtype = MEM_MC1;
2134 memaddr = offset - mc0_end;
2135 } else {
2136 /* offset beyond the end of any memory */
2137 goto err;
2138 }
2139 }
2140 }
2141
2142 spin_lock(&adap->win0_lock);
2143 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2144 spin_unlock(&adap->win0_lock);
2145 return ret;
2146
2147err:
2148 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2149 stag, offset);
2150 return -EINVAL;
2151}
2152EXPORT_SYMBOL(cxgb4_read_tpte);
2153
7730b4c7
HS		 2154u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2155{
2156 u32 hi, lo;
2157 struct adapter *adap;
2158
2159 adap = netdev2adap(dev);
f612b815
HS		 2160 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2161 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 2162
2163 return ((u64)hi << 32) | (u64)lo;
2164}
2165EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2166
df64e4d3
HS		 2167int cxgb4_bar2_sge_qregs(struct net_device *dev,
2168 unsigned int qid,
2169 enum cxgb4_bar2_qtype qtype,
2170 u64 *pbar2_qoffset,
2171 unsigned int *pbar2_qid)
2172{
dd0bcc0b 2173 return cxgb4_t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 2174 qid,
2175 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2176 ? T4_BAR2_QTYPE_EGRESS
2177 : T4_BAR2_QTYPE_INGRESS),
2178 pbar2_qoffset,
2179 pbar2_qid);
2180}
2181EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2182
b8ff05a9
DM		 2183static struct pci_driver cxgb4_driver;
2184
2185static void check_neigh_update(struct neighbour *neigh)
2186{
2187 const struct device *parent;
2188 const struct net_device *netdev = neigh->dev;
2189
2190 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2191 netdev = vlan_dev_real_dev(netdev);
2192 parent = netdev->dev.parent;
2193 if (parent && parent->driver == &cxgb4_driver.driver)
2194 t4_l2t_update(dev_get_drvdata(parent), neigh);
2195}
2196
2197static int netevent_cb(struct notifier_block *nb, unsigned long event,
2198 void *data)
2199{
2200 switch (event) {
2201 case NETEVENT_NEIGH_UPDATE:
2202 check_neigh_update(data);
2203 break;
b8ff05a9
DM		 2204 case NETEVENT_REDIRECT:
2205 default:
2206 break;
2207 }
2208 return 0;
2209}
2210
2211static bool netevent_registered;
2212static struct notifier_block cxgb4_netevent_nb = {
2213 .notifier_call = netevent_cb
2214};
2215
3069ee9b
VP		 2216static void drain_db_fifo(struct adapter *adap, int usecs)
2217{
2cc301d2 2218 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 2219
2220 do {
f061de42
HS		 2221 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2222 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 2223 if (is_t4(adap->params.chip)) {
f061de42
HS		 2224 lp_count = LP_COUNT_G(v1);
2225 hp_count = HP_COUNT_G(v1);
2cc301d2 2226 } else {
f061de42
HS		 2227 lp_count = LP_COUNT_T5_G(v1);
2228 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 2229 }
2230
2231 if (lp_count == 0 && hp_count == 0)
2232 break;
3069ee9b
VP		 2233 set_current_state(TASK_UNINTERRUPTIBLE);
2234 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 2235 } while (1);
2236}
2237
2238static void disable_txq_db(struct sge_txq *q)
2239{
05eb2389
SW		 2240 unsigned long flags;
2241
2242 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 2243 q->db_disabled = 1;
05eb2389 2244 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 2245}
2246
05eb2389 2247static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 2248{
2249 spin_lock_irq(&q->db_lock);
05eb2389
SW		 2250 if (q->db_pidx_inc) {
2251 /* Make sure that all writes to the TX descriptors
2252 * are committed before we tell HW about them.
2253 */
2254 wmb();
f612b815
HS		 2255 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2256 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 2257 q->db_pidx_inc = 0;
2258 }
3069ee9b
VP		 2259 q->db_disabled = 0;
2260 spin_unlock_irq(&q->db_lock);
2261}
2262
2263static void disable_dbs(struct adapter *adap)
2264{
2265 int i;
2266
2267 for_each_ethrxq(&adap->sge, i)
2268 disable_txq_db(&adap->sge.ethtxq[i].q);
2269 for_each_ofldrxq(&adap->sge, i)
2270 disable_txq_db(&adap->sge.ofldtxq[i].q);
2271 for_each_port(adap, i)
2272 disable_txq_db(&adap->sge.ctrlq[i].q);
2273}
2274
2275static void enable_dbs(struct adapter *adap)
2276{
2277 int i;
2278
2279 for_each_ethrxq(&adap->sge, i)
05eb2389 2280 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 2281 for_each_ofldrxq(&adap->sge, i)
05eb2389 2282 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 2283 for_each_port(adap, i)
05eb2389
SW		 2284 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2285}
2286
2287static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2288{
2289 if (adap->uld_handle[CXGB4_ULD_RDMA])
2290 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2291 cmd);
2292}
2293
2294static void process_db_full(struct work_struct *work)
2295{
2296 struct adapter *adap;
2297
2298 adap = container_of(work, struct adapter, db_full_task);
2299
2300 drain_db_fifo(adap, dbfifo_drain_delay);
2301 enable_dbs(adap);
2302 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
f612b815
HS		 2303 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2304 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2305 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
3069ee9b
VP		 2306}
2307
2308static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2309{
2310 u16 hw_pidx, hw_cidx;
2311 int ret;
2312
05eb2389 2313 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 2314 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2315 if (ret)
2316 goto out;
2317 if (q->db_pidx != hw_pidx) {
2318 u16 delta;
f612b815 2319 u32 val;
3069ee9b
VP		 2320
2321 if (q->db_pidx >= hw_pidx)
2322 delta = q->db_pidx - hw_pidx;
2323 else
2324 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 2325
2326 if (is_t4(adap->params.chip))
2327 val = PIDX_V(delta);
2328 else
2329 val = PIDX_T5_V(delta);
3069ee9b 2330 wmb();
f612b815
HS		 2331 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2332 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2333 }
2334out:
2335 q->db_disabled = 0;
05eb2389
SW		 2336 q->db_pidx_inc = 0;
2337 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2338 if (ret)
2339 CH_WARN(adap, "DB drop recovery failed.\n");
2340}
2341static void recover_all_queues(struct adapter *adap)
2342{
2343 int i;
2344
2345 for_each_ethrxq(&adap->sge, i)
2346 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2347 for_each_ofldrxq(&adap->sge, i)
2348 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2349 for_each_port(adap, i)
2350 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2351}
2352
881806bc
VP		 2353static void process_db_drop(struct work_struct *work)
2354{
2355 struct adapter *adap;
881806bc 2356
3069ee9b 2357 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2358
d14807dd 2359 if (is_t4(adap->params.chip)) {
05eb2389 2360 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2361 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2362 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2363 recover_all_queues(adap);
05eb2389 2364 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2365 enable_dbs(adap);
05eb2389 2366 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2cc301d2
SR		 2367 } else {
2368 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2369 u16 qid = (dropped_db >> 15) & 0x1ffff;
2370 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2371 u64 bar2_qoffset;
2372 unsigned int bar2_qid;
2373 int ret;
2cc301d2 2374
dd0bcc0b 2375 ret = cxgb4_t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
df64e4d3
HS		 2376 &bar2_qoffset, &bar2_qid);
2377 if (ret)
2378 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2379 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2380 else
f612b815 2381 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2382 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2383
2384 /* Re-enable BAR2 WC */
2385 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2386 }
2387
f061de42 2388 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2389}
2390
2391void t4_db_full(struct adapter *adap)
2392{
d14807dd 2393 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2394 disable_dbs(adap);
2395 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2396 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2397 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2398 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2399 }
881806bc
VP		 2400}
2401
2402void t4_db_dropped(struct adapter *adap)
2403{
05eb2389
SW		 2404 if (is_t4(adap->params.chip)) {
2405 disable_dbs(adap);
2406 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2407 }
29aaee65 2408 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2409}
2410
b8ff05a9
DM		 2411static void uld_attach(struct adapter *adap, unsigned int uld)
2412{
2413 void *handle;
2414 struct cxgb4_lld_info lli;
dca4faeb 2415 unsigned short i;
b8ff05a9
DM		 2416
2417 lli.pdev = adap->pdev;
35b1de55 2418 lli.pf = adap->fn;
b8ff05a9
DM		 2419 lli.l2t = adap->l2t;
2420 lli.tids = &adap->tids;
2421 lli.ports = adap->port;
2422 lli.vr = &adap->vres;
2423 lli.mtus = adap->params.mtus;
2424 if (uld == CXGB4_ULD_RDMA) {
2425 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 2426 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 2427 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 2428 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM		 2429 } else if (uld == CXGB4_ULD_ISCSI) {
2430 lli.rxq_ids = adap->sge.ofld_rxq;
2431 lli.nrxq = adap->sge.ofldqsets;
2432 }
2433 lli.ntxq = adap->sge.ofldqsets;
2434 lli.nchan = adap->params.nports;
2435 lli.nports = adap->params.nports;
2436 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 2437 lli.adapter_type = adap->params.chip;
837e4a42 2438 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
7730b4c7 2439 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
df64e4d3
HS		 2440 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2441 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
dcf7b6f5 2442 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 2443 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2444 for (i = 0; i < NCHAN; i++)
2445 lli.tx_modq[i] = i;
f612b815
HS		 2446 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2447 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
b8ff05a9 2448 lli.fw_vers = adap->params.fw_vers;
3069ee9b 2449 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS		 2450 lli.sge_ingpadboundary = adap->sge.fl_align;
2451 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP		 2452 lli.sge_pktshift = adap->sge.pktshift;
2453 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS		 2454 lli.max_ordird_qp = adap->params.max_ordird_qp;
2455 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 2456 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
982b81eb 2457 lli.nodeid = dev_to_node(adap->pdev_dev);
b8ff05a9
DM		 2458
2459 handle = ulds[uld].add(&lli);
2460 if (IS_ERR(handle)) {
2461 dev_warn(adap->pdev_dev,
2462 "could not attach to the %s driver, error %ld\n",
2463 uld_str[uld], PTR_ERR(handle));
2464 return;
2465 }
2466
2467 adap->uld_handle[uld] = handle;
2468
2469 if (!netevent_registered) {
2470 register_netevent_notifier(&cxgb4_netevent_nb);
2471 netevent_registered = true;
2472 }
e29f5dbc
DM		 2473
2474 if (adap->flags & FULL_INIT_DONE)
2475 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 2476}
2477
2478static void attach_ulds(struct adapter *adap)
2479{
2480 unsigned int i;
2481
01bcca68
VP		 2482 spin_lock(&adap_rcu_lock);
2483 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2484 spin_unlock(&adap_rcu_lock);
2485
b8ff05a9
DM		 2486 mutex_lock(&uld_mutex);
2487 list_add_tail(&adap->list_node, &adapter_list);
2488 for (i = 0; i < CXGB4_ULD_MAX; i++)
2489 if (ulds[i].add)
2490 uld_attach(adap, i);
2491 mutex_unlock(&uld_mutex);
2492}
2493
2494static void detach_ulds(struct adapter *adap)
2495{
2496 unsigned int i;
2497
2498 mutex_lock(&uld_mutex);
2499 list_del(&adap->list_node);
2500 for (i = 0; i < CXGB4_ULD_MAX; i++)
2501 if (adap->uld_handle[i]) {
2502 ulds[i].state_change(adap->uld_handle[i],
2503 CXGB4_STATE_DETACH);
2504 adap->uld_handle[i] = NULL;
2505 }
2506 if (netevent_registered && list_empty(&adapter_list)) {
2507 unregister_netevent_notifier(&cxgb4_netevent_nb);
2508 netevent_registered = false;
2509 }
2510 mutex_unlock(&uld_mutex);
01bcca68
VP		 2511
2512 spin_lock(&adap_rcu_lock);
2513 list_del_rcu(&adap->rcu_node);
2514 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 2515}
2516
2517static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2518{
2519 unsigned int i;
2520
2521 mutex_lock(&uld_mutex);
2522 for (i = 0; i < CXGB4_ULD_MAX; i++)
2523 if (adap->uld_handle[i])
2524 ulds[i].state_change(adap->uld_handle[i], new_state);
2525 mutex_unlock(&uld_mutex);
2526}
2527
2528/**
2529 * cxgb4_register_uld - register an upper-layer driver
2530 * @type: the ULD type
2531 * @p: the ULD methods
2532 *
2533 * Registers an upper-layer driver with this driver and notifies the ULD
2534 * about any presently available devices that support its type. Returns
2535 * %-EBUSY if a ULD of the same type is already registered.
2536 */
2537int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2538{
2539 int ret = 0;
2540 struct adapter *adap;
2541
2542 if (type >= CXGB4_ULD_MAX)
2543 return -EINVAL;
2544 mutex_lock(&uld_mutex);
2545 if (ulds[type].add) {
2546 ret = -EBUSY;
2547 goto out;
2548 }
2549 ulds[type] = *p;
2550 list_for_each_entry(adap, &adapter_list, list_node)
2551 uld_attach(adap, type);
2552out: mutex_unlock(&uld_mutex);
2553 return ret;
2554}
2555EXPORT_SYMBOL(cxgb4_register_uld);
2556
2557/**
2558 * cxgb4_unregister_uld - unregister an upper-layer driver
2559 * @type: the ULD type
2560 *
2561 * Unregisters an existing upper-layer driver.
2562 */
2563int cxgb4_unregister_uld(enum cxgb4_uld type)
2564{
2565 struct adapter *adap;
2566
2567 if (type >= CXGB4_ULD_MAX)
2568 return -EINVAL;
2569 mutex_lock(&uld_mutex);
2570 list_for_each_entry(adap, &adapter_list, list_node)
2571 adap->uld_handle[type] = NULL;
2572 ulds[type].add = NULL;
2573 mutex_unlock(&uld_mutex);
2574 return 0;
2575}
2576EXPORT_SYMBOL(cxgb4_unregister_uld);
2577
1bb60376 2578#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2579static int cxgb4_inet6addr_handler(struct notifier_block *this,
2580 unsigned long event, void *data)
01bcca68 2581{
b5a02f50
AB		 2582 struct inet6_ifaddr *ifa = data;
2583 struct net_device *event_dev = ifa->idev->dev;
2584 const struct device *parent = NULL;
2585#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2586 struct adapter *adap;
b5a02f50
AB		 2587#endif
2588 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2589 event_dev = vlan_dev_real_dev(event_dev);
2590#if IS_ENABLED(CONFIG_BONDING)
2591 if (event_dev->flags & IFF_MASTER) {
2592 list_for_each_entry(adap, &adapter_list, list_node) {
2593 switch (event) {
2594 case NETDEV_UP:
2595 cxgb4_clip_get(adap->port[0],
2596 (const u32 *)ifa, 1);
2597 break;
2598 case NETDEV_DOWN:
2599 cxgb4_clip_release(adap->port[0],
2600 (const u32 *)ifa, 1);
2601 break;
2602 default:
2603 break;
2604 }
2605 }
2606 return NOTIFY_OK;
2607 }
2608#endif
01bcca68 2609
b5a02f50
AB		 2610 if (event_dev)
2611 parent = event_dev->dev.parent;
01bcca68 2612
b5a02f50 2613 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2614 switch (event) {
2615 case NETDEV_UP:
b5a02f50 2616 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2617 break;
2618 case NETDEV_DOWN:
b5a02f50 2619 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2620 break;
2621 default:
2622 break;
2623 }
2624 }
b5a02f50 2625 return NOTIFY_OK;
01bcca68
VP		 2626}
2627
b5a02f50 2628static bool inet6addr_registered;
01bcca68
VP		 2629static struct notifier_block cxgb4_inet6addr_notifier = {
2630 .notifier_call = cxgb4_inet6addr_handler
2631};
2632
01bcca68
VP		 2633static void update_clip(const struct adapter *adap)
2634{
2635 int i;
2636 struct net_device *dev;
2637 int ret;
2638
2639 rcu_read_lock();
2640
2641 for (i = 0; i < MAX_NPORTS; i++) {
2642 dev = adap->port[i];
2643 ret = 0;
2644
2645 if (dev)
b5a02f50 2646 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2647
2648 if (ret < 0)
2649 break;
2650 }
2651 rcu_read_unlock();
2652}
1bb60376 2653#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2654
b8ff05a9
DM		 2655/**
2656 * cxgb_up - enable the adapter
2657 * @adap: adapter being enabled
2658 *
2659 * Called when the first port is enabled, this function performs the
2660 * actions necessary to make an adapter operational, such as completing
2661 * the initialization of HW modules, and enabling interrupts.
2662 *
2663 * Must be called with the rtnl lock held.
2664 */
2665static int cxgb_up(struct adapter *adap)
2666{
aaefae9b 2667 int err;
b8ff05a9 2668
aaefae9b
DM		 2669 err = setup_sge_queues(adap);
2670 if (err)
2671 goto out;
2672 err = setup_rss(adap);
2673 if (err)
2674 goto freeq;
b8ff05a9
DM		 2675
2676 if (adap->flags & USING_MSIX) {
aaefae9b 2677 name_msix_vecs(adap);
b8ff05a9
DM		 2678 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2679 adap->msix_info[0].desc, adap);
2680 if (err)
2681 goto irq_err;
2682
2683 err = request_msix_queue_irqs(adap);
2684 if (err) {
2685 free_irq(adap->msix_info[0].vec, adap);
2686 goto irq_err;
2687 }
2688 } else {
2689 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2690 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2691 adap->port[0]->name, adap);
b8ff05a9
DM		 2692 if (err)
2693 goto irq_err;
2694 }
2695 enable_rx(adap);
2696 t4_sge_start(adap);
2697 t4_intr_enable(adap);
aaefae9b 2698 adap->flags |= FULL_INIT_DONE;
b8ff05a9 2699 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2700#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2701 update_clip(adap);
1bb60376 2702#endif
b8ff05a9
DM		 2703 out:
2704 return err;
2705 irq_err:
2706 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2707 freeq:
2708 t4_free_sge_resources(adap);
b8ff05a9
DM		 2709 goto out;
2710}
2711
2712static void cxgb_down(struct adapter *adapter)
2713{
b8ff05a9 2714 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2715 cancel_work_sync(&adapter->db_full_task);
2716 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2717 adapter->tid_release_task_busy = false;
204dc3c0 2718 adapter->tid_release_head = NULL;
b8ff05a9 2719
aaefae9b
DM		 2720 t4_sge_stop(adapter);
2721 t4_free_sge_resources(adapter);
2722 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2723}
2724
2725/*
2726 * net_device operations
2727 */
2728static int cxgb_open(struct net_device *dev)
2729{
2730 int err;
2731 struct port_info *pi = netdev_priv(dev);
2732 struct adapter *adapter = pi->adapter;
2733
6a3c869a
DM		 2734 netif_carrier_off(dev);
2735
aaefae9b
DM		 2736 if (!(adapter->flags & FULL_INIT_DONE)) {
2737 err = cxgb_up(adapter);
2738 if (err < 0)
2739 return err;
2740 }
b8ff05a9 2741
f68707b8
DM		 2742 err = link_start(dev);
2743 if (!err)
2744 netif_tx_start_all_queues(dev);
2745 return err;
b8ff05a9
DM		 2746}
2747
2748static int cxgb_close(struct net_device *dev)
2749{
b8ff05a9
DM		 2750 struct port_info *pi = netdev_priv(dev);
2751 struct adapter *adapter = pi->adapter;
2752
2753 netif_tx_stop_all_queues(dev);
2754 netif_carrier_off(dev);
060e0c75 2755 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
b8ff05a9
DM		 2756}
2757
f2b7e78d
VP		 2758/* Return an error number if the indicated filter isn't writable ...
2759 */
2760static int writable_filter(struct filter_entry *f)
2761{
2762 if (f->locked)
2763 return -EPERM;
2764 if (f->pending)
2765 return -EBUSY;
2766
2767 return 0;
2768}
2769
2770/* Delete the filter at the specified index (if valid). The checks for all
2771 * the common problems with doing this like the filter being locked, currently
2772 * pending in another operation, etc.
2773 */
2774static int delete_filter(struct adapter *adapter, unsigned int fidx)
2775{
2776 struct filter_entry *f;
2777 int ret;
2778
dca4faeb 2779 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 2780 return -EINVAL;
2781
2782 f = &adapter->tids.ftid_tab[fidx];
2783 ret = writable_filter(f);
2784 if (ret)
2785 return ret;
2786 if (f->valid)
2787 return del_filter_wr(adapter, fidx);
2788
2789 return 0;
2790}
2791
dca4faeb 2792int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2793 __be32 sip, __be16 sport, __be16 vlan,
2794 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2795{
2796 int ret;
2797 struct filter_entry *f;
2798 struct adapter *adap;
2799 int i;
2800 u8 *val;
2801
2802 adap = netdev2adap(dev);
2803
1cab775c 2804 /* Adjust stid to correct filter index */
470c60c4 2805 stid -= adap->tids.sftid_base;
1cab775c
VP		 2806 stid += adap->tids.nftids;
2807
dca4faeb
VP		 2808 /* Check to make sure the filter requested is writable ...
2809 */
2810 f = &adap->tids.ftid_tab[stid];
2811 ret = writable_filter(f);
2812 if (ret)
2813 return ret;
2814
2815 /* Clear out any old resources being used by the filter before
2816 * we start constructing the new filter.
2817 */
2818 if (f->valid)
2819 clear_filter(adap, f);
2820
2821 /* Clear out filter specifications */
2822 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2823 f->fs.val.lport = cpu_to_be16(sport);
2824 f->fs.mask.lport = ~0;
2825 val = (u8 *)&sip;
793dad94 2826 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2827 for (i = 0; i < 4; i++) {
2828 f->fs.val.lip[i] = val[i];
2829 f->fs.mask.lip[i] = ~0;
2830 }
0d804338 2831 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2832 f->fs.val.iport = port;
2833 f->fs.mask.iport = mask;
2834 }
2835 }
dca4faeb 2836
0d804338 2837 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2838 f->fs.val.proto = IPPROTO_TCP;
2839 f->fs.mask.proto = ~0;
2840 }
2841
dca4faeb
VP		 2842 f->fs.dirsteer = 1;
2843 f->fs.iq = queue;
2844 /* Mark filter as locked */
2845 f->locked = 1;
2846 f->fs.rpttid = 1;
2847
2848 ret = set_filter_wr(adap, stid);
2849 if (ret) {
2850 clear_filter(adap, f);
2851 return ret;
2852 }
2853
2854 return 0;
2855}
2856EXPORT_SYMBOL(cxgb4_create_server_filter);
2857
2858int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2859 unsigned int queue, bool ipv6)
2860{
2861 int ret;
2862 struct filter_entry *f;
2863 struct adapter *adap;
2864
2865 adap = netdev2adap(dev);
1cab775c
VP		 2866
2867 /* Adjust stid to correct filter index */
470c60c4 2868 stid -= adap->tids.sftid_base;
1cab775c
VP		 2869 stid += adap->tids.nftids;
2870
dca4faeb
VP		 2871 f = &adap->tids.ftid_tab[stid];
2872 /* Unlock the filter */
2873 f->locked = 0;
2874
2875 ret = delete_filter(adap, stid);
2876 if (ret)
2877 return ret;
2878
2879 return 0;
2880}
2881EXPORT_SYMBOL(cxgb4_remove_server_filter);
2882
f5152c90
DM		 2883static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2884 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2885{
2886 struct port_stats stats;
2887 struct port_info *p = netdev_priv(dev);
2888 struct adapter *adapter = p->adapter;
b8ff05a9 2889
9fe6cb58
GS		 2890 /* Block retrieving statistics during EEH error
2891 * recovery. Otherwise, the recovery might fail
2892 * and the PCI device will be removed permanently
2893 */
b8ff05a9 2894 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2895 if (!netif_device_present(dev)) {
2896 spin_unlock(&adapter->stats_lock);
2897 return ns;
2898 }
b8ff05a9
DM		 2899 t4_get_port_stats(adapter, p->tx_chan, &stats);
2900 spin_unlock(&adapter->stats_lock);
2901
2902 ns->tx_bytes = stats.tx_octets;
2903 ns->tx_packets = stats.tx_frames;
2904 ns->rx_bytes = stats.rx_octets;
2905 ns->rx_packets = stats.rx_frames;
2906 ns->multicast = stats.rx_mcast_frames;
2907
2908 /* detailed rx_errors */
2909 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2910 stats.rx_runt;
2911 ns->rx_over_errors = 0;
2912 ns->rx_crc_errors = stats.rx_fcs_err;
2913 ns->rx_frame_errors = stats.rx_symbol_err;
2914 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2915 stats.rx_ovflow2 + stats.rx_ovflow3 +
2916 stats.rx_trunc0 + stats.rx_trunc1 +
2917 stats.rx_trunc2 + stats.rx_trunc3;
2918 ns->rx_missed_errors = 0;
2919
2920 /* detailed tx_errors */
2921 ns->tx_aborted_errors = 0;
2922 ns->tx_carrier_errors = 0;
2923 ns->tx_fifo_errors = 0;
2924 ns->tx_heartbeat_errors = 0;
2925 ns->tx_window_errors = 0;
2926
2927 ns->tx_errors = stats.tx_error_frames;
2928 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2929 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2930 return ns;
2931}
2932
2933static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2934{
060e0c75 2935 unsigned int mbox;
b8ff05a9
DM		 2936 int ret = 0, prtad, devad;
2937 struct port_info *pi = netdev_priv(dev);
2938 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2939
2940 switch (cmd) {
2941 case SIOCGMIIPHY:
2942 if (pi->mdio_addr < 0)
2943 return -EOPNOTSUPP;
2944 data->phy_id = pi->mdio_addr;
2945 break;
2946 case SIOCGMIIREG:
2947 case SIOCSMIIREG:
2948 if (mdio_phy_id_is_c45(data->phy_id)) {
2949 prtad = mdio_phy_id_prtad(data->phy_id);
2950 devad = mdio_phy_id_devad(data->phy_id);
2951 } else if (data->phy_id < 32) {
2952 prtad = data->phy_id;
2953 devad = 0;
2954 data->reg_num &= 0x1f;
2955 } else
2956 return -EINVAL;
2957
060e0c75 2958 mbox = pi->adapter->fn;
b8ff05a9 2959 if (cmd == SIOCGMIIREG)
060e0c75 2960 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2961 data->reg_num, &data->val_out);
2962 else
060e0c75 2963 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2964 data->reg_num, data->val_in);
2965 break;
2966 default:
2967 return -EOPNOTSUPP;
2968 }
2969 return ret;
2970}
2971
2972static void cxgb_set_rxmode(struct net_device *dev)
2973{
2974 /* unfortunately we can't return errors to the stack */
2975 set_rxmode(dev, -1, false);
2976}
2977
2978static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2979{
2980 int ret;
2981 struct port_info *pi = netdev_priv(dev);
2982
2983 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2984 return -EINVAL;
060e0c75
DM		 2985 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
2986 -1, -1, -1, true);
b8ff05a9
DM		 2987 if (!ret)
2988 dev->mtu = new_mtu;
2989 return ret;
2990}
2991
2992static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2993{
2994 int ret;
2995 struct sockaddr *addr = p;
2996 struct port_info *pi = netdev_priv(dev);
2997
2998 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2999 return -EADDRNOTAVAIL;
b8ff05a9 3000
060e0c75
DM		 3001 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
3002 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 3003 if (ret < 0)
3004 return ret;
3005
3006 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3007 pi->xact_addr_filt = ret;
3008 return 0;
3009}
3010
b8ff05a9
DM		 3011#ifdef CONFIG_NET_POLL_CONTROLLER
3012static void cxgb_netpoll(struct net_device *dev)
3013{
3014 struct port_info *pi = netdev_priv(dev);
3015 struct adapter *adap = pi->adapter;
3016
3017 if (adap->flags & USING_MSIX) {
3018 int i;
3019 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3020
3021 for (i = pi->nqsets; i; i--, rx++)
3022 t4_sge_intr_msix(0, &rx->rspq);
3023 } else
3024 t4_intr_handler(adap)(0, adap);
3025}
3026#endif
3027
3028static const struct net_device_ops cxgb4_netdev_ops = {
3029 .ndo_open = cxgb_open,
3030 .ndo_stop = cxgb_close,
3031 .ndo_start_xmit = t4_eth_xmit,
688848b1 3032 .ndo_select_queue = cxgb_select_queue,
9be793bf 3033 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3034 .ndo_set_rx_mode = cxgb_set_rxmode,
3035 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3036 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3037 .ndo_validate_addr = eth_validate_addr,
3038 .ndo_do_ioctl = cxgb_ioctl,
3039 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3040#ifdef CONFIG_NET_POLL_CONTROLLER
3041 .ndo_poll_controller = cxgb_netpoll,
3042#endif
84a200b3
VP		 3043#ifdef CONFIG_CHELSIO_T4_FCOE
3044 .ndo_fcoe_enable = cxgb_fcoe_enable,
3045 .ndo_fcoe_disable = cxgb_fcoe_disable,
3046#endif /* CONFIG_CHELSIO_T4_FCOE */
3a336cb1
HS		 3047#ifdef CONFIG_NET_RX_BUSY_POLL
3048 .ndo_busy_poll = cxgb_busy_poll,
3049#endif
3050
b8ff05a9
DM		 3051};
3052
3053void t4_fatal_err(struct adapter *adap)
3054{
f612b815 3055 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
b8ff05a9
DM		 3056 t4_intr_disable(adap);
3057 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3058}
3059
0abfd152
HS		 3060/* Return the specified PCI-E Configuration Space register from our Physical
3061 * Function. We try first via a Firmware LDST Command since we prefer to let
3062 * the firmware own all of these registers, but if that fails we go for it
3063 * directly ourselves.
3064 */
3065static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
3066{
3067 struct fw_ldst_cmd ldst_cmd;
3068 u32 val;
3069 int ret;
3070
3071 /* Construct and send the Firmware LDST Command to retrieve the
3072 * specified PCI-E Configuration Space register.
3073 */
3074 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
3075 ldst_cmd.op_to_addrspace =
e2ac9628
HS		 3076 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
3077 FW_CMD_REQUEST_F |
3078 FW_CMD_READ_F |
5167865a 3079 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
0abfd152 3080 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
5167865a 3081 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
0abfd152 3082 ldst_cmd.u.pcie.ctrl_to_fn =
5167865a 3083 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
0abfd152
HS		 3084 ldst_cmd.u.pcie.r = reg;
3085 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
3086 &ldst_cmd);
3087
3088 /* If the LDST Command suucceeded, exctract the returned register
3089 * value. Otherwise read it directly ourself.
3090 */
3091 if (ret == 0)
3092 val = ntohl(ldst_cmd.u.pcie.data[0]);
3093 else
3094 t4_hw_pci_read_cfg4(adap, reg, &val);
3095
3096 return val;
3097}
3098
b8ff05a9
DM		 3099static void setup_memwin(struct adapter *adap)
3100{
0abfd152 3101 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
b8ff05a9 3102
d14807dd 3103 if (is_t4(adap->params.chip)) {
0abfd152
HS		 3104 u32 bar0;
3105
3106 /* Truncation intentional: we only read the bottom 32-bits of
3107 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
3108 * mechanism to read BAR0 instead of using
3109 * pci_resource_start() because we could be operating from
3110 * within a Virtual Machine which is trapping our accesses to
3111 * our Configuration Space and we need to set up the PCI-E
3112 * Memory Window decoders with the actual addresses which will
3113 * be coming across the PCI-E link.
3114 */
3115 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
3116 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
3117 adap->t4_bar0 = bar0;
3118
19dd37ba
SR		 3119 mem_win0_base = bar0 + MEMWIN0_BASE;
3120 mem_win1_base = bar0 + MEMWIN1_BASE;
3121 mem_win2_base = bar0 + MEMWIN2_BASE;
0abfd152 3122 mem_win2_aperture = MEMWIN2_APERTURE;
19dd37ba
SR		 3123 } else {
3124 /* For T5, only relative offset inside the PCIe BAR is passed */
3125 mem_win0_base = MEMWIN0_BASE;
0abfd152 3126 mem_win1_base = MEMWIN1_BASE;
19dd37ba 3127 mem_win2_base = MEMWIN2_BASE_T5;
0abfd152 3128 mem_win2_aperture = MEMWIN2_APERTURE_T5;
19dd37ba 3129 }
f061de42
HS		 3130 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
3131 mem_win0_base | BIR_V(0) |
3132 WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
3133 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
3134 mem_win1_base | BIR_V(0) |
3135 WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
3136 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
3137 mem_win2_base | BIR_V(0) |
3138 WINDOW_V(ilog2(mem_win2_aperture) - 10));
3139 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
636f9d37
VP		 3140}
3141
3142static void setup_memwin_rdma(struct adapter *adap)
3143{
1ae970e0 3144 if (adap->vres.ocq.size) {
0abfd152
HS		 3145 u32 start;
3146 unsigned int sz_kb;
1ae970e0 3147
0abfd152
HS		 3148 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3149 start &= PCI_BASE_ADDRESS_MEM_MASK;
3150 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3151 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3152 t4_write_reg(adap,
f061de42
HS		 3153 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3154 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3155 t4_write_reg(adap,
f061de42 3156 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3157 adap->vres.ocq.start);
3158 t4_read_reg(adap,
f061de42 3159 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3160 }
b8ff05a9
DM		 3161}
3162
02b5fb8e
DM		 3163static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3164{
3165 u32 v;
3166 int ret;
3167
3168 /* get device capabilities */
3169 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3170 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3171 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3172 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
060e0c75 3173 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
02b5fb8e
DM		 3174 if (ret < 0)
3175 return ret;
3176
3177 /* select capabilities we'll be using */
3178 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3179 if (!vf_acls)
3180 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3181 else
3182 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3183 } else if (vf_acls) {
3184 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3185 return ret;
3186 }
e2ac9628
HS		 3187 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3188 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
060e0c75 3189 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
02b5fb8e
DM		 3190 if (ret < 0)
3191 return ret;
3192
060e0c75 3193 ret = t4_config_glbl_rss(adap, adap->fn,
02b5fb8e 3194 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3195 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3196 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3197 if (ret < 0)
3198 return ret;
3199
4b8e27a8
HS		 3200 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, adap->sge.egr_sz, 64,
3201 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3202 FW_CMD_CAP_PF);
02b5fb8e
DM		 3203 if (ret < 0)
3204 return ret;
3205
3206 t4_sge_init(adap);
3207
02b5fb8e 3208 /* tweak some settings */
837e4a42 3209 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3210 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3211 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3212 v = t4_read_reg(adap, TP_PIO_DATA_A);
3213 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3214
dca4faeb
VP		 3215 /* first 4 Tx modulation queues point to consecutive Tx channels */
3216 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3217 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3218 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3219
3220 /* associate each Tx modulation queue with consecutive Tx channels */
3221 v = 0x84218421;
837e4a42 3222 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3223 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3224 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3225 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3226 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3227 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3228
3229#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3230 if (is_offload(adap)) {
0d804338
HS		 3231 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3232 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3233 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3234 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3235 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3236 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3237 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3238 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3239 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3240 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3241 }
3242
060e0c75
DM		 3243 /* get basic stuff going */
3244 return t4_early_init(adap, adap->fn);
02b5fb8e
DM		 3245}
3246
b8ff05a9
DM		 3247/*
3248 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3249 */
3250#define MAX_ATIDS 8192U
3251
636f9d37
VP		 3252/*
3253 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3254 *
3255 * If the firmware we're dealing with has Configuration File support, then
3256 * we use that to perform all configuration
3257 */
3258
3259/*
3260 * Tweak configuration based on module parameters, etc. Most of these have
3261 * defaults assigned to them by Firmware Configuration Files (if we're using
3262 * them) but need to be explicitly set if we're using hard-coded
3263 * initialization. But even in the case of using Firmware Configuration
3264 * Files, we'd like to expose the ability to change these via module
3265 * parameters so these are essentially common tweaks/settings for
3266 * Configuration Files and hard-coded initialization ...
3267 */
3268static int adap_init0_tweaks(struct adapter *adapter)
3269{
3270 /*
3271 * Fix up various Host-Dependent Parameters like Page Size, Cache
3272 * Line Size, etc. The firmware default is for a 4KB Page Size and
3273 * 64B Cache Line Size ...
3274 */
3275 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3276
3277 /*
3278 * Process module parameters which affect early initialization.
3279 */
3280 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3281 dev_err(&adapter->pdev->dev,
3282 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3283 rx_dma_offset);
3284 rx_dma_offset = 2;
3285 }
f612b815
HS		 3286 t4_set_reg_field(adapter, SGE_CONTROL_A,
3287 PKTSHIFT_V(PKTSHIFT_M),
3288 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3289
3290 /*
3291 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3292 * adds the pseudo header itself.
3293 */
837e4a42
HS		 3294 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3295 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3296
3297 return 0;
3298}
3299
3300/*
3301 * Attempt to initialize the adapter via a Firmware Configuration File.
3302 */
3303static int adap_init0_config(struct adapter *adapter, int reset)
3304{
3305 struct fw_caps_config_cmd caps_cmd;
3306 const struct firmware *cf;
3307 unsigned long mtype = 0, maddr = 0;
3308 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3309 int ret;
3310 int config_issued = 0;
0a57a536 3311 char *fw_config_file, fw_config_file_path[256];
16e47624 3312 char *config_name = NULL;
636f9d37
VP		 3313
3314 /*
3315 * Reset device if necessary.
3316 */
3317 if (reset) {
3318 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3319 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3320 if (ret < 0)
3321 goto bye;
3322 }
3323
3324 /*
3325 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3326 * then use that. Otherwise, use the configuration file stored
3327 * in the adapter flash ...
3328 */
d14807dd 3329 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3330 case CHELSIO_T4:
16e47624 3331 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3332 break;
3333 case CHELSIO_T5:
3334 fw_config_file = FW5_CFNAME;
3335 break;
3336 default:
3337 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3338 adapter->pdev->device);
3339 ret = -EINVAL;
3340 goto bye;
3341 }
3342
3343 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3344 if (ret < 0) {
16e47624 3345 config_name = "On FLASH";
636f9d37
VP		 3346 mtype = FW_MEMTYPE_CF_FLASH;
3347 maddr = t4_flash_cfg_addr(adapter);
3348 } else {
3349 u32 params[7], val[7];
3350
16e47624
HS		 3351 sprintf(fw_config_file_path,
3352 "/lib/firmware/%s", fw_config_file);
3353 config_name = fw_config_file_path;
3354
636f9d37
VP		 3355 if (cf->size >= FLASH_CFG_MAX_SIZE)
3356 ret = -ENOMEM;
3357 else {
5167865a
HS		 3358 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3359 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37
VP		 3360 ret = t4_query_params(adapter, adapter->mbox,
3361 adapter->fn, 0, 1, params, val);
3362 if (ret == 0) {
3363 /*
fc5ab020 3364 * For t4_memory_rw() below addresses and
636f9d37
VP		 3365 * sizes have to be in terms of multiples of 4
3366 * bytes. So, if the Configuration File isn't
3367 * a multiple of 4 bytes in length we'll have
3368 * to write that out separately since we can't
3369 * guarantee that the bytes following the
3370 * residual byte in the buffer returned by
3371 * request_firmware() are zeroed out ...
3372 */
3373 size_t resid = cf->size & 0x3;
3374 size_t size = cf->size & ~0x3;
3375 __be32 *data = (__be32 *)cf->data;
3376
5167865a
HS		 3377 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3378 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3379
fc5ab020
HS		 3380 spin_lock(&adapter->win0_lock);
3381 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3382 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3383 if (ret == 0 && resid != 0) {
3384 union {
3385 __be32 word;
3386 char buf[4];
3387 } last;
3388 int i;
3389
3390 last.word = data[size >> 2];
3391 for (i = resid; i < 4; i++)
3392 last.buf[i] = 0;
fc5ab020
HS		 3393 ret = t4_memory_rw(adapter, 0, mtype,
3394 maddr + size,
3395 4, &last.word,
3396 T4_MEMORY_WRITE);
636f9d37 3397 }
fc5ab020 3398 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3399 }
3400 }
3401
3402 release_firmware(cf);
3403 if (ret)
3404 goto bye;
3405 }
3406
3407 /*
3408 * Issue a Capability Configuration command to the firmware to get it
3409 * to parse the Configuration File. We don't use t4_fw_config_file()
3410 * because we want the ability to modify various features after we've
3411 * processed the configuration file ...
3412 */
3413 memset(&caps_cmd, 0, sizeof(caps_cmd));
3414 caps_cmd.op_to_write =
e2ac9628
HS		 3415 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3416 FW_CMD_REQUEST_F |
3417 FW_CMD_READ_F);
ce91a923 3418 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3419 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3420 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3421 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3422 FW_LEN16(caps_cmd));
3423 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3424 &caps_cmd);
16e47624
HS		 3425
3426 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3427 * Configuration File in FLASH), our last gasp effort is to use the
3428 * Firmware Configuration File which is embedded in the firmware. A
3429 * very few early versions of the firmware didn't have one embedded
3430 * but we can ignore those.
3431 */
3432 if (ret == -ENOENT) {
3433 memset(&caps_cmd, 0, sizeof(caps_cmd));
3434 caps_cmd.op_to_write =
e2ac9628
HS		 3435 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3436 FW_CMD_REQUEST_F |
3437 FW_CMD_READ_F);
16e47624
HS		 3438 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3439 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3440 sizeof(caps_cmd), &caps_cmd);
3441 config_name = "Firmware Default";
3442 }
3443
3444 config_issued = 1;
636f9d37
VP		 3445 if (ret < 0)
3446 goto bye;
3447
3448 finiver = ntohl(caps_cmd.finiver);
3449 finicsum = ntohl(caps_cmd.finicsum);
3450 cfcsum = ntohl(caps_cmd.cfcsum);
3451 if (finicsum != cfcsum)
3452 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3453 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3454 finicsum, cfcsum);
3455
636f9d37
VP		 3456 /*
3457 * And now tell the firmware to use the configuration we just loaded.
3458 */
3459 caps_cmd.op_to_write =
e2ac9628
HS		 3460 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3461 FW_CMD_REQUEST_F |
3462 FW_CMD_WRITE_F);
ce91a923 3463 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3464 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3465 NULL);
3466 if (ret < 0)
3467 goto bye;
3468
3469 /*
3470 * Tweak configuration based on system architecture, module
3471 * parameters, etc.
3472 */
3473 ret = adap_init0_tweaks(adapter);
3474 if (ret < 0)
3475 goto bye;
3476
3477 /*
3478 * And finally tell the firmware to initialize itself using the
3479 * parameters from the Configuration File.
3480 */
3481 ret = t4_fw_initialize(adapter, adapter->mbox);
3482 if (ret < 0)
3483 goto bye;
3484
06640310
HS		 3485 /* Emit Firmware Configuration File information and return
3486 * successfully.
636f9d37 3487 */
636f9d37 3488 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 3489 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3490 config_name, finiver, cfcsum);
636f9d37
VP		 3491 return 0;
3492
3493 /*
3494 * Something bad happened. Return the error ... (If the "error"
3495 * is that there's no Configuration File on the adapter we don't
3496 * want to issue a warning since this is fairly common.)
3497 */
3498bye:
16e47624
HS		 3499 if (config_issued && ret != -ENOENT)
3500 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3501 config_name, -ret);
636f9d37
VP		 3502 return ret;
3503}
3504
16e47624
HS		 3505static struct fw_info fw_info_array[] = {
3506 {
3507 .chip = CHELSIO_T4,
3508 .fs_name = FW4_CFNAME,
3509 .fw_mod_name = FW4_FNAME,
3510 .fw_hdr = {
3511 .chip = FW_HDR_CHIP_T4,
3512 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3513 .intfver_nic = FW_INTFVER(T4, NIC),
3514 .intfver_vnic = FW_INTFVER(T4, VNIC),
3515 .intfver_ri = FW_INTFVER(T4, RI),
3516 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3517 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3518 },
3519 }, {
3520 .chip = CHELSIO_T5,
3521 .fs_name = FW5_CFNAME,
3522 .fw_mod_name = FW5_FNAME,
3523 .fw_hdr = {
3524 .chip = FW_HDR_CHIP_T5,
3525 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3526 .intfver_nic = FW_INTFVER(T5, NIC),
3527 .intfver_vnic = FW_INTFVER(T5, VNIC),
3528 .intfver_ri = FW_INTFVER(T5, RI),
3529 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3530 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3531 },
3532 }
3533};
3534
3535static struct fw_info *find_fw_info(int chip)
3536{
3537 int i;
3538
3539 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3540 if (fw_info_array[i].chip == chip)
3541 return &fw_info_array[i];
3542 }
3543 return NULL;
3544}
3545
b8ff05a9
DM		 3546/*
3547 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3548 */
3549static int adap_init0(struct adapter *adap)
3550{
3551 int ret;
3552 u32 v, port_vec;
3553 enum dev_state state;
3554 u32 params[7], val[7];
9a4da2cd 3555 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 3556 int reset = 1;
b8ff05a9 3557
ae469b68
HS		 3558 /* Grab Firmware Device Log parameters as early as possible so we have
3559 * access to it for debugging, etc.
3560 */
3561 ret = t4_init_devlog_params(adap);
3562 if (ret < 0)
3563 return ret;
3564
666224d4
HS		 3565 /* Contact FW, advertising Master capability */
3566 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
b8ff05a9
DM		 3567 if (ret < 0) {
3568 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3569 ret);
3570 return ret;
3571 }
636f9d37
VP		 3572 if (ret == adap->mbox)
3573 adap->flags |= MASTER_PF;
b8ff05a9 3574
636f9d37
VP		 3575 /*
3576 * If we're the Master PF Driver and the device is uninitialized,
3577 * then let's consider upgrading the firmware ... (We always want
3578 * to check the firmware version number in order to A. get it for
3579 * later reporting and B. to warn if the currently loaded firmware
3580 * is excessively mismatched relative to the driver.)
3581 */
16e47624
HS		 3582 t4_get_fw_version(adap, &adap->params.fw_vers);
3583 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 3584 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 3585 struct fw_info *fw_info;
3586 struct fw_hdr *card_fw;
3587 const struct firmware *fw;
3588 const u8 *fw_data = NULL;
3589 unsigned int fw_size = 0;
3590
3591 /* This is the firmware whose headers the driver was compiled
3592 * against
3593 */
3594 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3595 if (fw_info == NULL) {
3596 dev_err(adap->pdev_dev,
3597 "unable to get firmware info for chip %d.\n",
3598 CHELSIO_CHIP_VERSION(adap->params.chip));
3599 return -EINVAL;
636f9d37 3600 }
16e47624
HS		 3601
3602 /* allocate memory to read the header of the firmware on the
3603 * card
3604 */
3605 card_fw = t4_alloc_mem(sizeof(*card_fw));
3606
3607 /* Get FW from from /lib/firmware/ */
3608 ret = request_firmware(&fw, fw_info->fw_mod_name,
3609 adap->pdev_dev);
3610 if (ret < 0) {
3611 dev_err(adap->pdev_dev,
3612 "unable to load firmware image %s, error %d\n",
3613 fw_info->fw_mod_name, ret);
3614 } else {
3615 fw_data = fw->data;
3616 fw_size = fw->size;
3617 }
3618
3619 /* upgrade FW logic */
3620 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3621 state, &reset);
3622
3623 /* Cleaning up */
0b5b6bee 3624 release_firmware(fw);
16e47624
HS		 3625 t4_free_mem(card_fw);
3626
636f9d37 3627 if (ret < 0)
16e47624 3628 goto bye;
636f9d37 3629 }
b8ff05a9 3630
636f9d37
VP		 3631 /*
3632 * Grab VPD parameters. This should be done after we establish a
3633 * connection to the firmware since some of the VPD parameters
3634 * (notably the Core Clock frequency) are retrieved via requests to
3635 * the firmware. On the other hand, we need these fairly early on
3636 * so we do this right after getting ahold of the firmware.
3637 */
3638 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 3639 if (ret < 0)
3640 goto bye;
a0881cab 3641
636f9d37 3642 /*
13ee15d3
VP		 3643 * Find out what ports are available to us. Note that we need to do
3644 * this before calling adap_init0_no_config() since it needs nports
3645 * and portvec ...
636f9d37
VP		 3646 */
3647 v =
5167865a
HS		 3648 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3649 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
636f9d37 3650 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
a0881cab
DM		 3651 if (ret < 0)
3652 goto bye;
3653
636f9d37
VP		 3654 adap->params.nports = hweight32(port_vec);
3655 adap->params.portvec = port_vec;
3656
06640310
HS		 3657 /* If the firmware is initialized already, emit a simply note to that
3658 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 3659 */
3660 if (state == DEV_STATE_INIT) {
3661 dev_info(adap->pdev_dev, "Coming up as %s: "\
3662 "Adapter already initialized\n",
3663 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 3664 } else {
3665 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3666 "Initializing adapter\n");
06640310
HS		 3667
3668 /* Find out whether we're dealing with a version of the
3669 * firmware which has configuration file support.
636f9d37 3670 */
06640310
HS		 3671 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3672 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3673 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
3674 params, val);
13ee15d3 3675
06640310
HS		 3676 /* If the firmware doesn't support Configuration Files,
3677 * return an error.
3678 */
3679 if (ret < 0) {
3680 dev_err(adap->pdev_dev, "firmware doesn't support "
3681 "Firmware Configuration Files\n");
3682 goto bye;
3683 }
3684
3685 /* The firmware provides us with a memory buffer where we can
3686 * load a Configuration File from the host if we want to
3687 * override the Configuration File in flash.
3688 */
3689 ret = adap_init0_config(adap, reset);
3690 if (ret == -ENOENT) {
3691 dev_err(adap->pdev_dev, "no Configuration File "
3692 "present on adapter.\n");
3693 goto bye;
636f9d37
VP		 3694 }
3695 if (ret < 0) {
06640310
HS		 3696 dev_err(adap->pdev_dev, "could not initialize "
3697 "adapter, error %d\n", -ret);
636f9d37
VP		 3698 goto bye;
3699 }
3700 }
3701
06640310
HS		 3702 /* Give the SGE code a chance to pull in anything that it needs ...
3703 * Note that this must be called after we retrieve our VPD parameters
3704 * in order to know how to convert core ticks to seconds, etc.
636f9d37 3705 */
06640310
HS		 3706 ret = t4_sge_init(adap);
3707 if (ret < 0)
3708 goto bye;
636f9d37 3709
9a4da2cd
VP		 3710 if (is_bypass_device(adap->pdev->device))
3711 adap->params.bypass = 1;
3712
636f9d37
VP		 3713 /*
3714 * Grab some of our basic fundamental operating parameters.
3715 */
3716#define FW_PARAM_DEV(param) \
5167865a
HS		 3717 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3718 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 3719
b8ff05a9 3720#define FW_PARAM_PFVF(param) \
5167865a
HS		 3721 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3722 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3723 FW_PARAMS_PARAM_Y_V(0) | \
3724 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 3725
636f9d37 3726 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 3727 params[1] = FW_PARAM_PFVF(L2T_START);
3728 params[2] = FW_PARAM_PFVF(L2T_END);
3729 params[3] = FW_PARAM_PFVF(FILTER_START);
3730 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 3731 params[5] = FW_PARAM_PFVF(IQFLINT_START);
636f9d37 3732 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
b8ff05a9
DM		 3733 if (ret < 0)
3734 goto bye;
636f9d37
VP		 3735 adap->sge.egr_start = val[0];
3736 adap->l2t_start = val[1];
3737 adap->l2t_end = val[2];
b8ff05a9
DM		 3738 adap->tids.ftid_base = val[3];
3739 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 3740 adap->sge.ingr_start = val[5];
b8ff05a9 3741
4b8e27a8
HS		 3742 /* qids (ingress/egress) returned from firmware can be anywhere
3743 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3744 * Hence driver needs to allocate memory for this range to
3745 * store the queue info. Get the highest IQFLINT/EQ index returned
3746 * in FW_EQ_*_CMD.alloc command.
3747 */
3748 params[0] = FW_PARAM_PFVF(EQ_END);
3749 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3750 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3751 if (ret < 0)
3752 goto bye;
3753 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3754 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3755
3756 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3757 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3758 if (!adap->sge.egr_map) {
3759 ret = -ENOMEM;
3760 goto bye;
3761 }
3762
3763 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3764 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3765 if (!adap->sge.ingr_map) {
3766 ret = -ENOMEM;
3767 goto bye;
3768 }
3769
3770 /* Allocate the memory for the vaious egress queue bitmaps
3771 * ie starving_fl and txq_maperr.
3772 */
3773 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3774 sizeof(long), GFP_KERNEL);
3775 if (!adap->sge.starving_fl) {
3776 ret = -ENOMEM;
3777 goto bye;
3778 }
3779
3780 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3781 sizeof(long), GFP_KERNEL);
3782 if (!adap->sge.txq_maperr) {
3783 ret = -ENOMEM;
3784 goto bye;
3785 }
3786
b5a02f50
AB		 3787 params[0] = FW_PARAM_PFVF(CLIP_START);
3788 params[1] = FW_PARAM_PFVF(CLIP_END);
3789 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3790 if (ret < 0)
3791 goto bye;
3792 adap->clipt_start = val[0];
3793 adap->clipt_end = val[1];
3794
636f9d37
VP		 3795 /* query params related to active filter region */
3796 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3797 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3798 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3799 /* If Active filter size is set we enable establishing
3800 * offload connection through firmware work request
3801 */
3802 if ((val[0] != val[1]) && (ret >= 0)) {
3803 adap->flags |= FW_OFLD_CONN;
3804 adap->tids.aftid_base = val[0];
3805 adap->tids.aftid_end = val[1];
3806 }
3807
b407a4a9
VP		 3808 /* If we're running on newer firmware, let it know that we're
3809 * prepared to deal with encapsulated CPL messages. Older
3810 * firmware won't understand this and we'll just get
3811 * unencapsulated messages ...
3812 */
3813 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3814 val[0] = 1;
3815 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
3816
1ac0f095
KS		 3817 /*
3818 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3819 * capability. Earlier versions of the firmware didn't have the
3820 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3821 * permission to use ULPTX MEMWRITE DSGL.
3822 */
3823 if (is_t4(adap->params.chip)) {
3824 adap->params.ulptx_memwrite_dsgl = false;
3825 } else {
3826 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3827 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
3828 1, params, val);
3829 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3830 }
3831
636f9d37
VP		 3832 /*
3833 * Get device capabilities so we can determine what resources we need
3834 * to manage.
3835 */
3836 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 3837 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3838 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3839 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3840 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3841 &caps_cmd);
3842 if (ret < 0)
3843 goto bye;
3844
13ee15d3 3845 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 3846 /* query offload-related parameters */
3847 params[0] = FW_PARAM_DEV(NTID);
3848 params[1] = FW_PARAM_PFVF(SERVER_START);
3849 params[2] = FW_PARAM_PFVF(SERVER_END);
3850 params[3] = FW_PARAM_PFVF(TDDP_START);
3851 params[4] = FW_PARAM_PFVF(TDDP_END);
3852 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
636f9d37
VP		 3853 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3854 params, val);
b8ff05a9
DM		 3855 if (ret < 0)
3856 goto bye;
3857 adap->tids.ntids = val[0];
3858 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3859 adap->tids.stid_base = val[1];
3860 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 3861 /*
dbedd44e 3862 * Setup server filter region. Divide the available filter
636f9d37
VP		 3863 * region into two parts. Regular filters get 1/3rd and server
3864 * filters get 2/3rd part. This is only enabled if workarond
3865 * path is enabled.
3866 * 1. For regular filters.
3867 * 2. Server filter: This are special filters which are used
3868 * to redirect SYN packets to offload queue.
3869 */
3870 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3871 adap->tids.sftid_base = adap->tids.ftid_base +
3872 DIV_ROUND_UP(adap->tids.nftids, 3);
3873 adap->tids.nsftids = adap->tids.nftids -
3874 DIV_ROUND_UP(adap->tids.nftids, 3);
3875 adap->tids.nftids = adap->tids.sftid_base -
3876 adap->tids.ftid_base;
3877 }
b8ff05a9
DM		 3878 adap->vres.ddp.start = val[3];
3879 adap->vres.ddp.size = val[4] - val[3] + 1;
3880 adap->params.ofldq_wr_cred = val[5];
636f9d37 3881
b8ff05a9
DM		 3882 adap->params.offload = 1;
3883 }
636f9d37 3884 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 3885 params[0] = FW_PARAM_PFVF(STAG_START);
3886 params[1] = FW_PARAM_PFVF(STAG_END);
3887 params[2] = FW_PARAM_PFVF(RQ_START);
3888 params[3] = FW_PARAM_PFVF(RQ_END);
3889 params[4] = FW_PARAM_PFVF(PBL_START);
3890 params[5] = FW_PARAM_PFVF(PBL_END);
636f9d37
VP		 3891 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3892 params, val);
b8ff05a9
DM		 3893 if (ret < 0)
3894 goto bye;
3895 adap->vres.stag.start = val[0];
3896 adap->vres.stag.size = val[1] - val[0] + 1;
3897 adap->vres.rq.start = val[2];
3898 adap->vres.rq.size = val[3] - val[2] + 1;
3899 adap->vres.pbl.start = val[4];
3900 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 3901
3902 params[0] = FW_PARAM_PFVF(SQRQ_START);
3903 params[1] = FW_PARAM_PFVF(SQRQ_END);
3904 params[2] = FW_PARAM_PFVF(CQ_START);
3905 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 3906 params[4] = FW_PARAM_PFVF(OCQ_START);
3907 params[5] = FW_PARAM_PFVF(OCQ_END);
5c937dd3
HS		 3908 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
3909 val);
a0881cab
DM		 3910 if (ret < 0)
3911 goto bye;
3912 adap->vres.qp.start = val[0];
3913 adap->vres.qp.size = val[1] - val[0] + 1;
3914 adap->vres.cq.start = val[2];
3915 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 3916 adap->vres.ocq.start = val[4];
3917 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 3918
3919 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3920 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5c937dd3
HS		 3921 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
3922 val);
4c2c5763
HS		 3923 if (ret < 0) {
3924 adap->params.max_ordird_qp = 8;
3925 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3926 ret = 0;
3927 } else {
3928 adap->params.max_ordird_qp = val[0];
3929 adap->params.max_ird_adapter = val[1];
3930 }
3931 dev_info(adap->pdev_dev,
3932 "max_ordird_qp %d max_ird_adapter %d\n",
3933 adap->params.max_ordird_qp,
3934 adap->params.max_ird_adapter);
b8ff05a9 3935 }
636f9d37 3936 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 3937 params[0] = FW_PARAM_PFVF(ISCSI_START);
3938 params[1] = FW_PARAM_PFVF(ISCSI_END);
636f9d37
VP		 3939 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
3940 params, val);
b8ff05a9
DM		 3941 if (ret < 0)
3942 goto bye;
3943 adap->vres.iscsi.start = val[0];
3944 adap->vres.iscsi.size = val[1] - val[0] + 1;
3945 }
3946#undef FW_PARAM_PFVF
3947#undef FW_PARAM_DEV
3948
92e7ae71
HS		 3949 /* The MTU/MSS Table is initialized by now, so load their values. If
3950 * we're initializing the adapter, then we'll make any modifications
3951 * we want to the MTU/MSS Table and also initialize the congestion
3952 * parameters.
636f9d37 3953 */
b8ff05a9 3954 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 3955 if (state != DEV_STATE_INIT) {
3956 int i;
3957
3958 /* The default MTU Table contains values 1492 and 1500.
3959 * However, for TCP, it's better to have two values which are
3960 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
3961 * This allows us to have a TCP Data Payload which is a
3962 * multiple of 8 regardless of what combination of TCP Options
3963 * are in use (always a multiple of 4 bytes) which is
3964 * important for performance reasons. For instance, if no
3965 * options are in use, then we have a 20-byte IP header and a
3966 * 20-byte TCP header. In this case, a 1500-byte MSS would
3967 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
3968 * which is not a multiple of 8. So using an MSS of 1488 in
3969 * this case results in a TCP Data Payload of 1448 bytes which
3970 * is a multiple of 8. On the other hand, if 12-byte TCP Time
3971 * Stamps have been negotiated, then an MTU of 1500 bytes
3972 * results in a TCP Data Payload of 1448 bytes which, as
3973 * above, is a multiple of 8 bytes ...
3974 */
3975 for (i = 0; i < NMTUS; i++)
3976 if (adap->params.mtus[i] == 1492) {
3977 adap->params.mtus[i] = 1488;
3978 break;
3979 }
7ee9ff94 3980
92e7ae71
HS		 3981 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3982 adap->params.b_wnd);
3983 }
df64e4d3 3984 t4_init_sge_params(adap);
dcf7b6f5 3985 t4_init_tp_params(adap);
636f9d37 3986 adap->flags |= FW_OK;
b8ff05a9
DM		 3987 return 0;
3988
3989 /*
636f9d37
VP		 3990 * Something bad happened. If a command timed out or failed with EIO
3991 * FW does not operate within its spec or something catastrophic
3992 * happened to HW/FW, stop issuing commands.
b8ff05a9 3993 */
636f9d37 3994bye:
4b8e27a8
HS		 3995 kfree(adap->sge.egr_map);
3996 kfree(adap->sge.ingr_map);
3997 kfree(adap->sge.starving_fl);
3998 kfree(adap->sge.txq_maperr);
636f9d37
VP		 3999 if (ret != -ETIMEDOUT && ret != -EIO)
4000 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4001 return ret;
4002}
4003
204dc3c0
DM		 4004/* EEH callbacks */
4005
4006static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4007 pci_channel_state_t state)
4008{
4009 int i;
4010 struct adapter *adap = pci_get_drvdata(pdev);
4011
4012 if (!adap)
4013 goto out;
4014
4015 rtnl_lock();
4016 adap->flags &= ~FW_OK;
4017 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4018 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4019 for_each_port(adap, i) {
4020 struct net_device *dev = adap->port[i];
4021
4022 netif_device_detach(dev);
4023 netif_carrier_off(dev);
4024 }
9fe6cb58 4025 spin_unlock(&adap->stats_lock);
b37987e8 4026 disable_interrupts(adap);
204dc3c0
DM		 4027 if (adap->flags & FULL_INIT_DONE)
4028 cxgb_down(adap);
4029 rtnl_unlock();
144be3d9
GS		 4030 if ((adap->flags & DEV_ENABLED)) {
4031 pci_disable_device(pdev);
4032 adap->flags &= ~DEV_ENABLED;
4033 }
204dc3c0
DM		 4034out: return state == pci_channel_io_perm_failure ?
4035 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4036}
4037
4038static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4039{
4040 int i, ret;
4041 struct fw_caps_config_cmd c;
4042 struct adapter *adap = pci_get_drvdata(pdev);
4043
4044 if (!adap) {
4045 pci_restore_state(pdev);
4046 pci_save_state(pdev);
4047 return PCI_ERS_RESULT_RECOVERED;
4048 }
4049
144be3d9
GS		 4050 if (!(adap->flags & DEV_ENABLED)) {
4051 if (pci_enable_device(pdev)) {
4052 dev_err(&pdev->dev, "Cannot reenable PCI "
4053 "device after reset\n");
4054 return PCI_ERS_RESULT_DISCONNECT;
4055 }
4056 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4057 }
4058
4059 pci_set_master(pdev);
4060 pci_restore_state(pdev);
4061 pci_save_state(pdev);
4062 pci_cleanup_aer_uncorrect_error_status(pdev);
4063
8203b509 4064 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4065 return PCI_ERS_RESULT_DISCONNECT;
777c2300 4066 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4067 return PCI_ERS_RESULT_DISCONNECT;
4068 adap->flags |= FW_OK;
4069 if (adap_init1(adap, &c))
4070 return PCI_ERS_RESULT_DISCONNECT;
4071
4072 for_each_port(adap, i) {
4073 struct port_info *p = adap2pinfo(adap, i);
4074
060e0c75
DM		 4075 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
4076 NULL, NULL);
204dc3c0
DM		 4077 if (ret < 0)
4078 return PCI_ERS_RESULT_DISCONNECT;
4079 p->viid = ret;
4080 p->xact_addr_filt = -1;
4081 }
4082
4083 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4084 adap->params.b_wnd);
1ae970e0 4085 setup_memwin(adap);
204dc3c0
DM		 4086 if (cxgb_up(adap))
4087 return PCI_ERS_RESULT_DISCONNECT;
4088 return PCI_ERS_RESULT_RECOVERED;
4089}
4090
4091static void eeh_resume(struct pci_dev *pdev)
4092{
4093 int i;
4094 struct adapter *adap = pci_get_drvdata(pdev);
4095
4096 if (!adap)
4097 return;
4098
4099 rtnl_lock();
4100 for_each_port(adap, i) {
4101 struct net_device *dev = adap->port[i];
4102
4103 if (netif_running(dev)) {
4104 link_start(dev);
4105 cxgb_set_rxmode(dev);
4106 }
4107 netif_device_attach(dev);
4108 }
4109 rtnl_unlock();
4110}
4111
3646f0e5 4112static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4113 .error_detected = eeh_err_detected,
4114 .slot_reset = eeh_slot_reset,
4115 .resume = eeh_resume,
4116};
4117
57d8b764 4118static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4119{
57d8b764
KS		 4120 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4121 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 4122}
4123
c887ad0e
HS		 4124static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4125 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 4126 unsigned int size, unsigned int iqe_size)
4127{
c887ad0e 4128 q->adap = adap;
812034f1 4129 cxgb4_set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 4130 q->iqe_len = iqe_size;
4131 q->size = size;
4132}
4133
4134/*
4135 * Perform default configuration of DMA queues depending on the number and type
4136 * of ports we found and the number of available CPUs. Most settings can be
4137 * modified by the admin prior to actual use.
4138 */
91744948 4139static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4140{
4141 struct sge *s = &adap->sge;
688848b1
AB		 4142 int i, n10g = 0, qidx = 0;
4143#ifndef CONFIG_CHELSIO_T4_DCB
4144 int q10g = 0;
4145#endif
cf38be6d 4146 int ciq_size;
b8ff05a9
DM		 4147
4148 for_each_port(adap, i)
57d8b764 4149 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 4150#ifdef CONFIG_CHELSIO_T4_DCB
4151 /* For Data Center Bridging support we need to be able to support up
4152 * to 8 Traffic Priorities; each of which will be assigned to its
4153 * own TX Queue in order to prevent Head-Of-Line Blocking.
4154 */
4155 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4156 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4157 MAX_ETH_QSETS, adap->params.nports * 8);
4158 BUG_ON(1);
4159 }
b8ff05a9 4160
688848b1
AB		 4161 for_each_port(adap, i) {
4162 struct port_info *pi = adap2pinfo(adap, i);
4163
4164 pi->first_qset = qidx;
4165 pi->nqsets = 8;
4166 qidx += pi->nqsets;
4167 }
4168#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4169 /*
4170 * We default to 1 queue per non-10G port and up to # of cores queues
4171 * per 10G port.
4172 */
4173 if (n10g)
4174 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4175 if (q10g > netif_get_num_default_rss_queues())
4176 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 4177
4178 for_each_port(adap, i) {
4179 struct port_info *pi = adap2pinfo(adap, i);
4180
4181 pi->first_qset = qidx;
57d8b764 4182 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4183 qidx += pi->nqsets;
4184 }
688848b1 4185#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4186
4187 s->ethqsets = qidx;
4188 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4189
4190 if (is_offload(adap)) {
4191 /*
4192 * For offload we use 1 queue/channel if all ports are up to 1G,
4193 * otherwise we divide all available queues amongst the channels
4194 * capped by the number of available cores.
4195 */
4196 if (n10g) {
4197 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4198 num_online_cpus());
4199 s->ofldqsets = roundup(i, adap->params.nports);
4200 } else
4201 s->ofldqsets = adap->params.nports;
4202 /* For RDMA one Rx queue per channel suffices */
4203 s->rdmaqs = adap->params.nports;
f36e58e5
HS		 4204 /* Try and allow at least 1 CIQ per cpu rounding down
4205 * to the number of ports, with a minimum of 1 per port.
4206 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4207 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4208 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4209 */
4210 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4211 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4212 adap->params.nports;
4213 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
b8ff05a9
DM		 4214 }
4215
4216 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4217 struct sge_eth_rxq *r = &s->ethrxq[i];
4218
c887ad0e 4219 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4220 r->fl.size = 72;
4221 }
4222
4223 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4224 s->ethtxq[i].q.size = 1024;
4225
4226 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4227 s->ctrlq[i].q.size = 512;
4228
4229 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4230 s->ofldtxq[i].q.size = 1024;
4231
4232 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4233 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4234
c887ad0e 4235 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 4236 r->rspq.uld = CXGB4_ULD_ISCSI;
4237 r->fl.size = 72;
4238 }
4239
4240 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4241 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4242
c887ad0e 4243 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 4244 r->rspq.uld = CXGB4_ULD_RDMA;
4245 r->fl.size = 72;
4246 }
4247
cf38be6d
HS		 4248 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4249 if (ciq_size > SGE_MAX_IQ_SIZE) {
4250 CH_WARN(adap, "CIQ size too small for available IQs\n");
4251 ciq_size = SGE_MAX_IQ_SIZE;
4252 }
4253
4254 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4255 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4256
c887ad0e 4257 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 4258 r->rspq.uld = CXGB4_ULD_RDMA;
4259 }
4260
c887ad0e
HS		 4261 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4262 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 4263}
4264
4265/*
4266 * Reduce the number of Ethernet queues across all ports to at most n.
4267 * n provides at least one queue per port.
4268 */
91744948 4269static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4270{
4271 int i;
4272 struct port_info *pi;
4273
4274 while (n < adap->sge.ethqsets)
4275 for_each_port(adap, i) {
4276 pi = adap2pinfo(adap, i);
4277 if (pi->nqsets > 1) {
4278 pi->nqsets--;
4279 adap->sge.ethqsets--;
4280 if (adap->sge.ethqsets <= n)
4281 break;
4282 }
4283 }
4284
4285 n = 0;
4286 for_each_port(adap, i) {
4287 pi = adap2pinfo(adap, i);
4288 pi->first_qset = n;
4289 n += pi->nqsets;
4290 }
4291}
4292
4293/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4294#define EXTRA_VECS 2
4295
91744948 4296static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 4297{
4298 int ofld_need = 0;
f36e58e5 4299 int i, want, need, allocated;
b8ff05a9
DM		 4300 struct sge *s = &adap->sge;
4301 unsigned int nchan = adap->params.nports;
f36e58e5
HS		 4302 struct msix_entry *entries;
4303
4304 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4305 GFP_KERNEL);
4306 if (!entries)
4307 return -ENOMEM;
b8ff05a9 4308
f36e58e5 4309 for (i = 0; i < MAX_INGQ + 1; ++i)
b8ff05a9
DM		 4310 entries[i].entry = i;
4311
4312 want = s->max_ethqsets + EXTRA_VECS;
4313 if (is_offload(adap)) {
cf38be6d 4314 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 4315 /* need nchan for each possible ULD */
cf38be6d 4316 ofld_need = 3 * nchan;
b8ff05a9 4317 }
688848b1
AB		 4318#ifdef CONFIG_CHELSIO_T4_DCB
4319 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4320 * each port.
4321 */
4322 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4323#else
b8ff05a9 4324 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 4325#endif
f36e58e5
HS		 4326 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4327 if (allocated < 0) {
4328 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4329 " not using MSI-X\n");
4330 kfree(entries);
4331 return allocated;
4332 }
b8ff05a9 4333
f36e58e5 4334 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 4335 * Every group gets its minimum requirement and NIC gets top
4336 * priority for leftovers.
4337 */
f36e58e5 4338 i = allocated - EXTRA_VECS - ofld_need;
c32ad224
AG		 4339 if (i < s->max_ethqsets) {
4340 s->max_ethqsets = i;
4341 if (i < s->ethqsets)
4342 reduce_ethqs(adap, i);
4343 }
4344 if (is_offload(adap)) {
f36e58e5
HS		 4345 if (allocated < want) {
4346 s->rdmaqs = nchan;
4347 s->rdmaciqs = nchan;
4348 }
4349
4350 /* leftovers go to OFLD */
4351 i = allocated - EXTRA_VECS - s->max_ethqsets -
4352 s->rdmaqs - s->rdmaciqs;
c32ad224
AG		 4353 s->ofldqsets = (i / nchan) * nchan; /* round down */
4354 }
f36e58e5 4355 for (i = 0; i < allocated; ++i)
c32ad224
AG		 4356 adap->msix_info[i].vec = entries[i].vector;
4357
f36e58e5 4358 kfree(entries);
c32ad224 4359 return 0;
b8ff05a9
DM		 4360}
4361
4362#undef EXTRA_VECS
4363
91744948 4364static int init_rss(struct adapter *adap)
671b0060 4365{
c035e183
HS		 4366 unsigned int i;
4367 int err;
4368
4369 err = t4_init_rss_mode(adap, adap->mbox);
4370 if (err)
4371 return err;
671b0060
DM		 4372
4373 for_each_port(adap, i) {
4374 struct port_info *pi = adap2pinfo(adap, i);
4375
4376 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4377 if (!pi->rss)
4378 return -ENOMEM;
671b0060
DM		 4379 }
4380 return 0;
4381}
4382
91744948 4383static void print_port_info(const struct net_device *dev)
b8ff05a9 4384{
b8ff05a9 4385 char buf[80];
118969ed 4386 char *bufp = buf;
f1a051b9 4387 const char *spd = "";
118969ed
DM		 4388 const struct port_info *pi = netdev_priv(dev);
4389 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 4390
4391 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4392 spd = " 2.5 GT/s";
4393 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4394 spd = " 5 GT/s";
d2e752db
RD		 4395 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4396 spd = " 8 GT/s";
b8ff05a9 4397
118969ed
DM		 4398 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4399 bufp += sprintf(bufp, "100/");
4400 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4401 bufp += sprintf(bufp, "1000/");
4402 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4403 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 4404 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4405 bufp += sprintf(bufp, "40G/");
118969ed
DM		 4406 if (bufp != buf)
4407 --bufp;
72aca4bf 4408 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM		 4409
4410 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 4411 adap->params.vpd.id,
d14807dd 4412 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM		 4413 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4414 (adap->flags & USING_MSIX) ? " MSI-X" :
4415 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 4416 netdev_info(dev, "S/N: %s, P/N: %s\n",
4417 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 4418}
4419
91744948 4420static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 4421{
e5c8ae5f 4422 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 4423}
4424
06546391
DM		 4425/*
4426 * Free the following resources:
4427 * - memory used for tables
4428 * - MSI/MSI-X
4429 * - net devices
4430 * - resources FW is holding for us
4431 */
4432static void free_some_resources(struct adapter *adapter)
4433{
4434 unsigned int i;
4435
4436 t4_free_mem(adapter->l2t);
4437 t4_free_mem(adapter->tids.tid_tab);
4b8e27a8
HS		 4438 kfree(adapter->sge.egr_map);
4439 kfree(adapter->sge.ingr_map);
4440 kfree(adapter->sge.starving_fl);
4441 kfree(adapter->sge.txq_maperr);
06546391
DM		 4442 disable_msi(adapter);
4443
4444 for_each_port(adapter, i)
671b0060
DM		 4445 if (adapter->port[i]) {
4446 kfree(adap2pinfo(adapter, i)->rss);
06546391 4447 free_netdev(adapter->port[i]);
671b0060 4448 }
06546391 4449 if (adapter->flags & FW_OK)
060e0c75 4450 t4_fw_bye(adapter, adapter->fn);
06546391
DM		 4451}
4452
2ed28baa 4453#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 4454#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 4455 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 4456#define SEGMENT_SIZE 128
b8ff05a9 4457
1dd06ae8 4458static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 4459{
22adfe0a 4460 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 4461 struct port_info *pi;
c8f44aff 4462 bool highdma = false;
b8ff05a9 4463 struct adapter *adapter = NULL;
d6ce2628 4464 void __iomem *regs;
b8ff05a9
DM		 4465
4466 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4467
4468 err = pci_request_regions(pdev, KBUILD_MODNAME);
4469 if (err) {
4470 /* Just info, some other driver may have claimed the device. */
4471 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4472 return err;
4473 }
4474
b8ff05a9
DM		 4475 err = pci_enable_device(pdev);
4476 if (err) {
4477 dev_err(&pdev->dev, "cannot enable PCI device\n");
4478 goto out_release_regions;
4479 }
4480
d6ce2628
HS		 4481 regs = pci_ioremap_bar(pdev, 0);
4482 if (!regs) {
4483 dev_err(&pdev->dev, "cannot map device registers\n");
4484 err = -ENOMEM;
4485 goto out_disable_device;
4486 }
4487
8203b509
HS		 4488 err = t4_wait_dev_ready(regs);
4489 if (err < 0)
4490 goto out_unmap_bar0;
4491
d6ce2628 4492 /* We control everything through one PF */
0d804338 4493 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
d6ce2628
HS		 4494 if (func != ent->driver_data) {
4495 iounmap(regs);
4496 pci_disable_device(pdev);
4497 pci_save_state(pdev); /* to restore SR-IOV later */
4498 goto sriov;
4499 }
4500
b8ff05a9 4501 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 4502 highdma = true;
b8ff05a9
DM		 4503 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4504 if (err) {
4505 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4506 "coherent allocations\n");
d6ce2628 4507 goto out_unmap_bar0;
b8ff05a9
DM		 4508 }
4509 } else {
4510 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4511 if (err) {
4512 dev_err(&pdev->dev, "no usable DMA configuration\n");
d6ce2628 4513 goto out_unmap_bar0;
b8ff05a9
DM		 4514 }
4515 }
4516
4517 pci_enable_pcie_error_reporting(pdev);
ef306b50 4518 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 4519 pci_set_master(pdev);
4520 pci_save_state(pdev);
4521
4522 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4523 if (!adapter) {
4524 err = -ENOMEM;
d6ce2628 4525 goto out_unmap_bar0;
b8ff05a9
DM		 4526 }
4527
29aaee65
AB		 4528 adapter->workq = create_singlethread_workqueue("cxgb4");
4529 if (!adapter->workq) {
4530 err = -ENOMEM;
4531 goto out_free_adapter;
4532 }
4533
144be3d9
GS		 4534 /* PCI device has been enabled */
4535 adapter->flags |= DEV_ENABLED;
4536
d6ce2628 4537 adapter->regs = regs;
b8ff05a9
DM		 4538 adapter->pdev = pdev;
4539 adapter->pdev_dev = &pdev->dev;
3069ee9b 4540 adapter->mbox = func;
060e0c75 4541 adapter->fn = func;
b8ff05a9
DM		 4542 adapter->msg_enable = dflt_msg_enable;
4543 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4544
4545 spin_lock_init(&adapter->stats_lock);
4546 spin_lock_init(&adapter->tid_release_lock);
e327c225 4547 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 4548
4549 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 4550 INIT_WORK(&adapter->db_full_task, process_db_full);
4551 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 4552
4553 err = t4_prep_adapter(adapter);
4554 if (err)
d6ce2628
HS		 4555 goto out_free_adapter;
4556
22adfe0a 4557
d14807dd 4558 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 4559 s_qpp = (QUEUESPERPAGEPF0_S +
4560 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4561 adapter->fn);
4562 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4563 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 4564 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4565
4566 /* Each segment size is 128B. Write coalescing is enabled only
4567 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4568 * queue is less no of segments that can be accommodated in
4569 * a page size.
4570 */
4571 if (qpp > num_seg) {
4572 dev_err(&pdev->dev,
4573 "Incorrect number of egress queues per page\n");
4574 err = -EINVAL;
d6ce2628 4575 goto out_free_adapter;
22adfe0a
SR		 4576 }
4577 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4578 pci_resource_len(pdev, 2));
4579 if (!adapter->bar2) {
4580 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4581 err = -ENOMEM;
d6ce2628 4582 goto out_free_adapter;
22adfe0a
SR		 4583 }
4584 }
4585
636f9d37 4586 setup_memwin(adapter);
b8ff05a9 4587 err = adap_init0(adapter);
636f9d37 4588 setup_memwin_rdma(adapter);
b8ff05a9
DM		 4589 if (err)
4590 goto out_unmap_bar;
4591
4592 for_each_port(adapter, i) {
4593 struct net_device *netdev;
4594
4595 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4596 MAX_ETH_QSETS);
4597 if (!netdev) {
4598 err = -ENOMEM;
4599 goto out_free_dev;
4600 }
4601
4602 SET_NETDEV_DEV(netdev, &pdev->dev);
4603
4604 adapter->port[i] = netdev;
4605 pi = netdev_priv(netdev);
4606 pi->adapter = adapter;
4607 pi->xact_addr_filt = -1;
b8ff05a9 4608 pi->port_id = i;
b8ff05a9
DM		 4609 netdev->irq = pdev->irq;
4610
2ed28baa
MM		 4611 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4612 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4613 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 4614 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 4615 if (highdma)
4616 netdev->hw_features |= NETIF_F_HIGHDMA;
4617 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 4618 netdev->vlan_features = netdev->features & VLAN_FEAT;
4619
01789349
JP		 4620 netdev->priv_flags |= IFF_UNICAST_FLT;
4621
b8ff05a9 4622 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 4623#ifdef CONFIG_CHELSIO_T4_DCB
4624 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4625 cxgb4_dcb_state_init(netdev);
4626#endif
812034f1 4627 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 4628 }
4629
4630 pci_set_drvdata(pdev, adapter);
4631
4632 if (adapter->flags & FW_OK) {
060e0c75 4633 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 4634 if (err)
4635 goto out_free_dev;
4636 }
4637
4638 /*
4639 * Configure queues and allocate tables now, they can be needed as
4640 * soon as the first register_netdev completes.
4641 */
4642 cfg_queues(adapter);
4643
4644 adapter->l2t = t4_init_l2t();
4645 if (!adapter->l2t) {
4646 /* We tolerate a lack of L2T, giving up some functionality */
4647 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4648 adapter->params.offload = 0;
4649 }
4650
b5a02f50
AB		 4651#if IS_ENABLED(CONFIG_IPV6)
4652 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4653 adapter->clipt_end);
4654 if (!adapter->clipt) {
4655 /* We tolerate a lack of clip_table, giving up
4656 * some functionality
4657 */
4658 dev_warn(&pdev->dev,
4659 "could not allocate Clip table, continuing\n");
4660 adapter->params.offload = 0;
4661 }
4662#endif
b8ff05a9
DM		 4663 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4664 dev_warn(&pdev->dev, "could not allocate TID table, "
4665 "continuing\n");
4666 adapter->params.offload = 0;
4667 }
4668
f7cabcdd
DM		 4669 /* See what interrupts we'll be using */
4670 if (msi > 1 && enable_msix(adapter) == 0)
4671 adapter->flags |= USING_MSIX;
4672 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4673 adapter->flags |= USING_MSI;
4674
671b0060
DM		 4675 err = init_rss(adapter);
4676 if (err)
4677 goto out_free_dev;
4678
b8ff05a9
DM		 4679 /*
4680 * The card is now ready to go. If any errors occur during device
4681 * registration we do not fail the whole card but rather proceed only
4682 * with the ports we manage to register successfully. However we must
4683 * register at least one net device.
4684 */
4685 for_each_port(adapter, i) {
a57cabe0
DM		 4686 pi = adap2pinfo(adapter, i);
4687 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4688 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4689
b8ff05a9
DM		 4690 err = register_netdev(adapter->port[i]);
4691 if (err)
b1a3c2b6 4692 break;
b1a3c2b6
DM		 4693 adapter->chan_map[pi->tx_chan] = i;
4694 print_port_info(adapter->port[i]);
b8ff05a9 4695 }
b1a3c2b6 4696 if (i == 0) {
b8ff05a9
DM		 4697 dev_err(&pdev->dev, "could not register any net devices\n");
4698 goto out_free_dev;
4699 }
b1a3c2b6
DM		 4700 if (err) {
4701 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4702 err = 0;
6403eab1 4703 }
b8ff05a9
DM		 4704
4705 if (cxgb4_debugfs_root) {
4706 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4707 cxgb4_debugfs_root);
4708 setup_debugfs(adapter);
4709 }
4710
6482aa7c
DLR		 4711 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4712 pdev->needs_freset = 1;
4713
b8ff05a9
DM		 4714 if (is_offload(adapter))
4715 attach_ulds(adapter);
4716
8e1e6059 4717sriov:
b8ff05a9 4718#ifdef CONFIG_PCI_IOV
7d6727cf 4719 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 4720 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4721 dev_info(&pdev->dev,
4722 "instantiated %u virtual functions\n",
4723 num_vf[func]);
4724#endif
4725 return 0;
4726
4727 out_free_dev:
06546391 4728 free_some_resources(adapter);
b8ff05a9 4729 out_unmap_bar:
d14807dd 4730 if (!is_t4(adapter->params.chip))
22adfe0a 4731 iounmap(adapter->bar2);
b8ff05a9 4732 out_free_adapter:
29aaee65
AB		 4733 if (adapter->workq)
4734 destroy_workqueue(adapter->workq);
4735
b8ff05a9 4736 kfree(adapter);
d6ce2628
HS		 4737 out_unmap_bar0:
4738 iounmap(regs);
b8ff05a9
DM		 4739 out_disable_device:
4740 pci_disable_pcie_error_reporting(pdev);
4741 pci_disable_device(pdev);
4742 out_release_regions:
4743 pci_release_regions(pdev);
b8ff05a9
DM		 4744 return err;
4745}
4746
91744948 4747static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 4748{
4749 struct adapter *adapter = pci_get_drvdata(pdev);
4750
636f9d37 4751#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 4752 pci_disable_sriov(pdev);
4753
636f9d37
VP		 4754#endif
4755
b8ff05a9
DM		 4756 if (adapter) {
4757 int i;
4758
29aaee65
AB		 4759 /* Tear down per-adapter Work Queue first since it can contain
4760 * references to our adapter data structure.
4761 */
4762 destroy_workqueue(adapter->workq);
4763
b8ff05a9
DM		 4764 if (is_offload(adapter))
4765 detach_ulds(adapter);
4766
b37987e8
HS		 4767 disable_interrupts(adapter);
4768
b8ff05a9 4769 for_each_port(adapter, i)
8f3a7676 4770 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 4771 unregister_netdev(adapter->port[i]);
4772
9f16dc2e 4773 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 4774
f2b7e78d
VP		 4775 /* If we allocated filters, free up state associated with any
4776 * valid filters ...
4777 */
4778 if (adapter->tids.ftid_tab) {
4779 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 4780 for (i = 0; i < (adapter->tids.nftids +
4781 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 4782 if (f->valid)
4783 clear_filter(adapter, f);
4784 }
4785
aaefae9b
DM		 4786 if (adapter->flags & FULL_INIT_DONE)
4787 cxgb_down(adapter);
b8ff05a9 4788
06546391 4789 free_some_resources(adapter);
b5a02f50
AB		 4790#if IS_ENABLED(CONFIG_IPV6)
4791 t4_cleanup_clip_tbl(adapter);
4792#endif
b8ff05a9 4793 iounmap(adapter->regs);
d14807dd 4794 if (!is_t4(adapter->params.chip))
22adfe0a 4795 iounmap(adapter->bar2);
b8ff05a9 4796 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 4797 if ((adapter->flags & DEV_ENABLED)) {
4798 pci_disable_device(pdev);
4799 adapter->flags &= ~DEV_ENABLED;
4800 }
b8ff05a9 4801 pci_release_regions(pdev);
ee9a33b2 4802 synchronize_rcu();
8b662fe7 4803 kfree(adapter);
a069ec91 4804 } else
b8ff05a9
DM		 4805 pci_release_regions(pdev);
4806}
4807
4808static struct pci_driver cxgb4_driver = {
4809 .name = KBUILD_MODNAME,
4810 .id_table = cxgb4_pci_tbl,
4811 .probe = init_one,
91744948 4812 .remove = remove_one,
687d705c 4813 .shutdown = remove_one,
204dc3c0 4814 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 4815};
4816
4817static int __init cxgb4_init_module(void)
4818{
4819 int ret;
4820
4821 /* Debugfs support is optional, just warn if this fails */
4822 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
4823 if (!cxgb4_debugfs_root)
428ac43f 4824 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 4825
4826 ret = pci_register_driver(&cxgb4_driver);
29aaee65 4827 if (ret < 0)
b8ff05a9 4828 debugfs_remove(cxgb4_debugfs_root);
01bcca68 4829
1bb60376 4830#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 4831 if (!inet6addr_registered) {
4832 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4833 inet6addr_registered = true;
4834 }
1bb60376 4835#endif
01bcca68 4836
b8ff05a9
DM		 4837 return ret;
4838}
4839
4840static void __exit cxgb4_cleanup_module(void)
4841{
1bb60376 4842#if IS_ENABLED(CONFIG_IPV6)
1793c798 4843 if (inet6addr_registered) {
b5a02f50
AB		 4844 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4845 inet6addr_registered = false;
4846 }
1bb60376 4847#endif
b8ff05a9
DM		 4848 pci_unregister_driver(&cxgb4_driver);
4849 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
4850}
4851
4852module_init(cxgb4_init_module);
4853module_exit(cxgb4_cleanup_module);
Linux kernel - Deliverables
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