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cxgb4: Update register ranges for T6 adapter
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_hw.c
CommitLineData
56d36be4
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
56d36be4
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
56d36be4
DM		 35#include <linux/delay.h>
36#include "cxgb4.h"
37#include "t4_regs.h"
f612b815 38#include "t4_values.h"
56d36be4
DM		 39#include "t4fw_api.h"
40
41/**
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
50 *
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
55 */
de498c89
RD		 56static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
57 int polarity, int attempts, int delay, u32 *valp)
56d36be4
DM		 58{
59 while (1) {
60 u32 val = t4_read_reg(adapter, reg);
61
62 if (!!(val & mask) == polarity) {
63 if (valp)
64 *valp = val;
65 return 0;
66 }
67 if (--attempts == 0)
68 return -EAGAIN;
69 if (delay)
70 udelay(delay);
71 }
72}
73
74static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
75 int polarity, int attempts, int delay)
76{
77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
78 delay, NULL);
79}
80
81/**
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
87 *
88 * Sets a register field specified by the supplied mask to the
89 * given value.
90 */
91void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
92 u32 val)
93{
94 u32 v = t4_read_reg(adapter, addr) & ~mask;
95
96 t4_write_reg(adapter, addr, v | val);
97 (void) t4_read_reg(adapter, addr); /* flush */
98}
99
100/**
101 * t4_read_indirect - read indirectly addressed registers
102 * @adap: the adapter
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
108 *
109 * Reads registers that are accessed indirectly through an address/data
110 * register pair.
111 */
f2b7e78d 112void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
de498c89
RD		 113 unsigned int data_reg, u32 *vals,
114 unsigned int nregs, unsigned int start_idx)
56d36be4
DM		 115{
116 while (nregs--) {
117 t4_write_reg(adap, addr_reg, start_idx);
118 *vals++ = t4_read_reg(adap, data_reg);
119 start_idx++;
120 }
121}
122
13ee15d3
VP		 123/**
124 * t4_write_indirect - write indirectly addressed registers
125 * @adap: the adapter
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
131 *
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
134 */
135void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
136 unsigned int data_reg, const u32 *vals,
137 unsigned int nregs, unsigned int start_idx)
138{
139 while (nregs--) {
140 t4_write_reg(adap, addr_reg, start_idx++);
141 t4_write_reg(adap, data_reg, *vals++);
142 }
143}
144
0abfd152
HS		 145/*
146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
147 * mechanism. This guarantees that we get the real value even if we're
148 * operating within a Virtual Machine and the Hypervisor is trapping our
149 * Configuration Space accesses.
150 */
151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
152{
3ccc6cf7
HS		 153 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
154
155 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
156 req |= ENABLE_F;
157 else
158 req |= T6_ENABLE_F;
0abfd152
HS		 159
160 if (is_t4(adap->params.chip))
f061de42 161 req |= LOCALCFG_F;
0abfd152 162
f061de42
HS		 163 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
164 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
0abfd152
HS		 165
166 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
167 * Configuration Space read. (None of the other fields matter when
168 * ENABLE is 0 so a simple register write is easier than a
169 * read-modify-write via t4_set_reg_field().)
170 */
f061de42 171 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
0abfd152
HS		 172}
173
31d55c2d
HS		 174/*
175 * t4_report_fw_error - report firmware error
176 * @adap: the adapter
177 *
178 * The adapter firmware can indicate error conditions to the host.
179 * If the firmware has indicated an error, print out the reason for
180 * the firmware error.
181 */
182static void t4_report_fw_error(struct adapter *adap)
183{
184 static const char *const reason[] = {
185 "Crash", /* PCIE_FW_EVAL_CRASH */
186 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
187 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
188 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
189 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
190 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
191 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
192 "Reserved", /* reserved */
193 };
194 u32 pcie_fw;
195
f061de42
HS		 196 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
197 if (pcie_fw & PCIE_FW_ERR_F)
31d55c2d 198 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
b2e1a3f0 199 reason[PCIE_FW_EVAL_G(pcie_fw)]);
31d55c2d
HS		 200}
201
56d36be4
DM		 202/*
203 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
204 */
205static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
206 u32 mbox_addr)
207{
208 for ( ; nflit; nflit--, mbox_addr += 8)
209 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
210}
211
212/*
213 * Handle a FW assertion reported in a mailbox.
214 */
215static void fw_asrt(struct adapter *adap, u32 mbox_addr)
216{
217 struct fw_debug_cmd asrt;
218
219 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
220 dev_alert(adap->pdev_dev,
221 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
f404f80c
HS		 222 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
223 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
56d36be4
DM		 224}
225
226static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
227{
228 dev_err(adap->pdev_dev,
229 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
230 (unsigned long long)t4_read_reg64(adap, data_reg),
231 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
238}
239
240/**
01b69614 241 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
56d36be4
DM		 242 * @adap: the adapter
243 * @mbox: index of the mailbox to use
244 * @cmd: the command to write
245 * @size: command length in bytes
246 * @rpl: where to optionally store the reply
247 * @sleep_ok: if true we may sleep while awaiting command completion
01b69614 248 * @timeout: time to wait for command to finish before timing out
56d36be4
DM		 249 *
250 * Sends the given command to FW through the selected mailbox and waits
251 * for the FW to execute the command. If @rpl is not %NULL it is used to
252 * store the FW's reply to the command. The command and its optional
253 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
254 * to respond. @sleep_ok determines whether we may sleep while awaiting
255 * the response. If sleeping is allowed we use progressive backoff
256 * otherwise we spin.
257 *
258 * The return value is 0 on success or a negative errno on failure. A
259 * failure can happen either because we are not able to execute the
260 * command or FW executes it but signals an error. In the latter case
261 * the return value is the error code indicated by FW (negated).
262 */
01b69614
HS		 263int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
264 int size, void *rpl, bool sleep_ok, int timeout)
56d36be4 265{
005b5717 266 static const int delay[] = {
56d36be4
DM		 267 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
268 };
269
270 u32 v;
271 u64 res;
272 int i, ms, delay_idx;
273 const __be64 *p = cmd;
89c3a86c
HS		 274 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
275 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
56d36be4
DM		 276
277 if ((size & 15) || size > MBOX_LEN)
278 return -EINVAL;
279
204dc3c0
DM		 280 /*
281 * If the device is off-line, as in EEH, commands will time out.
282 * Fail them early so we don't waste time waiting.
283 */
284 if (adap->pdev->error_state != pci_channel_io_normal)
285 return -EIO;
286
89c3a86c 287 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
56d36be4 288 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
89c3a86c 289 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
56d36be4
DM		 290
291 if (v != MBOX_OWNER_DRV)
292 return v ? -EBUSY : -ETIMEDOUT;
293
294 for (i = 0; i < size; i += 8)
295 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
296
89c3a86c 297 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
56d36be4
DM		 298 t4_read_reg(adap, ctl_reg); /* flush write */
299
300 delay_idx = 0;
301 ms = delay[0];
302
01b69614 303 for (i = 0; i < timeout; i += ms) {
56d36be4
DM		 304 if (sleep_ok) {
305 ms = delay[delay_idx]; /* last element may repeat */
306 if (delay_idx < ARRAY_SIZE(delay) - 1)
307 delay_idx++;
308 msleep(ms);
309 } else
310 mdelay(ms);
311
312 v = t4_read_reg(adap, ctl_reg);
89c3a86c
HS		 313 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
314 if (!(v & MBMSGVALID_F)) {
56d36be4
DM		 315 t4_write_reg(adap, ctl_reg, 0);
316 continue;
317 }
318
319 res = t4_read_reg64(adap, data_reg);
e2ac9628 320 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
56d36be4 321 fw_asrt(adap, data_reg);
e2ac9628
HS		 322 res = FW_CMD_RETVAL_V(EIO);
323 } else if (rpl) {
56d36be4 324 get_mbox_rpl(adap, rpl, size / 8, data_reg);
e2ac9628 325 }
56d36be4 326
e2ac9628 327 if (FW_CMD_RETVAL_G((int)res))
56d36be4
DM		 328 dump_mbox(adap, mbox, data_reg);
329 t4_write_reg(adap, ctl_reg, 0);
e2ac9628 330 return -FW_CMD_RETVAL_G((int)res);
56d36be4
DM		 331 }
332 }
333
334 dump_mbox(adap, mbox, data_reg);
335 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
336 *(const u8 *)cmd, mbox);
31d55c2d 337 t4_report_fw_error(adap);
56d36be4
DM		 338 return -ETIMEDOUT;
339}
340
01b69614
HS		 341int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
342 void *rpl, bool sleep_ok)
56d36be4 343{
01b69614
HS		 344 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
345 FW_CMD_MAX_TIMEOUT);
56d36be4
DM		 346}
347
5afc8b84
VP		 348/**
349 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
350 * @adap: the adapter
fc5ab020 351 * @win: PCI-E Memory Window to use
5afc8b84
VP		 352 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
353 * @addr: address within indicated memory type
354 * @len: amount of memory to transfer
f01aa633 355 * @hbuf: host memory buffer
fc5ab020 356 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
5afc8b84
VP		 357 *
358 * Reads/writes an [almost] arbitrary memory region in the firmware: the
fc5ab020
HS		 359 * firmware memory address and host buffer must be aligned on 32-bit
360 * boudaries; the length may be arbitrary. The memory is transferred as
361 * a raw byte sequence from/to the firmware's memory. If this memory
362 * contains data structures which contain multi-byte integers, it's the
363 * caller's responsibility to perform appropriate byte order conversions.
5afc8b84 364 */
fc5ab020 365int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
f01aa633 366 u32 len, void *hbuf, int dir)
5afc8b84 367{
fc5ab020
HS		 368 u32 pos, offset, resid, memoffset;
369 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
f01aa633 370 u32 *buf;
5afc8b84 371
fc5ab020 372 /* Argument sanity checks ...
5afc8b84 373 */
f01aa633 374 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
5afc8b84 375 return -EINVAL;
f01aa633 376 buf = (u32 *)hbuf;
5afc8b84 377
fc5ab020
HS		 378 /* It's convenient to be able to handle lengths which aren't a
379 * multiple of 32-bits because we often end up transferring files to
380 * the firmware. So we'll handle that by normalizing the length here
381 * and then handling any residual transfer at the end.
382 */
383 resid = len & 0x3;
384 len -= resid;
8c357ebd 385
19dd37ba 386 /* Offset into the region of memory which is being accessed
5afc8b84
VP		 387 * MEM_EDC0 = 0
388 * MEM_EDC1 = 1
3ccc6cf7
HS		 389 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
390 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
5afc8b84 391 */
6559a7e8 392 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
19dd37ba
SR		 393 if (mtype != MEM_MC1)
394 memoffset = (mtype * (edc_size * 1024 * 1024));
395 else {
6559a7e8 396 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
7f0b8a56 397 MA_EXT_MEMORY0_BAR_A));
19dd37ba
SR		 398 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
399 }
5afc8b84
VP		 400
401 /* Determine the PCIE_MEM_ACCESS_OFFSET */
402 addr = addr + memoffset;
403
fc5ab020
HS		 404 /* Each PCI-E Memory Window is programmed with a window size -- or
405 * "aperture" -- which controls the granularity of its mapping onto
406 * adapter memory. We need to grab that aperture in order to know
407 * how to use the specified window. The window is also programmed
408 * with the base address of the Memory Window in BAR0's address
409 * space. For T4 this is an absolute PCI-E Bus Address. For T5
410 * the address is relative to BAR0.
5afc8b84 411 */
fc5ab020 412 mem_reg = t4_read_reg(adap,
f061de42 413 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
fc5ab020 414 win));
f061de42
HS		 415 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
416 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
fc5ab020
HS		 417 if (is_t4(adap->params.chip))
418 mem_base -= adap->t4_bar0;
b2612722 419 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
5afc8b84 420
fc5ab020
HS		 421 /* Calculate our initial PCI-E Memory Window Position and Offset into
422 * that Window.
423 */
424 pos = addr & ~(mem_aperture-1);
425 offset = addr - pos;
5afc8b84 426
fc5ab020
HS		 427 /* Set up initial PCI-E Memory Window to cover the start of our
428 * transfer. (Read it back to ensure that changes propagate before we
429 * attempt to use the new value.)
430 */
431 t4_write_reg(adap,
f061de42 432 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
fc5ab020
HS		 433 pos | win_pf);
434 t4_read_reg(adap,
f061de42 435 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
fc5ab020
HS		 436
437 /* Transfer data to/from the adapter as long as there's an integral
438 * number of 32-bit transfers to complete.
f01aa633
HS		 439 *
440 * A note on Endianness issues:
441 *
442 * The "register" reads and writes below from/to the PCI-E Memory
443 * Window invoke the standard adapter Big-Endian to PCI-E Link
444 * Little-Endian "swizzel." As a result, if we have the following
445 * data in adapter memory:
446 *
447 * Memory: ... | b0 | b1 | b2 | b3 | ...
448 * Address: i+0 i+1 i+2 i+3
449 *
450 * Then a read of the adapter memory via the PCI-E Memory Window
451 * will yield:
452 *
453 * x = readl(i)
454 * 31 0
455 * [ b3 | b2 | b1 | b0 ]
456 *
457 * If this value is stored into local memory on a Little-Endian system
458 * it will show up correctly in local memory as:
459 *
460 * ( ..., b0, b1, b2, b3, ... )
461 *
462 * But on a Big-Endian system, the store will show up in memory
463 * incorrectly swizzled as:
464 *
465 * ( ..., b3, b2, b1, b0, ... )
466 *
467 * So we need to account for this in the reads and writes to the
468 * PCI-E Memory Window below by undoing the register read/write
469 * swizzels.
fc5ab020
HS		 470 */
471 while (len > 0) {
472 if (dir == T4_MEMORY_READ)
f01aa633
HS		 473 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
474 mem_base + offset));
fc5ab020
HS		 475 else
476 t4_write_reg(adap, mem_base + offset,
f01aa633 477 (__force u32)cpu_to_le32(*buf++));
fc5ab020
HS		 478 offset += sizeof(__be32);
479 len -= sizeof(__be32);
480
481 /* If we've reached the end of our current window aperture,
482 * move the PCI-E Memory Window on to the next. Note that
483 * doing this here after "len" may be 0 allows us to set up
484 * the PCI-E Memory Window for a possible final residual
485 * transfer below ...
5afc8b84 486 */
fc5ab020
HS		 487 if (offset == mem_aperture) {
488 pos += mem_aperture;
489 offset = 0;
490 t4_write_reg(adap,
f061de42
HS		 491 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
492 win), pos | win_pf);
fc5ab020 493 t4_read_reg(adap,
f061de42
HS		 494 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
495 win));
5afc8b84 496 }
5afc8b84
VP		 497 }
498
fc5ab020
HS		 499 /* If the original transfer had a length which wasn't a multiple of
500 * 32-bits, now's where we need to finish off the transfer of the
501 * residual amount. The PCI-E Memory Window has already been moved
502 * above (if necessary) to cover this final transfer.
503 */
504 if (resid) {
505 union {
f01aa633 506 u32 word;
fc5ab020
HS		 507 char byte[4];
508 } last;
509 unsigned char *bp;
510 int i;
511
c81576c2 512 if (dir == T4_MEMORY_READ) {
f01aa633
HS		 513 last.word = le32_to_cpu(
514 (__force __le32)t4_read_reg(adap,
515 mem_base + offset));
fc5ab020
HS		 516 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
517 bp[i] = last.byte[i];
518 } else {
519 last.word = *buf;
520 for (i = resid; i < 4; i++)
521 last.byte[i] = 0;
522 t4_write_reg(adap, mem_base + offset,
f01aa633 523 (__force u32)cpu_to_le32(last.word));
fc5ab020
HS		 524 }
525 }
5afc8b84 526
fc5ab020 527 return 0;
5afc8b84
VP		 528}
529
b562fc37
HS		 530/* Return the specified PCI-E Configuration Space register from our Physical
531 * Function. We try first via a Firmware LDST Command since we prefer to let
532 * the firmware own all of these registers, but if that fails we go for it
533 * directly ourselves.
534 */
535u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
536{
537 u32 val, ldst_addrspace;
538
539 /* If fw_attach != 0, construct and send the Firmware LDST Command to
540 * retrieve the specified PCI-E Configuration Space register.
541 */
542 struct fw_ldst_cmd ldst_cmd;
543 int ret;
544
545 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
546 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
547 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
548 FW_CMD_REQUEST_F |
549 FW_CMD_READ_F |
550 ldst_addrspace);
551 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
552 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
553 ldst_cmd.u.pcie.ctrl_to_fn =
b2612722 554 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
b562fc37
HS		 555 ldst_cmd.u.pcie.r = reg;
556
557 /* If the LDST Command succeeds, return the result, otherwise
558 * fall through to reading it directly ourselves ...
559 */
560 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
561 &ldst_cmd);
562 if (ret == 0)
563 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
564 else
565 /* Read the desired Configuration Space register via the PCI-E
566 * Backdoor mechanism.
567 */
568 t4_hw_pci_read_cfg4(adap, reg, &val);
569 return val;
570}
571
572/* Get the window based on base passed to it.
573 * Window aperture is currently unhandled, but there is no use case for it
574 * right now
575 */
576static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
577 u32 memwin_base)
578{
579 u32 ret;
580
581 if (is_t4(adap->params.chip)) {
582 u32 bar0;
583
584 /* Truncation intentional: we only read the bottom 32-bits of
585 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
586 * mechanism to read BAR0 instead of using
587 * pci_resource_start() because we could be operating from
588 * within a Virtual Machine which is trapping our accesses to
589 * our Configuration Space and we need to set up the PCI-E
590 * Memory Window decoders with the actual addresses which will
591 * be coming across the PCI-E link.
592 */
593 bar0 = t4_read_pcie_cfg4(adap, pci_base);
594 bar0 &= pci_mask;
595 adap->t4_bar0 = bar0;
596
597 ret = bar0 + memwin_base;
598 } else {
599 /* For T5, only relative offset inside the PCIe BAR is passed */
600 ret = memwin_base;
601 }
602 return ret;
603}
604
605/* Get the default utility window (win0) used by everyone */
606u32 t4_get_util_window(struct adapter *adap)
607{
608 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
609 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
610}
611
612/* Set up memory window for accessing adapter memory ranges. (Read
613 * back MA register to ensure that changes propagate before we attempt
614 * to use the new values.)
615 */
616void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
617{
618 t4_write_reg(adap,
619 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
620 memwin_base | BIR_V(0) |
621 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
622 t4_read_reg(adap,
623 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
624}
625
812034f1
HS		 626/**
627 * t4_get_regs_len - return the size of the chips register set
628 * @adapter: the adapter
629 *
630 * Returns the size of the chip's BAR0 register space.
631 */
632unsigned int t4_get_regs_len(struct adapter *adapter)
633{
634 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
635
636 switch (chip_version) {
637 case CHELSIO_T4:
638 return T4_REGMAP_SIZE;
639
640 case CHELSIO_T5:
ab4b583b 641 case CHELSIO_T6:
812034f1
HS		 642 return T5_REGMAP_SIZE;
643 }
644
645 dev_err(adapter->pdev_dev,
646 "Unsupported chip version %d\n", chip_version);
647 return 0;
648}
649
650/**
651 * t4_get_regs - read chip registers into provided buffer
652 * @adap: the adapter
653 * @buf: register buffer
654 * @buf_size: size (in bytes) of register buffer
655 *
656 * If the provided register buffer isn't large enough for the chip's
657 * full register range, the register dump will be truncated to the
658 * register buffer's size.
659 */
660void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
661{
662 static const unsigned int t4_reg_ranges[] = {
663 0x1008, 0x1108,
664 0x1180, 0x11b4,
665 0x11fc, 0x123c,
666 0x1300, 0x173c,
667 0x1800, 0x18fc,
9f5ac48d
HS		 668 0x3000, 0x305c,
669 0x3068, 0x30d8,
812034f1
HS		 670 0x30e0, 0x5924,
671 0x5960, 0x59d4,
672 0x5a00, 0x5af8,
673 0x6000, 0x6098,
674 0x6100, 0x6150,
675 0x6200, 0x6208,
676 0x6240, 0x6248,
677 0x6280, 0x6338,
678 0x6370, 0x638c,
679 0x6400, 0x643c,
680 0x6500, 0x6524,
681 0x6a00, 0x6a38,
682 0x6a60, 0x6a78,
683 0x6b00, 0x6b84,
684 0x6bf0, 0x6c84,
685 0x6cf0, 0x6d84,
686 0x6df0, 0x6e84,
687 0x6ef0, 0x6f84,
688 0x6ff0, 0x7084,
689 0x70f0, 0x7184,
690 0x71f0, 0x7284,
691 0x72f0, 0x7384,
692 0x73f0, 0x7450,
693 0x7500, 0x7530,
694 0x7600, 0x761c,
695 0x7680, 0x76cc,
696 0x7700, 0x7798,
697 0x77c0, 0x77fc,
698 0x7900, 0x79fc,
699 0x7b00, 0x7c38,
700 0x7d00, 0x7efc,
701 0x8dc0, 0x8e1c,
702 0x8e30, 0x8e78,
703 0x8ea0, 0x8f6c,
704 0x8fc0, 0x9074,
705 0x90fc, 0x90fc,
706 0x9400, 0x9458,
707 0x9600, 0x96bc,
708 0x9800, 0x9808,
709 0x9820, 0x983c,
710 0x9850, 0x9864,
711 0x9c00, 0x9c6c,
712 0x9c80, 0x9cec,
713 0x9d00, 0x9d6c,
714 0x9d80, 0x9dec,
715 0x9e00, 0x9e6c,
716 0x9e80, 0x9eec,
717 0x9f00, 0x9f6c,
718 0x9f80, 0x9fec,
719 0xd004, 0xd03c,
720 0xdfc0, 0xdfe0,
721 0xe000, 0xea7c,
722 0xf000, 0x11110,
723 0x11118, 0x11190,
724 0x19040, 0x1906c,
725 0x19078, 0x19080,
726 0x1908c, 0x19124,
727 0x19150, 0x191b0,
728 0x191d0, 0x191e8,
729 0x19238, 0x1924c,
730 0x193f8, 0x19474,
731 0x19490, 0x194f8,
9f5ac48d 732 0x19800, 0x19f4c,
812034f1
HS		 733 0x1a000, 0x1a06c,
734 0x1a0b0, 0x1a120,
735 0x1a128, 0x1a138,
736 0x1a190, 0x1a1c4,
737 0x1a1fc, 0x1a1fc,
738 0x1e040, 0x1e04c,
739 0x1e284, 0x1e28c,
740 0x1e2c0, 0x1e2c0,
741 0x1e2e0, 0x1e2e0,
742 0x1e300, 0x1e384,
743 0x1e3c0, 0x1e3c8,
744 0x1e440, 0x1e44c,
745 0x1e684, 0x1e68c,
746 0x1e6c0, 0x1e6c0,
747 0x1e6e0, 0x1e6e0,
748 0x1e700, 0x1e784,
749 0x1e7c0, 0x1e7c8,
750 0x1e840, 0x1e84c,
751 0x1ea84, 0x1ea8c,
752 0x1eac0, 0x1eac0,
753 0x1eae0, 0x1eae0,
754 0x1eb00, 0x1eb84,
755 0x1ebc0, 0x1ebc8,
756 0x1ec40, 0x1ec4c,
757 0x1ee84, 0x1ee8c,
758 0x1eec0, 0x1eec0,
759 0x1eee0, 0x1eee0,
760 0x1ef00, 0x1ef84,
761 0x1efc0, 0x1efc8,
762 0x1f040, 0x1f04c,
763 0x1f284, 0x1f28c,
764 0x1f2c0, 0x1f2c0,
765 0x1f2e0, 0x1f2e0,
766 0x1f300, 0x1f384,
767 0x1f3c0, 0x1f3c8,
768 0x1f440, 0x1f44c,
769 0x1f684, 0x1f68c,
770 0x1f6c0, 0x1f6c0,
771 0x1f6e0, 0x1f6e0,
772 0x1f700, 0x1f784,
773 0x1f7c0, 0x1f7c8,
774 0x1f840, 0x1f84c,
775 0x1fa84, 0x1fa8c,
776 0x1fac0, 0x1fac0,
777 0x1fae0, 0x1fae0,
778 0x1fb00, 0x1fb84,
779 0x1fbc0, 0x1fbc8,
780 0x1fc40, 0x1fc4c,
781 0x1fe84, 0x1fe8c,
782 0x1fec0, 0x1fec0,
783 0x1fee0, 0x1fee0,
784 0x1ff00, 0x1ff84,
785 0x1ffc0, 0x1ffc8,
786 0x20000, 0x2002c,
787 0x20100, 0x2013c,
788 0x20190, 0x201c8,
789 0x20200, 0x20318,
790 0x20400, 0x20528,
791 0x20540, 0x20614,
792 0x21000, 0x21040,
793 0x2104c, 0x21060,
794 0x210c0, 0x210ec,
795 0x21200, 0x21268,
796 0x21270, 0x21284,
797 0x212fc, 0x21388,
798 0x21400, 0x21404,
799 0x21500, 0x21518,
800 0x2152c, 0x2153c,
801 0x21550, 0x21554,
802 0x21600, 0x21600,
803 0x21608, 0x21628,
804 0x21630, 0x2163c,
805 0x21700, 0x2171c,
806 0x21780, 0x2178c,
807 0x21800, 0x21c38,
808 0x21c80, 0x21d7c,
809 0x21e00, 0x21e04,
810 0x22000, 0x2202c,
811 0x22100, 0x2213c,
812 0x22190, 0x221c8,
813 0x22200, 0x22318,
814 0x22400, 0x22528,
815 0x22540, 0x22614,
816 0x23000, 0x23040,
817 0x2304c, 0x23060,
818 0x230c0, 0x230ec,
819 0x23200, 0x23268,
820 0x23270, 0x23284,
821 0x232fc, 0x23388,
822 0x23400, 0x23404,
823 0x23500, 0x23518,
824 0x2352c, 0x2353c,
825 0x23550, 0x23554,
826 0x23600, 0x23600,
827 0x23608, 0x23628,
828 0x23630, 0x2363c,
829 0x23700, 0x2371c,
830 0x23780, 0x2378c,
831 0x23800, 0x23c38,
832 0x23c80, 0x23d7c,
833 0x23e00, 0x23e04,
834 0x24000, 0x2402c,
835 0x24100, 0x2413c,
836 0x24190, 0x241c8,
837 0x24200, 0x24318,
838 0x24400, 0x24528,
839 0x24540, 0x24614,
840 0x25000, 0x25040,
841 0x2504c, 0x25060,
842 0x250c0, 0x250ec,
843 0x25200, 0x25268,
844 0x25270, 0x25284,
845 0x252fc, 0x25388,
846 0x25400, 0x25404,
847 0x25500, 0x25518,
848 0x2552c, 0x2553c,
849 0x25550, 0x25554,
850 0x25600, 0x25600,
851 0x25608, 0x25628,
852 0x25630, 0x2563c,
853 0x25700, 0x2571c,
854 0x25780, 0x2578c,
855 0x25800, 0x25c38,
856 0x25c80, 0x25d7c,
857 0x25e00, 0x25e04,
858 0x26000, 0x2602c,
859 0x26100, 0x2613c,
860 0x26190, 0x261c8,
861 0x26200, 0x26318,
862 0x26400, 0x26528,
863 0x26540, 0x26614,
864 0x27000, 0x27040,
865 0x2704c, 0x27060,
866 0x270c0, 0x270ec,
867 0x27200, 0x27268,
868 0x27270, 0x27284,
869 0x272fc, 0x27388,
870 0x27400, 0x27404,
871 0x27500, 0x27518,
872 0x2752c, 0x2753c,
873 0x27550, 0x27554,
874 0x27600, 0x27600,
875 0x27608, 0x27628,
876 0x27630, 0x2763c,
877 0x27700, 0x2771c,
878 0x27780, 0x2778c,
879 0x27800, 0x27c38,
880 0x27c80, 0x27d7c,
9f5ac48d 881 0x27e00, 0x27e04,
812034f1
HS		 882 };
883
884 static const unsigned int t5_reg_ranges[] = {
885 0x1008, 0x1148,
886 0x1180, 0x11b4,
887 0x11fc, 0x123c,
888 0x1280, 0x173c,
889 0x1800, 0x18fc,
890 0x3000, 0x3028,
9f5ac48d 891 0x3068, 0x30d8,
812034f1
HS		 892 0x30e0, 0x30fc,
893 0x3140, 0x357c,
894 0x35a8, 0x35cc,
895 0x35ec, 0x35ec,
896 0x3600, 0x5624,
897 0x56cc, 0x575c,
898 0x580c, 0x5814,
899 0x5890, 0x58bc,
900 0x5940, 0x59dc,
901 0x59fc, 0x5a18,
902 0x5a60, 0x5a9c,
9f5ac48d 903 0x5b94, 0x5bfc,
812034f1
HS		 904 0x6000, 0x6040,
905 0x6058, 0x614c,
906 0x7700, 0x7798,
907 0x77c0, 0x78fc,
908 0x7b00, 0x7c54,
909 0x7d00, 0x7efc,
910 0x8dc0, 0x8de0,
911 0x8df8, 0x8e84,
912 0x8ea0, 0x8f84,
913 0x8fc0, 0x90f8,
914 0x9400, 0x9470,
915 0x9600, 0x96f4,
916 0x9800, 0x9808,
917 0x9820, 0x983c,
918 0x9850, 0x9864,
919 0x9c00, 0x9c6c,
920 0x9c80, 0x9cec,
921 0x9d00, 0x9d6c,
922 0x9d80, 0x9dec,
923 0x9e00, 0x9e6c,
924 0x9e80, 0x9eec,
925 0x9f00, 0x9f6c,
926 0x9f80, 0xa020,
927 0xd004, 0xd03c,
928 0xdfc0, 0xdfe0,
929 0xe000, 0x11088,
930 0x1109c, 0x11110,
931 0x11118, 0x1117c,
932 0x11190, 0x11204,
933 0x19040, 0x1906c,
934 0x19078, 0x19080,
935 0x1908c, 0x19124,
936 0x19150, 0x191b0,
937 0x191d0, 0x191e8,
938 0x19238, 0x19290,
939 0x193f8, 0x19474,
940 0x19490, 0x194cc,
941 0x194f0, 0x194f8,
942 0x19c00, 0x19c60,
943 0x19c94, 0x19e10,
944 0x19e50, 0x19f34,
945 0x19f40, 0x19f50,
946 0x19f90, 0x19fe4,
947 0x1a000, 0x1a06c,
948 0x1a0b0, 0x1a120,
949 0x1a128, 0x1a138,
950 0x1a190, 0x1a1c4,
951 0x1a1fc, 0x1a1fc,
952 0x1e008, 0x1e00c,
953 0x1e040, 0x1e04c,
954 0x1e284, 0x1e290,
955 0x1e2c0, 0x1e2c0,
956 0x1e2e0, 0x1e2e0,
957 0x1e300, 0x1e384,
958 0x1e3c0, 0x1e3c8,
959 0x1e408, 0x1e40c,
960 0x1e440, 0x1e44c,
961 0x1e684, 0x1e690,
962 0x1e6c0, 0x1e6c0,
963 0x1e6e0, 0x1e6e0,
964 0x1e700, 0x1e784,
965 0x1e7c0, 0x1e7c8,
966 0x1e808, 0x1e80c,
967 0x1e840, 0x1e84c,
968 0x1ea84, 0x1ea90,
969 0x1eac0, 0x1eac0,
970 0x1eae0, 0x1eae0,
971 0x1eb00, 0x1eb84,
972 0x1ebc0, 0x1ebc8,
973 0x1ec08, 0x1ec0c,
974 0x1ec40, 0x1ec4c,
975 0x1ee84, 0x1ee90,
976 0x1eec0, 0x1eec0,
977 0x1eee0, 0x1eee0,
978 0x1ef00, 0x1ef84,
979 0x1efc0, 0x1efc8,
980 0x1f008, 0x1f00c,
981 0x1f040, 0x1f04c,
982 0x1f284, 0x1f290,
983 0x1f2c0, 0x1f2c0,
984 0x1f2e0, 0x1f2e0,
985 0x1f300, 0x1f384,
986 0x1f3c0, 0x1f3c8,
987 0x1f408, 0x1f40c,
988 0x1f440, 0x1f44c,
989 0x1f684, 0x1f690,
990 0x1f6c0, 0x1f6c0,
991 0x1f6e0, 0x1f6e0,
992 0x1f700, 0x1f784,
993 0x1f7c0, 0x1f7c8,
994 0x1f808, 0x1f80c,
995 0x1f840, 0x1f84c,
996 0x1fa84, 0x1fa90,
997 0x1fac0, 0x1fac0,
998 0x1fae0, 0x1fae0,
999 0x1fb00, 0x1fb84,
1000 0x1fbc0, 0x1fbc8,
1001 0x1fc08, 0x1fc0c,
1002 0x1fc40, 0x1fc4c,
1003 0x1fe84, 0x1fe90,
1004 0x1fec0, 0x1fec0,
1005 0x1fee0, 0x1fee0,
1006 0x1ff00, 0x1ff84,
1007 0x1ffc0, 0x1ffc8,
1008 0x30000, 0x30030,
1009 0x30100, 0x30144,
1010 0x30190, 0x301d0,
1011 0x30200, 0x30318,
1012 0x30400, 0x3052c,
1013 0x30540, 0x3061c,
1014 0x30800, 0x30834,
1015 0x308c0, 0x30908,
1016 0x30910, 0x309ac,
9f5ac48d 1017 0x30a00, 0x30a2c,
812034f1
HS		 1018 0x30a44, 0x30a50,
1019 0x30a74, 0x30c24,
9f5ac48d 1020 0x30d00, 0x30d00,
812034f1
HS		 1021 0x30d08, 0x30d14,
1022 0x30d1c, 0x30d20,
1023 0x30d3c, 0x30d50,
1024 0x31200, 0x3120c,
1025 0x31220, 0x31220,
1026 0x31240, 0x31240,
9f5ac48d 1027 0x31600, 0x3160c,
812034f1 1028 0x31a00, 0x31a1c,
9f5ac48d 1029 0x31e00, 0x31e20,
812034f1
HS		 1030 0x31e38, 0x31e3c,
1031 0x31e80, 0x31e80,
1032 0x31e88, 0x31ea8,
1033 0x31eb0, 0x31eb4,
1034 0x31ec8, 0x31ed4,
1035 0x31fb8, 0x32004,
9f5ac48d
HS		 1036 0x32200, 0x32200,
1037 0x32208, 0x32240,
1038 0x32248, 0x32280,
1039 0x32288, 0x322c0,
1040 0x322c8, 0x322fc,
812034f1
HS		 1041 0x32600, 0x32630,
1042 0x32a00, 0x32abc,
1043 0x32b00, 0x32b70,
1044 0x33000, 0x33048,
1045 0x33060, 0x3309c,
1046 0x330f0, 0x33148,
1047 0x33160, 0x3319c,
1048 0x331f0, 0x332e4,
1049 0x332f8, 0x333e4,
1050 0x333f8, 0x33448,
1051 0x33460, 0x3349c,
1052 0x334f0, 0x33548,
1053 0x33560, 0x3359c,
1054 0x335f0, 0x336e4,
1055 0x336f8, 0x337e4,
1056 0x337f8, 0x337fc,
1057 0x33814, 0x33814,
1058 0x3382c, 0x3382c,
1059 0x33880, 0x3388c,
1060 0x338e8, 0x338ec,
1061 0x33900, 0x33948,
1062 0x33960, 0x3399c,
1063 0x339f0, 0x33ae4,
1064 0x33af8, 0x33b10,
1065 0x33b28, 0x33b28,
1066 0x33b3c, 0x33b50,
1067 0x33bf0, 0x33c10,
1068 0x33c28, 0x33c28,
1069 0x33c3c, 0x33c50,
1070 0x33cf0, 0x33cfc,
1071 0x34000, 0x34030,
1072 0x34100, 0x34144,
1073 0x34190, 0x341d0,
1074 0x34200, 0x34318,
1075 0x34400, 0x3452c,
1076 0x34540, 0x3461c,
1077 0x34800, 0x34834,
1078 0x348c0, 0x34908,
1079 0x34910, 0x349ac,
9f5ac48d 1080 0x34a00, 0x34a2c,
812034f1
HS		 1081 0x34a44, 0x34a50,
1082 0x34a74, 0x34c24,
9f5ac48d 1083 0x34d00, 0x34d00,
812034f1
HS		 1084 0x34d08, 0x34d14,
1085 0x34d1c, 0x34d20,
1086 0x34d3c, 0x34d50,
1087 0x35200, 0x3520c,
1088 0x35220, 0x35220,
1089 0x35240, 0x35240,
9f5ac48d 1090 0x35600, 0x3560c,
812034f1 1091 0x35a00, 0x35a1c,
9f5ac48d 1092 0x35e00, 0x35e20,
812034f1
HS		 1093 0x35e38, 0x35e3c,
1094 0x35e80, 0x35e80,
1095 0x35e88, 0x35ea8,
1096 0x35eb0, 0x35eb4,
1097 0x35ec8, 0x35ed4,
1098 0x35fb8, 0x36004,
9f5ac48d
HS		 1099 0x36200, 0x36200,
1100 0x36208, 0x36240,
1101 0x36248, 0x36280,
1102 0x36288, 0x362c0,
1103 0x362c8, 0x362fc,
812034f1
HS		 1104 0x36600, 0x36630,
1105 0x36a00, 0x36abc,
1106 0x36b00, 0x36b70,
1107 0x37000, 0x37048,
1108 0x37060, 0x3709c,
1109 0x370f0, 0x37148,
1110 0x37160, 0x3719c,
1111 0x371f0, 0x372e4,
1112 0x372f8, 0x373e4,
1113 0x373f8, 0x37448,
1114 0x37460, 0x3749c,
1115 0x374f0, 0x37548,
1116 0x37560, 0x3759c,
1117 0x375f0, 0x376e4,
1118 0x376f8, 0x377e4,
1119 0x377f8, 0x377fc,
1120 0x37814, 0x37814,
1121 0x3782c, 0x3782c,
1122 0x37880, 0x3788c,
1123 0x378e8, 0x378ec,
1124 0x37900, 0x37948,
1125 0x37960, 0x3799c,
1126 0x379f0, 0x37ae4,
1127 0x37af8, 0x37b10,
1128 0x37b28, 0x37b28,
1129 0x37b3c, 0x37b50,
1130 0x37bf0, 0x37c10,
1131 0x37c28, 0x37c28,
1132 0x37c3c, 0x37c50,
1133 0x37cf0, 0x37cfc,
1134 0x38000, 0x38030,
1135 0x38100, 0x38144,
1136 0x38190, 0x381d0,
1137 0x38200, 0x38318,
1138 0x38400, 0x3852c,
1139 0x38540, 0x3861c,
1140 0x38800, 0x38834,
1141 0x388c0, 0x38908,
1142 0x38910, 0x389ac,
9f5ac48d 1143 0x38a00, 0x38a2c,
812034f1
HS		 1144 0x38a44, 0x38a50,
1145 0x38a74, 0x38c24,
9f5ac48d 1146 0x38d00, 0x38d00,
812034f1
HS		 1147 0x38d08, 0x38d14,
1148 0x38d1c, 0x38d20,
1149 0x38d3c, 0x38d50,
1150 0x39200, 0x3920c,
1151 0x39220, 0x39220,
1152 0x39240, 0x39240,
9f5ac48d 1153 0x39600, 0x3960c,
812034f1 1154 0x39a00, 0x39a1c,
9f5ac48d 1155 0x39e00, 0x39e20,
812034f1
HS		 1156 0x39e38, 0x39e3c,
1157 0x39e80, 0x39e80,
1158 0x39e88, 0x39ea8,
1159 0x39eb0, 0x39eb4,
1160 0x39ec8, 0x39ed4,
1161 0x39fb8, 0x3a004,
9f5ac48d
HS		 1162 0x3a200, 0x3a200,
1163 0x3a208, 0x3a240,
1164 0x3a248, 0x3a280,
1165 0x3a288, 0x3a2c0,
1166 0x3a2c8, 0x3a2fc,
812034f1
HS		 1167 0x3a600, 0x3a630,
1168 0x3aa00, 0x3aabc,
1169 0x3ab00, 0x3ab70,
1170 0x3b000, 0x3b048,
1171 0x3b060, 0x3b09c,
1172 0x3b0f0, 0x3b148,
1173 0x3b160, 0x3b19c,
1174 0x3b1f0, 0x3b2e4,
1175 0x3b2f8, 0x3b3e4,
1176 0x3b3f8, 0x3b448,
1177 0x3b460, 0x3b49c,
1178 0x3b4f0, 0x3b548,
1179 0x3b560, 0x3b59c,
1180 0x3b5f0, 0x3b6e4,
1181 0x3b6f8, 0x3b7e4,
1182 0x3b7f8, 0x3b7fc,
1183 0x3b814, 0x3b814,
1184 0x3b82c, 0x3b82c,
1185 0x3b880, 0x3b88c,
1186 0x3b8e8, 0x3b8ec,
1187 0x3b900, 0x3b948,
1188 0x3b960, 0x3b99c,
1189 0x3b9f0, 0x3bae4,
1190 0x3baf8, 0x3bb10,
1191 0x3bb28, 0x3bb28,
1192 0x3bb3c, 0x3bb50,
1193 0x3bbf0, 0x3bc10,
1194 0x3bc28, 0x3bc28,
1195 0x3bc3c, 0x3bc50,
1196 0x3bcf0, 0x3bcfc,
1197 0x3c000, 0x3c030,
1198 0x3c100, 0x3c144,
1199 0x3c190, 0x3c1d0,
1200 0x3c200, 0x3c318,
1201 0x3c400, 0x3c52c,
1202 0x3c540, 0x3c61c,
1203 0x3c800, 0x3c834,
1204 0x3c8c0, 0x3c908,
1205 0x3c910, 0x3c9ac,
9f5ac48d 1206 0x3ca00, 0x3ca2c,
812034f1
HS		 1207 0x3ca44, 0x3ca50,
1208 0x3ca74, 0x3cc24,
9f5ac48d 1209 0x3cd00, 0x3cd00,
812034f1
HS		 1210 0x3cd08, 0x3cd14,
1211 0x3cd1c, 0x3cd20,
1212 0x3cd3c, 0x3cd50,
1213 0x3d200, 0x3d20c,
1214 0x3d220, 0x3d220,
1215 0x3d240, 0x3d240,
9f5ac48d 1216 0x3d600, 0x3d60c,
812034f1 1217 0x3da00, 0x3da1c,
9f5ac48d 1218 0x3de00, 0x3de20,
812034f1
HS		 1219 0x3de38, 0x3de3c,
1220 0x3de80, 0x3de80,
1221 0x3de88, 0x3dea8,
1222 0x3deb0, 0x3deb4,
1223 0x3dec8, 0x3ded4,
1224 0x3dfb8, 0x3e004,
9f5ac48d
HS		 1225 0x3e200, 0x3e200,
1226 0x3e208, 0x3e240,
1227 0x3e248, 0x3e280,
1228 0x3e288, 0x3e2c0,
1229 0x3e2c8, 0x3e2fc,
812034f1
HS		 1230 0x3e600, 0x3e630,
1231 0x3ea00, 0x3eabc,
1232 0x3eb00, 0x3eb70,
1233 0x3f000, 0x3f048,
1234 0x3f060, 0x3f09c,
1235 0x3f0f0, 0x3f148,
1236 0x3f160, 0x3f19c,
1237 0x3f1f0, 0x3f2e4,
1238 0x3f2f8, 0x3f3e4,
1239 0x3f3f8, 0x3f448,
1240 0x3f460, 0x3f49c,
1241 0x3f4f0, 0x3f548,
1242 0x3f560, 0x3f59c,
1243 0x3f5f0, 0x3f6e4,
1244 0x3f6f8, 0x3f7e4,
1245 0x3f7f8, 0x3f7fc,
1246 0x3f814, 0x3f814,
1247 0x3f82c, 0x3f82c,
1248 0x3f880, 0x3f88c,
1249 0x3f8e8, 0x3f8ec,
1250 0x3f900, 0x3f948,
1251 0x3f960, 0x3f99c,
1252 0x3f9f0, 0x3fae4,
1253 0x3faf8, 0x3fb10,
1254 0x3fb28, 0x3fb28,
1255 0x3fb3c, 0x3fb50,
1256 0x3fbf0, 0x3fc10,
1257 0x3fc28, 0x3fc28,
1258 0x3fc3c, 0x3fc50,
1259 0x3fcf0, 0x3fcfc,
1260 0x40000, 0x4000c,
1261 0x40040, 0x40068,
9f5ac48d 1262 0x4007c, 0x40144,
812034f1
HS		 1263 0x40180, 0x4018c,
1264 0x40200, 0x40298,
1265 0x402ac, 0x4033c,
1266 0x403f8, 0x403fc,
1267 0x41304, 0x413c4,
1268 0x41400, 0x4141c,
1269 0x41480, 0x414d0,
1270 0x44000, 0x44078,
1271 0x440c0, 0x44278,
1272 0x442c0, 0x44478,
1273 0x444c0, 0x44678,
1274 0x446c0, 0x44878,
1275 0x448c0, 0x449fc,
1276 0x45000, 0x45068,
1277 0x45080, 0x45084,
1278 0x450a0, 0x450b0,
1279 0x45200, 0x45268,
1280 0x45280, 0x45284,
1281 0x452a0, 0x452b0,
1282 0x460c0, 0x460e4,
1283 0x47000, 0x4708c,
1284 0x47200, 0x47250,
1285 0x47400, 0x47420,
1286 0x47600, 0x47618,
1287 0x47800, 0x47814,
1288 0x48000, 0x4800c,
1289 0x48040, 0x48068,
9f5ac48d 1290 0x4807c, 0x48144,
812034f1
HS		 1291 0x48180, 0x4818c,
1292 0x48200, 0x48298,
1293 0x482ac, 0x4833c,
1294 0x483f8, 0x483fc,
1295 0x49304, 0x493c4,
1296 0x49400, 0x4941c,
1297 0x49480, 0x494d0,
1298 0x4c000, 0x4c078,
1299 0x4c0c0, 0x4c278,
1300 0x4c2c0, 0x4c478,
1301 0x4c4c0, 0x4c678,
1302 0x4c6c0, 0x4c878,
1303 0x4c8c0, 0x4c9fc,
1304 0x4d000, 0x4d068,
1305 0x4d080, 0x4d084,
1306 0x4d0a0, 0x4d0b0,
1307 0x4d200, 0x4d268,
1308 0x4d280, 0x4d284,
1309 0x4d2a0, 0x4d2b0,
1310 0x4e0c0, 0x4e0e4,
1311 0x4f000, 0x4f08c,
1312 0x4f200, 0x4f250,
1313 0x4f400, 0x4f420,
1314 0x4f600, 0x4f618,
1315 0x4f800, 0x4f814,
1316 0x50000, 0x500cc,
1317 0x50400, 0x50400,
1318 0x50800, 0x508cc,
1319 0x50c00, 0x50c00,
1320 0x51000, 0x5101c,
1321 0x51300, 0x51308,
1322 };
1323
ab4b583b
HS		 1324 static const unsigned int t6_reg_ranges[] = {
1325 0x1008, 0x114c,
1326 0x1180, 0x11b4,
1327 0x11fc, 0x1250,
1328 0x1280, 0x133c,
1329 0x1800, 0x18fc,
1330 0x3000, 0x302c,
1331 0x3060, 0x30d8,
1332 0x30e0, 0x30fc,
1333 0x3140, 0x357c,
1334 0x35a8, 0x35cc,
1335 0x35ec, 0x35ec,
1336 0x3600, 0x5624,
1337 0x56cc, 0x575c,
1338 0x580c, 0x5814,
1339 0x5890, 0x58bc,
1340 0x5940, 0x595c,
1341 0x5980, 0x598c,
1342 0x59b0, 0x59dc,
1343 0x59fc, 0x5a18,
1344 0x5a60, 0x5a6c,
1345 0x5a80, 0x5a9c,
1346 0x5b94, 0x5bfc,
1347 0x5c10, 0x5ec0,
5b4e83e1 1348 0x5ec8, 0x5ecc,
ab4b583b 1349 0x6000, 0x6040,
5b4e83e1 1350 0x6058, 0x615c,
ab4b583b
HS		 1351 0x7700, 0x7798,
1352 0x77c0, 0x7880,
1353 0x78cc, 0x78fc,
1354 0x7b00, 0x7c54,
1355 0x7d00, 0x7efc,
1356 0x8dc0, 0x8de0,
1357 0x8df8, 0x8e84,
1358 0x8ea0, 0x8f88,
1359 0x8fb8, 0x911c,
1360 0x9400, 0x9470,
1361 0x9600, 0x971c,
1362 0x9800, 0x9808,
1363 0x9820, 0x983c,
1364 0x9850, 0x9864,
1365 0x9c00, 0x9c6c,
1366 0x9c80, 0x9cec,
1367 0x9d00, 0x9d6c,
1368 0x9d80, 0x9dec,
1369 0x9e00, 0x9e6c,
1370 0x9e80, 0x9eec,
1371 0x9f00, 0x9f6c,
1372 0x9f80, 0xa020,
1373 0xd004, 0xd03c,
5b4e83e1
HS		 1374 0xd100, 0xd118,
1375 0xd200, 0xd31c,
ab4b583b
HS		 1376 0xdfc0, 0xdfe0,
1377 0xe000, 0xf008,
1378 0x11000, 0x11014,
1379 0x11048, 0x11110,
1380 0x11118, 0x1117c,
5b4e83e1 1381 0x11190, 0x11264,
ab4b583b 1382 0x11300, 0x1130c,
5b4e83e1 1383 0x12000, 0x1206c,
ab4b583b
HS		 1384 0x19040, 0x1906c,
1385 0x19078, 0x19080,
1386 0x1908c, 0x19124,
1387 0x19150, 0x191b0,
1388 0x191d0, 0x191e8,
5b4e83e1 1389 0x19238, 0x192bc,
ab4b583b
HS		 1390 0x193f8, 0x19474,
1391 0x19490, 0x194cc,
1392 0x194f0, 0x194f8,
1393 0x19c00, 0x19c80,
1394 0x19c94, 0x19cbc,
1395 0x19ce4, 0x19d28,
1396 0x19d50, 0x19d78,
1397 0x19d94, 0x19dc8,
1398 0x19df0, 0x19e10,
1399 0x19e50, 0x19e6c,
1400 0x19ea0, 0x19f34,
1401 0x19f40, 0x19f50,
1402 0x19f90, 0x19fac,
1403 0x19fc4, 0x19fe4,
1404 0x1a000, 0x1a06c,
1405 0x1a0b0, 0x1a120,
1406 0x1a128, 0x1a138,
1407 0x1a190, 0x1a1c4,
1408 0x1a1fc, 0x1a1fc,
1409 0x1e008, 0x1e00c,
1410 0x1e040, 0x1e04c,
1411 0x1e284, 0x1e290,
1412 0x1e2c0, 0x1e2c0,
1413 0x1e2e0, 0x1e2e0,
1414 0x1e300, 0x1e384,
1415 0x1e3c0, 0x1e3c8,
1416 0x1e408, 0x1e40c,
1417 0x1e440, 0x1e44c,
1418 0x1e684, 0x1e690,
1419 0x1e6c0, 0x1e6c0,
1420 0x1e6e0, 0x1e6e0,
1421 0x1e700, 0x1e784,
1422 0x1e7c0, 0x1e7c8,
1423 0x1e808, 0x1e80c,
1424 0x1e840, 0x1e84c,
1425 0x1ea84, 0x1ea90,
1426 0x1eac0, 0x1eac0,
1427 0x1eae0, 0x1eae0,
1428 0x1eb00, 0x1eb84,
1429 0x1ebc0, 0x1ebc8,
1430 0x1ec08, 0x1ec0c,
1431 0x1ec40, 0x1ec4c,
1432 0x1ee84, 0x1ee90,
1433 0x1eec0, 0x1eec0,
1434 0x1eee0, 0x1eee0,
1435 0x1ef00, 0x1ef84,
1436 0x1efc0, 0x1efc8,
1437 0x1f008, 0x1f00c,
1438 0x1f040, 0x1f04c,
1439 0x1f284, 0x1f290,
1440 0x1f2c0, 0x1f2c0,
1441 0x1f2e0, 0x1f2e0,
1442 0x1f300, 0x1f384,
1443 0x1f3c0, 0x1f3c8,
1444 0x1f408, 0x1f40c,
1445 0x1f440, 0x1f44c,
1446 0x1f684, 0x1f690,
1447 0x1f6c0, 0x1f6c0,
1448 0x1f6e0, 0x1f6e0,
1449 0x1f700, 0x1f784,
1450 0x1f7c0, 0x1f7c8,
1451 0x1f808, 0x1f80c,
1452 0x1f840, 0x1f84c,
1453 0x1fa84, 0x1fa90,
1454 0x1fac0, 0x1fac0,
1455 0x1fae0, 0x1fae0,
1456 0x1fb00, 0x1fb84,
1457 0x1fbc0, 0x1fbc8,
1458 0x1fc08, 0x1fc0c,
1459 0x1fc40, 0x1fc4c,
1460 0x1fe84, 0x1fe90,
1461 0x1fec0, 0x1fec0,
1462 0x1fee0, 0x1fee0,
1463 0x1ff00, 0x1ff84,
1464 0x1ffc0, 0x1ffc8,
1465 0x30000, 0x30070,
1466 0x30100, 0x3015c,
1467 0x30190, 0x301d0,
1468 0x30200, 0x30318,
1469 0x30400, 0x3052c,
1470 0x30540, 0x3061c,
5b4e83e1 1471 0x30800, 0x30890,
ab4b583b
HS		 1472 0x308c0, 0x30908,
1473 0x30910, 0x309b8,
1474 0x30a00, 0x30a04,
1475 0x30a0c, 0x30a2c,
1476 0x30a44, 0x30a50,
1477 0x30a74, 0x30c24,
1478 0x30d00, 0x30d3c,
1479 0x30d44, 0x30d7c,
1480 0x30de0, 0x30de0,
1481 0x30e00, 0x30ed4,
1482 0x30f00, 0x30fa4,
1483 0x30fc0, 0x30fc4,
1484 0x31000, 0x31004,
1485 0x31080, 0x310fc,
1486 0x31208, 0x31220,
1487 0x3123c, 0x31254,
1488 0x31300, 0x31300,
1489 0x31308, 0x3131c,
1490 0x31338, 0x3133c,
1491 0x31380, 0x31380,
1492 0x31388, 0x313a8,
1493 0x313b4, 0x313b4,
1494 0x31400, 0x31420,
1495 0x31438, 0x3143c,
1496 0x31480, 0x31480,
1497 0x314a8, 0x314a8,
1498 0x314b0, 0x314b4,
1499 0x314c8, 0x314d4,
1500 0x31a40, 0x31a4c,
1501 0x31af0, 0x31b20,
1502 0x31b38, 0x31b3c,
1503 0x31b80, 0x31b80,
1504 0x31ba8, 0x31ba8,
1505 0x31bb0, 0x31bb4,
1506 0x31bc8, 0x31bd4,
1507 0x32140, 0x3218c,
1508 0x321f0, 0x32200,
1509 0x32218, 0x32218,
1510 0x32400, 0x32400,
1511 0x32408, 0x3241c,
1512 0x32618, 0x32620,
1513 0x32664, 0x32664,
1514 0x326a8, 0x326a8,
1515 0x326ec, 0x326ec,
1516 0x32a00, 0x32abc,
1517 0x32b00, 0x32b78,
1518 0x32c00, 0x32c00,
1519 0x32c08, 0x32c3c,
1520 0x32e00, 0x32e2c,
1521 0x32f00, 0x32f2c,
1522 0x33000, 0x330ac,
1523 0x330c0, 0x331ac,
1524 0x331c0, 0x332c4,
1525 0x332e4, 0x333c4,
1526 0x333e4, 0x334ac,
1527 0x334c0, 0x335ac,
1528 0x335c0, 0x336c4,
1529 0x336e4, 0x337c4,
1530 0x337e4, 0x337fc,
1531 0x33814, 0x33814,
1532 0x33854, 0x33868,
1533 0x33880, 0x3388c,
1534 0x338c0, 0x338d0,
1535 0x338e8, 0x338ec,
1536 0x33900, 0x339ac,
1537 0x339c0, 0x33ac4,
1538 0x33ae4, 0x33b10,
1539 0x33b24, 0x33b50,
1540 0x33bf0, 0x33c10,
1541 0x33c24, 0x33c50,
1542 0x33cf0, 0x33cfc,
1543 0x34000, 0x34070,
1544 0x34100, 0x3415c,
1545 0x34190, 0x341d0,
1546 0x34200, 0x34318,
1547 0x34400, 0x3452c,
1548 0x34540, 0x3461c,
5b4e83e1 1549 0x34800, 0x34890,
ab4b583b
HS		 1550 0x348c0, 0x34908,
1551 0x34910, 0x349b8,
1552 0x34a00, 0x34a04,
1553 0x34a0c, 0x34a2c,
1554 0x34a44, 0x34a50,
1555 0x34a74, 0x34c24,
1556 0x34d00, 0x34d3c,
1557 0x34d44, 0x34d7c,
1558 0x34de0, 0x34de0,
1559 0x34e00, 0x34ed4,
1560 0x34f00, 0x34fa4,
1561 0x34fc0, 0x34fc4,
1562 0x35000, 0x35004,
1563 0x35080, 0x350fc,
1564 0x35208, 0x35220,
1565 0x3523c, 0x35254,
1566 0x35300, 0x35300,
1567 0x35308, 0x3531c,
1568 0x35338, 0x3533c,
1569 0x35380, 0x35380,
1570 0x35388, 0x353a8,
1571 0x353b4, 0x353b4,
1572 0x35400, 0x35420,
1573 0x35438, 0x3543c,
1574 0x35480, 0x35480,
1575 0x354a8, 0x354a8,
1576 0x354b0, 0x354b4,
1577 0x354c8, 0x354d4,
1578 0x35a40, 0x35a4c,
1579 0x35af0, 0x35b20,
1580 0x35b38, 0x35b3c,
1581 0x35b80, 0x35b80,
1582 0x35ba8, 0x35ba8,
1583 0x35bb0, 0x35bb4,
1584 0x35bc8, 0x35bd4,
1585 0x36140, 0x3618c,
1586 0x361f0, 0x36200,
1587 0x36218, 0x36218,
1588 0x36400, 0x36400,
1589 0x36408, 0x3641c,
1590 0x36618, 0x36620,
1591 0x36664, 0x36664,
1592 0x366a8, 0x366a8,
1593 0x366ec, 0x366ec,
1594 0x36a00, 0x36abc,
1595 0x36b00, 0x36b78,
1596 0x36c00, 0x36c00,
1597 0x36c08, 0x36c3c,
1598 0x36e00, 0x36e2c,
1599 0x36f00, 0x36f2c,
1600 0x37000, 0x370ac,
1601 0x370c0, 0x371ac,
1602 0x371c0, 0x372c4,
1603 0x372e4, 0x373c4,
1604 0x373e4, 0x374ac,
1605 0x374c0, 0x375ac,
1606 0x375c0, 0x376c4,
1607 0x376e4, 0x377c4,
1608 0x377e4, 0x377fc,
1609 0x37814, 0x37814,
1610 0x37854, 0x37868,
1611 0x37880, 0x3788c,
1612 0x378c0, 0x378d0,
1613 0x378e8, 0x378ec,
1614 0x37900, 0x379ac,
1615 0x379c0, 0x37ac4,
1616 0x37ae4, 0x37b10,
1617 0x37b24, 0x37b50,
1618 0x37bf0, 0x37c10,
1619 0x37c24, 0x37c50,
1620 0x37cf0, 0x37cfc,
1621 0x40040, 0x40040,
1622 0x40080, 0x40084,
1623 0x40100, 0x40100,
1624 0x40140, 0x401bc,
1625 0x40200, 0x40214,
1626 0x40228, 0x40228,
1627 0x40240, 0x40258,
1628 0x40280, 0x40280,
1629 0x40304, 0x40304,
1630 0x40330, 0x4033c,
1631 0x41304, 0x413dc,
1632 0x41400, 0x4141c,
1633 0x41480, 0x414d0,
1634 0x44000, 0x4407c,
1635 0x440c0, 0x4427c,
1636 0x442c0, 0x4447c,
1637 0x444c0, 0x4467c,
1638 0x446c0, 0x4487c,
1639 0x448c0, 0x44a7c,
1640 0x44ac0, 0x44c7c,
1641 0x44cc0, 0x44e7c,
1642 0x44ec0, 0x4507c,
1643 0x450c0, 0x451fc,
1644 0x45800, 0x45868,
1645 0x45880, 0x45884,
1646 0x458a0, 0x458b0,
1647 0x45a00, 0x45a68,
1648 0x45a80, 0x45a84,
1649 0x45aa0, 0x45ab0,
1650 0x460c0, 0x460e4,
1651 0x47000, 0x4708c,
1652 0x47200, 0x47250,
1653 0x47400, 0x47420,
1654 0x47600, 0x47618,
1655 0x47800, 0x4782c,
1656 0x50000, 0x500cc,
1657 0x50400, 0x50400,
1658 0x50800, 0x508cc,
1659 0x50c00, 0x50c00,
1660 0x51000, 0x510b0,
1661 0x51300, 0x51324,
1662 };
1663
812034f1
HS		 1664 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1665 const unsigned int *reg_ranges;
1666 int reg_ranges_size, range;
1667 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1668
1669 /* Select the right set of register ranges to dump depending on the
1670 * adapter chip type.
1671 */
1672 switch (chip_version) {
1673 case CHELSIO_T4:
1674 reg_ranges = t4_reg_ranges;
1675 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
1676 break;
1677
1678 case CHELSIO_T5:
1679 reg_ranges = t5_reg_ranges;
1680 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1681 break;
1682
ab4b583b
HS		 1683 case CHELSIO_T6:
1684 reg_ranges = t6_reg_ranges;
1685 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1686 break;
1687
812034f1
HS		 1688 default:
1689 dev_err(adap->pdev_dev,
1690 "Unsupported chip version %d\n", chip_version);
1691 return;
1692 }
1693
1694 /* Clear the register buffer and insert the appropriate register
1695 * values selected by the above register ranges.
1696 */
1697 memset(buf, 0, buf_size);
1698 for (range = 0; range < reg_ranges_size; range += 2) {
1699 unsigned int reg = reg_ranges[range];
1700 unsigned int last_reg = reg_ranges[range + 1];
1701 u32 *bufp = (u32 *)((char *)buf + reg);
1702
1703 /* Iterate across the register range filling in the register
1704 * buffer but don't write past the end of the register buffer.
1705 */
1706 while (reg <= last_reg && bufp < buf_end) {
1707 *bufp++ = t4_read_reg(adap, reg);
1708 reg += sizeof(u32);
1709 }
1710 }
1711}
1712
56d36be4 1713#define EEPROM_STAT_ADDR 0x7bfc
47ce9c48
SR		 1714#define VPD_BASE 0x400
1715#define VPD_BASE_OLD 0
0a57a536 1716#define VPD_LEN 1024
63a92fe6 1717#define CHELSIO_VPD_UNIQUE_ID 0x82
56d36be4
DM		 1718
1719/**
1720 * t4_seeprom_wp - enable/disable EEPROM write protection
1721 * @adapter: the adapter
1722 * @enable: whether to enable or disable write protection
1723 *
1724 * Enables or disables write protection on the serial EEPROM.
1725 */
1726int t4_seeprom_wp(struct adapter *adapter, bool enable)
1727{
1728 unsigned int v = enable ? 0xc : 0;
1729 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
1730 return ret < 0 ? ret : 0;
1731}
1732
1733/**
098ef6c2 1734 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
56d36be4
DM		 1735 * @adapter: adapter to read
1736 * @p: where to store the parameters
1737 *
1738 * Reads card parameters stored in VPD EEPROM.
1739 */
098ef6c2 1740int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
56d36be4 1741{
098ef6c2
HS		 1742 int i, ret = 0, addr;
1743 int ec, sn, pn, na;
8c357ebd 1744 u8 *vpd, csum;
23d88e1d 1745 unsigned int vpdr_len, kw_offset, id_len;
56d36be4 1746
8c357ebd
VP		 1747 vpd = vmalloc(VPD_LEN);
1748 if (!vpd)
1749 return -ENOMEM;
1750
098ef6c2
HS		 1751 /* Card information normally starts at VPD_BASE but early cards had
1752 * it at 0.
1753 */
47ce9c48
SR		 1754 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
1755 if (ret < 0)
1756 goto out;
63a92fe6
HS		 1757
1758 /* The VPD shall have a unique identifier specified by the PCI SIG.
1759 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
1760 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
1761 * is expected to automatically put this entry at the
1762 * beginning of the VPD.
1763 */
1764 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
47ce9c48
SR		 1765
1766 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
56d36be4 1767 if (ret < 0)
8c357ebd 1768 goto out;
56d36be4 1769
23d88e1d
DM		 1770 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
1771 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
8c357ebd
VP		 1772 ret = -EINVAL;
1773 goto out;
23d88e1d
DM		 1774 }
1775
1776 id_len = pci_vpd_lrdt_size(vpd);
1777 if (id_len > ID_LEN)
1778 id_len = ID_LEN;
1779
1780 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
1781 if (i < 0) {
1782 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
8c357ebd
VP		 1783 ret = -EINVAL;
1784 goto out;
23d88e1d
DM		 1785 }
1786
1787 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
1788 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
1789 if (vpdr_len + kw_offset > VPD_LEN) {
226ec5fd 1790 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
8c357ebd
VP		 1791 ret = -EINVAL;
1792 goto out;
226ec5fd
DM		 1793 }
1794
1795#define FIND_VPD_KW(var, name) do { \
23d88e1d 1796 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
226ec5fd
DM		 1797 if (var < 0) { \
1798 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
8c357ebd
VP		 1799 ret = -EINVAL; \
1800 goto out; \
226ec5fd
DM		 1801 } \
1802 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
1803} while (0)
1804
1805 FIND_VPD_KW(i, "RV");
1806 for (csum = 0; i >= 0; i--)
1807 csum += vpd[i];
56d36be4
DM		 1808
1809 if (csum) {
1810 dev_err(adapter->pdev_dev,
1811 "corrupted VPD EEPROM, actual csum %u\n", csum);
8c357ebd
VP		 1812 ret = -EINVAL;
1813 goto out;
56d36be4
DM		 1814 }
1815
226ec5fd
DM		 1816 FIND_VPD_KW(ec, "EC");
1817 FIND_VPD_KW(sn, "SN");
a94cd705 1818 FIND_VPD_KW(pn, "PN");
098ef6c2 1819 FIND_VPD_KW(na, "NA");
226ec5fd
DM		 1820#undef FIND_VPD_KW
1821
23d88e1d 1822 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
56d36be4 1823 strim(p->id);
226ec5fd 1824 memcpy(p->ec, vpd + ec, EC_LEN);
56d36be4 1825 strim(p->ec);
226ec5fd
DM		 1826 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
1827 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
56d36be4 1828 strim(p->sn);
63a92fe6 1829 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
a94cd705
KS		 1830 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
1831 strim(p->pn);
098ef6c2
HS		 1832 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
1833 strim((char *)p->na);
636f9d37 1834
098ef6c2
HS		 1835out:
1836 vfree(vpd);
1837 return ret;
1838}
1839
1840/**
1841 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
1842 * @adapter: adapter to read
1843 * @p: where to store the parameters
1844 *
1845 * Reads card parameters stored in VPD EEPROM and retrieves the Core
1846 * Clock. This can only be called after a connection to the firmware
1847 * is established.
1848 */
1849int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
1850{
1851 u32 cclk_param, cclk_val;
1852 int ret;
1853
1854 /* Grab the raw VPD parameters.
1855 */
1856 ret = t4_get_raw_vpd_params(adapter, p);
1857 if (ret)
1858 return ret;
1859
1860 /* Ask firmware for the Core Clock since it knows how to translate the
636f9d37
VP		 1861 * Reference Clock ('V2') VPD field into a Core Clock value ...
1862 */
5167865a
HS		 1863 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1864 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
098ef6c2 1865 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
636f9d37 1866 1, &cclk_param, &cclk_val);
8c357ebd 1867
636f9d37
VP		 1868 if (ret)
1869 return ret;
1870 p->cclk = cclk_val;
1871
56d36be4
DM		 1872 return 0;
1873}
1874
1875/* serial flash and firmware constants */
1876enum {
1877 SF_ATTEMPTS = 10, /* max retries for SF operations */
1878
1879 /* flash command opcodes */
1880 SF_PROG_PAGE = 2, /* program page */
1881 SF_WR_DISABLE = 4, /* disable writes */
1882 SF_RD_STATUS = 5, /* read status register */
1883 SF_WR_ENABLE = 6, /* enable writes */
1884 SF_RD_DATA_FAST = 0xb, /* read flash */
900a6596 1885 SF_RD_ID = 0x9f, /* read ID */
56d36be4
DM		 1886 SF_ERASE_SECTOR = 0xd8, /* erase sector */
1887
6f1d7210 1888 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
56d36be4
DM		 1889};
1890
1891/**
1892 * sf1_read - read data from the serial flash
1893 * @adapter: the adapter
1894 * @byte_cnt: number of bytes to read
1895 * @cont: whether another operation will be chained
1896 * @lock: whether to lock SF for PL access only
1897 * @valp: where to store the read data
1898 *
1899 * Reads up to 4 bytes of data from the serial flash. The location of
1900 * the read needs to be specified prior to calling this by issuing the
1901 * appropriate commands to the serial flash.
1902 */
1903static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1904 int lock, u32 *valp)
1905{
1906 int ret;
1907
1908 if (!byte_cnt || byte_cnt > 4)
1909 return -EINVAL;
0d804338 1910 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
56d36be4 1911 return -EBUSY;
0d804338
HS		 1912 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
1913 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
1914 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
56d36be4 1915 if (!ret)
0d804338 1916 *valp = t4_read_reg(adapter, SF_DATA_A);
56d36be4
DM		 1917 return ret;
1918}
1919
1920/**
1921 * sf1_write - write data to the serial flash
1922 * @adapter: the adapter
1923 * @byte_cnt: number of bytes to write
1924 * @cont: whether another operation will be chained
1925 * @lock: whether to lock SF for PL access only
1926 * @val: value to write
1927 *
1928 * Writes up to 4 bytes of data to the serial flash. The location of
1929 * the write needs to be specified prior to calling this by issuing the
1930 * appropriate commands to the serial flash.
1931 */
1932static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1933 int lock, u32 val)
1934{
1935 if (!byte_cnt || byte_cnt > 4)
1936 return -EINVAL;
0d804338 1937 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
56d36be4 1938 return -EBUSY;
0d804338
HS		 1939 t4_write_reg(adapter, SF_DATA_A, val);
1940 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
1941 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
1942 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
56d36be4
DM		 1943}
1944
1945/**
1946 * flash_wait_op - wait for a flash operation to complete
1947 * @adapter: the adapter
1948 * @attempts: max number of polls of the status register
1949 * @delay: delay between polls in ms
1950 *
1951 * Wait for a flash operation to complete by polling the status register.
1952 */
1953static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
1954{
1955 int ret;
1956 u32 status;
1957
1958 while (1) {
1959 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
1960 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
1961 return ret;
1962 if (!(status & 1))
1963 return 0;
1964 if (--attempts == 0)
1965 return -EAGAIN;
1966 if (delay)
1967 msleep(delay);
1968 }
1969}
1970
1971/**
1972 * t4_read_flash - read words from serial flash
1973 * @adapter: the adapter
1974 * @addr: the start address for the read
1975 * @nwords: how many 32-bit words to read
1976 * @data: where to store the read data
1977 * @byte_oriented: whether to store data as bytes or as words
1978 *
1979 * Read the specified number of 32-bit words from the serial flash.
1980 * If @byte_oriented is set the read data is stored as a byte array
1981 * (i.e., big-endian), otherwise as 32-bit words in the platform's
dbedd44e 1982 * natural endianness.
56d36be4 1983 */
49216c1c
HS		 1984int t4_read_flash(struct adapter *adapter, unsigned int addr,
1985 unsigned int nwords, u32 *data, int byte_oriented)
56d36be4
DM		 1986{
1987 int ret;
1988
900a6596 1989 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
56d36be4
DM		 1990 return -EINVAL;
1991
1992 addr = swab32(addr) | SF_RD_DATA_FAST;
1993
1994 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
1995 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
1996 return ret;
1997
1998 for ( ; nwords; nwords--, data++) {
1999 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2000 if (nwords == 1)
0d804338 2001 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM		 2002 if (ret)
2003 return ret;
2004 if (byte_oriented)
f404f80c 2005 *data = (__force __u32)(cpu_to_be32(*data));
56d36be4
DM		 2006 }
2007 return 0;
2008}
2009
2010/**
2011 * t4_write_flash - write up to a page of data to the serial flash
2012 * @adapter: the adapter
2013 * @addr: the start address to write
2014 * @n: length of data to write in bytes
2015 * @data: the data to write
2016 *
2017 * Writes up to a page of data (256 bytes) to the serial flash starting
2018 * at the given address. All the data must be written to the same page.
2019 */
2020static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2021 unsigned int n, const u8 *data)
2022{
2023 int ret;
2024 u32 buf[64];
2025 unsigned int i, c, left, val, offset = addr & 0xff;
2026
900a6596 2027 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
56d36be4
DM		 2028 return -EINVAL;
2029
2030 val = swab32(addr) | SF_PROG_PAGE;
2031
2032 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2033 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2034 goto unlock;
2035
2036 for (left = n; left; left -= c) {
2037 c = min(left, 4U);
2038 for (val = 0, i = 0; i < c; ++i)
2039 val = (val << 8) + *data++;
2040
2041 ret = sf1_write(adapter, c, c != left, 1, val);
2042 if (ret)
2043 goto unlock;
2044 }
900a6596 2045 ret = flash_wait_op(adapter, 8, 1);
56d36be4
DM		 2046 if (ret)
2047 goto unlock;
2048
0d804338 2049 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM		 2050
2051 /* Read the page to verify the write succeeded */
2052 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2053 if (ret)
2054 return ret;
2055
2056 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2057 dev_err(adapter->pdev_dev,
2058 "failed to correctly write the flash page at %#x\n",
2059 addr);
2060 return -EIO;
2061 }
2062 return 0;
2063
2064unlock:
0d804338 2065 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM		 2066 return ret;
2067}
2068
2069/**
16e47624 2070 * t4_get_fw_version - read the firmware version
56d36be4
DM		 2071 * @adapter: the adapter
2072 * @vers: where to place the version
2073 *
2074 * Reads the FW version from flash.
2075 */
16e47624 2076int t4_get_fw_version(struct adapter *adapter, u32 *vers)
56d36be4 2077{
16e47624
HS		 2078 return t4_read_flash(adapter, FLASH_FW_START +
2079 offsetof(struct fw_hdr, fw_ver), 1,
2080 vers, 0);
56d36be4
DM		 2081}
2082
2083/**
16e47624 2084 * t4_get_tp_version - read the TP microcode version
56d36be4
DM		 2085 * @adapter: the adapter
2086 * @vers: where to place the version
2087 *
2088 * Reads the TP microcode version from flash.
2089 */
16e47624 2090int t4_get_tp_version(struct adapter *adapter, u32 *vers)
56d36be4 2091{
16e47624 2092 return t4_read_flash(adapter, FLASH_FW_START +
900a6596 2093 offsetof(struct fw_hdr, tp_microcode_ver),
56d36be4
DM		 2094 1, vers, 0);
2095}
2096
ba3f8cd5
HS		 2097/**
2098 * t4_get_exprom_version - return the Expansion ROM version (if any)
2099 * @adapter: the adapter
2100 * @vers: where to place the version
2101 *
2102 * Reads the Expansion ROM header from FLASH and returns the version
2103 * number (if present) through the @vers return value pointer. We return
2104 * this in the Firmware Version Format since it's convenient. Return
2105 * 0 on success, -ENOENT if no Expansion ROM is present.
2106 */
2107int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2108{
2109 struct exprom_header {
2110 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2111 unsigned char hdr_ver[4]; /* Expansion ROM version */
2112 } *hdr;
2113 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2114 sizeof(u32))];
2115 int ret;
2116
2117 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2118 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2119 0);
2120 if (ret)
2121 return ret;
2122
2123 hdr = (struct exprom_header *)exprom_header_buf;
2124 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2125 return -ENOENT;
2126
2127 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2128 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2129 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2130 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2131 return 0;
2132}
2133
16e47624
HS		 2134/* Is the given firmware API compatible with the one the driver was compiled
2135 * with?
56d36be4 2136 */
16e47624 2137static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
56d36be4 2138{
56d36be4 2139
16e47624
HS		 2140 /* short circuit if it's the exact same firmware version */
2141 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2142 return 1;
56d36be4 2143
16e47624
HS		 2144#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2145 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2146 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
2147 return 1;
2148#undef SAME_INTF
0a57a536 2149
16e47624
HS		 2150 return 0;
2151}
56d36be4 2152
16e47624
HS		 2153/* The firmware in the filesystem is usable, but should it be installed?
2154 * This routine explains itself in detail if it indicates the filesystem
2155 * firmware should be installed.
2156 */
2157static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
2158 int k, int c)
2159{
2160 const char *reason;
2161
2162 if (!card_fw_usable) {
2163 reason = "incompatible or unusable";
2164 goto install;
e69972f5
JH		 2165 }
2166
16e47624
HS		 2167 if (k > c) {
2168 reason = "older than the version supported with this driver";
2169 goto install;
56d36be4
DM		 2170 }
2171
16e47624
HS		 2172 return 0;
2173
2174install:
2175 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
2176 "installing firmware %u.%u.%u.%u on card.\n",
b2e1a3f0
HS		 2177 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
2178 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
2179 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
2180 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
56d36be4 2181
56d36be4
DM		 2182 return 1;
2183}
2184
16e47624
HS		 2185int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
2186 const u8 *fw_data, unsigned int fw_size,
2187 struct fw_hdr *card_fw, enum dev_state state,
2188 int *reset)
2189{
2190 int ret, card_fw_usable, fs_fw_usable;
2191 const struct fw_hdr *fs_fw;
2192 const struct fw_hdr *drv_fw;
2193
2194 drv_fw = &fw_info->fw_hdr;
2195
2196 /* Read the header of the firmware on the card */
2197 ret = -t4_read_flash(adap, FLASH_FW_START,
2198 sizeof(*card_fw) / sizeof(uint32_t),
2199 (uint32_t *)card_fw, 1);
2200 if (ret == 0) {
2201 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
2202 } else {
2203 dev_err(adap->pdev_dev,
2204 "Unable to read card's firmware header: %d\n", ret);
2205 card_fw_usable = 0;
2206 }
2207
2208 if (fw_data != NULL) {
2209 fs_fw = (const void *)fw_data;
2210 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
2211 } else {
2212 fs_fw = NULL;
2213 fs_fw_usable = 0;
2214 }
2215
2216 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2217 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
2218 /* Common case: the firmware on the card is an exact match and
2219 * the filesystem one is an exact match too, or the filesystem
2220 * one is absent/incompatible.
2221 */
2222 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
2223 should_install_fs_fw(adap, card_fw_usable,
2224 be32_to_cpu(fs_fw->fw_ver),
2225 be32_to_cpu(card_fw->fw_ver))) {
2226 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
2227 fw_size, 0);
2228 if (ret != 0) {
2229 dev_err(adap->pdev_dev,
2230 "failed to install firmware: %d\n", ret);
2231 goto bye;
2232 }
2233
2234 /* Installed successfully, update the cached header too. */
e3d50738 2235 *card_fw = *fs_fw;
16e47624
HS		 2236 card_fw_usable = 1;
2237 *reset = 0; /* already reset as part of load_fw */
2238 }
2239
2240 if (!card_fw_usable) {
2241 uint32_t d, c, k;
2242
2243 d = be32_to_cpu(drv_fw->fw_ver);
2244 c = be32_to_cpu(card_fw->fw_ver);
2245 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
2246
2247 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
2248 "chip state %d, "
2249 "driver compiled with %d.%d.%d.%d, "
2250 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
2251 state,
b2e1a3f0
HS		 2252 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
2253 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
2254 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
2255 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
2256 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
2257 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
16e47624
HS		 2258 ret = EINVAL;
2259 goto bye;
2260 }
2261
2262 /* We're using whatever's on the card and it's known to be good. */
2263 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
2264 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
2265
2266bye:
2267 return ret;
2268}
2269
56d36be4
DM		 2270/**
2271 * t4_flash_erase_sectors - erase a range of flash sectors
2272 * @adapter: the adapter
2273 * @start: the first sector to erase
2274 * @end: the last sector to erase
2275 *
2276 * Erases the sectors in the given inclusive range.
2277 */
2278static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
2279{
2280 int ret = 0;
2281
c0d5b8cf
HS		 2282 if (end >= adapter->params.sf_nsec)
2283 return -EINVAL;
2284
56d36be4
DM		 2285 while (start <= end) {
2286 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2287 (ret = sf1_write(adapter, 4, 0, 1,
2288 SF_ERASE_SECTOR | (start << 8))) != 0 ||
900a6596 2289 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
56d36be4
DM		 2290 dev_err(adapter->pdev_dev,
2291 "erase of flash sector %d failed, error %d\n",
2292 start, ret);
2293 break;
2294 }
2295 start++;
2296 }
0d804338 2297 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM		 2298 return ret;
2299}
2300
636f9d37
VP		 2301/**
2302 * t4_flash_cfg_addr - return the address of the flash configuration file
2303 * @adapter: the adapter
2304 *
2305 * Return the address within the flash where the Firmware Configuration
2306 * File is stored.
2307 */
2308unsigned int t4_flash_cfg_addr(struct adapter *adapter)
2309{
2310 if (adapter->params.sf_size == 0x100000)
2311 return FLASH_FPGA_CFG_START;
2312 else
2313 return FLASH_CFG_START;
2314}
2315
79af221d
HS		 2316/* Return TRUE if the specified firmware matches the adapter. I.e. T4
2317 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
2318 * and emit an error message for mismatched firmware to save our caller the
2319 * effort ...
2320 */
2321static bool t4_fw_matches_chip(const struct adapter *adap,
2322 const struct fw_hdr *hdr)
2323{
2324 /* The expression below will return FALSE for any unsupported adapter
2325 * which will keep us "honest" in the future ...
2326 */
2327 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3ccc6cf7
HS		 2328 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
2329 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
79af221d
HS		 2330 return true;
2331
2332 dev_err(adap->pdev_dev,
2333 "FW image (%d) is not suitable for this adapter (%d)\n",
2334 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
2335 return false;
2336}
2337
56d36be4
DM		 2338/**
2339 * t4_load_fw - download firmware
2340 * @adap: the adapter
2341 * @fw_data: the firmware image to write
2342 * @size: image size
2343 *
2344 * Write the supplied firmware image to the card's serial flash.
2345 */
2346int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
2347{
2348 u32 csum;
2349 int ret, addr;
2350 unsigned int i;
2351 u8 first_page[SF_PAGE_SIZE];
404d9e3f 2352 const __be32 *p = (const __be32 *)fw_data;
56d36be4 2353 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
900a6596
DM		 2354 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
2355 unsigned int fw_img_start = adap->params.sf_fw_start;
2356 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
56d36be4
DM		 2357
2358 if (!size) {
2359 dev_err(adap->pdev_dev, "FW image has no data\n");
2360 return -EINVAL;
2361 }
2362 if (size & 511) {
2363 dev_err(adap->pdev_dev,
2364 "FW image size not multiple of 512 bytes\n");
2365 return -EINVAL;
2366 }
f404f80c 2367 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
56d36be4
DM		 2368 dev_err(adap->pdev_dev,
2369 "FW image size differs from size in FW header\n");
2370 return -EINVAL;
2371 }
2372 if (size > FW_MAX_SIZE) {
2373 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
2374 FW_MAX_SIZE);
2375 return -EFBIG;
2376 }
79af221d
HS		 2377 if (!t4_fw_matches_chip(adap, hdr))
2378 return -EINVAL;
56d36be4
DM		 2379
2380 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
f404f80c 2381 csum += be32_to_cpu(p[i]);
56d36be4
DM		 2382
2383 if (csum != 0xffffffff) {
2384 dev_err(adap->pdev_dev,
2385 "corrupted firmware image, checksum %#x\n", csum);
2386 return -EINVAL;
2387 }
2388
900a6596
DM		 2389 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
2390 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
56d36be4
DM		 2391 if (ret)
2392 goto out;
2393
2394 /*
2395 * We write the correct version at the end so the driver can see a bad
2396 * version if the FW write fails. Start by writing a copy of the
2397 * first page with a bad version.
2398 */
2399 memcpy(first_page, fw_data, SF_PAGE_SIZE);
f404f80c 2400 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
900a6596 2401 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
56d36be4
DM		 2402 if (ret)
2403 goto out;
2404
900a6596 2405 addr = fw_img_start;
56d36be4
DM		 2406 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
2407 addr += SF_PAGE_SIZE;
2408 fw_data += SF_PAGE_SIZE;
2409 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
2410 if (ret)
2411 goto out;
2412 }
2413
2414 ret = t4_write_flash(adap,
900a6596 2415 fw_img_start + offsetof(struct fw_hdr, fw_ver),
56d36be4
DM		 2416 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
2417out:
2418 if (ret)
2419 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
2420 ret);
dff04bce
HS		 2421 else
2422 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
56d36be4
DM		 2423 return ret;
2424}
2425
01b69614
HS		 2426/**
2427 * t4_phy_fw_ver - return current PHY firmware version
2428 * @adap: the adapter
2429 * @phy_fw_ver: return value buffer for PHY firmware version
2430 *
2431 * Returns the current version of external PHY firmware on the
2432 * adapter.
2433 */
2434int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
2435{
2436 u32 param, val;
2437 int ret;
2438
2439 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2440 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
2441 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
2442 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
b2612722 2443 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 2444 &param, &val);
2445 if (ret < 0)
2446 return ret;
2447 *phy_fw_ver = val;
2448 return 0;
2449}
2450
2451/**
2452 * t4_load_phy_fw - download port PHY firmware
2453 * @adap: the adapter
2454 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
2455 * @win_lock: the lock to use to guard the memory copy
2456 * @phy_fw_version: function to check PHY firmware versions
2457 * @phy_fw_data: the PHY firmware image to write
2458 * @phy_fw_size: image size
2459 *
2460 * Transfer the specified PHY firmware to the adapter. If a non-NULL
2461 * @phy_fw_version is supplied, then it will be used to determine if
2462 * it's necessary to perform the transfer by comparing the version
2463 * of any existing adapter PHY firmware with that of the passed in
2464 * PHY firmware image. If @win_lock is non-NULL then it will be used
2465 * around the call to t4_memory_rw() which transfers the PHY firmware
2466 * to the adapter.
2467 *
2468 * A negative error number will be returned if an error occurs. If
2469 * version number support is available and there's no need to upgrade
2470 * the firmware, 0 will be returned. If firmware is successfully
2471 * transferred to the adapter, 1 will be retured.
2472 *
2473 * NOTE: some adapters only have local RAM to store the PHY firmware. As
2474 * a result, a RESET of the adapter would cause that RAM to lose its
2475 * contents. Thus, loading PHY firmware on such adapters must happen
2476 * after any FW_RESET_CMDs ...
2477 */
2478int t4_load_phy_fw(struct adapter *adap,
2479 int win, spinlock_t *win_lock,
2480 int (*phy_fw_version)(const u8 *, size_t),
2481 const u8 *phy_fw_data, size_t phy_fw_size)
2482{
2483 unsigned long mtype = 0, maddr = 0;
2484 u32 param, val;
2485 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
2486 int ret;
2487
2488 /* If we have version number support, then check to see if the adapter
2489 * already has up-to-date PHY firmware loaded.
2490 */
2491 if (phy_fw_version) {
2492 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
2493 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
2494 if (ret < 0)
2495 return ret;
2496
2497 if (cur_phy_fw_ver >= new_phy_fw_vers) {
2498 CH_WARN(adap, "PHY Firmware already up-to-date, "
2499 "version %#x\n", cur_phy_fw_ver);
2500 return 0;
2501 }
2502 }
2503
2504 /* Ask the firmware where it wants us to copy the PHY firmware image.
2505 * The size of the file requires a special version of the READ coommand
2506 * which will pass the file size via the values field in PARAMS_CMD and
2507 * retrieve the return value from firmware and place it in the same
2508 * buffer values
2509 */
2510 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2511 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
2512 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
2513 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
2514 val = phy_fw_size;
b2612722 2515 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 2516 &param, &val, 1);
2517 if (ret < 0)
2518 return ret;
2519 mtype = val >> 8;
2520 maddr = (val & 0xff) << 16;
2521
2522 /* Copy the supplied PHY Firmware image to the adapter memory location
2523 * allocated by the adapter firmware.
2524 */
2525 if (win_lock)
2526 spin_lock_bh(win_lock);
2527 ret = t4_memory_rw(adap, win, mtype, maddr,
2528 phy_fw_size, (__be32 *)phy_fw_data,
2529 T4_MEMORY_WRITE);
2530 if (win_lock)
2531 spin_unlock_bh(win_lock);
2532 if (ret)
2533 return ret;
2534
2535 /* Tell the firmware that the PHY firmware image has been written to
2536 * RAM and it can now start copying it over to the PHYs. The chip
2537 * firmware will RESET the affected PHYs as part of this operation
2538 * leaving them running the new PHY firmware image.
2539 */
2540 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2541 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
2542 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
2543 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
b2612722 2544 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 2545 &param, &val, 30000);
2546
2547 /* If we have version number support, then check to see that the new
2548 * firmware got loaded properly.
2549 */
2550 if (phy_fw_version) {
2551 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
2552 if (ret < 0)
2553 return ret;
2554
2555 if (cur_phy_fw_ver != new_phy_fw_vers) {
2556 CH_WARN(adap, "PHY Firmware did not update: "
2557 "version on adapter %#x, "
2558 "version flashed %#x\n",
2559 cur_phy_fw_ver, new_phy_fw_vers);
2560 return -ENXIO;
2561 }
2562 }
2563
2564 return 1;
2565}
2566
49216c1c
HS		 2567/**
2568 * t4_fwcache - firmware cache operation
2569 * @adap: the adapter
2570 * @op : the operation (flush or flush and invalidate)
2571 */
2572int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
2573{
2574 struct fw_params_cmd c;
2575
2576 memset(&c, 0, sizeof(c));
2577 c.op_to_vfn =
2578 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
2579 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
b2612722 2580 FW_PARAMS_CMD_PFN_V(adap->pf) |
49216c1c
HS		 2581 FW_PARAMS_CMD_VFN_V(0));
2582 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2583 c.param[0].mnem =
2584 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2585 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
2586 c.param[0].val = (__force __be32)op;
2587
2588 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
2589}
2590
19689609
HS		 2591void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
2592 unsigned int *pif_req_wrptr,
2593 unsigned int *pif_rsp_wrptr)
2594{
2595 int i, j;
2596 u32 cfg, val, req, rsp;
2597
2598 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
2599 if (cfg & LADBGEN_F)
2600 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
2601
2602 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
2603 req = POLADBGWRPTR_G(val);
2604 rsp = PILADBGWRPTR_G(val);
2605 if (pif_req_wrptr)
2606 *pif_req_wrptr = req;
2607 if (pif_rsp_wrptr)
2608 *pif_rsp_wrptr = rsp;
2609
2610 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
2611 for (j = 0; j < 6; j++) {
2612 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
2613 PILADBGRDPTR_V(rsp));
2614 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
2615 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
2616 req++;
2617 rsp++;
2618 }
2619 req = (req + 2) & POLADBGRDPTR_M;
2620 rsp = (rsp + 2) & PILADBGRDPTR_M;
2621 }
2622 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
2623}
2624
26fae93f
HS		 2625void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
2626{
2627 u32 cfg;
2628 int i, j, idx;
2629
2630 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
2631 if (cfg & LADBGEN_F)
2632 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
2633
2634 for (i = 0; i < CIM_MALA_SIZE; i++) {
2635 for (j = 0; j < 5; j++) {
2636 idx = 8 * i + j;
2637 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
2638 PILADBGRDPTR_V(idx));
2639 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
2640 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
2641 }
2642 }
2643 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
2644}
2645
797ff0f5
HS		 2646void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
2647{
2648 unsigned int i, j;
2649
2650 for (i = 0; i < 8; i++) {
2651 u32 *p = la_buf + i;
2652
2653 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
2654 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
2655 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
2656 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
2657 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
2658 }
2659}
2660
56d36be4 2661#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
72aca4bf
KS		 2662 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
2663 FW_PORT_CAP_ANEG)
56d36be4
DM		 2664
2665/**
4036da90 2666 * t4_link_l1cfg - apply link configuration to MAC/PHY
56d36be4
DM		 2667 * @phy: the PHY to setup
2668 * @mac: the MAC to setup
2669 * @lc: the requested link configuration
2670 *
2671 * Set up a port's MAC and PHY according to a desired link configuration.
2672 * - If the PHY can auto-negotiate first decide what to advertise, then
2673 * enable/disable auto-negotiation as desired, and reset.
2674 * - If the PHY does not auto-negotiate just reset it.
2675 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2676 * otherwise do it later based on the outcome of auto-negotiation.
2677 */
4036da90 2678int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
56d36be4
DM		 2679 struct link_config *lc)
2680{
2681 struct fw_port_cmd c;
2b5fb1f2 2682 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
56d36be4
DM		 2683
2684 lc->link_ok = 0;
2685 if (lc->requested_fc & PAUSE_RX)
2686 fc |= FW_PORT_CAP_FC_RX;
2687 if (lc->requested_fc & PAUSE_TX)
2688 fc |= FW_PORT_CAP_FC_TX;
2689
2690 memset(&c, 0, sizeof(c));
f404f80c
HS		 2691 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
2692 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
2693 FW_PORT_CMD_PORTID_V(port));
2694 c.action_to_len16 =
2695 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
2696 FW_LEN16(c));
56d36be4
DM		 2697
2698 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
f404f80c
HS		 2699 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2700 fc);
56d36be4
DM		 2701 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2702 } else if (lc->autoneg == AUTONEG_DISABLE) {
f404f80c 2703 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
56d36be4
DM		 2704 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2705 } else
f404f80c 2706 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
56d36be4
DM		 2707
2708 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2709}
2710
2711/**
2712 * t4_restart_aneg - restart autonegotiation
2713 * @adap: the adapter
2714 * @mbox: mbox to use for the FW command
2715 * @port: the port id
2716 *
2717 * Restarts autonegotiation for the selected port.
2718 */
2719int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
2720{
2721 struct fw_port_cmd c;
2722
2723 memset(&c, 0, sizeof(c));
f404f80c
HS		 2724 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
2725 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
2726 FW_PORT_CMD_PORTID_V(port));
2727 c.action_to_len16 =
2728 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
2729 FW_LEN16(c));
2730 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
56d36be4
DM		 2731 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2732}
2733
8caa1e84
VP		 2734typedef void (*int_handler_t)(struct adapter *adap);
2735
56d36be4
DM		 2736struct intr_info {
2737 unsigned int mask; /* bits to check in interrupt status */
2738 const char *msg; /* message to print or NULL */
2739 short stat_idx; /* stat counter to increment or -1 */
2740 unsigned short fatal; /* whether the condition reported is fatal */
8caa1e84 2741 int_handler_t int_handler; /* platform-specific int handler */
56d36be4
DM		 2742};
2743
2744/**
2745 * t4_handle_intr_status - table driven interrupt handler
2746 * @adapter: the adapter that generated the interrupt
2747 * @reg: the interrupt status register to process
2748 * @acts: table of interrupt actions
2749 *
2750 * A table driven interrupt handler that applies a set of masks to an
2751 * interrupt status word and performs the corresponding actions if the
25985edc 2752 * interrupts described by the mask have occurred. The actions include
56d36be4
DM		 2753 * optionally emitting a warning or alert message. The table is terminated
2754 * by an entry specifying mask 0. Returns the number of fatal interrupt
2755 * conditions.
2756 */
2757static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
2758 const struct intr_info *acts)
2759{
2760 int fatal = 0;
2761 unsigned int mask = 0;
2762 unsigned int status = t4_read_reg(adapter, reg);
2763
2764 for ( ; acts->mask; ++acts) {
2765 if (!(status & acts->mask))
2766 continue;
2767 if (acts->fatal) {
2768 fatal++;
2769 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
2770 status & acts->mask);
2771 } else if (acts->msg && printk_ratelimit())
2772 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
2773 status & acts->mask);
8caa1e84
VP		 2774 if (acts->int_handler)
2775 acts->int_handler(adapter);
56d36be4
DM		 2776 mask |= acts->mask;
2777 }
2778 status &= mask;
2779 if (status) /* clear processed interrupts */
2780 t4_write_reg(adapter, reg, status);
2781 return fatal;
2782}
2783
2784/*
2785 * Interrupt handler for the PCIE module.
2786 */
2787static void pcie_intr_handler(struct adapter *adapter)
2788{
005b5717 2789 static const struct intr_info sysbus_intr_info[] = {
f061de42
HS		 2790 { RNPP_F, "RXNP array parity error", -1, 1 },
2791 { RPCP_F, "RXPC array parity error", -1, 1 },
2792 { RCIP_F, "RXCIF array parity error", -1, 1 },
2793 { RCCP_F, "Rx completions control array parity error", -1, 1 },
2794 { RFTP_F, "RXFT array parity error", -1, 1 },
56d36be4
DM		 2795 { 0 }
2796 };
005b5717 2797 static const struct intr_info pcie_port_intr_info[] = {
f061de42
HS		 2798 { TPCP_F, "TXPC array parity error", -1, 1 },
2799 { TNPP_F, "TXNP array parity error", -1, 1 },
2800 { TFTP_F, "TXFT array parity error", -1, 1 },
2801 { TCAP_F, "TXCA array parity error", -1, 1 },
2802 { TCIP_F, "TXCIF array parity error", -1, 1 },
2803 { RCAP_F, "RXCA array parity error", -1, 1 },
2804 { OTDD_F, "outbound request TLP discarded", -1, 1 },
2805 { RDPE_F, "Rx data parity error", -1, 1 },
2806 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
56d36be4
DM		 2807 { 0 }
2808 };
005b5717 2809 static const struct intr_info pcie_intr_info[] = {
f061de42
HS		 2810 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
2811 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
2812 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
2813 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
2814 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
2815 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
2816 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
2817 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
2818 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
2819 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
2820 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
2821 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
2822 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
2823 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
2824 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
2825 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
2826 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
2827 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
2828 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
2829 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
2830 { FIDPERR_F, "PCI FID parity error", -1, 1 },
2831 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
2832 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
2833 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
2834 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
2835 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
2836 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
2837 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
2838 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
2839 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
2840 -1, 0 },
56d36be4
DM		 2841 { 0 }
2842 };
2843
0a57a536 2844 static struct intr_info t5_pcie_intr_info[] = {
f061de42 2845 { MSTGRPPERR_F, "Master Response Read Queue parity error",
0a57a536 2846 -1, 1 },
f061de42
HS		 2847 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
2848 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
2849 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
2850 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
2851 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
2852 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
2853 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
0a57a536 2854 -1, 1 },
f061de42 2855 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
0a57a536 2856 -1, 1 },
f061de42
HS		 2857 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
2858 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
2859 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
2860 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
2861 { DREQWRPERR_F, "PCI DMA channel write request parity error",
0a57a536 2862 -1, 1 },
f061de42
HS		 2863 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
2864 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
2865 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
2866 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
2867 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
2868 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
2869 { FIDPERR_F, "PCI FID parity error", -1, 1 },
2870 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
2871 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
2872 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
2873 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
0a57a536 2874 -1, 1 },
f061de42
HS		 2875 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
2876 -1, 1 },
2877 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
2878 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
2879 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
2880 { READRSPERR_F, "Outbound read error", -1, 0 },
0a57a536
SR		 2881 { 0 }
2882 };
2883
56d36be4
DM		 2884 int fat;
2885
9bb59b96
HS		 2886 if (is_t4(adapter->params.chip))
2887 fat = t4_handle_intr_status(adapter,
f061de42
HS		 2888 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
2889 sysbus_intr_info) +
9bb59b96 2890 t4_handle_intr_status(adapter,
f061de42
HS		 2891 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
2892 pcie_port_intr_info) +
2893 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
9bb59b96
HS		 2894 pcie_intr_info);
2895 else
f061de42 2896 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
9bb59b96 2897 t5_pcie_intr_info);
0a57a536 2898
56d36be4
DM		 2899 if (fat)
2900 t4_fatal_err(adapter);
2901}
2902
2903/*
2904 * TP interrupt handler.
2905 */
2906static void tp_intr_handler(struct adapter *adapter)
2907{
005b5717 2908 static const struct intr_info tp_intr_info[] = {
56d36be4 2909 { 0x3fffffff, "TP parity error", -1, 1 },
837e4a42 2910 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
56d36be4
DM		 2911 { 0 }
2912 };
2913
837e4a42 2914 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
56d36be4
DM		 2915 t4_fatal_err(adapter);
2916}
2917
2918/*
2919 * SGE interrupt handler.
2920 */
2921static void sge_intr_handler(struct adapter *adapter)
2922{
2923 u64 v;
3ccc6cf7 2924 u32 err;
56d36be4 2925
005b5717 2926 static const struct intr_info sge_intr_info[] = {
f612b815 2927 { ERR_CPL_EXCEED_IQE_SIZE_F,
56d36be4 2928 "SGE received CPL exceeding IQE size", -1, 1 },
f612b815 2929 { ERR_INVALID_CIDX_INC_F,
56d36be4 2930 "SGE GTS CIDX increment too large", -1, 0 },
f612b815
HS		 2931 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
2932 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
f612b815 2933 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
56d36be4 2934 "SGE IQID > 1023 received CPL for FL", -1, 0 },
f612b815 2935 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
56d36be4 2936 0 },
f612b815 2937 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
56d36be4 2938 0 },
f612b815 2939 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
56d36be4 2940 0 },
f612b815 2941 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
56d36be4 2942 0 },
f612b815 2943 { ERR_ING_CTXT_PRIO_F,
56d36be4 2944 "SGE too many priority ingress contexts", -1, 0 },
f612b815
HS		 2945 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
2946 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
56d36be4
DM		 2947 { 0 }
2948 };
2949
3ccc6cf7
HS		 2950 static struct intr_info t4t5_sge_intr_info[] = {
2951 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
2952 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
2953 { ERR_EGR_CTXT_PRIO_F,
2954 "SGE too many priority egress contexts", -1, 0 },
2955 { 0 }
2956 };
2957
f612b815
HS		 2958 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
2959 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
56d36be4
DM		 2960 if (v) {
2961 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
8caa1e84 2962 (unsigned long long)v);
f612b815
HS		 2963 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
2964 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
56d36be4
DM		 2965 }
2966
3ccc6cf7
HS		 2967 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
2968 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2969 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
2970 t4t5_sge_intr_info);
2971
2972 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
2973 if (err & ERROR_QID_VALID_F) {
2974 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
2975 ERROR_QID_G(err));
2976 if (err & UNCAPTURED_ERROR_F)
2977 dev_err(adapter->pdev_dev,
2978 "SGE UNCAPTURED_ERROR set (clearing)\n");
2979 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
2980 UNCAPTURED_ERROR_F);
2981 }
2982
2983 if (v != 0)
56d36be4
DM		 2984 t4_fatal_err(adapter);
2985}
2986
89c3a86c
HS		 2987#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
2988 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
2989#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
2990 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
2991
56d36be4
DM		 2992/*
2993 * CIM interrupt handler.
2994 */
2995static void cim_intr_handler(struct adapter *adapter)
2996{
005b5717 2997 static const struct intr_info cim_intr_info[] = {
89c3a86c
HS		 2998 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
2999 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3000 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3001 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3002 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3003 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3004 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
56d36be4
DM		 3005 { 0 }
3006 };
005b5717 3007 static const struct intr_info cim_upintr_info[] = {
89c3a86c
HS		 3008 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3009 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3010 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3011 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3012 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3013 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3014 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3015 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3016 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3017 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3018 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3019 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3020 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3021 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3022 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3023 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3024 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3025 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3026 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3027 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3028 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3029 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3030 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3031 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3032 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3033 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3034 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3035 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
56d36be4
DM		 3036 { 0 }
3037 };
3038
3039 int fat;
3040
f061de42 3041 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
31d55c2d
HS		 3042 t4_report_fw_error(adapter);
3043
89c3a86c 3044 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
56d36be4 3045 cim_intr_info) +
89c3a86c 3046 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
56d36be4
DM		 3047 cim_upintr_info);
3048 if (fat)
3049 t4_fatal_err(adapter);
3050}
3051
3052/*
3053 * ULP RX interrupt handler.
3054 */
3055static void ulprx_intr_handler(struct adapter *adapter)
3056{
005b5717 3057 static const struct intr_info ulprx_intr_info[] = {
91e9a1ec 3058 { 0x1800000, "ULPRX context error", -1, 1 },
56d36be4
DM		 3059 { 0x7fffff, "ULPRX parity error", -1, 1 },
3060 { 0 }
3061 };
3062
0d804338 3063 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
56d36be4
DM		 3064 t4_fatal_err(adapter);
3065}
3066
3067/*
3068 * ULP TX interrupt handler.
3069 */
3070static void ulptx_intr_handler(struct adapter *adapter)
3071{
005b5717 3072 static const struct intr_info ulptx_intr_info[] = {
837e4a42 3073 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
56d36be4 3074 0 },
837e4a42 3075 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
56d36be4 3076 0 },
837e4a42 3077 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
56d36be4 3078 0 },
837e4a42 3079 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
56d36be4
DM		 3080 0 },
3081 { 0xfffffff, "ULPTX parity error", -1, 1 },
3082 { 0 }
3083 };
3084
837e4a42 3085 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
56d36be4
DM		 3086 t4_fatal_err(adapter);
3087}
3088
3089/*
3090 * PM TX interrupt handler.
3091 */
3092static void pmtx_intr_handler(struct adapter *adapter)
3093{
005b5717 3094 static const struct intr_info pmtx_intr_info[] = {
837e4a42
HS		 3095 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
3096 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
3097 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
3098 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
3099 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
3100 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
3101 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
3102 -1, 1 },
3103 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
3104 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
56d36be4
DM		 3105 { 0 }
3106 };
3107
837e4a42 3108 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
56d36be4
DM		 3109 t4_fatal_err(adapter);
3110}
3111
3112/*
3113 * PM RX interrupt handler.
3114 */
3115static void pmrx_intr_handler(struct adapter *adapter)
3116{
005b5717 3117 static const struct intr_info pmrx_intr_info[] = {
837e4a42
HS		 3118 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
3119 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
3120 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
3121 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
3122 -1, 1 },
3123 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
3124 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
56d36be4
DM		 3125 { 0 }
3126 };
3127
837e4a42 3128 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
56d36be4
DM		 3129 t4_fatal_err(adapter);
3130}
3131
3132/*
3133 * CPL switch interrupt handler.
3134 */
3135static void cplsw_intr_handler(struct adapter *adapter)
3136{
005b5717 3137 static const struct intr_info cplsw_intr_info[] = {
0d804338
HS		 3138 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
3139 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
3140 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
3141 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
3142 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
3143 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
56d36be4
DM		 3144 { 0 }
3145 };
3146
0d804338 3147 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
56d36be4
DM		 3148 t4_fatal_err(adapter);
3149}
3150
3151/*
3152 * LE interrupt handler.
3153 */
3154static void le_intr_handler(struct adapter *adap)
3155{
3ccc6cf7 3156 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
005b5717 3157 static const struct intr_info le_intr_info[] = {
0d804338
HS		 3158 { LIPMISS_F, "LE LIP miss", -1, 0 },
3159 { LIP0_F, "LE 0 LIP error", -1, 0 },
3160 { PARITYERR_F, "LE parity error", -1, 1 },
3161 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3162 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
56d36be4
DM		 3163 { 0 }
3164 };
3165
3ccc6cf7
HS		 3166 static struct intr_info t6_le_intr_info[] = {
3167 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
3168 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
3169 { TCAMINTPERR_F, "LE parity error", -1, 1 },
3170 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3171 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
3172 { 0 }
3173 };
3174
3175 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
3176 (chip <= CHELSIO_T5) ?
3177 le_intr_info : t6_le_intr_info))
56d36be4
DM		 3178 t4_fatal_err(adap);
3179}
3180
3181/*
3182 * MPS interrupt handler.
3183 */
3184static void mps_intr_handler(struct adapter *adapter)
3185{
005b5717 3186 static const struct intr_info mps_rx_intr_info[] = {
56d36be4
DM		 3187 { 0xffffff, "MPS Rx parity error", -1, 1 },
3188 { 0 }
3189 };
005b5717 3190 static const struct intr_info mps_tx_intr_info[] = {
837e4a42
HS		 3191 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
3192 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
3193 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
3194 -1, 1 },
3195 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
3196 -1, 1 },
3197 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
3198 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
3199 { FRMERR_F, "MPS Tx framing error", -1, 1 },
56d36be4
DM		 3200 { 0 }
3201 };
005b5717 3202 static const struct intr_info mps_trc_intr_info[] = {
837e4a42
HS		 3203 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
3204 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
3205 -1, 1 },
3206 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
56d36be4
DM		 3207 { 0 }
3208 };
005b5717 3209 static const struct intr_info mps_stat_sram_intr_info[] = {
56d36be4
DM		 3210 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
3211 { 0 }
3212 };
005b5717 3213 static const struct intr_info mps_stat_tx_intr_info[] = {
56d36be4
DM		 3214 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
3215 { 0 }
3216 };
005b5717 3217 static const struct intr_info mps_stat_rx_intr_info[] = {
56d36be4
DM		 3218 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
3219 { 0 }
3220 };
005b5717 3221 static const struct intr_info mps_cls_intr_info[] = {
837e4a42
HS		 3222 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
3223 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
3224 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
56d36be4
DM		 3225 { 0 }
3226 };
3227
3228 int fat;
3229
837e4a42 3230 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
56d36be4 3231 mps_rx_intr_info) +
837e4a42 3232 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
56d36be4 3233 mps_tx_intr_info) +
837e4a42 3234 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
56d36be4 3235 mps_trc_intr_info) +
837e4a42 3236 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
56d36be4 3237 mps_stat_sram_intr_info) +
837e4a42 3238 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
56d36be4 3239 mps_stat_tx_intr_info) +
837e4a42 3240 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
56d36be4 3241 mps_stat_rx_intr_info) +
837e4a42 3242 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
56d36be4
DM		 3243 mps_cls_intr_info);
3244
837e4a42
HS		 3245 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
3246 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
56d36be4
DM		 3247 if (fat)
3248 t4_fatal_err(adapter);
3249}
3250
89c3a86c
HS		 3251#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
3252 ECC_UE_INT_CAUSE_F)
56d36be4
DM		 3253
3254/*
3255 * EDC/MC interrupt handler.
3256 */
3257static void mem_intr_handler(struct adapter *adapter, int idx)
3258{
822dd8a8 3259 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
56d36be4
DM		 3260
3261 unsigned int addr, cnt_addr, v;
3262
3263 if (idx <= MEM_EDC1) {
89c3a86c
HS		 3264 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
3265 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
822dd8a8
HS		 3266 } else if (idx == MEM_MC) {
3267 if (is_t4(adapter->params.chip)) {
89c3a86c
HS		 3268 addr = MC_INT_CAUSE_A;
3269 cnt_addr = MC_ECC_STATUS_A;
822dd8a8 3270 } else {
89c3a86c
HS		 3271 addr = MC_P_INT_CAUSE_A;
3272 cnt_addr = MC_P_ECC_STATUS_A;
822dd8a8 3273 }
56d36be4 3274 } else {
89c3a86c
HS		 3275 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
3276 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
56d36be4
DM		 3277 }
3278
3279 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
89c3a86c 3280 if (v & PERR_INT_CAUSE_F)
56d36be4
DM		 3281 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
3282 name[idx]);
89c3a86c
HS		 3283 if (v & ECC_CE_INT_CAUSE_F) {
3284 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
56d36be4 3285
89c3a86c 3286 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
56d36be4
DM		 3287 if (printk_ratelimit())
3288 dev_warn(adapter->pdev_dev,
3289 "%u %s correctable ECC data error%s\n",
3290 cnt, name[idx], cnt > 1 ? "s" : "");
3291 }
89c3a86c 3292 if (v & ECC_UE_INT_CAUSE_F)
56d36be4
DM		 3293 dev_alert(adapter->pdev_dev,
3294 "%s uncorrectable ECC data error\n", name[idx]);
3295
3296 t4_write_reg(adapter, addr, v);
89c3a86c 3297 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
56d36be4
DM		 3298 t4_fatal_err(adapter);
3299}
3300
3301/*
3302 * MA interrupt handler.
3303 */
3304static void ma_intr_handler(struct adapter *adap)
3305{
89c3a86c 3306 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
56d36be4 3307
89c3a86c 3308 if (status & MEM_PERR_INT_CAUSE_F) {
56d36be4
DM		 3309 dev_alert(adap->pdev_dev,
3310 "MA parity error, parity status %#x\n",
89c3a86c 3311 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
9bb59b96
HS		 3312 if (is_t5(adap->params.chip))
3313 dev_alert(adap->pdev_dev,
3314 "MA parity error, parity status %#x\n",
3315 t4_read_reg(adap,
89c3a86c 3316 MA_PARITY_ERROR_STATUS2_A));
9bb59b96 3317 }
89c3a86c
HS		 3318 if (status & MEM_WRAP_INT_CAUSE_F) {
3319 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
56d36be4
DM		 3320 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
3321 "client %u to address %#x\n",
89c3a86c
HS		 3322 MEM_WRAP_CLIENT_NUM_G(v),
3323 MEM_WRAP_ADDRESS_G(v) << 4);
56d36be4 3324 }
89c3a86c 3325 t4_write_reg(adap, MA_INT_CAUSE_A, status);
56d36be4
DM		 3326 t4_fatal_err(adap);
3327}
3328
3329/*
3330 * SMB interrupt handler.
3331 */
3332static void smb_intr_handler(struct adapter *adap)
3333{
005b5717 3334 static const struct intr_info smb_intr_info[] = {
0d804338
HS		 3335 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
3336 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
3337 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
56d36be4
DM		 3338 { 0 }
3339 };
3340
0d804338 3341 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
56d36be4
DM		 3342 t4_fatal_err(adap);
3343}
3344
3345/*
3346 * NC-SI interrupt handler.
3347 */
3348static void ncsi_intr_handler(struct adapter *adap)
3349{
005b5717 3350 static const struct intr_info ncsi_intr_info[] = {
0d804338
HS		 3351 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
3352 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
3353 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
3354 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
56d36be4
DM		 3355 { 0 }
3356 };
3357
0d804338 3358 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
56d36be4
DM		 3359 t4_fatal_err(adap);
3360}
3361
3362/*
3363 * XGMAC interrupt handler.
3364 */
3365static void xgmac_intr_handler(struct adapter *adap, int port)
3366{
0a57a536
SR		 3367 u32 v, int_cause_reg;
3368
d14807dd 3369 if (is_t4(adap->params.chip))
0d804338 3370 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
0a57a536 3371 else
0d804338 3372 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
0a57a536
SR		 3373
3374 v = t4_read_reg(adap, int_cause_reg);
56d36be4 3375
0d804338 3376 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
56d36be4
DM		 3377 if (!v)
3378 return;
3379
0d804338 3380 if (v & TXFIFO_PRTY_ERR_F)
56d36be4
DM		 3381 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
3382 port);
0d804338 3383 if (v & RXFIFO_PRTY_ERR_F)
56d36be4
DM		 3384 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
3385 port);
0d804338 3386 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
56d36be4
DM		 3387 t4_fatal_err(adap);
3388}
3389
3390/*
3391 * PL interrupt handler.
3392 */
3393static void pl_intr_handler(struct adapter *adap)
3394{
005b5717 3395 static const struct intr_info pl_intr_info[] = {
0d804338
HS		 3396 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
3397 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
56d36be4
DM		 3398 { 0 }
3399 };
3400
0d804338 3401 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
56d36be4
DM		 3402 t4_fatal_err(adap);
3403}
3404
0d804338
HS		 3405#define PF_INTR_MASK (PFSW_F)
3406#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
3407 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
3408 CPL_SWITCH_F | SGE_F | ULP_TX_F)
56d36be4
DM		 3409
3410/**
3411 * t4_slow_intr_handler - control path interrupt handler
3412 * @adapter: the adapter
3413 *
3414 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
3415 * The designation 'slow' is because it involves register reads, while
3416 * data interrupts typically don't involve any MMIOs.
3417 */
3418int t4_slow_intr_handler(struct adapter *adapter)
3419{
0d804338 3420 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
56d36be4
DM		 3421
3422 if (!(cause & GLBL_INTR_MASK))
3423 return 0;
0d804338 3424 if (cause & CIM_F)
56d36be4 3425 cim_intr_handler(adapter);
0d804338 3426 if (cause & MPS_F)
56d36be4 3427 mps_intr_handler(adapter);
0d804338 3428 if (cause & NCSI_F)
56d36be4 3429 ncsi_intr_handler(adapter);
0d804338 3430 if (cause & PL_F)
56d36be4 3431 pl_intr_handler(adapter);
0d804338 3432 if (cause & SMB_F)
56d36be4 3433 smb_intr_handler(adapter);
0d804338 3434 if (cause & XGMAC0_F)
56d36be4 3435 xgmac_intr_handler(adapter, 0);
0d804338 3436 if (cause & XGMAC1_F)
56d36be4 3437 xgmac_intr_handler(adapter, 1);
0d804338 3438 if (cause & XGMAC_KR0_F)
56d36be4 3439 xgmac_intr_handler(adapter, 2);
0d804338 3440 if (cause & XGMAC_KR1_F)
56d36be4 3441 xgmac_intr_handler(adapter, 3);
0d804338 3442 if (cause & PCIE_F)
56d36be4 3443 pcie_intr_handler(adapter);
0d804338 3444 if (cause & MC_F)
56d36be4 3445 mem_intr_handler(adapter, MEM_MC);
3ccc6cf7 3446 if (is_t5(adapter->params.chip) && (cause & MC1_F))
822dd8a8 3447 mem_intr_handler(adapter, MEM_MC1);
0d804338 3448 if (cause & EDC0_F)
56d36be4 3449 mem_intr_handler(adapter, MEM_EDC0);
0d804338 3450 if (cause & EDC1_F)
56d36be4 3451 mem_intr_handler(adapter, MEM_EDC1);
0d804338 3452 if (cause & LE_F)
56d36be4 3453 le_intr_handler(adapter);
0d804338 3454 if (cause & TP_F)
56d36be4 3455 tp_intr_handler(adapter);
0d804338 3456 if (cause & MA_F)
56d36be4 3457 ma_intr_handler(adapter);
0d804338 3458 if (cause & PM_TX_F)
56d36be4 3459 pmtx_intr_handler(adapter);
0d804338 3460 if (cause & PM_RX_F)
56d36be4 3461 pmrx_intr_handler(adapter);
0d804338 3462 if (cause & ULP_RX_F)
56d36be4 3463 ulprx_intr_handler(adapter);
0d804338 3464 if (cause & CPL_SWITCH_F)
56d36be4 3465 cplsw_intr_handler(adapter);
0d804338 3466 if (cause & SGE_F)
56d36be4 3467 sge_intr_handler(adapter);
0d804338 3468 if (cause & ULP_TX_F)
56d36be4
DM		 3469 ulptx_intr_handler(adapter);
3470
3471 /* Clear the interrupts just processed for which we are the master. */
0d804338
HS		 3472 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
3473 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
56d36be4
DM		 3474 return 1;
3475}
3476
3477/**
3478 * t4_intr_enable - enable interrupts
3479 * @adapter: the adapter whose interrupts should be enabled
3480 *
3481 * Enable PF-specific interrupts for the calling function and the top-level
3482 * interrupt concentrator for global interrupts. Interrupts are already
3483 * enabled at each module, here we just enable the roots of the interrupt
3484 * hierarchies.
3485 *
3486 * Note: this function should be called only when the driver manages
3487 * non PF-specific interrupts from the various HW modules. Only one PCI
3488 * function at a time should be doing this.
3489 */
3490void t4_intr_enable(struct adapter *adapter)
3491{
3ccc6cf7 3492 u32 val = 0;
0d804338 3493 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
56d36be4 3494
3ccc6cf7
HS		 3495 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3496 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
f612b815
HS		 3497 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
3498 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
3ccc6cf7 3499 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
f612b815
HS		 3500 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
3501 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
3502 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
3ccc6cf7 3503 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
0d804338
HS		 3504 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
3505 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
56d36be4
DM		 3506}
3507
3508/**
3509 * t4_intr_disable - disable interrupts
3510 * @adapter: the adapter whose interrupts should be disabled
3511 *
3512 * Disable interrupts. We only disable the top-level interrupt
3513 * concentrators. The caller must be a PCI function managing global
3514 * interrupts.
3515 */
3516void t4_intr_disable(struct adapter *adapter)
3517{
0d804338 3518 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
56d36be4 3519
0d804338
HS		 3520 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
3521 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
56d36be4
DM		 3522}
3523
56d36be4
DM		 3524/**
3525 * hash_mac_addr - return the hash value of a MAC address
3526 * @addr: the 48-bit Ethernet MAC address
3527 *
3528 * Hashes a MAC address according to the hash function used by HW inexact
3529 * (hash) address matching.
3530 */
3531static int hash_mac_addr(const u8 *addr)
3532{
3533 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
3534 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
3535 a ^= b;
3536 a ^= (a >> 12);
3537 a ^= (a >> 6);
3538 return a & 0x3f;
3539}
3540
3541/**
3542 * t4_config_rss_range - configure a portion of the RSS mapping table
3543 * @adapter: the adapter
3544 * @mbox: mbox to use for the FW command
3545 * @viid: virtual interface whose RSS subtable is to be written
3546 * @start: start entry in the table to write
3547 * @n: how many table entries to write
3548 * @rspq: values for the response queue lookup table
3549 * @nrspq: number of values in @rspq
3550 *
3551 * Programs the selected part of the VI's RSS mapping table with the
3552 * provided values. If @nrspq < @n the supplied values are used repeatedly
3553 * until the full table range is populated.
3554 *
3555 * The caller must ensure the values in @rspq are in the range allowed for
3556 * @viid.
3557 */
3558int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
3559 int start, int n, const u16 *rspq, unsigned int nrspq)
3560{
3561 int ret;
3562 const u16 *rsp = rspq;
3563 const u16 *rsp_end = rspq + nrspq;
3564 struct fw_rss_ind_tbl_cmd cmd;
3565
3566 memset(&cmd, 0, sizeof(cmd));
f404f80c 3567 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
e2ac9628 3568 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
b2e1a3f0 3569 FW_RSS_IND_TBL_CMD_VIID_V(viid));
f404f80c 3570 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
56d36be4
DM		 3571
3572 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
3573 while (n > 0) {
3574 int nq = min(n, 32);
3575 __be32 *qp = &cmd.iq0_to_iq2;
3576
f404f80c
HS		 3577 cmd.niqid = cpu_to_be16(nq);
3578 cmd.startidx = cpu_to_be16(start);
56d36be4
DM		 3579
3580 start += nq;
3581 n -= nq;
3582
3583 while (nq > 0) {
3584 unsigned int v;
3585
b2e1a3f0 3586 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
56d36be4
DM		 3587 if (++rsp >= rsp_end)
3588 rsp = rspq;
b2e1a3f0 3589 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
56d36be4
DM		 3590 if (++rsp >= rsp_end)
3591 rsp = rspq;
b2e1a3f0 3592 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
56d36be4
DM		 3593 if (++rsp >= rsp_end)
3594 rsp = rspq;
3595
f404f80c 3596 *qp++ = cpu_to_be32(v);
56d36be4
DM		 3597 nq -= 3;
3598 }
3599
3600 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
3601 if (ret)
3602 return ret;
3603 }
3604 return 0;
3605}
3606
3607/**
3608 * t4_config_glbl_rss - configure the global RSS mode
3609 * @adapter: the adapter
3610 * @mbox: mbox to use for the FW command
3611 * @mode: global RSS mode
3612 * @flags: mode-specific flags
3613 *
3614 * Sets the global RSS mode.
3615 */
3616int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
3617 unsigned int flags)
3618{
3619 struct fw_rss_glb_config_cmd c;
3620
3621 memset(&c, 0, sizeof(c));
f404f80c
HS		 3622 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
3623 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3624 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
56d36be4 3625 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
f404f80c
HS		 3626 c.u.manual.mode_pkd =
3627 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
56d36be4
DM		 3628 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
3629 c.u.basicvirtual.mode_pkd =
f404f80c
HS		 3630 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
3631 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
56d36be4
DM		 3632 } else
3633 return -EINVAL;
3634 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
3635}
3636
c035e183
HS		 3637/**
3638 * t4_config_vi_rss - configure per VI RSS settings
3639 * @adapter: the adapter
3640 * @mbox: mbox to use for the FW command
3641 * @viid: the VI id
3642 * @flags: RSS flags
3643 * @defq: id of the default RSS queue for the VI.
3644 *
3645 * Configures VI-specific RSS properties.
3646 */
3647int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
3648 unsigned int flags, unsigned int defq)
3649{
3650 struct fw_rss_vi_config_cmd c;
3651
3652 memset(&c, 0, sizeof(c));
3653 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
3654 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3655 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
3656 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3657 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
3658 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
3659 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
3660}
3661
688ea5fe
HS		 3662/* Read an RSS table row */
3663static int rd_rss_row(struct adapter *adap, int row, u32 *val)
3664{
3665 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
3666 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
3667 5, 0, val);
3668}
3669
3670/**
3671 * t4_read_rss - read the contents of the RSS mapping table
3672 * @adapter: the adapter
3673 * @map: holds the contents of the RSS mapping table
3674 *
3675 * Reads the contents of the RSS hash->queue mapping table.
3676 */
3677int t4_read_rss(struct adapter *adapter, u16 *map)
3678{
3679 u32 val;
3680 int i, ret;
3681
3682 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
3683 ret = rd_rss_row(adapter, i, &val);
3684 if (ret)
3685 return ret;
3686 *map++ = LKPTBLQUEUE0_G(val);
3687 *map++ = LKPTBLQUEUE1_G(val);
3688 }
3689 return 0;
3690}
3691
c1e9af0c
HS		 3692/**
3693 * t4_fw_tp_pio_rw - Access TP PIO through LDST
3694 * @adap: the adapter
3695 * @vals: where the indirect register values are stored/written
3696 * @nregs: how many indirect registers to read/write
3697 * @start_idx: index of first indirect register to read/write
3698 * @rw: Read (1) or Write (0)
3699 *
3700 * Access TP PIO registers through LDST
3701 */
3702static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
3703 unsigned int start_index, unsigned int rw)
3704{
3705 int ret, i;
3706 int cmd = FW_LDST_ADDRSPC_TP_PIO;
3707 struct fw_ldst_cmd c;
3708
3709 for (i = 0 ; i < nregs; i++) {
3710 memset(&c, 0, sizeof(c));
3711 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
3712 FW_CMD_REQUEST_F |
3713 (rw ? FW_CMD_READ_F :
3714 FW_CMD_WRITE_F) |
3715 FW_LDST_CMD_ADDRSPACE_V(cmd));
3716 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
3717
3718 c.u.addrval.addr = cpu_to_be32(start_index + i);
3719 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
3720 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
3721 if (!ret && rw)
3722 vals[i] = be32_to_cpu(c.u.addrval.val);
3723 }
3724}
3725
688ea5fe
HS		 3726/**
3727 * t4_read_rss_key - read the global RSS key
3728 * @adap: the adapter
3729 * @key: 10-entry array holding the 320-bit RSS key
3730 *
3731 * Reads the global 320-bit RSS key.
3732 */
3733void t4_read_rss_key(struct adapter *adap, u32 *key)
3734{
c1e9af0c
HS		 3735 if (adap->flags & FW_OK)
3736 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
3737 else
3738 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
3739 TP_RSS_SECRET_KEY0_A);
688ea5fe
HS		 3740}
3741
3742/**
3743 * t4_write_rss_key - program one of the RSS keys
3744 * @adap: the adapter
3745 * @key: 10-entry array holding the 320-bit RSS key
3746 * @idx: which RSS key to write
3747 *
3748 * Writes one of the RSS keys with the given 320-bit value. If @idx is
3749 * 0..15 the corresponding entry in the RSS key table is written,
3750 * otherwise the global RSS key is written.
3751 */
3752void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
3753{
3ccc6cf7
HS		 3754 u8 rss_key_addr_cnt = 16;
3755 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
3756
3757 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
3758 * allows access to key addresses 16-63 by using KeyWrAddrX
3759 * as index[5:4](upper 2) into key table
3760 */
3761 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
3762 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
3763 rss_key_addr_cnt = 32;
3764
c1e9af0c
HS		 3765 if (adap->flags & FW_OK)
3766 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
3767 else
3768 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
3769 TP_RSS_SECRET_KEY0_A);
3ccc6cf7
HS		 3770
3771 if (idx >= 0 && idx < rss_key_addr_cnt) {
3772 if (rss_key_addr_cnt > 16)
3773 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
3774 KEYWRADDRX_V(idx >> 4) |
3775 T6_VFWRADDR_V(idx) | KEYWREN_F);
3776 else
3777 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
3778 KEYWRADDR_V(idx) | KEYWREN_F);
3779 }
688ea5fe
HS		 3780}
3781
3782/**
3783 * t4_read_rss_pf_config - read PF RSS Configuration Table
3784 * @adapter: the adapter
3785 * @index: the entry in the PF RSS table to read
3786 * @valp: where to store the returned value
3787 *
3788 * Reads the PF RSS Configuration Table at the specified index and returns
3789 * the value found there.
3790 */
3791void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
3792 u32 *valp)
3793{
c1e9af0c
HS		 3794 if (adapter->flags & FW_OK)
3795 t4_fw_tp_pio_rw(adapter, valp, 1,
3796 TP_RSS_PF0_CONFIG_A + index, 1);
3797 else
3798 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3799 valp, 1, TP_RSS_PF0_CONFIG_A + index);
688ea5fe
HS		 3800}
3801
3802/**
3803 * t4_read_rss_vf_config - read VF RSS Configuration Table
3804 * @adapter: the adapter
3805 * @index: the entry in the VF RSS table to read
3806 * @vfl: where to store the returned VFL
3807 * @vfh: where to store the returned VFH
3808 *
3809 * Reads the VF RSS Configuration Table at the specified index and returns
3810 * the (VFL, VFH) values found there.
3811 */
3812void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
3813 u32 *vfl, u32 *vfh)
3814{
3815 u32 vrt, mask, data;
3816
3ccc6cf7
HS		 3817 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
3818 mask = VFWRADDR_V(VFWRADDR_M);
3819 data = VFWRADDR_V(index);
3820 } else {
3821 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
3822 data = T6_VFWRADDR_V(index);
3823 }
688ea5fe
HS		 3824
3825 /* Request that the index'th VF Table values be read into VFL/VFH.
3826 */
3827 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
3828 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
3829 vrt |= data | VFRDEN_F;
3830 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
3831
3832 /* Grab the VFL/VFH values ...
3833 */
c1e9af0c
HS		 3834 if (adapter->flags & FW_OK) {
3835 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
3836 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
3837 } else {
3838 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3839 vfl, 1, TP_RSS_VFL_CONFIG_A);
3840 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3841 vfh, 1, TP_RSS_VFH_CONFIG_A);
3842 }
688ea5fe
HS		 3843}
3844
3845/**
3846 * t4_read_rss_pf_map - read PF RSS Map
3847 * @adapter: the adapter
3848 *
3849 * Reads the PF RSS Map register and returns its value.
3850 */
3851u32 t4_read_rss_pf_map(struct adapter *adapter)
3852{
3853 u32 pfmap;
3854
c1e9af0c
HS		 3855 if (adapter->flags & FW_OK)
3856 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
3857 else
3858 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3859 &pfmap, 1, TP_RSS_PF_MAP_A);
688ea5fe
HS		 3860 return pfmap;
3861}
3862
3863/**
3864 * t4_read_rss_pf_mask - read PF RSS Mask
3865 * @adapter: the adapter
3866 *
3867 * Reads the PF RSS Mask register and returns its value.
3868 */
3869u32 t4_read_rss_pf_mask(struct adapter *adapter)
3870{
3871 u32 pfmask;
3872
c1e9af0c
HS		 3873 if (adapter->flags & FW_OK)
3874 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
3875 else
3876 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3877 &pfmask, 1, TP_RSS_PF_MSK_A);
688ea5fe
HS		 3878 return pfmask;
3879}
3880
56d36be4
DM		 3881/**
3882 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
3883 * @adap: the adapter
3884 * @v4: holds the TCP/IP counter values
3885 * @v6: holds the TCP/IPv6 counter values
3886 *
3887 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
3888 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
3889 */
3890void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
3891 struct tp_tcp_stats *v6)
3892{
837e4a42 3893 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
56d36be4 3894
837e4a42 3895#define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
56d36be4
DM		 3896#define STAT(x) val[STAT_IDX(x)]
3897#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
3898
3899 if (v4) {
837e4a42
HS		 3900 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
3901 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
a4cfd929
HS		 3902 v4->tcp_out_rsts = STAT(OUT_RST);
3903 v4->tcp_in_segs = STAT64(IN_SEG);
3904 v4->tcp_out_segs = STAT64(OUT_SEG);
3905 v4->tcp_retrans_segs = STAT64(RXT_SEG);
56d36be4
DM		 3906 }
3907 if (v6) {
837e4a42
HS		 3908 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
3909 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
a4cfd929
HS		 3910 v6->tcp_out_rsts = STAT(OUT_RST);
3911 v6->tcp_in_segs = STAT64(IN_SEG);
3912 v6->tcp_out_segs = STAT64(OUT_SEG);
3913 v6->tcp_retrans_segs = STAT64(RXT_SEG);
56d36be4
DM		 3914 }
3915#undef STAT64
3916#undef STAT
3917#undef STAT_IDX
3918}
3919
a4cfd929
HS		 3920/**
3921 * t4_tp_get_err_stats - read TP's error MIB counters
3922 * @adap: the adapter
3923 * @st: holds the counter values
3924 *
3925 * Returns the values of TP's error counters.
3926 */
3927void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
3928{
3929 /* T6 and later has 2 channels */
3930 if (adap->params.arch.nchan == NCHAN) {
3931 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3932 st->mac_in_errs, 12, TP_MIB_MAC_IN_ERR_0_A);
3933 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3934 st->tnl_cong_drops, 8,
3935 TP_MIB_TNL_CNG_DROP_0_A);
3936 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3937 st->tnl_tx_drops, 4,
3938 TP_MIB_TNL_DROP_0_A);
3939 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3940 st->ofld_vlan_drops, 4,
3941 TP_MIB_OFD_VLN_DROP_0_A);
3942 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3943 st->tcp6_in_errs, 4,
3944 TP_MIB_TCP_V6IN_ERR_0_A);
3945 } else {
3946 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3947 st->mac_in_errs, 2, TP_MIB_MAC_IN_ERR_0_A);
3948 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3949 st->hdr_in_errs, 2, TP_MIB_HDR_IN_ERR_0_A);
3950 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3951 st->tcp_in_errs, 2, TP_MIB_TCP_IN_ERR_0_A);
3952 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3953 st->tnl_cong_drops, 2,
3954 TP_MIB_TNL_CNG_DROP_0_A);
3955 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3956 st->ofld_chan_drops, 2,
3957 TP_MIB_OFD_CHN_DROP_0_A);
3958 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3959 st->tnl_tx_drops, 2, TP_MIB_TNL_DROP_0_A);
3960 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3961 st->ofld_vlan_drops, 2,
3962 TP_MIB_OFD_VLN_DROP_0_A);
3963 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3964 st->tcp6_in_errs, 2, TP_MIB_TCP_V6IN_ERR_0_A);
3965 }
3966 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
3967 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
3968}
3969
a6222975
HS		 3970/**
3971 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
3972 * @adap: the adapter
3973 * @st: holds the counter values
3974 *
3975 * Returns the values of TP's CPL counters.
3976 */
3977void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
3978{
3979 /* T6 and later has 2 channels */
3980 if (adap->params.arch.nchan == NCHAN) {
3981 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
3982 8, TP_MIB_CPL_IN_REQ_0_A);
3983 } else {
3984 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
3985 2, TP_MIB_CPL_IN_REQ_0_A);
3986 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
3987 2, TP_MIB_CPL_OUT_RSP_0_A);
3988 }
3989}
3990
a4cfd929
HS		 3991/**
3992 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
3993 * @adap: the adapter
3994 * @st: holds the counter values
3995 *
3996 * Returns the values of TP's RDMA counters.
3997 */
3998void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
3999{
4000 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4001 2, TP_MIB_RQE_DFR_PKT_A);
4002}
4003
a6222975
HS		 4004/**
4005 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4006 * @adap: the adapter
4007 * @idx: the port index
4008 * @st: holds the counter values
4009 *
4010 * Returns the values of TP's FCoE counters for the selected port.
4011 */
4012void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4013 struct tp_fcoe_stats *st)
4014{
4015 u32 val[2];
4016
4017 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4018 1, TP_MIB_FCOE_DDP_0_A + idx);
4019 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4020 1, TP_MIB_FCOE_DROP_0_A + idx);
4021 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4022 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4023 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4024}
4025
a4cfd929
HS		 4026/**
4027 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4028 * @adap: the adapter
4029 * @st: holds the counter values
4030 *
4031 * Returns the values of TP's counters for non-TCP directly-placed packets.
4032 */
4033void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4034{
4035 u32 val[4];
4036
4037 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4038 TP_MIB_USM_PKTS_A);
4039 st->frames = val[0];
4040 st->drops = val[1];
4041 st->octets = ((u64)val[2] << 32) | val[3];
4042}
4043
56d36be4
DM		 4044/**
4045 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4046 * @adap: the adapter
4047 * @mtus: where to store the MTU values
4048 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4049 *
4050 * Reads the HW path MTU table.
4051 */
4052void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4053{
4054 u32 v;
4055 int i;
4056
4057 for (i = 0; i < NMTUS; ++i) {
837e4a42
HS		 4058 t4_write_reg(adap, TP_MTU_TABLE_A,
4059 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4060 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4061 mtus[i] = MTUVALUE_G(v);
56d36be4 4062 if (mtu_log)
837e4a42 4063 mtu_log[i] = MTUWIDTH_G(v);
56d36be4
DM		 4064 }
4065}
4066
bad43792
HS		 4067/**
4068 * t4_read_cong_tbl - reads the congestion control table
4069 * @adap: the adapter
4070 * @incr: where to store the alpha values
4071 *
4072 * Reads the additive increments programmed into the HW congestion
4073 * control table.
4074 */
4075void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4076{
4077 unsigned int mtu, w;
4078
4079 for (mtu = 0; mtu < NMTUS; ++mtu)
4080 for (w = 0; w < NCCTRL_WIN; ++w) {
4081 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4082 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4083 incr[mtu][w] = (u16)t4_read_reg(adap,
4084 TP_CCTRL_TABLE_A) & 0x1fff;
4085 }
4086}
4087
636f9d37
VP		 4088/**
4089 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4090 * @adap: the adapter
4091 * @addr: the indirect TP register address
4092 * @mask: specifies the field within the register to modify
4093 * @val: new value for the field
4094 *
4095 * Sets a field of an indirect TP register to the given value.
4096 */
4097void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4098 unsigned int mask, unsigned int val)
4099{
837e4a42
HS		 4100 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4101 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4102 t4_write_reg(adap, TP_PIO_DATA_A, val);
636f9d37
VP		 4103}
4104
56d36be4
DM		 4105/**
4106 * init_cong_ctrl - initialize congestion control parameters
4107 * @a: the alpha values for congestion control
4108 * @b: the beta values for congestion control
4109 *
4110 * Initialize the congestion control parameters.
4111 */
91744948 4112static void init_cong_ctrl(unsigned short *a, unsigned short *b)
56d36be4
DM		 4113{
4114 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
4115 a[9] = 2;
4116 a[10] = 3;
4117 a[11] = 4;
4118 a[12] = 5;
4119 a[13] = 6;
4120 a[14] = 7;
4121 a[15] = 8;
4122 a[16] = 9;
4123 a[17] = 10;
4124 a[18] = 14;
4125 a[19] = 17;
4126 a[20] = 21;
4127 a[21] = 25;
4128 a[22] = 30;
4129 a[23] = 35;
4130 a[24] = 45;
4131 a[25] = 60;
4132 a[26] = 80;
4133 a[27] = 100;
4134 a[28] = 200;
4135 a[29] = 300;
4136 a[30] = 400;
4137 a[31] = 500;
4138
4139 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
4140 b[9] = b[10] = 1;
4141 b[11] = b[12] = 2;
4142 b[13] = b[14] = b[15] = b[16] = 3;
4143 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
4144 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
4145 b[28] = b[29] = 6;
4146 b[30] = b[31] = 7;
4147}
4148
4149/* The minimum additive increment value for the congestion control table */
4150#define CC_MIN_INCR 2U
4151
4152/**
4153 * t4_load_mtus - write the MTU and congestion control HW tables
4154 * @adap: the adapter
4155 * @mtus: the values for the MTU table
4156 * @alpha: the values for the congestion control alpha parameter
4157 * @beta: the values for the congestion control beta parameter
4158 *
4159 * Write the HW MTU table with the supplied MTUs and the high-speed
4160 * congestion control table with the supplied alpha, beta, and MTUs.
4161 * We write the two tables together because the additive increments
4162 * depend on the MTUs.
4163 */
4164void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
4165 const unsigned short *alpha, const unsigned short *beta)
4166{
4167 static const unsigned int avg_pkts[NCCTRL_WIN] = {
4168 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
4169 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
4170 28672, 40960, 57344, 81920, 114688, 163840, 229376
4171 };
4172
4173 unsigned int i, w;
4174
4175 for (i = 0; i < NMTUS; ++i) {
4176 unsigned int mtu = mtus[i];
4177 unsigned int log2 = fls(mtu);
4178
4179 if (!(mtu & ((1 << log2) >> 2))) /* round */
4180 log2--;
837e4a42
HS		 4181 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
4182 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
56d36be4
DM		 4183
4184 for (w = 0; w < NCCTRL_WIN; ++w) {
4185 unsigned int inc;
4186
4187 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
4188 CC_MIN_INCR);
4189
837e4a42 4190 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
56d36be4
DM		 4191 (w << 16) | (beta[w] << 13) | inc);
4192 }
4193 }
4194}
4195
7864026b
HS		 4196/* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
4197 * clocks. The formula is
4198 *
4199 * bytes/s = bytes256 * 256 * ClkFreq / 4096
4200 *
4201 * which is equivalent to
4202 *
4203 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
4204 */
4205static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
4206{
4207 u64 v = bytes256 * adap->params.vpd.cclk;
4208
4209 return v * 62 + v / 2;
4210}
4211
4212/**
4213 * t4_get_chan_txrate - get the current per channel Tx rates
4214 * @adap: the adapter
4215 * @nic_rate: rates for NIC traffic
4216 * @ofld_rate: rates for offloaded traffic
4217 *
4218 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
4219 * for each channel.
4220 */
4221void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
4222{
4223 u32 v;
4224
4225 v = t4_read_reg(adap, TP_TX_TRATE_A);
4226 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
4227 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
4228 if (adap->params.arch.nchan == NCHAN) {
4229 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
4230 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
4231 }
4232
4233 v = t4_read_reg(adap, TP_TX_ORATE_A);
4234 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
4235 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
4236 if (adap->params.arch.nchan == NCHAN) {
4237 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
4238 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
4239 }
4240}
4241
b3bbe36a
HS		 4242/**
4243 * t4_pmtx_get_stats - returns the HW stats from PMTX
4244 * @adap: the adapter
4245 * @cnt: where to store the count statistics
4246 * @cycles: where to store the cycle statistics
4247 *
4248 * Returns performance statistics from PMTX.
4249 */
4250void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
4251{
4252 int i;
4253 u32 data[2];
4254
4255 for (i = 0; i < PM_NSTATS; i++) {
4256 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
4257 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
4258 if (is_t4(adap->params.chip)) {
4259 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
4260 } else {
4261 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
4262 PM_TX_DBG_DATA_A, data, 2,
4263 PM_TX_DBG_STAT_MSB_A);
4264 cycles[i] = (((u64)data[0] << 32) | data[1]);
4265 }
4266 }
4267}
4268
4269/**
4270 * t4_pmrx_get_stats - returns the HW stats from PMRX
4271 * @adap: the adapter
4272 * @cnt: where to store the count statistics
4273 * @cycles: where to store the cycle statistics
4274 *
4275 * Returns performance statistics from PMRX.
4276 */
4277void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
4278{
4279 int i;
4280 u32 data[2];
4281
4282 for (i = 0; i < PM_NSTATS; i++) {
4283 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
4284 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
4285 if (is_t4(adap->params.chip)) {
4286 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
4287 } else {
4288 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
4289 PM_RX_DBG_DATA_A, data, 2,
4290 PM_RX_DBG_STAT_MSB_A);
4291 cycles[i] = (((u64)data[0] << 32) | data[1]);
4292 }
4293 }
4294}
4295
56d36be4 4296/**
145ef8a5 4297 * t4_get_mps_bg_map - return the buffer groups associated with a port
56d36be4
DM		 4298 * @adap: the adapter
4299 * @idx: the port index
4300 *
4301 * Returns a bitmap indicating which MPS buffer groups are associated
4302 * with the given port. Bit i is set if buffer group i is used by the
4303 * port.
4304 */
145ef8a5 4305unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
56d36be4 4306{
837e4a42 4307 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
56d36be4
DM		 4308
4309 if (n == 0)
4310 return idx == 0 ? 0xf : 0;
4311 if (n == 1)
4312 return idx < 2 ? (3 << (2 * idx)) : 0;
4313 return 1 << idx;
4314}
4315
72aca4bf
KS		 4316/**
4317 * t4_get_port_type_description - return Port Type string description
4318 * @port_type: firmware Port Type enumeration
4319 */
4320const char *t4_get_port_type_description(enum fw_port_type port_type)
4321{
4322 static const char *const port_type_description[] = {
4323 "R XFI",
4324 "R XAUI",
4325 "T SGMII",
4326 "T XFI",
4327 "T XAUI",
4328 "KX4",
4329 "CX4",
4330 "KX",
4331 "KR",
4332 "R SFP+",
4333 "KR/KX",
4334 "KR/KX/KX4",
4335 "R QSFP_10G",
5aa80e51 4336 "R QSA",
72aca4bf
KS		 4337 "R QSFP",
4338 "R BP40_BA",
4339 };
4340
4341 if (port_type < ARRAY_SIZE(port_type_description))
4342 return port_type_description[port_type];
4343 return "UNKNOWN";
4344}
4345
a4cfd929
HS		 4346/**
4347 * t4_get_port_stats_offset - collect port stats relative to a previous
4348 * snapshot
4349 * @adap: The adapter
4350 * @idx: The port
4351 * @stats: Current stats to fill
4352 * @offset: Previous stats snapshot
4353 */
4354void t4_get_port_stats_offset(struct adapter *adap, int idx,
4355 struct port_stats *stats,
4356 struct port_stats *offset)
4357{
4358 u64 *s, *o;
4359 int i;
4360
4361 t4_get_port_stats(adap, idx, stats);
4362 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
4363 i < (sizeof(struct port_stats) / sizeof(u64));
4364 i++, s++, o++)
4365 *s -= *o;
4366}
4367
56d36be4
DM		 4368/**
4369 * t4_get_port_stats - collect port statistics
4370 * @adap: the adapter
4371 * @idx: the port index
4372 * @p: the stats structure to fill
4373 *
4374 * Collect statistics related to the given port from HW.
4375 */
4376void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
4377{
145ef8a5 4378 u32 bgmap = t4_get_mps_bg_map(adap, idx);
56d36be4
DM		 4379
4380#define GET_STAT(name) \
0a57a536 4381 t4_read_reg64(adap, \
d14807dd 4382 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
0a57a536 4383 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
56d36be4
DM		 4384#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
4385
4386 p->tx_octets = GET_STAT(TX_PORT_BYTES);
4387 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
4388 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
4389 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
4390 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
4391 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
4392 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
4393 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
4394 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
4395 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
4396 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
4397 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
4398 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
4399 p->tx_drop = GET_STAT(TX_PORT_DROP);
4400 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
4401 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
4402 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
4403 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
4404 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
4405 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
4406 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
4407 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
4408 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
4409
4410 p->rx_octets = GET_STAT(RX_PORT_BYTES);
4411 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
4412 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
4413 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
4414 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
4415 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
4416 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
4417 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
4418 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
4419 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
4420 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
4421 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
4422 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
4423 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
4424 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
4425 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
4426 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
4427 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
4428 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
4429 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
4430 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
4431 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
4432 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
4433 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
4434 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
4435 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
4436 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
4437
4438 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
4439 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
4440 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
4441 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
4442 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
4443 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
4444 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
4445 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
4446
4447#undef GET_STAT
4448#undef GET_STAT_COM
4449}
4450
56d36be4 4451/**
65046e84 4452 * t4_get_lb_stats - collect loopback port statistics
56d36be4 4453 * @adap: the adapter
65046e84
HS		 4454 * @idx: the loopback port index
4455 * @p: the stats structure to fill
56d36be4 4456 *
65046e84 4457 * Return HW statistics for the given loopback port.
56d36be4 4458 */
65046e84 4459void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
56d36be4 4460{
65046e84 4461 u32 bgmap = t4_get_mps_bg_map(adap, idx);
56d36be4 4462
65046e84
HS		 4463#define GET_STAT(name) \
4464 t4_read_reg64(adap, \
0d804338 4465 (is_t4(adap->params.chip) ? \
65046e84
HS		 4466 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
4467 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
4468#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
56d36be4 4469
65046e84
HS		 4470 p->octets = GET_STAT(BYTES);
4471 p->frames = GET_STAT(FRAMES);
4472 p->bcast_frames = GET_STAT(BCAST);
4473 p->mcast_frames = GET_STAT(MCAST);
4474 p->ucast_frames = GET_STAT(UCAST);
4475 p->error_frames = GET_STAT(ERROR);
4476
4477 p->frames_64 = GET_STAT(64B);
4478 p->frames_65_127 = GET_STAT(65B_127B);
4479 p->frames_128_255 = GET_STAT(128B_255B);
4480 p->frames_256_511 = GET_STAT(256B_511B);
4481 p->frames_512_1023 = GET_STAT(512B_1023B);
4482 p->frames_1024_1518 = GET_STAT(1024B_1518B);
4483 p->frames_1519_max = GET_STAT(1519B_MAX);
4484 p->drop = GET_STAT(DROP_FRAMES);
4485
4486 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
4487 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
4488 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
4489 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
4490 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
4491 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
4492 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
4493 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
56d36be4 4494
65046e84
HS		 4495#undef GET_STAT
4496#undef GET_STAT_COM
56d36be4
DM		 4497}
4498
f2b7e78d
VP		 4499/* t4_mk_filtdelwr - create a delete filter WR
4500 * @ftid: the filter ID
4501 * @wr: the filter work request to populate
4502 * @qid: ingress queue to receive the delete notification
4503 *
4504 * Creates a filter work request to delete the supplied filter. If @qid is
4505 * negative the delete notification is suppressed.
4506 */
4507void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
4508{
4509 memset(wr, 0, sizeof(*wr));
f404f80c
HS		 4510 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
4511 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
4512 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
4513 FW_FILTER_WR_NOREPLY_V(qid < 0));
4514 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
f2b7e78d 4515 if (qid >= 0)
f404f80c
HS		 4516 wr->rx_chan_rx_rpl_iq =
4517 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
f2b7e78d
VP		 4518}
4519
56d36be4 4520#define INIT_CMD(var, cmd, rd_wr) do { \
f404f80c
HS		 4521 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
4522 FW_CMD_REQUEST_F | \
4523 FW_CMD_##rd_wr##_F); \
4524 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
56d36be4
DM		 4525} while (0)
4526
8caa1e84
VP		 4527int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
4528 u32 addr, u32 val)
4529{
f404f80c 4530 u32 ldst_addrspace;
8caa1e84
VP		 4531 struct fw_ldst_cmd c;
4532
4533 memset(&c, 0, sizeof(c));
f404f80c
HS		 4534 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
4535 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4536 FW_CMD_REQUEST_F |
4537 FW_CMD_WRITE_F |
4538 ldst_addrspace);
4539 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4540 c.u.addrval.addr = cpu_to_be32(addr);
4541 c.u.addrval.val = cpu_to_be32(val);
8caa1e84
VP		 4542
4543 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4544}
4545
56d36be4
DM		 4546/**
4547 * t4_mdio_rd - read a PHY register through MDIO
4548 * @adap: the adapter
4549 * @mbox: mailbox to use for the FW command
4550 * @phy_addr: the PHY address
4551 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
4552 * @reg: the register to read
4553 * @valp: where to store the value
4554 *
4555 * Issues a FW command through the given mailbox to read a PHY register.
4556 */
4557int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
4558 unsigned int mmd, unsigned int reg, u16 *valp)
4559{
4560 int ret;
f404f80c 4561 u32 ldst_addrspace;
56d36be4
DM		 4562 struct fw_ldst_cmd c;
4563
4564 memset(&c, 0, sizeof(c));
f404f80c
HS		 4565 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
4566 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4567 FW_CMD_REQUEST_F | FW_CMD_READ_F |
4568 ldst_addrspace);
4569 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4570 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
4571 FW_LDST_CMD_MMD_V(mmd));
4572 c.u.mdio.raddr = cpu_to_be16(reg);
56d36be4
DM		 4573
4574 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4575 if (ret == 0)
f404f80c 4576 *valp = be16_to_cpu(c.u.mdio.rval);
56d36be4
DM		 4577 return ret;
4578}
4579
4580/**
4581 * t4_mdio_wr - write a PHY register through MDIO
4582 * @adap: the adapter
4583 * @mbox: mailbox to use for the FW command
4584 * @phy_addr: the PHY address
4585 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
4586 * @reg: the register to write
4587 * @valp: value to write
4588 *
4589 * Issues a FW command through the given mailbox to write a PHY register.
4590 */
4591int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
4592 unsigned int mmd, unsigned int reg, u16 val)
4593{
f404f80c 4594 u32 ldst_addrspace;
56d36be4
DM		 4595 struct fw_ldst_cmd c;
4596
4597 memset(&c, 0, sizeof(c));
f404f80c
HS		 4598 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
4599 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4600 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4601 ldst_addrspace);
4602 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4603 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
4604 FW_LDST_CMD_MMD_V(mmd));
4605 c.u.mdio.raddr = cpu_to_be16(reg);
4606 c.u.mdio.rval = cpu_to_be16(val);
56d36be4
DM		 4607
4608 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4609}
4610
68bce192
KS		 4611/**
4612 * t4_sge_decode_idma_state - decode the idma state
4613 * @adap: the adapter
4614 * @state: the state idma is stuck in
4615 */
4616void t4_sge_decode_idma_state(struct adapter *adapter, int state)
4617{
4618 static const char * const t4_decode[] = {
4619 "IDMA_IDLE",
4620 "IDMA_PUSH_MORE_CPL_FIFO",
4621 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
4622 "Not used",
4623 "IDMA_PHYSADDR_SEND_PCIEHDR",
4624 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
4625 "IDMA_PHYSADDR_SEND_PAYLOAD",
4626 "IDMA_SEND_FIFO_TO_IMSG",
4627 "IDMA_FL_REQ_DATA_FL_PREP",
4628 "IDMA_FL_REQ_DATA_FL",
4629 "IDMA_FL_DROP",
4630 "IDMA_FL_H_REQ_HEADER_FL",
4631 "IDMA_FL_H_SEND_PCIEHDR",
4632 "IDMA_FL_H_PUSH_CPL_FIFO",
4633 "IDMA_FL_H_SEND_CPL",
4634 "IDMA_FL_H_SEND_IP_HDR_FIRST",
4635 "IDMA_FL_H_SEND_IP_HDR",
4636 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
4637 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
4638 "IDMA_FL_H_SEND_IP_HDR_PADDING",
4639 "IDMA_FL_D_SEND_PCIEHDR",
4640 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
4641 "IDMA_FL_D_REQ_NEXT_DATA_FL",
4642 "IDMA_FL_SEND_PCIEHDR",
4643 "IDMA_FL_PUSH_CPL_FIFO",
4644 "IDMA_FL_SEND_CPL",
4645 "IDMA_FL_SEND_PAYLOAD_FIRST",
4646 "IDMA_FL_SEND_PAYLOAD",
4647 "IDMA_FL_REQ_NEXT_DATA_FL",
4648 "IDMA_FL_SEND_NEXT_PCIEHDR",
4649 "IDMA_FL_SEND_PADDING",
4650 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
4651 "IDMA_FL_SEND_FIFO_TO_IMSG",
4652 "IDMA_FL_REQ_DATAFL_DONE",
4653 "IDMA_FL_REQ_HEADERFL_DONE",
4654 };
4655 static const char * const t5_decode[] = {
4656 "IDMA_IDLE",
4657 "IDMA_ALMOST_IDLE",
4658 "IDMA_PUSH_MORE_CPL_FIFO",
4659 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
4660 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
4661 "IDMA_PHYSADDR_SEND_PCIEHDR",
4662 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
4663 "IDMA_PHYSADDR_SEND_PAYLOAD",
4664 "IDMA_SEND_FIFO_TO_IMSG",
4665 "IDMA_FL_REQ_DATA_FL",
4666 "IDMA_FL_DROP",
4667 "IDMA_FL_DROP_SEND_INC",
4668 "IDMA_FL_H_REQ_HEADER_FL",
4669 "IDMA_FL_H_SEND_PCIEHDR",
4670 "IDMA_FL_H_PUSH_CPL_FIFO",
4671 "IDMA_FL_H_SEND_CPL",
4672 "IDMA_FL_H_SEND_IP_HDR_FIRST",
4673 "IDMA_FL_H_SEND_IP_HDR",
4674 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
4675 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
4676 "IDMA_FL_H_SEND_IP_HDR_PADDING",
4677 "IDMA_FL_D_SEND_PCIEHDR",
4678 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
4679 "IDMA_FL_D_REQ_NEXT_DATA_FL",
4680 "IDMA_FL_SEND_PCIEHDR",
4681 "IDMA_FL_PUSH_CPL_FIFO",
4682 "IDMA_FL_SEND_CPL",
4683 "IDMA_FL_SEND_PAYLOAD_FIRST",
4684 "IDMA_FL_SEND_PAYLOAD",
4685 "IDMA_FL_REQ_NEXT_DATA_FL",
4686 "IDMA_FL_SEND_NEXT_PCIEHDR",
4687 "IDMA_FL_SEND_PADDING",
4688 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
4689 };
4690 static const u32 sge_regs[] = {
f061de42
HS		 4691 SGE_DEBUG_DATA_LOW_INDEX_2_A,
4692 SGE_DEBUG_DATA_LOW_INDEX_3_A,
4693 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
68bce192
KS		 4694 };
4695 const char **sge_idma_decode;
4696 int sge_idma_decode_nstates;
4697 int i;
4698
4699 if (is_t4(adapter->params.chip)) {
4700 sge_idma_decode = (const char **)t4_decode;
4701 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
4702 } else {
4703 sge_idma_decode = (const char **)t5_decode;
4704 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
4705 }
4706
4707 if (state < sge_idma_decode_nstates)
4708 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
4709 else
4710 CH_WARN(adapter, "idma state %d unknown\n", state);
4711
4712 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
4713 CH_WARN(adapter, "SGE register %#x value %#x\n",
4714 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
4715}
4716
5d700ecb
HS		 4717/**
4718 * t4_sge_ctxt_flush - flush the SGE context cache
4719 * @adap: the adapter
4720 * @mbox: mailbox to use for the FW command
4721 *
4722 * Issues a FW command through the given mailbox to flush the
4723 * SGE context cache.
4724 */
4725int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
4726{
4727 int ret;
4728 u32 ldst_addrspace;
4729 struct fw_ldst_cmd c;
4730
4731 memset(&c, 0, sizeof(c));
4732 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
4733 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4734 FW_CMD_REQUEST_F | FW_CMD_READ_F |
4735 ldst_addrspace);
4736 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4737 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
4738
4739 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4740 return ret;
4741}
4742
56d36be4 4743/**
636f9d37
VP		 4744 * t4_fw_hello - establish communication with FW
4745 * @adap: the adapter
4746 * @mbox: mailbox to use for the FW command
4747 * @evt_mbox: mailbox to receive async FW events
4748 * @master: specifies the caller's willingness to be the device master
4749 * @state: returns the current device state (if non-NULL)
56d36be4 4750 *
636f9d37
VP		 4751 * Issues a command to establish communication with FW. Returns either
4752 * an error (negative integer) or the mailbox of the Master PF.
56d36be4
DM		 4753 */
4754int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
4755 enum dev_master master, enum dev_state *state)
4756{
4757 int ret;
4758 struct fw_hello_cmd c;
636f9d37
VP		 4759 u32 v;
4760 unsigned int master_mbox;
4761 int retries = FW_CMD_HELLO_RETRIES;
56d36be4 4762
636f9d37
VP		 4763retry:
4764 memset(&c, 0, sizeof(c));
56d36be4 4765 INIT_CMD(c, HELLO, WRITE);
f404f80c 4766 c.err_to_clearinit = cpu_to_be32(
5167865a
HS		 4767 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
4768 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
f404f80c
HS		 4769 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
4770 mbox : FW_HELLO_CMD_MBMASTER_M) |
5167865a
HS		 4771 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
4772 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
4773 FW_HELLO_CMD_CLEARINIT_F);
56d36be4 4774
636f9d37
VP		 4775 /*
4776 * Issue the HELLO command to the firmware. If it's not successful
4777 * but indicates that we got a "busy" or "timeout" condition, retry
31d55c2d
HS		 4778 * the HELLO until we exhaust our retry limit. If we do exceed our
4779 * retry limit, check to see if the firmware left us any error
4780 * information and report that if so.
636f9d37 4781 */
56d36be4 4782 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
636f9d37
VP		 4783 if (ret < 0) {
4784 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
4785 goto retry;
f061de42 4786 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
31d55c2d 4787 t4_report_fw_error(adap);
636f9d37
VP		 4788 return ret;
4789 }
4790
f404f80c 4791 v = be32_to_cpu(c.err_to_clearinit);
5167865a 4792 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
636f9d37 4793 if (state) {
5167865a 4794 if (v & FW_HELLO_CMD_ERR_F)
56d36be4 4795 *state = DEV_STATE_ERR;
5167865a 4796 else if (v & FW_HELLO_CMD_INIT_F)
636f9d37 4797 *state = DEV_STATE_INIT;
56d36be4
DM		 4798 else
4799 *state = DEV_STATE_UNINIT;
4800 }
636f9d37
VP		 4801
4802 /*
4803 * If we're not the Master PF then we need to wait around for the
4804 * Master PF Driver to finish setting up the adapter.
4805 *
4806 * Note that we also do this wait if we're a non-Master-capable PF and
4807 * there is no current Master PF; a Master PF may show up momentarily
4808 * and we wouldn't want to fail pointlessly. (This can happen when an
4809 * OS loads lots of different drivers rapidly at the same time). In
4810 * this case, the Master PF returned by the firmware will be
b2e1a3f0 4811 * PCIE_FW_MASTER_M so the test below will work ...
636f9d37 4812 */
5167865a 4813 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
636f9d37
VP		 4814 master_mbox != mbox) {
4815 int waiting = FW_CMD_HELLO_TIMEOUT;
4816
4817 /*
4818 * Wait for the firmware to either indicate an error or
4819 * initialized state. If we see either of these we bail out
4820 * and report the issue to the caller. If we exhaust the
4821 * "hello timeout" and we haven't exhausted our retries, try
4822 * again. Otherwise bail with a timeout error.
4823 */
4824 for (;;) {
4825 u32 pcie_fw;
4826
4827 msleep(50);
4828 waiting -= 50;
4829
4830 /*
4831 * If neither Error nor Initialialized are indicated
4832 * by the firmware keep waiting till we exaust our
4833 * timeout ... and then retry if we haven't exhausted
4834 * our retries ...
4835 */
f061de42
HS		 4836 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
4837 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
636f9d37
VP		 4838 if (waiting <= 0) {
4839 if (retries-- > 0)
4840 goto retry;
4841
4842 return -ETIMEDOUT;
4843 }
4844 continue;
4845 }
4846
4847 /*
4848 * We either have an Error or Initialized condition
4849 * report errors preferentially.
4850 */
4851 if (state) {
f061de42 4852 if (pcie_fw & PCIE_FW_ERR_F)
636f9d37 4853 *state = DEV_STATE_ERR;
f061de42 4854 else if (pcie_fw & PCIE_FW_INIT_F)
636f9d37
VP		 4855 *state = DEV_STATE_INIT;
4856 }
4857
4858 /*
4859 * If we arrived before a Master PF was selected and
4860 * there's not a valid Master PF, grab its identity
4861 * for our caller.
4862 */
b2e1a3f0 4863 if (master_mbox == PCIE_FW_MASTER_M &&
f061de42 4864 (pcie_fw & PCIE_FW_MASTER_VLD_F))
b2e1a3f0 4865 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
636f9d37
VP		 4866 break;
4867 }
4868 }
4869
4870 return master_mbox;
56d36be4
DM		 4871}
4872
4873/**
4874 * t4_fw_bye - end communication with FW
4875 * @adap: the adapter
4876 * @mbox: mailbox to use for the FW command
4877 *
4878 * Issues a command to terminate communication with FW.
4879 */
4880int t4_fw_bye(struct adapter *adap, unsigned int mbox)
4881{
4882 struct fw_bye_cmd c;
4883
0062b15c 4884 memset(&c, 0, sizeof(c));
56d36be4
DM		 4885 INIT_CMD(c, BYE, WRITE);
4886 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4887}
4888
4889/**
4890 * t4_init_cmd - ask FW to initialize the device
4891 * @adap: the adapter
4892 * @mbox: mailbox to use for the FW command
4893 *
4894 * Issues a command to FW to partially initialize the device. This
4895 * performs initialization that generally doesn't depend on user input.
4896 */
4897int t4_early_init(struct adapter *adap, unsigned int mbox)
4898{
4899 struct fw_initialize_cmd c;
4900
0062b15c 4901 memset(&c, 0, sizeof(c));
56d36be4
DM		 4902 INIT_CMD(c, INITIALIZE, WRITE);
4903 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4904}
4905
4906/**
4907 * t4_fw_reset - issue a reset to FW
4908 * @adap: the adapter
4909 * @mbox: mailbox to use for the FW command
4910 * @reset: specifies the type of reset to perform
4911 *
4912 * Issues a reset command of the specified type to FW.
4913 */
4914int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
4915{
4916 struct fw_reset_cmd c;
4917
0062b15c 4918 memset(&c, 0, sizeof(c));
56d36be4 4919 INIT_CMD(c, RESET, WRITE);
f404f80c 4920 c.val = cpu_to_be32(reset);
56d36be4
DM		 4921 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4922}
4923
26f7cbc0
VP		 4924/**
4925 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
4926 * @adap: the adapter
4927 * @mbox: mailbox to use for the FW RESET command (if desired)
4928 * @force: force uP into RESET even if FW RESET command fails
4929 *
4930 * Issues a RESET command to firmware (if desired) with a HALT indication
4931 * and then puts the microprocessor into RESET state. The RESET command
4932 * will only be issued if a legitimate mailbox is provided (mbox <=
b2e1a3f0 4933 * PCIE_FW_MASTER_M).
26f7cbc0
VP		 4934 *
4935 * This is generally used in order for the host to safely manipulate the
4936 * adapter without fear of conflicting with whatever the firmware might
4937 * be doing. The only way out of this state is to RESTART the firmware
4938 * ...
4939 */
de5b8677 4940static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
26f7cbc0
VP		 4941{
4942 int ret = 0;
4943
4944 /*
4945 * If a legitimate mailbox is provided, issue a RESET command
4946 * with a HALT indication.
4947 */
b2e1a3f0 4948 if (mbox <= PCIE_FW_MASTER_M) {
26f7cbc0
VP		 4949 struct fw_reset_cmd c;
4950
4951 memset(&c, 0, sizeof(c));
4952 INIT_CMD(c, RESET, WRITE);
f404f80c
HS		 4953 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
4954 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
26f7cbc0
VP		 4955 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4956 }
4957
4958 /*
4959 * Normally we won't complete the operation if the firmware RESET
4960 * command fails but if our caller insists we'll go ahead and put the
4961 * uP into RESET. This can be useful if the firmware is hung or even
4962 * missing ... We'll have to take the risk of putting the uP into
4963 * RESET without the cooperation of firmware in that case.
4964 *
4965 * We also force the firmware's HALT flag to be on in case we bypassed
4966 * the firmware RESET command above or we're dealing with old firmware
4967 * which doesn't have the HALT capability. This will serve as a flag
4968 * for the incoming firmware to know that it's coming out of a HALT
4969 * rather than a RESET ... if it's new enough to understand that ...
4970 */
4971 if (ret == 0 || force) {
89c3a86c 4972 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
f061de42 4973 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
b2e1a3f0 4974 PCIE_FW_HALT_F);
26f7cbc0
VP		 4975 }
4976
4977 /*
4978 * And we always return the result of the firmware RESET command
4979 * even when we force the uP into RESET ...
4980 */
4981 return ret;
4982}
4983
4984/**
4985 * t4_fw_restart - restart the firmware by taking the uP out of RESET
4986 * @adap: the adapter
4987 * @reset: if we want to do a RESET to restart things
4988 *
4989 * Restart firmware previously halted by t4_fw_halt(). On successful
4990 * return the previous PF Master remains as the new PF Master and there
4991 * is no need to issue a new HELLO command, etc.
4992 *
4993 * We do this in two ways:
4994 *
4995 * 1. If we're dealing with newer firmware we'll simply want to take
4996 * the chip's microprocessor out of RESET. This will cause the
4997 * firmware to start up from its start vector. And then we'll loop
4998 * until the firmware indicates it's started again (PCIE_FW.HALT
4999 * reset to 0) or we timeout.
5000 *
5001 * 2. If we're dealing with older firmware then we'll need to RESET
5002 * the chip since older firmware won't recognize the PCIE_FW.HALT
5003 * flag and automatically RESET itself on startup.
5004 */
de5b8677 5005static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
26f7cbc0
VP		 5006{
5007 if (reset) {
5008 /*
5009 * Since we're directing the RESET instead of the firmware
5010 * doing it automatically, we need to clear the PCIE_FW.HALT
5011 * bit.
5012 */
f061de42 5013 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
26f7cbc0
VP		 5014
5015 /*
5016 * If we've been given a valid mailbox, first try to get the
5017 * firmware to do the RESET. If that works, great and we can
5018 * return success. Otherwise, if we haven't been given a
5019 * valid mailbox or the RESET command failed, fall back to
5020 * hitting the chip with a hammer.
5021 */
b2e1a3f0 5022 if (mbox <= PCIE_FW_MASTER_M) {
89c3a86c 5023 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
26f7cbc0
VP		 5024 msleep(100);
5025 if (t4_fw_reset(adap, mbox,
0d804338 5026 PIORST_F | PIORSTMODE_F) == 0)
26f7cbc0
VP		 5027 return 0;
5028 }
5029
0d804338 5030 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
26f7cbc0
VP		 5031 msleep(2000);
5032 } else {
5033 int ms;
5034
89c3a86c 5035 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
26f7cbc0 5036 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
f061de42 5037 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
26f7cbc0
VP		 5038 return 0;
5039 msleep(100);
5040 ms += 100;
5041 }
5042 return -ETIMEDOUT;
5043 }
5044 return 0;
5045}
5046
5047/**
5048 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
5049 * @adap: the adapter
5050 * @mbox: mailbox to use for the FW RESET command (if desired)
5051 * @fw_data: the firmware image to write
5052 * @size: image size
5053 * @force: force upgrade even if firmware doesn't cooperate
5054 *
5055 * Perform all of the steps necessary for upgrading an adapter's
5056 * firmware image. Normally this requires the cooperation of the
5057 * existing firmware in order to halt all existing activities
5058 * but if an invalid mailbox token is passed in we skip that step
5059 * (though we'll still put the adapter microprocessor into RESET in
5060 * that case).
5061 *
5062 * On successful return the new firmware will have been loaded and
5063 * the adapter will have been fully RESET losing all previous setup
5064 * state. On unsuccessful return the adapter may be completely hosed ...
5065 * positive errno indicates that the adapter is ~probably~ intact, a
5066 * negative errno indicates that things are looking bad ...
5067 */
22c0b963
HS		 5068int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
5069 const u8 *fw_data, unsigned int size, int force)
26f7cbc0
VP		 5070{
5071 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
5072 int reset, ret;
5073
79af221d
HS		 5074 if (!t4_fw_matches_chip(adap, fw_hdr))
5075 return -EINVAL;
5076
26f7cbc0
VP		 5077 ret = t4_fw_halt(adap, mbox, force);
5078 if (ret < 0 && !force)
5079 return ret;
5080
5081 ret = t4_load_fw(adap, fw_data, size);
5082 if (ret < 0)
5083 return ret;
5084
5085 /*
5086 * Older versions of the firmware don't understand the new
5087 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
5088 * restart. So for newly loaded older firmware we'll have to do the
5089 * RESET for it so it starts up on a clean slate. We can tell if
5090 * the newly loaded firmware will handle this right by checking
5091 * its header flags to see if it advertises the capability.
5092 */
f404f80c 5093 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
26f7cbc0
VP		 5094 return t4_fw_restart(adap, mbox, reset);
5095}
5096
636f9d37
VP		 5097/**
5098 * t4_fixup_host_params - fix up host-dependent parameters
5099 * @adap: the adapter
5100 * @page_size: the host's Base Page Size
5101 * @cache_line_size: the host's Cache Line Size
5102 *
5103 * Various registers in T4 contain values which are dependent on the
5104 * host's Base Page and Cache Line Sizes. This function will fix all of
5105 * those registers with the appropriate values as passed in ...
5106 */
5107int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
5108 unsigned int cache_line_size)
5109{
5110 unsigned int page_shift = fls(page_size) - 1;
5111 unsigned int sge_hps = page_shift - 10;
5112 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
5113 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
5114 unsigned int fl_align_log = fls(fl_align) - 1;
5115
f612b815
HS		 5116 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
5117 HOSTPAGESIZEPF0_V(sge_hps) |
5118 HOSTPAGESIZEPF1_V(sge_hps) |
5119 HOSTPAGESIZEPF2_V(sge_hps) |
5120 HOSTPAGESIZEPF3_V(sge_hps) |
5121 HOSTPAGESIZEPF4_V(sge_hps) |
5122 HOSTPAGESIZEPF5_V(sge_hps) |
5123 HOSTPAGESIZEPF6_V(sge_hps) |
5124 HOSTPAGESIZEPF7_V(sge_hps));
636f9d37 5125
ce8f407a 5126 if (is_t4(adap->params.chip)) {
f612b815
HS		 5127 t4_set_reg_field(adap, SGE_CONTROL_A,
5128 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
5129 EGRSTATUSPAGESIZE_F,
5130 INGPADBOUNDARY_V(fl_align_log -
5131 INGPADBOUNDARY_SHIFT_X) |
5132 EGRSTATUSPAGESIZE_V(stat_len != 64));
ce8f407a
HS		 5133 } else {
5134 /* T5 introduced the separation of the Free List Padding and
5135 * Packing Boundaries. Thus, we can select a smaller Padding
5136 * Boundary to avoid uselessly chewing up PCIe Link and Memory
5137 * Bandwidth, and use a Packing Boundary which is large enough
5138 * to avoid false sharing between CPUs, etc.
5139 *
5140 * For the PCI Link, the smaller the Padding Boundary the
5141 * better. For the Memory Controller, a smaller Padding
5142 * Boundary is better until we cross under the Memory Line
5143 * Size (the minimum unit of transfer to/from Memory). If we
5144 * have a Padding Boundary which is smaller than the Memory
5145 * Line Size, that'll involve a Read-Modify-Write cycle on the
5146 * Memory Controller which is never good. For T5 the smallest
5147 * Padding Boundary which we can select is 32 bytes which is
5148 * larger than any known Memory Controller Line Size so we'll
5149 * use that.
5150 *
5151 * T5 has a different interpretation of the "0" value for the
5152 * Packing Boundary. This corresponds to 16 bytes instead of
5153 * the expected 32 bytes. We never have a Packing Boundary
5154 * less than 32 bytes so we can't use that special value but
5155 * on the other hand, if we wanted 32 bytes, the best we can
5156 * really do is 64 bytes.
5157 */
5158 if (fl_align <= 32) {
5159 fl_align = 64;
5160 fl_align_log = 6;
5161 }
f612b815
HS		 5162 t4_set_reg_field(adap, SGE_CONTROL_A,
5163 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
5164 EGRSTATUSPAGESIZE_F,
5165 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) |
5166 EGRSTATUSPAGESIZE_V(stat_len != 64));
ce8f407a
HS		 5167 t4_set_reg_field(adap, SGE_CONTROL2_A,
5168 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
5169 INGPACKBOUNDARY_V(fl_align_log -
f612b815 5170 INGPACKBOUNDARY_SHIFT_X));
ce8f407a 5171 }
636f9d37
VP		 5172 /*
5173 * Adjust various SGE Free List Host Buffer Sizes.
5174 *
5175 * This is something of a crock since we're using fixed indices into
5176 * the array which are also known by the sge.c code and the T4
5177 * Firmware Configuration File. We need to come up with a much better
5178 * approach to managing this array. For now, the first four entries
5179 * are:
5180 *
5181 * 0: Host Page Size
5182 * 1: 64KB
5183 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
5184 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
5185 *
5186 * For the single-MTU buffers in unpacked mode we need to include
5187 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
5188 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
dbedd44e 5189 * Padding boundary. All of these are accommodated in the Factory
636f9d37
VP		 5190 * Default Firmware Configuration File but we need to adjust it for
5191 * this host's cache line size.
5192 */
f612b815
HS		 5193 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
5194 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
5195 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
636f9d37 5196 & ~(fl_align-1));
f612b815
HS		 5197 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
5198 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
636f9d37
VP		 5199 & ~(fl_align-1));
5200
0d804338 5201 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
636f9d37
VP		 5202
5203 return 0;
5204}
5205
5206/**
5207 * t4_fw_initialize - ask FW to initialize the device
5208 * @adap: the adapter
5209 * @mbox: mailbox to use for the FW command
5210 *
5211 * Issues a command to FW to partially initialize the device. This
5212 * performs initialization that generally doesn't depend on user input.
5213 */
5214int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
5215{
5216 struct fw_initialize_cmd c;
5217
5218 memset(&c, 0, sizeof(c));
5219 INIT_CMD(c, INITIALIZE, WRITE);
5220 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5221}
5222
56d36be4 5223/**
01b69614 5224 * t4_query_params_rw - query FW or device parameters
56d36be4
DM		 5225 * @adap: the adapter
5226 * @mbox: mailbox to use for the FW command
5227 * @pf: the PF
5228 * @vf: the VF
5229 * @nparams: the number of parameters
5230 * @params: the parameter names
5231 * @val: the parameter values
01b69614 5232 * @rw: Write and read flag
56d36be4
DM		 5233 *
5234 * Reads the value of FW or device parameters. Up to 7 parameters can be
5235 * queried at once.
5236 */
01b69614
HS		 5237int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
5238 unsigned int vf, unsigned int nparams, const u32 *params,
5239 u32 *val, int rw)
56d36be4
DM		 5240{
5241 int i, ret;
5242 struct fw_params_cmd c;
5243 __be32 *p = &c.param[0].mnem;
5244
5245 if (nparams > 7)
5246 return -EINVAL;
5247
5248 memset(&c, 0, sizeof(c));
f404f80c
HS		 5249 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
5250 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5251 FW_PARAMS_CMD_PFN_V(pf) |
5252 FW_PARAMS_CMD_VFN_V(vf));
5253 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5254
01b69614
HS		 5255 for (i = 0; i < nparams; i++) {
5256 *p++ = cpu_to_be32(*params++);
5257 if (rw)
5258 *p = cpu_to_be32(*(val + i));
5259 p++;
5260 }
56d36be4
DM		 5261
5262 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5263 if (ret == 0)
5264 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
f404f80c 5265 *val++ = be32_to_cpu(*p);
56d36be4
DM		 5266 return ret;
5267}
5268
01b69614
HS		 5269int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
5270 unsigned int vf, unsigned int nparams, const u32 *params,
5271 u32 *val)
5272{
5273 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
5274}
5275
688848b1 5276/**
01b69614 5277 * t4_set_params_timeout - sets FW or device parameters
688848b1
AB		 5278 * @adap: the adapter
5279 * @mbox: mailbox to use for the FW command
5280 * @pf: the PF
5281 * @vf: the VF
5282 * @nparams: the number of parameters
5283 * @params: the parameter names
5284 * @val: the parameter values
01b69614 5285 * @timeout: the timeout time
688848b1 5286 *
688848b1
AB		 5287 * Sets the value of FW or device parameters. Up to 7 parameters can be
5288 * specified at once.
5289 */
01b69614 5290int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
688848b1
AB		 5291 unsigned int pf, unsigned int vf,
5292 unsigned int nparams, const u32 *params,
01b69614 5293 const u32 *val, int timeout)
688848b1
AB		 5294{
5295 struct fw_params_cmd c;
5296 __be32 *p = &c.param[0].mnem;
5297
5298 if (nparams > 7)
5299 return -EINVAL;
5300
5301 memset(&c, 0, sizeof(c));
e2ac9628 5302 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
01b69614
HS		 5303 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5304 FW_PARAMS_CMD_PFN_V(pf) |
5305 FW_PARAMS_CMD_VFN_V(vf));
688848b1
AB		 5306 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5307
5308 while (nparams--) {
5309 *p++ = cpu_to_be32(*params++);
5310 *p++ = cpu_to_be32(*val++);
5311 }
5312
01b69614 5313 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
688848b1
AB		 5314}
5315
56d36be4
DM		 5316/**
5317 * t4_set_params - sets FW or device parameters
5318 * @adap: the adapter
5319 * @mbox: mailbox to use for the FW command
5320 * @pf: the PF
5321 * @vf: the VF
5322 * @nparams: the number of parameters
5323 * @params: the parameter names
5324 * @val: the parameter values
5325 *
5326 * Sets the value of FW or device parameters. Up to 7 parameters can be
5327 * specified at once.
5328 */
5329int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
5330 unsigned int vf, unsigned int nparams, const u32 *params,
5331 const u32 *val)
5332{
01b69614
HS		 5333 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
5334 FW_CMD_MAX_TIMEOUT);
56d36be4
DM		 5335}
5336
5337/**
5338 * t4_cfg_pfvf - configure PF/VF resource limits
5339 * @adap: the adapter
5340 * @mbox: mailbox to use for the FW command
5341 * @pf: the PF being configured
5342 * @vf: the VF being configured
5343 * @txq: the max number of egress queues
5344 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
5345 * @rxqi: the max number of interrupt-capable ingress queues
5346 * @rxq: the max number of interruptless ingress queues
5347 * @tc: the PCI traffic class
5348 * @vi: the max number of virtual interfaces
5349 * @cmask: the channel access rights mask for the PF/VF
5350 * @pmask: the port access rights mask for the PF/VF
5351 * @nexact: the maximum number of exact MPS filters
5352 * @rcaps: read capabilities
5353 * @wxcaps: write/execute capabilities
5354 *
5355 * Configures resource limits and capabilities for a physical or virtual
5356 * function.
5357 */
5358int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
5359 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
5360 unsigned int rxqi, unsigned int rxq, unsigned int tc,
5361 unsigned int vi, unsigned int cmask, unsigned int pmask,
5362 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
5363{
5364 struct fw_pfvf_cmd c;
5365
5366 memset(&c, 0, sizeof(c));
f404f80c
HS		 5367 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
5368 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
5369 FW_PFVF_CMD_VFN_V(vf));
5370 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5371 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
5372 FW_PFVF_CMD_NIQ_V(rxq));
5373 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
5374 FW_PFVF_CMD_PMASK_V(pmask) |
5375 FW_PFVF_CMD_NEQ_V(txq));
5376 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
5377 FW_PFVF_CMD_NVI_V(vi) |
5378 FW_PFVF_CMD_NEXACTF_V(nexact));
5379 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
5380 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
5381 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
56d36be4
DM		 5382 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5383}
5384
5385/**
5386 * t4_alloc_vi - allocate a virtual interface
5387 * @adap: the adapter
5388 * @mbox: mailbox to use for the FW command
5389 * @port: physical port associated with the VI
5390 * @pf: the PF owning the VI
5391 * @vf: the VF owning the VI
5392 * @nmac: number of MAC addresses needed (1 to 5)
5393 * @mac: the MAC addresses of the VI
5394 * @rss_size: size of RSS table slice associated with this VI
5395 *
5396 * Allocates a virtual interface for the given physical port. If @mac is
5397 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
5398 * @mac should be large enough to hold @nmac Ethernet addresses, they are
5399 * stored consecutively so the space needed is @nmac * 6 bytes.
5400 * Returns a negative error number or the non-negative VI id.
5401 */
5402int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
5403 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
5404 unsigned int *rss_size)
5405{
5406 int ret;
5407 struct fw_vi_cmd c;
5408
5409 memset(&c, 0, sizeof(c));
f404f80c
HS		 5410 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
5411 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
5412 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
5413 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
2b5fb1f2 5414 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
56d36be4
DM		 5415 c.nmac = nmac - 1;
5416
5417 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5418 if (ret)
5419 return ret;
5420
5421 if (mac) {
5422 memcpy(mac, c.mac, sizeof(c.mac));
5423 switch (nmac) {
5424 case 5:
5425 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
5426 case 4:
5427 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
5428 case 3:
5429 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
5430 case 2:
5431 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
5432 }
5433 }
5434 if (rss_size)
f404f80c
HS		 5435 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
5436 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
56d36be4
DM		 5437}
5438
4f3a0fcf
HS		 5439/**
5440 * t4_free_vi - free a virtual interface
5441 * @adap: the adapter
5442 * @mbox: mailbox to use for the FW command
5443 * @pf: the PF owning the VI
5444 * @vf: the VF owning the VI
5445 * @viid: virtual interface identifiler
5446 *
5447 * Free a previously allocated virtual interface.
5448 */
5449int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
5450 unsigned int vf, unsigned int viid)
5451{
5452 struct fw_vi_cmd c;
5453
5454 memset(&c, 0, sizeof(c));
5455 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
5456 FW_CMD_REQUEST_F |
5457 FW_CMD_EXEC_F |
5458 FW_VI_CMD_PFN_V(pf) |
5459 FW_VI_CMD_VFN_V(vf));
5460 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
5461 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
5462
5463 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
56d36be4
DM		 5464}
5465
56d36be4
DM		 5466/**
5467 * t4_set_rxmode - set Rx properties of a virtual interface
5468 * @adap: the adapter
5469 * @mbox: mailbox to use for the FW command
5470 * @viid: the VI id
5471 * @mtu: the new MTU or -1
5472 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
5473 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
5474 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
f8f5aafa 5475 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
56d36be4
DM		 5476 * @sleep_ok: if true we may sleep while awaiting command completion
5477 *
5478 * Sets Rx properties of a virtual interface.
5479 */
5480int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 5481 int mtu, int promisc, int all_multi, int bcast, int vlanex,
5482 bool sleep_ok)
56d36be4
DM		 5483{
5484 struct fw_vi_rxmode_cmd c;
5485
5486 /* convert to FW values */
5487 if (mtu < 0)
5488 mtu = FW_RXMODE_MTU_NO_CHG;
5489 if (promisc < 0)
2b5fb1f2 5490 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
56d36be4 5491 if (all_multi < 0)
2b5fb1f2 5492 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
56d36be4 5493 if (bcast < 0)
2b5fb1f2 5494 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
f8f5aafa 5495 if (vlanex < 0)
2b5fb1f2 5496 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
56d36be4
DM		 5497
5498 memset(&c, 0, sizeof(c));
f404f80c
HS		 5499 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
5500 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5501 FW_VI_RXMODE_CMD_VIID_V(viid));
5502 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5503 c.mtu_to_vlanexen =
5504 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
5505 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
5506 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
5507 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
5508 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
56d36be4
DM		 5509 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
5510}
5511
5512/**
5513 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
5514 * @adap: the adapter
5515 * @mbox: mailbox to use for the FW command
5516 * @viid: the VI id
5517 * @free: if true any existing filters for this VI id are first removed
5518 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
5519 * @addr: the MAC address(es)
5520 * @idx: where to store the index of each allocated filter
5521 * @hash: pointer to hash address filter bitmap
5522 * @sleep_ok: call is allowed to sleep
5523 *
5524 * Allocates an exact-match filter for each of the supplied addresses and
5525 * sets it to the corresponding address. If @idx is not %NULL it should
5526 * have at least @naddr entries, each of which will be set to the index of
5527 * the filter allocated for the corresponding MAC address. If a filter
5528 * could not be allocated for an address its index is set to 0xffff.
5529 * If @hash is not %NULL addresses that fail to allocate an exact filter
5530 * are hashed and update the hash filter bitmap pointed at by @hash.
5531 *
5532 * Returns a negative error number or the number of filters allocated.
5533 */
5534int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
5535 unsigned int viid, bool free, unsigned int naddr,
5536 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
5537{
3ccc6cf7 5538 int offset, ret = 0;
56d36be4 5539 struct fw_vi_mac_cmd c;
3ccc6cf7
HS		 5540 unsigned int nfilters = 0;
5541 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
5542 unsigned int rem = naddr;
56d36be4 5543
3ccc6cf7 5544 if (naddr > max_naddr)
56d36be4
DM		 5545 return -EINVAL;
5546
3ccc6cf7
HS		 5547 for (offset = 0; offset < naddr ; /**/) {
5548 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
5549 rem : ARRAY_SIZE(c.u.exact));
5550 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
5551 u.exact[fw_naddr]), 16);
5552 struct fw_vi_mac_exact *p;
5553 int i;
56d36be4 5554
3ccc6cf7
HS		 5555 memset(&c, 0, sizeof(c));
5556 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
5557 FW_CMD_REQUEST_F |
5558 FW_CMD_WRITE_F |
5559 FW_CMD_EXEC_V(free) |
5560 FW_VI_MAC_CMD_VIID_V(viid));
5561 c.freemacs_to_len16 =
5562 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
5563 FW_CMD_LEN16_V(len16));
5564
5565 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
5566 p->valid_to_idx =
5567 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
5568 FW_VI_MAC_CMD_IDX_V(
5569 FW_VI_MAC_ADD_MAC));
5570 memcpy(p->macaddr, addr[offset + i],
5571 sizeof(p->macaddr));
5572 }
56d36be4 5573
3ccc6cf7
HS		 5574 /* It's okay if we run out of space in our MAC address arena.
5575 * Some of the addresses we submit may get stored so we need
5576 * to run through the reply to see what the results were ...
5577 */
5578 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
5579 if (ret && ret != -FW_ENOMEM)
5580 break;
56d36be4 5581
3ccc6cf7
HS		 5582 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
5583 u16 index = FW_VI_MAC_CMD_IDX_G(
5584 be16_to_cpu(p->valid_to_idx));
5585
5586 if (idx)
5587 idx[offset + i] = (index >= max_naddr ?
5588 0xffff : index);
5589 if (index < max_naddr)
5590 nfilters++;
5591 else if (hash)
5592 *hash |= (1ULL <<
5593 hash_mac_addr(addr[offset + i]));
5594 }
56d36be4 5595
3ccc6cf7
HS		 5596 free = false;
5597 offset += fw_naddr;
5598 rem -= fw_naddr;
56d36be4 5599 }
3ccc6cf7
HS		 5600
5601 if (ret == 0 || ret == -FW_ENOMEM)
5602 ret = nfilters;
56d36be4
DM		 5603 return ret;
5604}
5605
5606/**
5607 * t4_change_mac - modifies the exact-match filter for a MAC address
5608 * @adap: the adapter
5609 * @mbox: mailbox to use for the FW command
5610 * @viid: the VI id
5611 * @idx: index of existing filter for old value of MAC address, or -1
5612 * @addr: the new MAC address value
5613 * @persist: whether a new MAC allocation should be persistent
5614 * @add_smt: if true also add the address to the HW SMT
5615 *
5616 * Modifies an exact-match filter and sets it to the new MAC address.
5617 * Note that in general it is not possible to modify the value of a given
5618 * filter so the generic way to modify an address filter is to free the one
5619 * being used by the old address value and allocate a new filter for the
5620 * new address value. @idx can be -1 if the address is a new addition.
5621 *
5622 * Returns a negative error number or the index of the filter with the new
5623 * MAC value.
5624 */
5625int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
5626 int idx, const u8 *addr, bool persist, bool add_smt)
5627{
5628 int ret, mode;
5629 struct fw_vi_mac_cmd c;
5630 struct fw_vi_mac_exact *p = c.u.exact;
3ccc6cf7 5631 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
56d36be4
DM		 5632
5633 if (idx < 0) /* new allocation */
5634 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
5635 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
5636
5637 memset(&c, 0, sizeof(c));
f404f80c
HS		 5638 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
5639 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5640 FW_VI_MAC_CMD_VIID_V(viid));
5641 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
5642 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
5643 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
5644 FW_VI_MAC_CMD_IDX_V(idx));
56d36be4
DM		 5645 memcpy(p->macaddr, addr, sizeof(p->macaddr));
5646
5647 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5648 if (ret == 0) {
f404f80c 5649 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
0a57a536 5650 if (ret >= max_mac_addr)
56d36be4
DM		 5651 ret = -ENOMEM;
5652 }
5653 return ret;
5654}
5655
5656/**
5657 * t4_set_addr_hash - program the MAC inexact-match hash filter
5658 * @adap: the adapter
5659 * @mbox: mailbox to use for the FW command
5660 * @viid: the VI id
5661 * @ucast: whether the hash filter should also match unicast addresses
5662 * @vec: the value to be written to the hash filter
5663 * @sleep_ok: call is allowed to sleep
5664 *
5665 * Sets the 64-bit inexact-match hash filter for a virtual interface.
5666 */
5667int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
5668 bool ucast, u64 vec, bool sleep_ok)
5669{
5670 struct fw_vi_mac_cmd c;
5671
5672 memset(&c, 0, sizeof(c));
f404f80c
HS		 5673 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
5674 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5675 FW_VI_ENABLE_CMD_VIID_V(viid));
5676 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
5677 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
5678 FW_CMD_LEN16_V(1));
56d36be4
DM		 5679 c.u.hash.hashvec = cpu_to_be64(vec);
5680 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
5681}
5682
688848b1
AB		 5683/**
5684 * t4_enable_vi_params - enable/disable a virtual interface
5685 * @adap: the adapter
5686 * @mbox: mailbox to use for the FW command
5687 * @viid: the VI id
5688 * @rx_en: 1=enable Rx, 0=disable Rx
5689 * @tx_en: 1=enable Tx, 0=disable Tx
5690 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
5691 *
5692 * Enables/disables a virtual interface. Note that setting DCB Enable
5693 * only makes sense when enabling a Virtual Interface ...
5694 */
5695int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
5696 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
5697{
5698 struct fw_vi_enable_cmd c;
5699
5700 memset(&c, 0, sizeof(c));
f404f80c
HS		 5701 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
5702 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
5703 FW_VI_ENABLE_CMD_VIID_V(viid));
5704 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
5705 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
5706 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
5707 FW_LEN16(c));
30f00847 5708 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
688848b1
AB		 5709}
5710
56d36be4
DM		 5711/**
5712 * t4_enable_vi - enable/disable a virtual interface
5713 * @adap: the adapter
5714 * @mbox: mailbox to use for the FW command
5715 * @viid: the VI id
5716 * @rx_en: 1=enable Rx, 0=disable Rx
5717 * @tx_en: 1=enable Tx, 0=disable Tx
5718 *
5719 * Enables/disables a virtual interface.
5720 */
5721int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
5722 bool rx_en, bool tx_en)
5723{
688848b1 5724 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
56d36be4
DM		 5725}
5726
5727/**
5728 * t4_identify_port - identify a VI's port by blinking its LED
5729 * @adap: the adapter
5730 * @mbox: mailbox to use for the FW command
5731 * @viid: the VI id
5732 * @nblinks: how many times to blink LED at 2.5 Hz
5733 *
5734 * Identifies a VI's port by blinking its LED.
5735 */
5736int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
5737 unsigned int nblinks)
5738{
5739 struct fw_vi_enable_cmd c;
5740
0062b15c 5741 memset(&c, 0, sizeof(c));
f404f80c
HS		 5742 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
5743 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
5744 FW_VI_ENABLE_CMD_VIID_V(viid));
5745 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
5746 c.blinkdur = cpu_to_be16(nblinks);
56d36be4 5747 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
56d36be4
DM		 5748}
5749
5750/**
5751 * t4_iq_free - free an ingress queue and its FLs
5752 * @adap: the adapter
5753 * @mbox: mailbox to use for the FW command
5754 * @pf: the PF owning the queues
5755 * @vf: the VF owning the queues
5756 * @iqtype: the ingress queue type
5757 * @iqid: ingress queue id
5758 * @fl0id: FL0 queue id or 0xffff if no attached FL0
5759 * @fl1id: FL1 queue id or 0xffff if no attached FL1
5760 *
5761 * Frees an ingress queue and its associated FLs, if any.
5762 */
5763int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
5764 unsigned int vf, unsigned int iqtype, unsigned int iqid,
5765 unsigned int fl0id, unsigned int fl1id)
5766{
5767 struct fw_iq_cmd c;
5768
5769 memset(&c, 0, sizeof(c));
f404f80c
HS		 5770 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
5771 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
5772 FW_IQ_CMD_VFN_V(vf));
5773 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
5774 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
5775 c.iqid = cpu_to_be16(iqid);
5776 c.fl0id = cpu_to_be16(fl0id);
5777 c.fl1id = cpu_to_be16(fl1id);
56d36be4
DM		 5778 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5779}
5780
5781/**
5782 * t4_eth_eq_free - free an Ethernet egress queue
5783 * @adap: the adapter
5784 * @mbox: mailbox to use for the FW command
5785 * @pf: the PF owning the queue
5786 * @vf: the VF owning the queue
5787 * @eqid: egress queue id
5788 *
5789 * Frees an Ethernet egress queue.
5790 */
5791int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
5792 unsigned int vf, unsigned int eqid)
5793{
5794 struct fw_eq_eth_cmd c;
5795
5796 memset(&c, 0, sizeof(c));
f404f80c
HS		 5797 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
5798 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
5799 FW_EQ_ETH_CMD_PFN_V(pf) |
5800 FW_EQ_ETH_CMD_VFN_V(vf));
5801 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
5802 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
56d36be4
DM		 5803 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5804}
5805
5806/**
5807 * t4_ctrl_eq_free - free a control egress queue
5808 * @adap: the adapter
5809 * @mbox: mailbox to use for the FW command
5810 * @pf: the PF owning the queue
5811 * @vf: the VF owning the queue
5812 * @eqid: egress queue id
5813 *
5814 * Frees a control egress queue.
5815 */
5816int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
5817 unsigned int vf, unsigned int eqid)
5818{
5819 struct fw_eq_ctrl_cmd c;
5820
5821 memset(&c, 0, sizeof(c));
f404f80c
HS		 5822 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
5823 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
5824 FW_EQ_CTRL_CMD_PFN_V(pf) |
5825 FW_EQ_CTRL_CMD_VFN_V(vf));
5826 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
5827 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
56d36be4
DM		 5828 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5829}
5830
5831/**
5832 * t4_ofld_eq_free - free an offload egress queue
5833 * @adap: the adapter
5834 * @mbox: mailbox to use for the FW command
5835 * @pf: the PF owning the queue
5836 * @vf: the VF owning the queue
5837 * @eqid: egress queue id
5838 *
5839 * Frees a control egress queue.
5840 */
5841int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
5842 unsigned int vf, unsigned int eqid)
5843{
5844 struct fw_eq_ofld_cmd c;
5845
5846 memset(&c, 0, sizeof(c));
f404f80c
HS		 5847 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
5848 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
5849 FW_EQ_OFLD_CMD_PFN_V(pf) |
5850 FW_EQ_OFLD_CMD_VFN_V(vf));
5851 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
5852 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
56d36be4
DM		 5853 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5854}
5855
5856/**
5857 * t4_handle_fw_rpl - process a FW reply message
5858 * @adap: the adapter
5859 * @rpl: start of the FW message
5860 *
5861 * Processes a FW message, such as link state change messages.
5862 */
5863int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
5864{
5865 u8 opcode = *(const u8 *)rpl;
5866
5867 if (opcode == FW_PORT_CMD) { /* link/module state change message */
5868 int speed = 0, fc = 0;
5869 const struct fw_port_cmd *p = (void *)rpl;
f404f80c 5870 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
56d36be4
DM		 5871 int port = adap->chan_map[chan];
5872 struct port_info *pi = adap2pinfo(adap, port);
5873 struct link_config *lc = &pi->link_cfg;
f404f80c 5874 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
2b5fb1f2
HS		 5875 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
5876 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
56d36be4 5877
2b5fb1f2 5878 if (stat & FW_PORT_CMD_RXPAUSE_F)
56d36be4 5879 fc |= PAUSE_RX;
2b5fb1f2 5880 if (stat & FW_PORT_CMD_TXPAUSE_F)
56d36be4 5881 fc |= PAUSE_TX;
2b5fb1f2 5882 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
e8b39015 5883 speed = 100;
2b5fb1f2 5884 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
e8b39015 5885 speed = 1000;
2b5fb1f2 5886 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
e8b39015 5887 speed = 10000;
2b5fb1f2 5888 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
e8b39015 5889 speed = 40000;
56d36be4
DM		 5890
5891 if (link_ok != lc->link_ok || speed != lc->speed ||
5892 fc != lc->fc) { /* something changed */
5893 lc->link_ok = link_ok;
5894 lc->speed = speed;
5895 lc->fc = fc;
444018a7 5896 lc->supported = be16_to_cpu(p->u.info.pcap);
56d36be4
DM		 5897 t4_os_link_changed(adap, port, link_ok);
5898 }
5899 if (mod != pi->mod_type) {
5900 pi->mod_type = mod;
5901 t4_os_portmod_changed(adap, port);
5902 }
5903 }
5904 return 0;
5905}
5906
1dd06ae8 5907static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
56d36be4
DM		 5908{
5909 u16 val;
56d36be4 5910
e5c8ae5f
JL		 5911 if (pci_is_pcie(adapter->pdev)) {
5912 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
56d36be4
DM		 5913 p->speed = val & PCI_EXP_LNKSTA_CLS;
5914 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
5915 }
5916}
5917
5918/**
5919 * init_link_config - initialize a link's SW state
5920 * @lc: structure holding the link state
5921 * @caps: link capabilities
5922 *
5923 * Initializes the SW state maintained for each link, including the link's
5924 * capabilities and default speed/flow-control/autonegotiation settings.
5925 */
1dd06ae8 5926static void init_link_config(struct link_config *lc, unsigned int caps)
56d36be4
DM		 5927{
5928 lc->supported = caps;
5929 lc->requested_speed = 0;
5930 lc->speed = 0;
5931 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
5932 if (lc->supported & FW_PORT_CAP_ANEG) {
5933 lc->advertising = lc->supported & ADVERT_MASK;
5934 lc->autoneg = AUTONEG_ENABLE;
5935 lc->requested_fc |= PAUSE_AUTONEG;
5936 } else {
5937 lc->advertising = 0;
5938 lc->autoneg = AUTONEG_DISABLE;
5939 }
5940}
5941
8203b509
HS		 5942#define CIM_PF_NOACCESS 0xeeeeeeee
5943
5944int t4_wait_dev_ready(void __iomem *regs)
56d36be4 5945{
8203b509
HS		 5946 u32 whoami;
5947
0d804338 5948 whoami = readl(regs + PL_WHOAMI_A);
8203b509 5949 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
56d36be4 5950 return 0;
8203b509 5951
56d36be4 5952 msleep(500);
0d804338 5953 whoami = readl(regs + PL_WHOAMI_A);
8203b509 5954 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
56d36be4
DM		 5955}
5956
fe2ee139
HS		 5957struct flash_desc {
5958 u32 vendor_and_model_id;
5959 u32 size_mb;
5960};
5961
91744948 5962static int get_flash_params(struct adapter *adap)
900a6596 5963{
fe2ee139
HS		 5964 /* Table for non-Numonix supported flash parts. Numonix parts are left
5965 * to the preexisting code. All flash parts have 64KB sectors.
5966 */
5967 static struct flash_desc supported_flash[] = {
5968 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
5969 };
5970
900a6596
DM		 5971 int ret;
5972 u32 info;
5973
5974 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
5975 if (!ret)
5976 ret = sf1_read(adap, 3, 0, 1, &info);
0d804338 5977 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
900a6596
DM		 5978 if (ret)
5979 return ret;
5980
fe2ee139
HS		 5981 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
5982 if (supported_flash[ret].vendor_and_model_id == info) {
5983 adap->params.sf_size = supported_flash[ret].size_mb;
5984 adap->params.sf_nsec =
5985 adap->params.sf_size / SF_SEC_SIZE;
5986 return 0;
5987 }
5988
900a6596
DM		 5989 if ((info & 0xff) != 0x20) /* not a Numonix flash */
5990 return -EINVAL;
5991 info >>= 16; /* log2 of size */
5992 if (info >= 0x14 && info < 0x18)
5993 adap->params.sf_nsec = 1 << (info - 16);
5994 else if (info == 0x18)
5995 adap->params.sf_nsec = 64;
5996 else
5997 return -EINVAL;
5998 adap->params.sf_size = 1 << info;
5999 adap->params.sf_fw_start =
89c3a86c 6000 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
c290607e
HS		 6001
6002 if (adap->params.sf_size < FLASH_MIN_SIZE)
6003 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
6004 adap->params.sf_size, FLASH_MIN_SIZE);
900a6596
DM		 6005 return 0;
6006}
6007
eca0f6ee
HS		 6008static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
6009{
6010 u16 val;
6011 u32 pcie_cap;
6012
6013 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6014 if (pcie_cap) {
6015 pci_read_config_word(adapter->pdev,
6016 pcie_cap + PCI_EXP_DEVCTL2, &val);
6017 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
6018 val |= range;
6019 pci_write_config_word(adapter->pdev,
6020 pcie_cap + PCI_EXP_DEVCTL2, val);
6021 }
6022}
6023
56d36be4
DM		 6024/**
6025 * t4_prep_adapter - prepare SW and HW for operation
6026 * @adapter: the adapter
6027 * @reset: if true perform a HW reset
6028 *
6029 * Initialize adapter SW state for the various HW modules, set initial
6030 * values for some adapter tunables, take PHYs out of reset, and
6031 * initialize the MDIO interface.
6032 */
91744948 6033int t4_prep_adapter(struct adapter *adapter)
56d36be4 6034{
0a57a536
SR		 6035 int ret, ver;
6036 uint16_t device_id;
d14807dd 6037 u32 pl_rev;
56d36be4 6038
56d36be4 6039 get_pci_mode(adapter, &adapter->params.pci);
0d804338 6040 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
56d36be4 6041
900a6596
DM		 6042 ret = get_flash_params(adapter);
6043 if (ret < 0) {
6044 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
6045 return ret;
6046 }
6047
0a57a536
SR		 6048 /* Retrieve adapter's device ID
6049 */
6050 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
6051 ver = device_id >> 12;
d14807dd 6052 adapter->params.chip = 0;
0a57a536
SR		 6053 switch (ver) {
6054 case CHELSIO_T4:
d14807dd 6055 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
3ccc6cf7
HS		 6056 adapter->params.arch.sge_fl_db = DBPRIO_F;
6057 adapter->params.arch.mps_tcam_size =
6058 NUM_MPS_CLS_SRAM_L_INSTANCES;
6059 adapter->params.arch.mps_rplc_size = 128;
6060 adapter->params.arch.nchan = NCHAN;
6061 adapter->params.arch.vfcount = 128;
0a57a536
SR		 6062 break;
6063 case CHELSIO_T5:
d14807dd 6064 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3ccc6cf7
HS		 6065 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
6066 adapter->params.arch.mps_tcam_size =
6067 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6068 adapter->params.arch.mps_rplc_size = 128;
6069 adapter->params.arch.nchan = NCHAN;
6070 adapter->params.arch.vfcount = 128;
6071 break;
6072 case CHELSIO_T6:
6073 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
6074 adapter->params.arch.sge_fl_db = 0;
6075 adapter->params.arch.mps_tcam_size =
6076 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6077 adapter->params.arch.mps_rplc_size = 256;
6078 adapter->params.arch.nchan = 2;
6079 adapter->params.arch.vfcount = 256;
0a57a536
SR		 6080 break;
6081 default:
6082 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
6083 device_id);
6084 return -EINVAL;
6085 }
6086
f1ff24aa 6087 adapter->params.cim_la_size = CIMLA_SIZE;
56d36be4
DM		 6088 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
6089
6090 /*
6091 * Default port for debugging in case we can't reach FW.
6092 */
6093 adapter->params.nports = 1;
6094 adapter->params.portvec = 1;
636f9d37 6095 adapter->params.vpd.cclk = 50000;
eca0f6ee
HS		 6096
6097 /* Set pci completion timeout value to 4 seconds. */
6098 set_pcie_completion_timeout(adapter, 0xd);
56d36be4
DM		 6099 return 0;
6100}
6101
e85c9a7a 6102/**
b2612722 6103 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
e85c9a7a
HS		 6104 * @adapter: the adapter
6105 * @qid: the Queue ID
6106 * @qtype: the Ingress or Egress type for @qid
66cf188e 6107 * @user: true if this request is for a user mode queue
e85c9a7a
HS		 6108 * @pbar2_qoffset: BAR2 Queue Offset
6109 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
6110 *
6111 * Returns the BAR2 SGE Queue Registers information associated with the
6112 * indicated Absolute Queue ID. These are passed back in return value
6113 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
6114 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
6115 *
6116 * This may return an error which indicates that BAR2 SGE Queue
6117 * registers aren't available. If an error is not returned, then the
6118 * following values are returned:
6119 *
6120 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
6121 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
6122 *
6123 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
6124 * require the "Inferred Queue ID" ability may be used. E.g. the
6125 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
6126 * then these "Inferred Queue ID" register may not be used.
6127 */
b2612722 6128int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 6129 unsigned int qid,
6130 enum t4_bar2_qtype qtype,
66cf188e 6131 int user,
e85c9a7a
HS		 6132 u64 *pbar2_qoffset,
6133 unsigned int *pbar2_qid)
6134{
6135 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
6136 u64 bar2_page_offset, bar2_qoffset;
6137 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
6138
66cf188e
H		 6139 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
6140 if (!user && is_t4(adapter->params.chip))
e85c9a7a
HS		 6141 return -EINVAL;
6142
6143 /* Get our SGE Page Size parameters.
6144 */
6145 page_shift = adapter->params.sge.hps + 10;
6146 page_size = 1 << page_shift;
6147
6148 /* Get the right Queues per Page parameters for our Queue.
6149 */
6150 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
6151 ? adapter->params.sge.eq_qpp
6152 : adapter->params.sge.iq_qpp);
6153 qpp_mask = (1 << qpp_shift) - 1;
6154
6155 /* Calculate the basics of the BAR2 SGE Queue register area:
6156 * o The BAR2 page the Queue registers will be in.
6157 * o The BAR2 Queue ID.
6158 * o The BAR2 Queue ID Offset into the BAR2 page.
6159 */
513d1a1d 6160 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
e85c9a7a
HS		 6161 bar2_qid = qid & qpp_mask;
6162 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
6163
6164 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
6165 * hardware will infer the Absolute Queue ID simply from the writes to
6166 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
6167 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
6168 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
6169 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
6170 * from the BAR2 Page and BAR2 Queue ID.
6171 *
6172 * One important censequence of this is that some BAR2 SGE registers
6173 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
6174 * there. But other registers synthesize the SGE Queue ID purely
6175 * from the writes to the registers -- the Write Combined Doorbell
6176 * Buffer is a good example. These BAR2 SGE Registers are only
6177 * available for those BAR2 SGE Register areas where the SGE Absolute
6178 * Queue ID can be inferred from simple writes.
6179 */
6180 bar2_qoffset = bar2_page_offset;
6181 bar2_qinferred = (bar2_qid_offset < page_size);
6182 if (bar2_qinferred) {
6183 bar2_qoffset += bar2_qid_offset;
6184 bar2_qid = 0;
6185 }
6186
6187 *pbar2_qoffset = bar2_qoffset;
6188 *pbar2_qid = bar2_qid;
6189 return 0;
6190}
6191
ae469b68
HS		 6192/**
6193 * t4_init_devlog_params - initialize adapter->params.devlog
6194 * @adap: the adapter
6195 *
6196 * Initialize various fields of the adapter's Firmware Device Log
6197 * Parameters structure.
6198 */
6199int t4_init_devlog_params(struct adapter *adap)
6200{
6201 struct devlog_params *dparams = &adap->params.devlog;
6202 u32 pf_dparams;
6203 unsigned int devlog_meminfo;
6204 struct fw_devlog_cmd devlog_cmd;
6205 int ret;
6206
6207 /* If we're dealing with newer firmware, the Device Log Paramerters
6208 * are stored in a designated register which allows us to access the
6209 * Device Log even if we can't talk to the firmware.
6210 */
6211 pf_dparams =
6212 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
6213 if (pf_dparams) {
6214 unsigned int nentries, nentries128;
6215
6216 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
6217 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
6218
6219 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
6220 nentries = (nentries128 + 1) * 128;
6221 dparams->size = nentries * sizeof(struct fw_devlog_e);
6222
6223 return 0;
6224 }
6225
6226 /* Otherwise, ask the firmware for it's Device Log Parameters.
6227 */
6228 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
f404f80c
HS		 6229 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
6230 FW_CMD_REQUEST_F | FW_CMD_READ_F);
6231 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
ae469b68
HS		 6232 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
6233 &devlog_cmd);
6234 if (ret)
6235 return ret;
6236
f404f80c
HS		 6237 devlog_meminfo =
6238 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
ae469b68
HS		 6239 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
6240 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
f404f80c 6241 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
ae469b68
HS		 6242
6243 return 0;
6244}
6245
e85c9a7a
HS		 6246/**
6247 * t4_init_sge_params - initialize adap->params.sge
6248 * @adapter: the adapter
6249 *
6250 * Initialize various fields of the adapter's SGE Parameters structure.
6251 */
6252int t4_init_sge_params(struct adapter *adapter)
6253{
6254 struct sge_params *sge_params = &adapter->params.sge;
6255 u32 hps, qpp;
6256 unsigned int s_hps, s_qpp;
6257
6258 /* Extract the SGE Page Size for our PF.
6259 */
f612b815 6260 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
e85c9a7a 6261 s_hps = (HOSTPAGESIZEPF0_S +
b2612722 6262 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
e85c9a7a
HS		 6263 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
6264
6265 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
6266 */
6267 s_qpp = (QUEUESPERPAGEPF0_S +
b2612722 6268 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
f612b815
HS		 6269 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
6270 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
f061de42 6271 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
f612b815 6272 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
e85c9a7a
HS		 6273
6274 return 0;
6275}
6276
dcf7b6f5
KS		 6277/**
6278 * t4_init_tp_params - initialize adap->params.tp
6279 * @adap: the adapter
6280 *
6281 * Initialize various fields of the adapter's TP Parameters structure.
6282 */
6283int t4_init_tp_params(struct adapter *adap)
6284{
6285 int chan;
6286 u32 v;
6287
837e4a42
HS		 6288 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
6289 adap->params.tp.tre = TIMERRESOLUTION_G(v);
6290 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
dcf7b6f5
KS		 6291
6292 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
6293 for (chan = 0; chan < NCHAN; chan++)
6294 adap->params.tp.tx_modq[chan] = chan;
6295
6296 /* Cache the adapter's Compressed Filter Mode and global Incress
6297 * Configuration.
6298 */
c1e9af0c
HS		 6299 if (adap->flags & FW_OK) {
6300 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
6301 TP_VLAN_PRI_MAP_A, 1);
6302 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
6303 TP_INGRESS_CONFIG_A, 1);
6304 } else {
6305 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
6306 &adap->params.tp.vlan_pri_map, 1,
6307 TP_VLAN_PRI_MAP_A);
6308 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
6309 &adap->params.tp.ingress_config, 1,
6310 TP_INGRESS_CONFIG_A);
6311 }
dcf7b6f5
KS		 6312
6313 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
6314 * shift positions of several elements of the Compressed Filter Tuple
6315 * for this adapter which we need frequently ...
6316 */
0d804338
HS		 6317 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
6318 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
6319 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
dcf7b6f5 6320 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
0d804338 6321 PROTOCOL_F);
dcf7b6f5
KS		 6322
6323 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
dbedd44e 6324 * represents the presence of an Outer VLAN instead of a VNIC ID.
dcf7b6f5 6325 */
0d804338 6326 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
dcf7b6f5
KS		 6327 adap->params.tp.vnic_shift = -1;
6328
6329 return 0;
6330}
6331
6332/**
6333 * t4_filter_field_shift - calculate filter field shift
6334 * @adap: the adapter
6335 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
6336 *
6337 * Return the shift position of a filter field within the Compressed
6338 * Filter Tuple. The filter field is specified via its selection bit
6339 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
6340 */
6341int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
6342{
6343 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
6344 unsigned int sel;
6345 int field_shift;
6346
6347 if ((filter_mode & filter_sel) == 0)
6348 return -1;
6349
6350 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
6351 switch (filter_mode & sel) {
0d804338
HS		 6352 case FCOE_F:
6353 field_shift += FT_FCOE_W;
dcf7b6f5 6354 break;
0d804338
HS		 6355 case PORT_F:
6356 field_shift += FT_PORT_W;
dcf7b6f5 6357 break;
0d804338
HS		 6358 case VNIC_ID_F:
6359 field_shift += FT_VNIC_ID_W;
dcf7b6f5 6360 break;
0d804338
HS		 6361 case VLAN_F:
6362 field_shift += FT_VLAN_W;
dcf7b6f5 6363 break;
0d804338
HS		 6364 case TOS_F:
6365 field_shift += FT_TOS_W;
dcf7b6f5 6366 break;
0d804338
HS		 6367 case PROTOCOL_F:
6368 field_shift += FT_PROTOCOL_W;
dcf7b6f5 6369 break;
0d804338
HS		 6370 case ETHERTYPE_F:
6371 field_shift += FT_ETHERTYPE_W;
dcf7b6f5 6372 break;
0d804338
HS		 6373 case MACMATCH_F:
6374 field_shift += FT_MACMATCH_W;
dcf7b6f5 6375 break;
0d804338
HS		 6376 case MPSHITTYPE_F:
6377 field_shift += FT_MPSHITTYPE_W;
dcf7b6f5 6378 break;
0d804338
HS		 6379 case FRAGMENTATION_F:
6380 field_shift += FT_FRAGMENTATION_W;
dcf7b6f5
KS		 6381 break;
6382 }
6383 }
6384 return field_shift;
6385}
6386
c035e183
HS		 6387int t4_init_rss_mode(struct adapter *adap, int mbox)
6388{
6389 int i, ret;
6390 struct fw_rss_vi_config_cmd rvc;
6391
6392 memset(&rvc, 0, sizeof(rvc));
6393
6394 for_each_port(adap, i) {
6395 struct port_info *p = adap2pinfo(adap, i);
6396
f404f80c
HS		 6397 rvc.op_to_viid =
6398 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
6399 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6400 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
6401 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
c035e183
HS		 6402 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
6403 if (ret)
6404 return ret;
f404f80c 6405 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
c035e183
HS		 6406 }
6407 return 0;
6408}
6409
91744948 6410int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
56d36be4
DM		 6411{
6412 u8 addr[6];
6413 int ret, i, j = 0;
6414 struct fw_port_cmd c;
f796564a 6415 struct fw_rss_vi_config_cmd rvc;
56d36be4
DM		 6416
6417 memset(&c, 0, sizeof(c));
f796564a 6418 memset(&rvc, 0, sizeof(rvc));
56d36be4
DM		 6419
6420 for_each_port(adap, i) {
6421 unsigned int rss_size;
6422 struct port_info *p = adap2pinfo(adap, i);
6423
6424 while ((adap->params.portvec & (1 << j)) == 0)
6425 j++;
6426
f404f80c
HS		 6427 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
6428 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6429 FW_PORT_CMD_PORTID_V(j));
6430 c.action_to_len16 = cpu_to_be32(
2b5fb1f2 6431 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
56d36be4
DM		 6432 FW_LEN16(c));
6433 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6434 if (ret)
6435 return ret;
6436
6437 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
6438 if (ret < 0)
6439 return ret;
6440
6441 p->viid = ret;
6442 p->tx_chan = j;
6443 p->lport = j;
6444 p->rss_size = rss_size;
6445 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
40c9f8ab 6446 adap->port[i]->dev_port = j;
56d36be4 6447
f404f80c 6448 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
2b5fb1f2
HS		 6449 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
6450 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
6451 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
a0881cab 6452 p->mod_type = FW_PORT_MOD_TYPE_NA;
56d36be4 6453
f404f80c
HS		 6454 rvc.op_to_viid =
6455 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
6456 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6457 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
6458 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
f796564a
DM		 6459 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
6460 if (ret)
6461 return ret;
f404f80c 6462 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
f796564a 6463
f404f80c 6464 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
56d36be4
DM		 6465 j++;
6466 }
6467 return 0;
6468}
f1ff24aa 6469
74b3092c
HS		 6470/**
6471 * t4_read_cimq_cfg - read CIM queue configuration
6472 * @adap: the adapter
6473 * @base: holds the queue base addresses in bytes
6474 * @size: holds the queue sizes in bytes
6475 * @thres: holds the queue full thresholds in bytes
6476 *
6477 * Returns the current configuration of the CIM queues, starting with
6478 * the IBQs, then the OBQs.
6479 */
6480void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
6481{
6482 unsigned int i, v;
6483 int cim_num_obq = is_t4(adap->params.chip) ?
6484 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
6485
6486 for (i = 0; i < CIM_NUM_IBQ; i++) {
6487 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
6488 QUENUMSELECT_V(i));
6489 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
6490 /* value is in 256-byte units */
6491 *base++ = CIMQBASE_G(v) * 256;
6492 *size++ = CIMQSIZE_G(v) * 256;
6493 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
6494 }
6495 for (i = 0; i < cim_num_obq; i++) {
6496 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
6497 QUENUMSELECT_V(i));
6498 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
6499 /* value is in 256-byte units */
6500 *base++ = CIMQBASE_G(v) * 256;
6501 *size++ = CIMQSIZE_G(v) * 256;
6502 }
6503}
6504
e5f0e43b
HS		 6505/**
6506 * t4_read_cim_ibq - read the contents of a CIM inbound queue
6507 * @adap: the adapter
6508 * @qid: the queue index
6509 * @data: where to store the queue contents
6510 * @n: capacity of @data in 32-bit words
6511 *
6512 * Reads the contents of the selected CIM queue starting at address 0 up
6513 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
6514 * error and the number of 32-bit words actually read on success.
6515 */
6516int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
6517{
6518 int i, err, attempts;
6519 unsigned int addr;
6520 const unsigned int nwords = CIM_IBQ_SIZE * 4;
6521
6522 if (qid > 5 || (n & 3))
6523 return -EINVAL;
6524
6525 addr = qid * nwords;
6526 if (n > nwords)
6527 n = nwords;
6528
6529 /* It might take 3-10ms before the IBQ debug read access is allowed.
6530 * Wait for 1 Sec with a delay of 1 usec.
6531 */
6532 attempts = 1000000;
6533
6534 for (i = 0; i < n; i++, addr++) {
6535 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
6536 IBQDBGEN_F);
6537 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
6538 attempts, 1);
6539 if (err)
6540 return err;
6541 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
6542 }
6543 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
c778af7d
HS		 6544 return i;
6545}
6546
6547/**
6548 * t4_read_cim_obq - read the contents of a CIM outbound queue
6549 * @adap: the adapter
6550 * @qid: the queue index
6551 * @data: where to store the queue contents
6552 * @n: capacity of @data in 32-bit words
6553 *
6554 * Reads the contents of the selected CIM queue starting at address 0 up
6555 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
6556 * error and the number of 32-bit words actually read on success.
6557 */
6558int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
6559{
6560 int i, err;
6561 unsigned int addr, v, nwords;
6562 int cim_num_obq = is_t4(adap->params.chip) ?
6563 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
6564
6565 if ((qid > (cim_num_obq - 1)) || (n & 3))
6566 return -EINVAL;
6567
6568 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
6569 QUENUMSELECT_V(qid));
6570 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
6571
6572 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
6573 nwords = CIMQSIZE_G(v) * 64; /* same */
6574 if (n > nwords)
6575 n = nwords;
6576
6577 for (i = 0; i < n; i++, addr++) {
6578 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
6579 OBQDBGEN_F);
6580 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
6581 2, 1);
6582 if (err)
6583 return err;
6584 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
6585 }
6586 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
e5f0e43b
HS		 6587 return i;
6588}
6589
f1ff24aa
HS		 6590/**
6591 * t4_cim_read - read a block from CIM internal address space
6592 * @adap: the adapter
6593 * @addr: the start address within the CIM address space
6594 * @n: number of words to read
6595 * @valp: where to store the result
6596 *
6597 * Reads a block of 4-byte words from the CIM intenal address space.
6598 */
6599int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
6600 unsigned int *valp)
6601{
6602 int ret = 0;
6603
6604 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
6605 return -EBUSY;
6606
6607 for ( ; !ret && n--; addr += 4) {
6608 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
6609 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
6610 0, 5, 2);
6611 if (!ret)
6612 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
6613 }
6614 return ret;
6615}
6616
6617/**
6618 * t4_cim_write - write a block into CIM internal address space
6619 * @adap: the adapter
6620 * @addr: the start address within the CIM address space
6621 * @n: number of words to write
6622 * @valp: set of values to write
6623 *
6624 * Writes a block of 4-byte words into the CIM intenal address space.
6625 */
6626int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
6627 const unsigned int *valp)
6628{
6629 int ret = 0;
6630
6631 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
6632 return -EBUSY;
6633
6634 for ( ; !ret && n--; addr += 4) {
6635 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
6636 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
6637 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
6638 0, 5, 2);
6639 }
6640 return ret;
6641}
6642
6643static int t4_cim_write1(struct adapter *adap, unsigned int addr,
6644 unsigned int val)
6645{
6646 return t4_cim_write(adap, addr, 1, &val);
6647}
6648
6649/**
6650 * t4_cim_read_la - read CIM LA capture buffer
6651 * @adap: the adapter
6652 * @la_buf: where to store the LA data
6653 * @wrptr: the HW write pointer within the capture buffer
6654 *
6655 * Reads the contents of the CIM LA buffer with the most recent entry at
6656 * the end of the returned data and with the entry at @wrptr first.
6657 * We try to leave the LA in the running state we find it in.
6658 */
6659int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
6660{
6661 int i, ret;
6662 unsigned int cfg, val, idx;
6663
6664 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
6665 if (ret)
6666 return ret;
6667
6668 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
6669 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
6670 if (ret)
6671 return ret;
6672 }
6673
6674 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
6675 if (ret)
6676 goto restart;
6677
6678 idx = UPDBGLAWRPTR_G(val);
6679 if (wrptr)
6680 *wrptr = idx;
6681
6682 for (i = 0; i < adap->params.cim_la_size; i++) {
6683 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
6684 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
6685 if (ret)
6686 break;
6687 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
6688 if (ret)
6689 break;
6690 if (val & UPDBGLARDEN_F) {
6691 ret = -ETIMEDOUT;
6692 break;
6693 }
6694 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
6695 if (ret)
6696 break;
6697 idx = (idx + 1) & UPDBGLARDPTR_M;
6698 }
6699restart:
6700 if (cfg & UPDBGLAEN_F) {
6701 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
6702 cfg & ~UPDBGLARDEN_F);
6703 if (!ret)
6704 ret = r;
6705 }
6706 return ret;
6707}
2d277b3b
HS		 6708
6709/**
6710 * t4_tp_read_la - read TP LA capture buffer
6711 * @adap: the adapter
6712 * @la_buf: where to store the LA data
6713 * @wrptr: the HW write pointer within the capture buffer
6714 *
6715 * Reads the contents of the TP LA buffer with the most recent entry at
6716 * the end of the returned data and with the entry at @wrptr first.
6717 * We leave the LA in the running state we find it in.
6718 */
6719void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
6720{
6721 bool last_incomplete;
6722 unsigned int i, cfg, val, idx;
6723
6724 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
6725 if (cfg & DBGLAENABLE_F) /* freeze LA */
6726 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
6727 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
6728
6729 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
6730 idx = DBGLAWPTR_G(val);
6731 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
6732 if (last_incomplete)
6733 idx = (idx + 1) & DBGLARPTR_M;
6734 if (wrptr)
6735 *wrptr = idx;
6736
6737 val &= 0xffff;
6738 val &= ~DBGLARPTR_V(DBGLARPTR_M);
6739 val |= adap->params.tp.la_mask;
6740
6741 for (i = 0; i < TPLA_SIZE; i++) {
6742 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
6743 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
6744 idx = (idx + 1) & DBGLARPTR_M;
6745 }
6746
6747 /* Wipe out last entry if it isn't valid */
6748 if (last_incomplete)
6749 la_buf[TPLA_SIZE - 1] = ~0ULL;
6750
6751 if (cfg & DBGLAENABLE_F) /* restore running state */
6752 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
6753 cfg | adap->params.tp.la_mask);
6754}
a3bfb617
HS		 6755
6756/* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
6757 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
6758 * state for more than the Warning Threshold then we'll issue a warning about
6759 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
6760 * appears to be hung every Warning Repeat second till the situation clears.
6761 * If the situation clears, we'll note that as well.
6762 */
6763#define SGE_IDMA_WARN_THRESH 1
6764#define SGE_IDMA_WARN_REPEAT 300
6765
6766/**
6767 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
6768 * @adapter: the adapter
6769 * @idma: the adapter IDMA Monitor state
6770 *
6771 * Initialize the state of an SGE Ingress DMA Monitor.
6772 */
6773void t4_idma_monitor_init(struct adapter *adapter,
6774 struct sge_idma_monitor_state *idma)
6775{
6776 /* Initialize the state variables for detecting an SGE Ingress DMA
6777 * hang. The SGE has internal counters which count up on each clock
6778 * tick whenever the SGE finds its Ingress DMA State Engines in the
6779 * same state they were on the previous clock tick. The clock used is
6780 * the Core Clock so we have a limit on the maximum "time" they can
6781 * record; typically a very small number of seconds. For instance,
6782 * with a 600MHz Core Clock, we can only count up to a bit more than
6783 * 7s. So we'll synthesize a larger counter in order to not run the
6784 * risk of having the "timers" overflow and give us the flexibility to
6785 * maintain a Hung SGE State Machine of our own which operates across
6786 * a longer time frame.
6787 */
6788 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
6789 idma->idma_stalled[0] = 0;
6790 idma->idma_stalled[1] = 0;
6791}
6792
6793/**
6794 * t4_idma_monitor - monitor SGE Ingress DMA state
6795 * @adapter: the adapter
6796 * @idma: the adapter IDMA Monitor state
6797 * @hz: number of ticks/second
6798 * @ticks: number of ticks since the last IDMA Monitor call
6799 */
6800void t4_idma_monitor(struct adapter *adapter,
6801 struct sge_idma_monitor_state *idma,
6802 int hz, int ticks)
6803{
6804 int i, idma_same_state_cnt[2];
6805
6806 /* Read the SGE Debug Ingress DMA Same State Count registers. These
6807 * are counters inside the SGE which count up on each clock when the
6808 * SGE finds its Ingress DMA State Engines in the same states they
6809 * were in the previous clock. The counters will peg out at
6810 * 0xffffffff without wrapping around so once they pass the 1s
6811 * threshold they'll stay above that till the IDMA state changes.
6812 */
6813 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
6814 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
6815 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
6816
6817 for (i = 0; i < 2; i++) {
6818 u32 debug0, debug11;
6819
6820 /* If the Ingress DMA Same State Counter ("timer") is less
6821 * than 1s, then we can reset our synthesized Stall Timer and
6822 * continue. If we have previously emitted warnings about a
6823 * potential stalled Ingress Queue, issue a note indicating
6824 * that the Ingress Queue has resumed forward progress.
6825 */
6826 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
6827 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
6828 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
6829 "resumed after %d seconds\n",
6830 i, idma->idma_qid[i],
6831 idma->idma_stalled[i] / hz);
6832 idma->idma_stalled[i] = 0;
6833 continue;
6834 }
6835
6836 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
6837 * domain. The first time we get here it'll be because we
6838 * passed the 1s Threshold; each additional time it'll be
6839 * because the RX Timer Callback is being fired on its regular
6840 * schedule.
6841 *
6842 * If the stall is below our Potential Hung Ingress Queue
6843 * Warning Threshold, continue.
6844 */
6845 if (idma->idma_stalled[i] == 0) {
6846 idma->idma_stalled[i] = hz;
6847 idma->idma_warn[i] = 0;
6848 } else {
6849 idma->idma_stalled[i] += ticks;
6850 idma->idma_warn[i] -= ticks;
6851 }
6852
6853 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
6854 continue;
6855
6856 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
6857 */
6858 if (idma->idma_warn[i] > 0)
6859 continue;
6860 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
6861
6862 /* Read and save the SGE IDMA State and Queue ID information.
6863 * We do this every time in case it changes across time ...
6864 * can't be too careful ...
6865 */
6866 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
6867 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
6868 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
6869
6870 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
6871 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
6872 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
6873
6874 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
6875 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
6876 i, idma->idma_qid[i], idma->idma_state[i],
6877 idma->idma_stalled[i] / hz,
6878 debug0, debug11);
6879 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
6880 }
6881}
Linux kernel - Deliverables
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