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56d36be4 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
56d36be4 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
56d36be4 DM |
35 | #include <linux/delay.h> |
36 | #include "cxgb4.h" | |
37 | #include "t4_regs.h" | |
f612b815 | 38 | #include "t4_values.h" |
56d36be4 | 39 | #include "t4fw_api.h" |
a69265e9 | 40 | #include "t4fw_version.h" |
56d36be4 DM |
41 | |
42 | /** | |
43 | * t4_wait_op_done_val - wait until an operation is completed | |
44 | * @adapter: the adapter performing the operation | |
45 | * @reg: the register to check for completion | |
46 | * @mask: a single-bit field within @reg that indicates completion | |
47 | * @polarity: the value of the field when the operation is completed | |
48 | * @attempts: number of check iterations | |
49 | * @delay: delay in usecs between iterations | |
50 | * @valp: where to store the value of the register at completion time | |
51 | * | |
52 | * Wait until an operation is completed by checking a bit in a register | |
53 | * up to @attempts times. If @valp is not NULL the value of the register | |
54 | * at the time it indicated completion is stored there. Returns 0 if the | |
55 | * operation completes and -EAGAIN otherwise. | |
56 | */ | |
de498c89 RD |
57 | static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, |
58 | int polarity, int attempts, int delay, u32 *valp) | |
56d36be4 DM |
59 | { |
60 | while (1) { | |
61 | u32 val = t4_read_reg(adapter, reg); | |
62 | ||
63 | if (!!(val & mask) == polarity) { | |
64 | if (valp) | |
65 | *valp = val; | |
66 | return 0; | |
67 | } | |
68 | if (--attempts == 0) | |
69 | return -EAGAIN; | |
70 | if (delay) | |
71 | udelay(delay); | |
72 | } | |
73 | } | |
74 | ||
75 | static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, | |
76 | int polarity, int attempts, int delay) | |
77 | { | |
78 | return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, | |
79 | delay, NULL); | |
80 | } | |
81 | ||
82 | /** | |
83 | * t4_set_reg_field - set a register field to a value | |
84 | * @adapter: the adapter to program | |
85 | * @addr: the register address | |
86 | * @mask: specifies the portion of the register to modify | |
87 | * @val: the new value for the register field | |
88 | * | |
89 | * Sets a register field specified by the supplied mask to the | |
90 | * given value. | |
91 | */ | |
92 | void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, | |
93 | u32 val) | |
94 | { | |
95 | u32 v = t4_read_reg(adapter, addr) & ~mask; | |
96 | ||
97 | t4_write_reg(adapter, addr, v | val); | |
98 | (void) t4_read_reg(adapter, addr); /* flush */ | |
99 | } | |
100 | ||
101 | /** | |
102 | * t4_read_indirect - read indirectly addressed registers | |
103 | * @adap: the adapter | |
104 | * @addr_reg: register holding the indirect address | |
105 | * @data_reg: register holding the value of the indirect register | |
106 | * @vals: where the read register values are stored | |
107 | * @nregs: how many indirect registers to read | |
108 | * @start_idx: index of first indirect register to read | |
109 | * | |
110 | * Reads registers that are accessed indirectly through an address/data | |
111 | * register pair. | |
112 | */ | |
f2b7e78d | 113 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
de498c89 RD |
114 | unsigned int data_reg, u32 *vals, |
115 | unsigned int nregs, unsigned int start_idx) | |
56d36be4 DM |
116 | { |
117 | while (nregs--) { | |
118 | t4_write_reg(adap, addr_reg, start_idx); | |
119 | *vals++ = t4_read_reg(adap, data_reg); | |
120 | start_idx++; | |
121 | } | |
122 | } | |
123 | ||
13ee15d3 VP |
124 | /** |
125 | * t4_write_indirect - write indirectly addressed registers | |
126 | * @adap: the adapter | |
127 | * @addr_reg: register holding the indirect addresses | |
128 | * @data_reg: register holding the value for the indirect registers | |
129 | * @vals: values to write | |
130 | * @nregs: how many indirect registers to write | |
131 | * @start_idx: address of first indirect register to write | |
132 | * | |
133 | * Writes a sequential block of registers that are accessed indirectly | |
134 | * through an address/data register pair. | |
135 | */ | |
136 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, | |
137 | unsigned int data_reg, const u32 *vals, | |
138 | unsigned int nregs, unsigned int start_idx) | |
139 | { | |
140 | while (nregs--) { | |
141 | t4_write_reg(adap, addr_reg, start_idx++); | |
142 | t4_write_reg(adap, data_reg, *vals++); | |
143 | } | |
144 | } | |
145 | ||
0abfd152 HS |
146 | /* |
147 | * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor | |
148 | * mechanism. This guarantees that we get the real value even if we're | |
149 | * operating within a Virtual Machine and the Hypervisor is trapping our | |
150 | * Configuration Space accesses. | |
151 | */ | |
152 | void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) | |
153 | { | |
3ccc6cf7 HS |
154 | u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); |
155 | ||
156 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
157 | req |= ENABLE_F; | |
158 | else | |
159 | req |= T6_ENABLE_F; | |
0abfd152 HS |
160 | |
161 | if (is_t4(adap->params.chip)) | |
f061de42 | 162 | req |= LOCALCFG_F; |
0abfd152 | 163 | |
f061de42 HS |
164 | t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); |
165 | *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); | |
0abfd152 HS |
166 | |
167 | /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a | |
168 | * Configuration Space read. (None of the other fields matter when | |
169 | * ENABLE is 0 so a simple register write is easier than a | |
170 | * read-modify-write via t4_set_reg_field().) | |
171 | */ | |
f061de42 | 172 | t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); |
0abfd152 HS |
173 | } |
174 | ||
31d55c2d HS |
175 | /* |
176 | * t4_report_fw_error - report firmware error | |
177 | * @adap: the adapter | |
178 | * | |
179 | * The adapter firmware can indicate error conditions to the host. | |
180 | * If the firmware has indicated an error, print out the reason for | |
181 | * the firmware error. | |
182 | */ | |
183 | static void t4_report_fw_error(struct adapter *adap) | |
184 | { | |
185 | static const char *const reason[] = { | |
186 | "Crash", /* PCIE_FW_EVAL_CRASH */ | |
187 | "During Device Preparation", /* PCIE_FW_EVAL_PREP */ | |
188 | "During Device Configuration", /* PCIE_FW_EVAL_CONF */ | |
189 | "During Device Initialization", /* PCIE_FW_EVAL_INIT */ | |
190 | "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ | |
191 | "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ | |
192 | "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ | |
193 | "Reserved", /* reserved */ | |
194 | }; | |
195 | u32 pcie_fw; | |
196 | ||
f061de42 HS |
197 | pcie_fw = t4_read_reg(adap, PCIE_FW_A); |
198 | if (pcie_fw & PCIE_FW_ERR_F) | |
31d55c2d | 199 | dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", |
b2e1a3f0 | 200 | reason[PCIE_FW_EVAL_G(pcie_fw)]); |
31d55c2d HS |
201 | } |
202 | ||
56d36be4 DM |
203 | /* |
204 | * Get the reply to a mailbox command and store it in @rpl in big-endian order. | |
205 | */ | |
206 | static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, | |
207 | u32 mbox_addr) | |
208 | { | |
209 | for ( ; nflit; nflit--, mbox_addr += 8) | |
210 | *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); | |
211 | } | |
212 | ||
213 | /* | |
214 | * Handle a FW assertion reported in a mailbox. | |
215 | */ | |
216 | static void fw_asrt(struct adapter *adap, u32 mbox_addr) | |
217 | { | |
218 | struct fw_debug_cmd asrt; | |
219 | ||
220 | get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); | |
221 | dev_alert(adap->pdev_dev, | |
222 | "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", | |
f404f80c HS |
223 | asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line), |
224 | be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y)); | |
56d36be4 DM |
225 | } |
226 | ||
227 | static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) | |
228 | { | |
229 | dev_err(adap->pdev_dev, | |
230 | "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, | |
231 | (unsigned long long)t4_read_reg64(adap, data_reg), | |
232 | (unsigned long long)t4_read_reg64(adap, data_reg + 8), | |
233 | (unsigned long long)t4_read_reg64(adap, data_reg + 16), | |
234 | (unsigned long long)t4_read_reg64(adap, data_reg + 24), | |
235 | (unsigned long long)t4_read_reg64(adap, data_reg + 32), | |
236 | (unsigned long long)t4_read_reg64(adap, data_reg + 40), | |
237 | (unsigned long long)t4_read_reg64(adap, data_reg + 48), | |
238 | (unsigned long long)t4_read_reg64(adap, data_reg + 56)); | |
239 | } | |
240 | ||
241 | /** | |
01b69614 | 242 | * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox |
56d36be4 DM |
243 | * @adap: the adapter |
244 | * @mbox: index of the mailbox to use | |
245 | * @cmd: the command to write | |
246 | * @size: command length in bytes | |
247 | * @rpl: where to optionally store the reply | |
248 | * @sleep_ok: if true we may sleep while awaiting command completion | |
01b69614 | 249 | * @timeout: time to wait for command to finish before timing out |
56d36be4 DM |
250 | * |
251 | * Sends the given command to FW through the selected mailbox and waits | |
252 | * for the FW to execute the command. If @rpl is not %NULL it is used to | |
253 | * store the FW's reply to the command. The command and its optional | |
254 | * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms | |
255 | * to respond. @sleep_ok determines whether we may sleep while awaiting | |
256 | * the response. If sleeping is allowed we use progressive backoff | |
257 | * otherwise we spin. | |
258 | * | |
259 | * The return value is 0 on success or a negative errno on failure. A | |
260 | * failure can happen either because we are not able to execute the | |
261 | * command or FW executes it but signals an error. In the latter case | |
262 | * the return value is the error code indicated by FW (negated). | |
263 | */ | |
01b69614 HS |
264 | int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, |
265 | int size, void *rpl, bool sleep_ok, int timeout) | |
56d36be4 | 266 | { |
005b5717 | 267 | static const int delay[] = { |
56d36be4 DM |
268 | 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 |
269 | }; | |
270 | ||
271 | u32 v; | |
272 | u64 res; | |
273 | int i, ms, delay_idx; | |
274 | const __be64 *p = cmd; | |
89c3a86c HS |
275 | u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); |
276 | u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); | |
56d36be4 DM |
277 | |
278 | if ((size & 15) || size > MBOX_LEN) | |
279 | return -EINVAL; | |
280 | ||
204dc3c0 DM |
281 | /* |
282 | * If the device is off-line, as in EEH, commands will time out. | |
283 | * Fail them early so we don't waste time waiting. | |
284 | */ | |
285 | if (adap->pdev->error_state != pci_channel_io_normal) | |
286 | return -EIO; | |
287 | ||
89c3a86c | 288 | v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); |
56d36be4 | 289 | for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) |
89c3a86c | 290 | v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); |
56d36be4 DM |
291 | |
292 | if (v != MBOX_OWNER_DRV) | |
293 | return v ? -EBUSY : -ETIMEDOUT; | |
294 | ||
295 | for (i = 0; i < size; i += 8) | |
296 | t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); | |
297 | ||
89c3a86c | 298 | t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); |
56d36be4 DM |
299 | t4_read_reg(adap, ctl_reg); /* flush write */ |
300 | ||
301 | delay_idx = 0; | |
302 | ms = delay[0]; | |
303 | ||
01b69614 | 304 | for (i = 0; i < timeout; i += ms) { |
56d36be4 DM |
305 | if (sleep_ok) { |
306 | ms = delay[delay_idx]; /* last element may repeat */ | |
307 | if (delay_idx < ARRAY_SIZE(delay) - 1) | |
308 | delay_idx++; | |
309 | msleep(ms); | |
310 | } else | |
311 | mdelay(ms); | |
312 | ||
313 | v = t4_read_reg(adap, ctl_reg); | |
89c3a86c HS |
314 | if (MBOWNER_G(v) == MBOX_OWNER_DRV) { |
315 | if (!(v & MBMSGVALID_F)) { | |
56d36be4 DM |
316 | t4_write_reg(adap, ctl_reg, 0); |
317 | continue; | |
318 | } | |
319 | ||
320 | res = t4_read_reg64(adap, data_reg); | |
e2ac9628 | 321 | if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) { |
56d36be4 | 322 | fw_asrt(adap, data_reg); |
e2ac9628 HS |
323 | res = FW_CMD_RETVAL_V(EIO); |
324 | } else if (rpl) { | |
56d36be4 | 325 | get_mbox_rpl(adap, rpl, size / 8, data_reg); |
e2ac9628 | 326 | } |
56d36be4 | 327 | |
e2ac9628 | 328 | if (FW_CMD_RETVAL_G((int)res)) |
56d36be4 DM |
329 | dump_mbox(adap, mbox, data_reg); |
330 | t4_write_reg(adap, ctl_reg, 0); | |
e2ac9628 | 331 | return -FW_CMD_RETVAL_G((int)res); |
56d36be4 DM |
332 | } |
333 | } | |
334 | ||
335 | dump_mbox(adap, mbox, data_reg); | |
336 | dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", | |
337 | *(const u8 *)cmd, mbox); | |
31d55c2d | 338 | t4_report_fw_error(adap); |
56d36be4 DM |
339 | return -ETIMEDOUT; |
340 | } | |
341 | ||
01b69614 HS |
342 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, |
343 | void *rpl, bool sleep_ok) | |
56d36be4 | 344 | { |
01b69614 HS |
345 | return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok, |
346 | FW_CMD_MAX_TIMEOUT); | |
56d36be4 DM |
347 | } |
348 | ||
bf8ebb67 HS |
349 | static int t4_edc_err_read(struct adapter *adap, int idx) |
350 | { | |
351 | u32 edc_ecc_err_addr_reg; | |
352 | u32 rdata_reg; | |
353 | ||
354 | if (is_t4(adap->params.chip)) { | |
355 | CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); | |
356 | return 0; | |
357 | } | |
358 | if (idx != 0 && idx != 1) { | |
359 | CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx); | |
364 | rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx); | |
365 | ||
366 | CH_WARN(adap, | |
367 | "edc%d err addr 0x%x: 0x%x.\n", | |
368 | idx, edc_ecc_err_addr_reg, | |
369 | t4_read_reg(adap, edc_ecc_err_addr_reg)); | |
370 | CH_WARN(adap, | |
371 | "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", | |
372 | rdata_reg, | |
373 | (unsigned long long)t4_read_reg64(adap, rdata_reg), | |
374 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 8), | |
375 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 16), | |
376 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 24), | |
377 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 32), | |
378 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 40), | |
379 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 48), | |
380 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 56), | |
381 | (unsigned long long)t4_read_reg64(adap, rdata_reg + 64)); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
5afc8b84 VP |
386 | /** |
387 | * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window | |
388 | * @adap: the adapter | |
fc5ab020 | 389 | * @win: PCI-E Memory Window to use |
5afc8b84 VP |
390 | * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC |
391 | * @addr: address within indicated memory type | |
392 | * @len: amount of memory to transfer | |
f01aa633 | 393 | * @hbuf: host memory buffer |
fc5ab020 | 394 | * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) |
5afc8b84 VP |
395 | * |
396 | * Reads/writes an [almost] arbitrary memory region in the firmware: the | |
fc5ab020 HS |
397 | * firmware memory address and host buffer must be aligned on 32-bit |
398 | * boudaries; the length may be arbitrary. The memory is transferred as | |
399 | * a raw byte sequence from/to the firmware's memory. If this memory | |
400 | * contains data structures which contain multi-byte integers, it's the | |
401 | * caller's responsibility to perform appropriate byte order conversions. | |
5afc8b84 | 402 | */ |
fc5ab020 | 403 | int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, |
f01aa633 | 404 | u32 len, void *hbuf, int dir) |
5afc8b84 | 405 | { |
fc5ab020 HS |
406 | u32 pos, offset, resid, memoffset; |
407 | u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; | |
f01aa633 | 408 | u32 *buf; |
5afc8b84 | 409 | |
fc5ab020 | 410 | /* Argument sanity checks ... |
5afc8b84 | 411 | */ |
f01aa633 | 412 | if (addr & 0x3 || (uintptr_t)hbuf & 0x3) |
5afc8b84 | 413 | return -EINVAL; |
f01aa633 | 414 | buf = (u32 *)hbuf; |
5afc8b84 | 415 | |
fc5ab020 HS |
416 | /* It's convenient to be able to handle lengths which aren't a |
417 | * multiple of 32-bits because we often end up transferring files to | |
418 | * the firmware. So we'll handle that by normalizing the length here | |
419 | * and then handling any residual transfer at the end. | |
420 | */ | |
421 | resid = len & 0x3; | |
422 | len -= resid; | |
8c357ebd | 423 | |
19dd37ba | 424 | /* Offset into the region of memory which is being accessed |
5afc8b84 VP |
425 | * MEM_EDC0 = 0 |
426 | * MEM_EDC1 = 1 | |
3ccc6cf7 HS |
427 | * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller |
428 | * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) | |
5afc8b84 | 429 | */ |
6559a7e8 | 430 | edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); |
19dd37ba SR |
431 | if (mtype != MEM_MC1) |
432 | memoffset = (mtype * (edc_size * 1024 * 1024)); | |
433 | else { | |
6559a7e8 | 434 | mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, |
7f0b8a56 | 435 | MA_EXT_MEMORY0_BAR_A)); |
19dd37ba SR |
436 | memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; |
437 | } | |
5afc8b84 VP |
438 | |
439 | /* Determine the PCIE_MEM_ACCESS_OFFSET */ | |
440 | addr = addr + memoffset; | |
441 | ||
fc5ab020 HS |
442 | /* Each PCI-E Memory Window is programmed with a window size -- or |
443 | * "aperture" -- which controls the granularity of its mapping onto | |
444 | * adapter memory. We need to grab that aperture in order to know | |
445 | * how to use the specified window. The window is also programmed | |
446 | * with the base address of the Memory Window in BAR0's address | |
447 | * space. For T4 this is an absolute PCI-E Bus Address. For T5 | |
448 | * the address is relative to BAR0. | |
5afc8b84 | 449 | */ |
fc5ab020 | 450 | mem_reg = t4_read_reg(adap, |
f061de42 | 451 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, |
fc5ab020 | 452 | win)); |
f061de42 HS |
453 | mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X); |
454 | mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X; | |
fc5ab020 HS |
455 | if (is_t4(adap->params.chip)) |
456 | mem_base -= adap->t4_bar0; | |
b2612722 | 457 | win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); |
5afc8b84 | 458 | |
fc5ab020 HS |
459 | /* Calculate our initial PCI-E Memory Window Position and Offset into |
460 | * that Window. | |
461 | */ | |
462 | pos = addr & ~(mem_aperture-1); | |
463 | offset = addr - pos; | |
5afc8b84 | 464 | |
fc5ab020 HS |
465 | /* Set up initial PCI-E Memory Window to cover the start of our |
466 | * transfer. (Read it back to ensure that changes propagate before we | |
467 | * attempt to use the new value.) | |
468 | */ | |
469 | t4_write_reg(adap, | |
f061de42 | 470 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win), |
fc5ab020 HS |
471 | pos | win_pf); |
472 | t4_read_reg(adap, | |
f061de42 | 473 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); |
fc5ab020 HS |
474 | |
475 | /* Transfer data to/from the adapter as long as there's an integral | |
476 | * number of 32-bit transfers to complete. | |
f01aa633 HS |
477 | * |
478 | * A note on Endianness issues: | |
479 | * | |
480 | * The "register" reads and writes below from/to the PCI-E Memory | |
481 | * Window invoke the standard adapter Big-Endian to PCI-E Link | |
482 | * Little-Endian "swizzel." As a result, if we have the following | |
483 | * data in adapter memory: | |
484 | * | |
485 | * Memory: ... | b0 | b1 | b2 | b3 | ... | |
486 | * Address: i+0 i+1 i+2 i+3 | |
487 | * | |
488 | * Then a read of the adapter memory via the PCI-E Memory Window | |
489 | * will yield: | |
490 | * | |
491 | * x = readl(i) | |
492 | * 31 0 | |
493 | * [ b3 | b2 | b1 | b0 ] | |
494 | * | |
495 | * If this value is stored into local memory on a Little-Endian system | |
496 | * it will show up correctly in local memory as: | |
497 | * | |
498 | * ( ..., b0, b1, b2, b3, ... ) | |
499 | * | |
500 | * But on a Big-Endian system, the store will show up in memory | |
501 | * incorrectly swizzled as: | |
502 | * | |
503 | * ( ..., b3, b2, b1, b0, ... ) | |
504 | * | |
505 | * So we need to account for this in the reads and writes to the | |
506 | * PCI-E Memory Window below by undoing the register read/write | |
507 | * swizzels. | |
fc5ab020 HS |
508 | */ |
509 | while (len > 0) { | |
510 | if (dir == T4_MEMORY_READ) | |
f01aa633 HS |
511 | *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, |
512 | mem_base + offset)); | |
fc5ab020 HS |
513 | else |
514 | t4_write_reg(adap, mem_base + offset, | |
f01aa633 | 515 | (__force u32)cpu_to_le32(*buf++)); |
fc5ab020 HS |
516 | offset += sizeof(__be32); |
517 | len -= sizeof(__be32); | |
518 | ||
519 | /* If we've reached the end of our current window aperture, | |
520 | * move the PCI-E Memory Window on to the next. Note that | |
521 | * doing this here after "len" may be 0 allows us to set up | |
522 | * the PCI-E Memory Window for a possible final residual | |
523 | * transfer below ... | |
5afc8b84 | 524 | */ |
fc5ab020 HS |
525 | if (offset == mem_aperture) { |
526 | pos += mem_aperture; | |
527 | offset = 0; | |
528 | t4_write_reg(adap, | |
f061de42 HS |
529 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, |
530 | win), pos | win_pf); | |
fc5ab020 | 531 | t4_read_reg(adap, |
f061de42 HS |
532 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, |
533 | win)); | |
5afc8b84 | 534 | } |
5afc8b84 VP |
535 | } |
536 | ||
fc5ab020 HS |
537 | /* If the original transfer had a length which wasn't a multiple of |
538 | * 32-bits, now's where we need to finish off the transfer of the | |
539 | * residual amount. The PCI-E Memory Window has already been moved | |
540 | * above (if necessary) to cover this final transfer. | |
541 | */ | |
542 | if (resid) { | |
543 | union { | |
f01aa633 | 544 | u32 word; |
fc5ab020 HS |
545 | char byte[4]; |
546 | } last; | |
547 | unsigned char *bp; | |
548 | int i; | |
549 | ||
c81576c2 | 550 | if (dir == T4_MEMORY_READ) { |
f01aa633 HS |
551 | last.word = le32_to_cpu( |
552 | (__force __le32)t4_read_reg(adap, | |
553 | mem_base + offset)); | |
fc5ab020 HS |
554 | for (bp = (unsigned char *)buf, i = resid; i < 4; i++) |
555 | bp[i] = last.byte[i]; | |
556 | } else { | |
557 | last.word = *buf; | |
558 | for (i = resid; i < 4; i++) | |
559 | last.byte[i] = 0; | |
560 | t4_write_reg(adap, mem_base + offset, | |
f01aa633 | 561 | (__force u32)cpu_to_le32(last.word)); |
fc5ab020 HS |
562 | } |
563 | } | |
5afc8b84 | 564 | |
fc5ab020 | 565 | return 0; |
5afc8b84 VP |
566 | } |
567 | ||
b562fc37 HS |
568 | /* Return the specified PCI-E Configuration Space register from our Physical |
569 | * Function. We try first via a Firmware LDST Command since we prefer to let | |
570 | * the firmware own all of these registers, but if that fails we go for it | |
571 | * directly ourselves. | |
572 | */ | |
573 | u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) | |
574 | { | |
575 | u32 val, ldst_addrspace; | |
576 | ||
577 | /* If fw_attach != 0, construct and send the Firmware LDST Command to | |
578 | * retrieve the specified PCI-E Configuration Space register. | |
579 | */ | |
580 | struct fw_ldst_cmd ldst_cmd; | |
581 | int ret; | |
582 | ||
583 | memset(&ldst_cmd, 0, sizeof(ldst_cmd)); | |
584 | ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE); | |
585 | ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
586 | FW_CMD_REQUEST_F | | |
587 | FW_CMD_READ_F | | |
588 | ldst_addrspace); | |
589 | ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); | |
590 | ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); | |
591 | ldst_cmd.u.pcie.ctrl_to_fn = | |
b2612722 | 592 | (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); |
b562fc37 HS |
593 | ldst_cmd.u.pcie.r = reg; |
594 | ||
595 | /* If the LDST Command succeeds, return the result, otherwise | |
596 | * fall through to reading it directly ourselves ... | |
597 | */ | |
598 | ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), | |
599 | &ldst_cmd); | |
600 | if (ret == 0) | |
601 | val = be32_to_cpu(ldst_cmd.u.pcie.data[0]); | |
602 | else | |
603 | /* Read the desired Configuration Space register via the PCI-E | |
604 | * Backdoor mechanism. | |
605 | */ | |
606 | t4_hw_pci_read_cfg4(adap, reg, &val); | |
607 | return val; | |
608 | } | |
609 | ||
610 | /* Get the window based on base passed to it. | |
611 | * Window aperture is currently unhandled, but there is no use case for it | |
612 | * right now | |
613 | */ | |
614 | static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask, | |
615 | u32 memwin_base) | |
616 | { | |
617 | u32 ret; | |
618 | ||
619 | if (is_t4(adap->params.chip)) { | |
620 | u32 bar0; | |
621 | ||
622 | /* Truncation intentional: we only read the bottom 32-bits of | |
623 | * the 64-bit BAR0/BAR1 ... We use the hardware backdoor | |
624 | * mechanism to read BAR0 instead of using | |
625 | * pci_resource_start() because we could be operating from | |
626 | * within a Virtual Machine which is trapping our accesses to | |
627 | * our Configuration Space and we need to set up the PCI-E | |
628 | * Memory Window decoders with the actual addresses which will | |
629 | * be coming across the PCI-E link. | |
630 | */ | |
631 | bar0 = t4_read_pcie_cfg4(adap, pci_base); | |
632 | bar0 &= pci_mask; | |
633 | adap->t4_bar0 = bar0; | |
634 | ||
635 | ret = bar0 + memwin_base; | |
636 | } else { | |
637 | /* For T5, only relative offset inside the PCIe BAR is passed */ | |
638 | ret = memwin_base; | |
639 | } | |
640 | return ret; | |
641 | } | |
642 | ||
643 | /* Get the default utility window (win0) used by everyone */ | |
644 | u32 t4_get_util_window(struct adapter *adap) | |
645 | { | |
646 | return t4_get_window(adap, PCI_BASE_ADDRESS_0, | |
647 | PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE); | |
648 | } | |
649 | ||
650 | /* Set up memory window for accessing adapter memory ranges. (Read | |
651 | * back MA register to ensure that changes propagate before we attempt | |
652 | * to use the new values.) | |
653 | */ | |
654 | void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) | |
655 | { | |
656 | t4_write_reg(adap, | |
657 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window), | |
658 | memwin_base | BIR_V(0) | | |
659 | WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X)); | |
660 | t4_read_reg(adap, | |
661 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window)); | |
662 | } | |
663 | ||
812034f1 HS |
664 | /** |
665 | * t4_get_regs_len - return the size of the chips register set | |
666 | * @adapter: the adapter | |
667 | * | |
668 | * Returns the size of the chip's BAR0 register space. | |
669 | */ | |
670 | unsigned int t4_get_regs_len(struct adapter *adapter) | |
671 | { | |
672 | unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); | |
673 | ||
674 | switch (chip_version) { | |
675 | case CHELSIO_T4: | |
676 | return T4_REGMAP_SIZE; | |
677 | ||
678 | case CHELSIO_T5: | |
ab4b583b | 679 | case CHELSIO_T6: |
812034f1 HS |
680 | return T5_REGMAP_SIZE; |
681 | } | |
682 | ||
683 | dev_err(adapter->pdev_dev, | |
684 | "Unsupported chip version %d\n", chip_version); | |
685 | return 0; | |
686 | } | |
687 | ||
688 | /** | |
689 | * t4_get_regs - read chip registers into provided buffer | |
690 | * @adap: the adapter | |
691 | * @buf: register buffer | |
692 | * @buf_size: size (in bytes) of register buffer | |
693 | * | |
694 | * If the provided register buffer isn't large enough for the chip's | |
695 | * full register range, the register dump will be truncated to the | |
696 | * register buffer's size. | |
697 | */ | |
698 | void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) | |
699 | { | |
700 | static const unsigned int t4_reg_ranges[] = { | |
701 | 0x1008, 0x1108, | |
8119c018 HS |
702 | 0x1180, 0x1184, |
703 | 0x1190, 0x1194, | |
704 | 0x11a0, 0x11a4, | |
705 | 0x11b0, 0x11b4, | |
812034f1 HS |
706 | 0x11fc, 0x123c, |
707 | 0x1300, 0x173c, | |
708 | 0x1800, 0x18fc, | |
8119c018 HS |
709 | 0x3000, 0x30d8, |
710 | 0x30e0, 0x30e4, | |
711 | 0x30ec, 0x5910, | |
712 | 0x5920, 0x5924, | |
713 | 0x5960, 0x5960, | |
714 | 0x5968, 0x5968, | |
715 | 0x5970, 0x5970, | |
716 | 0x5978, 0x5978, | |
717 | 0x5980, 0x5980, | |
718 | 0x5988, 0x5988, | |
719 | 0x5990, 0x5990, | |
720 | 0x5998, 0x5998, | |
721 | 0x59a0, 0x59d4, | |
722 | 0x5a00, 0x5ae0, | |
723 | 0x5ae8, 0x5ae8, | |
724 | 0x5af0, 0x5af0, | |
725 | 0x5af8, 0x5af8, | |
812034f1 HS |
726 | 0x6000, 0x6098, |
727 | 0x6100, 0x6150, | |
728 | 0x6200, 0x6208, | |
729 | 0x6240, 0x6248, | |
8119c018 HS |
730 | 0x6280, 0x62b0, |
731 | 0x62c0, 0x6338, | |
812034f1 HS |
732 | 0x6370, 0x638c, |
733 | 0x6400, 0x643c, | |
734 | 0x6500, 0x6524, | |
8119c018 HS |
735 | 0x6a00, 0x6a04, |
736 | 0x6a14, 0x6a38, | |
737 | 0x6a60, 0x6a70, | |
738 | 0x6a78, 0x6a78, | |
739 | 0x6b00, 0x6b0c, | |
740 | 0x6b1c, 0x6b84, | |
741 | 0x6bf0, 0x6bf8, | |
742 | 0x6c00, 0x6c0c, | |
743 | 0x6c1c, 0x6c84, | |
744 | 0x6cf0, 0x6cf8, | |
745 | 0x6d00, 0x6d0c, | |
746 | 0x6d1c, 0x6d84, | |
747 | 0x6df0, 0x6df8, | |
748 | 0x6e00, 0x6e0c, | |
749 | 0x6e1c, 0x6e84, | |
750 | 0x6ef0, 0x6ef8, | |
751 | 0x6f00, 0x6f0c, | |
752 | 0x6f1c, 0x6f84, | |
753 | 0x6ff0, 0x6ff8, | |
754 | 0x7000, 0x700c, | |
755 | 0x701c, 0x7084, | |
756 | 0x70f0, 0x70f8, | |
757 | 0x7100, 0x710c, | |
758 | 0x711c, 0x7184, | |
759 | 0x71f0, 0x71f8, | |
760 | 0x7200, 0x720c, | |
761 | 0x721c, 0x7284, | |
762 | 0x72f0, 0x72f8, | |
763 | 0x7300, 0x730c, | |
764 | 0x731c, 0x7384, | |
765 | 0x73f0, 0x73f8, | |
766 | 0x7400, 0x7450, | |
812034f1 | 767 | 0x7500, 0x7530, |
8119c018 HS |
768 | 0x7600, 0x760c, |
769 | 0x7614, 0x761c, | |
812034f1 HS |
770 | 0x7680, 0x76cc, |
771 | 0x7700, 0x7798, | |
772 | 0x77c0, 0x77fc, | |
773 | 0x7900, 0x79fc, | |
8119c018 HS |
774 | 0x7b00, 0x7b58, |
775 | 0x7b60, 0x7b84, | |
776 | 0x7b8c, 0x7c38, | |
777 | 0x7d00, 0x7d38, | |
778 | 0x7d40, 0x7d80, | |
779 | 0x7d8c, 0x7ddc, | |
780 | 0x7de4, 0x7e04, | |
781 | 0x7e10, 0x7e1c, | |
782 | 0x7e24, 0x7e38, | |
783 | 0x7e40, 0x7e44, | |
784 | 0x7e4c, 0x7e78, | |
785 | 0x7e80, 0x7ea4, | |
786 | 0x7eac, 0x7edc, | |
787 | 0x7ee8, 0x7efc, | |
788 | 0x8dc0, 0x8e04, | |
789 | 0x8e10, 0x8e1c, | |
812034f1 | 790 | 0x8e30, 0x8e78, |
8119c018 HS |
791 | 0x8ea0, 0x8eb8, |
792 | 0x8ec0, 0x8f6c, | |
793 | 0x8fc0, 0x9008, | |
794 | 0x9010, 0x9058, | |
795 | 0x9060, 0x9060, | |
796 | 0x9068, 0x9074, | |
812034f1 | 797 | 0x90fc, 0x90fc, |
8119c018 HS |
798 | 0x9400, 0x9408, |
799 | 0x9410, 0x9458, | |
800 | 0x9600, 0x9600, | |
801 | 0x9608, 0x9638, | |
802 | 0x9640, 0x96bc, | |
812034f1 HS |
803 | 0x9800, 0x9808, |
804 | 0x9820, 0x983c, | |
805 | 0x9850, 0x9864, | |
806 | 0x9c00, 0x9c6c, | |
807 | 0x9c80, 0x9cec, | |
808 | 0x9d00, 0x9d6c, | |
809 | 0x9d80, 0x9dec, | |
810 | 0x9e00, 0x9e6c, | |
811 | 0x9e80, 0x9eec, | |
812 | 0x9f00, 0x9f6c, | |
813 | 0x9f80, 0x9fec, | |
8119c018 HS |
814 | 0xd004, 0xd004, |
815 | 0xd010, 0xd03c, | |
812034f1 HS |
816 | 0xdfc0, 0xdfe0, |
817 | 0xe000, 0xea7c, | |
8119c018 | 818 | 0xf000, 0x11190, |
812034f1 HS |
819 | 0x19040, 0x1906c, |
820 | 0x19078, 0x19080, | |
8119c018 HS |
821 | 0x1908c, 0x190e4, |
822 | 0x190f0, 0x190f8, | |
823 | 0x19100, 0x19110, | |
824 | 0x19120, 0x19124, | |
825 | 0x19150, 0x19194, | |
826 | 0x1919c, 0x191b0, | |
812034f1 HS |
827 | 0x191d0, 0x191e8, |
828 | 0x19238, 0x1924c, | |
8119c018 HS |
829 | 0x193f8, 0x1943c, |
830 | 0x1944c, 0x19474, | |
831 | 0x19490, 0x194e0, | |
832 | 0x194f0, 0x194f8, | |
833 | 0x19800, 0x19c08, | |
834 | 0x19c10, 0x19c90, | |
835 | 0x19ca0, 0x19ce4, | |
836 | 0x19cf0, 0x19d40, | |
837 | 0x19d50, 0x19d94, | |
838 | 0x19da0, 0x19de8, | |
839 | 0x19df0, 0x19e40, | |
840 | 0x19e50, 0x19e90, | |
841 | 0x19ea0, 0x19f4c, | |
842 | 0x1a000, 0x1a004, | |
843 | 0x1a010, 0x1a06c, | |
844 | 0x1a0b0, 0x1a0e4, | |
845 | 0x1a0ec, 0x1a0f4, | |
846 | 0x1a100, 0x1a108, | |
847 | 0x1a114, 0x1a120, | |
848 | 0x1a128, 0x1a130, | |
849 | 0x1a138, 0x1a138, | |
812034f1 HS |
850 | 0x1a190, 0x1a1c4, |
851 | 0x1a1fc, 0x1a1fc, | |
852 | 0x1e040, 0x1e04c, | |
853 | 0x1e284, 0x1e28c, | |
854 | 0x1e2c0, 0x1e2c0, | |
855 | 0x1e2e0, 0x1e2e0, | |
856 | 0x1e300, 0x1e384, | |
857 | 0x1e3c0, 0x1e3c8, | |
858 | 0x1e440, 0x1e44c, | |
859 | 0x1e684, 0x1e68c, | |
860 | 0x1e6c0, 0x1e6c0, | |
861 | 0x1e6e0, 0x1e6e0, | |
862 | 0x1e700, 0x1e784, | |
863 | 0x1e7c0, 0x1e7c8, | |
864 | 0x1e840, 0x1e84c, | |
865 | 0x1ea84, 0x1ea8c, | |
866 | 0x1eac0, 0x1eac0, | |
867 | 0x1eae0, 0x1eae0, | |
868 | 0x1eb00, 0x1eb84, | |
869 | 0x1ebc0, 0x1ebc8, | |
870 | 0x1ec40, 0x1ec4c, | |
871 | 0x1ee84, 0x1ee8c, | |
872 | 0x1eec0, 0x1eec0, | |
873 | 0x1eee0, 0x1eee0, | |
874 | 0x1ef00, 0x1ef84, | |
875 | 0x1efc0, 0x1efc8, | |
876 | 0x1f040, 0x1f04c, | |
877 | 0x1f284, 0x1f28c, | |
878 | 0x1f2c0, 0x1f2c0, | |
879 | 0x1f2e0, 0x1f2e0, | |
880 | 0x1f300, 0x1f384, | |
881 | 0x1f3c0, 0x1f3c8, | |
882 | 0x1f440, 0x1f44c, | |
883 | 0x1f684, 0x1f68c, | |
884 | 0x1f6c0, 0x1f6c0, | |
885 | 0x1f6e0, 0x1f6e0, | |
886 | 0x1f700, 0x1f784, | |
887 | 0x1f7c0, 0x1f7c8, | |
888 | 0x1f840, 0x1f84c, | |
889 | 0x1fa84, 0x1fa8c, | |
890 | 0x1fac0, 0x1fac0, | |
891 | 0x1fae0, 0x1fae0, | |
892 | 0x1fb00, 0x1fb84, | |
893 | 0x1fbc0, 0x1fbc8, | |
894 | 0x1fc40, 0x1fc4c, | |
895 | 0x1fe84, 0x1fe8c, | |
896 | 0x1fec0, 0x1fec0, | |
897 | 0x1fee0, 0x1fee0, | |
898 | 0x1ff00, 0x1ff84, | |
899 | 0x1ffc0, 0x1ffc8, | |
900 | 0x20000, 0x2002c, | |
901 | 0x20100, 0x2013c, | |
8119c018 HS |
902 | 0x20190, 0x201a0, |
903 | 0x201a8, 0x201b8, | |
904 | 0x201c4, 0x201c8, | |
812034f1 | 905 | 0x20200, 0x20318, |
8119c018 HS |
906 | 0x20400, 0x204b4, |
907 | 0x204c0, 0x20528, | |
812034f1 HS |
908 | 0x20540, 0x20614, |
909 | 0x21000, 0x21040, | |
910 | 0x2104c, 0x21060, | |
911 | 0x210c0, 0x210ec, | |
912 | 0x21200, 0x21268, | |
913 | 0x21270, 0x21284, | |
914 | 0x212fc, 0x21388, | |
915 | 0x21400, 0x21404, | |
8119c018 HS |
916 | 0x21500, 0x21500, |
917 | 0x21510, 0x21518, | |
918 | 0x2152c, 0x21530, | |
919 | 0x2153c, 0x2153c, | |
812034f1 HS |
920 | 0x21550, 0x21554, |
921 | 0x21600, 0x21600, | |
8119c018 HS |
922 | 0x21608, 0x2161c, |
923 | 0x21624, 0x21628, | |
924 | 0x21630, 0x21634, | |
925 | 0x2163c, 0x2163c, | |
812034f1 HS |
926 | 0x21700, 0x2171c, |
927 | 0x21780, 0x2178c, | |
8119c018 HS |
928 | 0x21800, 0x21818, |
929 | 0x21820, 0x21828, | |
930 | 0x21830, 0x21848, | |
931 | 0x21850, 0x21854, | |
932 | 0x21860, 0x21868, | |
933 | 0x21870, 0x21870, | |
934 | 0x21878, 0x21898, | |
935 | 0x218a0, 0x218a8, | |
936 | 0x218b0, 0x218c8, | |
937 | 0x218d0, 0x218d4, | |
938 | 0x218e0, 0x218e8, | |
939 | 0x218f0, 0x218f0, | |
940 | 0x218f8, 0x21a18, | |
941 | 0x21a20, 0x21a28, | |
942 | 0x21a30, 0x21a48, | |
943 | 0x21a50, 0x21a54, | |
944 | 0x21a60, 0x21a68, | |
945 | 0x21a70, 0x21a70, | |
946 | 0x21a78, 0x21a98, | |
947 | 0x21aa0, 0x21aa8, | |
948 | 0x21ab0, 0x21ac8, | |
949 | 0x21ad0, 0x21ad4, | |
950 | 0x21ae0, 0x21ae8, | |
951 | 0x21af0, 0x21af0, | |
952 | 0x21af8, 0x21c18, | |
953 | 0x21c20, 0x21c20, | |
954 | 0x21c28, 0x21c30, | |
955 | 0x21c38, 0x21c38, | |
956 | 0x21c80, 0x21c98, | |
957 | 0x21ca0, 0x21ca8, | |
958 | 0x21cb0, 0x21cc8, | |
959 | 0x21cd0, 0x21cd4, | |
960 | 0x21ce0, 0x21ce8, | |
961 | 0x21cf0, 0x21cf0, | |
962 | 0x21cf8, 0x21d7c, | |
812034f1 HS |
963 | 0x21e00, 0x21e04, |
964 | 0x22000, 0x2202c, | |
965 | 0x22100, 0x2213c, | |
8119c018 HS |
966 | 0x22190, 0x221a0, |
967 | 0x221a8, 0x221b8, | |
968 | 0x221c4, 0x221c8, | |
812034f1 | 969 | 0x22200, 0x22318, |
8119c018 HS |
970 | 0x22400, 0x224b4, |
971 | 0x224c0, 0x22528, | |
812034f1 HS |
972 | 0x22540, 0x22614, |
973 | 0x23000, 0x23040, | |
974 | 0x2304c, 0x23060, | |
975 | 0x230c0, 0x230ec, | |
976 | 0x23200, 0x23268, | |
977 | 0x23270, 0x23284, | |
978 | 0x232fc, 0x23388, | |
979 | 0x23400, 0x23404, | |
8119c018 HS |
980 | 0x23500, 0x23500, |
981 | 0x23510, 0x23518, | |
982 | 0x2352c, 0x23530, | |
983 | 0x2353c, 0x2353c, | |
812034f1 HS |
984 | 0x23550, 0x23554, |
985 | 0x23600, 0x23600, | |
8119c018 HS |
986 | 0x23608, 0x2361c, |
987 | 0x23624, 0x23628, | |
988 | 0x23630, 0x23634, | |
989 | 0x2363c, 0x2363c, | |
812034f1 HS |
990 | 0x23700, 0x2371c, |
991 | 0x23780, 0x2378c, | |
8119c018 HS |
992 | 0x23800, 0x23818, |
993 | 0x23820, 0x23828, | |
994 | 0x23830, 0x23848, | |
995 | 0x23850, 0x23854, | |
996 | 0x23860, 0x23868, | |
997 | 0x23870, 0x23870, | |
998 | 0x23878, 0x23898, | |
999 | 0x238a0, 0x238a8, | |
1000 | 0x238b0, 0x238c8, | |
1001 | 0x238d0, 0x238d4, | |
1002 | 0x238e0, 0x238e8, | |
1003 | 0x238f0, 0x238f0, | |
1004 | 0x238f8, 0x23a18, | |
1005 | 0x23a20, 0x23a28, | |
1006 | 0x23a30, 0x23a48, | |
1007 | 0x23a50, 0x23a54, | |
1008 | 0x23a60, 0x23a68, | |
1009 | 0x23a70, 0x23a70, | |
1010 | 0x23a78, 0x23a98, | |
1011 | 0x23aa0, 0x23aa8, | |
1012 | 0x23ab0, 0x23ac8, | |
1013 | 0x23ad0, 0x23ad4, | |
1014 | 0x23ae0, 0x23ae8, | |
1015 | 0x23af0, 0x23af0, | |
1016 | 0x23af8, 0x23c18, | |
1017 | 0x23c20, 0x23c20, | |
1018 | 0x23c28, 0x23c30, | |
1019 | 0x23c38, 0x23c38, | |
1020 | 0x23c80, 0x23c98, | |
1021 | 0x23ca0, 0x23ca8, | |
1022 | 0x23cb0, 0x23cc8, | |
1023 | 0x23cd0, 0x23cd4, | |
1024 | 0x23ce0, 0x23ce8, | |
1025 | 0x23cf0, 0x23cf0, | |
1026 | 0x23cf8, 0x23d7c, | |
812034f1 HS |
1027 | 0x23e00, 0x23e04, |
1028 | 0x24000, 0x2402c, | |
1029 | 0x24100, 0x2413c, | |
8119c018 HS |
1030 | 0x24190, 0x241a0, |
1031 | 0x241a8, 0x241b8, | |
1032 | 0x241c4, 0x241c8, | |
812034f1 | 1033 | 0x24200, 0x24318, |
8119c018 HS |
1034 | 0x24400, 0x244b4, |
1035 | 0x244c0, 0x24528, | |
812034f1 HS |
1036 | 0x24540, 0x24614, |
1037 | 0x25000, 0x25040, | |
1038 | 0x2504c, 0x25060, | |
1039 | 0x250c0, 0x250ec, | |
1040 | 0x25200, 0x25268, | |
1041 | 0x25270, 0x25284, | |
1042 | 0x252fc, 0x25388, | |
1043 | 0x25400, 0x25404, | |
8119c018 HS |
1044 | 0x25500, 0x25500, |
1045 | 0x25510, 0x25518, | |
1046 | 0x2552c, 0x25530, | |
1047 | 0x2553c, 0x2553c, | |
812034f1 HS |
1048 | 0x25550, 0x25554, |
1049 | 0x25600, 0x25600, | |
8119c018 HS |
1050 | 0x25608, 0x2561c, |
1051 | 0x25624, 0x25628, | |
1052 | 0x25630, 0x25634, | |
1053 | 0x2563c, 0x2563c, | |
812034f1 HS |
1054 | 0x25700, 0x2571c, |
1055 | 0x25780, 0x2578c, | |
8119c018 HS |
1056 | 0x25800, 0x25818, |
1057 | 0x25820, 0x25828, | |
1058 | 0x25830, 0x25848, | |
1059 | 0x25850, 0x25854, | |
1060 | 0x25860, 0x25868, | |
1061 | 0x25870, 0x25870, | |
1062 | 0x25878, 0x25898, | |
1063 | 0x258a0, 0x258a8, | |
1064 | 0x258b0, 0x258c8, | |
1065 | 0x258d0, 0x258d4, | |
1066 | 0x258e0, 0x258e8, | |
1067 | 0x258f0, 0x258f0, | |
1068 | 0x258f8, 0x25a18, | |
1069 | 0x25a20, 0x25a28, | |
1070 | 0x25a30, 0x25a48, | |
1071 | 0x25a50, 0x25a54, | |
1072 | 0x25a60, 0x25a68, | |
1073 | 0x25a70, 0x25a70, | |
1074 | 0x25a78, 0x25a98, | |
1075 | 0x25aa0, 0x25aa8, | |
1076 | 0x25ab0, 0x25ac8, | |
1077 | 0x25ad0, 0x25ad4, | |
1078 | 0x25ae0, 0x25ae8, | |
1079 | 0x25af0, 0x25af0, | |
1080 | 0x25af8, 0x25c18, | |
1081 | 0x25c20, 0x25c20, | |
1082 | 0x25c28, 0x25c30, | |
1083 | 0x25c38, 0x25c38, | |
1084 | 0x25c80, 0x25c98, | |
1085 | 0x25ca0, 0x25ca8, | |
1086 | 0x25cb0, 0x25cc8, | |
1087 | 0x25cd0, 0x25cd4, | |
1088 | 0x25ce0, 0x25ce8, | |
1089 | 0x25cf0, 0x25cf0, | |
1090 | 0x25cf8, 0x25d7c, | |
812034f1 HS |
1091 | 0x25e00, 0x25e04, |
1092 | 0x26000, 0x2602c, | |
1093 | 0x26100, 0x2613c, | |
8119c018 HS |
1094 | 0x26190, 0x261a0, |
1095 | 0x261a8, 0x261b8, | |
1096 | 0x261c4, 0x261c8, | |
812034f1 | 1097 | 0x26200, 0x26318, |
8119c018 HS |
1098 | 0x26400, 0x264b4, |
1099 | 0x264c0, 0x26528, | |
812034f1 HS |
1100 | 0x26540, 0x26614, |
1101 | 0x27000, 0x27040, | |
1102 | 0x2704c, 0x27060, | |
1103 | 0x270c0, 0x270ec, | |
1104 | 0x27200, 0x27268, | |
1105 | 0x27270, 0x27284, | |
1106 | 0x272fc, 0x27388, | |
1107 | 0x27400, 0x27404, | |
8119c018 HS |
1108 | 0x27500, 0x27500, |
1109 | 0x27510, 0x27518, | |
1110 | 0x2752c, 0x27530, | |
1111 | 0x2753c, 0x2753c, | |
812034f1 HS |
1112 | 0x27550, 0x27554, |
1113 | 0x27600, 0x27600, | |
8119c018 HS |
1114 | 0x27608, 0x2761c, |
1115 | 0x27624, 0x27628, | |
1116 | 0x27630, 0x27634, | |
1117 | 0x2763c, 0x2763c, | |
812034f1 HS |
1118 | 0x27700, 0x2771c, |
1119 | 0x27780, 0x2778c, | |
8119c018 HS |
1120 | 0x27800, 0x27818, |
1121 | 0x27820, 0x27828, | |
1122 | 0x27830, 0x27848, | |
1123 | 0x27850, 0x27854, | |
1124 | 0x27860, 0x27868, | |
1125 | 0x27870, 0x27870, | |
1126 | 0x27878, 0x27898, | |
1127 | 0x278a0, 0x278a8, | |
1128 | 0x278b0, 0x278c8, | |
1129 | 0x278d0, 0x278d4, | |
1130 | 0x278e0, 0x278e8, | |
1131 | 0x278f0, 0x278f0, | |
1132 | 0x278f8, 0x27a18, | |
1133 | 0x27a20, 0x27a28, | |
1134 | 0x27a30, 0x27a48, | |
1135 | 0x27a50, 0x27a54, | |
1136 | 0x27a60, 0x27a68, | |
1137 | 0x27a70, 0x27a70, | |
1138 | 0x27a78, 0x27a98, | |
1139 | 0x27aa0, 0x27aa8, | |
1140 | 0x27ab0, 0x27ac8, | |
1141 | 0x27ad0, 0x27ad4, | |
1142 | 0x27ae0, 0x27ae8, | |
1143 | 0x27af0, 0x27af0, | |
1144 | 0x27af8, 0x27c18, | |
1145 | 0x27c20, 0x27c20, | |
1146 | 0x27c28, 0x27c30, | |
1147 | 0x27c38, 0x27c38, | |
1148 | 0x27c80, 0x27c98, | |
1149 | 0x27ca0, 0x27ca8, | |
1150 | 0x27cb0, 0x27cc8, | |
1151 | 0x27cd0, 0x27cd4, | |
1152 | 0x27ce0, 0x27ce8, | |
1153 | 0x27cf0, 0x27cf0, | |
1154 | 0x27cf8, 0x27d7c, | |
9f5ac48d | 1155 | 0x27e00, 0x27e04, |
812034f1 HS |
1156 | }; |
1157 | ||
1158 | static const unsigned int t5_reg_ranges[] = { | |
8119c018 HS |
1159 | 0x1008, 0x10c0, |
1160 | 0x10cc, 0x10f8, | |
1161 | 0x1100, 0x1100, | |
1162 | 0x110c, 0x1148, | |
1163 | 0x1180, 0x1184, | |
1164 | 0x1190, 0x1194, | |
1165 | 0x11a0, 0x11a4, | |
1166 | 0x11b0, 0x11b4, | |
812034f1 HS |
1167 | 0x11fc, 0x123c, |
1168 | 0x1280, 0x173c, | |
1169 | 0x1800, 0x18fc, | |
1170 | 0x3000, 0x3028, | |
8119c018 HS |
1171 | 0x3060, 0x30b0, |
1172 | 0x30b8, 0x30d8, | |
812034f1 HS |
1173 | 0x30e0, 0x30fc, |
1174 | 0x3140, 0x357c, | |
1175 | 0x35a8, 0x35cc, | |
1176 | 0x35ec, 0x35ec, | |
1177 | 0x3600, 0x5624, | |
8119c018 HS |
1178 | 0x56cc, 0x56ec, |
1179 | 0x56f4, 0x5720, | |
1180 | 0x5728, 0x575c, | |
812034f1 | 1181 | 0x580c, 0x5814, |
8119c018 HS |
1182 | 0x5890, 0x589c, |
1183 | 0x58a4, 0x58ac, | |
1184 | 0x58b8, 0x58bc, | |
1185 | 0x5940, 0x59c8, | |
1186 | 0x59d0, 0x59dc, | |
812034f1 | 1187 | 0x59fc, 0x5a18, |
8119c018 HS |
1188 | 0x5a60, 0x5a70, |
1189 | 0x5a80, 0x5a9c, | |
9f5ac48d | 1190 | 0x5b94, 0x5bfc, |
8119c018 HS |
1191 | 0x6000, 0x6020, |
1192 | 0x6028, 0x6040, | |
1193 | 0x6058, 0x609c, | |
1194 | 0x60a8, 0x614c, | |
812034f1 HS |
1195 | 0x7700, 0x7798, |
1196 | 0x77c0, 0x78fc, | |
8119c018 HS |
1197 | 0x7b00, 0x7b58, |
1198 | 0x7b60, 0x7b84, | |
1199 | 0x7b8c, 0x7c54, | |
1200 | 0x7d00, 0x7d38, | |
1201 | 0x7d40, 0x7d80, | |
1202 | 0x7d8c, 0x7ddc, | |
1203 | 0x7de4, 0x7e04, | |
1204 | 0x7e10, 0x7e1c, | |
1205 | 0x7e24, 0x7e38, | |
1206 | 0x7e40, 0x7e44, | |
1207 | 0x7e4c, 0x7e78, | |
1208 | 0x7e80, 0x7edc, | |
1209 | 0x7ee8, 0x7efc, | |
812034f1 | 1210 | 0x8dc0, 0x8de0, |
8119c018 HS |
1211 | 0x8df8, 0x8e04, |
1212 | 0x8e10, 0x8e84, | |
812034f1 | 1213 | 0x8ea0, 0x8f84, |
8119c018 HS |
1214 | 0x8fc0, 0x9058, |
1215 | 0x9060, 0x9060, | |
1216 | 0x9068, 0x90f8, | |
1217 | 0x9400, 0x9408, | |
1218 | 0x9410, 0x9470, | |
1219 | 0x9600, 0x9600, | |
1220 | 0x9608, 0x9638, | |
1221 | 0x9640, 0x96f4, | |
812034f1 HS |
1222 | 0x9800, 0x9808, |
1223 | 0x9820, 0x983c, | |
1224 | 0x9850, 0x9864, | |
1225 | 0x9c00, 0x9c6c, | |
1226 | 0x9c80, 0x9cec, | |
1227 | 0x9d00, 0x9d6c, | |
1228 | 0x9d80, 0x9dec, | |
1229 | 0x9e00, 0x9e6c, | |
1230 | 0x9e80, 0x9eec, | |
1231 | 0x9f00, 0x9f6c, | |
1232 | 0x9f80, 0xa020, | |
8119c018 HS |
1233 | 0xd004, 0xd004, |
1234 | 0xd010, 0xd03c, | |
812034f1 | 1235 | 0xdfc0, 0xdfe0, |
8119c018 HS |
1236 | 0xe000, 0x1106c, |
1237 | 0x11074, 0x11088, | |
1238 | 0x1109c, 0x1117c, | |
812034f1 HS |
1239 | 0x11190, 0x11204, |
1240 | 0x19040, 0x1906c, | |
1241 | 0x19078, 0x19080, | |
8119c018 HS |
1242 | 0x1908c, 0x190e8, |
1243 | 0x190f0, 0x190f8, | |
1244 | 0x19100, 0x19110, | |
1245 | 0x19120, 0x19124, | |
1246 | 0x19150, 0x19194, | |
1247 | 0x1919c, 0x191b0, | |
812034f1 HS |
1248 | 0x191d0, 0x191e8, |
1249 | 0x19238, 0x19290, | |
8119c018 HS |
1250 | 0x193f8, 0x19428, |
1251 | 0x19430, 0x19444, | |
1252 | 0x1944c, 0x1946c, | |
1253 | 0x19474, 0x19474, | |
812034f1 HS |
1254 | 0x19490, 0x194cc, |
1255 | 0x194f0, 0x194f8, | |
8119c018 HS |
1256 | 0x19c00, 0x19c08, |
1257 | 0x19c10, 0x19c60, | |
1258 | 0x19c94, 0x19ce4, | |
1259 | 0x19cf0, 0x19d40, | |
1260 | 0x19d50, 0x19d94, | |
1261 | 0x19da0, 0x19de8, | |
1262 | 0x19df0, 0x19e10, | |
1263 | 0x19e50, 0x19e90, | |
1264 | 0x19ea0, 0x19f24, | |
1265 | 0x19f34, 0x19f34, | |
812034f1 | 1266 | 0x19f40, 0x19f50, |
8119c018 HS |
1267 | 0x19f90, 0x19fb4, |
1268 | 0x19fc4, 0x19fe4, | |
1269 | 0x1a000, 0x1a004, | |
1270 | 0x1a010, 0x1a06c, | |
1271 | 0x1a0b0, 0x1a0e4, | |
1272 | 0x1a0ec, 0x1a0f8, | |
1273 | 0x1a100, 0x1a108, | |
1274 | 0x1a114, 0x1a120, | |
1275 | 0x1a128, 0x1a130, | |
1276 | 0x1a138, 0x1a138, | |
812034f1 HS |
1277 | 0x1a190, 0x1a1c4, |
1278 | 0x1a1fc, 0x1a1fc, | |
1279 | 0x1e008, 0x1e00c, | |
8119c018 HS |
1280 | 0x1e040, 0x1e044, |
1281 | 0x1e04c, 0x1e04c, | |
812034f1 HS |
1282 | 0x1e284, 0x1e290, |
1283 | 0x1e2c0, 0x1e2c0, | |
1284 | 0x1e2e0, 0x1e2e0, | |
1285 | 0x1e300, 0x1e384, | |
1286 | 0x1e3c0, 0x1e3c8, | |
1287 | 0x1e408, 0x1e40c, | |
8119c018 HS |
1288 | 0x1e440, 0x1e444, |
1289 | 0x1e44c, 0x1e44c, | |
812034f1 HS |
1290 | 0x1e684, 0x1e690, |
1291 | 0x1e6c0, 0x1e6c0, | |
1292 | 0x1e6e0, 0x1e6e0, | |
1293 | 0x1e700, 0x1e784, | |
1294 | 0x1e7c0, 0x1e7c8, | |
1295 | 0x1e808, 0x1e80c, | |
8119c018 HS |
1296 | 0x1e840, 0x1e844, |
1297 | 0x1e84c, 0x1e84c, | |
812034f1 HS |
1298 | 0x1ea84, 0x1ea90, |
1299 | 0x1eac0, 0x1eac0, | |
1300 | 0x1eae0, 0x1eae0, | |
1301 | 0x1eb00, 0x1eb84, | |
1302 | 0x1ebc0, 0x1ebc8, | |
1303 | 0x1ec08, 0x1ec0c, | |
8119c018 HS |
1304 | 0x1ec40, 0x1ec44, |
1305 | 0x1ec4c, 0x1ec4c, | |
812034f1 HS |
1306 | 0x1ee84, 0x1ee90, |
1307 | 0x1eec0, 0x1eec0, | |
1308 | 0x1eee0, 0x1eee0, | |
1309 | 0x1ef00, 0x1ef84, | |
1310 | 0x1efc0, 0x1efc8, | |
1311 | 0x1f008, 0x1f00c, | |
8119c018 HS |
1312 | 0x1f040, 0x1f044, |
1313 | 0x1f04c, 0x1f04c, | |
812034f1 HS |
1314 | 0x1f284, 0x1f290, |
1315 | 0x1f2c0, 0x1f2c0, | |
1316 | 0x1f2e0, 0x1f2e0, | |
1317 | 0x1f300, 0x1f384, | |
1318 | 0x1f3c0, 0x1f3c8, | |
1319 | 0x1f408, 0x1f40c, | |
8119c018 HS |
1320 | 0x1f440, 0x1f444, |
1321 | 0x1f44c, 0x1f44c, | |
812034f1 HS |
1322 | 0x1f684, 0x1f690, |
1323 | 0x1f6c0, 0x1f6c0, | |
1324 | 0x1f6e0, 0x1f6e0, | |
1325 | 0x1f700, 0x1f784, | |
1326 | 0x1f7c0, 0x1f7c8, | |
1327 | 0x1f808, 0x1f80c, | |
8119c018 HS |
1328 | 0x1f840, 0x1f844, |
1329 | 0x1f84c, 0x1f84c, | |
812034f1 HS |
1330 | 0x1fa84, 0x1fa90, |
1331 | 0x1fac0, 0x1fac0, | |
1332 | 0x1fae0, 0x1fae0, | |
1333 | 0x1fb00, 0x1fb84, | |
1334 | 0x1fbc0, 0x1fbc8, | |
1335 | 0x1fc08, 0x1fc0c, | |
8119c018 HS |
1336 | 0x1fc40, 0x1fc44, |
1337 | 0x1fc4c, 0x1fc4c, | |
812034f1 HS |
1338 | 0x1fe84, 0x1fe90, |
1339 | 0x1fec0, 0x1fec0, | |
1340 | 0x1fee0, 0x1fee0, | |
1341 | 0x1ff00, 0x1ff84, | |
1342 | 0x1ffc0, 0x1ffc8, | |
1343 | 0x30000, 0x30030, | |
8119c018 HS |
1344 | 0x30038, 0x30038, |
1345 | 0x30040, 0x30040, | |
812034f1 | 1346 | 0x30100, 0x30144, |
8119c018 HS |
1347 | 0x30190, 0x301a0, |
1348 | 0x301a8, 0x301b8, | |
1349 | 0x301c4, 0x301c8, | |
1350 | 0x301d0, 0x301d0, | |
812034f1 | 1351 | 0x30200, 0x30318, |
8119c018 HS |
1352 | 0x30400, 0x304b4, |
1353 | 0x304c0, 0x3052c, | |
812034f1 | 1354 | 0x30540, 0x3061c, |
8119c018 HS |
1355 | 0x30800, 0x30828, |
1356 | 0x30834, 0x30834, | |
812034f1 HS |
1357 | 0x308c0, 0x30908, |
1358 | 0x30910, 0x309ac, | |
8119c018 HS |
1359 | 0x30a00, 0x30a14, |
1360 | 0x30a1c, 0x30a2c, | |
812034f1 | 1361 | 0x30a44, 0x30a50, |
8119c018 HS |
1362 | 0x30a74, 0x30a74, |
1363 | 0x30a7c, 0x30afc, | |
1364 | 0x30b08, 0x30c24, | |
9f5ac48d | 1365 | 0x30d00, 0x30d00, |
812034f1 HS |
1366 | 0x30d08, 0x30d14, |
1367 | 0x30d1c, 0x30d20, | |
8119c018 HS |
1368 | 0x30d3c, 0x30d3c, |
1369 | 0x30d48, 0x30d50, | |
812034f1 HS |
1370 | 0x31200, 0x3120c, |
1371 | 0x31220, 0x31220, | |
1372 | 0x31240, 0x31240, | |
9f5ac48d | 1373 | 0x31600, 0x3160c, |
812034f1 | 1374 | 0x31a00, 0x31a1c, |
9f5ac48d | 1375 | 0x31e00, 0x31e20, |
812034f1 HS |
1376 | 0x31e38, 0x31e3c, |
1377 | 0x31e80, 0x31e80, | |
1378 | 0x31e88, 0x31ea8, | |
1379 | 0x31eb0, 0x31eb4, | |
1380 | 0x31ec8, 0x31ed4, | |
1381 | 0x31fb8, 0x32004, | |
9f5ac48d HS |
1382 | 0x32200, 0x32200, |
1383 | 0x32208, 0x32240, | |
1384 | 0x32248, 0x32280, | |
1385 | 0x32288, 0x322c0, | |
1386 | 0x322c8, 0x322fc, | |
812034f1 HS |
1387 | 0x32600, 0x32630, |
1388 | 0x32a00, 0x32abc, | |
8119c018 HS |
1389 | 0x32b00, 0x32b10, |
1390 | 0x32b20, 0x32b30, | |
1391 | 0x32b40, 0x32b50, | |
1392 | 0x32b60, 0x32b70, | |
1393 | 0x33000, 0x33028, | |
1394 | 0x33030, 0x33048, | |
1395 | 0x33060, 0x33068, | |
1396 | 0x33070, 0x3309c, | |
1397 | 0x330f0, 0x33128, | |
1398 | 0x33130, 0x33148, | |
1399 | 0x33160, 0x33168, | |
1400 | 0x33170, 0x3319c, | |
1401 | 0x331f0, 0x33238, | |
1402 | 0x33240, 0x33240, | |
1403 | 0x33248, 0x33250, | |
1404 | 0x3325c, 0x33264, | |
1405 | 0x33270, 0x332b8, | |
1406 | 0x332c0, 0x332e4, | |
1407 | 0x332f8, 0x33338, | |
1408 | 0x33340, 0x33340, | |
1409 | 0x33348, 0x33350, | |
1410 | 0x3335c, 0x33364, | |
1411 | 0x33370, 0x333b8, | |
1412 | 0x333c0, 0x333e4, | |
1413 | 0x333f8, 0x33428, | |
1414 | 0x33430, 0x33448, | |
1415 | 0x33460, 0x33468, | |
1416 | 0x33470, 0x3349c, | |
1417 | 0x334f0, 0x33528, | |
1418 | 0x33530, 0x33548, | |
1419 | 0x33560, 0x33568, | |
1420 | 0x33570, 0x3359c, | |
1421 | 0x335f0, 0x33638, | |
1422 | 0x33640, 0x33640, | |
1423 | 0x33648, 0x33650, | |
1424 | 0x3365c, 0x33664, | |
1425 | 0x33670, 0x336b8, | |
1426 | 0x336c0, 0x336e4, | |
1427 | 0x336f8, 0x33738, | |
1428 | 0x33740, 0x33740, | |
1429 | 0x33748, 0x33750, | |
1430 | 0x3375c, 0x33764, | |
1431 | 0x33770, 0x337b8, | |
1432 | 0x337c0, 0x337e4, | |
812034f1 HS |
1433 | 0x337f8, 0x337fc, |
1434 | 0x33814, 0x33814, | |
1435 | 0x3382c, 0x3382c, | |
1436 | 0x33880, 0x3388c, | |
1437 | 0x338e8, 0x338ec, | |
8119c018 HS |
1438 | 0x33900, 0x33928, |
1439 | 0x33930, 0x33948, | |
1440 | 0x33960, 0x33968, | |
1441 | 0x33970, 0x3399c, | |
1442 | 0x339f0, 0x33a38, | |
1443 | 0x33a40, 0x33a40, | |
1444 | 0x33a48, 0x33a50, | |
1445 | 0x33a5c, 0x33a64, | |
1446 | 0x33a70, 0x33ab8, | |
1447 | 0x33ac0, 0x33ae4, | |
812034f1 HS |
1448 | 0x33af8, 0x33b10, |
1449 | 0x33b28, 0x33b28, | |
1450 | 0x33b3c, 0x33b50, | |
1451 | 0x33bf0, 0x33c10, | |
1452 | 0x33c28, 0x33c28, | |
1453 | 0x33c3c, 0x33c50, | |
1454 | 0x33cf0, 0x33cfc, | |
1455 | 0x34000, 0x34030, | |
8119c018 HS |
1456 | 0x34038, 0x34038, |
1457 | 0x34040, 0x34040, | |
812034f1 | 1458 | 0x34100, 0x34144, |
8119c018 HS |
1459 | 0x34190, 0x341a0, |
1460 | 0x341a8, 0x341b8, | |
1461 | 0x341c4, 0x341c8, | |
1462 | 0x341d0, 0x341d0, | |
812034f1 | 1463 | 0x34200, 0x34318, |
8119c018 HS |
1464 | 0x34400, 0x344b4, |
1465 | 0x344c0, 0x3452c, | |
812034f1 | 1466 | 0x34540, 0x3461c, |
8119c018 HS |
1467 | 0x34800, 0x34828, |
1468 | 0x34834, 0x34834, | |
812034f1 HS |
1469 | 0x348c0, 0x34908, |
1470 | 0x34910, 0x349ac, | |
8119c018 HS |
1471 | 0x34a00, 0x34a14, |
1472 | 0x34a1c, 0x34a2c, | |
812034f1 | 1473 | 0x34a44, 0x34a50, |
8119c018 HS |
1474 | 0x34a74, 0x34a74, |
1475 | 0x34a7c, 0x34afc, | |
1476 | 0x34b08, 0x34c24, | |
9f5ac48d | 1477 | 0x34d00, 0x34d00, |
812034f1 HS |
1478 | 0x34d08, 0x34d14, |
1479 | 0x34d1c, 0x34d20, | |
8119c018 HS |
1480 | 0x34d3c, 0x34d3c, |
1481 | 0x34d48, 0x34d50, | |
812034f1 HS |
1482 | 0x35200, 0x3520c, |
1483 | 0x35220, 0x35220, | |
1484 | 0x35240, 0x35240, | |
9f5ac48d | 1485 | 0x35600, 0x3560c, |
812034f1 | 1486 | 0x35a00, 0x35a1c, |
9f5ac48d | 1487 | 0x35e00, 0x35e20, |
812034f1 HS |
1488 | 0x35e38, 0x35e3c, |
1489 | 0x35e80, 0x35e80, | |
1490 | 0x35e88, 0x35ea8, | |
1491 | 0x35eb0, 0x35eb4, | |
1492 | 0x35ec8, 0x35ed4, | |
1493 | 0x35fb8, 0x36004, | |
9f5ac48d HS |
1494 | 0x36200, 0x36200, |
1495 | 0x36208, 0x36240, | |
1496 | 0x36248, 0x36280, | |
1497 | 0x36288, 0x362c0, | |
1498 | 0x362c8, 0x362fc, | |
812034f1 HS |
1499 | 0x36600, 0x36630, |
1500 | 0x36a00, 0x36abc, | |
8119c018 HS |
1501 | 0x36b00, 0x36b10, |
1502 | 0x36b20, 0x36b30, | |
1503 | 0x36b40, 0x36b50, | |
1504 | 0x36b60, 0x36b70, | |
1505 | 0x37000, 0x37028, | |
1506 | 0x37030, 0x37048, | |
1507 | 0x37060, 0x37068, | |
1508 | 0x37070, 0x3709c, | |
1509 | 0x370f0, 0x37128, | |
1510 | 0x37130, 0x37148, | |
1511 | 0x37160, 0x37168, | |
1512 | 0x37170, 0x3719c, | |
1513 | 0x371f0, 0x37238, | |
1514 | 0x37240, 0x37240, | |
1515 | 0x37248, 0x37250, | |
1516 | 0x3725c, 0x37264, | |
1517 | 0x37270, 0x372b8, | |
1518 | 0x372c0, 0x372e4, | |
1519 | 0x372f8, 0x37338, | |
1520 | 0x37340, 0x37340, | |
1521 | 0x37348, 0x37350, | |
1522 | 0x3735c, 0x37364, | |
1523 | 0x37370, 0x373b8, | |
1524 | 0x373c0, 0x373e4, | |
1525 | 0x373f8, 0x37428, | |
1526 | 0x37430, 0x37448, | |
1527 | 0x37460, 0x37468, | |
1528 | 0x37470, 0x3749c, | |
1529 | 0x374f0, 0x37528, | |
1530 | 0x37530, 0x37548, | |
1531 | 0x37560, 0x37568, | |
1532 | 0x37570, 0x3759c, | |
1533 | 0x375f0, 0x37638, | |
1534 | 0x37640, 0x37640, | |
1535 | 0x37648, 0x37650, | |
1536 | 0x3765c, 0x37664, | |
1537 | 0x37670, 0x376b8, | |
1538 | 0x376c0, 0x376e4, | |
1539 | 0x376f8, 0x37738, | |
1540 | 0x37740, 0x37740, | |
1541 | 0x37748, 0x37750, | |
1542 | 0x3775c, 0x37764, | |
1543 | 0x37770, 0x377b8, | |
1544 | 0x377c0, 0x377e4, | |
812034f1 HS |
1545 | 0x377f8, 0x377fc, |
1546 | 0x37814, 0x37814, | |
1547 | 0x3782c, 0x3782c, | |
1548 | 0x37880, 0x3788c, | |
1549 | 0x378e8, 0x378ec, | |
8119c018 HS |
1550 | 0x37900, 0x37928, |
1551 | 0x37930, 0x37948, | |
1552 | 0x37960, 0x37968, | |
1553 | 0x37970, 0x3799c, | |
1554 | 0x379f0, 0x37a38, | |
1555 | 0x37a40, 0x37a40, | |
1556 | 0x37a48, 0x37a50, | |
1557 | 0x37a5c, 0x37a64, | |
1558 | 0x37a70, 0x37ab8, | |
1559 | 0x37ac0, 0x37ae4, | |
812034f1 HS |
1560 | 0x37af8, 0x37b10, |
1561 | 0x37b28, 0x37b28, | |
1562 | 0x37b3c, 0x37b50, | |
1563 | 0x37bf0, 0x37c10, | |
1564 | 0x37c28, 0x37c28, | |
1565 | 0x37c3c, 0x37c50, | |
1566 | 0x37cf0, 0x37cfc, | |
1567 | 0x38000, 0x38030, | |
8119c018 HS |
1568 | 0x38038, 0x38038, |
1569 | 0x38040, 0x38040, | |
812034f1 | 1570 | 0x38100, 0x38144, |
8119c018 HS |
1571 | 0x38190, 0x381a0, |
1572 | 0x381a8, 0x381b8, | |
1573 | 0x381c4, 0x381c8, | |
1574 | 0x381d0, 0x381d0, | |
812034f1 | 1575 | 0x38200, 0x38318, |
8119c018 HS |
1576 | 0x38400, 0x384b4, |
1577 | 0x384c0, 0x3852c, | |
812034f1 | 1578 | 0x38540, 0x3861c, |
8119c018 HS |
1579 | 0x38800, 0x38828, |
1580 | 0x38834, 0x38834, | |
812034f1 HS |
1581 | 0x388c0, 0x38908, |
1582 | 0x38910, 0x389ac, | |
8119c018 HS |
1583 | 0x38a00, 0x38a14, |
1584 | 0x38a1c, 0x38a2c, | |
812034f1 | 1585 | 0x38a44, 0x38a50, |
8119c018 HS |
1586 | 0x38a74, 0x38a74, |
1587 | 0x38a7c, 0x38afc, | |
1588 | 0x38b08, 0x38c24, | |
9f5ac48d | 1589 | 0x38d00, 0x38d00, |
812034f1 HS |
1590 | 0x38d08, 0x38d14, |
1591 | 0x38d1c, 0x38d20, | |
8119c018 HS |
1592 | 0x38d3c, 0x38d3c, |
1593 | 0x38d48, 0x38d50, | |
812034f1 HS |
1594 | 0x39200, 0x3920c, |
1595 | 0x39220, 0x39220, | |
1596 | 0x39240, 0x39240, | |
9f5ac48d | 1597 | 0x39600, 0x3960c, |
812034f1 | 1598 | 0x39a00, 0x39a1c, |
9f5ac48d | 1599 | 0x39e00, 0x39e20, |
812034f1 HS |
1600 | 0x39e38, 0x39e3c, |
1601 | 0x39e80, 0x39e80, | |
1602 | 0x39e88, 0x39ea8, | |
1603 | 0x39eb0, 0x39eb4, | |
1604 | 0x39ec8, 0x39ed4, | |
1605 | 0x39fb8, 0x3a004, | |
9f5ac48d HS |
1606 | 0x3a200, 0x3a200, |
1607 | 0x3a208, 0x3a240, | |
1608 | 0x3a248, 0x3a280, | |
1609 | 0x3a288, 0x3a2c0, | |
1610 | 0x3a2c8, 0x3a2fc, | |
812034f1 HS |
1611 | 0x3a600, 0x3a630, |
1612 | 0x3aa00, 0x3aabc, | |
8119c018 HS |
1613 | 0x3ab00, 0x3ab10, |
1614 | 0x3ab20, 0x3ab30, | |
1615 | 0x3ab40, 0x3ab50, | |
1616 | 0x3ab60, 0x3ab70, | |
1617 | 0x3b000, 0x3b028, | |
1618 | 0x3b030, 0x3b048, | |
1619 | 0x3b060, 0x3b068, | |
1620 | 0x3b070, 0x3b09c, | |
1621 | 0x3b0f0, 0x3b128, | |
1622 | 0x3b130, 0x3b148, | |
1623 | 0x3b160, 0x3b168, | |
1624 | 0x3b170, 0x3b19c, | |
1625 | 0x3b1f0, 0x3b238, | |
1626 | 0x3b240, 0x3b240, | |
1627 | 0x3b248, 0x3b250, | |
1628 | 0x3b25c, 0x3b264, | |
1629 | 0x3b270, 0x3b2b8, | |
1630 | 0x3b2c0, 0x3b2e4, | |
1631 | 0x3b2f8, 0x3b338, | |
1632 | 0x3b340, 0x3b340, | |
1633 | 0x3b348, 0x3b350, | |
1634 | 0x3b35c, 0x3b364, | |
1635 | 0x3b370, 0x3b3b8, | |
1636 | 0x3b3c0, 0x3b3e4, | |
1637 | 0x3b3f8, 0x3b428, | |
1638 | 0x3b430, 0x3b448, | |
1639 | 0x3b460, 0x3b468, | |
1640 | 0x3b470, 0x3b49c, | |
1641 | 0x3b4f0, 0x3b528, | |
1642 | 0x3b530, 0x3b548, | |
1643 | 0x3b560, 0x3b568, | |
1644 | 0x3b570, 0x3b59c, | |
1645 | 0x3b5f0, 0x3b638, | |
1646 | 0x3b640, 0x3b640, | |
1647 | 0x3b648, 0x3b650, | |
1648 | 0x3b65c, 0x3b664, | |
1649 | 0x3b670, 0x3b6b8, | |
1650 | 0x3b6c0, 0x3b6e4, | |
1651 | 0x3b6f8, 0x3b738, | |
1652 | 0x3b740, 0x3b740, | |
1653 | 0x3b748, 0x3b750, | |
1654 | 0x3b75c, 0x3b764, | |
1655 | 0x3b770, 0x3b7b8, | |
1656 | 0x3b7c0, 0x3b7e4, | |
812034f1 HS |
1657 | 0x3b7f8, 0x3b7fc, |
1658 | 0x3b814, 0x3b814, | |
1659 | 0x3b82c, 0x3b82c, | |
1660 | 0x3b880, 0x3b88c, | |
1661 | 0x3b8e8, 0x3b8ec, | |
8119c018 HS |
1662 | 0x3b900, 0x3b928, |
1663 | 0x3b930, 0x3b948, | |
1664 | 0x3b960, 0x3b968, | |
1665 | 0x3b970, 0x3b99c, | |
1666 | 0x3b9f0, 0x3ba38, | |
1667 | 0x3ba40, 0x3ba40, | |
1668 | 0x3ba48, 0x3ba50, | |
1669 | 0x3ba5c, 0x3ba64, | |
1670 | 0x3ba70, 0x3bab8, | |
1671 | 0x3bac0, 0x3bae4, | |
812034f1 HS |
1672 | 0x3baf8, 0x3bb10, |
1673 | 0x3bb28, 0x3bb28, | |
1674 | 0x3bb3c, 0x3bb50, | |
1675 | 0x3bbf0, 0x3bc10, | |
1676 | 0x3bc28, 0x3bc28, | |
1677 | 0x3bc3c, 0x3bc50, | |
1678 | 0x3bcf0, 0x3bcfc, | |
1679 | 0x3c000, 0x3c030, | |
8119c018 HS |
1680 | 0x3c038, 0x3c038, |
1681 | 0x3c040, 0x3c040, | |
812034f1 | 1682 | 0x3c100, 0x3c144, |
8119c018 HS |
1683 | 0x3c190, 0x3c1a0, |
1684 | 0x3c1a8, 0x3c1b8, | |
1685 | 0x3c1c4, 0x3c1c8, | |
1686 | 0x3c1d0, 0x3c1d0, | |
812034f1 | 1687 | 0x3c200, 0x3c318, |
8119c018 HS |
1688 | 0x3c400, 0x3c4b4, |
1689 | 0x3c4c0, 0x3c52c, | |
812034f1 | 1690 | 0x3c540, 0x3c61c, |
8119c018 HS |
1691 | 0x3c800, 0x3c828, |
1692 | 0x3c834, 0x3c834, | |
812034f1 HS |
1693 | 0x3c8c0, 0x3c908, |
1694 | 0x3c910, 0x3c9ac, | |
8119c018 HS |
1695 | 0x3ca00, 0x3ca14, |
1696 | 0x3ca1c, 0x3ca2c, | |
812034f1 | 1697 | 0x3ca44, 0x3ca50, |
8119c018 HS |
1698 | 0x3ca74, 0x3ca74, |
1699 | 0x3ca7c, 0x3cafc, | |
1700 | 0x3cb08, 0x3cc24, | |
9f5ac48d | 1701 | 0x3cd00, 0x3cd00, |
812034f1 HS |
1702 | 0x3cd08, 0x3cd14, |
1703 | 0x3cd1c, 0x3cd20, | |
8119c018 HS |
1704 | 0x3cd3c, 0x3cd3c, |
1705 | 0x3cd48, 0x3cd50, | |
812034f1 HS |
1706 | 0x3d200, 0x3d20c, |
1707 | 0x3d220, 0x3d220, | |
1708 | 0x3d240, 0x3d240, | |
9f5ac48d | 1709 | 0x3d600, 0x3d60c, |
812034f1 | 1710 | 0x3da00, 0x3da1c, |
9f5ac48d | 1711 | 0x3de00, 0x3de20, |
812034f1 HS |
1712 | 0x3de38, 0x3de3c, |
1713 | 0x3de80, 0x3de80, | |
1714 | 0x3de88, 0x3dea8, | |
1715 | 0x3deb0, 0x3deb4, | |
1716 | 0x3dec8, 0x3ded4, | |
1717 | 0x3dfb8, 0x3e004, | |
9f5ac48d HS |
1718 | 0x3e200, 0x3e200, |
1719 | 0x3e208, 0x3e240, | |
1720 | 0x3e248, 0x3e280, | |
1721 | 0x3e288, 0x3e2c0, | |
1722 | 0x3e2c8, 0x3e2fc, | |
812034f1 HS |
1723 | 0x3e600, 0x3e630, |
1724 | 0x3ea00, 0x3eabc, | |
8119c018 HS |
1725 | 0x3eb00, 0x3eb10, |
1726 | 0x3eb20, 0x3eb30, | |
1727 | 0x3eb40, 0x3eb50, | |
1728 | 0x3eb60, 0x3eb70, | |
1729 | 0x3f000, 0x3f028, | |
1730 | 0x3f030, 0x3f048, | |
1731 | 0x3f060, 0x3f068, | |
1732 | 0x3f070, 0x3f09c, | |
1733 | 0x3f0f0, 0x3f128, | |
1734 | 0x3f130, 0x3f148, | |
1735 | 0x3f160, 0x3f168, | |
1736 | 0x3f170, 0x3f19c, | |
1737 | 0x3f1f0, 0x3f238, | |
1738 | 0x3f240, 0x3f240, | |
1739 | 0x3f248, 0x3f250, | |
1740 | 0x3f25c, 0x3f264, | |
1741 | 0x3f270, 0x3f2b8, | |
1742 | 0x3f2c0, 0x3f2e4, | |
1743 | 0x3f2f8, 0x3f338, | |
1744 | 0x3f340, 0x3f340, | |
1745 | 0x3f348, 0x3f350, | |
1746 | 0x3f35c, 0x3f364, | |
1747 | 0x3f370, 0x3f3b8, | |
1748 | 0x3f3c0, 0x3f3e4, | |
1749 | 0x3f3f8, 0x3f428, | |
1750 | 0x3f430, 0x3f448, | |
1751 | 0x3f460, 0x3f468, | |
1752 | 0x3f470, 0x3f49c, | |
1753 | 0x3f4f0, 0x3f528, | |
1754 | 0x3f530, 0x3f548, | |
1755 | 0x3f560, 0x3f568, | |
1756 | 0x3f570, 0x3f59c, | |
1757 | 0x3f5f0, 0x3f638, | |
1758 | 0x3f640, 0x3f640, | |
1759 | 0x3f648, 0x3f650, | |
1760 | 0x3f65c, 0x3f664, | |
1761 | 0x3f670, 0x3f6b8, | |
1762 | 0x3f6c0, 0x3f6e4, | |
1763 | 0x3f6f8, 0x3f738, | |
1764 | 0x3f740, 0x3f740, | |
1765 | 0x3f748, 0x3f750, | |
1766 | 0x3f75c, 0x3f764, | |
1767 | 0x3f770, 0x3f7b8, | |
1768 | 0x3f7c0, 0x3f7e4, | |
812034f1 HS |
1769 | 0x3f7f8, 0x3f7fc, |
1770 | 0x3f814, 0x3f814, | |
1771 | 0x3f82c, 0x3f82c, | |
1772 | 0x3f880, 0x3f88c, | |
1773 | 0x3f8e8, 0x3f8ec, | |
8119c018 HS |
1774 | 0x3f900, 0x3f928, |
1775 | 0x3f930, 0x3f948, | |
1776 | 0x3f960, 0x3f968, | |
1777 | 0x3f970, 0x3f99c, | |
1778 | 0x3f9f0, 0x3fa38, | |
1779 | 0x3fa40, 0x3fa40, | |
1780 | 0x3fa48, 0x3fa50, | |
1781 | 0x3fa5c, 0x3fa64, | |
1782 | 0x3fa70, 0x3fab8, | |
1783 | 0x3fac0, 0x3fae4, | |
812034f1 HS |
1784 | 0x3faf8, 0x3fb10, |
1785 | 0x3fb28, 0x3fb28, | |
1786 | 0x3fb3c, 0x3fb50, | |
1787 | 0x3fbf0, 0x3fc10, | |
1788 | 0x3fc28, 0x3fc28, | |
1789 | 0x3fc3c, 0x3fc50, | |
1790 | 0x3fcf0, 0x3fcfc, | |
1791 | 0x40000, 0x4000c, | |
8119c018 HS |
1792 | 0x40040, 0x40050, |
1793 | 0x40060, 0x40068, | |
1794 | 0x4007c, 0x4008c, | |
1795 | 0x40094, 0x400b0, | |
1796 | 0x400c0, 0x40144, | |
812034f1 | 1797 | 0x40180, 0x4018c, |
8119c018 HS |
1798 | 0x40200, 0x40254, |
1799 | 0x40260, 0x40264, | |
1800 | 0x40270, 0x40288, | |
1801 | 0x40290, 0x40298, | |
1802 | 0x402ac, 0x402c8, | |
1803 | 0x402d0, 0x402e0, | |
1804 | 0x402f0, 0x402f0, | |
1805 | 0x40300, 0x4033c, | |
812034f1 HS |
1806 | 0x403f8, 0x403fc, |
1807 | 0x41304, 0x413c4, | |
8119c018 HS |
1808 | 0x41400, 0x4140c, |
1809 | 0x41414, 0x4141c, | |
812034f1 | 1810 | 0x41480, 0x414d0, |
8119c018 HS |
1811 | 0x44000, 0x44054, |
1812 | 0x4405c, 0x44078, | |
1813 | 0x440c0, 0x44174, | |
1814 | 0x44180, 0x441ac, | |
1815 | 0x441b4, 0x441b8, | |
1816 | 0x441c0, 0x44254, | |
1817 | 0x4425c, 0x44278, | |
1818 | 0x442c0, 0x44374, | |
1819 | 0x44380, 0x443ac, | |
1820 | 0x443b4, 0x443b8, | |
1821 | 0x443c0, 0x44454, | |
1822 | 0x4445c, 0x44478, | |
1823 | 0x444c0, 0x44574, | |
1824 | 0x44580, 0x445ac, | |
1825 | 0x445b4, 0x445b8, | |
1826 | 0x445c0, 0x44654, | |
1827 | 0x4465c, 0x44678, | |
1828 | 0x446c0, 0x44774, | |
1829 | 0x44780, 0x447ac, | |
1830 | 0x447b4, 0x447b8, | |
1831 | 0x447c0, 0x44854, | |
1832 | 0x4485c, 0x44878, | |
1833 | 0x448c0, 0x44974, | |
1834 | 0x44980, 0x449ac, | |
1835 | 0x449b4, 0x449b8, | |
1836 | 0x449c0, 0x449fc, | |
1837 | 0x45000, 0x45004, | |
1838 | 0x45010, 0x45030, | |
1839 | 0x45040, 0x45060, | |
1840 | 0x45068, 0x45068, | |
812034f1 HS |
1841 | 0x45080, 0x45084, |
1842 | 0x450a0, 0x450b0, | |
8119c018 HS |
1843 | 0x45200, 0x45204, |
1844 | 0x45210, 0x45230, | |
1845 | 0x45240, 0x45260, | |
1846 | 0x45268, 0x45268, | |
812034f1 HS |
1847 | 0x45280, 0x45284, |
1848 | 0x452a0, 0x452b0, | |
1849 | 0x460c0, 0x460e4, | |
8119c018 HS |
1850 | 0x47000, 0x4703c, |
1851 | 0x47044, 0x4708c, | |
812034f1 | 1852 | 0x47200, 0x47250, |
8119c018 HS |
1853 | 0x47400, 0x47408, |
1854 | 0x47414, 0x47420, | |
812034f1 HS |
1855 | 0x47600, 0x47618, |
1856 | 0x47800, 0x47814, | |
1857 | 0x48000, 0x4800c, | |
8119c018 HS |
1858 | 0x48040, 0x48050, |
1859 | 0x48060, 0x48068, | |
1860 | 0x4807c, 0x4808c, | |
1861 | 0x48094, 0x480b0, | |
1862 | 0x480c0, 0x48144, | |
812034f1 | 1863 | 0x48180, 0x4818c, |
8119c018 HS |
1864 | 0x48200, 0x48254, |
1865 | 0x48260, 0x48264, | |
1866 | 0x48270, 0x48288, | |
1867 | 0x48290, 0x48298, | |
1868 | 0x482ac, 0x482c8, | |
1869 | 0x482d0, 0x482e0, | |
1870 | 0x482f0, 0x482f0, | |
1871 | 0x48300, 0x4833c, | |
812034f1 HS |
1872 | 0x483f8, 0x483fc, |
1873 | 0x49304, 0x493c4, | |
8119c018 HS |
1874 | 0x49400, 0x4940c, |
1875 | 0x49414, 0x4941c, | |
812034f1 | 1876 | 0x49480, 0x494d0, |
8119c018 HS |
1877 | 0x4c000, 0x4c054, |
1878 | 0x4c05c, 0x4c078, | |
1879 | 0x4c0c0, 0x4c174, | |
1880 | 0x4c180, 0x4c1ac, | |
1881 | 0x4c1b4, 0x4c1b8, | |
1882 | 0x4c1c0, 0x4c254, | |
1883 | 0x4c25c, 0x4c278, | |
1884 | 0x4c2c0, 0x4c374, | |
1885 | 0x4c380, 0x4c3ac, | |
1886 | 0x4c3b4, 0x4c3b8, | |
1887 | 0x4c3c0, 0x4c454, | |
1888 | 0x4c45c, 0x4c478, | |
1889 | 0x4c4c0, 0x4c574, | |
1890 | 0x4c580, 0x4c5ac, | |
1891 | 0x4c5b4, 0x4c5b8, | |
1892 | 0x4c5c0, 0x4c654, | |
1893 | 0x4c65c, 0x4c678, | |
1894 | 0x4c6c0, 0x4c774, | |
1895 | 0x4c780, 0x4c7ac, | |
1896 | 0x4c7b4, 0x4c7b8, | |
1897 | 0x4c7c0, 0x4c854, | |
1898 | 0x4c85c, 0x4c878, | |
1899 | 0x4c8c0, 0x4c974, | |
1900 | 0x4c980, 0x4c9ac, | |
1901 | 0x4c9b4, 0x4c9b8, | |
1902 | 0x4c9c0, 0x4c9fc, | |
1903 | 0x4d000, 0x4d004, | |
1904 | 0x4d010, 0x4d030, | |
1905 | 0x4d040, 0x4d060, | |
1906 | 0x4d068, 0x4d068, | |
812034f1 HS |
1907 | 0x4d080, 0x4d084, |
1908 | 0x4d0a0, 0x4d0b0, | |
8119c018 HS |
1909 | 0x4d200, 0x4d204, |
1910 | 0x4d210, 0x4d230, | |
1911 | 0x4d240, 0x4d260, | |
1912 | 0x4d268, 0x4d268, | |
812034f1 HS |
1913 | 0x4d280, 0x4d284, |
1914 | 0x4d2a0, 0x4d2b0, | |
1915 | 0x4e0c0, 0x4e0e4, | |
8119c018 HS |
1916 | 0x4f000, 0x4f03c, |
1917 | 0x4f044, 0x4f08c, | |
812034f1 | 1918 | 0x4f200, 0x4f250, |
8119c018 HS |
1919 | 0x4f400, 0x4f408, |
1920 | 0x4f414, 0x4f420, | |
812034f1 HS |
1921 | 0x4f600, 0x4f618, |
1922 | 0x4f800, 0x4f814, | |
8119c018 HS |
1923 | 0x50000, 0x50084, |
1924 | 0x50090, 0x500cc, | |
812034f1 | 1925 | 0x50400, 0x50400, |
8119c018 HS |
1926 | 0x50800, 0x50884, |
1927 | 0x50890, 0x508cc, | |
812034f1 HS |
1928 | 0x50c00, 0x50c00, |
1929 | 0x51000, 0x5101c, | |
1930 | 0x51300, 0x51308, | |
1931 | }; | |
1932 | ||
ab4b583b | 1933 | static const unsigned int t6_reg_ranges[] = { |
8119c018 HS |
1934 | 0x1008, 0x101c, |
1935 | 0x1024, 0x10a8, | |
1936 | 0x10b4, 0x10f8, | |
1937 | 0x1100, 0x1114, | |
1938 | 0x111c, 0x112c, | |
1939 | 0x1138, 0x113c, | |
1940 | 0x1144, 0x114c, | |
1941 | 0x1180, 0x1184, | |
1942 | 0x1190, 0x1194, | |
1943 | 0x11a0, 0x11a4, | |
1944 | 0x11b0, 0x11b4, | |
676d6a75 HS |
1945 | 0x11fc, 0x1258, |
1946 | 0x1280, 0x12d4, | |
1947 | 0x12d9, 0x12d9, | |
1948 | 0x12de, 0x12de, | |
1949 | 0x12e3, 0x12e3, | |
1950 | 0x12e8, 0x133c, | |
ab4b583b HS |
1951 | 0x1800, 0x18fc, |
1952 | 0x3000, 0x302c, | |
8119c018 HS |
1953 | 0x3060, 0x30b0, |
1954 | 0x30b8, 0x30d8, | |
ab4b583b HS |
1955 | 0x30e0, 0x30fc, |
1956 | 0x3140, 0x357c, | |
1957 | 0x35a8, 0x35cc, | |
1958 | 0x35ec, 0x35ec, | |
1959 | 0x3600, 0x5624, | |
8119c018 HS |
1960 | 0x56cc, 0x56ec, |
1961 | 0x56f4, 0x5720, | |
1962 | 0x5728, 0x575c, | |
ab4b583b | 1963 | 0x580c, 0x5814, |
8119c018 HS |
1964 | 0x5890, 0x589c, |
1965 | 0x58a4, 0x58ac, | |
1966 | 0x58b8, 0x58bc, | |
ab4b583b HS |
1967 | 0x5940, 0x595c, |
1968 | 0x5980, 0x598c, | |
8119c018 HS |
1969 | 0x59b0, 0x59c8, |
1970 | 0x59d0, 0x59dc, | |
ab4b583b HS |
1971 | 0x59fc, 0x5a18, |
1972 | 0x5a60, 0x5a6c, | |
8119c018 HS |
1973 | 0x5a80, 0x5a8c, |
1974 | 0x5a94, 0x5a9c, | |
ab4b583b | 1975 | 0x5b94, 0x5bfc, |
8119c018 HS |
1976 | 0x5c10, 0x5e48, |
1977 | 0x5e50, 0x5e94, | |
1978 | 0x5ea0, 0x5eb0, | |
1979 | 0x5ec0, 0x5ec0, | |
676d6a75 | 1980 | 0x5ec8, 0x5ed0, |
8119c018 HS |
1981 | 0x6000, 0x6020, |
1982 | 0x6028, 0x6040, | |
1983 | 0x6058, 0x609c, | |
1984 | 0x60a8, 0x619c, | |
ab4b583b HS |
1985 | 0x7700, 0x7798, |
1986 | 0x77c0, 0x7880, | |
1987 | 0x78cc, 0x78fc, | |
8119c018 HS |
1988 | 0x7b00, 0x7b58, |
1989 | 0x7b60, 0x7b84, | |
1990 | 0x7b8c, 0x7c54, | |
1991 | 0x7d00, 0x7d38, | |
1992 | 0x7d40, 0x7d84, | |
1993 | 0x7d8c, 0x7ddc, | |
1994 | 0x7de4, 0x7e04, | |
1995 | 0x7e10, 0x7e1c, | |
1996 | 0x7e24, 0x7e38, | |
1997 | 0x7e40, 0x7e44, | |
1998 | 0x7e4c, 0x7e78, | |
1999 | 0x7e80, 0x7edc, | |
2000 | 0x7ee8, 0x7efc, | |
f109ff11 | 2001 | 0x8dc0, 0x8de4, |
8119c018 HS |
2002 | 0x8df8, 0x8e04, |
2003 | 0x8e10, 0x8e84, | |
ab4b583b | 2004 | 0x8ea0, 0x8f88, |
8119c018 HS |
2005 | 0x8fb8, 0x9058, |
2006 | 0x9060, 0x9060, | |
2007 | 0x9068, 0x90f8, | |
2008 | 0x9100, 0x9124, | |
ab4b583b | 2009 | 0x9400, 0x9470, |
8119c018 HS |
2010 | 0x9600, 0x9600, |
2011 | 0x9608, 0x9638, | |
2012 | 0x9640, 0x9704, | |
2013 | 0x9710, 0x971c, | |
ab4b583b HS |
2014 | 0x9800, 0x9808, |
2015 | 0x9820, 0x983c, | |
2016 | 0x9850, 0x9864, | |
2017 | 0x9c00, 0x9c6c, | |
2018 | 0x9c80, 0x9cec, | |
2019 | 0x9d00, 0x9d6c, | |
2020 | 0x9d80, 0x9dec, | |
2021 | 0x9e00, 0x9e6c, | |
2022 | 0x9e80, 0x9eec, | |
2023 | 0x9f00, 0x9f6c, | |
2024 | 0x9f80, 0xa020, | |
2025 | 0xd004, 0xd03c, | |
5b4e83e1 | 2026 | 0xd100, 0xd118, |
8119c018 HS |
2027 | 0xd200, 0xd214, |
2028 | 0xd220, 0xd234, | |
2029 | 0xd240, 0xd254, | |
2030 | 0xd260, 0xd274, | |
2031 | 0xd280, 0xd294, | |
2032 | 0xd2a0, 0xd2b4, | |
2033 | 0xd2c0, 0xd2d4, | |
2034 | 0xd2e0, 0xd2f4, | |
2035 | 0xd300, 0xd31c, | |
ab4b583b HS |
2036 | 0xdfc0, 0xdfe0, |
2037 | 0xe000, 0xf008, | |
2038 | 0x11000, 0x11014, | |
8119c018 HS |
2039 | 0x11048, 0x1106c, |
2040 | 0x11074, 0x11088, | |
2041 | 0x11098, 0x11120, | |
2042 | 0x1112c, 0x1117c, | |
2043 | 0x11190, 0x112e0, | |
ab4b583b | 2044 | 0x11300, 0x1130c, |
5b4e83e1 | 2045 | 0x12000, 0x1206c, |
ab4b583b HS |
2046 | 0x19040, 0x1906c, |
2047 | 0x19078, 0x19080, | |
8119c018 HS |
2048 | 0x1908c, 0x190e8, |
2049 | 0x190f0, 0x190f8, | |
2050 | 0x19100, 0x19110, | |
2051 | 0x19120, 0x19124, | |
2052 | 0x19150, 0x19194, | |
2053 | 0x1919c, 0x191b0, | |
ab4b583b | 2054 | 0x191d0, 0x191e8, |
676d6a75 HS |
2055 | 0x19238, 0x19290, |
2056 | 0x192a4, 0x192b0, | |
8119c018 HS |
2057 | 0x192bc, 0x192bc, |
2058 | 0x19348, 0x1934c, | |
2059 | 0x193f8, 0x19418, | |
2060 | 0x19420, 0x19428, | |
2061 | 0x19430, 0x19444, | |
2062 | 0x1944c, 0x1946c, | |
2063 | 0x19474, 0x19474, | |
ab4b583b HS |
2064 | 0x19490, 0x194cc, |
2065 | 0x194f0, 0x194f8, | |
8119c018 HS |
2066 | 0x19c00, 0x19c48, |
2067 | 0x19c50, 0x19c80, | |
2068 | 0x19c94, 0x19c98, | |
2069 | 0x19ca0, 0x19cbc, | |
2070 | 0x19ce4, 0x19ce4, | |
2071 | 0x19cf0, 0x19cf8, | |
2072 | 0x19d00, 0x19d28, | |
ab4b583b | 2073 | 0x19d50, 0x19d78, |
8119c018 HS |
2074 | 0x19d94, 0x19d98, |
2075 | 0x19da0, 0x19dc8, | |
ab4b583b HS |
2076 | 0x19df0, 0x19e10, |
2077 | 0x19e50, 0x19e6c, | |
8119c018 HS |
2078 | 0x19ea0, 0x19ebc, |
2079 | 0x19ec4, 0x19ef4, | |
2080 | 0x19f04, 0x19f2c, | |
2081 | 0x19f34, 0x19f34, | |
ab4b583b HS |
2082 | 0x19f40, 0x19f50, |
2083 | 0x19f90, 0x19fac, | |
8119c018 HS |
2084 | 0x19fc4, 0x19fc8, |
2085 | 0x19fd0, 0x19fe4, | |
2086 | 0x1a000, 0x1a004, | |
2087 | 0x1a010, 0x1a06c, | |
2088 | 0x1a0b0, 0x1a0e4, | |
2089 | 0x1a0ec, 0x1a0f8, | |
2090 | 0x1a100, 0x1a108, | |
2091 | 0x1a114, 0x1a120, | |
2092 | 0x1a128, 0x1a130, | |
2093 | 0x1a138, 0x1a138, | |
ab4b583b HS |
2094 | 0x1a190, 0x1a1c4, |
2095 | 0x1a1fc, 0x1a1fc, | |
2096 | 0x1e008, 0x1e00c, | |
8119c018 HS |
2097 | 0x1e040, 0x1e044, |
2098 | 0x1e04c, 0x1e04c, | |
ab4b583b HS |
2099 | 0x1e284, 0x1e290, |
2100 | 0x1e2c0, 0x1e2c0, | |
2101 | 0x1e2e0, 0x1e2e0, | |
2102 | 0x1e300, 0x1e384, | |
2103 | 0x1e3c0, 0x1e3c8, | |
2104 | 0x1e408, 0x1e40c, | |
8119c018 HS |
2105 | 0x1e440, 0x1e444, |
2106 | 0x1e44c, 0x1e44c, | |
ab4b583b HS |
2107 | 0x1e684, 0x1e690, |
2108 | 0x1e6c0, 0x1e6c0, | |
2109 | 0x1e6e0, 0x1e6e0, | |
2110 | 0x1e700, 0x1e784, | |
2111 | 0x1e7c0, 0x1e7c8, | |
2112 | 0x1e808, 0x1e80c, | |
8119c018 HS |
2113 | 0x1e840, 0x1e844, |
2114 | 0x1e84c, 0x1e84c, | |
ab4b583b HS |
2115 | 0x1ea84, 0x1ea90, |
2116 | 0x1eac0, 0x1eac0, | |
2117 | 0x1eae0, 0x1eae0, | |
2118 | 0x1eb00, 0x1eb84, | |
2119 | 0x1ebc0, 0x1ebc8, | |
2120 | 0x1ec08, 0x1ec0c, | |
8119c018 HS |
2121 | 0x1ec40, 0x1ec44, |
2122 | 0x1ec4c, 0x1ec4c, | |
ab4b583b HS |
2123 | 0x1ee84, 0x1ee90, |
2124 | 0x1eec0, 0x1eec0, | |
2125 | 0x1eee0, 0x1eee0, | |
2126 | 0x1ef00, 0x1ef84, | |
2127 | 0x1efc0, 0x1efc8, | |
2128 | 0x1f008, 0x1f00c, | |
8119c018 HS |
2129 | 0x1f040, 0x1f044, |
2130 | 0x1f04c, 0x1f04c, | |
ab4b583b HS |
2131 | 0x1f284, 0x1f290, |
2132 | 0x1f2c0, 0x1f2c0, | |
2133 | 0x1f2e0, 0x1f2e0, | |
2134 | 0x1f300, 0x1f384, | |
2135 | 0x1f3c0, 0x1f3c8, | |
2136 | 0x1f408, 0x1f40c, | |
8119c018 HS |
2137 | 0x1f440, 0x1f444, |
2138 | 0x1f44c, 0x1f44c, | |
ab4b583b HS |
2139 | 0x1f684, 0x1f690, |
2140 | 0x1f6c0, 0x1f6c0, | |
2141 | 0x1f6e0, 0x1f6e0, | |
2142 | 0x1f700, 0x1f784, | |
2143 | 0x1f7c0, 0x1f7c8, | |
2144 | 0x1f808, 0x1f80c, | |
8119c018 HS |
2145 | 0x1f840, 0x1f844, |
2146 | 0x1f84c, 0x1f84c, | |
ab4b583b HS |
2147 | 0x1fa84, 0x1fa90, |
2148 | 0x1fac0, 0x1fac0, | |
2149 | 0x1fae0, 0x1fae0, | |
2150 | 0x1fb00, 0x1fb84, | |
2151 | 0x1fbc0, 0x1fbc8, | |
2152 | 0x1fc08, 0x1fc0c, | |
8119c018 HS |
2153 | 0x1fc40, 0x1fc44, |
2154 | 0x1fc4c, 0x1fc4c, | |
ab4b583b HS |
2155 | 0x1fe84, 0x1fe90, |
2156 | 0x1fec0, 0x1fec0, | |
2157 | 0x1fee0, 0x1fee0, | |
2158 | 0x1ff00, 0x1ff84, | |
2159 | 0x1ffc0, 0x1ffc8, | |
8119c018 HS |
2160 | 0x30000, 0x30030, |
2161 | 0x30038, 0x30038, | |
2162 | 0x30040, 0x30040, | |
2163 | 0x30048, 0x30048, | |
2164 | 0x30050, 0x30050, | |
2165 | 0x3005c, 0x30060, | |
2166 | 0x30068, 0x30068, | |
2167 | 0x30070, 0x30070, | |
2168 | 0x30100, 0x30168, | |
2169 | 0x30190, 0x301a0, | |
2170 | 0x301a8, 0x301b8, | |
2171 | 0x301c4, 0x301c8, | |
2172 | 0x301d0, 0x301d0, | |
f109ff11 | 2173 | 0x30200, 0x30320, |
8119c018 HS |
2174 | 0x30400, 0x304b4, |
2175 | 0x304c0, 0x3052c, | |
ab4b583b | 2176 | 0x30540, 0x3061c, |
8119c018 | 2177 | 0x30800, 0x308a0, |
ab4b583b HS |
2178 | 0x308c0, 0x30908, |
2179 | 0x30910, 0x309b8, | |
2180 | 0x30a00, 0x30a04, | |
8119c018 HS |
2181 | 0x30a0c, 0x30a14, |
2182 | 0x30a1c, 0x30a2c, | |
ab4b583b | 2183 | 0x30a44, 0x30a50, |
8119c018 HS |
2184 | 0x30a74, 0x30a74, |
2185 | 0x30a7c, 0x30afc, | |
2186 | 0x30b08, 0x30c24, | |
2187 | 0x30d00, 0x30d14, | |
2188 | 0x30d1c, 0x30d3c, | |
2189 | 0x30d44, 0x30d4c, | |
2190 | 0x30d54, 0x30d74, | |
2191 | 0x30d7c, 0x30d7c, | |
ab4b583b HS |
2192 | 0x30de0, 0x30de0, |
2193 | 0x30e00, 0x30ed4, | |
2194 | 0x30f00, 0x30fa4, | |
2195 | 0x30fc0, 0x30fc4, | |
2196 | 0x31000, 0x31004, | |
2197 | 0x31080, 0x310fc, | |
2198 | 0x31208, 0x31220, | |
2199 | 0x3123c, 0x31254, | |
2200 | 0x31300, 0x31300, | |
2201 | 0x31308, 0x3131c, | |
2202 | 0x31338, 0x3133c, | |
2203 | 0x31380, 0x31380, | |
2204 | 0x31388, 0x313a8, | |
2205 | 0x313b4, 0x313b4, | |
2206 | 0x31400, 0x31420, | |
2207 | 0x31438, 0x3143c, | |
2208 | 0x31480, 0x31480, | |
2209 | 0x314a8, 0x314a8, | |
2210 | 0x314b0, 0x314b4, | |
2211 | 0x314c8, 0x314d4, | |
2212 | 0x31a40, 0x31a4c, | |
2213 | 0x31af0, 0x31b20, | |
2214 | 0x31b38, 0x31b3c, | |
2215 | 0x31b80, 0x31b80, | |
2216 | 0x31ba8, 0x31ba8, | |
2217 | 0x31bb0, 0x31bb4, | |
2218 | 0x31bc8, 0x31bd4, | |
2219 | 0x32140, 0x3218c, | |
8119c018 HS |
2220 | 0x321f0, 0x321f4, |
2221 | 0x32200, 0x32200, | |
ab4b583b HS |
2222 | 0x32218, 0x32218, |
2223 | 0x32400, 0x32400, | |
2224 | 0x32408, 0x3241c, | |
2225 | 0x32618, 0x32620, | |
2226 | 0x32664, 0x32664, | |
2227 | 0x326a8, 0x326a8, | |
2228 | 0x326ec, 0x326ec, | |
2229 | 0x32a00, 0x32abc, | |
8119c018 HS |
2230 | 0x32b00, 0x32b38, |
2231 | 0x32b40, 0x32b58, | |
2232 | 0x32b60, 0x32b78, | |
ab4b583b HS |
2233 | 0x32c00, 0x32c00, |
2234 | 0x32c08, 0x32c3c, | |
2235 | 0x32e00, 0x32e2c, | |
2236 | 0x32f00, 0x32f2c, | |
8119c018 HS |
2237 | 0x33000, 0x3302c, |
2238 | 0x33034, 0x33050, | |
2239 | 0x33058, 0x33058, | |
2240 | 0x33060, 0x3308c, | |
2241 | 0x3309c, 0x330ac, | |
2242 | 0x330c0, 0x330c0, | |
2243 | 0x330c8, 0x330d0, | |
2244 | 0x330d8, 0x330e0, | |
2245 | 0x330ec, 0x3312c, | |
2246 | 0x33134, 0x33150, | |
2247 | 0x33158, 0x33158, | |
2248 | 0x33160, 0x3318c, | |
2249 | 0x3319c, 0x331ac, | |
2250 | 0x331c0, 0x331c0, | |
2251 | 0x331c8, 0x331d0, | |
2252 | 0x331d8, 0x331e0, | |
2253 | 0x331ec, 0x33290, | |
2254 | 0x33298, 0x332c4, | |
2255 | 0x332e4, 0x33390, | |
2256 | 0x33398, 0x333c4, | |
2257 | 0x333e4, 0x3342c, | |
2258 | 0x33434, 0x33450, | |
2259 | 0x33458, 0x33458, | |
2260 | 0x33460, 0x3348c, | |
2261 | 0x3349c, 0x334ac, | |
2262 | 0x334c0, 0x334c0, | |
2263 | 0x334c8, 0x334d0, | |
2264 | 0x334d8, 0x334e0, | |
2265 | 0x334ec, 0x3352c, | |
2266 | 0x33534, 0x33550, | |
2267 | 0x33558, 0x33558, | |
2268 | 0x33560, 0x3358c, | |
2269 | 0x3359c, 0x335ac, | |
2270 | 0x335c0, 0x335c0, | |
2271 | 0x335c8, 0x335d0, | |
2272 | 0x335d8, 0x335e0, | |
2273 | 0x335ec, 0x33690, | |
2274 | 0x33698, 0x336c4, | |
2275 | 0x336e4, 0x33790, | |
2276 | 0x33798, 0x337c4, | |
ab4b583b HS |
2277 | 0x337e4, 0x337fc, |
2278 | 0x33814, 0x33814, | |
2279 | 0x33854, 0x33868, | |
2280 | 0x33880, 0x3388c, | |
2281 | 0x338c0, 0x338d0, | |
2282 | 0x338e8, 0x338ec, | |
8119c018 HS |
2283 | 0x33900, 0x3392c, |
2284 | 0x33934, 0x33950, | |
2285 | 0x33958, 0x33958, | |
2286 | 0x33960, 0x3398c, | |
2287 | 0x3399c, 0x339ac, | |
2288 | 0x339c0, 0x339c0, | |
2289 | 0x339c8, 0x339d0, | |
2290 | 0x339d8, 0x339e0, | |
2291 | 0x339ec, 0x33a90, | |
2292 | 0x33a98, 0x33ac4, | |
ab4b583b | 2293 | 0x33ae4, 0x33b10, |
8119c018 HS |
2294 | 0x33b24, 0x33b28, |
2295 | 0x33b38, 0x33b50, | |
ab4b583b | 2296 | 0x33bf0, 0x33c10, |
8119c018 HS |
2297 | 0x33c24, 0x33c28, |
2298 | 0x33c38, 0x33c50, | |
ab4b583b | 2299 | 0x33cf0, 0x33cfc, |
8119c018 HS |
2300 | 0x34000, 0x34030, |
2301 | 0x34038, 0x34038, | |
2302 | 0x34040, 0x34040, | |
2303 | 0x34048, 0x34048, | |
2304 | 0x34050, 0x34050, | |
2305 | 0x3405c, 0x34060, | |
2306 | 0x34068, 0x34068, | |
2307 | 0x34070, 0x34070, | |
2308 | 0x34100, 0x34168, | |
2309 | 0x34190, 0x341a0, | |
2310 | 0x341a8, 0x341b8, | |
2311 | 0x341c4, 0x341c8, | |
2312 | 0x341d0, 0x341d0, | |
f109ff11 | 2313 | 0x34200, 0x34320, |
8119c018 HS |
2314 | 0x34400, 0x344b4, |
2315 | 0x344c0, 0x3452c, | |
ab4b583b | 2316 | 0x34540, 0x3461c, |
8119c018 | 2317 | 0x34800, 0x348a0, |
ab4b583b HS |
2318 | 0x348c0, 0x34908, |
2319 | 0x34910, 0x349b8, | |
2320 | 0x34a00, 0x34a04, | |
8119c018 HS |
2321 | 0x34a0c, 0x34a14, |
2322 | 0x34a1c, 0x34a2c, | |
ab4b583b | 2323 | 0x34a44, 0x34a50, |
8119c018 HS |
2324 | 0x34a74, 0x34a74, |
2325 | 0x34a7c, 0x34afc, | |
2326 | 0x34b08, 0x34c24, | |
2327 | 0x34d00, 0x34d14, | |
2328 | 0x34d1c, 0x34d3c, | |
2329 | 0x34d44, 0x34d4c, | |
2330 | 0x34d54, 0x34d74, | |
2331 | 0x34d7c, 0x34d7c, | |
ab4b583b HS |
2332 | 0x34de0, 0x34de0, |
2333 | 0x34e00, 0x34ed4, | |
2334 | 0x34f00, 0x34fa4, | |
2335 | 0x34fc0, 0x34fc4, | |
2336 | 0x35000, 0x35004, | |
2337 | 0x35080, 0x350fc, | |
2338 | 0x35208, 0x35220, | |
2339 | 0x3523c, 0x35254, | |
2340 | 0x35300, 0x35300, | |
2341 | 0x35308, 0x3531c, | |
2342 | 0x35338, 0x3533c, | |
2343 | 0x35380, 0x35380, | |
2344 | 0x35388, 0x353a8, | |
2345 | 0x353b4, 0x353b4, | |
2346 | 0x35400, 0x35420, | |
2347 | 0x35438, 0x3543c, | |
2348 | 0x35480, 0x35480, | |
2349 | 0x354a8, 0x354a8, | |
2350 | 0x354b0, 0x354b4, | |
2351 | 0x354c8, 0x354d4, | |
2352 | 0x35a40, 0x35a4c, | |
2353 | 0x35af0, 0x35b20, | |
2354 | 0x35b38, 0x35b3c, | |
2355 | 0x35b80, 0x35b80, | |
2356 | 0x35ba8, 0x35ba8, | |
2357 | 0x35bb0, 0x35bb4, | |
2358 | 0x35bc8, 0x35bd4, | |
2359 | 0x36140, 0x3618c, | |
8119c018 HS |
2360 | 0x361f0, 0x361f4, |
2361 | 0x36200, 0x36200, | |
ab4b583b HS |
2362 | 0x36218, 0x36218, |
2363 | 0x36400, 0x36400, | |
2364 | 0x36408, 0x3641c, | |
2365 | 0x36618, 0x36620, | |
2366 | 0x36664, 0x36664, | |
2367 | 0x366a8, 0x366a8, | |
2368 | 0x366ec, 0x366ec, | |
2369 | 0x36a00, 0x36abc, | |
8119c018 HS |
2370 | 0x36b00, 0x36b38, |
2371 | 0x36b40, 0x36b58, | |
2372 | 0x36b60, 0x36b78, | |
ab4b583b HS |
2373 | 0x36c00, 0x36c00, |
2374 | 0x36c08, 0x36c3c, | |
2375 | 0x36e00, 0x36e2c, | |
2376 | 0x36f00, 0x36f2c, | |
8119c018 HS |
2377 | 0x37000, 0x3702c, |
2378 | 0x37034, 0x37050, | |
2379 | 0x37058, 0x37058, | |
2380 | 0x37060, 0x3708c, | |
2381 | 0x3709c, 0x370ac, | |
2382 | 0x370c0, 0x370c0, | |
2383 | 0x370c8, 0x370d0, | |
2384 | 0x370d8, 0x370e0, | |
2385 | 0x370ec, 0x3712c, | |
2386 | 0x37134, 0x37150, | |
2387 | 0x37158, 0x37158, | |
2388 | 0x37160, 0x3718c, | |
2389 | 0x3719c, 0x371ac, | |
2390 | 0x371c0, 0x371c0, | |
2391 | 0x371c8, 0x371d0, | |
2392 | 0x371d8, 0x371e0, | |
2393 | 0x371ec, 0x37290, | |
2394 | 0x37298, 0x372c4, | |
2395 | 0x372e4, 0x37390, | |
2396 | 0x37398, 0x373c4, | |
2397 | 0x373e4, 0x3742c, | |
2398 | 0x37434, 0x37450, | |
2399 | 0x37458, 0x37458, | |
2400 | 0x37460, 0x3748c, | |
2401 | 0x3749c, 0x374ac, | |
2402 | 0x374c0, 0x374c0, | |
2403 | 0x374c8, 0x374d0, | |
2404 | 0x374d8, 0x374e0, | |
2405 | 0x374ec, 0x3752c, | |
2406 | 0x37534, 0x37550, | |
2407 | 0x37558, 0x37558, | |
2408 | 0x37560, 0x3758c, | |
2409 | 0x3759c, 0x375ac, | |
2410 | 0x375c0, 0x375c0, | |
2411 | 0x375c8, 0x375d0, | |
2412 | 0x375d8, 0x375e0, | |
2413 | 0x375ec, 0x37690, | |
2414 | 0x37698, 0x376c4, | |
2415 | 0x376e4, 0x37790, | |
2416 | 0x37798, 0x377c4, | |
ab4b583b HS |
2417 | 0x377e4, 0x377fc, |
2418 | 0x37814, 0x37814, | |
2419 | 0x37854, 0x37868, | |
2420 | 0x37880, 0x3788c, | |
2421 | 0x378c0, 0x378d0, | |
2422 | 0x378e8, 0x378ec, | |
8119c018 HS |
2423 | 0x37900, 0x3792c, |
2424 | 0x37934, 0x37950, | |
2425 | 0x37958, 0x37958, | |
2426 | 0x37960, 0x3798c, | |
2427 | 0x3799c, 0x379ac, | |
2428 | 0x379c0, 0x379c0, | |
2429 | 0x379c8, 0x379d0, | |
2430 | 0x379d8, 0x379e0, | |
2431 | 0x379ec, 0x37a90, | |
2432 | 0x37a98, 0x37ac4, | |
ab4b583b | 2433 | 0x37ae4, 0x37b10, |
8119c018 HS |
2434 | 0x37b24, 0x37b28, |
2435 | 0x37b38, 0x37b50, | |
ab4b583b | 2436 | 0x37bf0, 0x37c10, |
8119c018 HS |
2437 | 0x37c24, 0x37c28, |
2438 | 0x37c38, 0x37c50, | |
ab4b583b HS |
2439 | 0x37cf0, 0x37cfc, |
2440 | 0x40040, 0x40040, | |
2441 | 0x40080, 0x40084, | |
2442 | 0x40100, 0x40100, | |
2443 | 0x40140, 0x401bc, | |
2444 | 0x40200, 0x40214, | |
2445 | 0x40228, 0x40228, | |
2446 | 0x40240, 0x40258, | |
2447 | 0x40280, 0x40280, | |
2448 | 0x40304, 0x40304, | |
2449 | 0x40330, 0x4033c, | |
676d6a75 HS |
2450 | 0x41304, 0x413b8, |
2451 | 0x413c0, 0x413c8, | |
8119c018 HS |
2452 | 0x413d0, 0x413dc, |
2453 | 0x413f0, 0x413f0, | |
2454 | 0x41400, 0x4140c, | |
2455 | 0x41414, 0x4141c, | |
ab4b583b HS |
2456 | 0x41480, 0x414d0, |
2457 | 0x44000, 0x4407c, | |
8119c018 HS |
2458 | 0x440c0, 0x441ac, |
2459 | 0x441b4, 0x4427c, | |
2460 | 0x442c0, 0x443ac, | |
2461 | 0x443b4, 0x4447c, | |
2462 | 0x444c0, 0x445ac, | |
2463 | 0x445b4, 0x4467c, | |
2464 | 0x446c0, 0x447ac, | |
2465 | 0x447b4, 0x4487c, | |
2466 | 0x448c0, 0x449ac, | |
2467 | 0x449b4, 0x44a7c, | |
2468 | 0x44ac0, 0x44bac, | |
2469 | 0x44bb4, 0x44c7c, | |
2470 | 0x44cc0, 0x44dac, | |
2471 | 0x44db4, 0x44e7c, | |
2472 | 0x44ec0, 0x44fac, | |
2473 | 0x44fb4, 0x4507c, | |
2474 | 0x450c0, 0x451ac, | |
2475 | 0x451b4, 0x451fc, | |
2476 | 0x45800, 0x45804, | |
2477 | 0x45810, 0x45830, | |
2478 | 0x45840, 0x45860, | |
2479 | 0x45868, 0x45868, | |
ab4b583b HS |
2480 | 0x45880, 0x45884, |
2481 | 0x458a0, 0x458b0, | |
8119c018 HS |
2482 | 0x45a00, 0x45a04, |
2483 | 0x45a10, 0x45a30, | |
2484 | 0x45a40, 0x45a60, | |
2485 | 0x45a68, 0x45a68, | |
ab4b583b HS |
2486 | 0x45a80, 0x45a84, |
2487 | 0x45aa0, 0x45ab0, | |
2488 | 0x460c0, 0x460e4, | |
8119c018 HS |
2489 | 0x47000, 0x4703c, |
2490 | 0x47044, 0x4708c, | |
ab4b583b | 2491 | 0x47200, 0x47250, |
8119c018 HS |
2492 | 0x47400, 0x47408, |
2493 | 0x47414, 0x47420, | |
ab4b583b | 2494 | 0x47600, 0x47618, |
8119c018 HS |
2495 | 0x47800, 0x47814, |
2496 | 0x47820, 0x4782c, | |
2497 | 0x50000, 0x50084, | |
2498 | 0x50090, 0x500cc, | |
2499 | 0x50300, 0x50384, | |
ab4b583b | 2500 | 0x50400, 0x50400, |
8119c018 HS |
2501 | 0x50800, 0x50884, |
2502 | 0x50890, 0x508cc, | |
2503 | 0x50b00, 0x50b84, | |
ab4b583b | 2504 | 0x50c00, 0x50c00, |
8119c018 HS |
2505 | 0x51000, 0x51020, |
2506 | 0x51028, 0x510b0, | |
ab4b583b HS |
2507 | 0x51300, 0x51324, |
2508 | }; | |
2509 | ||
812034f1 HS |
2510 | u32 *buf_end = (u32 *)((char *)buf + buf_size); |
2511 | const unsigned int *reg_ranges; | |
2512 | int reg_ranges_size, range; | |
2513 | unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); | |
2514 | ||
2515 | /* Select the right set of register ranges to dump depending on the | |
2516 | * adapter chip type. | |
2517 | */ | |
2518 | switch (chip_version) { | |
2519 | case CHELSIO_T4: | |
2520 | reg_ranges = t4_reg_ranges; | |
2521 | reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); | |
2522 | break; | |
2523 | ||
2524 | case CHELSIO_T5: | |
2525 | reg_ranges = t5_reg_ranges; | |
2526 | reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); | |
2527 | break; | |
2528 | ||
ab4b583b HS |
2529 | case CHELSIO_T6: |
2530 | reg_ranges = t6_reg_ranges; | |
2531 | reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); | |
2532 | break; | |
2533 | ||
812034f1 HS |
2534 | default: |
2535 | dev_err(adap->pdev_dev, | |
2536 | "Unsupported chip version %d\n", chip_version); | |
2537 | return; | |
2538 | } | |
2539 | ||
2540 | /* Clear the register buffer and insert the appropriate register | |
2541 | * values selected by the above register ranges. | |
2542 | */ | |
2543 | memset(buf, 0, buf_size); | |
2544 | for (range = 0; range < reg_ranges_size; range += 2) { | |
2545 | unsigned int reg = reg_ranges[range]; | |
2546 | unsigned int last_reg = reg_ranges[range + 1]; | |
2547 | u32 *bufp = (u32 *)((char *)buf + reg); | |
2548 | ||
2549 | /* Iterate across the register range filling in the register | |
2550 | * buffer but don't write past the end of the register buffer. | |
2551 | */ | |
2552 | while (reg <= last_reg && bufp < buf_end) { | |
2553 | *bufp++ = t4_read_reg(adap, reg); | |
2554 | reg += sizeof(u32); | |
2555 | } | |
2556 | } | |
2557 | } | |
2558 | ||
56d36be4 | 2559 | #define EEPROM_STAT_ADDR 0x7bfc |
47ce9c48 SR |
2560 | #define VPD_BASE 0x400 |
2561 | #define VPD_BASE_OLD 0 | |
0a57a536 | 2562 | #define VPD_LEN 1024 |
63a92fe6 | 2563 | #define CHELSIO_VPD_UNIQUE_ID 0x82 |
56d36be4 DM |
2564 | |
2565 | /** | |
2566 | * t4_seeprom_wp - enable/disable EEPROM write protection | |
2567 | * @adapter: the adapter | |
2568 | * @enable: whether to enable or disable write protection | |
2569 | * | |
2570 | * Enables or disables write protection on the serial EEPROM. | |
2571 | */ | |
2572 | int t4_seeprom_wp(struct adapter *adapter, bool enable) | |
2573 | { | |
2574 | unsigned int v = enable ? 0xc : 0; | |
2575 | int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); | |
2576 | return ret < 0 ? ret : 0; | |
2577 | } | |
2578 | ||
2579 | /** | |
098ef6c2 | 2580 | * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM |
56d36be4 DM |
2581 | * @adapter: adapter to read |
2582 | * @p: where to store the parameters | |
2583 | * | |
2584 | * Reads card parameters stored in VPD EEPROM. | |
2585 | */ | |
098ef6c2 | 2586 | int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p) |
56d36be4 | 2587 | { |
098ef6c2 HS |
2588 | int i, ret = 0, addr; |
2589 | int ec, sn, pn, na; | |
8c357ebd | 2590 | u8 *vpd, csum; |
23d88e1d | 2591 | unsigned int vpdr_len, kw_offset, id_len; |
56d36be4 | 2592 | |
8c357ebd VP |
2593 | vpd = vmalloc(VPD_LEN); |
2594 | if (!vpd) | |
2595 | return -ENOMEM; | |
2596 | ||
098ef6c2 HS |
2597 | /* Card information normally starts at VPD_BASE but early cards had |
2598 | * it at 0. | |
2599 | */ | |
47ce9c48 SR |
2600 | ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd); |
2601 | if (ret < 0) | |
2602 | goto out; | |
63a92fe6 HS |
2603 | |
2604 | /* The VPD shall have a unique identifier specified by the PCI SIG. | |
2605 | * For chelsio adapters, the identifier is 0x82. The first byte of a VPD | |
2606 | * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software | |
2607 | * is expected to automatically put this entry at the | |
2608 | * beginning of the VPD. | |
2609 | */ | |
2610 | addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; | |
47ce9c48 SR |
2611 | |
2612 | ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); | |
56d36be4 | 2613 | if (ret < 0) |
8c357ebd | 2614 | goto out; |
56d36be4 | 2615 | |
23d88e1d DM |
2616 | if (vpd[0] != PCI_VPD_LRDT_ID_STRING) { |
2617 | dev_err(adapter->pdev_dev, "missing VPD ID string\n"); | |
8c357ebd VP |
2618 | ret = -EINVAL; |
2619 | goto out; | |
23d88e1d DM |
2620 | } |
2621 | ||
2622 | id_len = pci_vpd_lrdt_size(vpd); | |
2623 | if (id_len > ID_LEN) | |
2624 | id_len = ID_LEN; | |
2625 | ||
2626 | i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA); | |
2627 | if (i < 0) { | |
2628 | dev_err(adapter->pdev_dev, "missing VPD-R section\n"); | |
8c357ebd VP |
2629 | ret = -EINVAL; |
2630 | goto out; | |
23d88e1d DM |
2631 | } |
2632 | ||
2633 | vpdr_len = pci_vpd_lrdt_size(&vpd[i]); | |
2634 | kw_offset = i + PCI_VPD_LRDT_TAG_SIZE; | |
2635 | if (vpdr_len + kw_offset > VPD_LEN) { | |
226ec5fd | 2636 | dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); |
8c357ebd VP |
2637 | ret = -EINVAL; |
2638 | goto out; | |
226ec5fd DM |
2639 | } |
2640 | ||
2641 | #define FIND_VPD_KW(var, name) do { \ | |
23d88e1d | 2642 | var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \ |
226ec5fd DM |
2643 | if (var < 0) { \ |
2644 | dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ | |
8c357ebd VP |
2645 | ret = -EINVAL; \ |
2646 | goto out; \ | |
226ec5fd DM |
2647 | } \ |
2648 | var += PCI_VPD_INFO_FLD_HDR_SIZE; \ | |
2649 | } while (0) | |
2650 | ||
2651 | FIND_VPD_KW(i, "RV"); | |
2652 | for (csum = 0; i >= 0; i--) | |
2653 | csum += vpd[i]; | |
56d36be4 DM |
2654 | |
2655 | if (csum) { | |
2656 | dev_err(adapter->pdev_dev, | |
2657 | "corrupted VPD EEPROM, actual csum %u\n", csum); | |
8c357ebd VP |
2658 | ret = -EINVAL; |
2659 | goto out; | |
56d36be4 DM |
2660 | } |
2661 | ||
226ec5fd DM |
2662 | FIND_VPD_KW(ec, "EC"); |
2663 | FIND_VPD_KW(sn, "SN"); | |
a94cd705 | 2664 | FIND_VPD_KW(pn, "PN"); |
098ef6c2 | 2665 | FIND_VPD_KW(na, "NA"); |
226ec5fd DM |
2666 | #undef FIND_VPD_KW |
2667 | ||
23d88e1d | 2668 | memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); |
56d36be4 | 2669 | strim(p->id); |
226ec5fd | 2670 | memcpy(p->ec, vpd + ec, EC_LEN); |
56d36be4 | 2671 | strim(p->ec); |
226ec5fd DM |
2672 | i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); |
2673 | memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); | |
56d36be4 | 2674 | strim(p->sn); |
63a92fe6 | 2675 | i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE); |
a94cd705 KS |
2676 | memcpy(p->pn, vpd + pn, min(i, PN_LEN)); |
2677 | strim(p->pn); | |
098ef6c2 HS |
2678 | memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); |
2679 | strim((char *)p->na); | |
636f9d37 | 2680 | |
098ef6c2 HS |
2681 | out: |
2682 | vfree(vpd); | |
2683 | return ret; | |
2684 | } | |
2685 | ||
2686 | /** | |
2687 | * t4_get_vpd_params - read VPD parameters & retrieve Core Clock | |
2688 | * @adapter: adapter to read | |
2689 | * @p: where to store the parameters | |
2690 | * | |
2691 | * Reads card parameters stored in VPD EEPROM and retrieves the Core | |
2692 | * Clock. This can only be called after a connection to the firmware | |
2693 | * is established. | |
2694 | */ | |
2695 | int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p) | |
2696 | { | |
2697 | u32 cclk_param, cclk_val; | |
2698 | int ret; | |
2699 | ||
2700 | /* Grab the raw VPD parameters. | |
2701 | */ | |
2702 | ret = t4_get_raw_vpd_params(adapter, p); | |
2703 | if (ret) | |
2704 | return ret; | |
2705 | ||
2706 | /* Ask firmware for the Core Clock since it knows how to translate the | |
636f9d37 VP |
2707 | * Reference Clock ('V2') VPD field into a Core Clock value ... |
2708 | */ | |
5167865a HS |
2709 | cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
2710 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK)); | |
098ef6c2 | 2711 | ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, |
636f9d37 | 2712 | 1, &cclk_param, &cclk_val); |
8c357ebd | 2713 | |
636f9d37 VP |
2714 | if (ret) |
2715 | return ret; | |
2716 | p->cclk = cclk_val; | |
2717 | ||
56d36be4 DM |
2718 | return 0; |
2719 | } | |
2720 | ||
2721 | /* serial flash and firmware constants */ | |
2722 | enum { | |
2723 | SF_ATTEMPTS = 10, /* max retries for SF operations */ | |
2724 | ||
2725 | /* flash command opcodes */ | |
2726 | SF_PROG_PAGE = 2, /* program page */ | |
2727 | SF_WR_DISABLE = 4, /* disable writes */ | |
2728 | SF_RD_STATUS = 5, /* read status register */ | |
2729 | SF_WR_ENABLE = 6, /* enable writes */ | |
2730 | SF_RD_DATA_FAST = 0xb, /* read flash */ | |
900a6596 | 2731 | SF_RD_ID = 0x9f, /* read ID */ |
56d36be4 DM |
2732 | SF_ERASE_SECTOR = 0xd8, /* erase sector */ |
2733 | ||
6f1d7210 | 2734 | FW_MAX_SIZE = 16 * SF_SEC_SIZE, |
56d36be4 DM |
2735 | }; |
2736 | ||
2737 | /** | |
2738 | * sf1_read - read data from the serial flash | |
2739 | * @adapter: the adapter | |
2740 | * @byte_cnt: number of bytes to read | |
2741 | * @cont: whether another operation will be chained | |
2742 | * @lock: whether to lock SF for PL access only | |
2743 | * @valp: where to store the read data | |
2744 | * | |
2745 | * Reads up to 4 bytes of data from the serial flash. The location of | |
2746 | * the read needs to be specified prior to calling this by issuing the | |
2747 | * appropriate commands to the serial flash. | |
2748 | */ | |
2749 | static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
2750 | int lock, u32 *valp) | |
2751 | { | |
2752 | int ret; | |
2753 | ||
2754 | if (!byte_cnt || byte_cnt > 4) | |
2755 | return -EINVAL; | |
0d804338 | 2756 | if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) |
56d36be4 | 2757 | return -EBUSY; |
0d804338 HS |
2758 | t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | |
2759 | SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); | |
2760 | ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); | |
56d36be4 | 2761 | if (!ret) |
0d804338 | 2762 | *valp = t4_read_reg(adapter, SF_DATA_A); |
56d36be4 DM |
2763 | return ret; |
2764 | } | |
2765 | ||
2766 | /** | |
2767 | * sf1_write - write data to the serial flash | |
2768 | * @adapter: the adapter | |
2769 | * @byte_cnt: number of bytes to write | |
2770 | * @cont: whether another operation will be chained | |
2771 | * @lock: whether to lock SF for PL access only | |
2772 | * @val: value to write | |
2773 | * | |
2774 | * Writes up to 4 bytes of data to the serial flash. The location of | |
2775 | * the write needs to be specified prior to calling this by issuing the | |
2776 | * appropriate commands to the serial flash. | |
2777 | */ | |
2778 | static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
2779 | int lock, u32 val) | |
2780 | { | |
2781 | if (!byte_cnt || byte_cnt > 4) | |
2782 | return -EINVAL; | |
0d804338 | 2783 | if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) |
56d36be4 | 2784 | return -EBUSY; |
0d804338 HS |
2785 | t4_write_reg(adapter, SF_DATA_A, val); |
2786 | t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | | |
2787 | SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); | |
2788 | return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); | |
56d36be4 DM |
2789 | } |
2790 | ||
2791 | /** | |
2792 | * flash_wait_op - wait for a flash operation to complete | |
2793 | * @adapter: the adapter | |
2794 | * @attempts: max number of polls of the status register | |
2795 | * @delay: delay between polls in ms | |
2796 | * | |
2797 | * Wait for a flash operation to complete by polling the status register. | |
2798 | */ | |
2799 | static int flash_wait_op(struct adapter *adapter, int attempts, int delay) | |
2800 | { | |
2801 | int ret; | |
2802 | u32 status; | |
2803 | ||
2804 | while (1) { | |
2805 | if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || | |
2806 | (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) | |
2807 | return ret; | |
2808 | if (!(status & 1)) | |
2809 | return 0; | |
2810 | if (--attempts == 0) | |
2811 | return -EAGAIN; | |
2812 | if (delay) | |
2813 | msleep(delay); | |
2814 | } | |
2815 | } | |
2816 | ||
2817 | /** | |
2818 | * t4_read_flash - read words from serial flash | |
2819 | * @adapter: the adapter | |
2820 | * @addr: the start address for the read | |
2821 | * @nwords: how many 32-bit words to read | |
2822 | * @data: where to store the read data | |
2823 | * @byte_oriented: whether to store data as bytes or as words | |
2824 | * | |
2825 | * Read the specified number of 32-bit words from the serial flash. | |
2826 | * If @byte_oriented is set the read data is stored as a byte array | |
2827 | * (i.e., big-endian), otherwise as 32-bit words in the platform's | |
dbedd44e | 2828 | * natural endianness. |
56d36be4 | 2829 | */ |
49216c1c HS |
2830 | int t4_read_flash(struct adapter *adapter, unsigned int addr, |
2831 | unsigned int nwords, u32 *data, int byte_oriented) | |
56d36be4 DM |
2832 | { |
2833 | int ret; | |
2834 | ||
900a6596 | 2835 | if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) |
56d36be4 DM |
2836 | return -EINVAL; |
2837 | ||
2838 | addr = swab32(addr) | SF_RD_DATA_FAST; | |
2839 | ||
2840 | if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || | |
2841 | (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) | |
2842 | return ret; | |
2843 | ||
2844 | for ( ; nwords; nwords--, data++) { | |
2845 | ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); | |
2846 | if (nwords == 1) | |
0d804338 | 2847 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
2848 | if (ret) |
2849 | return ret; | |
2850 | if (byte_oriented) | |
f404f80c | 2851 | *data = (__force __u32)(cpu_to_be32(*data)); |
56d36be4 DM |
2852 | } |
2853 | return 0; | |
2854 | } | |
2855 | ||
2856 | /** | |
2857 | * t4_write_flash - write up to a page of data to the serial flash | |
2858 | * @adapter: the adapter | |
2859 | * @addr: the start address to write | |
2860 | * @n: length of data to write in bytes | |
2861 | * @data: the data to write | |
2862 | * | |
2863 | * Writes up to a page of data (256 bytes) to the serial flash starting | |
2864 | * at the given address. All the data must be written to the same page. | |
2865 | */ | |
2866 | static int t4_write_flash(struct adapter *adapter, unsigned int addr, | |
2867 | unsigned int n, const u8 *data) | |
2868 | { | |
2869 | int ret; | |
2870 | u32 buf[64]; | |
2871 | unsigned int i, c, left, val, offset = addr & 0xff; | |
2872 | ||
900a6596 | 2873 | if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) |
56d36be4 DM |
2874 | return -EINVAL; |
2875 | ||
2876 | val = swab32(addr) | SF_PROG_PAGE; | |
2877 | ||
2878 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
2879 | (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) | |
2880 | goto unlock; | |
2881 | ||
2882 | for (left = n; left; left -= c) { | |
2883 | c = min(left, 4U); | |
2884 | for (val = 0, i = 0; i < c; ++i) | |
2885 | val = (val << 8) + *data++; | |
2886 | ||
2887 | ret = sf1_write(adapter, c, c != left, 1, val); | |
2888 | if (ret) | |
2889 | goto unlock; | |
2890 | } | |
900a6596 | 2891 | ret = flash_wait_op(adapter, 8, 1); |
56d36be4 DM |
2892 | if (ret) |
2893 | goto unlock; | |
2894 | ||
0d804338 | 2895 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
2896 | |
2897 | /* Read the page to verify the write succeeded */ | |
2898 | ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); | |
2899 | if (ret) | |
2900 | return ret; | |
2901 | ||
2902 | if (memcmp(data - n, (u8 *)buf + offset, n)) { | |
2903 | dev_err(adapter->pdev_dev, | |
2904 | "failed to correctly write the flash page at %#x\n", | |
2905 | addr); | |
2906 | return -EIO; | |
2907 | } | |
2908 | return 0; | |
2909 | ||
2910 | unlock: | |
0d804338 | 2911 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
2912 | return ret; |
2913 | } | |
2914 | ||
2915 | /** | |
16e47624 | 2916 | * t4_get_fw_version - read the firmware version |
56d36be4 DM |
2917 | * @adapter: the adapter |
2918 | * @vers: where to place the version | |
2919 | * | |
2920 | * Reads the FW version from flash. | |
2921 | */ | |
16e47624 | 2922 | int t4_get_fw_version(struct adapter *adapter, u32 *vers) |
56d36be4 | 2923 | { |
16e47624 HS |
2924 | return t4_read_flash(adapter, FLASH_FW_START + |
2925 | offsetof(struct fw_hdr, fw_ver), 1, | |
2926 | vers, 0); | |
56d36be4 DM |
2927 | } |
2928 | ||
2929 | /** | |
16e47624 | 2930 | * t4_get_tp_version - read the TP microcode version |
56d36be4 DM |
2931 | * @adapter: the adapter |
2932 | * @vers: where to place the version | |
2933 | * | |
2934 | * Reads the TP microcode version from flash. | |
2935 | */ | |
16e47624 | 2936 | int t4_get_tp_version(struct adapter *adapter, u32 *vers) |
56d36be4 | 2937 | { |
16e47624 | 2938 | return t4_read_flash(adapter, FLASH_FW_START + |
900a6596 | 2939 | offsetof(struct fw_hdr, tp_microcode_ver), |
56d36be4 DM |
2940 | 1, vers, 0); |
2941 | } | |
2942 | ||
ba3f8cd5 HS |
2943 | /** |
2944 | * t4_get_exprom_version - return the Expansion ROM version (if any) | |
2945 | * @adapter: the adapter | |
2946 | * @vers: where to place the version | |
2947 | * | |
2948 | * Reads the Expansion ROM header from FLASH and returns the version | |
2949 | * number (if present) through the @vers return value pointer. We return | |
2950 | * this in the Firmware Version Format since it's convenient. Return | |
2951 | * 0 on success, -ENOENT if no Expansion ROM is present. | |
2952 | */ | |
2953 | int t4_get_exprom_version(struct adapter *adap, u32 *vers) | |
2954 | { | |
2955 | struct exprom_header { | |
2956 | unsigned char hdr_arr[16]; /* must start with 0x55aa */ | |
2957 | unsigned char hdr_ver[4]; /* Expansion ROM version */ | |
2958 | } *hdr; | |
2959 | u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), | |
2960 | sizeof(u32))]; | |
2961 | int ret; | |
2962 | ||
2963 | ret = t4_read_flash(adap, FLASH_EXP_ROM_START, | |
2964 | ARRAY_SIZE(exprom_header_buf), exprom_header_buf, | |
2965 | 0); | |
2966 | if (ret) | |
2967 | return ret; | |
2968 | ||
2969 | hdr = (struct exprom_header *)exprom_header_buf; | |
2970 | if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) | |
2971 | return -ENOENT; | |
2972 | ||
2973 | *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) | | |
2974 | FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) | | |
2975 | FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) | | |
2976 | FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3])); | |
2977 | return 0; | |
2978 | } | |
2979 | ||
a69265e9 HS |
2980 | /** |
2981 | * t4_check_fw_version - check if the FW is supported with this driver | |
2982 | * @adap: the adapter | |
2983 | * | |
2984 | * Checks if an adapter's FW is compatible with the driver. Returns 0 | |
2985 | * if there's exact match, a negative error if the version could not be | |
2986 | * read or there's a major version mismatch | |
2987 | */ | |
2988 | int t4_check_fw_version(struct adapter *adap) | |
2989 | { | |
21d11bd6 | 2990 | int i, ret, major, minor, micro; |
a69265e9 HS |
2991 | int exp_major, exp_minor, exp_micro; |
2992 | unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); | |
2993 | ||
2994 | ret = t4_get_fw_version(adap, &adap->params.fw_vers); | |
21d11bd6 HS |
2995 | /* Try multiple times before returning error */ |
2996 | for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++) | |
2997 | ret = t4_get_fw_version(adap, &adap->params.fw_vers); | |
2998 | ||
a69265e9 HS |
2999 | if (ret) |
3000 | return ret; | |
3001 | ||
3002 | major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); | |
3003 | minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); | |
3004 | micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); | |
3005 | ||
3006 | switch (chip_version) { | |
3007 | case CHELSIO_T4: | |
3008 | exp_major = T4FW_MIN_VERSION_MAJOR; | |
3009 | exp_minor = T4FW_MIN_VERSION_MINOR; | |
3010 | exp_micro = T4FW_MIN_VERSION_MICRO; | |
3011 | break; | |
3012 | case CHELSIO_T5: | |
3013 | exp_major = T5FW_MIN_VERSION_MAJOR; | |
3014 | exp_minor = T5FW_MIN_VERSION_MINOR; | |
3015 | exp_micro = T5FW_MIN_VERSION_MICRO; | |
3016 | break; | |
3017 | case CHELSIO_T6: | |
3018 | exp_major = T6FW_MIN_VERSION_MAJOR; | |
3019 | exp_minor = T6FW_MIN_VERSION_MINOR; | |
3020 | exp_micro = T6FW_MIN_VERSION_MICRO; | |
3021 | break; | |
3022 | default: | |
3023 | dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", | |
3024 | adap->chip); | |
3025 | return -EINVAL; | |
3026 | } | |
3027 | ||
3028 | if (major < exp_major || (major == exp_major && minor < exp_minor) || | |
3029 | (major == exp_major && minor == exp_minor && micro < exp_micro)) { | |
3030 | dev_err(adap->pdev_dev, | |
3031 | "Card has firmware version %u.%u.%u, minimum " | |
3032 | "supported firmware is %u.%u.%u.\n", major, minor, | |
3033 | micro, exp_major, exp_minor, exp_micro); | |
3034 | return -EFAULT; | |
3035 | } | |
3036 | return 0; | |
3037 | } | |
3038 | ||
16e47624 HS |
3039 | /* Is the given firmware API compatible with the one the driver was compiled |
3040 | * with? | |
56d36be4 | 3041 | */ |
16e47624 | 3042 | static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) |
56d36be4 | 3043 | { |
56d36be4 | 3044 | |
16e47624 HS |
3045 | /* short circuit if it's the exact same firmware version */ |
3046 | if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) | |
3047 | return 1; | |
56d36be4 | 3048 | |
16e47624 HS |
3049 | #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) |
3050 | if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && | |
3051 | SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe)) | |
3052 | return 1; | |
3053 | #undef SAME_INTF | |
0a57a536 | 3054 | |
16e47624 HS |
3055 | return 0; |
3056 | } | |
56d36be4 | 3057 | |
16e47624 HS |
3058 | /* The firmware in the filesystem is usable, but should it be installed? |
3059 | * This routine explains itself in detail if it indicates the filesystem | |
3060 | * firmware should be installed. | |
3061 | */ | |
3062 | static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, | |
3063 | int k, int c) | |
3064 | { | |
3065 | const char *reason; | |
3066 | ||
3067 | if (!card_fw_usable) { | |
3068 | reason = "incompatible or unusable"; | |
3069 | goto install; | |
e69972f5 JH |
3070 | } |
3071 | ||
16e47624 HS |
3072 | if (k > c) { |
3073 | reason = "older than the version supported with this driver"; | |
3074 | goto install; | |
56d36be4 DM |
3075 | } |
3076 | ||
16e47624 HS |
3077 | return 0; |
3078 | ||
3079 | install: | |
3080 | dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " | |
3081 | "installing firmware %u.%u.%u.%u on card.\n", | |
b2e1a3f0 HS |
3082 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), |
3083 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason, | |
3084 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
3085 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
56d36be4 | 3086 | |
56d36be4 DM |
3087 | return 1; |
3088 | } | |
3089 | ||
16e47624 HS |
3090 | int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, |
3091 | const u8 *fw_data, unsigned int fw_size, | |
3092 | struct fw_hdr *card_fw, enum dev_state state, | |
3093 | int *reset) | |
3094 | { | |
3095 | int ret, card_fw_usable, fs_fw_usable; | |
3096 | const struct fw_hdr *fs_fw; | |
3097 | const struct fw_hdr *drv_fw; | |
3098 | ||
3099 | drv_fw = &fw_info->fw_hdr; | |
3100 | ||
3101 | /* Read the header of the firmware on the card */ | |
3102 | ret = -t4_read_flash(adap, FLASH_FW_START, | |
3103 | sizeof(*card_fw) / sizeof(uint32_t), | |
3104 | (uint32_t *)card_fw, 1); | |
3105 | if (ret == 0) { | |
3106 | card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw); | |
3107 | } else { | |
3108 | dev_err(adap->pdev_dev, | |
3109 | "Unable to read card's firmware header: %d\n", ret); | |
3110 | card_fw_usable = 0; | |
3111 | } | |
3112 | ||
3113 | if (fw_data != NULL) { | |
3114 | fs_fw = (const void *)fw_data; | |
3115 | fs_fw_usable = fw_compatible(drv_fw, fs_fw); | |
3116 | } else { | |
3117 | fs_fw = NULL; | |
3118 | fs_fw_usable = 0; | |
3119 | } | |
3120 | ||
3121 | if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && | |
3122 | (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { | |
3123 | /* Common case: the firmware on the card is an exact match and | |
3124 | * the filesystem one is an exact match too, or the filesystem | |
3125 | * one is absent/incompatible. | |
3126 | */ | |
3127 | } else if (fs_fw_usable && state == DEV_STATE_UNINIT && | |
3128 | should_install_fs_fw(adap, card_fw_usable, | |
3129 | be32_to_cpu(fs_fw->fw_ver), | |
3130 | be32_to_cpu(card_fw->fw_ver))) { | |
3131 | ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, | |
3132 | fw_size, 0); | |
3133 | if (ret != 0) { | |
3134 | dev_err(adap->pdev_dev, | |
3135 | "failed to install firmware: %d\n", ret); | |
3136 | goto bye; | |
3137 | } | |
3138 | ||
3139 | /* Installed successfully, update the cached header too. */ | |
e3d50738 | 3140 | *card_fw = *fs_fw; |
16e47624 HS |
3141 | card_fw_usable = 1; |
3142 | *reset = 0; /* already reset as part of load_fw */ | |
3143 | } | |
3144 | ||
3145 | if (!card_fw_usable) { | |
3146 | uint32_t d, c, k; | |
3147 | ||
3148 | d = be32_to_cpu(drv_fw->fw_ver); | |
3149 | c = be32_to_cpu(card_fw->fw_ver); | |
3150 | k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; | |
3151 | ||
3152 | dev_err(adap->pdev_dev, "Cannot find a usable firmware: " | |
3153 | "chip state %d, " | |
3154 | "driver compiled with %d.%d.%d.%d, " | |
3155 | "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n", | |
3156 | state, | |
b2e1a3f0 HS |
3157 | FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d), |
3158 | FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d), | |
3159 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), | |
3160 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), | |
3161 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
3162 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
16e47624 HS |
3163 | ret = EINVAL; |
3164 | goto bye; | |
3165 | } | |
3166 | ||
3167 | /* We're using whatever's on the card and it's known to be good. */ | |
3168 | adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); | |
3169 | adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); | |
3170 | ||
3171 | bye: | |
3172 | return ret; | |
3173 | } | |
3174 | ||
56d36be4 DM |
3175 | /** |
3176 | * t4_flash_erase_sectors - erase a range of flash sectors | |
3177 | * @adapter: the adapter | |
3178 | * @start: the first sector to erase | |
3179 | * @end: the last sector to erase | |
3180 | * | |
3181 | * Erases the sectors in the given inclusive range. | |
3182 | */ | |
3183 | static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) | |
3184 | { | |
3185 | int ret = 0; | |
3186 | ||
c0d5b8cf HS |
3187 | if (end >= adapter->params.sf_nsec) |
3188 | return -EINVAL; | |
3189 | ||
56d36be4 DM |
3190 | while (start <= end) { |
3191 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
3192 | (ret = sf1_write(adapter, 4, 0, 1, | |
3193 | SF_ERASE_SECTOR | (start << 8))) != 0 || | |
900a6596 | 3194 | (ret = flash_wait_op(adapter, 14, 500)) != 0) { |
56d36be4 DM |
3195 | dev_err(adapter->pdev_dev, |
3196 | "erase of flash sector %d failed, error %d\n", | |
3197 | start, ret); | |
3198 | break; | |
3199 | } | |
3200 | start++; | |
3201 | } | |
0d804338 | 3202 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
3203 | return ret; |
3204 | } | |
3205 | ||
636f9d37 VP |
3206 | /** |
3207 | * t4_flash_cfg_addr - return the address of the flash configuration file | |
3208 | * @adapter: the adapter | |
3209 | * | |
3210 | * Return the address within the flash where the Firmware Configuration | |
3211 | * File is stored. | |
3212 | */ | |
3213 | unsigned int t4_flash_cfg_addr(struct adapter *adapter) | |
3214 | { | |
3215 | if (adapter->params.sf_size == 0x100000) | |
3216 | return FLASH_FPGA_CFG_START; | |
3217 | else | |
3218 | return FLASH_CFG_START; | |
3219 | } | |
3220 | ||
79af221d HS |
3221 | /* Return TRUE if the specified firmware matches the adapter. I.e. T4 |
3222 | * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead | |
3223 | * and emit an error message for mismatched firmware to save our caller the | |
3224 | * effort ... | |
3225 | */ | |
3226 | static bool t4_fw_matches_chip(const struct adapter *adap, | |
3227 | const struct fw_hdr *hdr) | |
3228 | { | |
3229 | /* The expression below will return FALSE for any unsupported adapter | |
3230 | * which will keep us "honest" in the future ... | |
3231 | */ | |
3232 | if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || | |
3ccc6cf7 HS |
3233 | (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || |
3234 | (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) | |
79af221d HS |
3235 | return true; |
3236 | ||
3237 | dev_err(adap->pdev_dev, | |
3238 | "FW image (%d) is not suitable for this adapter (%d)\n", | |
3239 | hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3240 | return false; | |
3241 | } | |
3242 | ||
56d36be4 DM |
3243 | /** |
3244 | * t4_load_fw - download firmware | |
3245 | * @adap: the adapter | |
3246 | * @fw_data: the firmware image to write | |
3247 | * @size: image size | |
3248 | * | |
3249 | * Write the supplied firmware image to the card's serial flash. | |
3250 | */ | |
3251 | int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) | |
3252 | { | |
3253 | u32 csum; | |
3254 | int ret, addr; | |
3255 | unsigned int i; | |
3256 | u8 first_page[SF_PAGE_SIZE]; | |
404d9e3f | 3257 | const __be32 *p = (const __be32 *)fw_data; |
56d36be4 | 3258 | const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; |
900a6596 DM |
3259 | unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; |
3260 | unsigned int fw_img_start = adap->params.sf_fw_start; | |
3261 | unsigned int fw_start_sec = fw_img_start / sf_sec_size; | |
56d36be4 DM |
3262 | |
3263 | if (!size) { | |
3264 | dev_err(adap->pdev_dev, "FW image has no data\n"); | |
3265 | return -EINVAL; | |
3266 | } | |
3267 | if (size & 511) { | |
3268 | dev_err(adap->pdev_dev, | |
3269 | "FW image size not multiple of 512 bytes\n"); | |
3270 | return -EINVAL; | |
3271 | } | |
f404f80c | 3272 | if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) { |
56d36be4 DM |
3273 | dev_err(adap->pdev_dev, |
3274 | "FW image size differs from size in FW header\n"); | |
3275 | return -EINVAL; | |
3276 | } | |
3277 | if (size > FW_MAX_SIZE) { | |
3278 | dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", | |
3279 | FW_MAX_SIZE); | |
3280 | return -EFBIG; | |
3281 | } | |
79af221d HS |
3282 | if (!t4_fw_matches_chip(adap, hdr)) |
3283 | return -EINVAL; | |
56d36be4 DM |
3284 | |
3285 | for (csum = 0, i = 0; i < size / sizeof(csum); i++) | |
f404f80c | 3286 | csum += be32_to_cpu(p[i]); |
56d36be4 DM |
3287 | |
3288 | if (csum != 0xffffffff) { | |
3289 | dev_err(adap->pdev_dev, | |
3290 | "corrupted firmware image, checksum %#x\n", csum); | |
3291 | return -EINVAL; | |
3292 | } | |
3293 | ||
900a6596 DM |
3294 | i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ |
3295 | ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); | |
56d36be4 DM |
3296 | if (ret) |
3297 | goto out; | |
3298 | ||
3299 | /* | |
3300 | * We write the correct version at the end so the driver can see a bad | |
3301 | * version if the FW write fails. Start by writing a copy of the | |
3302 | * first page with a bad version. | |
3303 | */ | |
3304 | memcpy(first_page, fw_data, SF_PAGE_SIZE); | |
f404f80c | 3305 | ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); |
900a6596 | 3306 | ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); |
56d36be4 DM |
3307 | if (ret) |
3308 | goto out; | |
3309 | ||
900a6596 | 3310 | addr = fw_img_start; |
56d36be4 DM |
3311 | for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { |
3312 | addr += SF_PAGE_SIZE; | |
3313 | fw_data += SF_PAGE_SIZE; | |
3314 | ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); | |
3315 | if (ret) | |
3316 | goto out; | |
3317 | } | |
3318 | ||
3319 | ret = t4_write_flash(adap, | |
900a6596 | 3320 | fw_img_start + offsetof(struct fw_hdr, fw_ver), |
56d36be4 DM |
3321 | sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); |
3322 | out: | |
3323 | if (ret) | |
3324 | dev_err(adap->pdev_dev, "firmware download failed, error %d\n", | |
3325 | ret); | |
dff04bce HS |
3326 | else |
3327 | ret = t4_get_fw_version(adap, &adap->params.fw_vers); | |
56d36be4 DM |
3328 | return ret; |
3329 | } | |
3330 | ||
01b69614 HS |
3331 | /** |
3332 | * t4_phy_fw_ver - return current PHY firmware version | |
3333 | * @adap: the adapter | |
3334 | * @phy_fw_ver: return value buffer for PHY firmware version | |
3335 | * | |
3336 | * Returns the current version of external PHY firmware on the | |
3337 | * adapter. | |
3338 | */ | |
3339 | int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver) | |
3340 | { | |
3341 | u32 param, val; | |
3342 | int ret; | |
3343 | ||
3344 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
3345 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | | |
3346 | FW_PARAMS_PARAM_Y_V(adap->params.portvec) | | |
3347 | FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION)); | |
b2612722 | 3348 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
3349 | ¶m, &val); |
3350 | if (ret < 0) | |
3351 | return ret; | |
3352 | *phy_fw_ver = val; | |
3353 | return 0; | |
3354 | } | |
3355 | ||
3356 | /** | |
3357 | * t4_load_phy_fw - download port PHY firmware | |
3358 | * @adap: the adapter | |
3359 | * @win: the PCI-E Memory Window index to use for t4_memory_rw() | |
3360 | * @win_lock: the lock to use to guard the memory copy | |
3361 | * @phy_fw_version: function to check PHY firmware versions | |
3362 | * @phy_fw_data: the PHY firmware image to write | |
3363 | * @phy_fw_size: image size | |
3364 | * | |
3365 | * Transfer the specified PHY firmware to the adapter. If a non-NULL | |
3366 | * @phy_fw_version is supplied, then it will be used to determine if | |
3367 | * it's necessary to perform the transfer by comparing the version | |
3368 | * of any existing adapter PHY firmware with that of the passed in | |
3369 | * PHY firmware image. If @win_lock is non-NULL then it will be used | |
3370 | * around the call to t4_memory_rw() which transfers the PHY firmware | |
3371 | * to the adapter. | |
3372 | * | |
3373 | * A negative error number will be returned if an error occurs. If | |
3374 | * version number support is available and there's no need to upgrade | |
3375 | * the firmware, 0 will be returned. If firmware is successfully | |
3376 | * transferred to the adapter, 1 will be retured. | |
3377 | * | |
3378 | * NOTE: some adapters only have local RAM to store the PHY firmware. As | |
3379 | * a result, a RESET of the adapter would cause that RAM to lose its | |
3380 | * contents. Thus, loading PHY firmware on such adapters must happen | |
3381 | * after any FW_RESET_CMDs ... | |
3382 | */ | |
3383 | int t4_load_phy_fw(struct adapter *adap, | |
3384 | int win, spinlock_t *win_lock, | |
3385 | int (*phy_fw_version)(const u8 *, size_t), | |
3386 | const u8 *phy_fw_data, size_t phy_fw_size) | |
3387 | { | |
3388 | unsigned long mtype = 0, maddr = 0; | |
3389 | u32 param, val; | |
3390 | int cur_phy_fw_ver = 0, new_phy_fw_vers = 0; | |
3391 | int ret; | |
3392 | ||
3393 | /* If we have version number support, then check to see if the adapter | |
3394 | * already has up-to-date PHY firmware loaded. | |
3395 | */ | |
3396 | if (phy_fw_version) { | |
3397 | new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size); | |
3398 | ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3399 | if (ret < 0) | |
3400 | return ret; | |
3401 | ||
3402 | if (cur_phy_fw_ver >= new_phy_fw_vers) { | |
3403 | CH_WARN(adap, "PHY Firmware already up-to-date, " | |
3404 | "version %#x\n", cur_phy_fw_ver); | |
3405 | return 0; | |
3406 | } | |
3407 | } | |
3408 | ||
3409 | /* Ask the firmware where it wants us to copy the PHY firmware image. | |
3410 | * The size of the file requires a special version of the READ coommand | |
3411 | * which will pass the file size via the values field in PARAMS_CMD and | |
3412 | * retrieve the return value from firmware and place it in the same | |
3413 | * buffer values | |
3414 | */ | |
3415 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
3416 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | | |
3417 | FW_PARAMS_PARAM_Y_V(adap->params.portvec) | | |
3418 | FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); | |
3419 | val = phy_fw_size; | |
b2612722 | 3420 | ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
3421 | ¶m, &val, 1); |
3422 | if (ret < 0) | |
3423 | return ret; | |
3424 | mtype = val >> 8; | |
3425 | maddr = (val & 0xff) << 16; | |
3426 | ||
3427 | /* Copy the supplied PHY Firmware image to the adapter memory location | |
3428 | * allocated by the adapter firmware. | |
3429 | */ | |
3430 | if (win_lock) | |
3431 | spin_lock_bh(win_lock); | |
3432 | ret = t4_memory_rw(adap, win, mtype, maddr, | |
3433 | phy_fw_size, (__be32 *)phy_fw_data, | |
3434 | T4_MEMORY_WRITE); | |
3435 | if (win_lock) | |
3436 | spin_unlock_bh(win_lock); | |
3437 | if (ret) | |
3438 | return ret; | |
3439 | ||
3440 | /* Tell the firmware that the PHY firmware image has been written to | |
3441 | * RAM and it can now start copying it over to the PHYs. The chip | |
3442 | * firmware will RESET the affected PHYs as part of this operation | |
3443 | * leaving them running the new PHY firmware image. | |
3444 | */ | |
3445 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
3446 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | | |
3447 | FW_PARAMS_PARAM_Y_V(adap->params.portvec) | | |
3448 | FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); | |
b2612722 | 3449 | ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
3450 | ¶m, &val, 30000); |
3451 | ||
3452 | /* If we have version number support, then check to see that the new | |
3453 | * firmware got loaded properly. | |
3454 | */ | |
3455 | if (phy_fw_version) { | |
3456 | ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3457 | if (ret < 0) | |
3458 | return ret; | |
3459 | ||
3460 | if (cur_phy_fw_ver != new_phy_fw_vers) { | |
3461 | CH_WARN(adap, "PHY Firmware did not update: " | |
3462 | "version on adapter %#x, " | |
3463 | "version flashed %#x\n", | |
3464 | cur_phy_fw_ver, new_phy_fw_vers); | |
3465 | return -ENXIO; | |
3466 | } | |
3467 | } | |
3468 | ||
3469 | return 1; | |
3470 | } | |
3471 | ||
49216c1c HS |
3472 | /** |
3473 | * t4_fwcache - firmware cache operation | |
3474 | * @adap: the adapter | |
3475 | * @op : the operation (flush or flush and invalidate) | |
3476 | */ | |
3477 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) | |
3478 | { | |
3479 | struct fw_params_cmd c; | |
3480 | ||
3481 | memset(&c, 0, sizeof(c)); | |
3482 | c.op_to_vfn = | |
3483 | cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | | |
3484 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
b2612722 | 3485 | FW_PARAMS_CMD_PFN_V(adap->pf) | |
49216c1c HS |
3486 | FW_PARAMS_CMD_VFN_V(0)); |
3487 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
3488 | c.param[0].mnem = | |
3489 | cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
3490 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE)); | |
3491 | c.param[0].val = (__force __be32)op; | |
3492 | ||
3493 | return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); | |
3494 | } | |
3495 | ||
19689609 HS |
3496 | void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, |
3497 | unsigned int *pif_req_wrptr, | |
3498 | unsigned int *pif_rsp_wrptr) | |
3499 | { | |
3500 | int i, j; | |
3501 | u32 cfg, val, req, rsp; | |
3502 | ||
3503 | cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); | |
3504 | if (cfg & LADBGEN_F) | |
3505 | t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); | |
3506 | ||
3507 | val = t4_read_reg(adap, CIM_DEBUGSTS_A); | |
3508 | req = POLADBGWRPTR_G(val); | |
3509 | rsp = PILADBGWRPTR_G(val); | |
3510 | if (pif_req_wrptr) | |
3511 | *pif_req_wrptr = req; | |
3512 | if (pif_rsp_wrptr) | |
3513 | *pif_rsp_wrptr = rsp; | |
3514 | ||
3515 | for (i = 0; i < CIM_PIFLA_SIZE; i++) { | |
3516 | for (j = 0; j < 6; j++) { | |
3517 | t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | | |
3518 | PILADBGRDPTR_V(rsp)); | |
3519 | *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); | |
3520 | *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); | |
3521 | req++; | |
3522 | rsp++; | |
3523 | } | |
3524 | req = (req + 2) & POLADBGRDPTR_M; | |
3525 | rsp = (rsp + 2) & PILADBGRDPTR_M; | |
3526 | } | |
3527 | t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); | |
3528 | } | |
3529 | ||
26fae93f HS |
3530 | void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) |
3531 | { | |
3532 | u32 cfg; | |
3533 | int i, j, idx; | |
3534 | ||
3535 | cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); | |
3536 | if (cfg & LADBGEN_F) | |
3537 | t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); | |
3538 | ||
3539 | for (i = 0; i < CIM_MALA_SIZE; i++) { | |
3540 | for (j = 0; j < 5; j++) { | |
3541 | idx = 8 * i + j; | |
3542 | t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | | |
3543 | PILADBGRDPTR_V(idx)); | |
3544 | *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); | |
3545 | *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); | |
3546 | } | |
3547 | } | |
3548 | t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); | |
3549 | } | |
3550 | ||
797ff0f5 HS |
3551 | void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) |
3552 | { | |
3553 | unsigned int i, j; | |
3554 | ||
3555 | for (i = 0; i < 8; i++) { | |
3556 | u32 *p = la_buf + i; | |
3557 | ||
3558 | t4_write_reg(adap, ULP_RX_LA_CTL_A, i); | |
3559 | j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); | |
3560 | t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); | |
3561 | for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) | |
3562 | *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); | |
3563 | } | |
3564 | } | |
3565 | ||
56d36be4 | 3566 | #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ |
72aca4bf KS |
3567 | FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ |
3568 | FW_PORT_CAP_ANEG) | |
56d36be4 DM |
3569 | |
3570 | /** | |
4036da90 | 3571 | * t4_link_l1cfg - apply link configuration to MAC/PHY |
56d36be4 DM |
3572 | * @phy: the PHY to setup |
3573 | * @mac: the MAC to setup | |
3574 | * @lc: the requested link configuration | |
3575 | * | |
3576 | * Set up a port's MAC and PHY according to a desired link configuration. | |
3577 | * - If the PHY can auto-negotiate first decide what to advertise, then | |
3578 | * enable/disable auto-negotiation as desired, and reset. | |
3579 | * - If the PHY does not auto-negotiate just reset it. | |
3580 | * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, | |
3581 | * otherwise do it later based on the outcome of auto-negotiation. | |
3582 | */ | |
4036da90 | 3583 | int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, |
56d36be4 DM |
3584 | struct link_config *lc) |
3585 | { | |
3586 | struct fw_port_cmd c; | |
2b5fb1f2 | 3587 | unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO); |
56d36be4 DM |
3588 | |
3589 | lc->link_ok = 0; | |
3590 | if (lc->requested_fc & PAUSE_RX) | |
3591 | fc |= FW_PORT_CAP_FC_RX; | |
3592 | if (lc->requested_fc & PAUSE_TX) | |
3593 | fc |= FW_PORT_CAP_FC_TX; | |
3594 | ||
3595 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
3596 | c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | |
3597 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
3598 | FW_PORT_CMD_PORTID_V(port)); | |
3599 | c.action_to_len16 = | |
3600 | cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | | |
3601 | FW_LEN16(c)); | |
56d36be4 DM |
3602 | |
3603 | if (!(lc->supported & FW_PORT_CAP_ANEG)) { | |
f404f80c HS |
3604 | c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) | |
3605 | fc); | |
56d36be4 DM |
3606 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); |
3607 | } else if (lc->autoneg == AUTONEG_DISABLE) { | |
f404f80c | 3608 | c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi); |
56d36be4 DM |
3609 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); |
3610 | } else | |
f404f80c | 3611 | c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi); |
56d36be4 DM |
3612 | |
3613 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3614 | } | |
3615 | ||
3616 | /** | |
3617 | * t4_restart_aneg - restart autonegotiation | |
3618 | * @adap: the adapter | |
3619 | * @mbox: mbox to use for the FW command | |
3620 | * @port: the port id | |
3621 | * | |
3622 | * Restarts autonegotiation for the selected port. | |
3623 | */ | |
3624 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) | |
3625 | { | |
3626 | struct fw_port_cmd c; | |
3627 | ||
3628 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
3629 | c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | |
3630 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
3631 | FW_PORT_CMD_PORTID_V(port)); | |
3632 | c.action_to_len16 = | |
3633 | cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | | |
3634 | FW_LEN16(c)); | |
3635 | c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); | |
56d36be4 DM |
3636 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
3637 | } | |
3638 | ||
8caa1e84 VP |
3639 | typedef void (*int_handler_t)(struct adapter *adap); |
3640 | ||
56d36be4 DM |
3641 | struct intr_info { |
3642 | unsigned int mask; /* bits to check in interrupt status */ | |
3643 | const char *msg; /* message to print or NULL */ | |
3644 | short stat_idx; /* stat counter to increment or -1 */ | |
3645 | unsigned short fatal; /* whether the condition reported is fatal */ | |
8caa1e84 | 3646 | int_handler_t int_handler; /* platform-specific int handler */ |
56d36be4 DM |
3647 | }; |
3648 | ||
3649 | /** | |
3650 | * t4_handle_intr_status - table driven interrupt handler | |
3651 | * @adapter: the adapter that generated the interrupt | |
3652 | * @reg: the interrupt status register to process | |
3653 | * @acts: table of interrupt actions | |
3654 | * | |
3655 | * A table driven interrupt handler that applies a set of masks to an | |
3656 | * interrupt status word and performs the corresponding actions if the | |
25985edc | 3657 | * interrupts described by the mask have occurred. The actions include |
56d36be4 DM |
3658 | * optionally emitting a warning or alert message. The table is terminated |
3659 | * by an entry specifying mask 0. Returns the number of fatal interrupt | |
3660 | * conditions. | |
3661 | */ | |
3662 | static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, | |
3663 | const struct intr_info *acts) | |
3664 | { | |
3665 | int fatal = 0; | |
3666 | unsigned int mask = 0; | |
3667 | unsigned int status = t4_read_reg(adapter, reg); | |
3668 | ||
3669 | for ( ; acts->mask; ++acts) { | |
3670 | if (!(status & acts->mask)) | |
3671 | continue; | |
3672 | if (acts->fatal) { | |
3673 | fatal++; | |
3674 | dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
3675 | status & acts->mask); | |
3676 | } else if (acts->msg && printk_ratelimit()) | |
3677 | dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
3678 | status & acts->mask); | |
8caa1e84 VP |
3679 | if (acts->int_handler) |
3680 | acts->int_handler(adapter); | |
56d36be4 DM |
3681 | mask |= acts->mask; |
3682 | } | |
3683 | status &= mask; | |
3684 | if (status) /* clear processed interrupts */ | |
3685 | t4_write_reg(adapter, reg, status); | |
3686 | return fatal; | |
3687 | } | |
3688 | ||
3689 | /* | |
3690 | * Interrupt handler for the PCIE module. | |
3691 | */ | |
3692 | static void pcie_intr_handler(struct adapter *adapter) | |
3693 | { | |
005b5717 | 3694 | static const struct intr_info sysbus_intr_info[] = { |
f061de42 HS |
3695 | { RNPP_F, "RXNP array parity error", -1, 1 }, |
3696 | { RPCP_F, "RXPC array parity error", -1, 1 }, | |
3697 | { RCIP_F, "RXCIF array parity error", -1, 1 }, | |
3698 | { RCCP_F, "Rx completions control array parity error", -1, 1 }, | |
3699 | { RFTP_F, "RXFT array parity error", -1, 1 }, | |
56d36be4 DM |
3700 | { 0 } |
3701 | }; | |
005b5717 | 3702 | static const struct intr_info pcie_port_intr_info[] = { |
f061de42 HS |
3703 | { TPCP_F, "TXPC array parity error", -1, 1 }, |
3704 | { TNPP_F, "TXNP array parity error", -1, 1 }, | |
3705 | { TFTP_F, "TXFT array parity error", -1, 1 }, | |
3706 | { TCAP_F, "TXCA array parity error", -1, 1 }, | |
3707 | { TCIP_F, "TXCIF array parity error", -1, 1 }, | |
3708 | { RCAP_F, "RXCA array parity error", -1, 1 }, | |
3709 | { OTDD_F, "outbound request TLP discarded", -1, 1 }, | |
3710 | { RDPE_F, "Rx data parity error", -1, 1 }, | |
3711 | { TDUE_F, "Tx uncorrectable data error", -1, 1 }, | |
56d36be4 DM |
3712 | { 0 } |
3713 | }; | |
005b5717 | 3714 | static const struct intr_info pcie_intr_info[] = { |
f061de42 HS |
3715 | { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, |
3716 | { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, | |
3717 | { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, | |
3718 | { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, | |
3719 | { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, | |
3720 | { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, | |
3721 | { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, | |
3722 | { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, | |
3723 | { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, | |
3724 | { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, | |
3725 | { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, | |
3726 | { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, | |
3727 | { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, | |
3728 | { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, | |
3729 | { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, | |
3730 | { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, | |
3731 | { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, | |
3732 | { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, | |
3733 | { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, | |
3734 | { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, | |
3735 | { FIDPERR_F, "PCI FID parity error", -1, 1 }, | |
3736 | { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, | |
3737 | { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, | |
3738 | { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, | |
3739 | { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, | |
3740 | { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, | |
3741 | { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, | |
3742 | { PCIESINT_F, "PCI core secondary fault", -1, 1 }, | |
3743 | { PCIEPINT_F, "PCI core primary fault", -1, 1 }, | |
3744 | { UNXSPLCPLERR_F, "PCI unexpected split completion error", | |
3745 | -1, 0 }, | |
56d36be4 DM |
3746 | { 0 } |
3747 | }; | |
3748 | ||
0a57a536 | 3749 | static struct intr_info t5_pcie_intr_info[] = { |
f061de42 | 3750 | { MSTGRPPERR_F, "Master Response Read Queue parity error", |
0a57a536 | 3751 | -1, 1 }, |
f061de42 HS |
3752 | { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, |
3753 | { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, | |
3754 | { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, | |
3755 | { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, | |
3756 | { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, | |
3757 | { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, | |
3758 | { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", | |
0a57a536 | 3759 | -1, 1 }, |
f061de42 | 3760 | { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", |
0a57a536 | 3761 | -1, 1 }, |
f061de42 HS |
3762 | { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, |
3763 | { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, | |
3764 | { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, | |
3765 | { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, | |
3766 | { DREQWRPERR_F, "PCI DMA channel write request parity error", | |
0a57a536 | 3767 | -1, 1 }, |
f061de42 HS |
3768 | { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, |
3769 | { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, | |
3770 | { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, | |
3771 | { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, | |
3772 | { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, | |
3773 | { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, | |
3774 | { FIDPERR_F, "PCI FID parity error", -1, 1 }, | |
3775 | { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, | |
3776 | { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, | |
3777 | { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, | |
3778 | { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", | |
0a57a536 | 3779 | -1, 1 }, |
f061de42 HS |
3780 | { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", |
3781 | -1, 1 }, | |
3782 | { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, | |
3783 | { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, | |
3784 | { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, | |
3785 | { READRSPERR_F, "Outbound read error", -1, 0 }, | |
0a57a536 SR |
3786 | { 0 } |
3787 | }; | |
3788 | ||
56d36be4 DM |
3789 | int fat; |
3790 | ||
9bb59b96 HS |
3791 | if (is_t4(adapter->params.chip)) |
3792 | fat = t4_handle_intr_status(adapter, | |
f061de42 HS |
3793 | PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A, |
3794 | sysbus_intr_info) + | |
9bb59b96 | 3795 | t4_handle_intr_status(adapter, |
f061de42 HS |
3796 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A, |
3797 | pcie_port_intr_info) + | |
3798 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, | |
9bb59b96 HS |
3799 | pcie_intr_info); |
3800 | else | |
f061de42 | 3801 | fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, |
9bb59b96 | 3802 | t5_pcie_intr_info); |
0a57a536 | 3803 | |
56d36be4 DM |
3804 | if (fat) |
3805 | t4_fatal_err(adapter); | |
3806 | } | |
3807 | ||
3808 | /* | |
3809 | * TP interrupt handler. | |
3810 | */ | |
3811 | static void tp_intr_handler(struct adapter *adapter) | |
3812 | { | |
005b5717 | 3813 | static const struct intr_info tp_intr_info[] = { |
56d36be4 | 3814 | { 0x3fffffff, "TP parity error", -1, 1 }, |
837e4a42 | 3815 | { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, |
56d36be4 DM |
3816 | { 0 } |
3817 | }; | |
3818 | ||
837e4a42 | 3819 | if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info)) |
56d36be4 DM |
3820 | t4_fatal_err(adapter); |
3821 | } | |
3822 | ||
3823 | /* | |
3824 | * SGE interrupt handler. | |
3825 | */ | |
3826 | static void sge_intr_handler(struct adapter *adapter) | |
3827 | { | |
3828 | u64 v; | |
3ccc6cf7 | 3829 | u32 err; |
56d36be4 | 3830 | |
005b5717 | 3831 | static const struct intr_info sge_intr_info[] = { |
f612b815 | 3832 | { ERR_CPL_EXCEED_IQE_SIZE_F, |
56d36be4 | 3833 | "SGE received CPL exceeding IQE size", -1, 1 }, |
f612b815 | 3834 | { ERR_INVALID_CIDX_INC_F, |
56d36be4 | 3835 | "SGE GTS CIDX increment too large", -1, 0 }, |
f612b815 HS |
3836 | { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, |
3837 | { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, | |
f612b815 | 3838 | { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, |
56d36be4 | 3839 | "SGE IQID > 1023 received CPL for FL", -1, 0 }, |
f612b815 | 3840 | { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, |
56d36be4 | 3841 | 0 }, |
f612b815 | 3842 | { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, |
56d36be4 | 3843 | 0 }, |
f612b815 | 3844 | { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, |
56d36be4 | 3845 | 0 }, |
f612b815 | 3846 | { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, |
56d36be4 | 3847 | 0 }, |
f612b815 | 3848 | { ERR_ING_CTXT_PRIO_F, |
56d36be4 | 3849 | "SGE too many priority ingress contexts", -1, 0 }, |
f612b815 HS |
3850 | { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, |
3851 | { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, | |
56d36be4 DM |
3852 | { 0 } |
3853 | }; | |
3854 | ||
3ccc6cf7 HS |
3855 | static struct intr_info t4t5_sge_intr_info[] = { |
3856 | { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, | |
3857 | { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, | |
3858 | { ERR_EGR_CTXT_PRIO_F, | |
3859 | "SGE too many priority egress contexts", -1, 0 }, | |
3860 | { 0 } | |
3861 | }; | |
3862 | ||
f612b815 HS |
3863 | v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | |
3864 | ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); | |
56d36be4 DM |
3865 | if (v) { |
3866 | dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", | |
8caa1e84 | 3867 | (unsigned long long)v); |
f612b815 HS |
3868 | t4_write_reg(adapter, SGE_INT_CAUSE1_A, v); |
3869 | t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32); | |
56d36be4 DM |
3870 | } |
3871 | ||
3ccc6cf7 HS |
3872 | v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info); |
3873 | if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) | |
3874 | v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, | |
3875 | t4t5_sge_intr_info); | |
3876 | ||
3877 | err = t4_read_reg(adapter, SGE_ERROR_STATS_A); | |
3878 | if (err & ERROR_QID_VALID_F) { | |
3879 | dev_err(adapter->pdev_dev, "SGE error for queue %u\n", | |
3880 | ERROR_QID_G(err)); | |
3881 | if (err & UNCAPTURED_ERROR_F) | |
3882 | dev_err(adapter->pdev_dev, | |
3883 | "SGE UNCAPTURED_ERROR set (clearing)\n"); | |
3884 | t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F | | |
3885 | UNCAPTURED_ERROR_F); | |
3886 | } | |
3887 | ||
3888 | if (v != 0) | |
56d36be4 DM |
3889 | t4_fatal_err(adapter); |
3890 | } | |
3891 | ||
89c3a86c HS |
3892 | #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\ |
3893 | OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F) | |
3894 | #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\ | |
3895 | IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F) | |
3896 | ||
56d36be4 DM |
3897 | /* |
3898 | * CIM interrupt handler. | |
3899 | */ | |
3900 | static void cim_intr_handler(struct adapter *adapter) | |
3901 | { | |
005b5717 | 3902 | static const struct intr_info cim_intr_info[] = { |
89c3a86c HS |
3903 | { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, |
3904 | { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, | |
3905 | { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, | |
3906 | { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, | |
3907 | { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, | |
3908 | { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, | |
3909 | { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, | |
56d36be4 DM |
3910 | { 0 } |
3911 | }; | |
005b5717 | 3912 | static const struct intr_info cim_upintr_info[] = { |
89c3a86c HS |
3913 | { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, |
3914 | { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, | |
3915 | { ILLWRINT_F, "CIM illegal write", -1, 1 }, | |
3916 | { ILLRDINT_F, "CIM illegal read", -1, 1 }, | |
3917 | { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, | |
3918 | { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, | |
3919 | { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, | |
3920 | { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, | |
3921 | { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, | |
3922 | { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, | |
3923 | { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, | |
3924 | { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, | |
3925 | { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, | |
3926 | { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, | |
3927 | { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, | |
3928 | { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, | |
3929 | { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, | |
3930 | { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, | |
3931 | { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, | |
3932 | { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, | |
3933 | { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, | |
3934 | { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, | |
3935 | { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, | |
3936 | { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, | |
3937 | { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, | |
3938 | { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, | |
3939 | { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, | |
3940 | { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, | |
56d36be4 DM |
3941 | { 0 } |
3942 | }; | |
3943 | ||
3944 | int fat; | |
3945 | ||
f061de42 | 3946 | if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F) |
31d55c2d HS |
3947 | t4_report_fw_error(adapter); |
3948 | ||
89c3a86c | 3949 | fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A, |
56d36be4 | 3950 | cim_intr_info) + |
89c3a86c | 3951 | t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A, |
56d36be4 DM |
3952 | cim_upintr_info); |
3953 | if (fat) | |
3954 | t4_fatal_err(adapter); | |
3955 | } | |
3956 | ||
3957 | /* | |
3958 | * ULP RX interrupt handler. | |
3959 | */ | |
3960 | static void ulprx_intr_handler(struct adapter *adapter) | |
3961 | { | |
005b5717 | 3962 | static const struct intr_info ulprx_intr_info[] = { |
91e9a1ec | 3963 | { 0x1800000, "ULPRX context error", -1, 1 }, |
56d36be4 DM |
3964 | { 0x7fffff, "ULPRX parity error", -1, 1 }, |
3965 | { 0 } | |
3966 | }; | |
3967 | ||
0d804338 | 3968 | if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) |
56d36be4 DM |
3969 | t4_fatal_err(adapter); |
3970 | } | |
3971 | ||
3972 | /* | |
3973 | * ULP TX interrupt handler. | |
3974 | */ | |
3975 | static void ulptx_intr_handler(struct adapter *adapter) | |
3976 | { | |
005b5717 | 3977 | static const struct intr_info ulptx_intr_info[] = { |
837e4a42 | 3978 | { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, |
56d36be4 | 3979 | 0 }, |
837e4a42 | 3980 | { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, |
56d36be4 | 3981 | 0 }, |
837e4a42 | 3982 | { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, |
56d36be4 | 3983 | 0 }, |
837e4a42 | 3984 | { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, |
56d36be4 DM |
3985 | 0 }, |
3986 | { 0xfffffff, "ULPTX parity error", -1, 1 }, | |
3987 | { 0 } | |
3988 | }; | |
3989 | ||
837e4a42 | 3990 | if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) |
56d36be4 DM |
3991 | t4_fatal_err(adapter); |
3992 | } | |
3993 | ||
3994 | /* | |
3995 | * PM TX interrupt handler. | |
3996 | */ | |
3997 | static void pmtx_intr_handler(struct adapter *adapter) | |
3998 | { | |
005b5717 | 3999 | static const struct intr_info pmtx_intr_info[] = { |
837e4a42 HS |
4000 | { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, |
4001 | { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, | |
4002 | { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, | |
4003 | { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, | |
4004 | { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, | |
4005 | { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, | |
4006 | { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", | |
4007 | -1, 1 }, | |
4008 | { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, | |
4009 | { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, | |
56d36be4 DM |
4010 | { 0 } |
4011 | }; | |
4012 | ||
837e4a42 | 4013 | if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info)) |
56d36be4 DM |
4014 | t4_fatal_err(adapter); |
4015 | } | |
4016 | ||
4017 | /* | |
4018 | * PM RX interrupt handler. | |
4019 | */ | |
4020 | static void pmrx_intr_handler(struct adapter *adapter) | |
4021 | { | |
005b5717 | 4022 | static const struct intr_info pmrx_intr_info[] = { |
837e4a42 HS |
4023 | { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, |
4024 | { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, | |
4025 | { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, | |
4026 | { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", | |
4027 | -1, 1 }, | |
4028 | { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, | |
4029 | { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, | |
56d36be4 DM |
4030 | { 0 } |
4031 | }; | |
4032 | ||
837e4a42 | 4033 | if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info)) |
56d36be4 DM |
4034 | t4_fatal_err(adapter); |
4035 | } | |
4036 | ||
4037 | /* | |
4038 | * CPL switch interrupt handler. | |
4039 | */ | |
4040 | static void cplsw_intr_handler(struct adapter *adapter) | |
4041 | { | |
005b5717 | 4042 | static const struct intr_info cplsw_intr_info[] = { |
0d804338 HS |
4043 | { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, |
4044 | { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, | |
4045 | { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, | |
4046 | { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, | |
4047 | { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, | |
4048 | { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, | |
56d36be4 DM |
4049 | { 0 } |
4050 | }; | |
4051 | ||
0d804338 | 4052 | if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info)) |
56d36be4 DM |
4053 | t4_fatal_err(adapter); |
4054 | } | |
4055 | ||
4056 | /* | |
4057 | * LE interrupt handler. | |
4058 | */ | |
4059 | static void le_intr_handler(struct adapter *adap) | |
4060 | { | |
3ccc6cf7 | 4061 | enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); |
005b5717 | 4062 | static const struct intr_info le_intr_info[] = { |
0d804338 HS |
4063 | { LIPMISS_F, "LE LIP miss", -1, 0 }, |
4064 | { LIP0_F, "LE 0 LIP error", -1, 0 }, | |
4065 | { PARITYERR_F, "LE parity error", -1, 1 }, | |
4066 | { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, | |
4067 | { REQQPARERR_F, "LE request queue parity error", -1, 1 }, | |
56d36be4 DM |
4068 | { 0 } |
4069 | }; | |
4070 | ||
3ccc6cf7 HS |
4071 | static struct intr_info t6_le_intr_info[] = { |
4072 | { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, | |
4073 | { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, | |
4074 | { TCAMINTPERR_F, "LE parity error", -1, 1 }, | |
4075 | { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, | |
4076 | { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, | |
4077 | { 0 } | |
4078 | }; | |
4079 | ||
4080 | if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, | |
4081 | (chip <= CHELSIO_T5) ? | |
4082 | le_intr_info : t6_le_intr_info)) | |
56d36be4 DM |
4083 | t4_fatal_err(adap); |
4084 | } | |
4085 | ||
4086 | /* | |
4087 | * MPS interrupt handler. | |
4088 | */ | |
4089 | static void mps_intr_handler(struct adapter *adapter) | |
4090 | { | |
005b5717 | 4091 | static const struct intr_info mps_rx_intr_info[] = { |
56d36be4 DM |
4092 | { 0xffffff, "MPS Rx parity error", -1, 1 }, |
4093 | { 0 } | |
4094 | }; | |
005b5717 | 4095 | static const struct intr_info mps_tx_intr_info[] = { |
837e4a42 HS |
4096 | { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, |
4097 | { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, | |
4098 | { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error", | |
4099 | -1, 1 }, | |
4100 | { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error", | |
4101 | -1, 1 }, | |
4102 | { BUBBLE_F, "MPS Tx underflow", -1, 1 }, | |
4103 | { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, | |
4104 | { FRMERR_F, "MPS Tx framing error", -1, 1 }, | |
56d36be4 DM |
4105 | { 0 } |
4106 | }; | |
005b5717 | 4107 | static const struct intr_info mps_trc_intr_info[] = { |
837e4a42 HS |
4108 | { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, |
4109 | { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error", | |
4110 | -1, 1 }, | |
4111 | { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, | |
56d36be4 DM |
4112 | { 0 } |
4113 | }; | |
005b5717 | 4114 | static const struct intr_info mps_stat_sram_intr_info[] = { |
56d36be4 DM |
4115 | { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, |
4116 | { 0 } | |
4117 | }; | |
005b5717 | 4118 | static const struct intr_info mps_stat_tx_intr_info[] = { |
56d36be4 DM |
4119 | { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, |
4120 | { 0 } | |
4121 | }; | |
005b5717 | 4122 | static const struct intr_info mps_stat_rx_intr_info[] = { |
56d36be4 DM |
4123 | { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, |
4124 | { 0 } | |
4125 | }; | |
005b5717 | 4126 | static const struct intr_info mps_cls_intr_info[] = { |
837e4a42 HS |
4127 | { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, |
4128 | { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, | |
4129 | { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, | |
56d36be4 DM |
4130 | { 0 } |
4131 | }; | |
4132 | ||
4133 | int fat; | |
4134 | ||
837e4a42 | 4135 | fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A, |
56d36be4 | 4136 | mps_rx_intr_info) + |
837e4a42 | 4137 | t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A, |
56d36be4 | 4138 | mps_tx_intr_info) + |
837e4a42 | 4139 | t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A, |
56d36be4 | 4140 | mps_trc_intr_info) + |
837e4a42 | 4141 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A, |
56d36be4 | 4142 | mps_stat_sram_intr_info) + |
837e4a42 | 4143 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, |
56d36be4 | 4144 | mps_stat_tx_intr_info) + |
837e4a42 | 4145 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, |
56d36be4 | 4146 | mps_stat_rx_intr_info) + |
837e4a42 | 4147 | t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A, |
56d36be4 DM |
4148 | mps_cls_intr_info); |
4149 | ||
837e4a42 HS |
4150 | t4_write_reg(adapter, MPS_INT_CAUSE_A, 0); |
4151 | t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */ | |
56d36be4 DM |
4152 | if (fat) |
4153 | t4_fatal_err(adapter); | |
4154 | } | |
4155 | ||
89c3a86c HS |
4156 | #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \ |
4157 | ECC_UE_INT_CAUSE_F) | |
56d36be4 DM |
4158 | |
4159 | /* | |
4160 | * EDC/MC interrupt handler. | |
4161 | */ | |
4162 | static void mem_intr_handler(struct adapter *adapter, int idx) | |
4163 | { | |
822dd8a8 | 4164 | static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; |
56d36be4 DM |
4165 | |
4166 | unsigned int addr, cnt_addr, v; | |
4167 | ||
4168 | if (idx <= MEM_EDC1) { | |
89c3a86c HS |
4169 | addr = EDC_REG(EDC_INT_CAUSE_A, idx); |
4170 | cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx); | |
822dd8a8 HS |
4171 | } else if (idx == MEM_MC) { |
4172 | if (is_t4(adapter->params.chip)) { | |
89c3a86c HS |
4173 | addr = MC_INT_CAUSE_A; |
4174 | cnt_addr = MC_ECC_STATUS_A; | |
822dd8a8 | 4175 | } else { |
89c3a86c HS |
4176 | addr = MC_P_INT_CAUSE_A; |
4177 | cnt_addr = MC_P_ECC_STATUS_A; | |
822dd8a8 | 4178 | } |
56d36be4 | 4179 | } else { |
89c3a86c HS |
4180 | addr = MC_REG(MC_P_INT_CAUSE_A, 1); |
4181 | cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1); | |
56d36be4 DM |
4182 | } |
4183 | ||
4184 | v = t4_read_reg(adapter, addr) & MEM_INT_MASK; | |
89c3a86c | 4185 | if (v & PERR_INT_CAUSE_F) |
56d36be4 DM |
4186 | dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", |
4187 | name[idx]); | |
89c3a86c HS |
4188 | if (v & ECC_CE_INT_CAUSE_F) { |
4189 | u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr)); | |
56d36be4 | 4190 | |
bf8ebb67 HS |
4191 | t4_edc_err_read(adapter, idx); |
4192 | ||
89c3a86c | 4193 | t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M)); |
56d36be4 DM |
4194 | if (printk_ratelimit()) |
4195 | dev_warn(adapter->pdev_dev, | |
4196 | "%u %s correctable ECC data error%s\n", | |
4197 | cnt, name[idx], cnt > 1 ? "s" : ""); | |
4198 | } | |
89c3a86c | 4199 | if (v & ECC_UE_INT_CAUSE_F) |
56d36be4 DM |
4200 | dev_alert(adapter->pdev_dev, |
4201 | "%s uncorrectable ECC data error\n", name[idx]); | |
4202 | ||
4203 | t4_write_reg(adapter, addr, v); | |
89c3a86c | 4204 | if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F)) |
56d36be4 DM |
4205 | t4_fatal_err(adapter); |
4206 | } | |
4207 | ||
4208 | /* | |
4209 | * MA interrupt handler. | |
4210 | */ | |
4211 | static void ma_intr_handler(struct adapter *adap) | |
4212 | { | |
89c3a86c | 4213 | u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); |
56d36be4 | 4214 | |
89c3a86c | 4215 | if (status & MEM_PERR_INT_CAUSE_F) { |
56d36be4 DM |
4216 | dev_alert(adap->pdev_dev, |
4217 | "MA parity error, parity status %#x\n", | |
89c3a86c | 4218 | t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); |
9bb59b96 HS |
4219 | if (is_t5(adap->params.chip)) |
4220 | dev_alert(adap->pdev_dev, | |
4221 | "MA parity error, parity status %#x\n", | |
4222 | t4_read_reg(adap, | |
89c3a86c | 4223 | MA_PARITY_ERROR_STATUS2_A)); |
9bb59b96 | 4224 | } |
89c3a86c HS |
4225 | if (status & MEM_WRAP_INT_CAUSE_F) { |
4226 | v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); | |
56d36be4 DM |
4227 | dev_alert(adap->pdev_dev, "MA address wrap-around error by " |
4228 | "client %u to address %#x\n", | |
89c3a86c HS |
4229 | MEM_WRAP_CLIENT_NUM_G(v), |
4230 | MEM_WRAP_ADDRESS_G(v) << 4); | |
56d36be4 | 4231 | } |
89c3a86c | 4232 | t4_write_reg(adap, MA_INT_CAUSE_A, status); |
56d36be4 DM |
4233 | t4_fatal_err(adap); |
4234 | } | |
4235 | ||
4236 | /* | |
4237 | * SMB interrupt handler. | |
4238 | */ | |
4239 | static void smb_intr_handler(struct adapter *adap) | |
4240 | { | |
005b5717 | 4241 | static const struct intr_info smb_intr_info[] = { |
0d804338 HS |
4242 | { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, |
4243 | { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, | |
4244 | { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, | |
56d36be4 DM |
4245 | { 0 } |
4246 | }; | |
4247 | ||
0d804338 | 4248 | if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) |
56d36be4 DM |
4249 | t4_fatal_err(adap); |
4250 | } | |
4251 | ||
4252 | /* | |
4253 | * NC-SI interrupt handler. | |
4254 | */ | |
4255 | static void ncsi_intr_handler(struct adapter *adap) | |
4256 | { | |
005b5717 | 4257 | static const struct intr_info ncsi_intr_info[] = { |
0d804338 HS |
4258 | { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, |
4259 | { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, | |
4260 | { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, | |
4261 | { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, | |
56d36be4 DM |
4262 | { 0 } |
4263 | }; | |
4264 | ||
0d804338 | 4265 | if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) |
56d36be4 DM |
4266 | t4_fatal_err(adap); |
4267 | } | |
4268 | ||
4269 | /* | |
4270 | * XGMAC interrupt handler. | |
4271 | */ | |
4272 | static void xgmac_intr_handler(struct adapter *adap, int port) | |
4273 | { | |
0a57a536 SR |
4274 | u32 v, int_cause_reg; |
4275 | ||
d14807dd | 4276 | if (is_t4(adap->params.chip)) |
0d804338 | 4277 | int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A); |
0a57a536 | 4278 | else |
0d804338 | 4279 | int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A); |
0a57a536 SR |
4280 | |
4281 | v = t4_read_reg(adap, int_cause_reg); | |
56d36be4 | 4282 | |
0d804338 | 4283 | v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; |
56d36be4 DM |
4284 | if (!v) |
4285 | return; | |
4286 | ||
0d804338 | 4287 | if (v & TXFIFO_PRTY_ERR_F) |
56d36be4 DM |
4288 | dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", |
4289 | port); | |
0d804338 | 4290 | if (v & RXFIFO_PRTY_ERR_F) |
56d36be4 DM |
4291 | dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", |
4292 | port); | |
0d804338 | 4293 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); |
56d36be4 DM |
4294 | t4_fatal_err(adap); |
4295 | } | |
4296 | ||
4297 | /* | |
4298 | * PL interrupt handler. | |
4299 | */ | |
4300 | static void pl_intr_handler(struct adapter *adap) | |
4301 | { | |
005b5717 | 4302 | static const struct intr_info pl_intr_info[] = { |
0d804338 HS |
4303 | { FATALPERR_F, "T4 fatal parity error", -1, 1 }, |
4304 | { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, | |
56d36be4 DM |
4305 | { 0 } |
4306 | }; | |
4307 | ||
0d804338 | 4308 | if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) |
56d36be4 DM |
4309 | t4_fatal_err(adap); |
4310 | } | |
4311 | ||
0d804338 HS |
4312 | #define PF_INTR_MASK (PFSW_F) |
4313 | #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \ | |
4314 | EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \ | |
4315 | CPL_SWITCH_F | SGE_F | ULP_TX_F) | |
56d36be4 DM |
4316 | |
4317 | /** | |
4318 | * t4_slow_intr_handler - control path interrupt handler | |
4319 | * @adapter: the adapter | |
4320 | * | |
4321 | * T4 interrupt handler for non-data global interrupt events, e.g., errors. | |
4322 | * The designation 'slow' is because it involves register reads, while | |
4323 | * data interrupts typically don't involve any MMIOs. | |
4324 | */ | |
4325 | int t4_slow_intr_handler(struct adapter *adapter) | |
4326 | { | |
0d804338 | 4327 | u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A); |
56d36be4 DM |
4328 | |
4329 | if (!(cause & GLBL_INTR_MASK)) | |
4330 | return 0; | |
0d804338 | 4331 | if (cause & CIM_F) |
56d36be4 | 4332 | cim_intr_handler(adapter); |
0d804338 | 4333 | if (cause & MPS_F) |
56d36be4 | 4334 | mps_intr_handler(adapter); |
0d804338 | 4335 | if (cause & NCSI_F) |
56d36be4 | 4336 | ncsi_intr_handler(adapter); |
0d804338 | 4337 | if (cause & PL_F) |
56d36be4 | 4338 | pl_intr_handler(adapter); |
0d804338 | 4339 | if (cause & SMB_F) |
56d36be4 | 4340 | smb_intr_handler(adapter); |
0d804338 | 4341 | if (cause & XGMAC0_F) |
56d36be4 | 4342 | xgmac_intr_handler(adapter, 0); |
0d804338 | 4343 | if (cause & XGMAC1_F) |
56d36be4 | 4344 | xgmac_intr_handler(adapter, 1); |
0d804338 | 4345 | if (cause & XGMAC_KR0_F) |
56d36be4 | 4346 | xgmac_intr_handler(adapter, 2); |
0d804338 | 4347 | if (cause & XGMAC_KR1_F) |
56d36be4 | 4348 | xgmac_intr_handler(adapter, 3); |
0d804338 | 4349 | if (cause & PCIE_F) |
56d36be4 | 4350 | pcie_intr_handler(adapter); |
0d804338 | 4351 | if (cause & MC_F) |
56d36be4 | 4352 | mem_intr_handler(adapter, MEM_MC); |
3ccc6cf7 | 4353 | if (is_t5(adapter->params.chip) && (cause & MC1_F)) |
822dd8a8 | 4354 | mem_intr_handler(adapter, MEM_MC1); |
0d804338 | 4355 | if (cause & EDC0_F) |
56d36be4 | 4356 | mem_intr_handler(adapter, MEM_EDC0); |
0d804338 | 4357 | if (cause & EDC1_F) |
56d36be4 | 4358 | mem_intr_handler(adapter, MEM_EDC1); |
0d804338 | 4359 | if (cause & LE_F) |
56d36be4 | 4360 | le_intr_handler(adapter); |
0d804338 | 4361 | if (cause & TP_F) |
56d36be4 | 4362 | tp_intr_handler(adapter); |
0d804338 | 4363 | if (cause & MA_F) |
56d36be4 | 4364 | ma_intr_handler(adapter); |
0d804338 | 4365 | if (cause & PM_TX_F) |
56d36be4 | 4366 | pmtx_intr_handler(adapter); |
0d804338 | 4367 | if (cause & PM_RX_F) |
56d36be4 | 4368 | pmrx_intr_handler(adapter); |
0d804338 | 4369 | if (cause & ULP_RX_F) |
56d36be4 | 4370 | ulprx_intr_handler(adapter); |
0d804338 | 4371 | if (cause & CPL_SWITCH_F) |
56d36be4 | 4372 | cplsw_intr_handler(adapter); |
0d804338 | 4373 | if (cause & SGE_F) |
56d36be4 | 4374 | sge_intr_handler(adapter); |
0d804338 | 4375 | if (cause & ULP_TX_F) |
56d36be4 DM |
4376 | ulptx_intr_handler(adapter); |
4377 | ||
4378 | /* Clear the interrupts just processed for which we are the master. */ | |
0d804338 HS |
4379 | t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK); |
4380 | (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */ | |
56d36be4 DM |
4381 | return 1; |
4382 | } | |
4383 | ||
4384 | /** | |
4385 | * t4_intr_enable - enable interrupts | |
4386 | * @adapter: the adapter whose interrupts should be enabled | |
4387 | * | |
4388 | * Enable PF-specific interrupts for the calling function and the top-level | |
4389 | * interrupt concentrator for global interrupts. Interrupts are already | |
4390 | * enabled at each module, here we just enable the roots of the interrupt | |
4391 | * hierarchies. | |
4392 | * | |
4393 | * Note: this function should be called only when the driver manages | |
4394 | * non PF-specific interrupts from the various HW modules. Only one PCI | |
4395 | * function at a time should be doing this. | |
4396 | */ | |
4397 | void t4_intr_enable(struct adapter *adapter) | |
4398 | { | |
3ccc6cf7 | 4399 | u32 val = 0; |
d86bd29e HS |
4400 | u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); |
4401 | u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? | |
4402 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
56d36be4 | 4403 | |
3ccc6cf7 HS |
4404 | if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) |
4405 | val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F; | |
f612b815 HS |
4406 | t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | |
4407 | ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | | |
3ccc6cf7 | 4408 | ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F | |
f612b815 HS |
4409 | ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | |
4410 | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | | |
4411 | ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | | |
3ccc6cf7 | 4412 | DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val); |
0d804338 HS |
4413 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); |
4414 | t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf); | |
56d36be4 DM |
4415 | } |
4416 | ||
4417 | /** | |
4418 | * t4_intr_disable - disable interrupts | |
4419 | * @adapter: the adapter whose interrupts should be disabled | |
4420 | * | |
4421 | * Disable interrupts. We only disable the top-level interrupt | |
4422 | * concentrators. The caller must be a PCI function managing global | |
4423 | * interrupts. | |
4424 | */ | |
4425 | void t4_intr_disable(struct adapter *adapter) | |
4426 | { | |
d86bd29e HS |
4427 | u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); |
4428 | u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? | |
4429 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
56d36be4 | 4430 | |
0d804338 HS |
4431 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0); |
4432 | t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0); | |
56d36be4 DM |
4433 | } |
4434 | ||
56d36be4 DM |
4435 | /** |
4436 | * hash_mac_addr - return the hash value of a MAC address | |
4437 | * @addr: the 48-bit Ethernet MAC address | |
4438 | * | |
4439 | * Hashes a MAC address according to the hash function used by HW inexact | |
4440 | * (hash) address matching. | |
4441 | */ | |
4442 | static int hash_mac_addr(const u8 *addr) | |
4443 | { | |
4444 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | |
4445 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | |
4446 | a ^= b; | |
4447 | a ^= (a >> 12); | |
4448 | a ^= (a >> 6); | |
4449 | return a & 0x3f; | |
4450 | } | |
4451 | ||
4452 | /** | |
4453 | * t4_config_rss_range - configure a portion of the RSS mapping table | |
4454 | * @adapter: the adapter | |
4455 | * @mbox: mbox to use for the FW command | |
4456 | * @viid: virtual interface whose RSS subtable is to be written | |
4457 | * @start: start entry in the table to write | |
4458 | * @n: how many table entries to write | |
4459 | * @rspq: values for the response queue lookup table | |
4460 | * @nrspq: number of values in @rspq | |
4461 | * | |
4462 | * Programs the selected part of the VI's RSS mapping table with the | |
4463 | * provided values. If @nrspq < @n the supplied values are used repeatedly | |
4464 | * until the full table range is populated. | |
4465 | * | |
4466 | * The caller must ensure the values in @rspq are in the range allowed for | |
4467 | * @viid. | |
4468 | */ | |
4469 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, | |
4470 | int start, int n, const u16 *rspq, unsigned int nrspq) | |
4471 | { | |
4472 | int ret; | |
4473 | const u16 *rsp = rspq; | |
4474 | const u16 *rsp_end = rspq + nrspq; | |
4475 | struct fw_rss_ind_tbl_cmd cmd; | |
4476 | ||
4477 | memset(&cmd, 0, sizeof(cmd)); | |
f404f80c | 4478 | cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) | |
e2ac9628 | 4479 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | |
b2e1a3f0 | 4480 | FW_RSS_IND_TBL_CMD_VIID_V(viid)); |
f404f80c | 4481 | cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); |
56d36be4 DM |
4482 | |
4483 | /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ | |
4484 | while (n > 0) { | |
4485 | int nq = min(n, 32); | |
4486 | __be32 *qp = &cmd.iq0_to_iq2; | |
4487 | ||
f404f80c HS |
4488 | cmd.niqid = cpu_to_be16(nq); |
4489 | cmd.startidx = cpu_to_be16(start); | |
56d36be4 DM |
4490 | |
4491 | start += nq; | |
4492 | n -= nq; | |
4493 | ||
4494 | while (nq > 0) { | |
4495 | unsigned int v; | |
4496 | ||
b2e1a3f0 | 4497 | v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp); |
56d36be4 DM |
4498 | if (++rsp >= rsp_end) |
4499 | rsp = rspq; | |
b2e1a3f0 | 4500 | v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp); |
56d36be4 DM |
4501 | if (++rsp >= rsp_end) |
4502 | rsp = rspq; | |
b2e1a3f0 | 4503 | v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp); |
56d36be4 DM |
4504 | if (++rsp >= rsp_end) |
4505 | rsp = rspq; | |
4506 | ||
f404f80c | 4507 | *qp++ = cpu_to_be32(v); |
56d36be4 DM |
4508 | nq -= 3; |
4509 | } | |
4510 | ||
4511 | ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); | |
4512 | if (ret) | |
4513 | return ret; | |
4514 | } | |
4515 | return 0; | |
4516 | } | |
4517 | ||
4518 | /** | |
4519 | * t4_config_glbl_rss - configure the global RSS mode | |
4520 | * @adapter: the adapter | |
4521 | * @mbox: mbox to use for the FW command | |
4522 | * @mode: global RSS mode | |
4523 | * @flags: mode-specific flags | |
4524 | * | |
4525 | * Sets the global RSS mode. | |
4526 | */ | |
4527 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
4528 | unsigned int flags) | |
4529 | { | |
4530 | struct fw_rss_glb_config_cmd c; | |
4531 | ||
4532 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
4533 | c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) | |
4534 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
4535 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
56d36be4 | 4536 | if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { |
f404f80c HS |
4537 | c.u.manual.mode_pkd = |
4538 | cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); | |
56d36be4 DM |
4539 | } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { |
4540 | c.u.basicvirtual.mode_pkd = | |
f404f80c HS |
4541 | cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); |
4542 | c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); | |
56d36be4 DM |
4543 | } else |
4544 | return -EINVAL; | |
4545 | return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); | |
4546 | } | |
4547 | ||
c035e183 HS |
4548 | /** |
4549 | * t4_config_vi_rss - configure per VI RSS settings | |
4550 | * @adapter: the adapter | |
4551 | * @mbox: mbox to use for the FW command | |
4552 | * @viid: the VI id | |
4553 | * @flags: RSS flags | |
4554 | * @defq: id of the default RSS queue for the VI. | |
4555 | * | |
4556 | * Configures VI-specific RSS properties. | |
4557 | */ | |
4558 | int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, | |
4559 | unsigned int flags, unsigned int defq) | |
4560 | { | |
4561 | struct fw_rss_vi_config_cmd c; | |
4562 | ||
4563 | memset(&c, 0, sizeof(c)); | |
4564 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | | |
4565 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
4566 | FW_RSS_VI_CONFIG_CMD_VIID_V(viid)); | |
4567 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
4568 | c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | | |
4569 | FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq)); | |
4570 | return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); | |
4571 | } | |
4572 | ||
688ea5fe HS |
4573 | /* Read an RSS table row */ |
4574 | static int rd_rss_row(struct adapter *adap, int row, u32 *val) | |
4575 | { | |
4576 | t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); | |
4577 | return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, | |
4578 | 5, 0, val); | |
4579 | } | |
4580 | ||
4581 | /** | |
4582 | * t4_read_rss - read the contents of the RSS mapping table | |
4583 | * @adapter: the adapter | |
4584 | * @map: holds the contents of the RSS mapping table | |
4585 | * | |
4586 | * Reads the contents of the RSS hash->queue mapping table. | |
4587 | */ | |
4588 | int t4_read_rss(struct adapter *adapter, u16 *map) | |
4589 | { | |
4590 | u32 val; | |
4591 | int i, ret; | |
4592 | ||
4593 | for (i = 0; i < RSS_NENTRIES / 2; ++i) { | |
4594 | ret = rd_rss_row(adapter, i, &val); | |
4595 | if (ret) | |
4596 | return ret; | |
4597 | *map++ = LKPTBLQUEUE0_G(val); | |
4598 | *map++ = LKPTBLQUEUE1_G(val); | |
4599 | } | |
4600 | return 0; | |
4601 | } | |
4602 | ||
0b2c2a93 HS |
4603 | static unsigned int t4_use_ldst(struct adapter *adap) |
4604 | { | |
4605 | return (adap->flags & FW_OK) || !adap->use_bd; | |
4606 | } | |
4607 | ||
c1e9af0c HS |
4608 | /** |
4609 | * t4_fw_tp_pio_rw - Access TP PIO through LDST | |
4610 | * @adap: the adapter | |
4611 | * @vals: where the indirect register values are stored/written | |
4612 | * @nregs: how many indirect registers to read/write | |
4613 | * @start_idx: index of first indirect register to read/write | |
4614 | * @rw: Read (1) or Write (0) | |
4615 | * | |
4616 | * Access TP PIO registers through LDST | |
4617 | */ | |
4618 | static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, | |
4619 | unsigned int start_index, unsigned int rw) | |
4620 | { | |
4621 | int ret, i; | |
4622 | int cmd = FW_LDST_ADDRSPC_TP_PIO; | |
4623 | struct fw_ldst_cmd c; | |
4624 | ||
4625 | for (i = 0 ; i < nregs; i++) { | |
4626 | memset(&c, 0, sizeof(c)); | |
4627 | c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
4628 | FW_CMD_REQUEST_F | | |
4629 | (rw ? FW_CMD_READ_F : | |
4630 | FW_CMD_WRITE_F) | | |
4631 | FW_LDST_CMD_ADDRSPACE_V(cmd)); | |
4632 | c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); | |
4633 | ||
4634 | c.u.addrval.addr = cpu_to_be32(start_index + i); | |
4635 | c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); | |
4636 | ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); | |
4637 | if (!ret && rw) | |
4638 | vals[i] = be32_to_cpu(c.u.addrval.val); | |
4639 | } | |
4640 | } | |
4641 | ||
688ea5fe HS |
4642 | /** |
4643 | * t4_read_rss_key - read the global RSS key | |
4644 | * @adap: the adapter | |
4645 | * @key: 10-entry array holding the 320-bit RSS key | |
4646 | * | |
4647 | * Reads the global 320-bit RSS key. | |
4648 | */ | |
4649 | void t4_read_rss_key(struct adapter *adap, u32 *key) | |
4650 | { | |
0b2c2a93 | 4651 | if (t4_use_ldst(adap)) |
c1e9af0c HS |
4652 | t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1); |
4653 | else | |
4654 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, | |
4655 | TP_RSS_SECRET_KEY0_A); | |
688ea5fe HS |
4656 | } |
4657 | ||
4658 | /** | |
4659 | * t4_write_rss_key - program one of the RSS keys | |
4660 | * @adap: the adapter | |
4661 | * @key: 10-entry array holding the 320-bit RSS key | |
4662 | * @idx: which RSS key to write | |
4663 | * | |
4664 | * Writes one of the RSS keys with the given 320-bit value. If @idx is | |
4665 | * 0..15 the corresponding entry in the RSS key table is written, | |
4666 | * otherwise the global RSS key is written. | |
4667 | */ | |
4668 | void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) | |
4669 | { | |
3ccc6cf7 HS |
4670 | u8 rss_key_addr_cnt = 16; |
4671 | u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); | |
4672 | ||
4673 | /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble), | |
4674 | * allows access to key addresses 16-63 by using KeyWrAddrX | |
4675 | * as index[5:4](upper 2) into key table | |
4676 | */ | |
4677 | if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && | |
4678 | (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3)) | |
4679 | rss_key_addr_cnt = 32; | |
4680 | ||
0b2c2a93 | 4681 | if (t4_use_ldst(adap)) |
c1e9af0c HS |
4682 | t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0); |
4683 | else | |
4684 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, | |
4685 | TP_RSS_SECRET_KEY0_A); | |
3ccc6cf7 HS |
4686 | |
4687 | if (idx >= 0 && idx < rss_key_addr_cnt) { | |
4688 | if (rss_key_addr_cnt > 16) | |
4689 | t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, | |
4690 | KEYWRADDRX_V(idx >> 4) | | |
4691 | T6_VFWRADDR_V(idx) | KEYWREN_F); | |
4692 | else | |
4693 | t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, | |
4694 | KEYWRADDR_V(idx) | KEYWREN_F); | |
4695 | } | |
688ea5fe HS |
4696 | } |
4697 | ||
4698 | /** | |
4699 | * t4_read_rss_pf_config - read PF RSS Configuration Table | |
4700 | * @adapter: the adapter | |
4701 | * @index: the entry in the PF RSS table to read | |
4702 | * @valp: where to store the returned value | |
4703 | * | |
4704 | * Reads the PF RSS Configuration Table at the specified index and returns | |
4705 | * the value found there. | |
4706 | */ | |
4707 | void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, | |
4708 | u32 *valp) | |
4709 | { | |
0b2c2a93 | 4710 | if (t4_use_ldst(adapter)) |
c1e9af0c HS |
4711 | t4_fw_tp_pio_rw(adapter, valp, 1, |
4712 | TP_RSS_PF0_CONFIG_A + index, 1); | |
4713 | else | |
4714 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
4715 | valp, 1, TP_RSS_PF0_CONFIG_A + index); | |
688ea5fe HS |
4716 | } |
4717 | ||
4718 | /** | |
4719 | * t4_read_rss_vf_config - read VF RSS Configuration Table | |
4720 | * @adapter: the adapter | |
4721 | * @index: the entry in the VF RSS table to read | |
4722 | * @vfl: where to store the returned VFL | |
4723 | * @vfh: where to store the returned VFH | |
4724 | * | |
4725 | * Reads the VF RSS Configuration Table at the specified index and returns | |
4726 | * the (VFL, VFH) values found there. | |
4727 | */ | |
4728 | void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, | |
4729 | u32 *vfl, u32 *vfh) | |
4730 | { | |
4731 | u32 vrt, mask, data; | |
4732 | ||
3ccc6cf7 HS |
4733 | if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { |
4734 | mask = VFWRADDR_V(VFWRADDR_M); | |
4735 | data = VFWRADDR_V(index); | |
4736 | } else { | |
4737 | mask = T6_VFWRADDR_V(T6_VFWRADDR_M); | |
4738 | data = T6_VFWRADDR_V(index); | |
4739 | } | |
688ea5fe HS |
4740 | |
4741 | /* Request that the index'th VF Table values be read into VFL/VFH. | |
4742 | */ | |
4743 | vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); | |
4744 | vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask); | |
4745 | vrt |= data | VFRDEN_F; | |
4746 | t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt); | |
4747 | ||
4748 | /* Grab the VFL/VFH values ... | |
4749 | */ | |
0b2c2a93 | 4750 | if (t4_use_ldst(adapter)) { |
c1e9af0c HS |
4751 | t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1); |
4752 | t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1); | |
4753 | } else { | |
4754 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
4755 | vfl, 1, TP_RSS_VFL_CONFIG_A); | |
4756 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
4757 | vfh, 1, TP_RSS_VFH_CONFIG_A); | |
4758 | } | |
688ea5fe HS |
4759 | } |
4760 | ||
4761 | /** | |
4762 | * t4_read_rss_pf_map - read PF RSS Map | |
4763 | * @adapter: the adapter | |
4764 | * | |
4765 | * Reads the PF RSS Map register and returns its value. | |
4766 | */ | |
4767 | u32 t4_read_rss_pf_map(struct adapter *adapter) | |
4768 | { | |
4769 | u32 pfmap; | |
4770 | ||
0b2c2a93 | 4771 | if (t4_use_ldst(adapter)) |
c1e9af0c HS |
4772 | t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1); |
4773 | else | |
4774 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
4775 | &pfmap, 1, TP_RSS_PF_MAP_A); | |
688ea5fe HS |
4776 | return pfmap; |
4777 | } | |
4778 | ||
4779 | /** | |
4780 | * t4_read_rss_pf_mask - read PF RSS Mask | |
4781 | * @adapter: the adapter | |
4782 | * | |
4783 | * Reads the PF RSS Mask register and returns its value. | |
4784 | */ | |
4785 | u32 t4_read_rss_pf_mask(struct adapter *adapter) | |
4786 | { | |
4787 | u32 pfmask; | |
4788 | ||
0b2c2a93 | 4789 | if (t4_use_ldst(adapter)) |
c1e9af0c HS |
4790 | t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1); |
4791 | else | |
4792 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
4793 | &pfmask, 1, TP_RSS_PF_MSK_A); | |
688ea5fe HS |
4794 | return pfmask; |
4795 | } | |
4796 | ||
56d36be4 DM |
4797 | /** |
4798 | * t4_tp_get_tcp_stats - read TP's TCP MIB counters | |
4799 | * @adap: the adapter | |
4800 | * @v4: holds the TCP/IP counter values | |
4801 | * @v6: holds the TCP/IPv6 counter values | |
4802 | * | |
4803 | * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. | |
4804 | * Either @v4 or @v6 may be %NULL to skip the corresponding stats. | |
4805 | */ | |
4806 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, | |
4807 | struct tp_tcp_stats *v6) | |
4808 | { | |
837e4a42 | 4809 | u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; |
56d36be4 | 4810 | |
837e4a42 | 4811 | #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) |
56d36be4 DM |
4812 | #define STAT(x) val[STAT_IDX(x)] |
4813 | #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) | |
4814 | ||
4815 | if (v4) { | |
837e4a42 HS |
4816 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, |
4817 | ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A); | |
a4cfd929 HS |
4818 | v4->tcp_out_rsts = STAT(OUT_RST); |
4819 | v4->tcp_in_segs = STAT64(IN_SEG); | |
4820 | v4->tcp_out_segs = STAT64(OUT_SEG); | |
4821 | v4->tcp_retrans_segs = STAT64(RXT_SEG); | |
56d36be4 DM |
4822 | } |
4823 | if (v6) { | |
837e4a42 HS |
4824 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, |
4825 | ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A); | |
a4cfd929 HS |
4826 | v6->tcp_out_rsts = STAT(OUT_RST); |
4827 | v6->tcp_in_segs = STAT64(IN_SEG); | |
4828 | v6->tcp_out_segs = STAT64(OUT_SEG); | |
4829 | v6->tcp_retrans_segs = STAT64(RXT_SEG); | |
56d36be4 DM |
4830 | } |
4831 | #undef STAT64 | |
4832 | #undef STAT | |
4833 | #undef STAT_IDX | |
4834 | } | |
4835 | ||
a4cfd929 HS |
4836 | /** |
4837 | * t4_tp_get_err_stats - read TP's error MIB counters | |
4838 | * @adap: the adapter | |
4839 | * @st: holds the counter values | |
4840 | * | |
4841 | * Returns the values of TP's error counters. | |
4842 | */ | |
4843 | void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) | |
4844 | { | |
df459ebc HS |
4845 | int nchan = adap->params.arch.nchan; |
4846 | ||
4847 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4848 | st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A); | |
4849 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4850 | st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A); | |
4851 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4852 | st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A); | |
4853 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4854 | st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A); | |
4855 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4856 | st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A); | |
4857 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4858 | st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A); | |
4859 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4860 | st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A); | |
4861 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, | |
4862 | st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A); | |
4863 | ||
a4cfd929 HS |
4864 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, |
4865 | &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A); | |
4866 | } | |
4867 | ||
a6222975 HS |
4868 | /** |
4869 | * t4_tp_get_cpl_stats - read TP's CPL MIB counters | |
4870 | * @adap: the adapter | |
4871 | * @st: holds the counter values | |
4872 | * | |
4873 | * Returns the values of TP's CPL counters. | |
4874 | */ | |
4875 | void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) | |
4876 | { | |
df459ebc HS |
4877 | int nchan = adap->params.arch.nchan; |
4878 | ||
4879 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req, | |
4880 | nchan, TP_MIB_CPL_IN_REQ_0_A); | |
4881 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp, | |
4882 | nchan, TP_MIB_CPL_OUT_RSP_0_A); | |
4883 | ||
a6222975 HS |
4884 | } |
4885 | ||
a4cfd929 HS |
4886 | /** |
4887 | * t4_tp_get_rdma_stats - read TP's RDMA MIB counters | |
4888 | * @adap: the adapter | |
4889 | * @st: holds the counter values | |
4890 | * | |
4891 | * Returns the values of TP's RDMA counters. | |
4892 | */ | |
4893 | void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) | |
4894 | { | |
4895 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt, | |
4896 | 2, TP_MIB_RQE_DFR_PKT_A); | |
4897 | } | |
4898 | ||
a6222975 HS |
4899 | /** |
4900 | * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port | |
4901 | * @adap: the adapter | |
4902 | * @idx: the port index | |
4903 | * @st: holds the counter values | |
4904 | * | |
4905 | * Returns the values of TP's FCoE counters for the selected port. | |
4906 | */ | |
4907 | void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, | |
4908 | struct tp_fcoe_stats *st) | |
4909 | { | |
4910 | u32 val[2]; | |
4911 | ||
4912 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp, | |
4913 | 1, TP_MIB_FCOE_DDP_0_A + idx); | |
4914 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop, | |
4915 | 1, TP_MIB_FCOE_DROP_0_A + idx); | |
4916 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, | |
4917 | 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx); | |
4918 | st->octets_ddp = ((u64)val[0] << 32) | val[1]; | |
4919 | } | |
4920 | ||
a4cfd929 HS |
4921 | /** |
4922 | * t4_get_usm_stats - read TP's non-TCP DDP MIB counters | |
4923 | * @adap: the adapter | |
4924 | * @st: holds the counter values | |
4925 | * | |
4926 | * Returns the values of TP's counters for non-TCP directly-placed packets. | |
4927 | */ | |
4928 | void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) | |
4929 | { | |
4930 | u32 val[4]; | |
4931 | ||
4932 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4, | |
4933 | TP_MIB_USM_PKTS_A); | |
4934 | st->frames = val[0]; | |
4935 | st->drops = val[1]; | |
4936 | st->octets = ((u64)val[2] << 32) | val[3]; | |
4937 | } | |
4938 | ||
56d36be4 DM |
4939 | /** |
4940 | * t4_read_mtu_tbl - returns the values in the HW path MTU table | |
4941 | * @adap: the adapter | |
4942 | * @mtus: where to store the MTU values | |
4943 | * @mtu_log: where to store the MTU base-2 log (may be %NULL) | |
4944 | * | |
4945 | * Reads the HW path MTU table. | |
4946 | */ | |
4947 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) | |
4948 | { | |
4949 | u32 v; | |
4950 | int i; | |
4951 | ||
4952 | for (i = 0; i < NMTUS; ++i) { | |
837e4a42 HS |
4953 | t4_write_reg(adap, TP_MTU_TABLE_A, |
4954 | MTUINDEX_V(0xff) | MTUVALUE_V(i)); | |
4955 | v = t4_read_reg(adap, TP_MTU_TABLE_A); | |
4956 | mtus[i] = MTUVALUE_G(v); | |
56d36be4 | 4957 | if (mtu_log) |
837e4a42 | 4958 | mtu_log[i] = MTUWIDTH_G(v); |
56d36be4 DM |
4959 | } |
4960 | } | |
4961 | ||
bad43792 HS |
4962 | /** |
4963 | * t4_read_cong_tbl - reads the congestion control table | |
4964 | * @adap: the adapter | |
4965 | * @incr: where to store the alpha values | |
4966 | * | |
4967 | * Reads the additive increments programmed into the HW congestion | |
4968 | * control table. | |
4969 | */ | |
4970 | void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) | |
4971 | { | |
4972 | unsigned int mtu, w; | |
4973 | ||
4974 | for (mtu = 0; mtu < NMTUS; ++mtu) | |
4975 | for (w = 0; w < NCCTRL_WIN; ++w) { | |
4976 | t4_write_reg(adap, TP_CCTRL_TABLE_A, | |
4977 | ROWINDEX_V(0xffff) | (mtu << 5) | w); | |
4978 | incr[mtu][w] = (u16)t4_read_reg(adap, | |
4979 | TP_CCTRL_TABLE_A) & 0x1fff; | |
4980 | } | |
4981 | } | |
4982 | ||
636f9d37 VP |
4983 | /** |
4984 | * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register | |
4985 | * @adap: the adapter | |
4986 | * @addr: the indirect TP register address | |
4987 | * @mask: specifies the field within the register to modify | |
4988 | * @val: new value for the field | |
4989 | * | |
4990 | * Sets a field of an indirect TP register to the given value. | |
4991 | */ | |
4992 | void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, | |
4993 | unsigned int mask, unsigned int val) | |
4994 | { | |
837e4a42 HS |
4995 | t4_write_reg(adap, TP_PIO_ADDR_A, addr); |
4996 | val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; | |
4997 | t4_write_reg(adap, TP_PIO_DATA_A, val); | |
636f9d37 VP |
4998 | } |
4999 | ||
56d36be4 DM |
5000 | /** |
5001 | * init_cong_ctrl - initialize congestion control parameters | |
5002 | * @a: the alpha values for congestion control | |
5003 | * @b: the beta values for congestion control | |
5004 | * | |
5005 | * Initialize the congestion control parameters. | |
5006 | */ | |
91744948 | 5007 | static void init_cong_ctrl(unsigned short *a, unsigned short *b) |
56d36be4 DM |
5008 | { |
5009 | a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; | |
5010 | a[9] = 2; | |
5011 | a[10] = 3; | |
5012 | a[11] = 4; | |
5013 | a[12] = 5; | |
5014 | a[13] = 6; | |
5015 | a[14] = 7; | |
5016 | a[15] = 8; | |
5017 | a[16] = 9; | |
5018 | a[17] = 10; | |
5019 | a[18] = 14; | |
5020 | a[19] = 17; | |
5021 | a[20] = 21; | |
5022 | a[21] = 25; | |
5023 | a[22] = 30; | |
5024 | a[23] = 35; | |
5025 | a[24] = 45; | |
5026 | a[25] = 60; | |
5027 | a[26] = 80; | |
5028 | a[27] = 100; | |
5029 | a[28] = 200; | |
5030 | a[29] = 300; | |
5031 | a[30] = 400; | |
5032 | a[31] = 500; | |
5033 | ||
5034 | b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; | |
5035 | b[9] = b[10] = 1; | |
5036 | b[11] = b[12] = 2; | |
5037 | b[13] = b[14] = b[15] = b[16] = 3; | |
5038 | b[17] = b[18] = b[19] = b[20] = b[21] = 4; | |
5039 | b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; | |
5040 | b[28] = b[29] = 6; | |
5041 | b[30] = b[31] = 7; | |
5042 | } | |
5043 | ||
5044 | /* The minimum additive increment value for the congestion control table */ | |
5045 | #define CC_MIN_INCR 2U | |
5046 | ||
5047 | /** | |
5048 | * t4_load_mtus - write the MTU and congestion control HW tables | |
5049 | * @adap: the adapter | |
5050 | * @mtus: the values for the MTU table | |
5051 | * @alpha: the values for the congestion control alpha parameter | |
5052 | * @beta: the values for the congestion control beta parameter | |
5053 | * | |
5054 | * Write the HW MTU table with the supplied MTUs and the high-speed | |
5055 | * congestion control table with the supplied alpha, beta, and MTUs. | |
5056 | * We write the two tables together because the additive increments | |
5057 | * depend on the MTUs. | |
5058 | */ | |
5059 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | |
5060 | const unsigned short *alpha, const unsigned short *beta) | |
5061 | { | |
5062 | static const unsigned int avg_pkts[NCCTRL_WIN] = { | |
5063 | 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, | |
5064 | 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, | |
5065 | 28672, 40960, 57344, 81920, 114688, 163840, 229376 | |
5066 | }; | |
5067 | ||
5068 | unsigned int i, w; | |
5069 | ||
5070 | for (i = 0; i < NMTUS; ++i) { | |
5071 | unsigned int mtu = mtus[i]; | |
5072 | unsigned int log2 = fls(mtu); | |
5073 | ||
5074 | if (!(mtu & ((1 << log2) >> 2))) /* round */ | |
5075 | log2--; | |
837e4a42 HS |
5076 | t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | |
5077 | MTUWIDTH_V(log2) | MTUVALUE_V(mtu)); | |
56d36be4 DM |
5078 | |
5079 | for (w = 0; w < NCCTRL_WIN; ++w) { | |
5080 | unsigned int inc; | |
5081 | ||
5082 | inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], | |
5083 | CC_MIN_INCR); | |
5084 | ||
837e4a42 | 5085 | t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | |
56d36be4 DM |
5086 | (w << 16) | (beta[w] << 13) | inc); |
5087 | } | |
5088 | } | |
5089 | } | |
5090 | ||
7864026b HS |
5091 | /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core |
5092 | * clocks. The formula is | |
5093 | * | |
5094 | * bytes/s = bytes256 * 256 * ClkFreq / 4096 | |
5095 | * | |
5096 | * which is equivalent to | |
5097 | * | |
5098 | * bytes/s = 62.5 * bytes256 * ClkFreq_ms | |
5099 | */ | |
5100 | static u64 chan_rate(struct adapter *adap, unsigned int bytes256) | |
5101 | { | |
5102 | u64 v = bytes256 * adap->params.vpd.cclk; | |
5103 | ||
5104 | return v * 62 + v / 2; | |
5105 | } | |
5106 | ||
5107 | /** | |
5108 | * t4_get_chan_txrate - get the current per channel Tx rates | |
5109 | * @adap: the adapter | |
5110 | * @nic_rate: rates for NIC traffic | |
5111 | * @ofld_rate: rates for offloaded traffic | |
5112 | * | |
5113 | * Return the current Tx rates in bytes/s for NIC and offloaded traffic | |
5114 | * for each channel. | |
5115 | */ | |
5116 | void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) | |
5117 | { | |
5118 | u32 v; | |
5119 | ||
5120 | v = t4_read_reg(adap, TP_TX_TRATE_A); | |
5121 | nic_rate[0] = chan_rate(adap, TNLRATE0_G(v)); | |
5122 | nic_rate[1] = chan_rate(adap, TNLRATE1_G(v)); | |
5123 | if (adap->params.arch.nchan == NCHAN) { | |
5124 | nic_rate[2] = chan_rate(adap, TNLRATE2_G(v)); | |
5125 | nic_rate[3] = chan_rate(adap, TNLRATE3_G(v)); | |
5126 | } | |
5127 | ||
5128 | v = t4_read_reg(adap, TP_TX_ORATE_A); | |
5129 | ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v)); | |
5130 | ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v)); | |
5131 | if (adap->params.arch.nchan == NCHAN) { | |
5132 | ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v)); | |
5133 | ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v)); | |
5134 | } | |
5135 | } | |
5136 | ||
8e3d04fd HS |
5137 | /** |
5138 | * t4_set_trace_filter - configure one of the tracing filters | |
5139 | * @adap: the adapter | |
5140 | * @tp: the desired trace filter parameters | |
5141 | * @idx: which filter to configure | |
5142 | * @enable: whether to enable or disable the filter | |
5143 | * | |
5144 | * Configures one of the tracing filters available in HW. If @enable is | |
5145 | * %0 @tp is not examined and may be %NULL. The user is responsible to | |
5146 | * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register | |
5147 | */ | |
5148 | int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, | |
5149 | int idx, int enable) | |
5150 | { | |
5151 | int i, ofst = idx * 4; | |
5152 | u32 data_reg, mask_reg, cfg; | |
5153 | u32 multitrc = TRCMULTIFILTER_F; | |
5154 | ||
5155 | if (!enable) { | |
5156 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); | |
5157 | return 0; | |
5158 | } | |
5159 | ||
5160 | cfg = t4_read_reg(adap, MPS_TRC_CFG_A); | |
5161 | if (cfg & TRCMULTIFILTER_F) { | |
5162 | /* If multiple tracers are enabled, then maximum | |
5163 | * capture size is 2.5KB (FIFO size of a single channel) | |
5164 | * minus 2 flits for CPL_TRACE_PKT header. | |
5165 | */ | |
5166 | if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) | |
5167 | return -EINVAL; | |
5168 | } else { | |
5169 | /* If multiple tracers are disabled, to avoid deadlocks | |
5170 | * maximum packet capture size of 9600 bytes is recommended. | |
5171 | * Also in this mode, only trace0 can be enabled and running. | |
5172 | */ | |
5173 | multitrc = 0; | |
5174 | if (tp->snap_len > 9600 || idx) | |
5175 | return -EINVAL; | |
5176 | } | |
5177 | ||
5178 | if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || | |
5179 | tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M || | |
5180 | tp->min_len > TFMINPKTSIZE_M) | |
5181 | return -EINVAL; | |
5182 | ||
5183 | /* stop the tracer we'll be changing */ | |
5184 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); | |
5185 | ||
5186 | idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A); | |
5187 | data_reg = MPS_TRC_FILTER0_MATCH_A + idx; | |
5188 | mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx; | |
5189 | ||
5190 | for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { | |
5191 | t4_write_reg(adap, data_reg, tp->data[i]); | |
5192 | t4_write_reg(adap, mask_reg, ~tp->mask[i]); | |
5193 | } | |
5194 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst, | |
5195 | TFCAPTUREMAX_V(tp->snap_len) | | |
5196 | TFMINPKTSIZE_V(tp->min_len)); | |
5197 | t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, | |
5198 | TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) | | |
5199 | (is_t4(adap->params.chip) ? | |
5200 | TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) : | |
5201 | T5_TFPORT_V(tp->port) | T5_TFEN_F | | |
5202 | T5_TFINVERTMATCH_V(tp->invert))); | |
5203 | ||
5204 | return 0; | |
5205 | } | |
5206 | ||
5207 | /** | |
5208 | * t4_get_trace_filter - query one of the tracing filters | |
5209 | * @adap: the adapter | |
5210 | * @tp: the current trace filter parameters | |
5211 | * @idx: which trace filter to query | |
5212 | * @enabled: non-zero if the filter is enabled | |
5213 | * | |
5214 | * Returns the current settings of one of the HW tracing filters. | |
5215 | */ | |
5216 | void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, | |
5217 | int *enabled) | |
5218 | { | |
5219 | u32 ctla, ctlb; | |
5220 | int i, ofst = idx * 4; | |
5221 | u32 data_reg, mask_reg; | |
5222 | ||
5223 | ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst); | |
5224 | ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst); | |
5225 | ||
5226 | if (is_t4(adap->params.chip)) { | |
5227 | *enabled = !!(ctla & TFEN_F); | |
5228 | tp->port = TFPORT_G(ctla); | |
5229 | tp->invert = !!(ctla & TFINVERTMATCH_F); | |
5230 | } else { | |
5231 | *enabled = !!(ctla & T5_TFEN_F); | |
5232 | tp->port = T5_TFPORT_G(ctla); | |
5233 | tp->invert = !!(ctla & T5_TFINVERTMATCH_F); | |
5234 | } | |
5235 | tp->snap_len = TFCAPTUREMAX_G(ctlb); | |
5236 | tp->min_len = TFMINPKTSIZE_G(ctlb); | |
5237 | tp->skip_ofst = TFOFFSET_G(ctla); | |
5238 | tp->skip_len = TFLENGTH_G(ctla); | |
5239 | ||
5240 | ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx; | |
5241 | data_reg = MPS_TRC_FILTER0_MATCH_A + ofst; | |
5242 | mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst; | |
5243 | ||
5244 | for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { | |
5245 | tp->mask[i] = ~t4_read_reg(adap, mask_reg); | |
5246 | tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; | |
5247 | } | |
5248 | } | |
5249 | ||
b3bbe36a HS |
5250 | /** |
5251 | * t4_pmtx_get_stats - returns the HW stats from PMTX | |
5252 | * @adap: the adapter | |
5253 | * @cnt: where to store the count statistics | |
5254 | * @cycles: where to store the cycle statistics | |
5255 | * | |
5256 | * Returns performance statistics from PMTX. | |
5257 | */ | |
5258 | void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) | |
5259 | { | |
5260 | int i; | |
5261 | u32 data[2]; | |
5262 | ||
44588560 | 5263 | for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { |
b3bbe36a HS |
5264 | t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); |
5265 | cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); | |
5266 | if (is_t4(adap->params.chip)) { | |
5267 | cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); | |
5268 | } else { | |
5269 | t4_read_indirect(adap, PM_TX_DBG_CTRL_A, | |
5270 | PM_TX_DBG_DATA_A, data, 2, | |
5271 | PM_TX_DBG_STAT_MSB_A); | |
5272 | cycles[i] = (((u64)data[0] << 32) | data[1]); | |
5273 | } | |
5274 | } | |
5275 | } | |
5276 | ||
5277 | /** | |
5278 | * t4_pmrx_get_stats - returns the HW stats from PMRX | |
5279 | * @adap: the adapter | |
5280 | * @cnt: where to store the count statistics | |
5281 | * @cycles: where to store the cycle statistics | |
5282 | * | |
5283 | * Returns performance statistics from PMRX. | |
5284 | */ | |
5285 | void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) | |
5286 | { | |
5287 | int i; | |
5288 | u32 data[2]; | |
5289 | ||
44588560 | 5290 | for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { |
b3bbe36a HS |
5291 | t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); |
5292 | cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); | |
5293 | if (is_t4(adap->params.chip)) { | |
5294 | cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); | |
5295 | } else { | |
5296 | t4_read_indirect(adap, PM_RX_DBG_CTRL_A, | |
5297 | PM_RX_DBG_DATA_A, data, 2, | |
5298 | PM_RX_DBG_STAT_MSB_A); | |
5299 | cycles[i] = (((u64)data[0] << 32) | data[1]); | |
5300 | } | |
5301 | } | |
5302 | } | |
5303 | ||
56d36be4 | 5304 | /** |
145ef8a5 | 5305 | * t4_get_mps_bg_map - return the buffer groups associated with a port |
56d36be4 DM |
5306 | * @adap: the adapter |
5307 | * @idx: the port index | |
5308 | * | |
5309 | * Returns a bitmap indicating which MPS buffer groups are associated | |
5310 | * with the given port. Bit i is set if buffer group i is used by the | |
5311 | * port. | |
5312 | */ | |
145ef8a5 | 5313 | unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) |
56d36be4 | 5314 | { |
837e4a42 | 5315 | u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); |
56d36be4 DM |
5316 | |
5317 | if (n == 0) | |
5318 | return idx == 0 ? 0xf : 0; | |
e9faeab8 HS |
5319 | /* In T6 (which is a 2 port card), |
5320 | * port 0 is mapped to channel 0 and port 1 is mapped to channel 1. | |
5321 | * For 2 port T4/T5 adapter, | |
5322 | * port 0 is mapped to channel 0 and 1, | |
5323 | * port 1 is mapped to channel 2 and 3. | |
5324 | */ | |
5325 | if ((n == 1) && | |
5326 | (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) | |
56d36be4 DM |
5327 | return idx < 2 ? (3 << (2 * idx)) : 0; |
5328 | return 1 << idx; | |
5329 | } | |
5330 | ||
72aca4bf KS |
5331 | /** |
5332 | * t4_get_port_type_description - return Port Type string description | |
5333 | * @port_type: firmware Port Type enumeration | |
5334 | */ | |
5335 | const char *t4_get_port_type_description(enum fw_port_type port_type) | |
5336 | { | |
5337 | static const char *const port_type_description[] = { | |
5338 | "R XFI", | |
5339 | "R XAUI", | |
5340 | "T SGMII", | |
5341 | "T XFI", | |
5342 | "T XAUI", | |
5343 | "KX4", | |
5344 | "CX4", | |
5345 | "KX", | |
5346 | "KR", | |
5347 | "R SFP+", | |
5348 | "KR/KX", | |
5349 | "KR/KX/KX4", | |
5350 | "R QSFP_10G", | |
5aa80e51 | 5351 | "R QSA", |
72aca4bf KS |
5352 | "R QSFP", |
5353 | "R BP40_BA", | |
5354 | }; | |
5355 | ||
5356 | if (port_type < ARRAY_SIZE(port_type_description)) | |
5357 | return port_type_description[port_type]; | |
5358 | return "UNKNOWN"; | |
5359 | } | |
5360 | ||
a4cfd929 HS |
5361 | /** |
5362 | * t4_get_port_stats_offset - collect port stats relative to a previous | |
5363 | * snapshot | |
5364 | * @adap: The adapter | |
5365 | * @idx: The port | |
5366 | * @stats: Current stats to fill | |
5367 | * @offset: Previous stats snapshot | |
5368 | */ | |
5369 | void t4_get_port_stats_offset(struct adapter *adap, int idx, | |
5370 | struct port_stats *stats, | |
5371 | struct port_stats *offset) | |
5372 | { | |
5373 | u64 *s, *o; | |
5374 | int i; | |
5375 | ||
5376 | t4_get_port_stats(adap, idx, stats); | |
5377 | for (i = 0, s = (u64 *)stats, o = (u64 *)offset; | |
5378 | i < (sizeof(struct port_stats) / sizeof(u64)); | |
5379 | i++, s++, o++) | |
5380 | *s -= *o; | |
5381 | } | |
5382 | ||
56d36be4 DM |
5383 | /** |
5384 | * t4_get_port_stats - collect port statistics | |
5385 | * @adap: the adapter | |
5386 | * @idx: the port index | |
5387 | * @p: the stats structure to fill | |
5388 | * | |
5389 | * Collect statistics related to the given port from HW. | |
5390 | */ | |
5391 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) | |
5392 | { | |
145ef8a5 | 5393 | u32 bgmap = t4_get_mps_bg_map(adap, idx); |
56d36be4 DM |
5394 | |
5395 | #define GET_STAT(name) \ | |
0a57a536 | 5396 | t4_read_reg64(adap, \ |
d14807dd | 5397 | (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ |
0a57a536 | 5398 | T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L))) |
56d36be4 DM |
5399 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) |
5400 | ||
5401 | p->tx_octets = GET_STAT(TX_PORT_BYTES); | |
5402 | p->tx_frames = GET_STAT(TX_PORT_FRAMES); | |
5403 | p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); | |
5404 | p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); | |
5405 | p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); | |
5406 | p->tx_error_frames = GET_STAT(TX_PORT_ERROR); | |
5407 | p->tx_frames_64 = GET_STAT(TX_PORT_64B); | |
5408 | p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); | |
5409 | p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); | |
5410 | p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); | |
5411 | p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); | |
5412 | p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); | |
5413 | p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); | |
5414 | p->tx_drop = GET_STAT(TX_PORT_DROP); | |
5415 | p->tx_pause = GET_STAT(TX_PORT_PAUSE); | |
5416 | p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); | |
5417 | p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); | |
5418 | p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); | |
5419 | p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); | |
5420 | p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); | |
5421 | p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); | |
5422 | p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); | |
5423 | p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); | |
5424 | ||
5425 | p->rx_octets = GET_STAT(RX_PORT_BYTES); | |
5426 | p->rx_frames = GET_STAT(RX_PORT_FRAMES); | |
5427 | p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); | |
5428 | p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); | |
5429 | p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); | |
5430 | p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); | |
5431 | p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); | |
5432 | p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); | |
5433 | p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); | |
5434 | p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); | |
5435 | p->rx_runt = GET_STAT(RX_PORT_LESS_64B); | |
5436 | p->rx_frames_64 = GET_STAT(RX_PORT_64B); | |
5437 | p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); | |
5438 | p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); | |
5439 | p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); | |
5440 | p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); | |
5441 | p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); | |
5442 | p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); | |
5443 | p->rx_pause = GET_STAT(RX_PORT_PAUSE); | |
5444 | p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); | |
5445 | p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); | |
5446 | p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); | |
5447 | p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); | |
5448 | p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); | |
5449 | p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); | |
5450 | p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); | |
5451 | p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); | |
5452 | ||
5453 | p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; | |
5454 | p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; | |
5455 | p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; | |
5456 | p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; | |
5457 | p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; | |
5458 | p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; | |
5459 | p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; | |
5460 | p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; | |
5461 | ||
5462 | #undef GET_STAT | |
5463 | #undef GET_STAT_COM | |
5464 | } | |
5465 | ||
56d36be4 | 5466 | /** |
65046e84 | 5467 | * t4_get_lb_stats - collect loopback port statistics |
56d36be4 | 5468 | * @adap: the adapter |
65046e84 HS |
5469 | * @idx: the loopback port index |
5470 | * @p: the stats structure to fill | |
56d36be4 | 5471 | * |
65046e84 | 5472 | * Return HW statistics for the given loopback port. |
56d36be4 | 5473 | */ |
65046e84 | 5474 | void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) |
56d36be4 | 5475 | { |
65046e84 | 5476 | u32 bgmap = t4_get_mps_bg_map(adap, idx); |
56d36be4 | 5477 | |
65046e84 HS |
5478 | #define GET_STAT(name) \ |
5479 | t4_read_reg64(adap, \ | |
0d804338 | 5480 | (is_t4(adap->params.chip) ? \ |
65046e84 HS |
5481 | PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \ |
5482 | T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L))) | |
5483 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) | |
56d36be4 | 5484 | |
65046e84 HS |
5485 | p->octets = GET_STAT(BYTES); |
5486 | p->frames = GET_STAT(FRAMES); | |
5487 | p->bcast_frames = GET_STAT(BCAST); | |
5488 | p->mcast_frames = GET_STAT(MCAST); | |
5489 | p->ucast_frames = GET_STAT(UCAST); | |
5490 | p->error_frames = GET_STAT(ERROR); | |
5491 | ||
5492 | p->frames_64 = GET_STAT(64B); | |
5493 | p->frames_65_127 = GET_STAT(65B_127B); | |
5494 | p->frames_128_255 = GET_STAT(128B_255B); | |
5495 | p->frames_256_511 = GET_STAT(256B_511B); | |
5496 | p->frames_512_1023 = GET_STAT(512B_1023B); | |
5497 | p->frames_1024_1518 = GET_STAT(1024B_1518B); | |
5498 | p->frames_1519_max = GET_STAT(1519B_MAX); | |
5499 | p->drop = GET_STAT(DROP_FRAMES); | |
5500 | ||
5501 | p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; | |
5502 | p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; | |
5503 | p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; | |
5504 | p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; | |
5505 | p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; | |
5506 | p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; | |
5507 | p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; | |
5508 | p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; | |
56d36be4 | 5509 | |
65046e84 HS |
5510 | #undef GET_STAT |
5511 | #undef GET_STAT_COM | |
56d36be4 DM |
5512 | } |
5513 | ||
f2b7e78d VP |
5514 | /* t4_mk_filtdelwr - create a delete filter WR |
5515 | * @ftid: the filter ID | |
5516 | * @wr: the filter work request to populate | |
5517 | * @qid: ingress queue to receive the delete notification | |
5518 | * | |
5519 | * Creates a filter work request to delete the supplied filter. If @qid is | |
5520 | * negative the delete notification is suppressed. | |
5521 | */ | |
5522 | void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) | |
5523 | { | |
5524 | memset(wr, 0, sizeof(*wr)); | |
f404f80c HS |
5525 | wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR)); |
5526 | wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16)); | |
5527 | wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) | | |
5528 | FW_FILTER_WR_NOREPLY_V(qid < 0)); | |
5529 | wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F); | |
f2b7e78d | 5530 | if (qid >= 0) |
f404f80c HS |
5531 | wr->rx_chan_rx_rpl_iq = |
5532 | cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid)); | |
f2b7e78d VP |
5533 | } |
5534 | ||
56d36be4 | 5535 | #define INIT_CMD(var, cmd, rd_wr) do { \ |
f404f80c HS |
5536 | (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \ |
5537 | FW_CMD_REQUEST_F | \ | |
5538 | FW_CMD_##rd_wr##_F); \ | |
5539 | (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ | |
56d36be4 DM |
5540 | } while (0) |
5541 | ||
8caa1e84 VP |
5542 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, |
5543 | u32 addr, u32 val) | |
5544 | { | |
f404f80c | 5545 | u32 ldst_addrspace; |
8caa1e84 VP |
5546 | struct fw_ldst_cmd c; |
5547 | ||
5548 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
5549 | ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE); |
5550 | c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
5551 | FW_CMD_REQUEST_F | | |
5552 | FW_CMD_WRITE_F | | |
5553 | ldst_addrspace); | |
5554 | c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); | |
5555 | c.u.addrval.addr = cpu_to_be32(addr); | |
5556 | c.u.addrval.val = cpu_to_be32(val); | |
8caa1e84 VP |
5557 | |
5558 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
5559 | } | |
5560 | ||
56d36be4 DM |
5561 | /** |
5562 | * t4_mdio_rd - read a PHY register through MDIO | |
5563 | * @adap: the adapter | |
5564 | * @mbox: mailbox to use for the FW command | |
5565 | * @phy_addr: the PHY address | |
5566 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
5567 | * @reg: the register to read | |
5568 | * @valp: where to store the value | |
5569 | * | |
5570 | * Issues a FW command through the given mailbox to read a PHY register. | |
5571 | */ | |
5572 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
5573 | unsigned int mmd, unsigned int reg, u16 *valp) | |
5574 | { | |
5575 | int ret; | |
f404f80c | 5576 | u32 ldst_addrspace; |
56d36be4 DM |
5577 | struct fw_ldst_cmd c; |
5578 | ||
5579 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
5580 | ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); |
5581 | c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
5582 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
5583 | ldst_addrspace); | |
5584 | c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); | |
5585 | c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | | |
5586 | FW_LDST_CMD_MMD_V(mmd)); | |
5587 | c.u.mdio.raddr = cpu_to_be16(reg); | |
56d36be4 DM |
5588 | |
5589 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
5590 | if (ret == 0) | |
f404f80c | 5591 | *valp = be16_to_cpu(c.u.mdio.rval); |
56d36be4 DM |
5592 | return ret; |
5593 | } | |
5594 | ||
5595 | /** | |
5596 | * t4_mdio_wr - write a PHY register through MDIO | |
5597 | * @adap: the adapter | |
5598 | * @mbox: mailbox to use for the FW command | |
5599 | * @phy_addr: the PHY address | |
5600 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
5601 | * @reg: the register to write | |
5602 | * @valp: value to write | |
5603 | * | |
5604 | * Issues a FW command through the given mailbox to write a PHY register. | |
5605 | */ | |
5606 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
5607 | unsigned int mmd, unsigned int reg, u16 val) | |
5608 | { | |
f404f80c | 5609 | u32 ldst_addrspace; |
56d36be4 DM |
5610 | struct fw_ldst_cmd c; |
5611 | ||
5612 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
5613 | ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); |
5614 | c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
5615 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
5616 | ldst_addrspace); | |
5617 | c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); | |
5618 | c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | | |
5619 | FW_LDST_CMD_MMD_V(mmd)); | |
5620 | c.u.mdio.raddr = cpu_to_be16(reg); | |
5621 | c.u.mdio.rval = cpu_to_be16(val); | |
56d36be4 DM |
5622 | |
5623 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
5624 | } | |
5625 | ||
68bce192 KS |
5626 | /** |
5627 | * t4_sge_decode_idma_state - decode the idma state | |
5628 | * @adap: the adapter | |
5629 | * @state: the state idma is stuck in | |
5630 | */ | |
5631 | void t4_sge_decode_idma_state(struct adapter *adapter, int state) | |
5632 | { | |
5633 | static const char * const t4_decode[] = { | |
5634 | "IDMA_IDLE", | |
5635 | "IDMA_PUSH_MORE_CPL_FIFO", | |
5636 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | |
5637 | "Not used", | |
5638 | "IDMA_PHYSADDR_SEND_PCIEHDR", | |
5639 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | |
5640 | "IDMA_PHYSADDR_SEND_PAYLOAD", | |
5641 | "IDMA_SEND_FIFO_TO_IMSG", | |
5642 | "IDMA_FL_REQ_DATA_FL_PREP", | |
5643 | "IDMA_FL_REQ_DATA_FL", | |
5644 | "IDMA_FL_DROP", | |
5645 | "IDMA_FL_H_REQ_HEADER_FL", | |
5646 | "IDMA_FL_H_SEND_PCIEHDR", | |
5647 | "IDMA_FL_H_PUSH_CPL_FIFO", | |
5648 | "IDMA_FL_H_SEND_CPL", | |
5649 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | |
5650 | "IDMA_FL_H_SEND_IP_HDR", | |
5651 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | |
5652 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | |
5653 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | |
5654 | "IDMA_FL_D_SEND_PCIEHDR", | |
5655 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | |
5656 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | |
5657 | "IDMA_FL_SEND_PCIEHDR", | |
5658 | "IDMA_FL_PUSH_CPL_FIFO", | |
5659 | "IDMA_FL_SEND_CPL", | |
5660 | "IDMA_FL_SEND_PAYLOAD_FIRST", | |
5661 | "IDMA_FL_SEND_PAYLOAD", | |
5662 | "IDMA_FL_REQ_NEXT_DATA_FL", | |
5663 | "IDMA_FL_SEND_NEXT_PCIEHDR", | |
5664 | "IDMA_FL_SEND_PADDING", | |
5665 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | |
5666 | "IDMA_FL_SEND_FIFO_TO_IMSG", | |
5667 | "IDMA_FL_REQ_DATAFL_DONE", | |
5668 | "IDMA_FL_REQ_HEADERFL_DONE", | |
5669 | }; | |
5670 | static const char * const t5_decode[] = { | |
5671 | "IDMA_IDLE", | |
5672 | "IDMA_ALMOST_IDLE", | |
5673 | "IDMA_PUSH_MORE_CPL_FIFO", | |
5674 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | |
5675 | "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", | |
5676 | "IDMA_PHYSADDR_SEND_PCIEHDR", | |
5677 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | |
5678 | "IDMA_PHYSADDR_SEND_PAYLOAD", | |
5679 | "IDMA_SEND_FIFO_TO_IMSG", | |
5680 | "IDMA_FL_REQ_DATA_FL", | |
5681 | "IDMA_FL_DROP", | |
5682 | "IDMA_FL_DROP_SEND_INC", | |
5683 | "IDMA_FL_H_REQ_HEADER_FL", | |
5684 | "IDMA_FL_H_SEND_PCIEHDR", | |
5685 | "IDMA_FL_H_PUSH_CPL_FIFO", | |
5686 | "IDMA_FL_H_SEND_CPL", | |
5687 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | |
5688 | "IDMA_FL_H_SEND_IP_HDR", | |
5689 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | |
5690 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | |
5691 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | |
5692 | "IDMA_FL_D_SEND_PCIEHDR", | |
5693 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | |
5694 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | |
5695 | "IDMA_FL_SEND_PCIEHDR", | |
5696 | "IDMA_FL_PUSH_CPL_FIFO", | |
5697 | "IDMA_FL_SEND_CPL", | |
5698 | "IDMA_FL_SEND_PAYLOAD_FIRST", | |
5699 | "IDMA_FL_SEND_PAYLOAD", | |
5700 | "IDMA_FL_REQ_NEXT_DATA_FL", | |
5701 | "IDMA_FL_SEND_NEXT_PCIEHDR", | |
5702 | "IDMA_FL_SEND_PADDING", | |
5703 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | |
5704 | }; | |
5705 | static const u32 sge_regs[] = { | |
f061de42 HS |
5706 | SGE_DEBUG_DATA_LOW_INDEX_2_A, |
5707 | SGE_DEBUG_DATA_LOW_INDEX_3_A, | |
5708 | SGE_DEBUG_DATA_HIGH_INDEX_10_A, | |
68bce192 KS |
5709 | }; |
5710 | const char **sge_idma_decode; | |
5711 | int sge_idma_decode_nstates; | |
5712 | int i; | |
5713 | ||
5714 | if (is_t4(adapter->params.chip)) { | |
5715 | sge_idma_decode = (const char **)t4_decode; | |
5716 | sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); | |
5717 | } else { | |
5718 | sge_idma_decode = (const char **)t5_decode; | |
5719 | sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); | |
5720 | } | |
5721 | ||
5722 | if (state < sge_idma_decode_nstates) | |
5723 | CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); | |
5724 | else | |
5725 | CH_WARN(adapter, "idma state %d unknown\n", state); | |
5726 | ||
5727 | for (i = 0; i < ARRAY_SIZE(sge_regs); i++) | |
5728 | CH_WARN(adapter, "SGE register %#x value %#x\n", | |
5729 | sge_regs[i], t4_read_reg(adapter, sge_regs[i])); | |
5730 | } | |
5731 | ||
5d700ecb HS |
5732 | /** |
5733 | * t4_sge_ctxt_flush - flush the SGE context cache | |
5734 | * @adap: the adapter | |
5735 | * @mbox: mailbox to use for the FW command | |
5736 | * | |
5737 | * Issues a FW command through the given mailbox to flush the | |
5738 | * SGE context cache. | |
5739 | */ | |
5740 | int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) | |
5741 | { | |
5742 | int ret; | |
5743 | u32 ldst_addrspace; | |
5744 | struct fw_ldst_cmd c; | |
5745 | ||
5746 | memset(&c, 0, sizeof(c)); | |
5747 | ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC); | |
5748 | c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | | |
5749 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
5750 | ldst_addrspace); | |
5751 | c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); | |
5752 | c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F); | |
5753 | ||
5754 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
5755 | return ret; | |
5756 | } | |
5757 | ||
56d36be4 | 5758 | /** |
636f9d37 VP |
5759 | * t4_fw_hello - establish communication with FW |
5760 | * @adap: the adapter | |
5761 | * @mbox: mailbox to use for the FW command | |
5762 | * @evt_mbox: mailbox to receive async FW events | |
5763 | * @master: specifies the caller's willingness to be the device master | |
5764 | * @state: returns the current device state (if non-NULL) | |
56d36be4 | 5765 | * |
636f9d37 VP |
5766 | * Issues a command to establish communication with FW. Returns either |
5767 | * an error (negative integer) or the mailbox of the Master PF. | |
56d36be4 DM |
5768 | */ |
5769 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
5770 | enum dev_master master, enum dev_state *state) | |
5771 | { | |
5772 | int ret; | |
5773 | struct fw_hello_cmd c; | |
636f9d37 VP |
5774 | u32 v; |
5775 | unsigned int master_mbox; | |
5776 | int retries = FW_CMD_HELLO_RETRIES; | |
56d36be4 | 5777 | |
636f9d37 VP |
5778 | retry: |
5779 | memset(&c, 0, sizeof(c)); | |
56d36be4 | 5780 | INIT_CMD(c, HELLO, WRITE); |
f404f80c | 5781 | c.err_to_clearinit = cpu_to_be32( |
5167865a HS |
5782 | FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) | |
5783 | FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) | | |
f404f80c HS |
5784 | FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? |
5785 | mbox : FW_HELLO_CMD_MBMASTER_M) | | |
5167865a HS |
5786 | FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) | |
5787 | FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) | | |
5788 | FW_HELLO_CMD_CLEARINIT_F); | |
56d36be4 | 5789 | |
636f9d37 VP |
5790 | /* |
5791 | * Issue the HELLO command to the firmware. If it's not successful | |
5792 | * but indicates that we got a "busy" or "timeout" condition, retry | |
31d55c2d HS |
5793 | * the HELLO until we exhaust our retry limit. If we do exceed our |
5794 | * retry limit, check to see if the firmware left us any error | |
5795 | * information and report that if so. | |
636f9d37 | 5796 | */ |
56d36be4 | 5797 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); |
636f9d37 VP |
5798 | if (ret < 0) { |
5799 | if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) | |
5800 | goto retry; | |
f061de42 | 5801 | if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) |
31d55c2d | 5802 | t4_report_fw_error(adap); |
636f9d37 VP |
5803 | return ret; |
5804 | } | |
5805 | ||
f404f80c | 5806 | v = be32_to_cpu(c.err_to_clearinit); |
5167865a | 5807 | master_mbox = FW_HELLO_CMD_MBMASTER_G(v); |
636f9d37 | 5808 | if (state) { |
5167865a | 5809 | if (v & FW_HELLO_CMD_ERR_F) |
56d36be4 | 5810 | *state = DEV_STATE_ERR; |
5167865a | 5811 | else if (v & FW_HELLO_CMD_INIT_F) |
636f9d37 | 5812 | *state = DEV_STATE_INIT; |
56d36be4 DM |
5813 | else |
5814 | *state = DEV_STATE_UNINIT; | |
5815 | } | |
636f9d37 VP |
5816 | |
5817 | /* | |
5818 | * If we're not the Master PF then we need to wait around for the | |
5819 | * Master PF Driver to finish setting up the adapter. | |
5820 | * | |
5821 | * Note that we also do this wait if we're a non-Master-capable PF and | |
5822 | * there is no current Master PF; a Master PF may show up momentarily | |
5823 | * and we wouldn't want to fail pointlessly. (This can happen when an | |
5824 | * OS loads lots of different drivers rapidly at the same time). In | |
5825 | * this case, the Master PF returned by the firmware will be | |
b2e1a3f0 | 5826 | * PCIE_FW_MASTER_M so the test below will work ... |
636f9d37 | 5827 | */ |
5167865a | 5828 | if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 && |
636f9d37 VP |
5829 | master_mbox != mbox) { |
5830 | int waiting = FW_CMD_HELLO_TIMEOUT; | |
5831 | ||
5832 | /* | |
5833 | * Wait for the firmware to either indicate an error or | |
5834 | * initialized state. If we see either of these we bail out | |
5835 | * and report the issue to the caller. If we exhaust the | |
5836 | * "hello timeout" and we haven't exhausted our retries, try | |
5837 | * again. Otherwise bail with a timeout error. | |
5838 | */ | |
5839 | for (;;) { | |
5840 | u32 pcie_fw; | |
5841 | ||
5842 | msleep(50); | |
5843 | waiting -= 50; | |
5844 | ||
5845 | /* | |
5846 | * If neither Error nor Initialialized are indicated | |
5847 | * by the firmware keep waiting till we exaust our | |
5848 | * timeout ... and then retry if we haven't exhausted | |
5849 | * our retries ... | |
5850 | */ | |
f061de42 HS |
5851 | pcie_fw = t4_read_reg(adap, PCIE_FW_A); |
5852 | if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { | |
636f9d37 VP |
5853 | if (waiting <= 0) { |
5854 | if (retries-- > 0) | |
5855 | goto retry; | |
5856 | ||
5857 | return -ETIMEDOUT; | |
5858 | } | |
5859 | continue; | |
5860 | } | |
5861 | ||
5862 | /* | |
5863 | * We either have an Error or Initialized condition | |
5864 | * report errors preferentially. | |
5865 | */ | |
5866 | if (state) { | |
f061de42 | 5867 | if (pcie_fw & PCIE_FW_ERR_F) |
636f9d37 | 5868 | *state = DEV_STATE_ERR; |
f061de42 | 5869 | else if (pcie_fw & PCIE_FW_INIT_F) |
636f9d37 VP |
5870 | *state = DEV_STATE_INIT; |
5871 | } | |
5872 | ||
5873 | /* | |
5874 | * If we arrived before a Master PF was selected and | |
5875 | * there's not a valid Master PF, grab its identity | |
5876 | * for our caller. | |
5877 | */ | |
b2e1a3f0 | 5878 | if (master_mbox == PCIE_FW_MASTER_M && |
f061de42 | 5879 | (pcie_fw & PCIE_FW_MASTER_VLD_F)) |
b2e1a3f0 | 5880 | master_mbox = PCIE_FW_MASTER_G(pcie_fw); |
636f9d37 VP |
5881 | break; |
5882 | } | |
5883 | } | |
5884 | ||
5885 | return master_mbox; | |
56d36be4 DM |
5886 | } |
5887 | ||
5888 | /** | |
5889 | * t4_fw_bye - end communication with FW | |
5890 | * @adap: the adapter | |
5891 | * @mbox: mailbox to use for the FW command | |
5892 | * | |
5893 | * Issues a command to terminate communication with FW. | |
5894 | */ | |
5895 | int t4_fw_bye(struct adapter *adap, unsigned int mbox) | |
5896 | { | |
5897 | struct fw_bye_cmd c; | |
5898 | ||
0062b15c | 5899 | memset(&c, 0, sizeof(c)); |
56d36be4 DM |
5900 | INIT_CMD(c, BYE, WRITE); |
5901 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
5902 | } | |
5903 | ||
5904 | /** | |
5905 | * t4_init_cmd - ask FW to initialize the device | |
5906 | * @adap: the adapter | |
5907 | * @mbox: mailbox to use for the FW command | |
5908 | * | |
5909 | * Issues a command to FW to partially initialize the device. This | |
5910 | * performs initialization that generally doesn't depend on user input. | |
5911 | */ | |
5912 | int t4_early_init(struct adapter *adap, unsigned int mbox) | |
5913 | { | |
5914 | struct fw_initialize_cmd c; | |
5915 | ||
0062b15c | 5916 | memset(&c, 0, sizeof(c)); |
56d36be4 DM |
5917 | INIT_CMD(c, INITIALIZE, WRITE); |
5918 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
5919 | } | |
5920 | ||
5921 | /** | |
5922 | * t4_fw_reset - issue a reset to FW | |
5923 | * @adap: the adapter | |
5924 | * @mbox: mailbox to use for the FW command | |
5925 | * @reset: specifies the type of reset to perform | |
5926 | * | |
5927 | * Issues a reset command of the specified type to FW. | |
5928 | */ | |
5929 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) | |
5930 | { | |
5931 | struct fw_reset_cmd c; | |
5932 | ||
0062b15c | 5933 | memset(&c, 0, sizeof(c)); |
56d36be4 | 5934 | INIT_CMD(c, RESET, WRITE); |
f404f80c | 5935 | c.val = cpu_to_be32(reset); |
56d36be4 DM |
5936 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
5937 | } | |
5938 | ||
26f7cbc0 VP |
5939 | /** |
5940 | * t4_fw_halt - issue a reset/halt to FW and put uP into RESET | |
5941 | * @adap: the adapter | |
5942 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
5943 | * @force: force uP into RESET even if FW RESET command fails | |
5944 | * | |
5945 | * Issues a RESET command to firmware (if desired) with a HALT indication | |
5946 | * and then puts the microprocessor into RESET state. The RESET command | |
5947 | * will only be issued if a legitimate mailbox is provided (mbox <= | |
b2e1a3f0 | 5948 | * PCIE_FW_MASTER_M). |
26f7cbc0 VP |
5949 | * |
5950 | * This is generally used in order for the host to safely manipulate the | |
5951 | * adapter without fear of conflicting with whatever the firmware might | |
5952 | * be doing. The only way out of this state is to RESTART the firmware | |
5953 | * ... | |
5954 | */ | |
de5b8677 | 5955 | static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) |
26f7cbc0 VP |
5956 | { |
5957 | int ret = 0; | |
5958 | ||
5959 | /* | |
5960 | * If a legitimate mailbox is provided, issue a RESET command | |
5961 | * with a HALT indication. | |
5962 | */ | |
b2e1a3f0 | 5963 | if (mbox <= PCIE_FW_MASTER_M) { |
26f7cbc0 VP |
5964 | struct fw_reset_cmd c; |
5965 | ||
5966 | memset(&c, 0, sizeof(c)); | |
5967 | INIT_CMD(c, RESET, WRITE); | |
f404f80c HS |
5968 | c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F); |
5969 | c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F); | |
26f7cbc0 VP |
5970 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
5971 | } | |
5972 | ||
5973 | /* | |
5974 | * Normally we won't complete the operation if the firmware RESET | |
5975 | * command fails but if our caller insists we'll go ahead and put the | |
5976 | * uP into RESET. This can be useful if the firmware is hung or even | |
5977 | * missing ... We'll have to take the risk of putting the uP into | |
5978 | * RESET without the cooperation of firmware in that case. | |
5979 | * | |
5980 | * We also force the firmware's HALT flag to be on in case we bypassed | |
5981 | * the firmware RESET command above or we're dealing with old firmware | |
5982 | * which doesn't have the HALT capability. This will serve as a flag | |
5983 | * for the incoming firmware to know that it's coming out of a HALT | |
5984 | * rather than a RESET ... if it's new enough to understand that ... | |
5985 | */ | |
5986 | if (ret == 0 || force) { | |
89c3a86c | 5987 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); |
f061de42 | 5988 | t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, |
b2e1a3f0 | 5989 | PCIE_FW_HALT_F); |
26f7cbc0 VP |
5990 | } |
5991 | ||
5992 | /* | |
5993 | * And we always return the result of the firmware RESET command | |
5994 | * even when we force the uP into RESET ... | |
5995 | */ | |
5996 | return ret; | |
5997 | } | |
5998 | ||
5999 | /** | |
6000 | * t4_fw_restart - restart the firmware by taking the uP out of RESET | |
6001 | * @adap: the adapter | |
6002 | * @reset: if we want to do a RESET to restart things | |
6003 | * | |
6004 | * Restart firmware previously halted by t4_fw_halt(). On successful | |
6005 | * return the previous PF Master remains as the new PF Master and there | |
6006 | * is no need to issue a new HELLO command, etc. | |
6007 | * | |
6008 | * We do this in two ways: | |
6009 | * | |
6010 | * 1. If we're dealing with newer firmware we'll simply want to take | |
6011 | * the chip's microprocessor out of RESET. This will cause the | |
6012 | * firmware to start up from its start vector. And then we'll loop | |
6013 | * until the firmware indicates it's started again (PCIE_FW.HALT | |
6014 | * reset to 0) or we timeout. | |
6015 | * | |
6016 | * 2. If we're dealing with older firmware then we'll need to RESET | |
6017 | * the chip since older firmware won't recognize the PCIE_FW.HALT | |
6018 | * flag and automatically RESET itself on startup. | |
6019 | */ | |
de5b8677 | 6020 | static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) |
26f7cbc0 VP |
6021 | { |
6022 | if (reset) { | |
6023 | /* | |
6024 | * Since we're directing the RESET instead of the firmware | |
6025 | * doing it automatically, we need to clear the PCIE_FW.HALT | |
6026 | * bit. | |
6027 | */ | |
f061de42 | 6028 | t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); |
26f7cbc0 VP |
6029 | |
6030 | /* | |
6031 | * If we've been given a valid mailbox, first try to get the | |
6032 | * firmware to do the RESET. If that works, great and we can | |
6033 | * return success. Otherwise, if we haven't been given a | |
6034 | * valid mailbox or the RESET command failed, fall back to | |
6035 | * hitting the chip with a hammer. | |
6036 | */ | |
b2e1a3f0 | 6037 | if (mbox <= PCIE_FW_MASTER_M) { |
89c3a86c | 6038 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); |
26f7cbc0 VP |
6039 | msleep(100); |
6040 | if (t4_fw_reset(adap, mbox, | |
0d804338 | 6041 | PIORST_F | PIORSTMODE_F) == 0) |
26f7cbc0 VP |
6042 | return 0; |
6043 | } | |
6044 | ||
0d804338 | 6045 | t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); |
26f7cbc0 VP |
6046 | msleep(2000); |
6047 | } else { | |
6048 | int ms; | |
6049 | ||
89c3a86c | 6050 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); |
26f7cbc0 | 6051 | for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { |
f061de42 | 6052 | if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) |
26f7cbc0 VP |
6053 | return 0; |
6054 | msleep(100); | |
6055 | ms += 100; | |
6056 | } | |
6057 | return -ETIMEDOUT; | |
6058 | } | |
6059 | return 0; | |
6060 | } | |
6061 | ||
6062 | /** | |
6063 | * t4_fw_upgrade - perform all of the steps necessary to upgrade FW | |
6064 | * @adap: the adapter | |
6065 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
6066 | * @fw_data: the firmware image to write | |
6067 | * @size: image size | |
6068 | * @force: force upgrade even if firmware doesn't cooperate | |
6069 | * | |
6070 | * Perform all of the steps necessary for upgrading an adapter's | |
6071 | * firmware image. Normally this requires the cooperation of the | |
6072 | * existing firmware in order to halt all existing activities | |
6073 | * but if an invalid mailbox token is passed in we skip that step | |
6074 | * (though we'll still put the adapter microprocessor into RESET in | |
6075 | * that case). | |
6076 | * | |
6077 | * On successful return the new firmware will have been loaded and | |
6078 | * the adapter will have been fully RESET losing all previous setup | |
6079 | * state. On unsuccessful return the adapter may be completely hosed ... | |
6080 | * positive errno indicates that the adapter is ~probably~ intact, a | |
6081 | * negative errno indicates that things are looking bad ... | |
6082 | */ | |
22c0b963 HS |
6083 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, |
6084 | const u8 *fw_data, unsigned int size, int force) | |
26f7cbc0 VP |
6085 | { |
6086 | const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; | |
6087 | int reset, ret; | |
6088 | ||
79af221d HS |
6089 | if (!t4_fw_matches_chip(adap, fw_hdr)) |
6090 | return -EINVAL; | |
6091 | ||
26f7cbc0 VP |
6092 | ret = t4_fw_halt(adap, mbox, force); |
6093 | if (ret < 0 && !force) | |
6094 | return ret; | |
6095 | ||
6096 | ret = t4_load_fw(adap, fw_data, size); | |
6097 | if (ret < 0) | |
6098 | return ret; | |
6099 | ||
6100 | /* | |
6101 | * Older versions of the firmware don't understand the new | |
6102 | * PCIE_FW.HALT flag and so won't know to perform a RESET when they | |
6103 | * restart. So for newly loaded older firmware we'll have to do the | |
6104 | * RESET for it so it starts up on a clean slate. We can tell if | |
6105 | * the newly loaded firmware will handle this right by checking | |
6106 | * its header flags to see if it advertises the capability. | |
6107 | */ | |
f404f80c | 6108 | reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); |
26f7cbc0 VP |
6109 | return t4_fw_restart(adap, mbox, reset); |
6110 | } | |
6111 | ||
acac5962 HS |
6112 | /** |
6113 | * t4_fl_pkt_align - return the fl packet alignment | |
6114 | * @adap: the adapter | |
6115 | * | |
6116 | * T4 has a single field to specify the packing and padding boundary. | |
6117 | * T5 onwards has separate fields for this and hence the alignment for | |
6118 | * next packet offset is maximum of these two. | |
6119 | * | |
6120 | */ | |
6121 | int t4_fl_pkt_align(struct adapter *adap) | |
6122 | { | |
6123 | u32 sge_control, sge_control2; | |
6124 | unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift; | |
6125 | ||
6126 | sge_control = t4_read_reg(adap, SGE_CONTROL_A); | |
6127 | ||
6128 | /* T4 uses a single control field to specify both the PCIe Padding and | |
6129 | * Packing Boundary. T5 introduced the ability to specify these | |
6130 | * separately. The actual Ingress Packet Data alignment boundary | |
6131 | * within Packed Buffer Mode is the maximum of these two | |
6132 | * specifications. (Note that it makes no real practical sense to | |
6133 | * have the Pading Boudary be larger than the Packing Boundary but you | |
6134 | * could set the chip up that way and, in fact, legacy T4 code would | |
6135 | * end doing this because it would initialize the Padding Boundary and | |
6136 | * leave the Packing Boundary initialized to 0 (16 bytes).) | |
6137 | * Padding Boundary values in T6 starts from 8B, | |
6138 | * where as it is 32B for T4 and T5. | |
6139 | */ | |
6140 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
6141 | ingpad_shift = INGPADBOUNDARY_SHIFT_X; | |
6142 | else | |
6143 | ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X; | |
6144 | ||
6145 | ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift); | |
6146 | ||
6147 | fl_align = ingpadboundary; | |
6148 | if (!is_t4(adap->params.chip)) { | |
6149 | /* T5 has a weird interpretation of one of the PCIe Packing | |
6150 | * Boundary values. No idea why ... | |
6151 | */ | |
6152 | sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); | |
6153 | ingpackboundary = INGPACKBOUNDARY_G(sge_control2); | |
6154 | if (ingpackboundary == INGPACKBOUNDARY_16B_X) | |
6155 | ingpackboundary = 16; | |
6156 | else | |
6157 | ingpackboundary = 1 << (ingpackboundary + | |
6158 | INGPACKBOUNDARY_SHIFT_X); | |
6159 | ||
6160 | fl_align = max(ingpadboundary, ingpackboundary); | |
6161 | } | |
6162 | return fl_align; | |
6163 | } | |
6164 | ||
636f9d37 VP |
6165 | /** |
6166 | * t4_fixup_host_params - fix up host-dependent parameters | |
6167 | * @adap: the adapter | |
6168 | * @page_size: the host's Base Page Size | |
6169 | * @cache_line_size: the host's Cache Line Size | |
6170 | * | |
6171 | * Various registers in T4 contain values which are dependent on the | |
6172 | * host's Base Page and Cache Line Sizes. This function will fix all of | |
6173 | * those registers with the appropriate values as passed in ... | |
6174 | */ | |
6175 | int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, | |
6176 | unsigned int cache_line_size) | |
6177 | { | |
6178 | unsigned int page_shift = fls(page_size) - 1; | |
6179 | unsigned int sge_hps = page_shift - 10; | |
6180 | unsigned int stat_len = cache_line_size > 64 ? 128 : 64; | |
6181 | unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; | |
6182 | unsigned int fl_align_log = fls(fl_align) - 1; | |
acac5962 | 6183 | unsigned int ingpad; |
636f9d37 | 6184 | |
f612b815 HS |
6185 | t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, |
6186 | HOSTPAGESIZEPF0_V(sge_hps) | | |
6187 | HOSTPAGESIZEPF1_V(sge_hps) | | |
6188 | HOSTPAGESIZEPF2_V(sge_hps) | | |
6189 | HOSTPAGESIZEPF3_V(sge_hps) | | |
6190 | HOSTPAGESIZEPF4_V(sge_hps) | | |
6191 | HOSTPAGESIZEPF5_V(sge_hps) | | |
6192 | HOSTPAGESIZEPF6_V(sge_hps) | | |
6193 | HOSTPAGESIZEPF7_V(sge_hps)); | |
636f9d37 | 6194 | |
ce8f407a | 6195 | if (is_t4(adap->params.chip)) { |
f612b815 HS |
6196 | t4_set_reg_field(adap, SGE_CONTROL_A, |
6197 | INGPADBOUNDARY_V(INGPADBOUNDARY_M) | | |
6198 | EGRSTATUSPAGESIZE_F, | |
6199 | INGPADBOUNDARY_V(fl_align_log - | |
6200 | INGPADBOUNDARY_SHIFT_X) | | |
6201 | EGRSTATUSPAGESIZE_V(stat_len != 64)); | |
ce8f407a HS |
6202 | } else { |
6203 | /* T5 introduced the separation of the Free List Padding and | |
6204 | * Packing Boundaries. Thus, we can select a smaller Padding | |
6205 | * Boundary to avoid uselessly chewing up PCIe Link and Memory | |
6206 | * Bandwidth, and use a Packing Boundary which is large enough | |
6207 | * to avoid false sharing between CPUs, etc. | |
6208 | * | |
6209 | * For the PCI Link, the smaller the Padding Boundary the | |
6210 | * better. For the Memory Controller, a smaller Padding | |
6211 | * Boundary is better until we cross under the Memory Line | |
6212 | * Size (the minimum unit of transfer to/from Memory). If we | |
6213 | * have a Padding Boundary which is smaller than the Memory | |
6214 | * Line Size, that'll involve a Read-Modify-Write cycle on the | |
6215 | * Memory Controller which is never good. For T5 the smallest | |
6216 | * Padding Boundary which we can select is 32 bytes which is | |
6217 | * larger than any known Memory Controller Line Size so we'll | |
6218 | * use that. | |
6219 | * | |
6220 | * T5 has a different interpretation of the "0" value for the | |
6221 | * Packing Boundary. This corresponds to 16 bytes instead of | |
6222 | * the expected 32 bytes. We never have a Packing Boundary | |
6223 | * less than 32 bytes so we can't use that special value but | |
6224 | * on the other hand, if we wanted 32 bytes, the best we can | |
6225 | * really do is 64 bytes. | |
6226 | */ | |
6227 | if (fl_align <= 32) { | |
6228 | fl_align = 64; | |
6229 | fl_align_log = 6; | |
6230 | } | |
acac5962 HS |
6231 | |
6232 | if (is_t5(adap->params.chip)) | |
6233 | ingpad = INGPCIEBOUNDARY_32B_X; | |
6234 | else | |
6235 | ingpad = T6_INGPADBOUNDARY_32B_X; | |
6236 | ||
f612b815 HS |
6237 | t4_set_reg_field(adap, SGE_CONTROL_A, |
6238 | INGPADBOUNDARY_V(INGPADBOUNDARY_M) | | |
6239 | EGRSTATUSPAGESIZE_F, | |
acac5962 | 6240 | INGPADBOUNDARY_V(ingpad) | |
f612b815 | 6241 | EGRSTATUSPAGESIZE_V(stat_len != 64)); |
ce8f407a HS |
6242 | t4_set_reg_field(adap, SGE_CONTROL2_A, |
6243 | INGPACKBOUNDARY_V(INGPACKBOUNDARY_M), | |
6244 | INGPACKBOUNDARY_V(fl_align_log - | |
f612b815 | 6245 | INGPACKBOUNDARY_SHIFT_X)); |
ce8f407a | 6246 | } |
636f9d37 VP |
6247 | /* |
6248 | * Adjust various SGE Free List Host Buffer Sizes. | |
6249 | * | |
6250 | * This is something of a crock since we're using fixed indices into | |
6251 | * the array which are also known by the sge.c code and the T4 | |
6252 | * Firmware Configuration File. We need to come up with a much better | |
6253 | * approach to managing this array. For now, the first four entries | |
6254 | * are: | |
6255 | * | |
6256 | * 0: Host Page Size | |
6257 | * 1: 64KB | |
6258 | * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode) | |
6259 | * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode) | |
6260 | * | |
6261 | * For the single-MTU buffers in unpacked mode we need to include | |
6262 | * space for the SGE Control Packet Shift, 14 byte Ethernet header, | |
6263 | * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet | |
dbedd44e | 6264 | * Padding boundary. All of these are accommodated in the Factory |
636f9d37 VP |
6265 | * Default Firmware Configuration File but we need to adjust it for |
6266 | * this host's cache line size. | |
6267 | */ | |
f612b815 HS |
6268 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); |
6269 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, | |
6270 | (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) | |
636f9d37 | 6271 | & ~(fl_align-1)); |
f612b815 HS |
6272 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, |
6273 | (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) | |
636f9d37 VP |
6274 | & ~(fl_align-1)); |
6275 | ||
0d804338 | 6276 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); |
636f9d37 VP |
6277 | |
6278 | return 0; | |
6279 | } | |
6280 | ||
6281 | /** | |
6282 | * t4_fw_initialize - ask FW to initialize the device | |
6283 | * @adap: the adapter | |
6284 | * @mbox: mailbox to use for the FW command | |
6285 | * | |
6286 | * Issues a command to FW to partially initialize the device. This | |
6287 | * performs initialization that generally doesn't depend on user input. | |
6288 | */ | |
6289 | int t4_fw_initialize(struct adapter *adap, unsigned int mbox) | |
6290 | { | |
6291 | struct fw_initialize_cmd c; | |
6292 | ||
6293 | memset(&c, 0, sizeof(c)); | |
6294 | INIT_CMD(c, INITIALIZE, WRITE); | |
6295 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
6296 | } | |
6297 | ||
56d36be4 | 6298 | /** |
01b69614 | 6299 | * t4_query_params_rw - query FW or device parameters |
56d36be4 DM |
6300 | * @adap: the adapter |
6301 | * @mbox: mailbox to use for the FW command | |
6302 | * @pf: the PF | |
6303 | * @vf: the VF | |
6304 | * @nparams: the number of parameters | |
6305 | * @params: the parameter names | |
6306 | * @val: the parameter values | |
01b69614 | 6307 | * @rw: Write and read flag |
56d36be4 DM |
6308 | * |
6309 | * Reads the value of FW or device parameters. Up to 7 parameters can be | |
6310 | * queried at once. | |
6311 | */ | |
01b69614 HS |
6312 | int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, |
6313 | unsigned int vf, unsigned int nparams, const u32 *params, | |
6314 | u32 *val, int rw) | |
56d36be4 DM |
6315 | { |
6316 | int i, ret; | |
6317 | struct fw_params_cmd c; | |
6318 | __be32 *p = &c.param[0].mnem; | |
6319 | ||
6320 | if (nparams > 7) | |
6321 | return -EINVAL; | |
6322 | ||
6323 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6324 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | |
6325 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
6326 | FW_PARAMS_CMD_PFN_V(pf) | | |
6327 | FW_PARAMS_CMD_VFN_V(vf)); | |
6328 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
6329 | ||
01b69614 HS |
6330 | for (i = 0; i < nparams; i++) { |
6331 | *p++ = cpu_to_be32(*params++); | |
6332 | if (rw) | |
6333 | *p = cpu_to_be32(*(val + i)); | |
6334 | p++; | |
6335 | } | |
56d36be4 DM |
6336 | |
6337 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
6338 | if (ret == 0) | |
6339 | for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) | |
f404f80c | 6340 | *val++ = be32_to_cpu(*p); |
56d36be4 DM |
6341 | return ret; |
6342 | } | |
6343 | ||
01b69614 HS |
6344 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, |
6345 | unsigned int vf, unsigned int nparams, const u32 *params, | |
6346 | u32 *val) | |
6347 | { | |
6348 | return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); | |
6349 | } | |
6350 | ||
688848b1 | 6351 | /** |
01b69614 | 6352 | * t4_set_params_timeout - sets FW or device parameters |
688848b1 AB |
6353 | * @adap: the adapter |
6354 | * @mbox: mailbox to use for the FW command | |
6355 | * @pf: the PF | |
6356 | * @vf: the VF | |
6357 | * @nparams: the number of parameters | |
6358 | * @params: the parameter names | |
6359 | * @val: the parameter values | |
01b69614 | 6360 | * @timeout: the timeout time |
688848b1 | 6361 | * |
688848b1 AB |
6362 | * Sets the value of FW or device parameters. Up to 7 parameters can be |
6363 | * specified at once. | |
6364 | */ | |
01b69614 | 6365 | int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, |
688848b1 AB |
6366 | unsigned int pf, unsigned int vf, |
6367 | unsigned int nparams, const u32 *params, | |
01b69614 | 6368 | const u32 *val, int timeout) |
688848b1 AB |
6369 | { |
6370 | struct fw_params_cmd c; | |
6371 | __be32 *p = &c.param[0].mnem; | |
6372 | ||
6373 | if (nparams > 7) | |
6374 | return -EINVAL; | |
6375 | ||
6376 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 6377 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | |
01b69614 HS |
6378 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | |
6379 | FW_PARAMS_CMD_PFN_V(pf) | | |
6380 | FW_PARAMS_CMD_VFN_V(vf)); | |
688848b1 AB |
6381 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); |
6382 | ||
6383 | while (nparams--) { | |
6384 | *p++ = cpu_to_be32(*params++); | |
6385 | *p++ = cpu_to_be32(*val++); | |
6386 | } | |
6387 | ||
01b69614 | 6388 | return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); |
688848b1 AB |
6389 | } |
6390 | ||
56d36be4 DM |
6391 | /** |
6392 | * t4_set_params - sets FW or device parameters | |
6393 | * @adap: the adapter | |
6394 | * @mbox: mailbox to use for the FW command | |
6395 | * @pf: the PF | |
6396 | * @vf: the VF | |
6397 | * @nparams: the number of parameters | |
6398 | * @params: the parameter names | |
6399 | * @val: the parameter values | |
6400 | * | |
6401 | * Sets the value of FW or device parameters. Up to 7 parameters can be | |
6402 | * specified at once. | |
6403 | */ | |
6404 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6405 | unsigned int vf, unsigned int nparams, const u32 *params, | |
6406 | const u32 *val) | |
6407 | { | |
01b69614 HS |
6408 | return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, |
6409 | FW_CMD_MAX_TIMEOUT); | |
56d36be4 DM |
6410 | } |
6411 | ||
6412 | /** | |
6413 | * t4_cfg_pfvf - configure PF/VF resource limits | |
6414 | * @adap: the adapter | |
6415 | * @mbox: mailbox to use for the FW command | |
6416 | * @pf: the PF being configured | |
6417 | * @vf: the VF being configured | |
6418 | * @txq: the max number of egress queues | |
6419 | * @txq_eth_ctrl: the max number of egress Ethernet or control queues | |
6420 | * @rxqi: the max number of interrupt-capable ingress queues | |
6421 | * @rxq: the max number of interruptless ingress queues | |
6422 | * @tc: the PCI traffic class | |
6423 | * @vi: the max number of virtual interfaces | |
6424 | * @cmask: the channel access rights mask for the PF/VF | |
6425 | * @pmask: the port access rights mask for the PF/VF | |
6426 | * @nexact: the maximum number of exact MPS filters | |
6427 | * @rcaps: read capabilities | |
6428 | * @wxcaps: write/execute capabilities | |
6429 | * | |
6430 | * Configures resource limits and capabilities for a physical or virtual | |
6431 | * function. | |
6432 | */ | |
6433 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6434 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
6435 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
6436 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
6437 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) | |
6438 | { | |
6439 | struct fw_pfvf_cmd c; | |
6440 | ||
6441 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6442 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F | |
6443 | FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) | | |
6444 | FW_PFVF_CMD_VFN_V(vf)); | |
6445 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
6446 | c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) | | |
6447 | FW_PFVF_CMD_NIQ_V(rxq)); | |
6448 | c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) | | |
6449 | FW_PFVF_CMD_PMASK_V(pmask) | | |
6450 | FW_PFVF_CMD_NEQ_V(txq)); | |
6451 | c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) | | |
6452 | FW_PFVF_CMD_NVI_V(vi) | | |
6453 | FW_PFVF_CMD_NEXACTF_V(nexact)); | |
6454 | c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) | | |
6455 | FW_PFVF_CMD_WX_CAPS_V(wxcaps) | | |
6456 | FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl)); | |
56d36be4 DM |
6457 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
6458 | } | |
6459 | ||
6460 | /** | |
6461 | * t4_alloc_vi - allocate a virtual interface | |
6462 | * @adap: the adapter | |
6463 | * @mbox: mailbox to use for the FW command | |
6464 | * @port: physical port associated with the VI | |
6465 | * @pf: the PF owning the VI | |
6466 | * @vf: the VF owning the VI | |
6467 | * @nmac: number of MAC addresses needed (1 to 5) | |
6468 | * @mac: the MAC addresses of the VI | |
6469 | * @rss_size: size of RSS table slice associated with this VI | |
6470 | * | |
6471 | * Allocates a virtual interface for the given physical port. If @mac is | |
6472 | * not %NULL it contains the MAC addresses of the VI as assigned by FW. | |
6473 | * @mac should be large enough to hold @nmac Ethernet addresses, they are | |
6474 | * stored consecutively so the space needed is @nmac * 6 bytes. | |
6475 | * Returns a negative error number or the non-negative VI id. | |
6476 | */ | |
6477 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
6478 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
6479 | unsigned int *rss_size) | |
6480 | { | |
6481 | int ret; | |
6482 | struct fw_vi_cmd c; | |
6483 | ||
6484 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6485 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F | |
6486 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
6487 | FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf)); | |
6488 | c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c)); | |
2b5fb1f2 | 6489 | c.portid_pkd = FW_VI_CMD_PORTID_V(port); |
56d36be4 DM |
6490 | c.nmac = nmac - 1; |
6491 | ||
6492 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
6493 | if (ret) | |
6494 | return ret; | |
6495 | ||
6496 | if (mac) { | |
6497 | memcpy(mac, c.mac, sizeof(c.mac)); | |
6498 | switch (nmac) { | |
6499 | case 5: | |
6500 | memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); | |
6501 | case 4: | |
6502 | memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); | |
6503 | case 3: | |
6504 | memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); | |
6505 | case 2: | |
6506 | memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); | |
6507 | } | |
6508 | } | |
6509 | if (rss_size) | |
f404f80c HS |
6510 | *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd)); |
6511 | return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid)); | |
56d36be4 DM |
6512 | } |
6513 | ||
4f3a0fcf HS |
6514 | /** |
6515 | * t4_free_vi - free a virtual interface | |
6516 | * @adap: the adapter | |
6517 | * @mbox: mailbox to use for the FW command | |
6518 | * @pf: the PF owning the VI | |
6519 | * @vf: the VF owning the VI | |
6520 | * @viid: virtual interface identifiler | |
6521 | * | |
6522 | * Free a previously allocated virtual interface. | |
6523 | */ | |
6524 | int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6525 | unsigned int vf, unsigned int viid) | |
6526 | { | |
6527 | struct fw_vi_cmd c; | |
6528 | ||
6529 | memset(&c, 0, sizeof(c)); | |
6530 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | | |
6531 | FW_CMD_REQUEST_F | | |
6532 | FW_CMD_EXEC_F | | |
6533 | FW_VI_CMD_PFN_V(pf) | | |
6534 | FW_VI_CMD_VFN_V(vf)); | |
6535 | c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c)); | |
6536 | c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid)); | |
6537 | ||
6538 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
56d36be4 DM |
6539 | } |
6540 | ||
56d36be4 DM |
6541 | /** |
6542 | * t4_set_rxmode - set Rx properties of a virtual interface | |
6543 | * @adap: the adapter | |
6544 | * @mbox: mailbox to use for the FW command | |
6545 | * @viid: the VI id | |
6546 | * @mtu: the new MTU or -1 | |
6547 | * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change | |
6548 | * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change | |
6549 | * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change | |
f8f5aafa | 6550 | * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change |
56d36be4 DM |
6551 | * @sleep_ok: if true we may sleep while awaiting command completion |
6552 | * | |
6553 | * Sets Rx properties of a virtual interface. | |
6554 | */ | |
6555 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
f8f5aafa DM |
6556 | int mtu, int promisc, int all_multi, int bcast, int vlanex, |
6557 | bool sleep_ok) | |
56d36be4 DM |
6558 | { |
6559 | struct fw_vi_rxmode_cmd c; | |
6560 | ||
6561 | /* convert to FW values */ | |
6562 | if (mtu < 0) | |
6563 | mtu = FW_RXMODE_MTU_NO_CHG; | |
6564 | if (promisc < 0) | |
2b5fb1f2 | 6565 | promisc = FW_VI_RXMODE_CMD_PROMISCEN_M; |
56d36be4 | 6566 | if (all_multi < 0) |
2b5fb1f2 | 6567 | all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M; |
56d36be4 | 6568 | if (bcast < 0) |
2b5fb1f2 | 6569 | bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M; |
f8f5aafa | 6570 | if (vlanex < 0) |
2b5fb1f2 | 6571 | vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M; |
56d36be4 DM |
6572 | |
6573 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6574 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | |
6575 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
6576 | FW_VI_RXMODE_CMD_VIID_V(viid)); | |
6577 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
6578 | c.mtu_to_vlanexen = | |
6579 | cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) | | |
6580 | FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) | | |
6581 | FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) | | |
6582 | FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) | | |
6583 | FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex)); | |
56d36be4 DM |
6584 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); |
6585 | } | |
6586 | ||
6587 | /** | |
6588 | * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses | |
6589 | * @adap: the adapter | |
6590 | * @mbox: mailbox to use for the FW command | |
6591 | * @viid: the VI id | |
6592 | * @free: if true any existing filters for this VI id are first removed | |
6593 | * @naddr: the number of MAC addresses to allocate filters for (up to 7) | |
6594 | * @addr: the MAC address(es) | |
6595 | * @idx: where to store the index of each allocated filter | |
6596 | * @hash: pointer to hash address filter bitmap | |
6597 | * @sleep_ok: call is allowed to sleep | |
6598 | * | |
6599 | * Allocates an exact-match filter for each of the supplied addresses and | |
6600 | * sets it to the corresponding address. If @idx is not %NULL it should | |
6601 | * have at least @naddr entries, each of which will be set to the index of | |
6602 | * the filter allocated for the corresponding MAC address. If a filter | |
6603 | * could not be allocated for an address its index is set to 0xffff. | |
6604 | * If @hash is not %NULL addresses that fail to allocate an exact filter | |
6605 | * are hashed and update the hash filter bitmap pointed at by @hash. | |
6606 | * | |
6607 | * Returns a negative error number or the number of filters allocated. | |
6608 | */ | |
6609 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, | |
6610 | unsigned int viid, bool free, unsigned int naddr, | |
6611 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) | |
6612 | { | |
3ccc6cf7 | 6613 | int offset, ret = 0; |
56d36be4 | 6614 | struct fw_vi_mac_cmd c; |
3ccc6cf7 HS |
6615 | unsigned int nfilters = 0; |
6616 | unsigned int max_naddr = adap->params.arch.mps_tcam_size; | |
6617 | unsigned int rem = naddr; | |
56d36be4 | 6618 | |
3ccc6cf7 | 6619 | if (naddr > max_naddr) |
56d36be4 DM |
6620 | return -EINVAL; |
6621 | ||
3ccc6cf7 HS |
6622 | for (offset = 0; offset < naddr ; /**/) { |
6623 | unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ? | |
6624 | rem : ARRAY_SIZE(c.u.exact)); | |
6625 | size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, | |
6626 | u.exact[fw_naddr]), 16); | |
6627 | struct fw_vi_mac_exact *p; | |
6628 | int i; | |
56d36be4 | 6629 | |
3ccc6cf7 HS |
6630 | memset(&c, 0, sizeof(c)); |
6631 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | | |
6632 | FW_CMD_REQUEST_F | | |
6633 | FW_CMD_WRITE_F | | |
6634 | FW_CMD_EXEC_V(free) | | |
6635 | FW_VI_MAC_CMD_VIID_V(viid)); | |
6636 | c.freemacs_to_len16 = | |
6637 | cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) | | |
6638 | FW_CMD_LEN16_V(len16)); | |
6639 | ||
6640 | for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { | |
6641 | p->valid_to_idx = | |
6642 | cpu_to_be16(FW_VI_MAC_CMD_VALID_F | | |
6643 | FW_VI_MAC_CMD_IDX_V( | |
6644 | FW_VI_MAC_ADD_MAC)); | |
6645 | memcpy(p->macaddr, addr[offset + i], | |
6646 | sizeof(p->macaddr)); | |
6647 | } | |
56d36be4 | 6648 | |
3ccc6cf7 HS |
6649 | /* It's okay if we run out of space in our MAC address arena. |
6650 | * Some of the addresses we submit may get stored so we need | |
6651 | * to run through the reply to see what the results were ... | |
6652 | */ | |
6653 | ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); | |
6654 | if (ret && ret != -FW_ENOMEM) | |
6655 | break; | |
56d36be4 | 6656 | |
3ccc6cf7 HS |
6657 | for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { |
6658 | u16 index = FW_VI_MAC_CMD_IDX_G( | |
6659 | be16_to_cpu(p->valid_to_idx)); | |
6660 | ||
6661 | if (idx) | |
6662 | idx[offset + i] = (index >= max_naddr ? | |
6663 | 0xffff : index); | |
6664 | if (index < max_naddr) | |
6665 | nfilters++; | |
6666 | else if (hash) | |
6667 | *hash |= (1ULL << | |
6668 | hash_mac_addr(addr[offset + i])); | |
6669 | } | |
56d36be4 | 6670 | |
3ccc6cf7 HS |
6671 | free = false; |
6672 | offset += fw_naddr; | |
6673 | rem -= fw_naddr; | |
56d36be4 | 6674 | } |
3ccc6cf7 HS |
6675 | |
6676 | if (ret == 0 || ret == -FW_ENOMEM) | |
6677 | ret = nfilters; | |
56d36be4 DM |
6678 | return ret; |
6679 | } | |
6680 | ||
6681 | /** | |
6682 | * t4_change_mac - modifies the exact-match filter for a MAC address | |
6683 | * @adap: the adapter | |
6684 | * @mbox: mailbox to use for the FW command | |
6685 | * @viid: the VI id | |
6686 | * @idx: index of existing filter for old value of MAC address, or -1 | |
6687 | * @addr: the new MAC address value | |
6688 | * @persist: whether a new MAC allocation should be persistent | |
6689 | * @add_smt: if true also add the address to the HW SMT | |
6690 | * | |
6691 | * Modifies an exact-match filter and sets it to the new MAC address. | |
6692 | * Note that in general it is not possible to modify the value of a given | |
6693 | * filter so the generic way to modify an address filter is to free the one | |
6694 | * being used by the old address value and allocate a new filter for the | |
6695 | * new address value. @idx can be -1 if the address is a new addition. | |
6696 | * | |
6697 | * Returns a negative error number or the index of the filter with the new | |
6698 | * MAC value. | |
6699 | */ | |
6700 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
6701 | int idx, const u8 *addr, bool persist, bool add_smt) | |
6702 | { | |
6703 | int ret, mode; | |
6704 | struct fw_vi_mac_cmd c; | |
6705 | struct fw_vi_mac_exact *p = c.u.exact; | |
3ccc6cf7 | 6706 | unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; |
56d36be4 DM |
6707 | |
6708 | if (idx < 0) /* new allocation */ | |
6709 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; | |
6710 | mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; | |
6711 | ||
6712 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6713 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | |
6714 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
6715 | FW_VI_MAC_CMD_VIID_V(viid)); | |
6716 | c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1)); | |
6717 | p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | | |
6718 | FW_VI_MAC_CMD_SMAC_RESULT_V(mode) | | |
6719 | FW_VI_MAC_CMD_IDX_V(idx)); | |
56d36be4 DM |
6720 | memcpy(p->macaddr, addr, sizeof(p->macaddr)); |
6721 | ||
6722 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
6723 | if (ret == 0) { | |
f404f80c | 6724 | ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); |
0a57a536 | 6725 | if (ret >= max_mac_addr) |
56d36be4 DM |
6726 | ret = -ENOMEM; |
6727 | } | |
6728 | return ret; | |
6729 | } | |
6730 | ||
6731 | /** | |
6732 | * t4_set_addr_hash - program the MAC inexact-match hash filter | |
6733 | * @adap: the adapter | |
6734 | * @mbox: mailbox to use for the FW command | |
6735 | * @viid: the VI id | |
6736 | * @ucast: whether the hash filter should also match unicast addresses | |
6737 | * @vec: the value to be written to the hash filter | |
6738 | * @sleep_ok: call is allowed to sleep | |
6739 | * | |
6740 | * Sets the 64-bit inexact-match hash filter for a virtual interface. | |
6741 | */ | |
6742 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
6743 | bool ucast, u64 vec, bool sleep_ok) | |
6744 | { | |
6745 | struct fw_vi_mac_cmd c; | |
6746 | ||
6747 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6748 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | |
6749 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
6750 | FW_VI_ENABLE_CMD_VIID_V(viid)); | |
6751 | c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F | | |
6752 | FW_VI_MAC_CMD_HASHUNIEN_V(ucast) | | |
6753 | FW_CMD_LEN16_V(1)); | |
56d36be4 DM |
6754 | c.u.hash.hashvec = cpu_to_be64(vec); |
6755 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); | |
6756 | } | |
6757 | ||
688848b1 AB |
6758 | /** |
6759 | * t4_enable_vi_params - enable/disable a virtual interface | |
6760 | * @adap: the adapter | |
6761 | * @mbox: mailbox to use for the FW command | |
6762 | * @viid: the VI id | |
6763 | * @rx_en: 1=enable Rx, 0=disable Rx | |
6764 | * @tx_en: 1=enable Tx, 0=disable Tx | |
6765 | * @dcb_en: 1=enable delivery of Data Center Bridging messages. | |
6766 | * | |
6767 | * Enables/disables a virtual interface. Note that setting DCB Enable | |
6768 | * only makes sense when enabling a Virtual Interface ... | |
6769 | */ | |
6770 | int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, | |
6771 | unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) | |
6772 | { | |
6773 | struct fw_vi_enable_cmd c; | |
6774 | ||
6775 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6776 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | |
6777 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6778 | FW_VI_ENABLE_CMD_VIID_V(viid)); | |
6779 | c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) | | |
6780 | FW_VI_ENABLE_CMD_EEN_V(tx_en) | | |
6781 | FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) | | |
6782 | FW_LEN16(c)); | |
30f00847 | 6783 | return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); |
688848b1 AB |
6784 | } |
6785 | ||
56d36be4 DM |
6786 | /** |
6787 | * t4_enable_vi - enable/disable a virtual interface | |
6788 | * @adap: the adapter | |
6789 | * @mbox: mailbox to use for the FW command | |
6790 | * @viid: the VI id | |
6791 | * @rx_en: 1=enable Rx, 0=disable Rx | |
6792 | * @tx_en: 1=enable Tx, 0=disable Tx | |
6793 | * | |
6794 | * Enables/disables a virtual interface. | |
6795 | */ | |
6796 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
6797 | bool rx_en, bool tx_en) | |
6798 | { | |
688848b1 | 6799 | return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); |
56d36be4 DM |
6800 | } |
6801 | ||
6802 | /** | |
6803 | * t4_identify_port - identify a VI's port by blinking its LED | |
6804 | * @adap: the adapter | |
6805 | * @mbox: mailbox to use for the FW command | |
6806 | * @viid: the VI id | |
6807 | * @nblinks: how many times to blink LED at 2.5 Hz | |
6808 | * | |
6809 | * Identifies a VI's port by blinking its LED. | |
6810 | */ | |
6811 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
6812 | unsigned int nblinks) | |
6813 | { | |
6814 | struct fw_vi_enable_cmd c; | |
6815 | ||
0062b15c | 6816 | memset(&c, 0, sizeof(c)); |
f404f80c HS |
6817 | c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | |
6818 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6819 | FW_VI_ENABLE_CMD_VIID_V(viid)); | |
6820 | c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c)); | |
6821 | c.blinkdur = cpu_to_be16(nblinks); | |
56d36be4 | 6822 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
56d36be4 DM |
6823 | } |
6824 | ||
6825 | /** | |
6826 | * t4_iq_free - free an ingress queue and its FLs | |
6827 | * @adap: the adapter | |
6828 | * @mbox: mailbox to use for the FW command | |
6829 | * @pf: the PF owning the queues | |
6830 | * @vf: the VF owning the queues | |
6831 | * @iqtype: the ingress queue type | |
6832 | * @iqid: ingress queue id | |
6833 | * @fl0id: FL0 queue id or 0xffff if no attached FL0 | |
6834 | * @fl1id: FL1 queue id or 0xffff if no attached FL1 | |
6835 | * | |
6836 | * Frees an ingress queue and its associated FLs, if any. | |
6837 | */ | |
6838 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6839 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
6840 | unsigned int fl0id, unsigned int fl1id) | |
6841 | { | |
6842 | struct fw_iq_cmd c; | |
6843 | ||
6844 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6845 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | |
6846 | FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) | | |
6847 | FW_IQ_CMD_VFN_V(vf)); | |
6848 | c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c)); | |
6849 | c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype)); | |
6850 | c.iqid = cpu_to_be16(iqid); | |
6851 | c.fl0id = cpu_to_be16(fl0id); | |
6852 | c.fl1id = cpu_to_be16(fl1id); | |
56d36be4 DM |
6853 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
6854 | } | |
6855 | ||
6856 | /** | |
6857 | * t4_eth_eq_free - free an Ethernet egress queue | |
6858 | * @adap: the adapter | |
6859 | * @mbox: mailbox to use for the FW command | |
6860 | * @pf: the PF owning the queue | |
6861 | * @vf: the VF owning the queue | |
6862 | * @eqid: egress queue id | |
6863 | * | |
6864 | * Frees an Ethernet egress queue. | |
6865 | */ | |
6866 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6867 | unsigned int vf, unsigned int eqid) | |
6868 | { | |
6869 | struct fw_eq_eth_cmd c; | |
6870 | ||
6871 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6872 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) | |
6873 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6874 | FW_EQ_ETH_CMD_PFN_V(pf) | | |
6875 | FW_EQ_ETH_CMD_VFN_V(vf)); | |
6876 | c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c)); | |
6877 | c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid)); | |
56d36be4 DM |
6878 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
6879 | } | |
6880 | ||
6881 | /** | |
6882 | * t4_ctrl_eq_free - free a control egress queue | |
6883 | * @adap: the adapter | |
6884 | * @mbox: mailbox to use for the FW command | |
6885 | * @pf: the PF owning the queue | |
6886 | * @vf: the VF owning the queue | |
6887 | * @eqid: egress queue id | |
6888 | * | |
6889 | * Frees a control egress queue. | |
6890 | */ | |
6891 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6892 | unsigned int vf, unsigned int eqid) | |
6893 | { | |
6894 | struct fw_eq_ctrl_cmd c; | |
6895 | ||
6896 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6897 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | |
6898 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6899 | FW_EQ_CTRL_CMD_PFN_V(pf) | | |
6900 | FW_EQ_CTRL_CMD_VFN_V(vf)); | |
6901 | c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c)); | |
6902 | c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid)); | |
56d36be4 DM |
6903 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
6904 | } | |
6905 | ||
6906 | /** | |
6907 | * t4_ofld_eq_free - free an offload egress queue | |
6908 | * @adap: the adapter | |
6909 | * @mbox: mailbox to use for the FW command | |
6910 | * @pf: the PF owning the queue | |
6911 | * @vf: the VF owning the queue | |
6912 | * @eqid: egress queue id | |
6913 | * | |
6914 | * Frees a control egress queue. | |
6915 | */ | |
6916 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
6917 | unsigned int vf, unsigned int eqid) | |
6918 | { | |
6919 | struct fw_eq_ofld_cmd c; | |
6920 | ||
6921 | memset(&c, 0, sizeof(c)); | |
f404f80c HS |
6922 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | |
6923 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6924 | FW_EQ_OFLD_CMD_PFN_V(pf) | | |
6925 | FW_EQ_OFLD_CMD_VFN_V(vf)); | |
6926 | c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c)); | |
6927 | c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid)); | |
56d36be4 DM |
6928 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
6929 | } | |
6930 | ||
6931 | /** | |
6932 | * t4_handle_fw_rpl - process a FW reply message | |
6933 | * @adap: the adapter | |
6934 | * @rpl: start of the FW message | |
6935 | * | |
6936 | * Processes a FW message, such as link state change messages. | |
6937 | */ | |
6938 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) | |
6939 | { | |
6940 | u8 opcode = *(const u8 *)rpl; | |
6941 | ||
6942 | if (opcode == FW_PORT_CMD) { /* link/module state change message */ | |
6943 | int speed = 0, fc = 0; | |
6944 | const struct fw_port_cmd *p = (void *)rpl; | |
f404f80c | 6945 | int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid)); |
56d36be4 DM |
6946 | int port = adap->chan_map[chan]; |
6947 | struct port_info *pi = adap2pinfo(adap, port); | |
6948 | struct link_config *lc = &pi->link_cfg; | |
f404f80c | 6949 | u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); |
2b5fb1f2 HS |
6950 | int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0; |
6951 | u32 mod = FW_PORT_CMD_MODTYPE_G(stat); | |
56d36be4 | 6952 | |
2b5fb1f2 | 6953 | if (stat & FW_PORT_CMD_RXPAUSE_F) |
56d36be4 | 6954 | fc |= PAUSE_RX; |
2b5fb1f2 | 6955 | if (stat & FW_PORT_CMD_TXPAUSE_F) |
56d36be4 | 6956 | fc |= PAUSE_TX; |
2b5fb1f2 | 6957 | if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M)) |
e8b39015 | 6958 | speed = 100; |
2b5fb1f2 | 6959 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G)) |
e8b39015 | 6960 | speed = 1000; |
2b5fb1f2 | 6961 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G)) |
e8b39015 | 6962 | speed = 10000; |
2b5fb1f2 | 6963 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G)) |
e8b39015 | 6964 | speed = 40000; |
56d36be4 DM |
6965 | |
6966 | if (link_ok != lc->link_ok || speed != lc->speed || | |
6967 | fc != lc->fc) { /* something changed */ | |
6968 | lc->link_ok = link_ok; | |
6969 | lc->speed = speed; | |
6970 | lc->fc = fc; | |
444018a7 | 6971 | lc->supported = be16_to_cpu(p->u.info.pcap); |
56d36be4 DM |
6972 | t4_os_link_changed(adap, port, link_ok); |
6973 | } | |
6974 | if (mod != pi->mod_type) { | |
6975 | pi->mod_type = mod; | |
6976 | t4_os_portmod_changed(adap, port); | |
6977 | } | |
6978 | } | |
6979 | return 0; | |
6980 | } | |
6981 | ||
1dd06ae8 | 6982 | static void get_pci_mode(struct adapter *adapter, struct pci_params *p) |
56d36be4 DM |
6983 | { |
6984 | u16 val; | |
56d36be4 | 6985 | |
e5c8ae5f JL |
6986 | if (pci_is_pcie(adapter->pdev)) { |
6987 | pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); | |
56d36be4 DM |
6988 | p->speed = val & PCI_EXP_LNKSTA_CLS; |
6989 | p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; | |
6990 | } | |
6991 | } | |
6992 | ||
6993 | /** | |
6994 | * init_link_config - initialize a link's SW state | |
6995 | * @lc: structure holding the link state | |
6996 | * @caps: link capabilities | |
6997 | * | |
6998 | * Initializes the SW state maintained for each link, including the link's | |
6999 | * capabilities and default speed/flow-control/autonegotiation settings. | |
7000 | */ | |
1dd06ae8 | 7001 | static void init_link_config(struct link_config *lc, unsigned int caps) |
56d36be4 DM |
7002 | { |
7003 | lc->supported = caps; | |
7004 | lc->requested_speed = 0; | |
7005 | lc->speed = 0; | |
7006 | lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; | |
7007 | if (lc->supported & FW_PORT_CAP_ANEG) { | |
7008 | lc->advertising = lc->supported & ADVERT_MASK; | |
7009 | lc->autoneg = AUTONEG_ENABLE; | |
7010 | lc->requested_fc |= PAUSE_AUTONEG; | |
7011 | } else { | |
7012 | lc->advertising = 0; | |
7013 | lc->autoneg = AUTONEG_DISABLE; | |
7014 | } | |
7015 | } | |
7016 | ||
8203b509 HS |
7017 | #define CIM_PF_NOACCESS 0xeeeeeeee |
7018 | ||
7019 | int t4_wait_dev_ready(void __iomem *regs) | |
56d36be4 | 7020 | { |
8203b509 HS |
7021 | u32 whoami; |
7022 | ||
0d804338 | 7023 | whoami = readl(regs + PL_WHOAMI_A); |
8203b509 | 7024 | if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS) |
56d36be4 | 7025 | return 0; |
8203b509 | 7026 | |
56d36be4 | 7027 | msleep(500); |
0d804338 | 7028 | whoami = readl(regs + PL_WHOAMI_A); |
8203b509 | 7029 | return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); |
56d36be4 DM |
7030 | } |
7031 | ||
fe2ee139 HS |
7032 | struct flash_desc { |
7033 | u32 vendor_and_model_id; | |
7034 | u32 size_mb; | |
7035 | }; | |
7036 | ||
91744948 | 7037 | static int get_flash_params(struct adapter *adap) |
900a6596 | 7038 | { |
fe2ee139 HS |
7039 | /* Table for non-Numonix supported flash parts. Numonix parts are left |
7040 | * to the preexisting code. All flash parts have 64KB sectors. | |
7041 | */ | |
7042 | static struct flash_desc supported_flash[] = { | |
7043 | { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ | |
7044 | }; | |
7045 | ||
900a6596 DM |
7046 | int ret; |
7047 | u32 info; | |
7048 | ||
7049 | ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); | |
7050 | if (!ret) | |
7051 | ret = sf1_read(adap, 3, 0, 1, &info); | |
0d804338 | 7052 | t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ |
900a6596 DM |
7053 | if (ret) |
7054 | return ret; | |
7055 | ||
fe2ee139 HS |
7056 | for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret) |
7057 | if (supported_flash[ret].vendor_and_model_id == info) { | |
7058 | adap->params.sf_size = supported_flash[ret].size_mb; | |
7059 | adap->params.sf_nsec = | |
7060 | adap->params.sf_size / SF_SEC_SIZE; | |
7061 | return 0; | |
7062 | } | |
7063 | ||
900a6596 DM |
7064 | if ((info & 0xff) != 0x20) /* not a Numonix flash */ |
7065 | return -EINVAL; | |
7066 | info >>= 16; /* log2 of size */ | |
7067 | if (info >= 0x14 && info < 0x18) | |
7068 | adap->params.sf_nsec = 1 << (info - 16); | |
7069 | else if (info == 0x18) | |
7070 | adap->params.sf_nsec = 64; | |
7071 | else | |
7072 | return -EINVAL; | |
7073 | adap->params.sf_size = 1 << info; | |
7074 | adap->params.sf_fw_start = | |
89c3a86c | 7075 | t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; |
c290607e HS |
7076 | |
7077 | if (adap->params.sf_size < FLASH_MIN_SIZE) | |
7078 | dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", | |
7079 | adap->params.sf_size, FLASH_MIN_SIZE); | |
900a6596 DM |
7080 | return 0; |
7081 | } | |
7082 | ||
eca0f6ee HS |
7083 | static void set_pcie_completion_timeout(struct adapter *adapter, u8 range) |
7084 | { | |
7085 | u16 val; | |
7086 | u32 pcie_cap; | |
7087 | ||
7088 | pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
7089 | if (pcie_cap) { | |
7090 | pci_read_config_word(adapter->pdev, | |
7091 | pcie_cap + PCI_EXP_DEVCTL2, &val); | |
7092 | val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; | |
7093 | val |= range; | |
7094 | pci_write_config_word(adapter->pdev, | |
7095 | pcie_cap + PCI_EXP_DEVCTL2, val); | |
7096 | } | |
7097 | } | |
7098 | ||
56d36be4 DM |
7099 | /** |
7100 | * t4_prep_adapter - prepare SW and HW for operation | |
7101 | * @adapter: the adapter | |
7102 | * @reset: if true perform a HW reset | |
7103 | * | |
7104 | * Initialize adapter SW state for the various HW modules, set initial | |
7105 | * values for some adapter tunables, take PHYs out of reset, and | |
7106 | * initialize the MDIO interface. | |
7107 | */ | |
91744948 | 7108 | int t4_prep_adapter(struct adapter *adapter) |
56d36be4 | 7109 | { |
0a57a536 SR |
7110 | int ret, ver; |
7111 | uint16_t device_id; | |
d14807dd | 7112 | u32 pl_rev; |
56d36be4 | 7113 | |
56d36be4 | 7114 | get_pci_mode(adapter, &adapter->params.pci); |
0d804338 | 7115 | pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A)); |
56d36be4 | 7116 | |
900a6596 DM |
7117 | ret = get_flash_params(adapter); |
7118 | if (ret < 0) { | |
7119 | dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); | |
7120 | return ret; | |
7121 | } | |
7122 | ||
0a57a536 SR |
7123 | /* Retrieve adapter's device ID |
7124 | */ | |
7125 | pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); | |
7126 | ver = device_id >> 12; | |
d14807dd | 7127 | adapter->params.chip = 0; |
0a57a536 SR |
7128 | switch (ver) { |
7129 | case CHELSIO_T4: | |
d14807dd | 7130 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
3ccc6cf7 HS |
7131 | adapter->params.arch.sge_fl_db = DBPRIO_F; |
7132 | adapter->params.arch.mps_tcam_size = | |
7133 | NUM_MPS_CLS_SRAM_L_INSTANCES; | |
7134 | adapter->params.arch.mps_rplc_size = 128; | |
7135 | adapter->params.arch.nchan = NCHAN; | |
44588560 | 7136 | adapter->params.arch.pm_stats_cnt = PM_NSTATS; |
3ccc6cf7 | 7137 | adapter->params.arch.vfcount = 128; |
0a57a536 SR |
7138 | break; |
7139 | case CHELSIO_T5: | |
d14807dd | 7140 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
3ccc6cf7 HS |
7141 | adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; |
7142 | adapter->params.arch.mps_tcam_size = | |
7143 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | |
7144 | adapter->params.arch.mps_rplc_size = 128; | |
7145 | adapter->params.arch.nchan = NCHAN; | |
44588560 | 7146 | adapter->params.arch.pm_stats_cnt = PM_NSTATS; |
3ccc6cf7 HS |
7147 | adapter->params.arch.vfcount = 128; |
7148 | break; | |
7149 | case CHELSIO_T6: | |
7150 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); | |
7151 | adapter->params.arch.sge_fl_db = 0; | |
7152 | adapter->params.arch.mps_tcam_size = | |
7153 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | |
7154 | adapter->params.arch.mps_rplc_size = 256; | |
7155 | adapter->params.arch.nchan = 2; | |
44588560 | 7156 | adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS; |
3ccc6cf7 | 7157 | adapter->params.arch.vfcount = 256; |
0a57a536 SR |
7158 | break; |
7159 | default: | |
7160 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
7161 | device_id); | |
7162 | return -EINVAL; | |
7163 | } | |
7164 | ||
f1ff24aa | 7165 | adapter->params.cim_la_size = CIMLA_SIZE; |
56d36be4 DM |
7166 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); |
7167 | ||
7168 | /* | |
7169 | * Default port for debugging in case we can't reach FW. | |
7170 | */ | |
7171 | adapter->params.nports = 1; | |
7172 | adapter->params.portvec = 1; | |
636f9d37 | 7173 | adapter->params.vpd.cclk = 50000; |
eca0f6ee HS |
7174 | |
7175 | /* Set pci completion timeout value to 4 seconds. */ | |
7176 | set_pcie_completion_timeout(adapter, 0xd); | |
56d36be4 DM |
7177 | return 0; |
7178 | } | |
7179 | ||
e85c9a7a | 7180 | /** |
b2612722 | 7181 | * t4_bar2_sge_qregs - return BAR2 SGE Queue register information |
e85c9a7a HS |
7182 | * @adapter: the adapter |
7183 | * @qid: the Queue ID | |
7184 | * @qtype: the Ingress or Egress type for @qid | |
66cf188e | 7185 | * @user: true if this request is for a user mode queue |
e85c9a7a HS |
7186 | * @pbar2_qoffset: BAR2 Queue Offset |
7187 | * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues | |
7188 | * | |
7189 | * Returns the BAR2 SGE Queue Registers information associated with the | |
7190 | * indicated Absolute Queue ID. These are passed back in return value | |
7191 | * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue | |
7192 | * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. | |
7193 | * | |
7194 | * This may return an error which indicates that BAR2 SGE Queue | |
7195 | * registers aren't available. If an error is not returned, then the | |
7196 | * following values are returned: | |
7197 | * | |
7198 | * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers | |
7199 | * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid | |
7200 | * | |
7201 | * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which | |
7202 | * require the "Inferred Queue ID" ability may be used. E.g. the | |
7203 | * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, | |
7204 | * then these "Inferred Queue ID" register may not be used. | |
7205 | */ | |
b2612722 | 7206 | int t4_bar2_sge_qregs(struct adapter *adapter, |
e85c9a7a HS |
7207 | unsigned int qid, |
7208 | enum t4_bar2_qtype qtype, | |
66cf188e | 7209 | int user, |
e85c9a7a HS |
7210 | u64 *pbar2_qoffset, |
7211 | unsigned int *pbar2_qid) | |
7212 | { | |
7213 | unsigned int page_shift, page_size, qpp_shift, qpp_mask; | |
7214 | u64 bar2_page_offset, bar2_qoffset; | |
7215 | unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; | |
7216 | ||
66cf188e H |
7217 | /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */ |
7218 | if (!user && is_t4(adapter->params.chip)) | |
e85c9a7a HS |
7219 | return -EINVAL; |
7220 | ||
7221 | /* Get our SGE Page Size parameters. | |
7222 | */ | |
7223 | page_shift = adapter->params.sge.hps + 10; | |
7224 | page_size = 1 << page_shift; | |
7225 | ||
7226 | /* Get the right Queues per Page parameters for our Queue. | |
7227 | */ | |
7228 | qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS | |
7229 | ? adapter->params.sge.eq_qpp | |
7230 | : adapter->params.sge.iq_qpp); | |
7231 | qpp_mask = (1 << qpp_shift) - 1; | |
7232 | ||
7233 | /* Calculate the basics of the BAR2 SGE Queue register area: | |
7234 | * o The BAR2 page the Queue registers will be in. | |
7235 | * o The BAR2 Queue ID. | |
7236 | * o The BAR2 Queue ID Offset into the BAR2 page. | |
7237 | */ | |
513d1a1d | 7238 | bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); |
e85c9a7a HS |
7239 | bar2_qid = qid & qpp_mask; |
7240 | bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; | |
7241 | ||
7242 | /* If the BAR2 Queue ID Offset is less than the Page Size, then the | |
7243 | * hardware will infer the Absolute Queue ID simply from the writes to | |
7244 | * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a | |
7245 | * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply | |
7246 | * write to the first BAR2 SGE Queue Area within the BAR2 Page with | |
7247 | * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID | |
7248 | * from the BAR2 Page and BAR2 Queue ID. | |
7249 | * | |
7250 | * One important censequence of this is that some BAR2 SGE registers | |
7251 | * have a "Queue ID" field and we can write the BAR2 SGE Queue ID | |
7252 | * there. But other registers synthesize the SGE Queue ID purely | |
7253 | * from the writes to the registers -- the Write Combined Doorbell | |
7254 | * Buffer is a good example. These BAR2 SGE Registers are only | |
7255 | * available for those BAR2 SGE Register areas where the SGE Absolute | |
7256 | * Queue ID can be inferred from simple writes. | |
7257 | */ | |
7258 | bar2_qoffset = bar2_page_offset; | |
7259 | bar2_qinferred = (bar2_qid_offset < page_size); | |
7260 | if (bar2_qinferred) { | |
7261 | bar2_qoffset += bar2_qid_offset; | |
7262 | bar2_qid = 0; | |
7263 | } | |
7264 | ||
7265 | *pbar2_qoffset = bar2_qoffset; | |
7266 | *pbar2_qid = bar2_qid; | |
7267 | return 0; | |
7268 | } | |
7269 | ||
ae469b68 HS |
7270 | /** |
7271 | * t4_init_devlog_params - initialize adapter->params.devlog | |
7272 | * @adap: the adapter | |
7273 | * | |
7274 | * Initialize various fields of the adapter's Firmware Device Log | |
7275 | * Parameters structure. | |
7276 | */ | |
7277 | int t4_init_devlog_params(struct adapter *adap) | |
7278 | { | |
7279 | struct devlog_params *dparams = &adap->params.devlog; | |
7280 | u32 pf_dparams; | |
7281 | unsigned int devlog_meminfo; | |
7282 | struct fw_devlog_cmd devlog_cmd; | |
7283 | int ret; | |
7284 | ||
7285 | /* If we're dealing with newer firmware, the Device Log Paramerters | |
7286 | * are stored in a designated register which allows us to access the | |
7287 | * Device Log even if we can't talk to the firmware. | |
7288 | */ | |
7289 | pf_dparams = | |
7290 | t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); | |
7291 | if (pf_dparams) { | |
7292 | unsigned int nentries, nentries128; | |
7293 | ||
7294 | dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams); | |
7295 | dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4; | |
7296 | ||
7297 | nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams); | |
7298 | nentries = (nentries128 + 1) * 128; | |
7299 | dparams->size = nentries * sizeof(struct fw_devlog_e); | |
7300 | ||
7301 | return 0; | |
7302 | } | |
7303 | ||
7304 | /* Otherwise, ask the firmware for it's Device Log Parameters. | |
7305 | */ | |
7306 | memset(&devlog_cmd, 0, sizeof(devlog_cmd)); | |
f404f80c HS |
7307 | devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) | |
7308 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
7309 | devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); | |
ae469b68 HS |
7310 | ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), |
7311 | &devlog_cmd); | |
7312 | if (ret) | |
7313 | return ret; | |
7314 | ||
f404f80c HS |
7315 | devlog_meminfo = |
7316 | be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); | |
ae469b68 HS |
7317 | dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo); |
7318 | dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4; | |
f404f80c | 7319 | dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); |
ae469b68 HS |
7320 | |
7321 | return 0; | |
7322 | } | |
7323 | ||
e85c9a7a HS |
7324 | /** |
7325 | * t4_init_sge_params - initialize adap->params.sge | |
7326 | * @adapter: the adapter | |
7327 | * | |
7328 | * Initialize various fields of the adapter's SGE Parameters structure. | |
7329 | */ | |
7330 | int t4_init_sge_params(struct adapter *adapter) | |
7331 | { | |
7332 | struct sge_params *sge_params = &adapter->params.sge; | |
7333 | u32 hps, qpp; | |
7334 | unsigned int s_hps, s_qpp; | |
7335 | ||
7336 | /* Extract the SGE Page Size for our PF. | |
7337 | */ | |
f612b815 | 7338 | hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A); |
e85c9a7a | 7339 | s_hps = (HOSTPAGESIZEPF0_S + |
b2612722 | 7340 | (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf); |
e85c9a7a HS |
7341 | sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); |
7342 | ||
7343 | /* Extract the SGE Egress and Ingess Queues Per Page for our PF. | |
7344 | */ | |
7345 | s_qpp = (QUEUESPERPAGEPF0_S + | |
b2612722 | 7346 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf); |
f612b815 HS |
7347 | qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); |
7348 | sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); | |
f061de42 | 7349 | qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A); |
f612b815 | 7350 | sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); |
e85c9a7a HS |
7351 | |
7352 | return 0; | |
7353 | } | |
7354 | ||
dcf7b6f5 KS |
7355 | /** |
7356 | * t4_init_tp_params - initialize adap->params.tp | |
7357 | * @adap: the adapter | |
7358 | * | |
7359 | * Initialize various fields of the adapter's TP Parameters structure. | |
7360 | */ | |
7361 | int t4_init_tp_params(struct adapter *adap) | |
7362 | { | |
7363 | int chan; | |
7364 | u32 v; | |
7365 | ||
837e4a42 HS |
7366 | v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); |
7367 | adap->params.tp.tre = TIMERRESOLUTION_G(v); | |
7368 | adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); | |
dcf7b6f5 KS |
7369 | |
7370 | /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ | |
7371 | for (chan = 0; chan < NCHAN; chan++) | |
7372 | adap->params.tp.tx_modq[chan] = chan; | |
7373 | ||
7374 | /* Cache the adapter's Compressed Filter Mode and global Incress | |
7375 | * Configuration. | |
7376 | */ | |
0b2c2a93 | 7377 | if (t4_use_ldst(adap)) { |
c1e9af0c HS |
7378 | t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, |
7379 | TP_VLAN_PRI_MAP_A, 1); | |
7380 | t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, | |
7381 | TP_INGRESS_CONFIG_A, 1); | |
7382 | } else { | |
7383 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
7384 | &adap->params.tp.vlan_pri_map, 1, | |
7385 | TP_VLAN_PRI_MAP_A); | |
7386 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
7387 | &adap->params.tp.ingress_config, 1, | |
7388 | TP_INGRESS_CONFIG_A); | |
7389 | } | |
dcf7b6f5 KS |
7390 | |
7391 | /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field | |
7392 | * shift positions of several elements of the Compressed Filter Tuple | |
7393 | * for this adapter which we need frequently ... | |
7394 | */ | |
0d804338 HS |
7395 | adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); |
7396 | adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); | |
7397 | adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); | |
dcf7b6f5 | 7398 | adap->params.tp.protocol_shift = t4_filter_field_shift(adap, |
0d804338 | 7399 | PROTOCOL_F); |
dcf7b6f5 KS |
7400 | |
7401 | /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID | |
dbedd44e | 7402 | * represents the presence of an Outer VLAN instead of a VNIC ID. |
dcf7b6f5 | 7403 | */ |
0d804338 | 7404 | if ((adap->params.tp.ingress_config & VNIC_F) == 0) |
dcf7b6f5 KS |
7405 | adap->params.tp.vnic_shift = -1; |
7406 | ||
7407 | return 0; | |
7408 | } | |
7409 | ||
7410 | /** | |
7411 | * t4_filter_field_shift - calculate filter field shift | |
7412 | * @adap: the adapter | |
7413 | * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) | |
7414 | * | |
7415 | * Return the shift position of a filter field within the Compressed | |
7416 | * Filter Tuple. The filter field is specified via its selection bit | |
7417 | * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. | |
7418 | */ | |
7419 | int t4_filter_field_shift(const struct adapter *adap, int filter_sel) | |
7420 | { | |
7421 | unsigned int filter_mode = adap->params.tp.vlan_pri_map; | |
7422 | unsigned int sel; | |
7423 | int field_shift; | |
7424 | ||
7425 | if ((filter_mode & filter_sel) == 0) | |
7426 | return -1; | |
7427 | ||
7428 | for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { | |
7429 | switch (filter_mode & sel) { | |
0d804338 HS |
7430 | case FCOE_F: |
7431 | field_shift += FT_FCOE_W; | |
dcf7b6f5 | 7432 | break; |
0d804338 HS |
7433 | case PORT_F: |
7434 | field_shift += FT_PORT_W; | |
dcf7b6f5 | 7435 | break; |
0d804338 HS |
7436 | case VNIC_ID_F: |
7437 | field_shift += FT_VNIC_ID_W; | |
dcf7b6f5 | 7438 | break; |
0d804338 HS |
7439 | case VLAN_F: |
7440 | field_shift += FT_VLAN_W; | |
dcf7b6f5 | 7441 | break; |
0d804338 HS |
7442 | case TOS_F: |
7443 | field_shift += FT_TOS_W; | |
dcf7b6f5 | 7444 | break; |
0d804338 HS |
7445 | case PROTOCOL_F: |
7446 | field_shift += FT_PROTOCOL_W; | |
dcf7b6f5 | 7447 | break; |
0d804338 HS |
7448 | case ETHERTYPE_F: |
7449 | field_shift += FT_ETHERTYPE_W; | |
dcf7b6f5 | 7450 | break; |
0d804338 HS |
7451 | case MACMATCH_F: |
7452 | field_shift += FT_MACMATCH_W; | |
dcf7b6f5 | 7453 | break; |
0d804338 HS |
7454 | case MPSHITTYPE_F: |
7455 | field_shift += FT_MPSHITTYPE_W; | |
dcf7b6f5 | 7456 | break; |
0d804338 HS |
7457 | case FRAGMENTATION_F: |
7458 | field_shift += FT_FRAGMENTATION_W; | |
dcf7b6f5 KS |
7459 | break; |
7460 | } | |
7461 | } | |
7462 | return field_shift; | |
7463 | } | |
7464 | ||
c035e183 HS |
7465 | int t4_init_rss_mode(struct adapter *adap, int mbox) |
7466 | { | |
7467 | int i, ret; | |
7468 | struct fw_rss_vi_config_cmd rvc; | |
7469 | ||
7470 | memset(&rvc, 0, sizeof(rvc)); | |
7471 | ||
7472 | for_each_port(adap, i) { | |
7473 | struct port_info *p = adap2pinfo(adap, i); | |
7474 | ||
f404f80c HS |
7475 | rvc.op_to_viid = |
7476 | cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | | |
7477 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
7478 | FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid)); | |
7479 | rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); | |
c035e183 HS |
7480 | ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); |
7481 | if (ret) | |
7482 | return ret; | |
f404f80c | 7483 | p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); |
c035e183 HS |
7484 | } |
7485 | return 0; | |
7486 | } | |
7487 | ||
91744948 | 7488 | int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) |
56d36be4 DM |
7489 | { |
7490 | u8 addr[6]; | |
7491 | int ret, i, j = 0; | |
7492 | struct fw_port_cmd c; | |
f796564a | 7493 | struct fw_rss_vi_config_cmd rvc; |
56d36be4 DM |
7494 | |
7495 | memset(&c, 0, sizeof(c)); | |
f796564a | 7496 | memset(&rvc, 0, sizeof(rvc)); |
56d36be4 DM |
7497 | |
7498 | for_each_port(adap, i) { | |
7499 | unsigned int rss_size; | |
7500 | struct port_info *p = adap2pinfo(adap, i); | |
7501 | ||
7502 | while ((adap->params.portvec & (1 << j)) == 0) | |
7503 | j++; | |
7504 | ||
f404f80c HS |
7505 | c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | |
7506 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
7507 | FW_PORT_CMD_PORTID_V(j)); | |
7508 | c.action_to_len16 = cpu_to_be32( | |
2b5fb1f2 | 7509 | FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | |
56d36be4 DM |
7510 | FW_LEN16(c)); |
7511 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
7512 | if (ret) | |
7513 | return ret; | |
7514 | ||
7515 | ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); | |
7516 | if (ret < 0) | |
7517 | return ret; | |
7518 | ||
7519 | p->viid = ret; | |
7520 | p->tx_chan = j; | |
7521 | p->lport = j; | |
7522 | p->rss_size = rss_size; | |
7523 | memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); | |
40c9f8ab | 7524 | adap->port[i]->dev_port = j; |
56d36be4 | 7525 | |
f404f80c | 7526 | ret = be32_to_cpu(c.u.info.lstatus_to_modtype); |
2b5fb1f2 HS |
7527 | p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ? |
7528 | FW_PORT_CMD_MDIOADDR_G(ret) : -1; | |
7529 | p->port_type = FW_PORT_CMD_PTYPE_G(ret); | |
a0881cab | 7530 | p->mod_type = FW_PORT_MOD_TYPE_NA; |
56d36be4 | 7531 | |
f404f80c HS |
7532 | rvc.op_to_viid = |
7533 | cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | | |
7534 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
7535 | FW_RSS_VI_CONFIG_CMD_VIID(p->viid)); | |
7536 | rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); | |
f796564a DM |
7537 | ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); |
7538 | if (ret) | |
7539 | return ret; | |
f404f80c | 7540 | p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); |
f796564a | 7541 | |
f404f80c | 7542 | init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap)); |
56d36be4 DM |
7543 | j++; |
7544 | } | |
7545 | return 0; | |
7546 | } | |
f1ff24aa | 7547 | |
74b3092c HS |
7548 | /** |
7549 | * t4_read_cimq_cfg - read CIM queue configuration | |
7550 | * @adap: the adapter | |
7551 | * @base: holds the queue base addresses in bytes | |
7552 | * @size: holds the queue sizes in bytes | |
7553 | * @thres: holds the queue full thresholds in bytes | |
7554 | * | |
7555 | * Returns the current configuration of the CIM queues, starting with | |
7556 | * the IBQs, then the OBQs. | |
7557 | */ | |
7558 | void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) | |
7559 | { | |
7560 | unsigned int i, v; | |
7561 | int cim_num_obq = is_t4(adap->params.chip) ? | |
7562 | CIM_NUM_OBQ : CIM_NUM_OBQ_T5; | |
7563 | ||
7564 | for (i = 0; i < CIM_NUM_IBQ; i++) { | |
7565 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | | |
7566 | QUENUMSELECT_V(i)); | |
7567 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
7568 | /* value is in 256-byte units */ | |
7569 | *base++ = CIMQBASE_G(v) * 256; | |
7570 | *size++ = CIMQSIZE_G(v) * 256; | |
7571 | *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ | |
7572 | } | |
7573 | for (i = 0; i < cim_num_obq; i++) { | |
7574 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | | |
7575 | QUENUMSELECT_V(i)); | |
7576 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
7577 | /* value is in 256-byte units */ | |
7578 | *base++ = CIMQBASE_G(v) * 256; | |
7579 | *size++ = CIMQSIZE_G(v) * 256; | |
7580 | } | |
7581 | } | |
7582 | ||
e5f0e43b HS |
7583 | /** |
7584 | * t4_read_cim_ibq - read the contents of a CIM inbound queue | |
7585 | * @adap: the adapter | |
7586 | * @qid: the queue index | |
7587 | * @data: where to store the queue contents | |
7588 | * @n: capacity of @data in 32-bit words | |
7589 | * | |
7590 | * Reads the contents of the selected CIM queue starting at address 0 up | |
7591 | * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on | |
7592 | * error and the number of 32-bit words actually read on success. | |
7593 | */ | |
7594 | int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) | |
7595 | { | |
7596 | int i, err, attempts; | |
7597 | unsigned int addr; | |
7598 | const unsigned int nwords = CIM_IBQ_SIZE * 4; | |
7599 | ||
7600 | if (qid > 5 || (n & 3)) | |
7601 | return -EINVAL; | |
7602 | ||
7603 | addr = qid * nwords; | |
7604 | if (n > nwords) | |
7605 | n = nwords; | |
7606 | ||
7607 | /* It might take 3-10ms before the IBQ debug read access is allowed. | |
7608 | * Wait for 1 Sec with a delay of 1 usec. | |
7609 | */ | |
7610 | attempts = 1000000; | |
7611 | ||
7612 | for (i = 0; i < n; i++, addr++) { | |
7613 | t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | | |
7614 | IBQDBGEN_F); | |
7615 | err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, | |
7616 | attempts, 1); | |
7617 | if (err) | |
7618 | return err; | |
7619 | *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); | |
7620 | } | |
7621 | t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); | |
c778af7d HS |
7622 | return i; |
7623 | } | |
7624 | ||
7625 | /** | |
7626 | * t4_read_cim_obq - read the contents of a CIM outbound queue | |
7627 | * @adap: the adapter | |
7628 | * @qid: the queue index | |
7629 | * @data: where to store the queue contents | |
7630 | * @n: capacity of @data in 32-bit words | |
7631 | * | |
7632 | * Reads the contents of the selected CIM queue starting at address 0 up | |
7633 | * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on | |
7634 | * error and the number of 32-bit words actually read on success. | |
7635 | */ | |
7636 | int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) | |
7637 | { | |
7638 | int i, err; | |
7639 | unsigned int addr, v, nwords; | |
7640 | int cim_num_obq = is_t4(adap->params.chip) ? | |
7641 | CIM_NUM_OBQ : CIM_NUM_OBQ_T5; | |
7642 | ||
7643 | if ((qid > (cim_num_obq - 1)) || (n & 3)) | |
7644 | return -EINVAL; | |
7645 | ||
7646 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | | |
7647 | QUENUMSELECT_V(qid)); | |
7648 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
7649 | ||
7650 | addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ | |
7651 | nwords = CIMQSIZE_G(v) * 64; /* same */ | |
7652 | if (n > nwords) | |
7653 | n = nwords; | |
7654 | ||
7655 | for (i = 0; i < n; i++, addr++) { | |
7656 | t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | | |
7657 | OBQDBGEN_F); | |
7658 | err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, | |
7659 | 2, 1); | |
7660 | if (err) | |
7661 | return err; | |
7662 | *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); | |
7663 | } | |
7664 | t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); | |
e5f0e43b HS |
7665 | return i; |
7666 | } | |
7667 | ||
f1ff24aa HS |
7668 | /** |
7669 | * t4_cim_read - read a block from CIM internal address space | |
7670 | * @adap: the adapter | |
7671 | * @addr: the start address within the CIM address space | |
7672 | * @n: number of words to read | |
7673 | * @valp: where to store the result | |
7674 | * | |
7675 | * Reads a block of 4-byte words from the CIM intenal address space. | |
7676 | */ | |
7677 | int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, | |
7678 | unsigned int *valp) | |
7679 | { | |
7680 | int ret = 0; | |
7681 | ||
7682 | if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) | |
7683 | return -EBUSY; | |
7684 | ||
7685 | for ( ; !ret && n--; addr += 4) { | |
7686 | t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); | |
7687 | ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, | |
7688 | 0, 5, 2); | |
7689 | if (!ret) | |
7690 | *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); | |
7691 | } | |
7692 | return ret; | |
7693 | } | |
7694 | ||
7695 | /** | |
7696 | * t4_cim_write - write a block into CIM internal address space | |
7697 | * @adap: the adapter | |
7698 | * @addr: the start address within the CIM address space | |
7699 | * @n: number of words to write | |
7700 | * @valp: set of values to write | |
7701 | * | |
7702 | * Writes a block of 4-byte words into the CIM intenal address space. | |
7703 | */ | |
7704 | int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, | |
7705 | const unsigned int *valp) | |
7706 | { | |
7707 | int ret = 0; | |
7708 | ||
7709 | if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) | |
7710 | return -EBUSY; | |
7711 | ||
7712 | for ( ; !ret && n--; addr += 4) { | |
7713 | t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); | |
7714 | t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); | |
7715 | ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, | |
7716 | 0, 5, 2); | |
7717 | } | |
7718 | return ret; | |
7719 | } | |
7720 | ||
7721 | static int t4_cim_write1(struct adapter *adap, unsigned int addr, | |
7722 | unsigned int val) | |
7723 | { | |
7724 | return t4_cim_write(adap, addr, 1, &val); | |
7725 | } | |
7726 | ||
7727 | /** | |
7728 | * t4_cim_read_la - read CIM LA capture buffer | |
7729 | * @adap: the adapter | |
7730 | * @la_buf: where to store the LA data | |
7731 | * @wrptr: the HW write pointer within the capture buffer | |
7732 | * | |
7733 | * Reads the contents of the CIM LA buffer with the most recent entry at | |
7734 | * the end of the returned data and with the entry at @wrptr first. | |
7735 | * We try to leave the LA in the running state we find it in. | |
7736 | */ | |
7737 | int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) | |
7738 | { | |
7739 | int i, ret; | |
7740 | unsigned int cfg, val, idx; | |
7741 | ||
7742 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); | |
7743 | if (ret) | |
7744 | return ret; | |
7745 | ||
7746 | if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */ | |
7747 | ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); | |
7748 | if (ret) | |
7749 | return ret; | |
7750 | } | |
7751 | ||
7752 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); | |
7753 | if (ret) | |
7754 | goto restart; | |
7755 | ||
7756 | idx = UPDBGLAWRPTR_G(val); | |
7757 | if (wrptr) | |
7758 | *wrptr = idx; | |
7759 | ||
7760 | for (i = 0; i < adap->params.cim_la_size; i++) { | |
7761 | ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, | |
7762 | UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F); | |
7763 | if (ret) | |
7764 | break; | |
7765 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); | |
7766 | if (ret) | |
7767 | break; | |
7768 | if (val & UPDBGLARDEN_F) { | |
7769 | ret = -ETIMEDOUT; | |
7770 | break; | |
7771 | } | |
7772 | ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); | |
7773 | if (ret) | |
7774 | break; | |
7775 | idx = (idx + 1) & UPDBGLARDPTR_M; | |
7776 | } | |
7777 | restart: | |
7778 | if (cfg & UPDBGLAEN_F) { | |
7779 | int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, | |
7780 | cfg & ~UPDBGLARDEN_F); | |
7781 | if (!ret) | |
7782 | ret = r; | |
7783 | } | |
7784 | return ret; | |
7785 | } | |
2d277b3b HS |
7786 | |
7787 | /** | |
7788 | * t4_tp_read_la - read TP LA capture buffer | |
7789 | * @adap: the adapter | |
7790 | * @la_buf: where to store the LA data | |
7791 | * @wrptr: the HW write pointer within the capture buffer | |
7792 | * | |
7793 | * Reads the contents of the TP LA buffer with the most recent entry at | |
7794 | * the end of the returned data and with the entry at @wrptr first. | |
7795 | * We leave the LA in the running state we find it in. | |
7796 | */ | |
7797 | void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) | |
7798 | { | |
7799 | bool last_incomplete; | |
7800 | unsigned int i, cfg, val, idx; | |
7801 | ||
7802 | cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; | |
7803 | if (cfg & DBGLAENABLE_F) /* freeze LA */ | |
7804 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, | |
7805 | adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); | |
7806 | ||
7807 | val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); | |
7808 | idx = DBGLAWPTR_G(val); | |
7809 | last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0; | |
7810 | if (last_incomplete) | |
7811 | idx = (idx + 1) & DBGLARPTR_M; | |
7812 | if (wrptr) | |
7813 | *wrptr = idx; | |
7814 | ||
7815 | val &= 0xffff; | |
7816 | val &= ~DBGLARPTR_V(DBGLARPTR_M); | |
7817 | val |= adap->params.tp.la_mask; | |
7818 | ||
7819 | for (i = 0; i < TPLA_SIZE; i++) { | |
7820 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); | |
7821 | la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); | |
7822 | idx = (idx + 1) & DBGLARPTR_M; | |
7823 | } | |
7824 | ||
7825 | /* Wipe out last entry if it isn't valid */ | |
7826 | if (last_incomplete) | |
7827 | la_buf[TPLA_SIZE - 1] = ~0ULL; | |
7828 | ||
7829 | if (cfg & DBGLAENABLE_F) /* restore running state */ | |
7830 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, | |
7831 | cfg | adap->params.tp.la_mask); | |
7832 | } | |
a3bfb617 HS |
7833 | |
7834 | /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in | |
7835 | * seconds). If we find one of the SGE Ingress DMA State Machines in the same | |
7836 | * state for more than the Warning Threshold then we'll issue a warning about | |
7837 | * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel | |
7838 | * appears to be hung every Warning Repeat second till the situation clears. | |
7839 | * If the situation clears, we'll note that as well. | |
7840 | */ | |
7841 | #define SGE_IDMA_WARN_THRESH 1 | |
7842 | #define SGE_IDMA_WARN_REPEAT 300 | |
7843 | ||
7844 | /** | |
7845 | * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor | |
7846 | * @adapter: the adapter | |
7847 | * @idma: the adapter IDMA Monitor state | |
7848 | * | |
7849 | * Initialize the state of an SGE Ingress DMA Monitor. | |
7850 | */ | |
7851 | void t4_idma_monitor_init(struct adapter *adapter, | |
7852 | struct sge_idma_monitor_state *idma) | |
7853 | { | |
7854 | /* Initialize the state variables for detecting an SGE Ingress DMA | |
7855 | * hang. The SGE has internal counters which count up on each clock | |
7856 | * tick whenever the SGE finds its Ingress DMA State Engines in the | |
7857 | * same state they were on the previous clock tick. The clock used is | |
7858 | * the Core Clock so we have a limit on the maximum "time" they can | |
7859 | * record; typically a very small number of seconds. For instance, | |
7860 | * with a 600MHz Core Clock, we can only count up to a bit more than | |
7861 | * 7s. So we'll synthesize a larger counter in order to not run the | |
7862 | * risk of having the "timers" overflow and give us the flexibility to | |
7863 | * maintain a Hung SGE State Machine of our own which operates across | |
7864 | * a longer time frame. | |
7865 | */ | |
7866 | idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ | |
7867 | idma->idma_stalled[0] = 0; | |
7868 | idma->idma_stalled[1] = 0; | |
7869 | } | |
7870 | ||
7871 | /** | |
7872 | * t4_idma_monitor - monitor SGE Ingress DMA state | |
7873 | * @adapter: the adapter | |
7874 | * @idma: the adapter IDMA Monitor state | |
7875 | * @hz: number of ticks/second | |
7876 | * @ticks: number of ticks since the last IDMA Monitor call | |
7877 | */ | |
7878 | void t4_idma_monitor(struct adapter *adapter, | |
7879 | struct sge_idma_monitor_state *idma, | |
7880 | int hz, int ticks) | |
7881 | { | |
7882 | int i, idma_same_state_cnt[2]; | |
7883 | ||
7884 | /* Read the SGE Debug Ingress DMA Same State Count registers. These | |
7885 | * are counters inside the SGE which count up on each clock when the | |
7886 | * SGE finds its Ingress DMA State Engines in the same states they | |
7887 | * were in the previous clock. The counters will peg out at | |
7888 | * 0xffffffff without wrapping around so once they pass the 1s | |
7889 | * threshold they'll stay above that till the IDMA state changes. | |
7890 | */ | |
7891 | t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13); | |
7892 | idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A); | |
7893 | idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); | |
7894 | ||
7895 | for (i = 0; i < 2; i++) { | |
7896 | u32 debug0, debug11; | |
7897 | ||
7898 | /* If the Ingress DMA Same State Counter ("timer") is less | |
7899 | * than 1s, then we can reset our synthesized Stall Timer and | |
7900 | * continue. If we have previously emitted warnings about a | |
7901 | * potential stalled Ingress Queue, issue a note indicating | |
7902 | * that the Ingress Queue has resumed forward progress. | |
7903 | */ | |
7904 | if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { | |
7905 | if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz) | |
7906 | dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, " | |
7907 | "resumed after %d seconds\n", | |
7908 | i, idma->idma_qid[i], | |
7909 | idma->idma_stalled[i] / hz); | |
7910 | idma->idma_stalled[i] = 0; | |
7911 | continue; | |
7912 | } | |
7913 | ||
7914 | /* Synthesize an SGE Ingress DMA Same State Timer in the Hz | |
7915 | * domain. The first time we get here it'll be because we | |
7916 | * passed the 1s Threshold; each additional time it'll be | |
7917 | * because the RX Timer Callback is being fired on its regular | |
7918 | * schedule. | |
7919 | * | |
7920 | * If the stall is below our Potential Hung Ingress Queue | |
7921 | * Warning Threshold, continue. | |
7922 | */ | |
7923 | if (idma->idma_stalled[i] == 0) { | |
7924 | idma->idma_stalled[i] = hz; | |
7925 | idma->idma_warn[i] = 0; | |
7926 | } else { | |
7927 | idma->idma_stalled[i] += ticks; | |
7928 | idma->idma_warn[i] -= ticks; | |
7929 | } | |
7930 | ||
7931 | if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz) | |
7932 | continue; | |
7933 | ||
7934 | /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. | |
7935 | */ | |
7936 | if (idma->idma_warn[i] > 0) | |
7937 | continue; | |
7938 | idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz; | |
7939 | ||
7940 | /* Read and save the SGE IDMA State and Queue ID information. | |
7941 | * We do this every time in case it changes across time ... | |
7942 | * can't be too careful ... | |
7943 | */ | |
7944 | t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0); | |
7945 | debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); | |
7946 | idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; | |
7947 | ||
7948 | t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11); | |
7949 | debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); | |
7950 | idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; | |
7951 | ||
7952 | dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in " | |
7953 | "state %u for %d seconds (debug0=%#x, debug11=%#x)\n", | |
7954 | i, idma->idma_qid[i], idma->idma_state[i], | |
7955 | idma->idma_stalled[i] / hz, | |
7956 | debug0, debug11); | |
7957 | t4_sge_decode_idma_state(adapter, idma->idma_state[i]); | |
7958 | } | |
7959 | } |