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bbc02c7e DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
bbc02c7e DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef __T4_REGS_H | |
36 | #define __T4_REGS_H | |
37 | ||
38 | #define MYPF_BASE 0x1b000 | |
39 | #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) | |
40 | ||
41 | #define PF0_BASE 0x1e000 | |
42 | #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) | |
43 | ||
44 | #define PF_STRIDE 0x400 | |
45 | #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) | |
46 | #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) | |
47 | ||
48 | #define MYPORT_BASE 0x1c000 | |
49 | #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) | |
50 | ||
51 | #define PORT0_BASE 0x20000 | |
52 | #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) | |
53 | ||
54 | #define PORT_STRIDE 0x2000 | |
55 | #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) | |
56 | #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) | |
57 | ||
58 | #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) | |
59 | #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) | |
60 | ||
61 | #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) | |
62 | #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) | |
63 | #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) | |
64 | #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) | |
65 | ||
ae469b68 HS |
66 | #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) |
67 | ||
f612b815 | 68 | #define SGE_PF_KDOORBELL_A 0x0 |
ce8f407a | 69 | |
f612b815 HS |
70 | #define QID_S 15 |
71 | #define QID_V(x) ((x) << QID_S) | |
72 | ||
73 | #define DBPRIO_S 14 | |
74 | #define DBPRIO_V(x) ((x) << DBPRIO_S) | |
75 | #define DBPRIO_F DBPRIO_V(1U) | |
76 | ||
77 | #define PIDX_S 0 | |
78 | #define PIDX_V(x) ((x) << PIDX_S) | |
79 | ||
80 | #define SGE_VF_KDOORBELL_A 0x0 | |
81 | ||
82 | #define DBTYPE_S 13 | |
83 | #define DBTYPE_V(x) ((x) << DBTYPE_S) | |
84 | #define DBTYPE_F DBTYPE_V(1U) | |
85 | ||
86 | #define PIDX_T5_S 0 | |
87 | #define PIDX_T5_M 0x1fffU | |
88 | #define PIDX_T5_V(x) ((x) << PIDX_T5_S) | |
89 | #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M) | |
90 | ||
91 | #define SGE_PF_GTS_A 0x4 | |
bbc02c7e | 92 | |
f612b815 HS |
93 | #define INGRESSQID_S 16 |
94 | #define INGRESSQID_V(x) ((x) << INGRESSQID_S) | |
636f9d37 | 95 | |
f612b815 HS |
96 | #define TIMERREG_S 13 |
97 | #define TIMERREG_V(x) ((x) << TIMERREG_S) | |
636f9d37 | 98 | |
f612b815 HS |
99 | #define SEINTARM_S 12 |
100 | #define SEINTARM_V(x) ((x) << SEINTARM_S) | |
636f9d37 | 101 | |
f612b815 HS |
102 | #define CIDXINC_S 0 |
103 | #define CIDXINC_M 0xfffU | |
104 | #define CIDXINC_V(x) ((x) << CIDXINC_S) | |
636f9d37 | 105 | |
f612b815 HS |
106 | #define SGE_CONTROL_A 0x1008 |
107 | #define SGE_CONTROL2_A 0x1124 | |
636f9d37 | 108 | |
f612b815 HS |
109 | #define RXPKTCPLMODE_S 18 |
110 | #define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S) | |
111 | #define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U) | |
636f9d37 | 112 | |
f612b815 HS |
113 | #define EGRSTATUSPAGESIZE_S 17 |
114 | #define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S) | |
115 | #define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U) | |
636f9d37 | 116 | |
f612b815 HS |
117 | #define PKTSHIFT_S 10 |
118 | #define PKTSHIFT_M 0x7U | |
119 | #define PKTSHIFT_V(x) ((x) << PKTSHIFT_S) | |
120 | #define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M) | |
636f9d37 | 121 | |
f612b815 HS |
122 | #define INGPCIEBOUNDARY_S 7 |
123 | #define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S) | |
bbc02c7e | 124 | |
f612b815 HS |
125 | #define INGPADBOUNDARY_S 4 |
126 | #define INGPADBOUNDARY_M 0x7U | |
127 | #define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S) | |
128 | #define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M) | |
129 | ||
130 | #define EGRPCIEBOUNDARY_S 1 | |
131 | #define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S) | |
132 | ||
133 | #define INGPACKBOUNDARY_S 16 | |
134 | #define INGPACKBOUNDARY_M 0x7U | |
135 | #define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S) | |
136 | #define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \ | |
137 | & INGPACKBOUNDARY_M) | |
138 | ||
139 | #define GLOBALENABLE_S 0 | |
140 | #define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S) | |
141 | #define GLOBALENABLE_F GLOBALENABLE_V(1U) | |
142 | ||
143 | #define SGE_HOST_PAGE_SIZE_A 0x100c | |
144 | ||
145 | #define HOSTPAGESIZEPF7_S 28 | |
146 | #define HOSTPAGESIZEPF7_M 0xfU | |
147 | #define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S) | |
148 | #define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M) | |
149 | ||
150 | #define HOSTPAGESIZEPF6_S 24 | |
151 | #define HOSTPAGESIZEPF6_M 0xfU | |
152 | #define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S) | |
153 | #define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M) | |
154 | ||
155 | #define HOSTPAGESIZEPF5_S 20 | |
156 | #define HOSTPAGESIZEPF5_M 0xfU | |
157 | #define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S) | |
158 | #define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M) | |
159 | ||
160 | #define HOSTPAGESIZEPF4_S 16 | |
161 | #define HOSTPAGESIZEPF4_M 0xfU | |
162 | #define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S) | |
163 | #define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M) | |
164 | ||
165 | #define HOSTPAGESIZEPF3_S 12 | |
166 | #define HOSTPAGESIZEPF3_M 0xfU | |
167 | #define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S) | |
168 | #define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M) | |
169 | ||
170 | #define HOSTPAGESIZEPF2_S 8 | |
171 | #define HOSTPAGESIZEPF2_M 0xfU | |
172 | #define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S) | |
173 | #define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M) | |
174 | ||
175 | #define HOSTPAGESIZEPF1_S 4 | |
176 | #define HOSTPAGESIZEPF1_M 0xfU | |
177 | #define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S) | |
178 | #define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M) | |
179 | ||
180 | #define HOSTPAGESIZEPF0_S 0 | |
181 | #define HOSTPAGESIZEPF0_M 0xfU | |
182 | #define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S) | |
183 | #define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M) | |
184 | ||
185 | #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010 | |
e0a8b34a HS |
186 | #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014 |
187 | ||
188 | #define QUEUESPERPAGEPF1_S 4 | |
189 | ||
190 | #define QUEUESPERPAGEPF0_S 0 | |
f612b815 HS |
191 | #define QUEUESPERPAGEPF0_M 0xfU |
192 | #define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S) | |
193 | #define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M) | |
b2decadd | 194 | |
f612b815 HS |
195 | #define SGE_INT_CAUSE1_A 0x1024 |
196 | #define SGE_INT_CAUSE2_A 0x1030 | |
197 | #define SGE_INT_CAUSE3_A 0x103c | |
198 | ||
199 | #define ERR_FLM_DBP_S 31 | |
200 | #define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S) | |
201 | #define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U) | |
202 | ||
203 | #define ERR_FLM_IDMA1_S 30 | |
204 | #define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S) | |
205 | #define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U) | |
206 | ||
207 | #define ERR_FLM_IDMA0_S 29 | |
208 | #define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S) | |
209 | #define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U) | |
210 | ||
211 | #define ERR_FLM_HINT_S 28 | |
212 | #define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S) | |
213 | #define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U) | |
214 | ||
215 | #define ERR_PCIE_ERROR3_S 27 | |
216 | #define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S) | |
217 | #define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U) | |
218 | ||
219 | #define ERR_PCIE_ERROR2_S 26 | |
220 | #define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S) | |
221 | #define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U) | |
222 | ||
223 | #define ERR_PCIE_ERROR1_S 25 | |
224 | #define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S) | |
225 | #define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U) | |
226 | ||
227 | #define ERR_PCIE_ERROR0_S 24 | |
228 | #define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S) | |
229 | #define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U) | |
230 | ||
231 | #define ERR_CPL_EXCEED_IQE_SIZE_S 22 | |
232 | #define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S) | |
233 | #define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U) | |
234 | ||
235 | #define ERR_INVALID_CIDX_INC_S 21 | |
236 | #define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S) | |
237 | #define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U) | |
238 | ||
239 | #define ERR_CPL_OPCODE_0_S 19 | |
240 | #define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S) | |
241 | #define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U) | |
242 | ||
243 | #define ERR_DROPPED_DB_S 18 | |
244 | #define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S) | |
245 | #define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U) | |
246 | ||
247 | #define ERR_DATA_CPL_ON_HIGH_QID1_S 17 | |
248 | #define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S) | |
249 | #define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U) | |
250 | ||
251 | #define ERR_DATA_CPL_ON_HIGH_QID0_S 16 | |
252 | #define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S) | |
253 | #define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U) | |
254 | ||
255 | #define ERR_BAD_DB_PIDX3_S 15 | |
256 | #define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S) | |
257 | #define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U) | |
258 | ||
259 | #define ERR_BAD_DB_PIDX2_S 14 | |
260 | #define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S) | |
261 | #define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U) | |
262 | ||
263 | #define ERR_BAD_DB_PIDX1_S 13 | |
264 | #define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S) | |
265 | #define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U) | |
266 | ||
267 | #define ERR_BAD_DB_PIDX0_S 12 | |
268 | #define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S) | |
269 | #define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U) | |
270 | ||
271 | #define ERR_ING_CTXT_PRIO_S 10 | |
272 | #define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S) | |
273 | #define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U) | |
274 | ||
275 | #define ERR_EGR_CTXT_PRIO_S 9 | |
276 | #define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S) | |
277 | #define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U) | |
278 | ||
279 | #define DBFIFO_HP_INT_S 8 | |
280 | #define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S) | |
281 | #define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U) | |
282 | ||
283 | #define DBFIFO_LP_INT_S 7 | |
284 | #define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S) | |
285 | #define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U) | |
286 | ||
287 | #define INGRESS_SIZE_ERR_S 5 | |
288 | #define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S) | |
289 | #define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U) | |
290 | ||
291 | #define EGRESS_SIZE_ERR_S 4 | |
292 | #define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S) | |
293 | #define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U) | |
294 | ||
295 | #define SGE_INT_ENABLE3_A 0x1040 | |
296 | #define SGE_FL_BUFFER_SIZE0_A 0x1044 | |
297 | #define SGE_FL_BUFFER_SIZE1_A 0x1048 | |
298 | #define SGE_FL_BUFFER_SIZE2_A 0x104c | |
299 | #define SGE_FL_BUFFER_SIZE3_A 0x1050 | |
300 | #define SGE_FL_BUFFER_SIZE4_A 0x1054 | |
301 | #define SGE_FL_BUFFER_SIZE5_A 0x1058 | |
302 | #define SGE_FL_BUFFER_SIZE6_A 0x105c | |
303 | #define SGE_FL_BUFFER_SIZE7_A 0x1060 | |
304 | #define SGE_FL_BUFFER_SIZE8_A 0x1064 | |
305 | ||
306 | #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0 | |
307 | ||
308 | #define THRESHOLD_0_S 24 | |
309 | #define THRESHOLD_0_M 0x3fU | |
310 | #define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S) | |
311 | #define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M) | |
312 | ||
313 | #define THRESHOLD_1_S 16 | |
314 | #define THRESHOLD_1_M 0x3fU | |
315 | #define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S) | |
316 | #define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M) | |
317 | ||
318 | #define THRESHOLD_2_S 8 | |
319 | #define THRESHOLD_2_M 0x3fU | |
320 | #define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S) | |
321 | #define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M) | |
322 | ||
323 | #define THRESHOLD_3_S 0 | |
324 | #define THRESHOLD_3_M 0x3fU | |
325 | #define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S) | |
326 | #define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M) | |
327 | ||
328 | #define SGE_CONM_CTRL_A 0x1094 | |
329 | ||
330 | #define EGRTHRESHOLD_S 8 | |
331 | #define EGRTHRESHOLD_M 0x3fU | |
332 | #define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S) | |
333 | #define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M) | |
334 | ||
335 | #define EGRTHRESHOLDPACKING_S 14 | |
336 | #define EGRTHRESHOLDPACKING_M 0x3fU | |
337 | #define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S) | |
338 | #define EGRTHRESHOLDPACKING_G(x) \ | |
339 | (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M) | |
340 | ||
341 | #define SGE_TIMESTAMP_LO_A 0x1098 | |
342 | #define SGE_TIMESTAMP_HI_A 0x109c | |
343 | ||
344 | #define TSOP_S 28 | |
345 | #define TSOP_M 0x3U | |
346 | #define TSOP_V(x) ((x) << TSOP_S) | |
347 | #define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M) | |
348 | ||
349 | #define TSVAL_S 0 | |
350 | #define TSVAL_M 0xfffffffU | |
351 | #define TSVAL_V(x) ((x) << TSVAL_S) | |
352 | #define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M) | |
353 | ||
354 | #define SGE_DBFIFO_STATUS_A 0x10a4 | |
355 | ||
356 | #define HP_INT_THRESH_S 28 | |
357 | #define HP_INT_THRESH_M 0xfU | |
358 | #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) | |
359 | ||
360 | #define LP_INT_THRESH_S 12 | |
361 | #define LP_INT_THRESH_M 0xfU | |
362 | #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) | |
363 | ||
364 | #define SGE_DOORBELL_CONTROL_A 0x10a8 | |
365 | ||
366 | #define NOCOALESCE_S 26 | |
367 | #define NOCOALESCE_V(x) ((x) << NOCOALESCE_S) | |
368 | #define NOCOALESCE_F NOCOALESCE_V(1U) | |
369 | ||
370 | #define ENABLE_DROP_S 13 | |
371 | #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) | |
372 | #define ENABLE_DROP_F ENABLE_DROP_V(1U) | |
7730b4c7 | 373 | |
f061de42 HS |
374 | #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8 |
375 | ||
376 | #define TIMERVALUE0_S 16 | |
377 | #define TIMERVALUE0_M 0xffffU | |
378 | #define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S) | |
379 | #define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M) | |
380 | ||
381 | #define TIMERVALUE1_S 0 | |
382 | #define TIMERVALUE1_M 0xffffU | |
383 | #define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S) | |
384 | #define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M) | |
385 | ||
386 | #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc | |
387 | ||
388 | #define TIMERVALUE2_S 16 | |
389 | #define TIMERVALUE2_M 0xffffU | |
390 | #define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S) | |
391 | #define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M) | |
392 | ||
393 | #define TIMERVALUE3_S 0 | |
394 | #define TIMERVALUE3_M 0xffffU | |
395 | #define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S) | |
396 | #define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M) | |
397 | ||
398 | #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0 | |
399 | ||
400 | #define TIMERVALUE4_S 16 | |
401 | #define TIMERVALUE4_M 0xffffU | |
402 | #define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S) | |
403 | #define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M) | |
404 | ||
405 | #define TIMERVALUE5_S 0 | |
406 | #define TIMERVALUE5_M 0xffffU | |
407 | #define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S) | |
408 | #define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M) | |
409 | ||
410 | #define SGE_DEBUG_INDEX_A 0x10cc | |
411 | #define SGE_DEBUG_DATA_HIGH_A 0x10d0 | |
412 | #define SGE_DEBUG_DATA_LOW_A 0x10d4 | |
413 | ||
414 | #define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8 | |
415 | #define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc | |
416 | #define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8 | |
417 | ||
418 | #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4 | |
e0a8b34a | 419 | #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8 |
bbc02c7e | 420 | |
3ccc6cf7 HS |
421 | #define SGE_ERROR_STATS_A 0x1100 |
422 | ||
423 | #define UNCAPTURED_ERROR_S 18 | |
424 | #define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S) | |
425 | #define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U) | |
426 | ||
427 | #define ERROR_QID_VALID_S 17 | |
428 | #define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S) | |
429 | #define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U) | |
430 | ||
431 | #define ERROR_QID_S 0 | |
432 | #define ERROR_QID_M 0x1ffffU | |
433 | #define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M) | |
434 | ||
f061de42 HS |
435 | #define HP_INT_THRESH_S 28 |
436 | #define HP_INT_THRESH_M 0xfU | |
437 | #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) | |
438 | ||
439 | #define HP_COUNT_S 16 | |
440 | #define HP_COUNT_M 0x7ffU | |
441 | #define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M) | |
442 | ||
443 | #define LP_INT_THRESH_S 12 | |
444 | #define LP_INT_THRESH_M 0xfU | |
445 | #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) | |
446 | ||
447 | #define LP_COUNT_S 0 | |
448 | #define LP_COUNT_M 0x7ffU | |
449 | #define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M) | |
450 | ||
451 | #define LP_INT_THRESH_T5_S 18 | |
452 | #define LP_INT_THRESH_T5_M 0xfffU | |
453 | #define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S) | |
454 | ||
455 | #define LP_COUNT_T5_S 0 | |
456 | #define LP_COUNT_T5_M 0x3ffffU | |
457 | #define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M) | |
458 | ||
459 | #define SGE_DOORBELL_CONTROL_A 0x10a8 | |
460 | ||
461 | #define SGE_STAT_TOTAL_A 0x10e4 | |
462 | #define SGE_STAT_MATCH_A 0x10e8 | |
463 | #define SGE_STAT_CFG_A 0x10ec | |
464 | ||
a4cfd929 HS |
465 | #define STATMODE_S 2 |
466 | #define STATMODE_V(x) ((x) << STATMODE_S) | |
467 | ||
f061de42 | 468 | #define STATSOURCE_T5_S 9 |
a4cfd929 | 469 | #define STATSOURCE_T5_M 0xfU |
f061de42 | 470 | #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S) |
a4cfd929 | 471 | #define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M) |
f061de42 HS |
472 | |
473 | #define SGE_DBFIFO_STATUS2_A 0x1118 | |
474 | ||
475 | #define HP_INT_THRESH_T5_S 10 | |
476 | #define HP_INT_THRESH_T5_M 0xfU | |
477 | #define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S) | |
478 | ||
479 | #define HP_COUNT_T5_S 0 | |
480 | #define HP_COUNT_T5_M 0x3ffU | |
481 | #define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M) | |
482 | ||
483 | #define ENABLE_DROP_S 13 | |
484 | #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) | |
485 | #define ENABLE_DROP_F ENABLE_DROP_V(1U) | |
486 | ||
487 | #define DROPPED_DB_S 0 | |
488 | #define DROPPED_DB_V(x) ((x) << DROPPED_DB_S) | |
489 | #define DROPPED_DB_F DROPPED_DB_V(1U) | |
490 | ||
491 | #define SGE_CTXT_CMD_A 0x11fc | |
492 | #define SGE_DBQ_CTXT_BADDR_A 0x1084 | |
493 | ||
494 | /* registers for module PCIE */ | |
495 | #define PCIE_PF_CFG_A 0x40 | |
496 | ||
497 | #define AIVEC_S 4 | |
498 | #define AIVEC_M 0x3ffU | |
499 | #define AIVEC_V(x) ((x) << AIVEC_S) | |
500 | ||
501 | #define PCIE_PF_CLI_A 0x44 | |
502 | #define PCIE_INT_CAUSE_A 0x3004 | |
503 | ||
504 | #define UNXSPLCPLERR_S 29 | |
505 | #define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S) | |
506 | #define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U) | |
507 | ||
508 | #define PCIEPINT_S 28 | |
509 | #define PCIEPINT_V(x) ((x) << PCIEPINT_S) | |
510 | #define PCIEPINT_F PCIEPINT_V(1U) | |
511 | ||
512 | #define PCIESINT_S 27 | |
513 | #define PCIESINT_V(x) ((x) << PCIESINT_S) | |
514 | #define PCIESINT_F PCIESINT_V(1U) | |
515 | ||
516 | #define RPLPERR_S 26 | |
517 | #define RPLPERR_V(x) ((x) << RPLPERR_S) | |
518 | #define RPLPERR_F RPLPERR_V(1U) | |
519 | ||
520 | #define RXWRPERR_S 25 | |
521 | #define RXWRPERR_V(x) ((x) << RXWRPERR_S) | |
522 | #define RXWRPERR_F RXWRPERR_V(1U) | |
523 | ||
524 | #define RXCPLPERR_S 24 | |
525 | #define RXCPLPERR_V(x) ((x) << RXCPLPERR_S) | |
526 | #define RXCPLPERR_F RXCPLPERR_V(1U) | |
527 | ||
528 | #define PIOTAGPERR_S 23 | |
529 | #define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S) | |
530 | #define PIOTAGPERR_F PIOTAGPERR_V(1U) | |
531 | ||
532 | #define MATAGPERR_S 22 | |
533 | #define MATAGPERR_V(x) ((x) << MATAGPERR_S) | |
534 | #define MATAGPERR_F MATAGPERR_V(1U) | |
535 | ||
536 | #define INTXCLRPERR_S 21 | |
537 | #define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S) | |
538 | #define INTXCLRPERR_F INTXCLRPERR_V(1U) | |
539 | ||
540 | #define FIDPERR_S 20 | |
541 | #define FIDPERR_V(x) ((x) << FIDPERR_S) | |
542 | #define FIDPERR_F FIDPERR_V(1U) | |
543 | ||
544 | #define CFGSNPPERR_S 19 | |
545 | #define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S) | |
546 | #define CFGSNPPERR_F CFGSNPPERR_V(1U) | |
547 | ||
548 | #define HRSPPERR_S 18 | |
549 | #define HRSPPERR_V(x) ((x) << HRSPPERR_S) | |
550 | #define HRSPPERR_F HRSPPERR_V(1U) | |
551 | ||
552 | #define HREQPERR_S 17 | |
553 | #define HREQPERR_V(x) ((x) << HREQPERR_S) | |
554 | #define HREQPERR_F HREQPERR_V(1U) | |
555 | ||
556 | #define HCNTPERR_S 16 | |
557 | #define HCNTPERR_V(x) ((x) << HCNTPERR_S) | |
558 | #define HCNTPERR_F HCNTPERR_V(1U) | |
559 | ||
560 | #define DRSPPERR_S 15 | |
561 | #define DRSPPERR_V(x) ((x) << DRSPPERR_S) | |
562 | #define DRSPPERR_F DRSPPERR_V(1U) | |
563 | ||
564 | #define DREQPERR_S 14 | |
565 | #define DREQPERR_V(x) ((x) << DREQPERR_S) | |
566 | #define DREQPERR_F DREQPERR_V(1U) | |
567 | ||
568 | #define DCNTPERR_S 13 | |
569 | #define DCNTPERR_V(x) ((x) << DCNTPERR_S) | |
570 | #define DCNTPERR_F DCNTPERR_V(1U) | |
571 | ||
572 | #define CRSPPERR_S 12 | |
573 | #define CRSPPERR_V(x) ((x) << CRSPPERR_S) | |
574 | #define CRSPPERR_F CRSPPERR_V(1U) | |
575 | ||
576 | #define CREQPERR_S 11 | |
577 | #define CREQPERR_V(x) ((x) << CREQPERR_S) | |
578 | #define CREQPERR_F CREQPERR_V(1U) | |
579 | ||
580 | #define CCNTPERR_S 10 | |
581 | #define CCNTPERR_V(x) ((x) << CCNTPERR_S) | |
582 | #define CCNTPERR_F CCNTPERR_V(1U) | |
583 | ||
584 | #define TARTAGPERR_S 9 | |
585 | #define TARTAGPERR_V(x) ((x) << TARTAGPERR_S) | |
586 | #define TARTAGPERR_F TARTAGPERR_V(1U) | |
587 | ||
588 | #define PIOREQPERR_S 8 | |
589 | #define PIOREQPERR_V(x) ((x) << PIOREQPERR_S) | |
590 | #define PIOREQPERR_F PIOREQPERR_V(1U) | |
591 | ||
592 | #define PIOCPLPERR_S 7 | |
593 | #define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S) | |
594 | #define PIOCPLPERR_F PIOCPLPERR_V(1U) | |
595 | ||
596 | #define MSIXDIPERR_S 6 | |
597 | #define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S) | |
598 | #define MSIXDIPERR_F MSIXDIPERR_V(1U) | |
599 | ||
600 | #define MSIXDATAPERR_S 5 | |
601 | #define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S) | |
602 | #define MSIXDATAPERR_F MSIXDATAPERR_V(1U) | |
603 | ||
604 | #define MSIXADDRHPERR_S 4 | |
605 | #define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S) | |
606 | #define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U) | |
607 | ||
608 | #define MSIXADDRLPERR_S 3 | |
609 | #define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S) | |
610 | #define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U) | |
611 | ||
612 | #define MSIDATAPERR_S 2 | |
613 | #define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S) | |
614 | #define MSIDATAPERR_F MSIDATAPERR_V(1U) | |
615 | ||
616 | #define MSIADDRHPERR_S 1 | |
617 | #define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S) | |
618 | #define MSIADDRHPERR_F MSIADDRHPERR_V(1U) | |
619 | ||
620 | #define MSIADDRLPERR_S 0 | |
621 | #define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S) | |
622 | #define MSIADDRLPERR_F MSIADDRLPERR_V(1U) | |
623 | ||
624 | #define READRSPERR_S 29 | |
625 | #define READRSPERR_V(x) ((x) << READRSPERR_S) | |
626 | #define READRSPERR_F READRSPERR_V(1U) | |
627 | ||
628 | #define TRGT1GRPPERR_S 28 | |
629 | #define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S) | |
630 | #define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U) | |
631 | ||
632 | #define IPSOTPERR_S 27 | |
633 | #define IPSOTPERR_V(x) ((x) << IPSOTPERR_S) | |
634 | #define IPSOTPERR_F IPSOTPERR_V(1U) | |
635 | ||
636 | #define IPRETRYPERR_S 26 | |
637 | #define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S) | |
638 | #define IPRETRYPERR_F IPRETRYPERR_V(1U) | |
639 | ||
640 | #define IPRXDATAGRPPERR_S 25 | |
641 | #define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S) | |
642 | #define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U) | |
643 | ||
644 | #define IPRXHDRGRPPERR_S 24 | |
645 | #define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S) | |
646 | #define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U) | |
647 | ||
648 | #define MAGRPPERR_S 22 | |
649 | #define MAGRPPERR_V(x) ((x) << MAGRPPERR_S) | |
650 | #define MAGRPPERR_F MAGRPPERR_V(1U) | |
651 | ||
652 | #define VFIDPERR_S 21 | |
653 | #define VFIDPERR_V(x) ((x) << VFIDPERR_S) | |
654 | #define VFIDPERR_F VFIDPERR_V(1U) | |
655 | ||
656 | #define HREQWRPERR_S 16 | |
657 | #define HREQWRPERR_V(x) ((x) << HREQWRPERR_S) | |
658 | #define HREQWRPERR_F HREQWRPERR_V(1U) | |
659 | ||
660 | #define DREQWRPERR_S 13 | |
661 | #define DREQWRPERR_V(x) ((x) << DREQWRPERR_S) | |
662 | #define DREQWRPERR_F DREQWRPERR_V(1U) | |
663 | ||
664 | #define CREQRDPERR_S 11 | |
665 | #define CREQRDPERR_V(x) ((x) << CREQRDPERR_S) | |
666 | #define CREQRDPERR_F CREQRDPERR_V(1U) | |
667 | ||
668 | #define MSTTAGQPERR_S 10 | |
669 | #define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S) | |
670 | #define MSTTAGQPERR_F MSTTAGQPERR_V(1U) | |
671 | ||
672 | #define PIOREQGRPPERR_S 8 | |
673 | #define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S) | |
674 | #define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U) | |
675 | ||
676 | #define PIOCPLGRPPERR_S 7 | |
677 | #define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S) | |
678 | #define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U) | |
679 | ||
680 | #define MSIXSTIPERR_S 2 | |
681 | #define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S) | |
682 | #define MSIXSTIPERR_F MSIXSTIPERR_V(1U) | |
683 | ||
684 | #define MSTTIMEOUTPERR_S 1 | |
685 | #define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S) | |
686 | #define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U) | |
687 | ||
688 | #define MSTGRPPERR_S 0 | |
689 | #define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S) | |
690 | #define MSTGRPPERR_F MSTGRPPERR_V(1U) | |
691 | ||
692 | #define PCIE_NONFAT_ERR_A 0x3010 | |
693 | #define PCIE_CFG_SPACE_REQ_A 0x3060 | |
694 | #define PCIE_CFG_SPACE_DATA_A 0x3064 | |
695 | #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068 | |
696 | ||
697 | #define PCIEOFST_S 10 | |
698 | #define PCIEOFST_M 0x3fffffU | |
699 | #define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M) | |
700 | ||
701 | #define BIR_S 8 | |
702 | #define BIR_M 0x3U | |
703 | #define BIR_V(x) ((x) << BIR_S) | |
704 | #define BIR_G(x) (((x) >> BIR_S) & BIR_M) | |
705 | ||
706 | #define WINDOW_S 0 | |
707 | #define WINDOW_M 0xffU | |
708 | #define WINDOW_V(x) ((x) << WINDOW_S) | |
709 | #define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M) | |
710 | ||
711 | #define PCIE_MEM_ACCESS_OFFSET_A 0x306c | |
712 | ||
713 | #define ENABLE_S 30 | |
714 | #define ENABLE_V(x) ((x) << ENABLE_S) | |
715 | #define ENABLE_F ENABLE_V(1U) | |
716 | ||
717 | #define LOCALCFG_S 28 | |
718 | #define LOCALCFG_V(x) ((x) << LOCALCFG_S) | |
719 | #define LOCALCFG_F LOCALCFG_V(1U) | |
720 | ||
721 | #define FUNCTION_S 12 | |
722 | #define FUNCTION_V(x) ((x) << FUNCTION_S) | |
723 | ||
724 | #define REGISTER_S 0 | |
725 | #define REGISTER_V(x) ((x) << REGISTER_S) | |
726 | ||
3ccc6cf7 HS |
727 | #define T6_ENABLE_S 31 |
728 | #define T6_ENABLE_V(x) ((x) << T6_ENABLE_S) | |
729 | #define T6_ENABLE_F T6_ENABLE_V(1U) | |
730 | ||
f061de42 HS |
731 | #define PFNUM_S 0 |
732 | #define PFNUM_V(x) ((x) << PFNUM_S) | |
733 | ||
734 | #define PCIE_FW_A 0x30b8 | |
ae469b68 | 735 | #define PCIE_FW_PF_A 0x30bc |
f061de42 HS |
736 | |
737 | #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908 | |
738 | ||
739 | #define RNPP_S 31 | |
740 | #define RNPP_V(x) ((x) << RNPP_S) | |
741 | #define RNPP_F RNPP_V(1U) | |
742 | ||
743 | #define RPCP_S 29 | |
744 | #define RPCP_V(x) ((x) << RPCP_S) | |
745 | #define RPCP_F RPCP_V(1U) | |
746 | ||
747 | #define RCIP_S 27 | |
748 | #define RCIP_V(x) ((x) << RCIP_S) | |
749 | #define RCIP_F RCIP_V(1U) | |
750 | ||
751 | #define RCCP_S 26 | |
752 | #define RCCP_V(x) ((x) << RCCP_S) | |
753 | #define RCCP_F RCCP_V(1U) | |
754 | ||
755 | #define RFTP_S 23 | |
756 | #define RFTP_V(x) ((x) << RFTP_S) | |
757 | #define RFTP_F RFTP_V(1U) | |
758 | ||
759 | #define PTRP_S 20 | |
760 | #define PTRP_V(x) ((x) << PTRP_S) | |
761 | #define PTRP_F PTRP_V(1U) | |
762 | ||
763 | #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4 | |
764 | ||
765 | #define TPCP_S 30 | |
766 | #define TPCP_V(x) ((x) << TPCP_S) | |
767 | #define TPCP_F TPCP_V(1U) | |
768 | ||
769 | #define TNPP_S 29 | |
770 | #define TNPP_V(x) ((x) << TNPP_S) | |
771 | #define TNPP_F TNPP_V(1U) | |
772 | ||
773 | #define TFTP_S 28 | |
774 | #define TFTP_V(x) ((x) << TFTP_S) | |
775 | #define TFTP_F TFTP_V(1U) | |
776 | ||
777 | #define TCAP_S 27 | |
778 | #define TCAP_V(x) ((x) << TCAP_S) | |
779 | #define TCAP_F TCAP_V(1U) | |
780 | ||
781 | #define TCIP_S 26 | |
782 | #define TCIP_V(x) ((x) << TCIP_S) | |
783 | #define TCIP_F TCIP_V(1U) | |
784 | ||
785 | #define RCAP_S 25 | |
786 | #define RCAP_V(x) ((x) << RCAP_S) | |
787 | #define RCAP_F RCAP_V(1U) | |
788 | ||
789 | #define PLUP_S 23 | |
790 | #define PLUP_V(x) ((x) << PLUP_S) | |
791 | #define PLUP_F PLUP_V(1U) | |
792 | ||
793 | #define PLDN_S 22 | |
794 | #define PLDN_V(x) ((x) << PLDN_S) | |
795 | #define PLDN_F PLDN_V(1U) | |
796 | ||
797 | #define OTDD_S 21 | |
798 | #define OTDD_V(x) ((x) << OTDD_S) | |
799 | #define OTDD_F OTDD_V(1U) | |
800 | ||
801 | #define GTRP_S 20 | |
802 | #define GTRP_V(x) ((x) << GTRP_S) | |
803 | #define GTRP_F GTRP_V(1U) | |
804 | ||
805 | #define RDPE_S 18 | |
806 | #define RDPE_V(x) ((x) << RDPE_S) | |
807 | #define RDPE_F RDPE_V(1U) | |
808 | ||
809 | #define TDCE_S 17 | |
810 | #define TDCE_V(x) ((x) << TDCE_S) | |
811 | #define TDCE_F TDCE_V(1U) | |
812 | ||
813 | #define TDUE_S 16 | |
814 | #define TDUE_V(x) ((x) << TDUE_S) | |
815 | #define TDUE_F TDUE_V(1U) | |
bbc02c7e | 816 | |
89c3a86c HS |
817 | /* registers for module MC */ |
818 | #define MC_INT_CAUSE_A 0x7518 | |
819 | #define MC_P_INT_CAUSE_A 0x41318 | |
bbc02c7e | 820 | |
89c3a86c HS |
821 | #define ECC_UE_INT_CAUSE_S 2 |
822 | #define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S) | |
823 | #define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U) | |
824 | ||
825 | #define ECC_CE_INT_CAUSE_S 1 | |
826 | #define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S) | |
827 | #define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U) | |
828 | ||
829 | #define PERR_INT_CAUSE_S 0 | |
830 | #define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S) | |
831 | #define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U) | |
832 | ||
833 | #define MC_ECC_STATUS_A 0x751c | |
834 | #define MC_P_ECC_STATUS_A 0x4131c | |
835 | ||
836 | #define ECC_CECNT_S 16 | |
837 | #define ECC_CECNT_M 0xffffU | |
838 | #define ECC_CECNT_V(x) ((x) << ECC_CECNT_S) | |
839 | #define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M) | |
840 | ||
841 | #define ECC_UECNT_S 0 | |
842 | #define ECC_UECNT_M 0xffffU | |
843 | #define ECC_UECNT_V(x) ((x) << ECC_UECNT_S) | |
844 | #define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M) | |
845 | ||
846 | #define MC_BIST_CMD_A 0x7600 | |
847 | ||
848 | #define START_BIST_S 31 | |
849 | #define START_BIST_V(x) ((x) << START_BIST_S) | |
850 | #define START_BIST_F START_BIST_V(1U) | |
851 | ||
852 | #define BIST_CMD_GAP_S 8 | |
853 | #define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S) | |
854 | ||
855 | #define BIST_OPCODE_S 0 | |
856 | #define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S) | |
857 | ||
858 | #define MC_BIST_CMD_ADDR_A 0x7604 | |
859 | #define MC_BIST_CMD_LEN_A 0x7608 | |
860 | #define MC_BIST_DATA_PATTERN_A 0x760c | |
861 | ||
862 | #define MC_BIST_STATUS_RDATA_A 0x7688 | |
863 | ||
864 | /* registers for module MA */ | |
6559a7e8 HS |
865 | #define MA_EDRAM0_BAR_A 0x77c0 |
866 | ||
867 | #define EDRAM0_SIZE_S 0 | |
868 | #define EDRAM0_SIZE_M 0xfffU | |
869 | #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S) | |
870 | #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M) | |
871 | ||
872 | #define MA_EDRAM1_BAR_A 0x77c4 | |
873 | ||
874 | #define EDRAM1_SIZE_S 0 | |
875 | #define EDRAM1_SIZE_M 0xfffU | |
876 | #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S) | |
877 | #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M) | |
878 | ||
879 | #define MA_EXT_MEMORY_BAR_A 0x77c8 | |
880 | ||
881 | #define EXT_MEM_SIZE_S 0 | |
882 | #define EXT_MEM_SIZE_M 0xfffU | |
883 | #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S) | |
884 | #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M) | |
885 | ||
886 | #define MA_EXT_MEMORY1_BAR_A 0x7808 | |
887 | ||
888 | #define EXT_MEM1_SIZE_S 0 | |
889 | #define EXT_MEM1_SIZE_M 0xfffU | |
890 | #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S) | |
891 | #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M) | |
892 | ||
893 | #define MA_EXT_MEMORY0_BAR_A 0x77c8 | |
894 | ||
895 | #define EXT_MEM0_SIZE_S 0 | |
896 | #define EXT_MEM0_SIZE_M 0xfffU | |
897 | #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S) | |
898 | #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M) | |
899 | ||
900 | #define MA_TARGET_MEM_ENABLE_A 0x77d8 | |
901 | ||
902 | #define EXT_MEM_ENABLE_S 2 | |
903 | #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S) | |
904 | #define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U) | |
905 | ||
906 | #define EDRAM1_ENABLE_S 1 | |
907 | #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S) | |
908 | #define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U) | |
909 | ||
910 | #define EDRAM0_ENABLE_S 0 | |
911 | #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S) | |
912 | #define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U) | |
913 | ||
914 | #define EXT_MEM1_ENABLE_S 4 | |
915 | #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S) | |
916 | #define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U) | |
917 | ||
918 | #define EXT_MEM0_ENABLE_S 2 | |
919 | #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S) | |
920 | #define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U) | |
bbc02c7e | 921 | |
89c3a86c HS |
922 | #define MA_INT_CAUSE_A 0x77e0 |
923 | ||
924 | #define MEM_PERR_INT_CAUSE_S 1 | |
925 | #define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S) | |
926 | #define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U) | |
927 | ||
928 | #define MEM_WRAP_INT_CAUSE_S 0 | |
929 | #define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S) | |
930 | #define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U) | |
931 | ||
932 | #define MA_INT_WRAP_STATUS_A 0x77e4 | |
933 | ||
934 | #define MEM_WRAP_ADDRESS_S 4 | |
935 | #define MEM_WRAP_ADDRESS_M 0xfffffffU | |
936 | #define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M) | |
937 | ||
938 | #define MEM_WRAP_CLIENT_NUM_S 0 | |
939 | #define MEM_WRAP_CLIENT_NUM_M 0xfU | |
940 | #define MEM_WRAP_CLIENT_NUM_G(x) \ | |
941 | (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M) | |
942 | ||
943 | #define MA_PARITY_ERROR_STATUS_A 0x77f4 | |
944 | #define MA_PARITY_ERROR_STATUS1_A 0x77f4 | |
945 | #define MA_PARITY_ERROR_STATUS2_A 0x7804 | |
946 | ||
947 | /* registers for module EDC_0 */ | |
948 | #define EDC_0_BASE_ADDR 0x7900 | |
949 | ||
950 | #define EDC_BIST_CMD_A 0x7904 | |
951 | #define EDC_BIST_CMD_ADDR_A 0x7908 | |
952 | #define EDC_BIST_CMD_LEN_A 0x790c | |
953 | #define EDC_BIST_DATA_PATTERN_A 0x7910 | |
954 | #define EDC_BIST_STATUS_RDATA_A 0x7928 | |
955 | #define EDC_INT_CAUSE_A 0x7978 | |
956 | ||
957 | #define ECC_UE_PAR_S 5 | |
958 | #define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S) | |
959 | #define ECC_UE_PAR_F ECC_UE_PAR_V(1U) | |
960 | ||
961 | #define ECC_CE_PAR_S 4 | |
962 | #define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S) | |
963 | #define ECC_CE_PAR_F ECC_CE_PAR_V(1U) | |
964 | ||
965 | #define PERR_PAR_CAUSE_S 3 | |
966 | #define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S) | |
967 | #define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U) | |
968 | ||
969 | #define EDC_ECC_STATUS_A 0x797c | |
970 | ||
971 | /* registers for module EDC_1 */ | |
972 | #define EDC_1_BASE_ADDR 0x7980 | |
973 | ||
974 | /* registers for module CIM */ | |
975 | #define CIM_BOOT_CFG_A 0x7b00 | |
bf7c781d | 976 | #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290 |
89c3a86c HS |
977 | |
978 | #define BOOTADDR_M 0xffffff00U | |
979 | ||
980 | #define UPCRST_S 0 | |
981 | #define UPCRST_V(x) ((x) << UPCRST_S) | |
982 | #define UPCRST_F UPCRST_V(1U) | |
983 | ||
984 | #define CIM_PF_MAILBOX_DATA_A 0x240 | |
985 | #define CIM_PF_MAILBOX_CTRL_A 0x280 | |
986 | ||
987 | #define MBMSGVALID_S 3 | |
988 | #define MBMSGVALID_V(x) ((x) << MBMSGVALID_S) | |
989 | #define MBMSGVALID_F MBMSGVALID_V(1U) | |
990 | ||
991 | #define MBINTREQ_S 2 | |
992 | #define MBINTREQ_V(x) ((x) << MBINTREQ_S) | |
993 | #define MBINTREQ_F MBINTREQ_V(1U) | |
994 | ||
995 | #define MBOWNER_S 0 | |
996 | #define MBOWNER_M 0x3U | |
997 | #define MBOWNER_V(x) ((x) << MBOWNER_S) | |
998 | #define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M) | |
999 | ||
1000 | #define CIM_PF_HOST_INT_ENABLE_A 0x288 | |
1001 | ||
1002 | #define MBMSGRDYINTEN_S 19 | |
1003 | #define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S) | |
1004 | #define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U) | |
1005 | ||
1006 | #define CIM_PF_HOST_INT_CAUSE_A 0x28c | |
1007 | ||
1008 | #define MBMSGRDYINT_S 19 | |
1009 | #define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S) | |
1010 | #define MBMSGRDYINT_F MBMSGRDYINT_V(1U) | |
1011 | ||
1012 | #define CIM_HOST_INT_CAUSE_A 0x7b2c | |
1013 | ||
1014 | #define TIEQOUTPARERRINT_S 20 | |
1015 | #define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S) | |
1016 | #define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U) | |
1017 | ||
1018 | #define TIEQINPARERRINT_S 19 | |
1019 | #define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S) | |
1020 | #define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U) | |
1021 | ||
1022 | #define PREFDROPINT_S 1 | |
1023 | #define PREFDROPINT_V(x) ((x) << PREFDROPINT_S) | |
1024 | #define PREFDROPINT_F PREFDROPINT_V(1U) | |
1025 | ||
1026 | #define UPACCNONZERO_S 0 | |
1027 | #define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S) | |
1028 | #define UPACCNONZERO_F UPACCNONZERO_V(1U) | |
1029 | ||
1030 | #define MBHOSTPARERR_S 18 | |
1031 | #define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S) | |
1032 | #define MBHOSTPARERR_F MBHOSTPARERR_V(1U) | |
1033 | ||
1034 | #define MBUPPARERR_S 17 | |
1035 | #define MBUPPARERR_V(x) ((x) << MBUPPARERR_S) | |
1036 | #define MBUPPARERR_F MBUPPARERR_V(1U) | |
1037 | ||
1038 | #define IBQTP0PARERR_S 16 | |
1039 | #define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S) | |
1040 | #define IBQTP0PARERR_F IBQTP0PARERR_V(1U) | |
1041 | ||
1042 | #define IBQTP1PARERR_S 15 | |
1043 | #define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S) | |
1044 | #define IBQTP1PARERR_F IBQTP1PARERR_V(1U) | |
1045 | ||
1046 | #define IBQULPPARERR_S 14 | |
1047 | #define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S) | |
1048 | #define IBQULPPARERR_F IBQULPPARERR_V(1U) | |
1049 | ||
1050 | #define IBQSGELOPARERR_S 13 | |
1051 | #define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S) | |
1052 | #define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U) | |
1053 | ||
1054 | #define IBQSGEHIPARERR_S 12 | |
1055 | #define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S) | |
1056 | #define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U) | |
1057 | ||
1058 | #define IBQNCSIPARERR_S 11 | |
1059 | #define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S) | |
1060 | #define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U) | |
1061 | ||
1062 | #define OBQULP0PARERR_S 10 | |
1063 | #define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S) | |
1064 | #define OBQULP0PARERR_F OBQULP0PARERR_V(1U) | |
1065 | ||
1066 | #define OBQULP1PARERR_S 9 | |
1067 | #define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S) | |
1068 | #define OBQULP1PARERR_F OBQULP1PARERR_V(1U) | |
1069 | ||
1070 | #define OBQULP2PARERR_S 8 | |
1071 | #define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S) | |
1072 | #define OBQULP2PARERR_F OBQULP2PARERR_V(1U) | |
1073 | ||
1074 | #define OBQULP3PARERR_S 7 | |
1075 | #define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S) | |
1076 | #define OBQULP3PARERR_F OBQULP3PARERR_V(1U) | |
1077 | ||
1078 | #define OBQSGEPARERR_S 6 | |
1079 | #define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S) | |
1080 | #define OBQSGEPARERR_F OBQSGEPARERR_V(1U) | |
1081 | ||
1082 | #define OBQNCSIPARERR_S 5 | |
1083 | #define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S) | |
1084 | #define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U) | |
1085 | ||
1086 | #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34 | |
1087 | ||
1088 | #define EEPROMWRINT_S 30 | |
1089 | #define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S) | |
1090 | #define EEPROMWRINT_F EEPROMWRINT_V(1U) | |
1091 | ||
1092 | #define TIMEOUTMAINT_S 29 | |
1093 | #define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S) | |
1094 | #define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U) | |
1095 | ||
1096 | #define TIMEOUTINT_S 28 | |
1097 | #define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S) | |
1098 | #define TIMEOUTINT_F TIMEOUTINT_V(1U) | |
1099 | ||
1100 | #define RSPOVRLOOKUPINT_S 27 | |
1101 | #define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S) | |
1102 | #define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U) | |
1103 | ||
1104 | #define REQOVRLOOKUPINT_S 26 | |
1105 | #define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S) | |
1106 | #define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U) | |
1107 | ||
1108 | #define BLKWRPLINT_S 25 | |
1109 | #define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S) | |
1110 | #define BLKWRPLINT_F BLKWRPLINT_V(1U) | |
1111 | ||
1112 | #define BLKRDPLINT_S 24 | |
1113 | #define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S) | |
1114 | #define BLKRDPLINT_F BLKRDPLINT_V(1U) | |
1115 | ||
1116 | #define SGLWRPLINT_S 23 | |
1117 | #define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S) | |
1118 | #define SGLWRPLINT_F SGLWRPLINT_V(1U) | |
1119 | ||
1120 | #define SGLRDPLINT_S 22 | |
1121 | #define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S) | |
1122 | #define SGLRDPLINT_F SGLRDPLINT_V(1U) | |
1123 | ||
1124 | #define BLKWRCTLINT_S 21 | |
1125 | #define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S) | |
1126 | #define BLKWRCTLINT_F BLKWRCTLINT_V(1U) | |
1127 | ||
1128 | #define BLKRDCTLINT_S 20 | |
1129 | #define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S) | |
1130 | #define BLKRDCTLINT_F BLKRDCTLINT_V(1U) | |
1131 | ||
1132 | #define SGLWRCTLINT_S 19 | |
1133 | #define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S) | |
1134 | #define SGLWRCTLINT_F SGLWRCTLINT_V(1U) | |
1135 | ||
1136 | #define SGLRDCTLINT_S 18 | |
1137 | #define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S) | |
1138 | #define SGLRDCTLINT_F SGLRDCTLINT_V(1U) | |
1139 | ||
1140 | #define BLKWREEPROMINT_S 17 | |
1141 | #define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S) | |
1142 | #define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U) | |
1143 | ||
1144 | #define BLKRDEEPROMINT_S 16 | |
1145 | #define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S) | |
1146 | #define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U) | |
1147 | ||
1148 | #define SGLWREEPROMINT_S 15 | |
1149 | #define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S) | |
1150 | #define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U) | |
1151 | ||
1152 | #define SGLRDEEPROMINT_S 14 | |
1153 | #define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S) | |
1154 | #define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U) | |
1155 | ||
1156 | #define BLKWRFLASHINT_S 13 | |
1157 | #define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S) | |
1158 | #define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U) | |
1159 | ||
1160 | #define BLKRDFLASHINT_S 12 | |
1161 | #define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S) | |
1162 | #define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U) | |
1163 | ||
1164 | #define SGLWRFLASHINT_S 11 | |
1165 | #define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S) | |
1166 | #define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U) | |
1167 | ||
1168 | #define SGLRDFLASHINT_S 10 | |
1169 | #define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S) | |
1170 | #define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U) | |
1171 | ||
1172 | #define BLKWRBOOTINT_S 9 | |
1173 | #define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S) | |
1174 | #define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U) | |
1175 | ||
1176 | #define BLKRDBOOTINT_S 8 | |
1177 | #define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S) | |
1178 | #define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U) | |
1179 | ||
1180 | #define SGLWRBOOTINT_S 7 | |
1181 | #define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S) | |
1182 | #define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U) | |
1183 | ||
1184 | #define SGLRDBOOTINT_S 6 | |
1185 | #define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S) | |
1186 | #define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U) | |
1187 | ||
1188 | #define ILLWRBEINT_S 5 | |
1189 | #define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S) | |
1190 | #define ILLWRBEINT_F ILLWRBEINT_V(1U) | |
1191 | ||
1192 | #define ILLRDBEINT_S 4 | |
1193 | #define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S) | |
1194 | #define ILLRDBEINT_F ILLRDBEINT_V(1U) | |
1195 | ||
1196 | #define ILLRDINT_S 3 | |
1197 | #define ILLRDINT_V(x) ((x) << ILLRDINT_S) | |
1198 | #define ILLRDINT_F ILLRDINT_V(1U) | |
1199 | ||
1200 | #define ILLWRINT_S 2 | |
1201 | #define ILLWRINT_V(x) ((x) << ILLWRINT_S) | |
1202 | #define ILLWRINT_F ILLWRINT_V(1U) | |
1203 | ||
1204 | #define ILLTRANSINT_S 1 | |
1205 | #define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S) | |
1206 | #define ILLTRANSINT_F ILLTRANSINT_V(1U) | |
1207 | ||
1208 | #define RSVDSPACEINT_S 0 | |
1209 | #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) | |
1210 | #define RSVDSPACEINT_F RSVDSPACEINT_V(1U) | |
bbc02c7e | 1211 | |
837e4a42 | 1212 | /* registers for module TP */ |
2d277b3b HS |
1213 | #define DBGLAWHLF_S 23 |
1214 | #define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S) | |
1215 | #define DBGLAWHLF_F DBGLAWHLF_V(1U) | |
1216 | ||
1217 | #define DBGLAWPTR_S 16 | |
1218 | #define DBGLAWPTR_M 0x7fU | |
1219 | #define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M) | |
1220 | ||
1221 | #define DBGLAENABLE_S 12 | |
1222 | #define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S) | |
1223 | #define DBGLAENABLE_F DBGLAENABLE_V(1U) | |
1224 | ||
1225 | #define DBGLARPTR_S 0 | |
1226 | #define DBGLARPTR_M 0x7fU | |
1227 | #define DBGLARPTR_V(x) ((x) << DBGLARPTR_S) | |
1228 | ||
1229 | #define TP_DBG_LA_DATAL_A 0x7ed8 | |
1230 | #define TP_DBG_LA_CONFIG_A 0x7ed4 | |
837e4a42 HS |
1231 | #define TP_OUT_CONFIG_A 0x7d04 |
1232 | #define TP_GLOBAL_CONFIG_A 0x7d08 | |
1233 | ||
2d277b3b HS |
1234 | #define DBGLAMODE_S 14 |
1235 | #define DBGLAMODE_M 0x3U | |
1236 | #define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M) | |
1237 | ||
837e4a42 HS |
1238 | #define FIVETUPLELOOKUP_S 17 |
1239 | #define FIVETUPLELOOKUP_M 0x3U | |
1240 | #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S) | |
1241 | #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M) | |
1242 | ||
1243 | #define TP_PARA_REG2_A 0x7d68 | |
1244 | ||
1245 | #define MAXRXDATA_S 16 | |
1246 | #define MAXRXDATA_M 0xffffU | |
1247 | #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M) | |
1248 | ||
1249 | #define TP_TIMER_RESOLUTION_A 0x7d90 | |
1250 | ||
1251 | #define TIMERRESOLUTION_S 16 | |
1252 | #define TIMERRESOLUTION_M 0xffU | |
1253 | #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M) | |
1254 | ||
b58b6676 HS |
1255 | #define TIMESTAMPRESOLUTION_S 8 |
1256 | #define TIMESTAMPRESOLUTION_M 0xffU | |
1257 | #define TIMESTAMPRESOLUTION_G(x) \ | |
1258 | (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M) | |
1259 | ||
837e4a42 HS |
1260 | #define DELAYEDACKRESOLUTION_S 0 |
1261 | #define DELAYEDACKRESOLUTION_M 0xffU | |
1262 | #define DELAYEDACKRESOLUTION_G(x) \ | |
1263 | (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M) | |
1264 | ||
1265 | #define TP_SHIFT_CNT_A 0x7dc0 | |
b58b6676 HS |
1266 | #define TP_RXT_MIN_A 0x7d98 |
1267 | #define TP_RXT_MAX_A 0x7d9c | |
1268 | #define TP_PERS_MIN_A 0x7da0 | |
1269 | #define TP_PERS_MAX_A 0x7da4 | |
1270 | #define TP_KEEP_IDLE_A 0x7da8 | |
1271 | #define TP_KEEP_INTVL_A 0x7dac | |
1272 | #define TP_INIT_SRTT_A 0x7db0 | |
1273 | #define TP_DACK_TIMER_A 0x7db4 | |
1274 | #define TP_FINWAIT2_TIMER_A 0x7db8 | |
1275 | ||
1276 | #define INITSRTT_S 0 | |
1277 | #define INITSRTT_M 0xffffU | |
1278 | #define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M) | |
1279 | ||
1280 | #define PERSMAX_S 0 | |
1281 | #define PERSMAX_M 0x3fffffffU | |
1282 | #define PERSMAX_V(x) ((x) << PERSMAX_S) | |
1283 | #define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M) | |
837e4a42 HS |
1284 | |
1285 | #define SYNSHIFTMAX_S 24 | |
1286 | #define SYNSHIFTMAX_M 0xffU | |
1287 | #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S) | |
1288 | #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M) | |
1289 | ||
1290 | #define RXTSHIFTMAXR1_S 20 | |
1291 | #define RXTSHIFTMAXR1_M 0xfU | |
1292 | #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S) | |
1293 | #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M) | |
1294 | ||
1295 | #define RXTSHIFTMAXR2_S 16 | |
1296 | #define RXTSHIFTMAXR2_M 0xfU | |
1297 | #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S) | |
1298 | #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M) | |
1299 | ||
1300 | #define PERSHIFTBACKOFFMAX_S 12 | |
1301 | #define PERSHIFTBACKOFFMAX_M 0xfU | |
1302 | #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S) | |
1303 | #define PERSHIFTBACKOFFMAX_G(x) \ | |
1304 | (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M) | |
1305 | ||
1306 | #define PERSHIFTMAX_S 8 | |
1307 | #define PERSHIFTMAX_M 0xfU | |
1308 | #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S) | |
1309 | #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M) | |
1310 | ||
1311 | #define KEEPALIVEMAXR1_S 4 | |
1312 | #define KEEPALIVEMAXR1_M 0xfU | |
1313 | #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S) | |
1314 | #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M) | |
1315 | ||
1316 | #define KEEPALIVEMAXR2_S 0 | |
1317 | #define KEEPALIVEMAXR2_M 0xfU | |
1318 | #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S) | |
1319 | #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M) | |
1320 | ||
bad43792 HS |
1321 | #define ROWINDEX_S 16 |
1322 | #define ROWINDEX_V(x) ((x) << ROWINDEX_S) | |
1323 | ||
837e4a42 HS |
1324 | #define TP_CCTRL_TABLE_A 0x7ddc |
1325 | #define TP_MTU_TABLE_A 0x7de4 | |
1326 | ||
1327 | #define MTUINDEX_S 24 | |
1328 | #define MTUINDEX_V(x) ((x) << MTUINDEX_S) | |
1329 | ||
1330 | #define MTUWIDTH_S 16 | |
1331 | #define MTUWIDTH_M 0xfU | |
1332 | #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S) | |
1333 | #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M) | |
1334 | ||
1335 | #define MTUVALUE_S 0 | |
1336 | #define MTUVALUE_M 0x3fffU | |
1337 | #define MTUVALUE_V(x) ((x) << MTUVALUE_S) | |
1338 | #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M) | |
1339 | ||
1340 | #define TP_RSS_LKP_TABLE_A 0x7dec | |
1341 | ||
1342 | #define LKPTBLROWVLD_S 31 | |
1343 | #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S) | |
1344 | #define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U) | |
1345 | ||
1346 | #define LKPTBLQUEUE1_S 10 | |
1347 | #define LKPTBLQUEUE1_M 0x3ffU | |
1348 | #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M) | |
1349 | ||
1350 | #define LKPTBLQUEUE0_S 0 | |
1351 | #define LKPTBLQUEUE0_M 0x3ffU | |
1352 | #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M) | |
1353 | ||
1354 | #define TP_PIO_ADDR_A 0x7e40 | |
1355 | #define TP_PIO_DATA_A 0x7e44 | |
1356 | #define TP_MIB_INDEX_A 0x7e50 | |
1357 | #define TP_MIB_DATA_A 0x7e54 | |
1358 | #define TP_INT_CAUSE_A 0x7e74 | |
1359 | ||
1360 | #define FLMTXFLSTEMPTY_S 30 | |
1361 | #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S) | |
1362 | #define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U) | |
1363 | ||
1364 | #define TP_VLAN_PRI_MAP_A 0x140 | |
1365 | ||
1366 | #define FRAGMENTATION_S 9 | |
1367 | #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S) | |
1368 | #define FRAGMENTATION_F FRAGMENTATION_V(1U) | |
1369 | ||
1370 | #define MPSHITTYPE_S 8 | |
1371 | #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S) | |
1372 | #define MPSHITTYPE_F MPSHITTYPE_V(1U) | |
1373 | ||
1374 | #define MACMATCH_S 7 | |
1375 | #define MACMATCH_V(x) ((x) << MACMATCH_S) | |
1376 | #define MACMATCH_F MACMATCH_V(1U) | |
1377 | ||
1378 | #define ETHERTYPE_S 6 | |
1379 | #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S) | |
1380 | #define ETHERTYPE_F ETHERTYPE_V(1U) | |
1381 | ||
1382 | #define PROTOCOL_S 5 | |
1383 | #define PROTOCOL_V(x) ((x) << PROTOCOL_S) | |
1384 | #define PROTOCOL_F PROTOCOL_V(1U) | |
1385 | ||
1386 | #define TOS_S 4 | |
1387 | #define TOS_V(x) ((x) << TOS_S) | |
1388 | #define TOS_F TOS_V(1U) | |
1389 | ||
1390 | #define VLAN_S 3 | |
1391 | #define VLAN_V(x) ((x) << VLAN_S) | |
1392 | #define VLAN_F VLAN_V(1U) | |
1393 | ||
1394 | #define VNIC_ID_S 2 | |
1395 | #define VNIC_ID_V(x) ((x) << VNIC_ID_S) | |
1396 | #define VNIC_ID_F VNIC_ID_V(1U) | |
1397 | ||
1398 | #define PORT_S 1 | |
1399 | #define PORT_V(x) ((x) << PORT_S) | |
1400 | #define PORT_F PORT_V(1U) | |
1401 | ||
1402 | #define FCOE_S 0 | |
1403 | #define FCOE_V(x) ((x) << FCOE_S) | |
1404 | #define FCOE_F FCOE_V(1U) | |
1405 | ||
1406 | #define FILTERMODE_S 15 | |
1407 | #define FILTERMODE_V(x) ((x) << FILTERMODE_S) | |
1408 | #define FILTERMODE_F FILTERMODE_V(1U) | |
1409 | ||
1410 | #define FCOEMASK_S 14 | |
1411 | #define FCOEMASK_V(x) ((x) << FCOEMASK_S) | |
1412 | #define FCOEMASK_F FCOEMASK_V(1U) | |
1413 | ||
1414 | #define TP_INGRESS_CONFIG_A 0x141 | |
1415 | ||
1416 | #define VNIC_S 11 | |
1417 | #define VNIC_V(x) ((x) << VNIC_S) | |
1418 | #define VNIC_F VNIC_V(1U) | |
1419 | ||
1420 | #define CSUM_HAS_PSEUDO_HDR_S 10 | |
1421 | #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S) | |
1422 | #define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U) | |
1423 | ||
1424 | #define TP_MIB_MAC_IN_ERR_0_A 0x0 | |
a4cfd929 HS |
1425 | #define TP_MIB_HDR_IN_ERR_0_A 0x4 |
1426 | #define TP_MIB_TCP_IN_ERR_0_A 0x8 | |
837e4a42 HS |
1427 | #define TP_MIB_TCP_OUT_RST_A 0xc |
1428 | #define TP_MIB_TCP_IN_SEG_HI_A 0x10 | |
1429 | #define TP_MIB_TCP_IN_SEG_LO_A 0x11 | |
1430 | #define TP_MIB_TCP_OUT_SEG_HI_A 0x12 | |
1431 | #define TP_MIB_TCP_OUT_SEG_LO_A 0x13 | |
1432 | #define TP_MIB_TCP_RXT_SEG_HI_A 0x14 | |
1433 | #define TP_MIB_TCP_RXT_SEG_LO_A 0x15 | |
1434 | #define TP_MIB_TNL_CNG_DROP_0_A 0x18 | |
a4cfd929 | 1435 | #define TP_MIB_OFD_CHN_DROP_0_A 0x1c |
837e4a42 HS |
1436 | #define TP_MIB_TCP_V6IN_ERR_0_A 0x28 |
1437 | #define TP_MIB_TCP_V6OUT_RST_A 0x2c | |
1438 | #define TP_MIB_OFD_ARP_DROP_A 0x36 | |
a6222975 HS |
1439 | #define TP_MIB_CPL_IN_REQ_0_A 0x38 |
1440 | #define TP_MIB_CPL_OUT_RSP_0_A 0x3c | |
837e4a42 | 1441 | #define TP_MIB_TNL_DROP_0_A 0x44 |
a6222975 HS |
1442 | #define TP_MIB_FCOE_DDP_0_A 0x48 |
1443 | #define TP_MIB_FCOE_DROP_0_A 0x4c | |
1444 | #define TP_MIB_FCOE_BYTE_0_HI_A 0x50 | |
837e4a42 | 1445 | #define TP_MIB_OFD_VLN_DROP_0_A 0x58 |
a4cfd929 HS |
1446 | #define TP_MIB_USM_PKTS_A 0x5c |
1447 | #define TP_MIB_RQE_DFR_PKT_A 0x64 | |
837e4a42 HS |
1448 | |
1449 | #define ULP_TX_INT_CAUSE_A 0x8dcc | |
1450 | ||
1451 | #define PBL_BOUND_ERR_CH3_S 31 | |
1452 | #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S) | |
1453 | #define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U) | |
1454 | ||
1455 | #define PBL_BOUND_ERR_CH2_S 30 | |
1456 | #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S) | |
1457 | #define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U) | |
1458 | ||
1459 | #define PBL_BOUND_ERR_CH1_S 29 | |
1460 | #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S) | |
1461 | #define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U) | |
1462 | ||
1463 | #define PBL_BOUND_ERR_CH0_S 28 | |
1464 | #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S) | |
1465 | #define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U) | |
1466 | ||
1467 | #define PM_RX_INT_CAUSE_A 0x8fdc | |
b3bbe36a HS |
1468 | #define PM_RX_STAT_CONFIG_A 0x8fc8 |
1469 | #define PM_RX_STAT_COUNT_A 0x8fcc | |
1470 | #define PM_RX_STAT_LSB_A 0x8fd0 | |
1471 | #define PM_RX_DBG_CTRL_A 0x8fd0 | |
1472 | #define PM_RX_DBG_DATA_A 0x8fd4 | |
1473 | #define PM_RX_DBG_STAT_MSB_A 0x10013 | |
837e4a42 HS |
1474 | |
1475 | #define PMRX_FRAMING_ERROR_F 0x003ffff0U | |
1476 | ||
1477 | #define ZERO_E_CMD_ERROR_S 22 | |
1478 | #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S) | |
1479 | #define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U) | |
1480 | ||
1481 | #define OCSPI_PAR_ERROR_S 3 | |
1482 | #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S) | |
1483 | #define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U) | |
1484 | ||
1485 | #define DB_OPTIONS_PAR_ERROR_S 2 | |
1486 | #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S) | |
1487 | #define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U) | |
1488 | ||
1489 | #define IESPI_PAR_ERROR_S 1 | |
1490 | #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S) | |
1491 | #define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U) | |
1492 | ||
1493 | #define PMRX_E_PCMD_PAR_ERROR_S 0 | |
1494 | #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S) | |
1495 | #define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U) | |
1496 | ||
1497 | #define PM_TX_INT_CAUSE_A 0x8ffc | |
b3bbe36a HS |
1498 | #define PM_TX_STAT_CONFIG_A 0x8fe8 |
1499 | #define PM_TX_STAT_COUNT_A 0x8fec | |
1500 | #define PM_TX_STAT_LSB_A 0x8ff0 | |
1501 | #define PM_TX_DBG_CTRL_A 0x8ff0 | |
1502 | #define PM_TX_DBG_DATA_A 0x8ff4 | |
1503 | #define PM_TX_DBG_STAT_MSB_A 0x1001a | |
837e4a42 HS |
1504 | |
1505 | #define PCMD_LEN_OVFL0_S 31 | |
1506 | #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S) | |
1507 | #define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U) | |
1508 | ||
1509 | #define PCMD_LEN_OVFL1_S 30 | |
1510 | #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S) | |
1511 | #define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U) | |
1512 | ||
1513 | #define PCMD_LEN_OVFL2_S 29 | |
1514 | #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S) | |
1515 | #define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U) | |
1516 | ||
1517 | #define ZERO_C_CMD_ERROR_S 28 | |
1518 | #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S) | |
1519 | #define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U) | |
1520 | ||
1521 | #define PMTX_FRAMING_ERROR_F 0x0ffffff0U | |
1522 | ||
1523 | #define OESPI_PAR_ERROR_S 3 | |
1524 | #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S) | |
1525 | #define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U) | |
1526 | ||
1527 | #define ICSPI_PAR_ERROR_S 1 | |
1528 | #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S) | |
1529 | #define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U) | |
1530 | ||
1531 | #define PMTX_C_PCMD_PAR_ERROR_S 0 | |
1532 | #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S) | |
1533 | #define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U) | |
bbc02c7e DM |
1534 | |
1535 | #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 | |
1536 | #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 | |
1537 | #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 | |
1538 | #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c | |
1539 | #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 | |
1540 | #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 | |
1541 | #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 | |
1542 | #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c | |
1543 | #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 | |
1544 | #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 | |
1545 | #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 | |
1546 | #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c | |
1547 | #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 | |
1548 | #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 | |
1549 | #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 | |
1550 | #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c | |
1551 | #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 | |
1552 | #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 | |
1553 | #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 | |
1554 | #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c | |
1555 | #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 | |
1556 | #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 | |
1557 | #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 | |
1558 | #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c | |
1559 | #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 | |
1560 | #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 | |
1561 | #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 | |
1562 | #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c | |
1563 | #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 | |
1564 | #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 | |
1565 | #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 | |
1566 | #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c | |
1567 | #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 | |
1568 | #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 | |
1569 | #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 | |
1570 | #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c | |
1571 | #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 | |
1572 | #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 | |
1573 | #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 | |
1574 | #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c | |
1575 | #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 | |
1576 | #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 | |
1577 | #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 | |
1578 | #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac | |
1579 | #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 | |
1580 | #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 | |
1581 | #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 | |
1582 | #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 | |
1583 | #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 | |
1584 | #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc | |
1585 | #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 | |
1586 | #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 | |
1587 | #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 | |
1588 | #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc | |
1589 | #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 | |
1590 | #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 | |
1591 | #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 | |
1592 | #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec | |
1593 | #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 | |
1594 | #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 | |
1595 | #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 | |
1596 | #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc | |
1597 | #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 | |
1598 | #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 | |
1599 | #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 | |
1600 | #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c | |
1601 | #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 | |
1602 | #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 | |
1603 | #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 | |
1604 | #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c | |
1605 | #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 | |
1606 | #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 | |
1607 | #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 | |
65046e84 | 1608 | #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 |
bbc02c7e DM |
1609 | #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 |
1610 | #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 | |
1611 | #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 | |
1612 | #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c | |
1613 | #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 | |
1614 | #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 | |
1615 | #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 | |
1616 | #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c | |
1617 | #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 | |
1618 | #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 | |
1619 | #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 | |
1620 | #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c | |
1621 | #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 | |
1622 | #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 | |
1623 | #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 | |
1624 | #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c | |
1625 | #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 | |
1626 | #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 | |
1627 | #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 | |
1628 | #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c | |
1629 | #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 | |
1630 | #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 | |
1631 | #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 | |
1632 | #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c | |
1633 | #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 | |
1634 | #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 | |
1635 | #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 | |
1636 | #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac | |
1637 | #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 | |
1638 | #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 | |
1639 | #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 | |
1640 | #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc | |
1641 | #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 | |
1642 | #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 | |
1643 | #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 | |
1644 | #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc | |
1645 | #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 | |
1646 | #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 | |
1647 | #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 | |
1648 | #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc | |
1649 | #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 | |
1650 | #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 | |
1651 | #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 | |
1652 | #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec | |
1653 | #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 | |
1654 | #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 | |
1655 | #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 | |
1656 | #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc | |
1657 | #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 | |
1658 | #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 | |
1659 | #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 | |
1660 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c | |
1661 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 | |
1662 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 | |
b2decadd SR |
1663 | #define MAC_PORT_MAGIC_MACID_LO 0x824 |
1664 | #define MAC_PORT_MAGIC_MACID_HI 0x828 | |
837e4a42 HS |
1665 | |
1666 | #define MAC_PORT_EPIO_DATA0_A 0x8c0 | |
1667 | #define MAC_PORT_EPIO_DATA1_A 0x8c4 | |
1668 | #define MAC_PORT_EPIO_DATA2_A 0x8c8 | |
1669 | #define MAC_PORT_EPIO_DATA3_A 0x8cc | |
1670 | #define MAC_PORT_EPIO_OP_A 0x8d0 | |
1671 | ||
1672 | #define MAC_PORT_CFG2_A 0x818 | |
1673 | ||
1674 | #define MPS_CMN_CTL_A 0x9000 | |
1675 | ||
1676 | #define NUMPORTS_S 0 | |
1677 | #define NUMPORTS_M 0x3U | |
1678 | #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M) | |
1679 | ||
1680 | #define MPS_INT_CAUSE_A 0x9008 | |
1681 | #define MPS_TX_INT_CAUSE_A 0x9408 | |
1682 | ||
1683 | #define FRMERR_S 15 | |
1684 | #define FRMERR_V(x) ((x) << FRMERR_S) | |
1685 | #define FRMERR_F FRMERR_V(1U) | |
1686 | ||
1687 | #define SECNTERR_S 14 | |
1688 | #define SECNTERR_V(x) ((x) << SECNTERR_S) | |
1689 | #define SECNTERR_F SECNTERR_V(1U) | |
1690 | ||
1691 | #define BUBBLE_S 13 | |
1692 | #define BUBBLE_V(x) ((x) << BUBBLE_S) | |
1693 | #define BUBBLE_F BUBBLE_V(1U) | |
1694 | ||
1695 | #define TXDESCFIFO_S 9 | |
1696 | #define TXDESCFIFO_M 0xfU | |
1697 | #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S) | |
1698 | ||
1699 | #define TXDATAFIFO_S 5 | |
1700 | #define TXDATAFIFO_M 0xfU | |
1701 | #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S) | |
1702 | ||
1703 | #define NCSIFIFO_S 4 | |
1704 | #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S) | |
1705 | #define NCSIFIFO_F NCSIFIFO_V(1U) | |
1706 | ||
1707 | #define TPFIFO_S 0 | |
1708 | #define TPFIFO_M 0xfU | |
1709 | #define TPFIFO_V(x) ((x) << TPFIFO_S) | |
1710 | ||
1711 | #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614 | |
1712 | #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620 | |
1713 | #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c | |
bbc02c7e DM |
1714 | |
1715 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 | |
1716 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 | |
1717 | #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 | |
1718 | #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c | |
1719 | #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 | |
1720 | #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 | |
1721 | #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 | |
1722 | #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c | |
1723 | #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 | |
1724 | #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 | |
1725 | #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 | |
1726 | #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c | |
1727 | #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 | |
1728 | #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 | |
1729 | #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 | |
1730 | #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c | |
1731 | #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 | |
1732 | #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 | |
1733 | #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 | |
1734 | #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c | |
1735 | #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 | |
1736 | #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 | |
1737 | #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 | |
1738 | #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c | |
1739 | #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 | |
1740 | #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 | |
1741 | #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 | |
1742 | #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac | |
1743 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 | |
1744 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 | |
1745 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 | |
1746 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc | |
837e4a42 HS |
1747 | |
1748 | #define MPS_TRC_CFG_A 0x9800 | |
1749 | ||
1750 | #define TRCFIFOEMPTY_S 4 | |
1751 | #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S) | |
1752 | #define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U) | |
1753 | ||
1754 | #define TRCIGNOREDROPINPUT_S 3 | |
1755 | #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S) | |
1756 | #define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U) | |
1757 | ||
1758 | #define TRCKEEPDUPLICATES_S 2 | |
1759 | #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S) | |
1760 | #define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U) | |
1761 | ||
1762 | #define TRCEN_S 1 | |
1763 | #define TRCEN_V(x) ((x) << TRCEN_S) | |
1764 | #define TRCEN_F TRCEN_V(1U) | |
1765 | ||
1766 | #define TRCMULTIFILTER_S 0 | |
1767 | #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S) | |
1768 | #define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U) | |
1769 | ||
1770 | #define MPS_TRC_RSS_CONTROL_A 0x9808 | |
1771 | #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c | |
1772 | ||
1773 | #define RSSCONTROL_S 16 | |
1774 | #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S) | |
1775 | ||
1776 | #define QUEUENUMBER_S 0 | |
1777 | #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S) | |
1778 | ||
688ea5fe HS |
1779 | #define TP_RSS_CONFIG_A 0x7df0 |
1780 | ||
1781 | #define TNL4TUPENIPV6_S 31 | |
1782 | #define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S) | |
1783 | #define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U) | |
1784 | ||
1785 | #define TNL2TUPENIPV6_S 30 | |
1786 | #define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S) | |
1787 | #define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U) | |
1788 | ||
1789 | #define TNL4TUPENIPV4_S 29 | |
1790 | #define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S) | |
1791 | #define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U) | |
1792 | ||
1793 | #define TNL2TUPENIPV4_S 28 | |
1794 | #define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S) | |
1795 | #define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U) | |
1796 | ||
1797 | #define TNLTCPSEL_S 27 | |
1798 | #define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S) | |
1799 | #define TNLTCPSEL_F TNLTCPSEL_V(1U) | |
1800 | ||
1801 | #define TNLIP6SEL_S 26 | |
1802 | #define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S) | |
1803 | #define TNLIP6SEL_F TNLIP6SEL_V(1U) | |
1804 | ||
1805 | #define TNLVRTSEL_S 25 | |
1806 | #define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S) | |
1807 | #define TNLVRTSEL_F TNLVRTSEL_V(1U) | |
1808 | ||
1809 | #define TNLMAPEN_S 24 | |
1810 | #define TNLMAPEN_V(x) ((x) << TNLMAPEN_S) | |
1811 | #define TNLMAPEN_F TNLMAPEN_V(1U) | |
1812 | ||
1813 | #define OFDHASHSAVE_S 19 | |
1814 | #define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S) | |
1815 | #define OFDHASHSAVE_F OFDHASHSAVE_V(1U) | |
1816 | ||
1817 | #define OFDVRTSEL_S 18 | |
1818 | #define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S) | |
1819 | #define OFDVRTSEL_F OFDVRTSEL_V(1U) | |
1820 | ||
1821 | #define OFDMAPEN_S 17 | |
1822 | #define OFDMAPEN_V(x) ((x) << OFDMAPEN_S) | |
1823 | #define OFDMAPEN_F OFDMAPEN_V(1U) | |
1824 | ||
1825 | #define OFDLKPEN_S 16 | |
1826 | #define OFDLKPEN_V(x) ((x) << OFDLKPEN_S) | |
1827 | #define OFDLKPEN_F OFDLKPEN_V(1U) | |
1828 | ||
1829 | #define SYN4TUPENIPV6_S 15 | |
1830 | #define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S) | |
1831 | #define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U) | |
1832 | ||
1833 | #define SYN2TUPENIPV6_S 14 | |
1834 | #define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S) | |
1835 | #define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U) | |
1836 | ||
1837 | #define SYN4TUPENIPV4_S 13 | |
1838 | #define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S) | |
1839 | #define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U) | |
1840 | ||
1841 | #define SYN2TUPENIPV4_S 12 | |
1842 | #define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S) | |
1843 | #define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U) | |
1844 | ||
1845 | #define SYNIP6SEL_S 11 | |
1846 | #define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S) | |
1847 | #define SYNIP6SEL_F SYNIP6SEL_V(1U) | |
1848 | ||
1849 | #define SYNVRTSEL_S 10 | |
1850 | #define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S) | |
1851 | #define SYNVRTSEL_F SYNVRTSEL_V(1U) | |
1852 | ||
1853 | #define SYNMAPEN_S 9 | |
1854 | #define SYNMAPEN_V(x) ((x) << SYNMAPEN_S) | |
1855 | #define SYNMAPEN_F SYNMAPEN_V(1U) | |
1856 | ||
1857 | #define SYNLKPEN_S 8 | |
1858 | #define SYNLKPEN_V(x) ((x) << SYNLKPEN_S) | |
1859 | #define SYNLKPEN_F SYNLKPEN_V(1U) | |
1860 | ||
1861 | #define CHANNELENABLE_S 7 | |
1862 | #define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S) | |
1863 | #define CHANNELENABLE_F CHANNELENABLE_V(1U) | |
1864 | ||
1865 | #define PORTENABLE_S 6 | |
1866 | #define PORTENABLE_V(x) ((x) << PORTENABLE_S) | |
1867 | #define PORTENABLE_F PORTENABLE_V(1U) | |
1868 | ||
1869 | #define TNLALLLOOKUP_S 5 | |
1870 | #define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S) | |
1871 | #define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U) | |
1872 | ||
1873 | #define VIRTENABLE_S 4 | |
1874 | #define VIRTENABLE_V(x) ((x) << VIRTENABLE_S) | |
1875 | #define VIRTENABLE_F VIRTENABLE_V(1U) | |
1876 | ||
1877 | #define CONGESTIONENABLE_S 3 | |
1878 | #define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S) | |
1879 | #define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U) | |
1880 | ||
1881 | #define HASHTOEPLITZ_S 2 | |
1882 | #define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S) | |
1883 | #define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U) | |
1884 | ||
1885 | #define UDPENABLE_S 1 | |
1886 | #define UDPENABLE_V(x) ((x) << UDPENABLE_S) | |
1887 | #define UDPENABLE_F UDPENABLE_V(1U) | |
1888 | ||
1889 | #define DISABLE_S 0 | |
1890 | #define DISABLE_V(x) ((x) << DISABLE_S) | |
1891 | #define DISABLE_F DISABLE_V(1U) | |
1892 | ||
1893 | #define TP_RSS_CONFIG_TNL_A 0x7df4 | |
1894 | ||
1895 | #define MASKSIZE_S 28 | |
1896 | #define MASKSIZE_M 0xfU | |
1897 | #define MASKSIZE_V(x) ((x) << MASKSIZE_S) | |
1898 | #define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M) | |
1899 | ||
1900 | #define MASKFILTER_S 16 | |
1901 | #define MASKFILTER_M 0x7ffU | |
1902 | #define MASKFILTER_V(x) ((x) << MASKFILTER_S) | |
1903 | #define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M) | |
1904 | ||
1905 | #define USEWIRECH_S 0 | |
1906 | #define USEWIRECH_V(x) ((x) << USEWIRECH_S) | |
1907 | #define USEWIRECH_F USEWIRECH_V(1U) | |
1908 | ||
1909 | #define HASHALL_S 2 | |
1910 | #define HASHALL_V(x) ((x) << HASHALL_S) | |
1911 | #define HASHALL_F HASHALL_V(1U) | |
1912 | ||
1913 | #define HASHETH_S 1 | |
1914 | #define HASHETH_V(x) ((x) << HASHETH_S) | |
1915 | #define HASHETH_F HASHETH_V(1U) | |
1916 | ||
1917 | #define TP_RSS_CONFIG_OFD_A 0x7df8 | |
1918 | ||
1919 | #define RRCPLMAPEN_S 20 | |
1920 | #define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S) | |
1921 | #define RRCPLMAPEN_F RRCPLMAPEN_V(1U) | |
1922 | ||
1923 | #define RRCPLQUEWIDTH_S 16 | |
1924 | #define RRCPLQUEWIDTH_M 0xfU | |
1925 | #define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S) | |
1926 | #define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M) | |
1927 | ||
1928 | #define TP_RSS_CONFIG_SYN_A 0x7dfc | |
1929 | #define TP_RSS_CONFIG_VRT_A 0x7e00 | |
1930 | ||
1931 | #define VFRDRG_S 25 | |
1932 | #define VFRDRG_V(x) ((x) << VFRDRG_S) | |
1933 | #define VFRDRG_F VFRDRG_V(1U) | |
1934 | ||
1935 | #define VFRDEN_S 24 | |
1936 | #define VFRDEN_V(x) ((x) << VFRDEN_S) | |
1937 | #define VFRDEN_F VFRDEN_V(1U) | |
1938 | ||
1939 | #define VFPERREN_S 23 | |
1940 | #define VFPERREN_V(x) ((x) << VFPERREN_S) | |
1941 | #define VFPERREN_F VFPERREN_V(1U) | |
1942 | ||
1943 | #define KEYPERREN_S 22 | |
1944 | #define KEYPERREN_V(x) ((x) << KEYPERREN_S) | |
1945 | #define KEYPERREN_F KEYPERREN_V(1U) | |
1946 | ||
1947 | #define DISABLEVLAN_S 21 | |
1948 | #define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S) | |
1949 | #define DISABLEVLAN_F DISABLEVLAN_V(1U) | |
1950 | ||
1951 | #define ENABLEUP0_S 20 | |
1952 | #define ENABLEUP0_V(x) ((x) << ENABLEUP0_S) | |
1953 | #define ENABLEUP0_F ENABLEUP0_V(1U) | |
1954 | ||
1955 | #define HASHDELAY_S 16 | |
1956 | #define HASHDELAY_M 0xfU | |
1957 | #define HASHDELAY_V(x) ((x) << HASHDELAY_S) | |
1958 | #define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M) | |
1959 | ||
1960 | #define VFWRADDR_S 8 | |
1961 | #define VFWRADDR_M 0x7fU | |
1962 | #define VFWRADDR_V(x) ((x) << VFWRADDR_S) | |
1963 | #define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M) | |
1964 | ||
1965 | #define KEYMODE_S 6 | |
1966 | #define KEYMODE_M 0x3U | |
1967 | #define KEYMODE_V(x) ((x) << KEYMODE_S) | |
1968 | #define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M) | |
1969 | ||
1970 | #define VFWREN_S 5 | |
1971 | #define VFWREN_V(x) ((x) << VFWREN_S) | |
1972 | #define VFWREN_F VFWREN_V(1U) | |
1973 | ||
1974 | #define KEYWREN_S 4 | |
1975 | #define KEYWREN_V(x) ((x) << KEYWREN_S) | |
1976 | #define KEYWREN_F KEYWREN_V(1U) | |
1977 | ||
1978 | #define KEYWRADDR_S 0 | |
1979 | #define KEYWRADDR_M 0xfU | |
1980 | #define KEYWRADDR_V(x) ((x) << KEYWRADDR_S) | |
1981 | #define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M) | |
1982 | ||
1983 | #define KEYWRADDRX_S 30 | |
1984 | #define KEYWRADDRX_M 0x3U | |
1985 | #define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S) | |
1986 | #define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M) | |
1987 | ||
1988 | #define KEYEXTEND_S 26 | |
1989 | #define KEYEXTEND_V(x) ((x) << KEYEXTEND_S) | |
1990 | #define KEYEXTEND_F KEYEXTEND_V(1U) | |
1991 | ||
1992 | #define LKPIDXSIZE_S 24 | |
1993 | #define LKPIDXSIZE_M 0x3U | |
1994 | #define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S) | |
1995 | #define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M) | |
1996 | ||
1997 | #define TP_RSS_VFL_CONFIG_A 0x3a | |
1998 | #define TP_RSS_VFH_CONFIG_A 0x3b | |
1999 | ||
2000 | #define ENABLEUDPHASH_S 31 | |
2001 | #define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S) | |
2002 | #define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U) | |
2003 | ||
2004 | #define VFUPEN_S 30 | |
2005 | #define VFUPEN_V(x) ((x) << VFUPEN_S) | |
2006 | #define VFUPEN_F VFUPEN_V(1U) | |
2007 | ||
2008 | #define VFVLNEX_S 28 | |
2009 | #define VFVLNEX_V(x) ((x) << VFVLNEX_S) | |
2010 | #define VFVLNEX_F VFVLNEX_V(1U) | |
2011 | ||
2012 | #define VFPRTEN_S 27 | |
2013 | #define VFPRTEN_V(x) ((x) << VFPRTEN_S) | |
2014 | #define VFPRTEN_F VFPRTEN_V(1U) | |
2015 | ||
2016 | #define VFCHNEN_S 26 | |
2017 | #define VFCHNEN_V(x) ((x) << VFCHNEN_S) | |
2018 | #define VFCHNEN_F VFCHNEN_V(1U) | |
2019 | ||
2020 | #define DEFAULTQUEUE_S 16 | |
2021 | #define DEFAULTQUEUE_M 0x3ffU | |
2022 | #define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M) | |
2023 | ||
2024 | #define VFIP6TWOTUPEN_S 6 | |
2025 | #define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S) | |
2026 | #define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U) | |
2027 | ||
2028 | #define VFIP4FOURTUPEN_S 5 | |
2029 | #define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S) | |
2030 | #define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U) | |
2031 | ||
2032 | #define VFIP4TWOTUPEN_S 4 | |
2033 | #define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S) | |
2034 | #define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U) | |
2035 | ||
2036 | #define KEYINDEX_S 0 | |
2037 | #define KEYINDEX_M 0xfU | |
2038 | #define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M) | |
2039 | ||
2040 | #define MAPENABLE_S 31 | |
2041 | #define MAPENABLE_V(x) ((x) << MAPENABLE_S) | |
2042 | #define MAPENABLE_F MAPENABLE_V(1U) | |
2043 | ||
2044 | #define CHNENABLE_S 30 | |
2045 | #define CHNENABLE_V(x) ((x) << CHNENABLE_S) | |
2046 | #define CHNENABLE_F CHNENABLE_V(1U) | |
2047 | ||
2048 | #define PRTENABLE_S 29 | |
2049 | #define PRTENABLE_V(x) ((x) << PRTENABLE_S) | |
2050 | #define PRTENABLE_F PRTENABLE_V(1U) | |
2051 | ||
2052 | #define UDPFOURTUPEN_S 28 | |
2053 | #define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S) | |
2054 | #define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U) | |
2055 | ||
2056 | #define IP6FOURTUPEN_S 27 | |
2057 | #define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S) | |
2058 | #define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U) | |
2059 | ||
2060 | #define IP6TWOTUPEN_S 26 | |
2061 | #define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S) | |
2062 | #define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U) | |
2063 | ||
2064 | #define IP4FOURTUPEN_S 25 | |
2065 | #define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S) | |
2066 | #define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U) | |
2067 | ||
2068 | #define IP4TWOTUPEN_S 24 | |
2069 | #define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S) | |
2070 | #define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U) | |
2071 | ||
2072 | #define IVFWIDTH_S 20 | |
2073 | #define IVFWIDTH_M 0xfU | |
2074 | #define IVFWIDTH_V(x) ((x) << IVFWIDTH_S) | |
2075 | #define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M) | |
2076 | ||
2077 | #define CH1DEFAULTQUEUE_S 10 | |
2078 | #define CH1DEFAULTQUEUE_M 0x3ffU | |
2079 | #define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S) | |
2080 | #define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M) | |
2081 | ||
2082 | #define CH0DEFAULTQUEUE_S 0 | |
2083 | #define CH0DEFAULTQUEUE_M 0x3ffU | |
2084 | #define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S) | |
2085 | #define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M) | |
2086 | ||
2087 | #define VFLKPIDX_S 8 | |
2088 | #define VFLKPIDX_M 0xffU | |
2089 | #define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M) | |
2090 | ||
3ccc6cf7 HS |
2091 | #define T6_VFWRADDR_S 8 |
2092 | #define T6_VFWRADDR_M 0xffU | |
2093 | #define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S) | |
2094 | #define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M) | |
2095 | ||
688ea5fe HS |
2096 | #define TP_RSS_CONFIG_CNG_A 0x7e04 |
2097 | #define TP_RSS_SECRET_KEY0_A 0x40 | |
2098 | #define TP_RSS_PF0_CONFIG_A 0x30 | |
2099 | #define TP_RSS_PF_MAP_A 0x38 | |
2100 | #define TP_RSS_PF_MSK_A 0x39 | |
2101 | ||
2102 | #define PF1LKPIDX_S 3 | |
2103 | ||
2104 | #define PF0LKPIDX_M 0x7U | |
2105 | ||
2106 | #define PF1MSKSIZE_S 4 | |
2107 | #define PF1MSKSIZE_M 0xfU | |
2108 | ||
2109 | #define CHNCOUNT3_S 31 | |
2110 | #define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S) | |
2111 | #define CHNCOUNT3_F CHNCOUNT3_V(1U) | |
2112 | ||
2113 | #define CHNCOUNT2_S 30 | |
2114 | #define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S) | |
2115 | #define CHNCOUNT2_F CHNCOUNT2_V(1U) | |
2116 | ||
2117 | #define CHNCOUNT1_S 29 | |
2118 | #define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S) | |
2119 | #define CHNCOUNT1_F CHNCOUNT1_V(1U) | |
2120 | ||
2121 | #define CHNCOUNT0_S 28 | |
2122 | #define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S) | |
2123 | #define CHNCOUNT0_F CHNCOUNT0_V(1U) | |
2124 | ||
2125 | #define CHNUNDFLOW3_S 27 | |
2126 | #define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S) | |
2127 | #define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U) | |
2128 | ||
2129 | #define CHNUNDFLOW2_S 26 | |
2130 | #define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S) | |
2131 | #define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U) | |
2132 | ||
2133 | #define CHNUNDFLOW1_S 25 | |
2134 | #define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S) | |
2135 | #define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U) | |
2136 | ||
2137 | #define CHNUNDFLOW0_S 24 | |
2138 | #define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S) | |
2139 | #define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U) | |
2140 | ||
2141 | #define RSTCHN3_S 19 | |
2142 | #define RSTCHN3_V(x) ((x) << RSTCHN3_S) | |
2143 | #define RSTCHN3_F RSTCHN3_V(1U) | |
2144 | ||
2145 | #define RSTCHN2_S 18 | |
2146 | #define RSTCHN2_V(x) ((x) << RSTCHN2_S) | |
2147 | #define RSTCHN2_F RSTCHN2_V(1U) | |
2148 | ||
2149 | #define RSTCHN1_S 17 | |
2150 | #define RSTCHN1_V(x) ((x) << RSTCHN1_S) | |
2151 | #define RSTCHN1_F RSTCHN1_V(1U) | |
2152 | ||
2153 | #define RSTCHN0_S 16 | |
2154 | #define RSTCHN0_V(x) ((x) << RSTCHN0_S) | |
2155 | #define RSTCHN0_F RSTCHN0_V(1U) | |
2156 | ||
2157 | #define UPDVLD_S 15 | |
2158 | #define UPDVLD_V(x) ((x) << UPDVLD_S) | |
2159 | #define UPDVLD_F UPDVLD_V(1U) | |
2160 | ||
2161 | #define XOFF_S 14 | |
2162 | #define XOFF_V(x) ((x) << XOFF_S) | |
2163 | #define XOFF_F XOFF_V(1U) | |
2164 | ||
2165 | #define UPDCHN3_S 13 | |
2166 | #define UPDCHN3_V(x) ((x) << UPDCHN3_S) | |
2167 | #define UPDCHN3_F UPDCHN3_V(1U) | |
2168 | ||
2169 | #define UPDCHN2_S 12 | |
2170 | #define UPDCHN2_V(x) ((x) << UPDCHN2_S) | |
2171 | #define UPDCHN2_F UPDCHN2_V(1U) | |
2172 | ||
2173 | #define UPDCHN1_S 11 | |
2174 | #define UPDCHN1_V(x) ((x) << UPDCHN1_S) | |
2175 | #define UPDCHN1_F UPDCHN1_V(1U) | |
2176 | ||
2177 | #define UPDCHN0_S 10 | |
2178 | #define UPDCHN0_V(x) ((x) << UPDCHN0_S) | |
2179 | #define UPDCHN0_F UPDCHN0_V(1U) | |
2180 | ||
2181 | #define QUEUE_S 0 | |
2182 | #define QUEUE_M 0x3ffU | |
2183 | #define QUEUE_V(x) ((x) << QUEUE_S) | |
2184 | #define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M) | |
2185 | ||
837e4a42 HS |
2186 | #define MPS_TRC_INT_CAUSE_A 0x985c |
2187 | ||
2188 | #define MISCPERR_S 8 | |
2189 | #define MISCPERR_V(x) ((x) << MISCPERR_S) | |
2190 | #define MISCPERR_F MISCPERR_V(1U) | |
2191 | ||
2192 | #define PKTFIFO_S 4 | |
2193 | #define PKTFIFO_M 0xfU | |
2194 | #define PKTFIFO_V(x) ((x) << PKTFIFO_S) | |
2195 | ||
2196 | #define FILTMEM_S 0 | |
2197 | #define FILTMEM_M 0xfU | |
2198 | #define FILTMEM_V(x) ((x) << FILTMEM_S) | |
2199 | ||
2200 | #define MPS_CLS_INT_CAUSE_A 0xd028 | |
2201 | ||
2202 | #define HASHSRAM_S 2 | |
2203 | #define HASHSRAM_V(x) ((x) << HASHSRAM_S) | |
2204 | #define HASHSRAM_F HASHSRAM_V(1U) | |
2205 | ||
2206 | #define MATCHTCAM_S 1 | |
2207 | #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S) | |
2208 | #define MATCHTCAM_F MATCHTCAM_V(1U) | |
2209 | ||
2210 | #define MATCHSRAM_S 0 | |
2211 | #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S) | |
2212 | #define MATCHSRAM_F MATCHSRAM_V(1U) | |
2213 | ||
2214 | #define MPS_RX_PERR_INT_CAUSE_A 0x11074 | |
bbc02c7e | 2215 | |
ef82f662 | 2216 | #define MPS_CLS_TCAM_Y_L_A 0xf000 |
3ccc6cf7 HS |
2217 | #define MPS_CLS_TCAM_DATA0_A 0xf000 |
2218 | #define MPS_CLS_TCAM_DATA1_A 0xf004 | |
2219 | ||
2220 | #define DMACH_S 0 | |
2221 | #define DMACH_M 0xffffU | |
2222 | #define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M) | |
2223 | ||
ef82f662 | 2224 | #define MPS_CLS_TCAM_X_L_A 0xf008 |
3ccc6cf7 HS |
2225 | #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008 |
2226 | ||
2227 | #define CTLCMDTYPE_S 31 | |
2228 | #define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S) | |
2229 | #define CTLCMDTYPE_F CTLCMDTYPE_V(1U) | |
2230 | ||
2231 | #define CTLTCAMSEL_S 25 | |
2232 | #define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S) | |
2233 | ||
2234 | #define CTLTCAMINDEX_S 17 | |
2235 | #define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S) | |
2236 | ||
2237 | #define CTLXYBITSEL_S 16 | |
2238 | #define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S) | |
ef82f662 HS |
2239 | |
2240 | #define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16) | |
2241 | #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 | |
2242 | ||
2243 | #define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16) | |
2244 | #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 | |
2245 | ||
2246 | #define MPS_CLS_SRAM_L_A 0xe000 | |
3ccc6cf7 HS |
2247 | |
2248 | #define T6_MULTILISTEN0_S 26 | |
2249 | ||
2250 | #define T6_SRAM_PRIO3_S 23 | |
2251 | #define T6_SRAM_PRIO3_M 0x7U | |
2252 | #define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M) | |
2253 | ||
2254 | #define T6_SRAM_PRIO2_S 20 | |
2255 | #define T6_SRAM_PRIO2_M 0x7U | |
2256 | #define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M) | |
2257 | ||
2258 | #define T6_SRAM_PRIO1_S 17 | |
2259 | #define T6_SRAM_PRIO1_M 0x7U | |
2260 | #define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M) | |
2261 | ||
2262 | #define T6_SRAM_PRIO0_S 14 | |
2263 | #define T6_SRAM_PRIO0_M 0x7U | |
2264 | #define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M) | |
2265 | ||
2266 | #define T6_SRAM_VLD_S 13 | |
2267 | #define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S) | |
2268 | #define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U) | |
2269 | ||
2270 | #define T6_REPLICATE_S 12 | |
2271 | #define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S) | |
2272 | #define T6_REPLICATE_F T6_REPLICATE_V(1U) | |
2273 | ||
2274 | #define T6_PF_S 9 | |
2275 | #define T6_PF_M 0x7U | |
2276 | #define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M) | |
2277 | ||
2278 | #define T6_VF_VALID_S 8 | |
2279 | #define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S) | |
2280 | #define T6_VF_VALID_F T6_VF_VALID_V(1U) | |
2281 | ||
2282 | #define T6_VF_S 0 | |
2283 | #define T6_VF_M 0xffU | |
2284 | #define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M) | |
2285 | ||
ef82f662 HS |
2286 | #define MPS_CLS_SRAM_H_A 0xe004 |
2287 | ||
2288 | #define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8) | |
2289 | #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 | |
2290 | ||
2291 | #define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8) | |
2292 | #define NUM_MPS_CLS_SRAM_H_INSTANCES 336 | |
2293 | ||
2294 | #define MULTILISTEN0_S 25 | |
2295 | ||
2296 | #define REPLICATE_S 11 | |
2297 | #define REPLICATE_V(x) ((x) << REPLICATE_S) | |
2298 | #define REPLICATE_F REPLICATE_V(1U) | |
2299 | ||
2300 | #define PF_S 8 | |
2301 | #define PF_M 0x7U | |
2302 | #define PF_G(x) (((x) >> PF_S) & PF_M) | |
2303 | ||
2304 | #define VF_VALID_S 7 | |
2305 | #define VF_VALID_V(x) ((x) << VF_VALID_S) | |
2306 | #define VF_VALID_F VF_VALID_V(1U) | |
2307 | ||
2308 | #define VF_S 0 | |
2309 | #define VF_M 0x7fU | |
2310 | #define VF_G(x) (((x) >> VF_S) & VF_M) | |
2311 | ||
2312 | #define SRAM_PRIO3_S 22 | |
2313 | #define SRAM_PRIO3_M 0x7U | |
2314 | #define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M) | |
2315 | ||
2316 | #define SRAM_PRIO2_S 19 | |
2317 | #define SRAM_PRIO2_M 0x7U | |
2318 | #define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M) | |
2319 | ||
2320 | #define SRAM_PRIO1_S 16 | |
2321 | #define SRAM_PRIO1_M 0x7U | |
2322 | #define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M) | |
2323 | ||
2324 | #define SRAM_PRIO0_S 13 | |
2325 | #define SRAM_PRIO0_M 0x7U | |
2326 | #define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M) | |
2327 | ||
2328 | #define SRAM_VLD_S 12 | |
2329 | #define SRAM_VLD_V(x) ((x) << SRAM_VLD_S) | |
2330 | #define SRAM_VLD_F SRAM_VLD_V(1U) | |
2331 | ||
2332 | #define PORTMAP_S 0 | |
2333 | #define PORTMAP_M 0xfU | |
2334 | #define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M) | |
2335 | ||
0d804338 | 2336 | #define CPL_INTR_CAUSE_A 0x19054 |
bbc02c7e | 2337 | |
0d804338 HS |
2338 | #define CIM_OP_MAP_PERR_S 5 |
2339 | #define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S) | |
2340 | #define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U) | |
2341 | ||
2342 | #define CIM_OVFL_ERROR_S 4 | |
2343 | #define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S) | |
2344 | #define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U) | |
2345 | ||
2346 | #define TP_FRAMING_ERROR_S 3 | |
2347 | #define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S) | |
2348 | #define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U) | |
2349 | ||
2350 | #define SGE_FRAMING_ERROR_S 2 | |
2351 | #define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S) | |
2352 | #define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U) | |
2353 | ||
2354 | #define CIM_FRAMING_ERROR_S 1 | |
2355 | #define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S) | |
2356 | #define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U) | |
2357 | ||
2358 | #define ZERO_SWITCH_ERROR_S 0 | |
2359 | #define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S) | |
2360 | #define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U) | |
2361 | ||
2362 | #define SMB_INT_CAUSE_A 0x19090 | |
2363 | ||
2364 | #define MSTTXFIFOPARINT_S 21 | |
2365 | #define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S) | |
2366 | #define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U) | |
2367 | ||
2368 | #define MSTRXFIFOPARINT_S 20 | |
2369 | #define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S) | |
2370 | #define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U) | |
2371 | ||
2372 | #define SLVFIFOPARINT_S 19 | |
2373 | #define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S) | |
2374 | #define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U) | |
2375 | ||
2376 | #define ULP_RX_INT_CAUSE_A 0x19158 | |
2377 | #define ULP_RX_ISCSI_TAGMASK_A 0x19164 | |
2378 | #define ULP_RX_ISCSI_PSZ_A 0x19168 | |
797ff0f5 HS |
2379 | #define ULP_RX_LA_CTL_A 0x1923c |
2380 | #define ULP_RX_LA_RDPTR_A 0x19240 | |
2381 | #define ULP_RX_LA_RDDATA_A 0x19244 | |
2382 | #define ULP_RX_LA_WRPTR_A 0x19248 | |
0d804338 HS |
2383 | |
2384 | #define HPZ3_S 24 | |
2385 | #define HPZ3_V(x) ((x) << HPZ3_S) | |
2386 | ||
2387 | #define HPZ2_S 16 | |
2388 | #define HPZ2_V(x) ((x) << HPZ2_S) | |
2389 | ||
2390 | #define HPZ1_S 8 | |
2391 | #define HPZ1_V(x) ((x) << HPZ1_S) | |
2392 | ||
2393 | #define HPZ0_S 0 | |
2394 | #define HPZ0_V(x) ((x) << HPZ0_S) | |
2395 | ||
2396 | #define ULP_RX_TDDP_PSZ_A 0x19178 | |
2397 | ||
2398 | /* registers for module SF */ | |
2399 | #define SF_DATA_A 0x193f8 | |
2400 | #define SF_OP_A 0x193fc | |
2401 | ||
2402 | #define SF_BUSY_S 31 | |
2403 | #define SF_BUSY_V(x) ((x) << SF_BUSY_S) | |
2404 | #define SF_BUSY_F SF_BUSY_V(1U) | |
2405 | ||
2406 | #define SF_LOCK_S 4 | |
2407 | #define SF_LOCK_V(x) ((x) << SF_LOCK_S) | |
2408 | #define SF_LOCK_F SF_LOCK_V(1U) | |
2409 | ||
2410 | #define SF_CONT_S 3 | |
2411 | #define SF_CONT_V(x) ((x) << SF_CONT_S) | |
2412 | #define SF_CONT_F SF_CONT_V(1U) | |
2413 | ||
2414 | #define BYTECNT_S 1 | |
2415 | #define BYTECNT_V(x) ((x) << BYTECNT_S) | |
2416 | ||
2417 | #define OP_S 0 | |
2418 | #define OP_V(x) ((x) << OP_S) | |
2419 | #define OP_F OP_V(1U) | |
2420 | ||
2421 | #define PL_PF_INT_CAUSE_A 0x3c0 | |
2422 | ||
2423 | #define PFSW_S 3 | |
2424 | #define PFSW_V(x) ((x) << PFSW_S) | |
2425 | #define PFSW_F PFSW_V(1U) | |
2426 | ||
2427 | #define PFCIM_S 1 | |
2428 | #define PFCIM_V(x) ((x) << PFCIM_S) | |
2429 | #define PFCIM_F PFCIM_V(1U) | |
2430 | ||
2431 | #define PL_PF_INT_ENABLE_A 0x3c4 | |
2432 | #define PL_PF_CTL_A 0x3c8 | |
2433 | ||
2434 | #define PL_WHOAMI_A 0x19400 | |
2435 | ||
2436 | #define SOURCEPF_S 8 | |
2437 | #define SOURCEPF_M 0x7U | |
2438 | #define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M) | |
2439 | ||
2440 | #define PL_INT_CAUSE_A 0x1940c | |
2441 | ||
2442 | #define ULP_TX_S 27 | |
2443 | #define ULP_TX_V(x) ((x) << ULP_TX_S) | |
2444 | #define ULP_TX_F ULP_TX_V(1U) | |
2445 | ||
2446 | #define SGE_S 26 | |
2447 | #define SGE_V(x) ((x) << SGE_S) | |
2448 | #define SGE_F SGE_V(1U) | |
2449 | ||
2450 | #define CPL_SWITCH_S 24 | |
2451 | #define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S) | |
2452 | #define CPL_SWITCH_F CPL_SWITCH_V(1U) | |
2453 | ||
2454 | #define ULP_RX_S 23 | |
2455 | #define ULP_RX_V(x) ((x) << ULP_RX_S) | |
2456 | #define ULP_RX_F ULP_RX_V(1U) | |
2457 | ||
2458 | #define PM_RX_S 22 | |
2459 | #define PM_RX_V(x) ((x) << PM_RX_S) | |
2460 | #define PM_RX_F PM_RX_V(1U) | |
2461 | ||
2462 | #define PM_TX_S 21 | |
2463 | #define PM_TX_V(x) ((x) << PM_TX_S) | |
2464 | #define PM_TX_F PM_TX_V(1U) | |
2465 | ||
2466 | #define MA_S 20 | |
2467 | #define MA_V(x) ((x) << MA_S) | |
2468 | #define MA_F MA_V(1U) | |
bbc02c7e | 2469 | |
0d804338 HS |
2470 | #define TP_S 19 |
2471 | #define TP_V(x) ((x) << TP_S) | |
2472 | #define TP_F TP_V(1U) | |
bbc02c7e | 2473 | |
0d804338 HS |
2474 | #define LE_S 18 |
2475 | #define LE_V(x) ((x) << LE_S) | |
2476 | #define LE_F LE_V(1U) | |
dca4faeb | 2477 | |
0d804338 HS |
2478 | #define EDC1_S 17 |
2479 | #define EDC1_V(x) ((x) << EDC1_S) | |
2480 | #define EDC1_F EDC1_V(1U) | |
dca4faeb | 2481 | |
0d804338 HS |
2482 | #define EDC0_S 16 |
2483 | #define EDC0_V(x) ((x) << EDC0_S) | |
2484 | #define EDC0_F EDC0_V(1U) | |
dca4faeb | 2485 | |
0d804338 HS |
2486 | #define MC_S 15 |
2487 | #define MC_V(x) ((x) << MC_S) | |
2488 | #define MC_F MC_V(1U) | |
dca4faeb | 2489 | |
0d804338 HS |
2490 | #define PCIE_S 14 |
2491 | #define PCIE_V(x) ((x) << PCIE_S) | |
2492 | #define PCIE_F PCIE_V(1U) | |
dca4faeb | 2493 | |
0d804338 HS |
2494 | #define XGMAC_KR1_S 12 |
2495 | #define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S) | |
2496 | #define XGMAC_KR1_F XGMAC_KR1_V(1U) | |
dca4faeb | 2497 | |
0d804338 HS |
2498 | #define XGMAC_KR0_S 11 |
2499 | #define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S) | |
2500 | #define XGMAC_KR0_F XGMAC_KR0_V(1U) | |
dca4faeb | 2501 | |
0d804338 HS |
2502 | #define XGMAC1_S 10 |
2503 | #define XGMAC1_V(x) ((x) << XGMAC1_S) | |
2504 | #define XGMAC1_F XGMAC1_V(1U) | |
dca4faeb | 2505 | |
0d804338 HS |
2506 | #define XGMAC0_S 9 |
2507 | #define XGMAC0_V(x) ((x) << XGMAC0_S) | |
2508 | #define XGMAC0_F XGMAC0_V(1U) | |
dca4faeb | 2509 | |
0d804338 HS |
2510 | #define SMB_S 8 |
2511 | #define SMB_V(x) ((x) << SMB_S) | |
2512 | #define SMB_F SMB_V(1U) | |
dca4faeb | 2513 | |
0d804338 HS |
2514 | #define SF_S 7 |
2515 | #define SF_V(x) ((x) << SF_S) | |
2516 | #define SF_F SF_V(1U) | |
dca4faeb | 2517 | |
0d804338 HS |
2518 | #define PL_S 6 |
2519 | #define PL_V(x) ((x) << PL_S) | |
2520 | #define PL_F PL_V(1U) | |
dca4faeb | 2521 | |
0d804338 HS |
2522 | #define NCSI_S 5 |
2523 | #define NCSI_V(x) ((x) << NCSI_S) | |
2524 | #define NCSI_F NCSI_V(1U) | |
dcf7b6f5 | 2525 | |
0d804338 HS |
2526 | #define MPS_S 4 |
2527 | #define MPS_V(x) ((x) << MPS_S) | |
2528 | #define MPS_F MPS_V(1U) | |
dcf7b6f5 | 2529 | |
0d804338 HS |
2530 | #define CIM_S 0 |
2531 | #define CIM_V(x) ((x) << CIM_S) | |
2532 | #define CIM_F CIM_V(1U) | |
dcf7b6f5 | 2533 | |
0d804338 | 2534 | #define MC1_S 31 |
3ccc6cf7 HS |
2535 | #define MC1_V(x) ((x) << MC1_S) |
2536 | #define MC1_F MC1_V(1U) | |
dcf7b6f5 | 2537 | |
0d804338 HS |
2538 | #define PL_INT_ENABLE_A 0x19410 |
2539 | #define PL_INT_MAP0_A 0x19414 | |
2540 | #define PL_RST_A 0x19428 | |
dcf7b6f5 | 2541 | |
0d804338 HS |
2542 | #define PIORST_S 1 |
2543 | #define PIORST_V(x) ((x) << PIORST_S) | |
2544 | #define PIORST_F PIORST_V(1U) | |
7c89e555 | 2545 | |
0d804338 HS |
2546 | #define PIORSTMODE_S 0 |
2547 | #define PIORSTMODE_V(x) ((x) << PIORSTMODE_S) | |
2548 | #define PIORSTMODE_F PIORSTMODE_V(1U) | |
dcf7b6f5 | 2549 | |
0d804338 | 2550 | #define PL_PL_INT_CAUSE_A 0x19430 |
dcf7b6f5 | 2551 | |
0d804338 HS |
2552 | #define FATALPERR_S 4 |
2553 | #define FATALPERR_V(x) ((x) << FATALPERR_S) | |
2554 | #define FATALPERR_F FATALPERR_V(1U) | |
dcf7b6f5 | 2555 | |
0d804338 HS |
2556 | #define PERRVFID_S 0 |
2557 | #define PERRVFID_V(x) ((x) << PERRVFID_S) | |
2558 | #define PERRVFID_F PERRVFID_V(1U) | |
5be78ee9 | 2559 | |
0d804338 HS |
2560 | #define PL_REV_A 0x1943c |
2561 | ||
2562 | #define REV_S 0 | |
2563 | #define REV_M 0xfU | |
2564 | #define REV_V(x) ((x) << REV_S) | |
2565 | #define REV_G(x) (((x) >> REV_S) & REV_M) | |
2566 | ||
3ccc6cf7 HS |
2567 | #define T6_UNKNOWNCMD_S 3 |
2568 | #define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S) | |
2569 | #define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U) | |
2570 | ||
2571 | #define T6_LIP0_S 2 | |
2572 | #define T6_LIP0_V(x) ((x) << T6_LIP0_S) | |
2573 | #define T6_LIP0_F T6_LIP0_V(1U) | |
2574 | ||
2575 | #define T6_LIPMISS_S 1 | |
2576 | #define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S) | |
2577 | #define T6_LIPMISS_F T6_LIPMISS_V(1U) | |
2578 | ||
0d804338 HS |
2579 | #define LE_DB_INT_CAUSE_A 0x19c3c |
2580 | ||
2581 | #define REQQPARERR_S 16 | |
2582 | #define REQQPARERR_V(x) ((x) << REQQPARERR_S) | |
2583 | #define REQQPARERR_F REQQPARERR_V(1U) | |
2584 | ||
2585 | #define UNKNOWNCMD_S 15 | |
2586 | #define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S) | |
2587 | #define UNKNOWNCMD_F UNKNOWNCMD_V(1U) | |
2588 | ||
2589 | #define PARITYERR_S 6 | |
2590 | #define PARITYERR_V(x) ((x) << PARITYERR_S) | |
2591 | #define PARITYERR_F PARITYERR_V(1U) | |
2592 | ||
2593 | #define LIPMISS_S 5 | |
2594 | #define LIPMISS_V(x) ((x) << LIPMISS_S) | |
2595 | #define LIPMISS_F LIPMISS_V(1U) | |
2596 | ||
2597 | #define LIP0_S 4 | |
2598 | #define LIP0_V(x) ((x) << LIP0_S) | |
2599 | #define LIP0_F LIP0_V(1U) | |
2600 | ||
3ccc6cf7 HS |
2601 | #define TCAMINTPERR_S 13 |
2602 | #define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S) | |
2603 | #define TCAMINTPERR_F TCAMINTPERR_V(1U) | |
2604 | ||
2605 | #define SSRAMINTPERR_S 10 | |
2606 | #define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S) | |
2607 | #define SSRAMINTPERR_F SSRAMINTPERR_V(1U) | |
2608 | ||
0d804338 HS |
2609 | #define NCSI_INT_CAUSE_A 0x1a0d8 |
2610 | ||
2611 | #define CIM_DM_PRTY_ERR_S 8 | |
2612 | #define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S) | |
2613 | #define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U) | |
2614 | ||
2615 | #define MPS_DM_PRTY_ERR_S 7 | |
2616 | #define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S) | |
2617 | #define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U) | |
2618 | ||
2619 | #define TXFIFO_PRTY_ERR_S 1 | |
2620 | #define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S) | |
2621 | #define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U) | |
2622 | ||
2623 | #define RXFIFO_PRTY_ERR_S 0 | |
2624 | #define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S) | |
2625 | #define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U) | |
2626 | ||
2627 | #define XGMAC_PORT_CFG2_A 0x1018 | |
2628 | ||
2629 | #define PATEN_S 18 | |
2630 | #define PATEN_V(x) ((x) << PATEN_S) | |
2631 | #define PATEN_F PATEN_V(1U) | |
2632 | ||
2633 | #define MAGICEN_S 17 | |
2634 | #define MAGICEN_V(x) ((x) << MAGICEN_S) | |
2635 | #define MAGICEN_F MAGICEN_V(1U) | |
2636 | ||
2637 | #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 | |
2638 | #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 | |
2639 | ||
2640 | #define XGMAC_PORT_EPIO_DATA0_A 0x10c0 | |
2641 | #define XGMAC_PORT_EPIO_DATA1_A 0x10c4 | |
2642 | #define XGMAC_PORT_EPIO_DATA2_A 0x10c8 | |
2643 | #define XGMAC_PORT_EPIO_DATA3_A 0x10cc | |
2644 | #define XGMAC_PORT_EPIO_OP_A 0x10d0 | |
2645 | ||
2646 | #define EPIOWR_S 8 | |
2647 | #define EPIOWR_V(x) ((x) << EPIOWR_S) | |
2648 | #define EPIOWR_F EPIOWR_V(1U) | |
2649 | ||
2650 | #define ADDRESS_S 0 | |
2651 | #define ADDRESS_V(x) ((x) << ADDRESS_S) | |
2652 | ||
2653 | #define MAC_PORT_INT_CAUSE_A 0x8dc | |
2654 | #define XGMAC_PORT_INT_CAUSE_A 0x10dc | |
2655 | ||
2656 | #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28 | |
2657 | ||
2658 | #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30 | |
2659 | #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34 | |
2660 | ||
2661 | #define TX_MOD_QUEUE_REQ_MAP_S 0 | |
2662 | #define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S) | |
2663 | ||
2664 | #define TX_MODQ_WEIGHT3_S 24 | |
2665 | #define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S) | |
2666 | ||
2667 | #define TX_MODQ_WEIGHT2_S 16 | |
2668 | #define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S) | |
2669 | ||
2670 | #define TX_MODQ_WEIGHT1_S 8 | |
2671 | #define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S) | |
2672 | ||
2673 | #define TX_MODQ_WEIGHT0_S 0 | |
2674 | #define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S) | |
2675 | ||
2676 | #define TP_TX_SCHED_HDR_A 0x23 | |
2677 | #define TP_TX_SCHED_FIFO_A 0x24 | |
2678 | #define TP_TX_SCHED_PCMD_A 0x25 | |
dcf7b6f5 | 2679 | |
b2decadd SR |
2680 | #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 |
2681 | #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 | |
2682 | ||
2683 | #define T5_PORT0_BASE 0x30000 | |
2684 | #define T5_PORT_STRIDE 0x4000 | |
2685 | #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) | |
2686 | #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) | |
2687 | ||
2688 | #define MC_0_BASE_ADDR 0x40000 | |
2689 | #define MC_1_BASE_ADDR 0x48000 | |
2690 | #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) | |
2691 | #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) | |
2692 | ||
89c3a86c HS |
2693 | #define MC_P_BIST_CMD_A 0x41400 |
2694 | #define MC_P_BIST_CMD_ADDR_A 0x41404 | |
2695 | #define MC_P_BIST_CMD_LEN_A 0x41408 | |
2696 | #define MC_P_BIST_DATA_PATTERN_A 0x4140c | |
2697 | #define MC_P_BIST_STATUS_RDATA_A 0x41488 | |
2698 | ||
2699 | #define EDC_T50_BASE_ADDR 0x50000 | |
2700 | ||
2701 | #define EDC_H_BIST_CMD_A 0x50004 | |
2702 | #define EDC_H_BIST_CMD_ADDR_A 0x50008 | |
2703 | #define EDC_H_BIST_CMD_LEN_A 0x5000c | |
2704 | #define EDC_H_BIST_DATA_PATTERN_A 0x50010 | |
2705 | #define EDC_H_BIST_STATUS_RDATA_A 0x50028 | |
2706 | ||
2707 | #define EDC_T51_BASE_ADDR 0x50800 | |
2708 | ||
b2decadd SR |
2709 | #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) |
2710 | #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) | |
2711 | ||
0d804338 HS |
2712 | #define PL_VF_REV_A 0x4 |
2713 | #define PL_VF_WHOAMI_A 0x0 | |
2714 | #define PL_VF_REVISION_A 0x8 | |
dcf7b6f5 | 2715 | |
f1ff24aa HS |
2716 | /* registers for module CIM */ |
2717 | #define CIM_HOST_ACC_CTRL_A 0x7b50 | |
2718 | #define CIM_HOST_ACC_DATA_A 0x7b54 | |
2719 | #define UP_UP_DBG_LA_CFG_A 0x140 | |
2720 | #define UP_UP_DBG_LA_DATA_A 0x144 | |
2721 | ||
2722 | #define HOSTBUSY_S 17 | |
2723 | #define HOSTBUSY_V(x) ((x) << HOSTBUSY_S) | |
2724 | #define HOSTBUSY_F HOSTBUSY_V(1U) | |
2725 | ||
2726 | #define HOSTWRITE_S 16 | |
2727 | #define HOSTWRITE_V(x) ((x) << HOSTWRITE_S) | |
2728 | #define HOSTWRITE_F HOSTWRITE_V(1U) | |
2729 | ||
e5f0e43b HS |
2730 | #define CIM_IBQ_DBG_CFG_A 0x7b60 |
2731 | ||
2732 | #define IBQDBGADDR_S 16 | |
2733 | #define IBQDBGADDR_M 0xfffU | |
2734 | #define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S) | |
2735 | #define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M) | |
2736 | ||
2737 | #define IBQDBGBUSY_S 1 | |
2738 | #define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S) | |
2739 | #define IBQDBGBUSY_F IBQDBGBUSY_V(1U) | |
2740 | ||
2741 | #define IBQDBGEN_S 0 | |
2742 | #define IBQDBGEN_V(x) ((x) << IBQDBGEN_S) | |
2743 | #define IBQDBGEN_F IBQDBGEN_V(1U) | |
2744 | ||
c778af7d HS |
2745 | #define CIM_OBQ_DBG_CFG_A 0x7b64 |
2746 | ||
2747 | #define OBQDBGADDR_S 16 | |
2748 | #define OBQDBGADDR_M 0xfffU | |
2749 | #define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S) | |
2750 | #define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M) | |
2751 | ||
2752 | #define OBQDBGBUSY_S 1 | |
2753 | #define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S) | |
2754 | #define OBQDBGBUSY_F OBQDBGBUSY_V(1U) | |
2755 | ||
2756 | #define OBQDBGEN_S 0 | |
2757 | #define OBQDBGEN_V(x) ((x) << OBQDBGEN_S) | |
2758 | #define OBQDBGEN_F OBQDBGEN_V(1U) | |
2759 | ||
e5f0e43b | 2760 | #define CIM_IBQ_DBG_DATA_A 0x7b68 |
c778af7d | 2761 | #define CIM_OBQ_DBG_DATA_A 0x7b6c |
e5f0e43b | 2762 | |
f1ff24aa HS |
2763 | #define UPDBGLARDEN_S 1 |
2764 | #define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S) | |
2765 | #define UPDBGLARDEN_F UPDBGLARDEN_V(1U) | |
2766 | ||
2767 | #define UPDBGLAEN_S 0 | |
2768 | #define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S) | |
2769 | #define UPDBGLAEN_F UPDBGLAEN_V(1U) | |
2770 | ||
2771 | #define UPDBGLARDPTR_S 2 | |
2772 | #define UPDBGLARDPTR_M 0xfffU | |
2773 | #define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S) | |
2774 | ||
2775 | #define UPDBGLAWRPTR_S 16 | |
2776 | #define UPDBGLAWRPTR_M 0xfffU | |
2777 | #define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M) | |
2778 | ||
2779 | #define UPDBGLACAPTPCONLY_S 30 | |
2780 | #define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S) | |
2781 | #define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U) | |
2782 | ||
74b3092c HS |
2783 | #define CIM_QUEUE_CONFIG_REF_A 0x7b48 |
2784 | #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c | |
2785 | ||
2786 | #define CIMQSIZE_S 24 | |
2787 | #define CIMQSIZE_M 0x3fU | |
2788 | #define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M) | |
2789 | ||
2790 | #define CIMQBASE_S 16 | |
2791 | #define CIMQBASE_M 0x3fU | |
2792 | #define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M) | |
2793 | ||
2794 | #define QUEFULLTHRSH_S 0 | |
2795 | #define QUEFULLTHRSH_M 0x1ffU | |
2796 | #define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M) | |
2797 | ||
2798 | #define UP_IBQ_0_RDADDR_A 0x10 | |
2799 | #define UP_IBQ_0_SHADOW_RDADDR_A 0x280 | |
2800 | #define UP_OBQ_0_REALADDR_A 0x104 | |
2801 | #define UP_OBQ_0_SHADOW_REALADDR_A 0x394 | |
2802 | ||
2803 | #define IBQRDADDR_S 0 | |
2804 | #define IBQRDADDR_M 0x1fffU | |
2805 | #define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M) | |
2806 | ||
2807 | #define IBQWRADDR_S 0 | |
2808 | #define IBQWRADDR_M 0x1fffU | |
2809 | #define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M) | |
2810 | ||
2811 | #define QUERDADDR_S 0 | |
2812 | #define QUERDADDR_M 0x7fffU | |
2813 | #define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M) | |
2814 | ||
2815 | #define QUEREMFLITS_S 0 | |
2816 | #define QUEREMFLITS_M 0x7ffU | |
2817 | #define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M) | |
2818 | ||
2819 | #define QUEEOPCNT_S 16 | |
2820 | #define QUEEOPCNT_M 0xfffU | |
2821 | #define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M) | |
2822 | ||
2823 | #define QUESOPCNT_S 0 | |
2824 | #define QUESOPCNT_M 0xfffU | |
2825 | #define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M) | |
2826 | ||
2827 | #define OBQSELECT_S 4 | |
2828 | #define OBQSELECT_V(x) ((x) << OBQSELECT_S) | |
2829 | #define OBQSELECT_F OBQSELECT_V(1U) | |
2830 | ||
2831 | #define IBQSELECT_S 3 | |
2832 | #define IBQSELECT_V(x) ((x) << IBQSELECT_S) | |
2833 | #define IBQSELECT_F IBQSELECT_V(1U) | |
2834 | ||
2835 | #define QUENUMSELECT_S 0 | |
2836 | #define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S) | |
2837 | ||
bbc02c7e | 2838 | #endif /* __T4_REGS_H */ |