projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
enic: fix work done in tx napi_poll
[deliverable/linux.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
b6e97c13
GV		 42#ifdef CONFIG_RFS_ACCEL
43#include <linux/cpu_rmap.h>
44#endif
14747cd9
GV		 45#ifdef CONFIG_NET_RX_BUSY_POLL
46#include <net/busy_poll.h>
47#endif
01f2e4ea
SF		 48
49#include "cq_enet_desc.h"
50#include "vnic_dev.h"
51#include "vnic_intr.h"
52#include "vnic_stats.h"
f8bd9091 53#include "vnic_vic.h"
01f2e4ea
SF		 54#include "enic_res.h"
55#include "enic.h"
51987461 56#include "enic_dev.h"
b3abfbd2 57#include "enic_pp.h"
a145df23 58#include "enic_clsf.h"
01f2e4ea
SF		 59
60#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 61#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
62#define MAX_TSO (1 << 16)
63#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
64
65#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 66#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 68
a03bb56e
GV		 69#define RX_COPYBREAK_DEFAULT 256
70
01f2e4ea 71/* Supported devices */
9baa3c34 72static const struct pci_device_id enic_id_table[] = {
ea0d7d91 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 76 { 0, } /* end of table */
77};
78
79MODULE_DESCRIPTION(DRV_DESCRIPTION);
80MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
81MODULE_LICENSE("GPL");
82MODULE_VERSION(DRV_VERSION);
83MODULE_DEVICE_TABLE(pci, enic_id_table);
84
7c2ce6e6
SS		 85#define ENIC_LARGE_PKT_THRESHOLD 1000
86#define ENIC_MAX_COALESCE_TIMERS 10
87/* Interrupt moderation table, which will be used to decide the
88 * coalescing timer values
89 * {rx_rate in Mbps, mapping percentage of the range}
90 */
91struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
92 {4000, 0},
93 {4400, 10},
94 {5060, 20},
95 {5230, 30},
96 {5540, 40},
97 {5820, 50},
98 {6120, 60},
99 {6435, 70},
100 {6745, 80},
101 {7000, 90},
102 {0xFFFFFFFF, 100}
103};
104
105/* This table helps the driver to pick different ranges for rx coalescing
106 * timer depending on the link speed.
107 */
108struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
109 {0, 0}, /* 0 - 4 Gbps */
110 {0, 3}, /* 4 - 10 Gbps */
111 {3, 6}, /* 10 - 40 Gbps */
112};
113
3f192795 114int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 115{
116 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
117}
118
8749b427
RP		 119int enic_sriov_enabled(struct enic *enic)
120{
121 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
122}
123
3a4adef5
RP		 124static int enic_is_sriov_vf(struct enic *enic)
125{
126 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
127}
128
889d13f5
RP		 129int enic_is_valid_vf(struct enic *enic, int vf)
130{
131#ifdef CONFIG_PCI_IOV
132 return vf >= 0 && vf < enic->num_vfs;
133#else
134 return 0;
135#endif
136}
137
01f2e4ea
SF		 138static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
139{
140 struct enic *enic = vnic_dev_priv(wq->vdev);
141
142 if (buf->sop)
143 pci_unmap_single(enic->pdev, buf->dma_addr,
144 buf->len, PCI_DMA_TODEVICE);
145 else
146 pci_unmap_page(enic->pdev, buf->dma_addr,
147 buf->len, PCI_DMA_TODEVICE);
148
149 if (buf->os_buf)
150 dev_kfree_skb_any(buf->os_buf);
151}
152
153static void enic_wq_free_buf(struct vnic_wq *wq,
154 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
155{
156 enic_free_wq_buf(wq, buf);
157}
158
159static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
160 u8 type, u16 q_number, u16 completed_index, void *opaque)
161{
162 struct enic *enic = vnic_dev_priv(vdev);
163
164 spin_lock(&enic->wq_lock[q_number]);
165
166 vnic_wq_service(&enic->wq[q_number], cq_desc,
167 completed_index, enic_wq_free_buf,
168 opaque);
169
822473b6 170 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 171 vnic_wq_desc_avail(&enic->wq[q_number]) >=
172 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 173 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 174
175 spin_unlock(&enic->wq_lock[q_number]);
176
177 return 0;
178}
179
180static void enic_log_q_error(struct enic *enic)
181{
182 unsigned int i;
183 u32 error_status;
184
185 for (i = 0; i < enic->wq_count; i++) {
186 error_status = vnic_wq_error_status(&enic->wq[i]);
187 if (error_status)
a7a79deb
VK		 188 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
189 i, error_status);
01f2e4ea
SF		 190 }
191
192 for (i = 0; i < enic->rq_count; i++) {
193 error_status = vnic_rq_error_status(&enic->rq[i]);
194 if (error_status)
a7a79deb
VK		 195 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
196 i, error_status);
01f2e4ea
SF		 197 }
198}
199
383ab92f 200static void enic_msglvl_check(struct enic *enic)
01f2e4ea 201{
383ab92f 202 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 203
383ab92f 204 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 205 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
206 enic->msg_enable, msg_enable);
383ab92f 207 enic->msg_enable = msg_enable;
01f2e4ea
SF		 208 }
209}
210
211static void enic_mtu_check(struct enic *enic)
212{
213 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 214 struct net_device *netdev = enic->netdev;
01f2e4ea 215
491598a4 216 if (mtu && mtu != enic->port_mtu) {
7c844599 217 enic->port_mtu = mtu;
7335903c 218 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 219 mtu = max_t(int, ENIC_MIN_MTU,
220 min_t(int, ENIC_MAX_MTU, mtu));
221 if (mtu != netdev->mtu)
222 schedule_work(&enic->change_mtu_work);
223 } else {
224 if (mtu < netdev->mtu)
225 netdev_warn(netdev,
226 "interface MTU (%d) set higher "
227 "than switch port MTU (%d)\n",
228 netdev->mtu, mtu);
229 }
01f2e4ea
SF		 230 }
231}
232
383ab92f 233static void enic_link_check(struct enic *enic)
01f2e4ea 234{
383ab92f
VK		 235 int link_status = vnic_dev_link_status(enic->vdev);
236 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 237
383ab92f 238 if (link_status && !carrier_ok) {
a7a79deb 239 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 240 netif_carrier_on(enic->netdev);
241 } else if (!link_status && carrier_ok) {
a7a79deb 242 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 243 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 244 }
245}
246
247static void enic_notify_check(struct enic *enic)
248{
249 enic_msglvl_check(enic);
250 enic_mtu_check(enic);
251 enic_link_check(enic);
252}
253
254#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
255
256static irqreturn_t enic_isr_legacy(int irq, void *data)
257{
258 struct net_device *netdev = data;
259 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 260 unsigned int io_intr = enic_legacy_io_intr();
261 unsigned int err_intr = enic_legacy_err_intr();
262 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 263 u32 pba;
264
717258ba 265 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 266
267 pba = vnic_intr_legacy_pba(enic->legacy_pba);
268 if (!pba) {
717258ba 269 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 270 return IRQ_NONE; /* not our interrupt */
271 }
272
717258ba
VK		 273 if (ENIC_TEST_INTR(pba, notify_intr)) {
274 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
01f2e4ea 275 enic_notify_check(enic);
ed8af6b2 276 }
01f2e4ea 277
717258ba
VK		 278 if (ENIC_TEST_INTR(pba, err_intr)) {
279 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 280 enic_log_q_error(enic);
281 /* schedule recovery from WQ/RQ error */
282 schedule_work(&enic->reset);
283 return IRQ_HANDLED;
284 }
285
717258ba
VK		 286 if (ENIC_TEST_INTR(pba, io_intr)) {
287 if (napi_schedule_prep(&enic->napi[0]))
288 __napi_schedule(&enic->napi[0]);
01f2e4ea 289 } else {
717258ba 290 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 291 }
292
293 return IRQ_HANDLED;
294}
295
296static irqreturn_t enic_isr_msi(int irq, void *data)
297{
298 struct enic *enic = data;
299
300 /* With MSI, there is no sharing of interrupts, so this is
301 * our interrupt and there is no need to ack it. The device
302 * is not providing per-vector masking, so the OS will not
303 * write to PCI config space to mask/unmask the interrupt.
304 * We're using mask_on_assertion for MSI, so the device
305 * automatically masks the interrupt when the interrupt is
306 * generated. Later, when exiting polling, the interrupt
307 * will be unmasked (see enic_poll).
308 *
309 * Also, the device uses the same PCIe Traffic Class (TC)
310 * for Memory Write data and MSI, so there are no ordering
311 * issues; the MSI will always arrive at the Root Complex
312 * _after_ corresponding Memory Writes (i.e. descriptor
313 * writes).
314 */
315
717258ba 316 napi_schedule(&enic->napi[0]);
01f2e4ea
SF		 317
318 return IRQ_HANDLED;
319}
320
4cfe8785 321static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 322{
717258ba 323 struct napi_struct *napi = data;
01f2e4ea 324
717258ba 325 napi_schedule(napi);
01f2e4ea
SF		 326
327 return IRQ_HANDLED;
328}
329
01f2e4ea
SF		 330static irqreturn_t enic_isr_msix_err(int irq, void *data)
331{
332 struct enic *enic = data;
717258ba 333 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 334
717258ba 335 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 336
01f2e4ea
SF		 337 enic_log_q_error(enic);
338
339 /* schedule recovery from WQ/RQ error */
340 schedule_work(&enic->reset);
341
342 return IRQ_HANDLED;
343}
344
345static irqreturn_t enic_isr_msix_notify(int irq, void *data)
346{
347 struct enic *enic = data;
717258ba 348 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea 349
717258ba 350 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea 351 enic_notify_check(enic);
01f2e4ea
SF		 352
353 return IRQ_HANDLED;
354}
355
356static inline void enic_queue_wq_skb_cont(struct enic *enic,
357 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 358 unsigned int len_left, int loopback)
01f2e4ea 359{
9e903e08 360 const skb_frag_t *frag;
01f2e4ea
SF		 361
362 /* Queue additional data fragments */
363 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 364 len_left -= skb_frag_size(frag);
01f2e4ea 365 enic_queue_wq_desc_cont(wq, skb,
4bf5adbf 366 skb_frag_dma_map(&enic->pdev->dev,
9e903e08 367 frag, 0, skb_frag_size(frag),
5d6bcdfe 368 DMA_TO_DEVICE),
9e903e08 369 skb_frag_size(frag),
1825aca6
VK		 370 (len_left == 0), /* EOP? */
371 loopback);
01f2e4ea
SF		 372 }
373}
374
375static inline void enic_queue_wq_skb_vlan(struct enic *enic,
376 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 377 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 378{
379 unsigned int head_len = skb_headlen(skb);
380 unsigned int len_left = skb->len - head_len;
381 int eop = (len_left == 0);
382
ea0d7d91
SF		 383 /* Queue the main skb fragment. The fragments are no larger
384 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
385 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
386 * per fragment is queued.
387 */
01f2e4ea
SF		 388 enic_queue_wq_desc(wq, skb,
389 pci_map_single(enic->pdev, skb->data,
390 head_len, PCI_DMA_TODEVICE),
391 head_len,
392 vlan_tag_insert, vlan_tag,
1825aca6 393 eop, loopback);
01f2e4ea
SF		 394
395 if (!eop)
1825aca6 396 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 397}
398
399static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
400 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 401 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 402{
403 unsigned int head_len = skb_headlen(skb);
404 unsigned int len_left = skb->len - head_len;
0d0b1672 405 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 406 unsigned int csum_offset = hdr_len + skb->csum_offset;
407 int eop = (len_left == 0);
408
ea0d7d91
SF		 409 /* Queue the main skb fragment. The fragments are no larger
410 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
411 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
412 * per fragment is queued.
413 */
01f2e4ea
SF		 414 enic_queue_wq_desc_csum_l4(wq, skb,
415 pci_map_single(enic->pdev, skb->data,
416 head_len, PCI_DMA_TODEVICE),
417 head_len,
418 csum_offset,
419 hdr_len,
420 vlan_tag_insert, vlan_tag,
1825aca6 421 eop, loopback);
01f2e4ea
SF		 422
423 if (!eop)
1825aca6 424 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 425}
426
427static inline void enic_queue_wq_skb_tso(struct enic *enic,
428 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
1825aca6 429 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea 430{
ea0d7d91
SF		 431 unsigned int frag_len_left = skb_headlen(skb);
432 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF		 433 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
434 int eop = (len_left == 0);
ea0d7d91
SF		 435 unsigned int len;
436 dma_addr_t dma_addr;
437 unsigned int offset = 0;
438 skb_frag_t *frag;
01f2e4ea
SF		 439
440 /* Preload TCP csum field with IP pseudo hdr calculated
441 * with IP length set to zero. HW will later add in length
442 * to each TCP segment resulting from the TSO.
443 */
444
09640e63 445 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 446 ip_hdr(skb)->check = 0;
447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
448 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 449 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 450 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
451 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
452 }
453
ea0d7d91
SF		 454 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
455 * for the main skb fragment
456 */
457 while (frag_len_left) {
458 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
459 dma_addr = pci_map_single(enic->pdev, skb->data + offset,
460 len, PCI_DMA_TODEVICE);
461 enic_queue_wq_desc_tso(wq, skb,
462 dma_addr,
463 len,
464 mss, hdr_len,
465 vlan_tag_insert, vlan_tag,
1825aca6 466 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 467 frag_len_left -= len;
468 offset += len;
469 }
01f2e4ea 470
ea0d7d91
SF		 471 if (eop)
472 return;
473
474 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
475 * for additional data fragments
476 */
477 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 478 len_left -= skb_frag_size(frag);
479 frag_len_left = skb_frag_size(frag);
4bf5adbf 480 offset = 0;
ea0d7d91
SF		 481
482 while (frag_len_left) {
483 len = min(frag_len_left,
484 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 485 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
486 offset, len,
5d6bcdfe 487 DMA_TO_DEVICE);
ea0d7d91
SF		 488 enic_queue_wq_desc_cont(wq, skb,
489 dma_addr,
490 len,
491 (len_left == 0) &&
1825aca6
VK		 492 (len == frag_len_left), /* EOP? */
493 loopback);
ea0d7d91
SF		 494 frag_len_left -= len;
495 offset += len;
496 }
497 }
01f2e4ea
SF		 498}
499
500static inline void enic_queue_wq_skb(struct enic *enic,
501 struct vnic_wq *wq, struct sk_buff *skb)
502{
503 unsigned int mss = skb_shinfo(skb)->gso_size;
504 unsigned int vlan_tag = 0;
505 int vlan_tag_insert = 0;
1825aca6 506 int loopback = 0;
01f2e4ea 507
eab6d18d 508 if (vlan_tx_tag_present(skb)) {
01f2e4ea
SF		 509 /* VLAN tag from trunking driver */
510 vlan_tag_insert = 1;
511 vlan_tag = vlan_tx_tag_get(skb);
1825aca6
VK		 512 } else if (enic->loop_enable) {
513 vlan_tag = enic->loop_tag;
514 loopback = 1;
01f2e4ea
SF		 515 }
516
517 if (mss)
518 enic_queue_wq_skb_tso(enic, wq, skb, mss,
1825aca6 519 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 520 else if (skb->ip_summed == CHECKSUM_PARTIAL)
521 enic_queue_wq_skb_csum_l4(enic, wq, skb,
1825aca6 522 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 523 else
524 enic_queue_wq_skb_vlan(enic, wq, skb,
1825aca6 525 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 526}
527
ed8af6b2 528/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 529static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 530 struct net_device *netdev)
01f2e4ea
SF		 531{
532 struct enic *enic = netdev_priv(netdev);
822473b6 533 struct vnic_wq *wq;
01f2e4ea 534 unsigned long flags;
822473b6 535 unsigned int txq_map;
01f2e4ea
SF		 536
537 if (skb->len <= 0) {
98d8a65d 538 dev_kfree_skb_any(skb);
01f2e4ea
SF		 539 return NETDEV_TX_OK;
540 }
541
822473b6 542 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
543 wq = &enic->wq[txq_map];
544
01f2e4ea
SF		 545 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
546 * which is very likely. In the off chance it's going to take
547 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
548 */
549
550 if (skb_shinfo(skb)->gso_size == 0 &&
551 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
552 skb_linearize(skb)) {
98d8a65d 553 dev_kfree_skb_any(skb);
01f2e4ea
SF		 554 return NETDEV_TX_OK;
555 }
556
822473b6 557 spin_lock_irqsave(&enic->wq_lock[txq_map], flags);
01f2e4ea 558
ea0d7d91
SF		 559 if (vnic_wq_desc_avail(wq) <
560 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
822473b6 561 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 562 /* This is a hard error, log it */
a7a79deb 563 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
822473b6 564 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 565 return NETDEV_TX_BUSY;
566 }
567
568 enic_queue_wq_skb(enic, wq, skb);
569
ea0d7d91 570 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
822473b6 571 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 572
822473b6 573 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 574
575 return NETDEV_TX_OK;
576}
577
578/* dev_base_lock rwlock held, nominally process context */
f20530bc 579static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
580 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 581{
582 struct enic *enic = netdev_priv(netdev);
583 struct vnic_stats *stats;
584
383ab92f 585 enic_dev_stats_dump(enic, &stats);
01f2e4ea 586
25f0a061
SF		 587 net_stats->tx_packets = stats->tx.tx_frames_ok;
588 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
589 net_stats->tx_errors = stats->tx.tx_errors;
590 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 591
25f0a061
SF		 592 net_stats->rx_packets = stats->rx.rx_frames_ok;
593 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
594 net_stats->rx_errors = stats->rx.rx_errors;
595 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 596 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 597 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 598 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 599
25f0a061 600 return net_stats;
01f2e4ea
SF		 601}
602
f009618a
AD		 603static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
604{
605 struct enic *enic = netdev_priv(netdev);
606
607 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
608 unsigned int mc_count = netdev_mc_count(netdev);
609
610 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
611 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
612
613 return -ENOSPC;
614 }
615
616 enic_dev_add_addr(enic, mc_addr);
617 enic->mc_count++;
618
619 return 0;
620}
621
622static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
623{
624 struct enic *enic = netdev_priv(netdev);
625
626 enic_dev_del_addr(enic, mc_addr);
627 enic->mc_count--;
628
629 return 0;
630}
631
632static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
633{
634 struct enic *enic = netdev_priv(netdev);
635
636 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
637 unsigned int uc_count = netdev_uc_count(netdev);
638
639 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
640 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
641
642 return -ENOSPC;
643 }
644
645 enic_dev_add_addr(enic, uc_addr);
646 enic->uc_count++;
647
648 return 0;
649}
650
651static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
652{
653 struct enic *enic = netdev_priv(netdev);
654
655 enic_dev_del_addr(enic, uc_addr);
656 enic->uc_count--;
657
658 return 0;
659}
660
b3abfbd2 661void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 662{
f009618a
AD		 663 struct net_device *netdev = enic->netdev;
664
665 __dev_uc_unsync(netdev, NULL);
666 __dev_mc_unsync(netdev, NULL);
667
01f2e4ea 668 enic->mc_count = 0;
e0afe53f 669 enic->uc_count = 0;
99ef5639 670 enic->flags = 0;
01f2e4ea
SF		 671}
672
673static int enic_set_mac_addr(struct net_device *netdev, char *addr)
674{
f8bd9091
SF		 675 struct enic *enic = netdev_priv(netdev);
676
7335903c 677 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 678 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
679 return -EADDRNOTAVAIL;
680 } else {
681 if (!is_valid_ether_addr(addr))
682 return -EADDRNOTAVAIL;
683 }
01f2e4ea
SF		 684
685 memcpy(netdev->dev_addr, addr, netdev->addr_len);
686
687 return 0;
688}
689
f8bd9091
SF		 690static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
691{
692 struct enic *enic = netdev_priv(netdev);
693 struct sockaddr *saddr = p;
694 char *addr = saddr->sa_data;
695 int err;
696
697 if (netif_running(enic->netdev)) {
698 err = enic_dev_del_station_addr(enic);
699 if (err)
700 return err;
701 }
702
703 err = enic_set_mac_addr(netdev, addr);
704 if (err)
705 return err;
706
707 if (netif_running(enic->netdev)) {
708 err = enic_dev_add_station_addr(enic);
709 if (err)
710 return err;
711 }
712
713 return err;
714}
715
716static int enic_set_mac_address(struct net_device *netdev, void *p)
717{
294dab25 718 struct sockaddr *saddr = p;
c76fd32d
VK		 719 char *addr = saddr->sa_data;
720 struct enic *enic = netdev_priv(netdev);
721 int err;
722
723 err = enic_dev_del_station_addr(enic);
724 if (err)
725 return err;
726
727 err = enic_set_mac_addr(netdev, addr);
728 if (err)
729 return err;
294dab25 730
c76fd32d 731 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 732}
733
319d7e84
RP		 734/* netif_tx_lock held, BHs disabled */
735static void enic_set_rx_mode(struct net_device *netdev)
736{
737 struct enic *enic = netdev_priv(netdev);
738 int directed = 1;
739 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
740 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
741 int promisc = (netdev->flags & IFF_PROMISC) ||
742 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
743 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
744 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
745 unsigned int flags = netdev->flags |
746 (allmulti ? IFF_ALLMULTI : 0) |
747 (promisc ? IFF_PROMISC : 0);
748
749 if (enic->flags != flags) {
750 enic->flags = flags;
751 enic_dev_packet_filter(enic, directed,
752 multicast, broadcast, promisc, allmulti);
753 }
754
755 if (!promisc) {
f009618a 756 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 757 if (!allmulti)
f009618a 758 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 759 }
760}
761
01f2e4ea
SF		 762/* netif_tx_lock held, BHs disabled */
763static void enic_tx_timeout(struct net_device *netdev)
764{
765 struct enic *enic = netdev_priv(netdev);
766 schedule_work(&enic->reset);
767}
768
0b1c00fc
RP		 769static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
770{
771 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 772 struct enic_port_profile *pp;
773 int err;
0b1c00fc 774
3f192795
RP		 775 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
776 if (err)
777 return err;
0b1c00fc 778
b8622cbd 779 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 780 if (vf == PORT_SELF_VF) {
781 memcpy(pp->vf_mac, mac, ETH_ALEN);
782 return 0;
783 } else {
784 /*
785 * For sriov vf's set the mac in hw
786 */
787 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
788 vnic_dev_set_mac_addr, mac);
789 return enic_dev_status_to_errno(err);
790 }
0b1c00fc
RP		 791 } else
792 return -EINVAL;
793}
794
f8bd9091
SF		 795static int enic_set_vf_port(struct net_device *netdev, int vf,
796 struct nlattr *port[])
797{
798 struct enic *enic = netdev_priv(netdev);
b3abfbd2 799 struct enic_port_profile prev_pp;
3f192795 800 struct enic_port_profile *pp;
b3abfbd2 801 int err = 0, restore_pp = 1;
08f382eb 802
3f192795
RP		 803 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
804 if (err)
805 return err;
08f382eb 806
b3abfbd2
RP		 807 if (!port[IFLA_PORT_REQUEST])
808 return -EOPNOTSUPP;
809
3f192795
RP		 810 memcpy(&prev_pp, pp, sizeof(*enic->pp));
811 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 812
3f192795
RP		 813 pp->set |= ENIC_SET_REQUEST;
814 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 815
816 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 817 pp->set |= ENIC_SET_NAME;
818 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 819 PORT_PROFILE_MAX);
820 }
821
822 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 823 pp->set |= ENIC_SET_INSTANCE;
824 memcpy(pp->instance_uuid,
08f382eb
SF		 825 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
826 }
827
828 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 829 pp->set |= ENIC_SET_HOST;
830 memcpy(pp->host_uuid,
08f382eb
SF		 831 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
832 }
f8bd9091 833
b4765833
RP		 834 if (vf == PORT_SELF_VF) {
835 /* Special case handling: mac came from IFLA_VF_MAC */
836 if (!is_zero_ether_addr(prev_pp.vf_mac))
837 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 838
b4765833
RP		 839 if (is_zero_ether_addr(netdev->dev_addr))
840 eth_hw_addr_random(netdev);
841 } else {
842 /* SR-IOV VF: get mac from adapter */
843 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
844 vnic_dev_get_mac_addr, pp->mac_addr);
845 if (err) {
846 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
847 memcpy(pp, &prev_pp, sizeof(*pp));
848 return enic_dev_status_to_errno(err);
849 }
850 }
f8bd9091 851
3f192795 852 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 853 if (err) {
854 if (restore_pp) {
855 /* Things are still the way they were: Implicit
856 * DISASSOCIATE failed
857 */
3f192795 858 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 859 } else {
3f192795
RP		 860 memset(pp, 0, sizeof(*pp));
861 if (vf == PORT_SELF_VF)
862 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 863 }
864 } else {
865 /* Set flag to indicate that the port assoc/disassoc
866 * request has been sent out to fw
867 */
3f192795 868 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 869
870 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795
RP		 871 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
872 memset(pp->mac_addr, 0, ETH_ALEN);
873 if (vf == PORT_SELF_VF)
874 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 875 }
876 }
29639059 877
b4765833
RP		 878 if (vf == PORT_SELF_VF)
879 memset(pp->vf_mac, 0, ETH_ALEN);
29639059 880
29639059 881 return err;
f8bd9091
SF		 882}
883
884static int enic_get_vf_port(struct net_device *netdev, int vf,
885 struct sk_buff *skb)
886{
887 struct enic *enic = netdev_priv(netdev);
f8bd9091 888 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 889 struct enic_port_profile *pp;
b3abfbd2 890 int err;
f8bd9091 891
3f192795
RP		 892 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
893 if (err)
894 return err;
895
896 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 897 return -ENODATA;
f8bd9091 898
3f192795 899 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 900 if (err)
b3abfbd2 901 return err;
f8bd9091 902
1a106de6
DM		 903 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
904 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
905 ((pp->set & ENIC_SET_NAME) &&
906 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
907 ((pp->set & ENIC_SET_INSTANCE) &&
908 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
909 pp->instance_uuid)) ||
910 ((pp->set & ENIC_SET_HOST) &&
911 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
912 goto nla_put_failure;
f8bd9091
SF		 913 return 0;
914
915nla_put_failure:
916 return -EMSGSIZE;
917}
918
01f2e4ea
SF		 919static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
920{
921 struct enic *enic = vnic_dev_priv(rq->vdev);
922
923 if (!buf->os_buf)
924 return;
925
926 pci_unmap_single(enic->pdev, buf->dma_addr,
927 buf->len, PCI_DMA_FROMDEVICE);
928 dev_kfree_skb_any(buf->os_buf);
a03bb56e 929 buf->os_buf = NULL;
01f2e4ea
SF		 930}
931
01f2e4ea
SF		 932static int enic_rq_alloc_buf(struct vnic_rq *rq)
933{
934 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 935 struct net_device *netdev = enic->netdev;
01f2e4ea 936 struct sk_buff *skb;
1825aca6 937 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 938 unsigned int os_buf_index = 0;
939 dma_addr_t dma_addr;
a03bb56e
GV		 940 struct vnic_rq_buf *buf = rq->to_use;
941
942 if (buf->os_buf) {
f6b7734b
GV		 943 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
944 buf->len);
01f2e4ea 945
a03bb56e
GV		 946 return 0;
947 }
89d71a66 948 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 949 if (!skb)
950 return -ENOMEM;
951
952 dma_addr = pci_map_single(enic->pdev, skb->data,
953 len, PCI_DMA_FROMDEVICE);
954
955 enic_queue_rq_desc(rq, skb, os_buf_index,
956 dma_addr, len);
957
958 return 0;
959}
960
7c2ce6e6
SS		 961static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
962 u32 pkt_len)
963{
964 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
965 pkt_size->large_pkt_bytes_cnt += pkt_len;
966 else
967 pkt_size->small_pkt_bytes_cnt += pkt_len;
968}
969
a03bb56e
GV		 970static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
971 struct vnic_rq_buf *buf, u16 len)
972{
973 struct enic *enic = netdev_priv(netdev);
974 struct sk_buff *new_skb;
975
976 if (len > enic->rx_copybreak)
977 return false;
978 new_skb = netdev_alloc_skb_ip_align(netdev, len);
979 if (!new_skb)
980 return false;
981 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
982 DMA_FROM_DEVICE);
983 memcpy(new_skb->data, (*skb)->data, len);
984 *skb = new_skb;
985
986 return true;
987}
988
01f2e4ea
SF		 989static void enic_rq_indicate_buf(struct vnic_rq *rq,
990 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
991 int skipped, void *opaque)
992{
993 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 994 struct net_device *netdev = enic->netdev;
01f2e4ea 995 struct sk_buff *skb;
7c2ce6e6 996 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 997
998 u8 type, color, eop, sop, ingress_port, vlan_stripped;
999 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1000 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1001 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1002 u8 packet_error;
f8cac14a 1003 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF		 1004 u32 rss_hash;
1005
1006 if (skipped)
1007 return;
1008
1009 skb = buf->os_buf;
01f2e4ea
SF		 1010
1011 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1012 &type, &color, &q_number, &completed_index,
1013 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1014 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1015 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1016 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1017 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1018 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1019 &fcs_ok);
1020
1021 if (packet_error) {
1022
350991e1
SF		 1023 if (!fcs_ok) {
1024 if (bytes_written > 0)
1025 enic->rq_bad_fcs++;
1026 else if (bytes_written == 0)
1027 enic->rq_truncated_pkts++;
1028 }
01f2e4ea 1029
44aa91ab
GV		 1030 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1031 PCI_DMA_FROMDEVICE);
01f2e4ea 1032 dev_kfree_skb_any(skb);
44aa91ab 1033 buf->os_buf = NULL;
01f2e4ea
SF		 1034
1035 return;
1036 }
1037
1038 if (eop && bytes_written > 0) {
1039
1040 /* Good receive
1041 */
1042
a03bb56e
GV		 1043 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1044 buf->os_buf = NULL;
1045 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1046 PCI_DMA_FROMDEVICE);
1047 }
1048 prefetch(skb->data - NET_IP_ALIGN);
1049
01f2e4ea 1050 skb_put(skb, bytes_written);
86ca9db7 1051 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1052 skb_record_rx_queue(skb, q_number);
1053 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH		 1054 skb_set_hash(skb, rss_hash,
1055 (rss_type &
1056 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1057 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1058 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1059 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1060 }
01f2e4ea 1061
5ec8f9b8 1062 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
01f2e4ea
SF		 1063 skb->csum = htons(checksum);
1064 skb->ip_summed = CHECKSUM_COMPLETE;
1065 }
1066
6ede746b 1067 if (vlan_stripped)
86a9bad3 1068 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1069
14747cd9
GV		 1070 skb_mark_napi_id(skb, &enic->napi[rq->index]);
1071 if (enic_poll_busy_polling(rq) ||
1072 !(netdev->features & NETIF_F_GRO))
6ede746b 1073 netif_receive_skb(skb);
14747cd9
GV		 1074 else
1075 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1076 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1077 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1078 bytes_written);
01f2e4ea
SF		 1079 } else {
1080
1081 /* Buffer overflow
1082 */
1083
44aa91ab
GV		 1084 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1085 PCI_DMA_FROMDEVICE);
01f2e4ea 1086 dev_kfree_skb_any(skb);
44aa91ab 1087 buf->os_buf = NULL;
01f2e4ea
SF		 1088 }
1089}
1090
1091static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1092 u8 type, u16 q_number, u16 completed_index, void *opaque)
1093{
1094 struct enic *enic = vnic_dev_priv(vdev);
1095
1096 vnic_rq_service(&enic->rq[q_number], cq_desc,
1097 completed_index, VNIC_RQ_RETURN_DESC,
1098 enic_rq_indicate_buf, opaque);
1099
1100 return 0;
1101}
1102
01f2e4ea
SF		 1103static int enic_poll(struct napi_struct *napi, int budget)
1104{
717258ba
VK		 1105 struct net_device *netdev = napi->dev;
1106 struct enic *enic = netdev_priv(netdev);
1107 unsigned int cq_rq = enic_cq_rq(enic, 0);
1108 unsigned int cq_wq = enic_cq_wq(enic, 0);
1109 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF		 1110 unsigned int rq_work_to_do = budget;
1111 unsigned int wq_work_to_do = -1; /* no limit */
4c502549 1112 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1113 int err;
01f2e4ea 1114
14747cd9
GV		 1115 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1116 enic_wq_service, NULL);
1117
1118 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) {
1119 if (wq_work_done > 0)
1120 vnic_intr_return_credits(&enic->intr[intr],
1121 wq_work_done,
1122 0 /* dont unmask intr */,
1123 0 /* dont reset intr timer */);
1124 return rq_work_done;
1125 }
01f2e4ea 1126
4c502549
EB		 1127 if (budget > 0)
1128 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1129 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1130
01f2e4ea
SF		 1131 /* Accumulate intr event credits for this polling
1132 * cycle. An intr event is the completion of a
1133 * a WQ or RQ packet.
1134 */
1135
1136 work_done = rq_work_done + wq_work_done;
1137
1138 if (work_done > 0)
717258ba 1139 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1140 work_done,
1141 0 /* don't unmask intr */,
1142 0 /* don't reset intr timer */);
1143
0eb26022 1144 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1145
2d6ddced
SF		 1146 /* Buffer allocation failed. Stay in polling
1147 * mode so we can try to fill the ring again.
1148 */
01f2e4ea 1149
2d6ddced
SF		 1150 if (err)
1151 rq_work_done = rq_work_to_do;
01f2e4ea 1152
2d6ddced 1153 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1154
2d6ddced 1155 /* Some work done, but not enough to stay in polling,
88132f55 1156 * exit polling
01f2e4ea
SF		 1157 */
1158
288379f0 1159 napi_complete(napi);
717258ba 1160 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1161 }
14747cd9 1162 enic_poll_unlock_napi(&enic->rq[cq_rq]);
01f2e4ea
SF		 1163
1164 return rq_work_done;
1165}
1166
7c2ce6e6
SS		 1167static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1168{
1169 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1170 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1171 u32 timer = cq->tobe_rx_coal_timeval;
1172
1173 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1174 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1175 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1176 }
1177}
1178
1179static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1180{
1181 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1182 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1183 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1184 int index;
1185 u32 timer;
1186 u32 range_start;
1187 u32 traffic;
1188 u64 delta;
1189 ktime_t now = ktime_get();
1190
1191 delta = ktime_us_delta(now, cq->prev_ts);
1192 if (delta < ENIC_AIC_TS_BREAK)
1193 return;
1194 cq->prev_ts = now;
1195
1196 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1197 pkt_size_counter->small_pkt_bytes_cnt;
1198 /* The table takes Mbps
1199 * traffic *= 8 => bits
1200 * traffic *= (10^6 / delta) => bps
1201 * traffic /= 10^6 => Mbps
1202 *
1203 * Combining, traffic *= (8 / delta)
1204 */
1205
1206 traffic <<= 3;
958c492c 1207 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
7c2ce6e6
SS		 1208
1209 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1210 if (traffic < mod_table[index].rx_rate)
1211 break;
1212 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1213 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1214 rx_coal->small_pkt_range_start :
1215 rx_coal->large_pkt_range_start;
1216 timer = range_start + ((rx_coal->range_end - range_start) *
1217 mod_table[index].range_percent / 100);
1218 /* Damping */
1219 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1220
1221 pkt_size_counter->large_pkt_bytes_cnt = 0;
1222 pkt_size_counter->small_pkt_bytes_cnt = 0;
1223}
1224
b6e97c13
GV		 1225#ifdef CONFIG_RFS_ACCEL
1226static void enic_free_rx_cpu_rmap(struct enic *enic)
1227{
1228 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1229 enic->netdev->rx_cpu_rmap = NULL;
1230}
1231
1232static void enic_set_rx_cpu_rmap(struct enic *enic)
1233{
1234 int i, res;
1235
1236 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1237 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1238 if (unlikely(!enic->netdev->rx_cpu_rmap))
1239 return;
1240 for (i = 0; i < enic->rq_count; i++) {
1241 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1242 enic->msix_entry[i].vector);
1243 if (unlikely(res)) {
1244 enic_free_rx_cpu_rmap(enic);
1245 return;
1246 }
1247 }
1248 }
1249}
1250
1251#else
1252
1253static void enic_free_rx_cpu_rmap(struct enic *enic)
1254{
1255}
1256
1257static void enic_set_rx_cpu_rmap(struct enic *enic)
1258{
1259}
1260
1261#endif /* CONFIG_RFS_ACCEL */
1262
14747cd9
GV		 1263#ifdef CONFIG_NET_RX_BUSY_POLL
1264int enic_busy_poll(struct napi_struct *napi)
1265{
1266 struct net_device *netdev = napi->dev;
1267 struct enic *enic = netdev_priv(netdev);
1268 unsigned int rq = (napi - &enic->napi[0]);
1269 unsigned int cq = enic_cq_rq(enic, rq);
1270 unsigned int intr = enic_msix_rq_intr(enic, rq);
1271 unsigned int work_to_do = -1; /* clean all pkts possible */
1272 unsigned int work_done;
1273
1274 if (!enic_poll_lock_poll(&enic->rq[rq]))
1275 return LL_FLUSH_BUSY;
1276 work_done = vnic_cq_service(&enic->cq[cq], work_to_do,
1277 enic_rq_service, NULL);
1278
1279 if (work_done > 0)
1280 vnic_intr_return_credits(&enic->intr[intr],
1281 work_done, 0, 0);
1282 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
1283 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1284 enic_calc_int_moderation(enic, &enic->rq[rq]);
1285 enic_poll_unlock_poll(&enic->rq[rq]);
1286
1287 return work_done;
1288}
1289#endif /* CONFIG_NET_RX_BUSY_POLL */
1290
4cfe8785
GV		 1291static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1292{
1293 struct net_device *netdev = napi->dev;
1294 struct enic *enic = netdev_priv(netdev);
1295 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1296 struct vnic_wq *wq = &enic->wq[wq_index];
1297 unsigned int cq;
1298 unsigned int intr;
1299 unsigned int wq_work_to_do = -1; /* clean all desc possible */
1300 unsigned int wq_work_done;
1301 unsigned int wq_irq;
1302
1303 wq_irq = wq->index;
1304 cq = enic_cq_wq(enic, wq_irq);
1305 intr = enic_msix_wq_intr(enic, wq_irq);
1306 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1307 enic_wq_service, NULL);
1308
1309 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1310 0 /* don't unmask intr */,
1311 1 /* reset intr timer */);
1312 if (!wq_work_done) {
1313 napi_complete(napi);
1314 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1315 return 0;
4cfe8785
GV		 1316 }
1317
f41281d0 1318 return budget;
4cfe8785
GV		 1319}
1320
1321static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1322{
717258ba
VK		 1323 struct net_device *netdev = napi->dev;
1324 struct enic *enic = netdev_priv(netdev);
1325 unsigned int rq = (napi - &enic->napi[0]);
1326 unsigned int cq = enic_cq_rq(enic, rq);
1327 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1328 unsigned int work_to_do = budget;
4c502549 1329 unsigned int work_done = 0;
2d6ddced 1330 int err;
01f2e4ea 1331
14747cd9
GV		 1332 if (!enic_poll_lock_napi(&enic->rq[rq]))
1333 return work_done;
01f2e4ea
SF		 1334 /* Service RQ
1335 */
1336
4c502549
EB		 1337 if (budget > 0)
1338 work_done = vnic_cq_service(&enic->cq[cq],
1339 work_to_do, enic_rq_service, NULL);
01f2e4ea 1340
2d6ddced
SF		 1341 /* Return intr event credits for this polling
1342 * cycle. An intr event is the completion of a
1343 * RQ packet.
1344 */
01f2e4ea 1345
2d6ddced 1346 if (work_done > 0)
717258ba 1347 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1348 work_done,
1349 0 /* don't unmask intr */,
1350 0 /* don't reset intr timer */);
01f2e4ea 1351
0eb26022 1352 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1353
1354 /* Buffer allocation failed. Stay in polling mode
1355 * so we can try to fill the ring again.
1356 */
1357
1358 if (err)
1359 work_done = work_to_do;
7c2ce6e6
SS		 1360 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1361 /* Call the function which refreshes
1362 * the intr coalescing timer value based on
1363 * the traffic. This is supported only in
1364 * the case of MSI-x mode
1365 */
1366 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced
SF		 1367
1368 if (work_done < work_to_do) {
1369
1370 /* Some work done, but not enough to stay in polling,
88132f55 1371 * exit polling
01f2e4ea
SF		 1372 */
1373
288379f0 1374 napi_complete(napi);
7c2ce6e6
SS		 1375 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1376 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1377 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1378 }
14747cd9 1379 enic_poll_unlock_napi(&enic->rq[rq]);
01f2e4ea
SF		 1380
1381 return work_done;
1382}
1383
1384static void enic_notify_timer(unsigned long data)
1385{
1386 struct enic *enic = (struct enic *)data;
1387
1388 enic_notify_check(enic);
1389
25f0a061
SF		 1390 mod_timer(&enic->notify_timer,
1391 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1392}
1393
1394static void enic_free_intr(struct enic *enic)
1395{
1396 struct net_device *netdev = enic->netdev;
1397 unsigned int i;
1398
b6e97c13 1399 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1400 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1401 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1402 free_irq(enic->pdev->irq, netdev);
1403 break;
8f4d248c
SF		 1404 case VNIC_DEV_INTR_MODE_MSI:
1405 free_irq(enic->pdev->irq, enic);
1406 break;
01f2e4ea
SF		 1407 case VNIC_DEV_INTR_MODE_MSIX:
1408 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1409 if (enic->msix[i].requested)
1410 free_irq(enic->msix_entry[i].vector,
1411 enic->msix[i].devid);
1412 break;
1413 default:
1414 break;
1415 }
1416}
1417
1418static int enic_request_intr(struct enic *enic)
1419{
1420 struct net_device *netdev = enic->netdev;
717258ba 1421 unsigned int i, intr;
01f2e4ea
SF		 1422 int err = 0;
1423
b6e97c13 1424 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1425 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1426
1427 case VNIC_DEV_INTR_MODE_INTX:
1428
1429 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1430 IRQF_SHARED, netdev->name, netdev);
1431 break;
1432
1433 case VNIC_DEV_INTR_MODE_MSI:
1434
1435 err = request_irq(enic->pdev->irq, enic_isr_msi,
1436 0, netdev->name, enic);
1437 break;
1438
1439 case VNIC_DEV_INTR_MODE_MSIX:
1440
717258ba
VK		 1441 for (i = 0; i < enic->rq_count; i++) {
1442 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1443 snprintf(enic->msix[intr].devname,
1444 sizeof(enic->msix[intr].devname),
717258ba 1445 "%.11s-rx-%d", netdev->name, i);
4cfe8785 1446 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1447 enic->msix[intr].devid = &enic->napi[i];
1448 }
01f2e4ea 1449
717258ba 1450 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1451 int wq = enic_cq_wq(enic, i);
1452
717258ba 1453 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1454 snprintf(enic->msix[intr].devname,
1455 sizeof(enic->msix[intr].devname),
717258ba 1456 "%.11s-tx-%d", netdev->name, i);
4cfe8785
GV		 1457 enic->msix[intr].isr = enic_isr_msix;
1458 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1459 }
01f2e4ea 1460
717258ba 1461 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1462 snprintf(enic->msix[intr].devname,
1463 sizeof(enic->msix[intr].devname),
01f2e4ea 1464 "%.11s-err", netdev->name);
717258ba
VK		 1465 enic->msix[intr].isr = enic_isr_msix_err;
1466 enic->msix[intr].devid = enic;
01f2e4ea 1467
717258ba 1468 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1469 snprintf(enic->msix[intr].devname,
1470 sizeof(enic->msix[intr].devname),
01f2e4ea 1471 "%.11s-notify", netdev->name);
717258ba
VK		 1472 enic->msix[intr].isr = enic_isr_msix_notify;
1473 enic->msix[intr].devid = enic;
1474
1475 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1476 enic->msix[i].requested = 0;
01f2e4ea 1477
717258ba 1478 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1479 err = request_irq(enic->msix_entry[i].vector,
1480 enic->msix[i].isr, 0,
1481 enic->msix[i].devname,
1482 enic->msix[i].devid);
1483 if (err) {
1484 enic_free_intr(enic);
1485 break;
1486 }
1487 enic->msix[i].requested = 1;
1488 }
1489
1490 break;
1491
1492 default:
1493 break;
1494 }
1495
1496 return err;
1497}
1498
b3d18d19
SF		 1499static void enic_synchronize_irqs(struct enic *enic)
1500{
1501 unsigned int i;
1502
1503 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1504 case VNIC_DEV_INTR_MODE_INTX:
1505 case VNIC_DEV_INTR_MODE_MSI:
1506 synchronize_irq(enic->pdev->irq);
1507 break;
1508 case VNIC_DEV_INTR_MODE_MSIX:
1509 for (i = 0; i < enic->intr_count; i++)
1510 synchronize_irq(enic->msix_entry[i].vector);
1511 break;
1512 default:
1513 break;
1514 }
1515}
1516
7c2ce6e6
SS		 1517static void enic_set_rx_coal_setting(struct enic *enic)
1518{
1519 unsigned int speed;
1520 int index = -1;
1521 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1522
1523 /* If intr mode is not MSIX, do not do adaptive coalescing */
1524 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
1525 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
1526 return;
1527 }
1528
1529 /* 1. Read the link speed from fw
1530 * 2. Pick the default range for the speed
1531 * 3. Update it in enic->rx_coalesce_setting
1532 */
1533 speed = vnic_dev_port_speed(enic->vdev);
1534 if (ENIC_LINK_SPEED_10G < speed)
1535 index = ENIC_LINK_40G_INDEX;
1536 else if (ENIC_LINK_SPEED_4G < speed)
1537 index = ENIC_LINK_10G_INDEX;
1538 else
1539 index = ENIC_LINK_4G_INDEX;
1540
1541 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1542 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1543 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1544
1545 /* Start with the value provided by UCSM */
1546 for (index = 0; index < enic->rq_count; index++)
1547 enic->cq[index].cur_rx_coal_timeval =
1548 enic->config.intr_timer_usec;
1549
1550 rx_coal->use_adaptive_rx_coalesce = 1;
1551}
1552
383ab92f 1553static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1554{
1555 int err;
1556
8e091340 1557 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1558 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1559 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1560 err = vnic_dev_notify_set(enic->vdev,
1561 enic_legacy_notify_intr());
01f2e4ea
SF		 1562 break;
1563 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1564 err = vnic_dev_notify_set(enic->vdev,
1565 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1566 break;
1567 default:
1568 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1569 break;
1570 }
8e091340 1571 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1572
1573 return err;
1574}
1575
1576static void enic_notify_timer_start(struct enic *enic)
1577{
1578 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1579 case VNIC_DEV_INTR_MODE_MSI:
1580 mod_timer(&enic->notify_timer, jiffies);
1581 break;
1582 default:
1583 /* Using intr for notification for INTx/MSI-X */
1584 break;
6403eab1 1585 }
01f2e4ea
SF		 1586}
1587
1588/* rtnl lock is held, process context */
1589static int enic_open(struct net_device *netdev)
1590{
1591 struct enic *enic = netdev_priv(netdev);
1592 unsigned int i;
1593 int err;
1594
4b75a442
SF		 1595 err = enic_request_intr(enic);
1596 if (err) {
a7a79deb 1597 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1598 return err;
1599 }
1600
383ab92f 1601 err = enic_dev_notify_set(enic);
4b75a442 1602 if (err) {
a7a79deb
VK		 1603 netdev_err(netdev,
1604 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1605 goto err_out_free_intr;
1606 }
1607
01f2e4ea 1608 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1609 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1610 /* Need at least one buffer on ring to get going */
1611 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1612 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1613 err = -ENOMEM;
4b75a442 1614 goto err_out_notify_unset;
01f2e4ea
SF		 1615 }
1616 }
1617
1618 for (i = 0; i < enic->wq_count; i++)
1619 vnic_wq_enable(&enic->wq[i]);
1620 for (i = 0; i < enic->rq_count; i++)
1621 vnic_rq_enable(&enic->rq[i]);
1622
7335903c 1623 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1624 enic_dev_add_station_addr(enic);
3f192795 1625
319d7e84 1626 enic_set_rx_mode(netdev);
01f2e4ea 1627
822473b6 1628 netif_tx_wake_all_queues(netdev);
717258ba 1629
14747cd9
GV		 1630 for (i = 0; i < enic->rq_count; i++) {
1631 enic_busy_poll_init_lock(&enic->rq[i]);
717258ba 1632 napi_enable(&enic->napi[i]);
14747cd9 1633 }
4cfe8785
GV		 1634 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1635 for (i = 0; i < enic->wq_count; i++)
1636 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1637 enic_dev_enable(enic);
01f2e4ea
SF		 1638
1639 for (i = 0; i < enic->intr_count; i++)
1640 vnic_intr_unmask(&enic->intr[i]);
1641
1642 enic_notify_timer_start(enic);
a145df23 1643 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1644
1645 return 0;
4b75a442
SF		 1646
1647err_out_notify_unset:
383ab92f 1648 enic_dev_notify_unset(enic);
4b75a442
SF		 1649err_out_free_intr:
1650 enic_free_intr(enic);
1651
1652 return err;
01f2e4ea
SF		 1653}
1654
1655/* rtnl lock is held, process context */
1656static int enic_stop(struct net_device *netdev)
1657{
1658 struct enic *enic = netdev_priv(netdev);
1659 unsigned int i;
1660 int err;
1661
29046f9b 1662 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1663 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1664 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1665 }
b3d18d19
SF		 1666
1667 enic_synchronize_irqs(enic);
1668
01f2e4ea 1669 del_timer_sync(&enic->notify_timer);
a145df23 1670 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1671
383ab92f 1672 enic_dev_disable(enic);
717258ba 1673
14747cd9 1674 for (i = 0; i < enic->rq_count; i++) {
717258ba 1675 napi_disable(&enic->napi[i]);
39dc90c1 1676 local_bh_disable();
14747cd9
GV		 1677 while (!enic_poll_lock_napi(&enic->rq[i]))
1678 mdelay(1);
39dc90c1 1679 local_bh_enable();
14747cd9 1680 }
717258ba 1681
b3d18d19
SF		 1682 netif_carrier_off(netdev);
1683 netif_tx_disable(netdev);
4cfe8785
GV		 1684 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1685 for (i = 0; i < enic->wq_count; i++)
1686 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 1687
7335903c 1688 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1689 enic_dev_del_station_addr(enic);
f8bd9091 1690
01f2e4ea
SF		 1691 for (i = 0; i < enic->wq_count; i++) {
1692 err = vnic_wq_disable(&enic->wq[i]);
1693 if (err)
1694 return err;
1695 }
1696 for (i = 0; i < enic->rq_count; i++) {
1697 err = vnic_rq_disable(&enic->rq[i]);
1698 if (err)
1699 return err;
1700 }
1701
383ab92f 1702 enic_dev_notify_unset(enic);
4b75a442
SF		 1703 enic_free_intr(enic);
1704
01f2e4ea
SF		 1705 for (i = 0; i < enic->wq_count; i++)
1706 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1707 for (i = 0; i < enic->rq_count; i++)
1708 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1709 for (i = 0; i < enic->cq_count; i++)
1710 vnic_cq_clean(&enic->cq[i]);
1711 for (i = 0; i < enic->intr_count; i++)
1712 vnic_intr_clean(&enic->intr[i]);
1713
1714 return 0;
1715}
1716
1717static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1718{
1719 struct enic *enic = netdev_priv(netdev);
1720 int running = netif_running(netdev);
1721
25f0a061
SF		 1722 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1723 return -EINVAL;
1724
7335903c 1725 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 1726 return -EOPNOTSUPP;
1727
01f2e4ea
SF		 1728 if (running)
1729 enic_stop(netdev);
1730
01f2e4ea
SF		 1731 netdev->mtu = new_mtu;
1732
1733 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 1734 netdev_warn(netdev,
1735 "interface MTU (%d) set higher than port MTU (%d)\n",
1736 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 1737
1738 if (running)
1739 enic_open(netdev);
1740
1741 return 0;
1742}
1743
c97c894d
RP		 1744static void enic_change_mtu_work(struct work_struct *work)
1745{
1746 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1747 struct net_device *netdev = enic->netdev;
1748 int new_mtu = vnic_dev_mtu(enic->vdev);
1749 int err;
1750 unsigned int i;
1751
1752 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1753
1754 rtnl_lock();
1755
1756 /* Stop RQ */
1757 del_timer_sync(&enic->notify_timer);
1758
1759 for (i = 0; i < enic->rq_count; i++)
1760 napi_disable(&enic->napi[i]);
1761
1762 vnic_intr_mask(&enic->intr[0]);
1763 enic_synchronize_irqs(enic);
1764 err = vnic_rq_disable(&enic->rq[0]);
1765 if (err) {
e057590b 1766 rtnl_unlock();
c97c894d
RP		 1767 netdev_err(netdev, "Unable to disable RQ.\n");
1768 return;
1769 }
1770 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1771 vnic_cq_clean(&enic->cq[0]);
1772 vnic_intr_clean(&enic->intr[0]);
1773
1774 /* Fill RQ with new_mtu-sized buffers */
1775 netdev->mtu = new_mtu;
1776 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1777 /* Need at least one buffer on ring to get going */
1778 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1779 rtnl_unlock();
c97c894d
RP		 1780 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1781 return;
1782 }
1783
1784 /* Start RQ */
1785 vnic_rq_enable(&enic->rq[0]);
1786 napi_enable(&enic->napi[0]);
1787 vnic_intr_unmask(&enic->intr[0]);
1788 enic_notify_timer_start(enic);
1789
1790 rtnl_unlock();
1791
1792 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1793}
1794
01f2e4ea
SF		 1795#ifdef CONFIG_NET_POLL_CONTROLLER
1796static void enic_poll_controller(struct net_device *netdev)
1797{
1798 struct enic *enic = netdev_priv(netdev);
1799 struct vnic_dev *vdev = enic->vdev;
717258ba 1800 unsigned int i, intr;
01f2e4ea
SF		 1801
1802 switch (vnic_dev_get_intr_mode(vdev)) {
1803 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1804 for (i = 0; i < enic->rq_count; i++) {
1805 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 1806 enic_isr_msix(enic->msix_entry[intr].vector,
1807 &enic->napi[i]);
717258ba 1808 }
b880a954
VK		 1809
1810 for (i = 0; i < enic->wq_count; i++) {
1811 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 1812 enic_isr_msix(enic->msix_entry[intr].vector,
1813 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 1814 }
1815
01f2e4ea
SF		 1816 break;
1817 case VNIC_DEV_INTR_MODE_MSI:
1818 enic_isr_msi(enic->pdev->irq, enic);
1819 break;
1820 case VNIC_DEV_INTR_MODE_INTX:
1821 enic_isr_legacy(enic->pdev->irq, netdev);
1822 break;
1823 default:
1824 break;
1825 }
1826}
1827#endif
1828
1829static int enic_dev_wait(struct vnic_dev *vdev,
1830 int (*start)(struct vnic_dev *, int),
1831 int (*finished)(struct vnic_dev *, int *),
1832 int arg)
1833{
1834 unsigned long time;
1835 int done;
1836 int err;
1837
1838 BUG_ON(in_interrupt());
1839
1840 err = start(vdev, arg);
1841 if (err)
1842 return err;
1843
1844 /* Wait for func to complete...2 seconds max
1845 */
1846
1847 time = jiffies + (HZ * 2);
1848 do {
1849
1850 err = finished(vdev, &done);
1851 if (err)
1852 return err;
1853
1854 if (done)
1855 return 0;
1856
1857 schedule_timeout_uninterruptible(HZ / 10);
1858
1859 } while (time_after(time, jiffies));
1860
1861 return -ETIMEDOUT;
1862}
1863
1864static int enic_dev_open(struct enic *enic)
1865{
1866 int err;
1867
1868 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1869 vnic_dev_open_done, 0);
1870 if (err)
a7a79deb
VK		 1871 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1872 err);
01f2e4ea
SF		 1873
1874 return err;
1875}
1876
99ef5639 1877static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 1878{
1879 int err;
1880
99ef5639
VK		 1881 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1882 vnic_dev_hang_reset_done, 0);
01f2e4ea 1883 if (err)
a7a79deb
VK		 1884 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1885 err);
01f2e4ea
SF		 1886
1887 return err;
1888}
1889
717258ba
VK		 1890static int enic_set_rsskey(struct enic *enic)
1891{
1f4f067f 1892 dma_addr_t rss_key_buf_pa;
717258ba
VK		 1893 union vnic_rss_key *rss_key_buf_va = NULL;
1894 union vnic_rss_key rss_key = {
1895 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
1896 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101},
1897 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115},
1898 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108},
1899 };
1900 int err;
1901
1902 rss_key_buf_va = pci_alloc_consistent(enic->pdev,
1903 sizeof(union vnic_rss_key), &rss_key_buf_pa);
1904 if (!rss_key_buf_va)
1905 return -ENOMEM;
1906
1907 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));
1908
8e091340 1909 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1910 err = enic_set_rss_key(enic,
1911 rss_key_buf_pa,
1912 sizeof(union vnic_rss_key));
8e091340 1913 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1914
1915 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1916 rss_key_buf_va, rss_key_buf_pa);
1917
1918 return err;
1919}
1920
1921static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1922{
1f4f067f 1923 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 1924 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1925 unsigned int i;
1926 int err;
1927
1928 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1929 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1930 if (!rss_cpu_buf_va)
1931 return -ENOMEM;
1932
1933 for (i = 0; i < (1 << rss_hash_bits); i++)
1934 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1935
8e091340 1936 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1937 err = enic_set_rss_cpu(enic,
1938 rss_cpu_buf_pa,
1939 sizeof(union vnic_rss_cpu));
8e091340 1940 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1941
1942 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1943 rss_cpu_buf_va, rss_cpu_buf_pa);
1944
1945 return err;
1946}
1947
1948static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1949 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1950{
68f71708
SF		 1951 const u8 tso_ipid_split_en = 0;
1952 const u8 ig_vlan_strip_en = 1;
383ab92f 1953 int err;
68f71708 1954
717258ba
VK		 1955 /* Enable VLAN tag stripping.
1956 */
68f71708 1957
8e091340 1958 spin_lock_bh(&enic->devcmd_lock);
383ab92f 1959 err = enic_set_nic_cfg(enic,
68f71708
SF		 1960 rss_default_cpu, rss_hash_type,
1961 rss_hash_bits, rss_base_cpu,
1962 rss_enable, tso_ipid_split_en,
1963 ig_vlan_strip_en);
8e091340 1964 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 1965
1966 return err;
1967}
1968
717258ba
VK		 1969static int enic_set_rss_nic_cfg(struct enic *enic)
1970{
1971 struct device *dev = enic_get_dev(enic);
1972 const u8 rss_default_cpu = 0;
1973 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
1974 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
1975 NIC_CFG_RSS_HASH_TYPE_IPV6 |
1976 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
1977 const u8 rss_hash_bits = 7;
1978 const u8 rss_base_cpu = 0;
1979 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
1980
1981 if (rss_enable) {
1982 if (!enic_set_rsskey(enic)) {
1983 if (enic_set_rsscpu(enic, rss_hash_bits)) {
1984 rss_enable = 0;
1985 dev_warn(dev, "RSS disabled, "
1986 "Failed to set RSS cpu indirection table.");
1987 }
1988 } else {
1989 rss_enable = 0;
1990 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
1991 }
1992 }
1993
1994 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
1995 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 1996}
1997
01f2e4ea
SF		 1998static void enic_reset(struct work_struct *work)
1999{
2000 struct enic *enic = container_of(work, struct enic, reset);
2001
2002 if (!netif_running(enic->netdev))
2003 return;
2004
2005 rtnl_lock();
2006
0b038566 2007 spin_lock(&enic->enic_api_lock);
383ab92f 2008 enic_dev_hang_notify(enic);
01f2e4ea 2009 enic_stop(enic->netdev);
99ef5639 2010 enic_dev_hang_reset(enic);
e0afe53f 2011 enic_reset_addr_lists(enic);
01f2e4ea 2012 enic_init_vnic_resources(enic);
717258ba 2013 enic_set_rss_nic_cfg(enic);
f8cac14a 2014 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2015 enic_open(enic->netdev);
0b038566 2016 spin_unlock(&enic->enic_api_lock);
d765bb41 2017 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2018
2019 rtnl_unlock();
2020}
2021
2022static int enic_set_intr_mode(struct enic *enic)
2023{
717258ba 2024 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2025 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2026 unsigned int i;
2027
2028 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2029 * on system capabilities.
01f2e4ea
SF		 2030 *
2031 * Try MSI-X first
2032 *
2033 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2034 * (the second to last INTR is used for WQ/RQ errors)
2035 * (the last INTR is used for notifications)
2036 */
2037
2038 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2039 for (i = 0; i < n + m + 2; i++)
2040 enic->msix_entry[i].entry = i;
2041
717258ba
VK		 2042 /* Use multiple RQs if RSS is enabled
2043 */
2044
2045 if (ENIC_SETTING(enic, RSS) &&
2046 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2047 enic->rq_count >= n &&
2048 enic->wq_count >= m &&
2049 enic->cq_count >= n + m &&
717258ba 2050 enic->intr_count >= n + m + 2) {
01f2e4ea 2051
abbb6a37
AG		 2052 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2053 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2054
717258ba
VK		 2055 enic->rq_count = n;
2056 enic->wq_count = m;
2057 enic->cq_count = n + m;
2058 enic->intr_count = n + m + 2;
01f2e4ea 2059
717258ba
VK		 2060 vnic_dev_set_intr_mode(enic->vdev,
2061 VNIC_DEV_INTR_MODE_MSIX);
2062
2063 return 0;
2064 }
2065 }
2066
2067 if (enic->config.intr_mode < 1 &&
2068 enic->rq_count >= 1 &&
2069 enic->wq_count >= m &&
2070 enic->cq_count >= 1 + m &&
2071 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2072 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2073 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2074
2075 enic->rq_count = 1;
2076 enic->wq_count = m;
2077 enic->cq_count = 1 + m;
2078 enic->intr_count = 1 + m + 2;
2079
2080 vnic_dev_set_intr_mode(enic->vdev,
2081 VNIC_DEV_INTR_MODE_MSIX);
2082
2083 return 0;
2084 }
01f2e4ea
SF		 2085 }
2086
2087 /* Next try MSI
2088 *
2089 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2090 */
2091
2092 if (enic->config.intr_mode < 2 &&
2093 enic->rq_count >= 1 &&
2094 enic->wq_count >= 1 &&
2095 enic->cq_count >= 2 &&
2096 enic->intr_count >= 1 &&
2097 !pci_enable_msi(enic->pdev)) {
2098
2099 enic->rq_count = 1;
2100 enic->wq_count = 1;
2101 enic->cq_count = 2;
2102 enic->intr_count = 1;
2103
2104 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2105
2106 return 0;
2107 }
2108
2109 /* Next try INTx
2110 *
2111 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2112 * (the first INTR is used for WQ/RQ)
2113 * (the second INTR is used for WQ/RQ errors)
2114 * (the last INTR is used for notifications)
2115 */
2116
2117 if (enic->config.intr_mode < 3 &&
2118 enic->rq_count >= 1 &&
2119 enic->wq_count >= 1 &&
2120 enic->cq_count >= 2 &&
2121 enic->intr_count >= 3) {
2122
2123 enic->rq_count = 1;
2124 enic->wq_count = 1;
2125 enic->cq_count = 2;
2126 enic->intr_count = 3;
2127
2128 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2129
2130 return 0;
2131 }
2132
2133 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2134
2135 return -EINVAL;
2136}
2137
2138static void enic_clear_intr_mode(struct enic *enic)
2139{
2140 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2141 case VNIC_DEV_INTR_MODE_MSIX:
2142 pci_disable_msix(enic->pdev);
2143 break;
2144 case VNIC_DEV_INTR_MODE_MSI:
2145 pci_disable_msi(enic->pdev);
2146 break;
2147 default:
2148 break;
2149 }
2150
2151 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2152}
2153
f8bd9091
SF		 2154static const struct net_device_ops enic_netdev_dynamic_ops = {
2155 .ndo_open = enic_open,
2156 .ndo_stop = enic_stop,
2157 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2158 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2159 .ndo_validate_addr = eth_validate_addr,
319d7e84 2160 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2161 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2162 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2163 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2164 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2165 .ndo_tx_timeout = enic_tx_timeout,
2166 .ndo_set_vf_port = enic_set_vf_port,
2167 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2168 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2169#ifdef CONFIG_NET_POLL_CONTROLLER
2170 .ndo_poll_controller = enic_poll_controller,
2171#endif
a145df23
GV		 2172#ifdef CONFIG_RFS_ACCEL
2173 .ndo_rx_flow_steer = enic_rx_flow_steer,
2174#endif
14747cd9
GV		 2175#ifdef CONFIG_NET_RX_BUSY_POLL
2176 .ndo_busy_poll = enic_busy_poll,
2177#endif
f8bd9091
SF		 2178};
2179
afe29f7a
SH		 2180static const struct net_device_ops enic_netdev_ops = {
2181 .ndo_open = enic_open,
2182 .ndo_stop = enic_stop,
00829823 2183 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2184 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2185 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2186 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2187 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2188 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2189 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2190 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2191 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2192 .ndo_set_vf_port = enic_set_vf_port,
2193 .ndo_get_vf_port = enic_get_vf_port,
2194 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2195#ifdef CONFIG_NET_POLL_CONTROLLER
2196 .ndo_poll_controller = enic_poll_controller,
2197#endif
a145df23
GV		 2198#ifdef CONFIG_RFS_ACCEL
2199 .ndo_rx_flow_steer = enic_rx_flow_steer,
2200#endif
14747cd9
GV		 2201#ifdef CONFIG_NET_RX_BUSY_POLL
2202 .ndo_busy_poll = enic_busy_poll,
2203#endif
afe29f7a
SH		 2204};
2205
2fdba388 2206static void enic_dev_deinit(struct enic *enic)
6fdfa970 2207{
717258ba
VK		 2208 unsigned int i;
2209
14747cd9
GV		 2210 for (i = 0; i < enic->rq_count; i++) {
2211 napi_hash_del(&enic->napi[i]);
717258ba 2212 netif_napi_del(&enic->napi[i]);
14747cd9 2213 }
4cfe8785
GV		 2214 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2215 for (i = 0; i < enic->wq_count; i++)
2216 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2217
6fdfa970
SF		 2218 enic_free_vnic_resources(enic);
2219 enic_clear_intr_mode(enic);
2220}
2221
2fdba388 2222static int enic_dev_init(struct enic *enic)
6fdfa970 2223{
a7a79deb 2224 struct device *dev = enic_get_dev(enic);
6fdfa970 2225 struct net_device *netdev = enic->netdev;
717258ba 2226 unsigned int i;
6fdfa970
SF		 2227 int err;
2228
ea7ea65a
VK		 2229 /* Get interrupt coalesce timer info */
2230 err = enic_dev_intr_coal_timer_info(enic);
2231 if (err) {
2232 dev_warn(dev, "Using default conversion factor for "
2233 "interrupt coalesce timer\n");
2234 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2235 }
2236
6fdfa970
SF		 2237 /* Get vNIC configuration
2238 */
2239
2240 err = enic_get_vnic_config(enic);
2241 if (err) {
a7a79deb 2242 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2243 return err;
2244 }
2245
2246 /* Get available resource counts
2247 */
2248
2249 enic_get_res_counts(enic);
2250
2251 /* Set interrupt mode based on resource counts and system
2252 * capabilities
2253 */
2254
2255 err = enic_set_intr_mode(enic);
2256 if (err) {
a7a79deb
VK		 2257 dev_err(dev, "Failed to set intr mode based on resource "
2258 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2259 return err;
2260 }
2261
2262 /* Allocate and configure vNIC resources
2263 */
2264
2265 err = enic_alloc_vnic_resources(enic);
2266 if (err) {
a7a79deb 2267 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2268 goto err_out_free_vnic_resources;
2269 }
2270
2271 enic_init_vnic_resources(enic);
2272
717258ba 2273 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2274 if (err) {
a7a79deb 2275 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2276 goto err_out_free_vnic_resources;
2277 }
2278
2279 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2280 default:
717258ba 2281 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
14747cd9 2282 napi_hash_add(&enic->napi[0]);
6fdfa970
SF		 2283 break;
2284 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2285 for (i = 0; i < enic->rq_count; i++) {
717258ba 2286 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2287 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9
GV		 2288 napi_hash_add(&enic->napi[i]);
2289 }
4cfe8785
GV		 2290 for (i = 0; i < enic->wq_count; i++)
2291 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2292 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2293 break;
2294 }
2295
2296 return 0;
2297
2298err_out_free_vnic_resources:
2299 enic_clear_intr_mode(enic);
2300 enic_free_vnic_resources(enic);
2301
2302 return err;
2303}
2304
27e6c7d3
SF		 2305static void enic_iounmap(struct enic *enic)
2306{
2307 unsigned int i;
2308
2309 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2310 if (enic->bar[i].vaddr)
2311 iounmap(enic->bar[i].vaddr);
2312}
2313
1dd06ae8 2314static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2315{
a7a79deb 2316 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2317 struct net_device *netdev;
2318 struct enic *enic;
2319 int using_dac = 0;
2320 unsigned int i;
2321 int err;
8749b427
RP		 2322#ifdef CONFIG_PCI_IOV
2323 int pos = 0;
2324#endif
b67f231d 2325 int num_pps = 1;
01f2e4ea 2326
01f2e4ea
SF		 2327 /* Allocate net device structure and initialize. Private
2328 * instance data is initialized to zero.
2329 */
2330
822473b6 2331 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2332 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2333 if (!netdev)
01f2e4ea 2334 return -ENOMEM;
01f2e4ea 2335
01f2e4ea
SF		 2336 pci_set_drvdata(pdev, netdev);
2337
2338 SET_NETDEV_DEV(netdev, &pdev->dev);
2339
2340 enic = netdev_priv(netdev);
2341 enic->netdev = netdev;
2342 enic->pdev = pdev;
2343
2344 /* Setup PCI resources
2345 */
2346
29046f9b 2347 err = pci_enable_device_mem(pdev);
01f2e4ea 2348 if (err) {
a7a79deb 2349 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2350 goto err_out_free_netdev;
2351 }
2352
2353 err = pci_request_regions(pdev, DRV_NAME);
2354 if (err) {
a7a79deb 2355 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2356 goto err_out_disable_device;
2357 }
2358
2359 pci_set_master(pdev);
2360
2361 /* Query PCI controller on system for DMA addressing
624dbf55 2362 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2363 * fail to 32-bit.
2364 */
2365
624dbf55 2366 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2367 if (err) {
284901a9 2368 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2369 if (err) {
a7a79deb 2370 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2371 goto err_out_release_regions;
2372 }
284901a9 2373 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2374 if (err) {
a7a79deb
VK		 2375 dev_err(dev, "Unable to obtain %u-bit DMA "
2376 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2377 goto err_out_release_regions;
2378 }
2379 } else {
624dbf55 2380 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2381 if (err) {
a7a79deb 2382 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2383 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2384 goto err_out_release_regions;
2385 }
2386 using_dac = 1;
2387 }
2388
27e6c7d3 2389 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2390 */
2391
27e6c7d3
SF		 2392 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2393 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2394 continue;
2395 enic->bar[i].len = pci_resource_len(pdev, i);
2396 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2397 if (!enic->bar[i].vaddr) {
a7a79deb 2398 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2399 err = -ENODEV;
2400 goto err_out_iounmap;
2401 }
2402 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2403 }
2404
2405 /* Register vNIC device
2406 */
2407
27e6c7d3
SF		 2408 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2409 ARRAY_SIZE(enic->bar));
01f2e4ea 2410 if (!enic->vdev) {
a7a79deb 2411 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2412 err = -ENODEV;
2413 goto err_out_iounmap;
2414 }
2415
8749b427
RP		 2416#ifdef CONFIG_PCI_IOV
2417 /* Get number of subvnics */
2418 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2419 if (pos) {
2420 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2421 &enic->num_vfs);
8749b427
RP		 2422 if (enic->num_vfs) {
2423 err = pci_enable_sriov(pdev, enic->num_vfs);
2424 if (err) {
2425 dev_err(dev, "SRIOV enable failed, aborting."
2426 " pci_enable_sriov() returned %d\n",
2427 err);
2428 goto err_out_vnic_unregister;
2429 }
2430 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2431 num_pps = enic->num_vfs;
8749b427
RP		 2432 }
2433 }
8749b427 2434#endif
ca2b721d 2435
3f192795 2436 /* Allocate structure for port profiles */
a1de2219 2437 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2438 if (!enic->pp) {
3f192795 2439 err = -ENOMEM;
ca2b721d 2440 goto err_out_disable_sriov_pp;
3f192795
RP		 2441 }
2442
01f2e4ea
SF		 2443 /* Issue device open to get device in known state
2444 */
2445
2446 err = enic_dev_open(enic);
2447 if (err) {
a7a79deb 2448 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2449 goto err_out_disable_sriov;
01f2e4ea
SF		 2450 }
2451
69161425
VK		 2452 /* Setup devcmd lock
2453 */
2454
2455 spin_lock_init(&enic->devcmd_lock);
0b038566 2456 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2457
2458 /*
2459 * Set ingress vlan rewrite mode before vnic initialization
2460 */
2461
2462 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2463 if (err) {
2464 dev_err(dev,
2465 "Failed to set ingress vlan rewrite mode, aborting.\n");
2466 goto err_out_dev_close;
2467 }
2468
01f2e4ea
SF		 2469 /* Issue device init to initialize the vnic-to-switch link.
2470 * We'll start with carrier off and wait for link UP
2471 * notification later to turn on carrier. We don't need
2472 * to wait here for the vnic-to-switch link initialization
2473 * to complete; link UP notification is the indication that
2474 * the process is complete.
2475 */
2476
2477 netif_carrier_off(netdev);
2478
a7a79deb
VK		 2479 /* Do not call dev_init for a dynamic vnic.
2480 * For a dynamic vnic, init_prov_info will be
2481 * called later by an upper layer.
2482 */
2483
2b68c181 2484 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2485 err = vnic_dev_init(enic->vdev, 0);
2486 if (err) {
a7a79deb 2487 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2488 goto err_out_dev_close;
2489 }
01f2e4ea
SF		 2490 }
2491
6fdfa970 2492 err = enic_dev_init(enic);
01f2e4ea 2493 if (err) {
a7a79deb 2494 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2495 goto err_out_dev_close;
2496 }
2497
822473b6 2498 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2499 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2500
383ab92f 2501 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2502 */
2503
2504 init_timer(&enic->notify_timer);
2505 enic->notify_timer.function = enic_notify_timer;
2506 enic->notify_timer.data = (unsigned long)enic;
2507
7c2ce6e6 2508 enic_set_rx_coal_setting(enic);
01f2e4ea 2509 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2510 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2511
2512 for (i = 0; i < enic->wq_count; i++)
2513 spin_lock_init(&enic->wq_lock[i]);
2514
01f2e4ea
SF		 2515 /* Register net device
2516 */
2517
2518 enic->port_mtu = enic->config.mtu;
2519 (void)enic_change_mtu(netdev, enic->port_mtu);
2520
2521 err = enic_set_mac_addr(netdev, enic->mac_addr);
2522 if (err) {
a7a79deb 2523 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2524 goto err_out_dev_deinit;
01f2e4ea
SF		 2525 }
2526
7c844599 2527 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2528 /* rx coalesce time already got initialized. This gets used
2529 * if adaptive coal is turned off
2530 */
7c844599
SF		 2531 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2532
7335903c 2533 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2534 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2535 else
2536 netdev->netdev_ops = &enic_netdev_ops;
2537
01f2e4ea 2538 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2539 enic_set_ethtool_ops(netdev);
01f2e4ea 2540
f646968f 2541 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2542 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2543 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2544 enic->loop_enable = 1;
2545 enic->loop_tag = enic->config.loop_tag;
2546 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2547 }
01f2e4ea 2548 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2549 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2550 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2551 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2552 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2553 if (ENIC_SETTING(enic, RSS))
2554 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2555 if (ENIC_SETTING(enic, RXCSUM))
2556 netdev->hw_features |= NETIF_F_RXCSUM;
2557
2558 netdev->features |= netdev->hw_features;
2559
a145df23
GV		 2560#ifdef CONFIG_RFS_ACCEL
2561 netdev->hw_features |= NETIF_F_NTUPLE;
2562#endif
2563
01f2e4ea
SF		 2564 if (using_dac)
2565 netdev->features |= NETIF_F_HIGHDMA;
2566
01789349
JP		 2567 netdev->priv_flags |= IFF_UNICAST_FLT;
2568
01f2e4ea
SF		 2569 err = register_netdev(netdev);
2570 if (err) {
a7a79deb 2571 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2572 goto err_out_dev_deinit;
01f2e4ea 2573 }
a03bb56e 2574 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2575
2576 return 0;
2577
6fdfa970
SF		 2578err_out_dev_deinit:
2579 enic_dev_deinit(enic);
01f2e4ea
SF		 2580err_out_dev_close:
2581 vnic_dev_close(enic->vdev);
8749b427 2582err_out_disable_sriov:
ca2b721d
RP		 2583 kfree(enic->pp);
2584err_out_disable_sriov_pp:
8749b427
RP		 2585#ifdef CONFIG_PCI_IOV
2586 if (enic_sriov_enabled(enic)) {
2587 pci_disable_sriov(pdev);
2588 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2589 }
01f2e4ea 2590err_out_vnic_unregister:
8749b427 2591#endif
35d87e33 2592 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2593err_out_iounmap:
2594 enic_iounmap(enic);
2595err_out_release_regions:
2596 pci_release_regions(pdev);
2597err_out_disable_device:
2598 pci_disable_device(pdev);
2599err_out_free_netdev:
01f2e4ea
SF		 2600 free_netdev(netdev);
2601
2602 return err;
2603}
2604
854de92f 2605static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2606{
2607 struct net_device *netdev = pci_get_drvdata(pdev);
2608
2609 if (netdev) {
2610 struct enic *enic = netdev_priv(netdev);
2611
23f333a2 2612 cancel_work_sync(&enic->reset);
c97c894d 2613 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2614 unregister_netdev(netdev);
6fdfa970 2615 enic_dev_deinit(enic);
01f2e4ea 2616 vnic_dev_close(enic->vdev);
8749b427
RP		 2617#ifdef CONFIG_PCI_IOV
2618 if (enic_sriov_enabled(enic)) {
2619 pci_disable_sriov(pdev);
2620 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2621 }
2622#endif
3f192795 2623 kfree(enic->pp);
01f2e4ea
SF		 2624 vnic_dev_unregister(enic->vdev);
2625 enic_iounmap(enic);
2626 pci_release_regions(pdev);
2627 pci_disable_device(pdev);
01f2e4ea
SF		 2628 free_netdev(netdev);
2629 }
2630}
2631
2632static struct pci_driver enic_driver = {
2633 .name = DRV_NAME,
2634 .id_table = enic_id_table,
2635 .probe = enic_probe,
854de92f 2636 .remove = enic_remove,
01f2e4ea
SF		 2637};
2638
2639static int __init enic_init_module(void)
2640{
a7a79deb 2641 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 2642
2643 return pci_register_driver(&enic_driver);
2644}
2645
2646static void __exit enic_cleanup_module(void)
2647{
2648 pci_unregister_driver(&enic_driver);
2649}
2650
2651module_init(enic_init_module);
2652module_exit(enic_cleanup_module);
Linux kernel - Deliverables
This page took 0.761921 seconds and 5 git commands to generate.